From f36c650bf3beee4295e0432e00ee1d017b636326 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Thu, 17 Dec 2020 17:25:17 +0500 Subject: [PATCH] imp-ID to 1 --- quasar_wrapper.anno.json | 2 +- quasar_wrapper.fir | 18164 ++++++++++------ quasar_wrapper.v | 10436 +++++---- src/main/scala/dec/dec.scala | 6 - src/main/scala/dec/dec_tlu_ctl.scala | 822 +- src/main/scala/exu/exu.scala | 68 +- src/main/scala/include/bundle.scala | 28 +- src/main/scala/lib/param.scala | 4 +- src/main/scala/lsu/lsu_bus_buffer.scala | 78 +- src/main/scala/lsu/lsu_ecc.scala | 2 - src/main/scala/lsu/lsu_stbuf.scala | 3 - src/main/scala/lsu/lsu_trigger.scala | 1 - src/main/scala/quasar_wrapper.scala | 6 +- target/scala-2.12/classes/QUASAR_Wrp$.class | Bin 3859 -> 3859 bytes .../classes/QUASAR_Wrp$delayedInit$body.class | Bin 729 -> 729 bytes target/scala-2.12/classes/dec/CSR_IO.class | Bin 84352 -> 84352 bytes target/scala-2.12/classes/dec/CSRs.class | Bin 23325 -> 23325 bytes target/scala-2.12/classes/dec/csr_tlu.class | Bin 216661 -> 216661 bytes target/scala-2.12/classes/dec/dec.class | Bin 111967 -> 111967 bytes .../classes/dec/dec_decode_csr_read.class | Bin 17583 -> 17583 bytes .../classes/dec/dec_decode_csr_read_IO.class | Bin 2043 -> 2043 bytes target/scala-2.12/classes/dec/dec_main$.class | Bin 3844 -> 3844 bytes .../dec/dec_main$delayedInit$body.class | Bin 730 -> 730 bytes .../classes/dec/dec_timer_ctl.class | Bin 62232 -> 62232 bytes .../classes/dec/dec_timer_ctl_IO.class | Bin 5563 -> 5563 bytes .../scala-2.12/classes/dec/dec_tlu_ctl.class | Bin 187386 -> 187387 bytes target/scala-2.12/classes/exu/exu.class | Bin 201592 -> 201592 bytes .../classes/include/ahb_channel.class | Bin 1327 -> 1327 bytes .../scala-2.12/classes/include/ahb_in.class | Bin 2081 -> 2081 bytes .../scala-2.12/classes/include/ahb_out.class | Bin 2944 -> 2944 bytes .../classes/include/ahb_out_dma.class | Bin 2957 -> 2957 bytes .../scala-2.12/classes/include/aln_dec.class | Bin 2031 -> 2031 bytes .../scala-2.12/classes/include/aln_ib.class | Bin 47300 -> 47300 bytes .../classes/include/alu_pkt_t.class | Bin 4169 -> 4169 bytes .../classes/include/axi_channels$.class | Bin 501 -> 501 bytes .../classes/include/axi_channels.class | Bin 46532 -> 46532 bytes .../scala-2.12/classes/include/br_pkt_t.class | Bin 2549 -> 2549 bytes .../classes/include/br_tlu_pkt_t.class | Bin 2108 -> 2108 bytes .../classes/include/cache_debug_pkt_t.class | Bin 2066 -> 2066 bytes .../classes/include/ccm_ext_in_pkt_t.class | Bin 2649 -> 2649 bytes .../classes/include/class_pkt_t.class | Bin 1751 -> 1751 bytes .../classes/include/dccm_ext_in_pkt_t.class | Bin 2652 -> 2652 bytes .../classes/include/dctl_busbuff.class | Bin 46540 -> 46540 bytes .../scala-2.12/classes/include/dec_aln.class | Bin 44956 -> 44956 bytes .../scala-2.12/classes/include/dec_alu.class | Bin 2443 -> 2443 bytes .../scala-2.12/classes/include/dec_bp.class | Bin 2263 -> 2263 bytes .../scala-2.12/classes/include/dec_div.class | Bin 2240 -> 2240 bytes .../scala-2.12/classes/include/dec_exu.class | Bin 45440 -> 45440 bytes .../scala-2.12/classes/include/dec_ifc.class | Bin 2274 -> 2274 bytes .../classes/include/dec_mem_ctrl.class | Bin 48157 -> 48157 bytes .../classes/include/dec_pkt_t.class | Bin 8199 -> 8199 bytes .../classes/include/dec_tlu_csr_pkt.class | Bin 13320 -> 13320 bytes .../classes/include/decode_exu.class | Bin 49558 -> 49558 bytes .../classes/include/dest_pkt_t.class | Bin 2551 -> 2551 bytes .../classes/include/div_pkt_t.class | Bin 1605 -> 1605 bytes .../classes/include/dma_dccm_ctl.class | Bin 2834 -> 2834 bytes .../scala-2.12/classes/include/dma_ifc.class | Bin 1369 -> 1369 bytes .../classes/include/dma_lsc_ctl.class | Bin 2541 -> 2541 bytes .../classes/include/dma_mem_ctl.class | Bin 2728 -> 2728 bytes .../scala-2.12/classes/include/exu_bp.class | Bin 46497 -> 46497 bytes .../scala-2.12/classes/include/gpr_exu.class | Bin 1814 -> 1814 bytes .../scala-2.12/classes/include/ib_exu.class | Bin 1836 -> 1836 bytes .../include/ic_data_ext_in_pkt_t.class | Bin 2662 -> 2662 bytes .../scala-2.12/classes/include/ic_mem.class | Bin 48825 -> 48825 bytes .../classes/include/ic_tag_ext_in_pkt_t.class | Bin 2659 -> 2659 bytes .../scala-2.12/classes/include/iccm_mem.class | Bin 46323 -> 46323 bytes .../scala-2.12/classes/include/ifu_dec.class | Bin 1860 -> 1860 bytes .../scala-2.12/classes/include/ifu_dma.class | Bin 1378 -> 1378 bytes .../classes/include/inst_pkt_t$.class | Bin 3015 -> 3015 bytes .../classes/include/load_cam_pkt_t.class | Bin 1750 -> 1750 bytes .../scala-2.12/classes/include/lsu_dec.class | Bin 1415 -> 1415 bytes .../scala-2.12/classes/include/lsu_dma.class | Bin 2565 -> 2565 bytes .../classes/include/lsu_error_pkt_t.class | Bin 2148 -> 2148 bytes .../scala-2.12/classes/include/lsu_exu.class | Bin 1821 -> 1821 bytes .../scala-2.12/classes/include/lsu_pic.class | Bin 2921 -> 2921 bytes .../classes/include/lsu_pkt_t.class | Bin 2874 -> 2874 bytes .../scala-2.12/classes/include/lsu_tlu.class | Bin 1608 -> 1608 bytes .../classes/include/mul_pkt_t.class | Bin 4102 -> 4102 bytes .../classes/include/predict_pkt_t.class | Bin 3328 -> 3328 bytes .../classes/include/read_addr$.class | Bin 495 -> 495 bytes .../classes/include/read_addr.class | Bin 46524 -> 46524 bytes .../classes/include/read_data$.class | Bin 495 -> 495 bytes .../classes/include/read_data.class | Bin 45620 -> 45620 bytes .../classes/include/reg_pkt_t.class | Bin 1738 -> 1738 bytes .../classes/include/rets_pkt_t.class | Bin 1787 -> 1787 bytes .../classes/include/tlu_busbuff.class | Bin 3899 -> 3899 bytes .../scala-2.12/classes/include/tlu_exu.class | Bin 47514 -> 47514 bytes .../classes/include/trace_pkt_t.class | Bin 2835 -> 2835 bytes .../classes/include/trap_pkt_t.class | Bin 2987 -> 2987 bytes .../classes/include/trigger_pkt_t.class | Bin 2395 -> 2395 bytes .../classes/include/write_addr$.class | Bin 497 -> 497 bytes .../classes/include/write_addr.class | Bin 46530 -> 46530 bytes .../classes/include/write_data.class | Bin 44959 -> 44959 bytes .../classes/include/write_resp.class | Bin 44885 -> 44885 bytes target/scala-2.12/classes/lib/param.class | Bin 23339 -> 23339 bytes .../classes/lsu/lsu_bus_buffer.class | Bin 549111 -> 549110 bytes target/scala-2.12/classes/lsu/lsu_ecc.class | Bin 101395 -> 101393 bytes target/scala-2.12/classes/lsu/lsu_stbuf.class | Bin 194201 -> 194201 bytes .../scala-2.12/classes/quasar_wrapper.class | Bin 86835 -> 86838 bytes 99 files changed, 18528 insertions(+), 11092 deletions(-) diff --git a/quasar_wrapper.anno.json b/quasar_wrapper.anno.json index bd0b063d..db6f563f 100644 --- a/quasar_wrapper.anno.json +++ b/quasar_wrapper.anno.json @@ -982,7 +982,7 @@ }, { "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~quasar_wrapper|csr_tlu>_T_755" + "target":"~quasar_wrapper|csr_tlu>_T_745" }, { "class":"firrtl.transforms.BlackBoxResourceAnno", diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 86f0fd80..6d160058 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -71689,32 +71689,32 @@ circuit quasar_wrapper : mitcnt1 <= UInt<1>("h00") wire mitcnt0 : UInt<32> mitcnt0 <= UInt<1>("h00") - node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2673:36] - node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2674:36] - io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2676:31] - io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2677:31] - node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2684:72] - node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2684:49] - node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2686:37] - node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2686:56] - node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2686:85] - node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2686:76] - node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2686:53] - node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2686:112] - node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2686:147] - node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2686:138] - node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2686:109] - node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2686:173] - node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2686:171] - node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2687:35] - node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2687:35] - node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2688:44] - node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2688:74] - node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2688:60] - node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2688:29] - node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2689:59] - node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2689:76] - node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2689:93] + node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2655:36] + node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2656:36] + io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2658:31] + io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2659:31] + node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2666:72] + node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2666:49] + node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2668:37] + node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2668:56] + node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2668:85] + node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2668:76] + node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2668:53] + node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2668:112] + node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2668:147] + node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2668:138] + node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2668:109] + node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2668:173] + node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2668:171] + node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2669:35] + node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2669:35] + node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2670:44] + node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2670:74] + node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2670:60] + node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2670:29] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2671:59] + node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2671:76] + node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2671:93] inst rvclkhdr of rvclkhdr_712 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -71723,34 +71723,34 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_18 <= mitcnt0_ns @[lib.scala 374:16] - mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2689:25] - node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2696:72] - node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2696:49] - node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2698:37] - node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2698:56] - node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2698:85] - node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2698:76] - node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2698:53] - node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2698:112] - node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2698:147] - node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2698:138] - node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2698:109] - node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2698:173] - node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2698:171] + mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2671:25] + node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2678:72] + node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2678:49] + node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2680:37] + node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2680:56] + node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2680:85] + node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2680:76] + node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2680:53] + node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2680:112] + node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2680:147] + node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2680:138] + node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2680:109] + node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2680:173] + node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2680:171] node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2701:68] - node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2701:60] - node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2701:72] + node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2683:68] + node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2683:60] + node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2683:72] node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58] - node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2701:35] - node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2701:35] - node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2702:45] - node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2702:75] - node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2702:61] - node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2702:30] - node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2703:60] - node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2703:77] - node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2703:94] + node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2683:35] + node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2683:35] + node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2684:45] + node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2684:75] + node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2684:61] + node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2684:30] + node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2685:60] + node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2685:77] + node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2685:94] inst rvclkhdr_1 of rvclkhdr_713 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -71759,11 +71759,11 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_42 <= mitcnt1_ns @[lib.scala 374:16] - mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2703:25] - node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2710:70] - node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2710:47] - node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2711:38] - node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2711:71] + mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2685:25] + node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2692:70] + node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2692:47] + node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2693:38] + node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2693:71] inst rvclkhdr_2 of rvclkhdr_714 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -71772,12 +71772,12 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mitb0_b <= _T_44 @[lib.scala 374:16] - node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2712:22] - mitb0 <= _T_46 @[dec_tlu_ctl.scala 2712:19] - node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2719:69] - node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2719:47] - node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2720:29] - node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2720:62] + node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2694:22] + mitb0 <= _T_46 @[dec_tlu_ctl.scala 2694:19] + node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2701:69] + node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2701:47] + node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2702:29] + node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2702:62] inst rvclkhdr_3 of rvclkhdr_715 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -71786,55 +71786,55 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mitb1_b <= _T_48 @[lib.scala 374:16] - node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2721:18] - mitb1 <= _T_50 @[dec_tlu_ctl.scala 2721:15] - node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2732:72] - node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2732:49] - node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2733:45] - node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2733:72] - node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2733:86] - node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2733:31] - node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2735:41] - node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2735:30] - reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2736:60] - mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2736:60] - node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2737:78] - reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2737:67] - _T_57 <= _T_56 @[dec_tlu_ctl.scala 2737:67] - node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2737:90] + node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2703:18] + mitb1 <= _T_50 @[dec_tlu_ctl.scala 2703:15] + node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2714:72] + node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2714:49] + node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2715:45] + node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2715:72] + node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2715:86] + node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2715:31] + node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2717:41] + node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2717:30] + reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2718:60] + mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2718:60] + node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2719:78] + reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2719:67] + _T_57 <= _T_56 @[dec_tlu_ctl.scala 2719:67] + node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2719:90] node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58] - mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2737:31] - node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2747:71] - node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2747:49] - node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2748:45] - node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2748:71] - node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2748:85] - node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2748:31] - node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2749:40] - node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2749:29] - reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2750:55] - mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2750:55] - node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2751:63] - reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2751:52] - _T_66 <= _T_65 @[dec_tlu_ctl.scala 2751:52] - node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2751:75] + mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2719:31] + node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2729:71] + node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2729:49] + node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2730:45] + node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2730:71] + node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2730:85] + node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2730:31] + node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2731:40] + node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2731:29] + reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2732:55] + mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2732:55] + node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2733:63] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2733:52] + _T_66 <= _T_65 @[dec_tlu_ctl.scala 2733:52] + node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2733:75] node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58] - mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2751:16] - node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2753:51] - node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2753:68] - node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2753:83] - node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2753:98] - node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2753:115] - io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2753:33] - node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2755:25] - node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2755:44] - node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2756:32] - node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2757:30] - node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2758:30] - node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2759:32] + mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2733:16] + node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2735:51] + node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2735:68] + node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2735:83] + node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2735:98] + node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2735:115] + io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2735:33] + node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2737:25] + node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2737:44] + node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2738:32] + node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2739:30] + node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2740:30] + node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2741:32] node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58] - node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2760:32] + node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2742:32] node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58] node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72] @@ -71850,7 +71850,7 @@ circuit quasar_wrapper : node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72] wire _T_96 : UInt<32> @[Mux.scala 27:72] _T_96 <= _T_95 @[Mux.scala 27:72] - io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2754:33] + io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2736:33] extmodule gated_latch_716 : output Q : Clock @@ -72833,8 +72833,8 @@ circuit quasar_wrapper : perfcnt_halted <= UInt<1>("h00") wire mhpmc3_incr : UInt<64> mhpmc3_incr <= UInt<1>("h00") - wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1393:41] - wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1394:65] + wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1376:41] + wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1377:65] wire wr_meicpct_r : UInt<1> wr_meicpct_r <= UInt<1>("h00") wire force_halt_ctr_f : UInt<32> @@ -72909,48 +72909,48 @@ circuit quasar_wrapper : mpmc <= UInt<1>("h00") wire dicad1 : UInt<32> dicad1 <= UInt<1>("h00") - node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1449:45] - node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1449:43] - node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1449:68] - node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1449:66] - io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1449:23] - node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1450:64] - node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1450:71] - node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1450:42] - node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1453:28] - node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1453:39] - node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1456:5] - node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1456:19] - node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1456:44] - node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1456:68] - node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1456:68] + node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1431:45] + node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1431:43] + node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1431:68] + node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1431:66] + io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1431:23] + node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1432:64] + node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1432:71] + node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1432:42] + node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1435:28] + node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1435:39] + node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1438:5] + node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1438:19] + node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1438:44] + node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1438:68] + node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1438:68] node _T_12 = cat(_T_11, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1457:18] - node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1457:43] - node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1457:76] + node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1439:18] + node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1439:43] + node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1439:76] node _T_16 = cat(_T_15, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1458:17] - node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1458:15] - node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1458:41] - node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1458:70] + node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1440:17] + node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1440:15] + node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1440:41] + node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1440:70] node _T_21 = cat(UInt<1>("h01"), _T_20) @[Cat.scala 29:58] - node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1459:26] - node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1459:50] + node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1441:26] + node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1441:50] node _T_24 = cat(_T_23, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1460:20] - node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1460:18] - node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1460:44] - node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1460:77] - node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1460:101] + node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1442:20] + node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1442:18] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1442:44] + node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1442:77] + node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1442:101] node _T_30 = cat(_T_28, _T_29) @[Cat.scala 29:58] - node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:5] - node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:21] - node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1461:19] - node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:46] - node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1461:44] - node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:59] - node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1461:57] - node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1461:81] + node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1443:5] + node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1443:21] + node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1443:19] + node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1443:46] + node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1443:44] + node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1443:59] + node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1443:57] + node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1443:81] node _T_39 = mux(_T_9, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] node _T_40 = mux(_T_14, _T_16, UInt<1>("h00")) @[Mux.scala 27:72] node _T_41 = mux(_T_19, _T_21, UInt<1>("h00")) @[Mux.scala 27:72] @@ -72964,23 +72964,23 @@ circuit quasar_wrapper : node _T_49 = or(_T_48, _T_44) @[Mux.scala 27:72] wire mstatus_ns : UInt<2> @[Mux.scala 27:72] mstatus_ns <= _T_49 @[Mux.scala 27:72] - node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1464:33] - node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1464:33] - node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1464:50] - node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1464:90] - node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1464:81] - node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1464:47] - io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1464:20] - reg _T_56 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1466:11] - _T_56 <= mstatus_ns @[dec_tlu_ctl.scala 1466:11] - io.mstatus <= _T_56 @[dec_tlu_ctl.scala 1465:13] - node _T_57 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1475:62] - node _T_58 = eq(_T_57, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1475:69] - node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_58) @[dec_tlu_ctl.scala 1475:40] - node _T_59 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1476:40] - node _T_60 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1476:68] + node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1446:33] + node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1446:33] + node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1446:50] + node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1446:90] + node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1446:81] + node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1446:47] + io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1446:20] + reg _T_56 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1448:11] + _T_56 <= mstatus_ns @[dec_tlu_ctl.scala 1448:11] + io.mstatus <= _T_56 @[dec_tlu_ctl.scala 1447:13] + node _T_57 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1457:62] + node _T_58 = eq(_T_57, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1457:69] + node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_58) @[dec_tlu_ctl.scala 1457:40] + node _T_59 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1458:40] + node _T_60 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1458:68] node mtvec_ns = cat(_T_59, _T_60) @[Cat.scala 29:58] - node _T_61 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1477:42] + node _T_61 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1459:42] inst rvclkhdr of rvclkhdr_720 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -72989,57 +72989,57 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_62 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_62 <= mtvec_ns @[lib.scala 374:16] - io.mtvec <= _T_62 @[dec_tlu_ctl.scala 1477:11] - node _T_63 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1489:30] - node ce_int = or(_T_63, mice_ce_req) @[dec_tlu_ctl.scala 1489:46] + io.mtvec <= _T_62 @[dec_tlu_ctl.scala 1459:11] + node _T_63 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1471:30] + node ce_int = or(_T_63, mice_ce_req) @[dec_tlu_ctl.scala 1471:46] node _T_64 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58] node _T_65 = cat(_T_64, io.soft_int_sync) @[Cat.scala 29:58] node _T_66 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58] node _T_67 = cat(_T_66, io.dec_timer_t1_pulse) @[Cat.scala 29:58] node mip_ns = cat(_T_67, _T_65) @[Cat.scala 29:58] - reg _T_68 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1493:11] - _T_68 <= mip_ns @[dec_tlu_ctl.scala 1493:11] - io.mip <= _T_68 @[dec_tlu_ctl.scala 1492:9] - node _T_69 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1505:60] - node _T_70 = eq(_T_69, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1505:67] - node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_70) @[dec_tlu_ctl.scala 1505:38] - node _T_71 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1506:28] - node _T_72 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1506:59] - node _T_73 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1506:88] - node _T_74 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1506:113] - node _T_75 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1506:137] + reg _T_68 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1475:11] + _T_68 <= mip_ns @[dec_tlu_ctl.scala 1475:11] + io.mip <= _T_68 @[dec_tlu_ctl.scala 1474:9] + node _T_69 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1487:60] + node _T_70 = eq(_T_69, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1487:67] + node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_70) @[dec_tlu_ctl.scala 1487:38] + node _T_71 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1488:28] + node _T_72 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1488:59] + node _T_73 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1488:88] + node _T_74 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1488:113] + node _T_75 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1488:137] node _T_76 = cat(_T_74, _T_75) @[Cat.scala 29:58] node _T_77 = cat(_T_72, _T_73) @[Cat.scala 29:58] node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58] - node _T_79 = mux(_T_71, _T_78, mie) @[dec_tlu_ctl.scala 1506:18] - io.mie_ns <= _T_79 @[dec_tlu_ctl.scala 1506:12] - reg _T_80 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1508:11] - _T_80 <= io.mie_ns @[dec_tlu_ctl.scala 1508:11] - mie <= _T_80 @[dec_tlu_ctl.scala 1507:6] - node _T_81 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1515:63] - node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_81) @[dec_tlu_ctl.scala 1515:54] - node _T_82 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1517:64] - node _T_83 = eq(_T_82, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1517:71] - node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_83) @[dec_tlu_ctl.scala 1517:42] - node _T_84 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1519:80] - node _T_85 = and(io.dec_tlu_dbg_halted, _T_84) @[dec_tlu_ctl.scala 1519:71] - node _T_86 = or(kill_ebreak_count_r, _T_85) @[dec_tlu_ctl.scala 1519:46] - node _T_87 = or(_T_86, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1519:94] - node _T_88 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1519:136] - node _T_89 = or(_T_87, _T_88) @[dec_tlu_ctl.scala 1519:121] - node mcyclel_cout_in = not(_T_89) @[dec_tlu_ctl.scala 1519:24] + node _T_79 = mux(_T_71, _T_78, mie) @[dec_tlu_ctl.scala 1488:18] + io.mie_ns <= _T_79 @[dec_tlu_ctl.scala 1488:12] + reg _T_80 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1490:11] + _T_80 <= io.mie_ns @[dec_tlu_ctl.scala 1490:11] + mie <= _T_80 @[dec_tlu_ctl.scala 1489:6] + node _T_81 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1497:63] + node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_81) @[dec_tlu_ctl.scala 1497:54] + node _T_82 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1499:64] + node _T_83 = eq(_T_82, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1499:71] + node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_83) @[dec_tlu_ctl.scala 1499:42] + node _T_84 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1501:80] + node _T_85 = and(io.dec_tlu_dbg_halted, _T_84) @[dec_tlu_ctl.scala 1501:71] + node _T_86 = or(kill_ebreak_count_r, _T_85) @[dec_tlu_ctl.scala 1501:46] + node _T_87 = or(_T_86, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1501:94] + node _T_88 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1501:136] + node _T_89 = or(_T_87, _T_88) @[dec_tlu_ctl.scala 1501:121] + node mcyclel_cout_in = not(_T_89) @[dec_tlu_ctl.scala 1501:24] wire mcyclel_inc : UInt<33> mcyclel_inc <= UInt<1>("h00") node _T_90 = cat(UInt<31>("h00"), mcyclel_cout_in) @[Cat.scala 29:58] - node _T_91 = add(mcyclel, _T_90) @[dec_tlu_ctl.scala 1523:25] - mcyclel_inc <= _T_91 @[dec_tlu_ctl.scala 1523:14] - node _T_92 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1524:36] - node _T_93 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1524:76] - node mcyclel_ns = mux(_T_92, io.dec_csr_wrdata_r, _T_93) @[dec_tlu_ctl.scala 1524:22] - node _T_94 = bits(mcyclel_inc, 32, 32) @[dec_tlu_ctl.scala 1525:32] - node mcyclel_cout = bits(_T_94, 0, 0) @[dec_tlu_ctl.scala 1525:37] - node _T_95 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1526:46] - node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 1526:72] + node _T_91 = add(mcyclel, _T_90) @[dec_tlu_ctl.scala 1505:25] + mcyclel_inc <= _T_91 @[dec_tlu_ctl.scala 1505:14] + node _T_92 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1506:36] + node _T_93 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1506:76] + node mcyclel_ns = mux(_T_92, io.dec_csr_wrdata_r, _T_93) @[dec_tlu_ctl.scala 1506:22] + node _T_94 = bits(mcyclel_inc, 32, 32) @[dec_tlu_ctl.scala 1507:32] + node mcyclel_cout = bits(_T_94, 0, 0) @[dec_tlu_ctl.scala 1507:37] + node _T_95 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1508:46] + node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 1508:72] inst rvclkhdr_1 of rvclkhdr_721 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -73048,22 +73048,22 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_97 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_97 <= mcyclel_ns @[lib.scala 374:16] - mcyclel <= _T_97 @[dec_tlu_ctl.scala 1526:10] - node _T_98 = eq(wr_mcycleh_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1527:71] - node _T_99 = and(mcyclel_cout, _T_98) @[dec_tlu_ctl.scala 1527:69] - reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1527:54] - mcyclel_cout_f <= _T_99 @[dec_tlu_ctl.scala 1527:54] - node _T_100 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1533:61] - node _T_101 = eq(_T_100, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1533:68] - node _T_102 = and(io.dec_csr_wen_r_mod, _T_101) @[dec_tlu_ctl.scala 1533:39] - wr_mcycleh_r <= _T_102 @[dec_tlu_ctl.scala 1533:15] + mcyclel <= _T_97 @[dec_tlu_ctl.scala 1508:10] + node _T_98 = eq(wr_mcycleh_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1509:71] + node _T_99 = and(mcyclel_cout, _T_98) @[dec_tlu_ctl.scala 1509:69] + reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1509:54] + mcyclel_cout_f <= _T_99 @[dec_tlu_ctl.scala 1509:54] + node _T_100 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1515:61] + node _T_101 = eq(_T_100, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1515:68] + node _T_102 = and(io.dec_csr_wen_r_mod, _T_101) @[dec_tlu_ctl.scala 1515:39] + wr_mcycleh_r <= _T_102 @[dec_tlu_ctl.scala 1515:15] node _T_103 = cat(UInt<31>("h00"), mcyclel_cout_f) @[Cat.scala 29:58] - node _T_104 = add(mcycleh, _T_103) @[dec_tlu_ctl.scala 1535:28] - node mcycleh_inc = tail(_T_104, 1) @[dec_tlu_ctl.scala 1535:28] - node _T_105 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1536:36] - node mcycleh_ns = mux(_T_105, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1536:22] - node _T_106 = or(wr_mcycleh_r, mcyclel_cout_f) @[dec_tlu_ctl.scala 1538:46] - node _T_107 = bits(_T_106, 0, 0) @[dec_tlu_ctl.scala 1538:64] + node _T_104 = add(mcycleh, _T_103) @[dec_tlu_ctl.scala 1517:28] + node mcycleh_inc = tail(_T_104, 1) @[dec_tlu_ctl.scala 1517:28] + node _T_105 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1518:36] + node mcycleh_ns = mux(_T_105, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1518:22] + node _T_106 = or(wr_mcycleh_r, mcyclel_cout_f) @[dec_tlu_ctl.scala 1520:46] + node _T_107 = bits(_T_106, 0, 0) @[dec_tlu_ctl.scala 1520:64] inst rvclkhdr_2 of rvclkhdr_722 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -73072,28 +73072,28 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_108 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_108 <= mcycleh_ns @[lib.scala 374:16] - mcycleh <= _T_108 @[dec_tlu_ctl.scala 1538:10] - node _T_109 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1552:72] - node _T_110 = or(_T_109, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1552:85] - node _T_111 = or(_T_110, io.illegal_r) @[dec_tlu_ctl.scala 1552:113] - node _T_112 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1552:143] - node _T_113 = or(_T_111, _T_112) @[dec_tlu_ctl.scala 1552:128] - node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 1552:148] - node _T_115 = not(_T_114) @[dec_tlu_ctl.scala 1552:58] - node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_115) @[dec_tlu_ctl.scala 1552:56] - node _T_116 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1554:66] - node _T_117 = eq(_T_116, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1554:73] - node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_117) @[dec_tlu_ctl.scala 1554:44] + mcycleh <= _T_108 @[dec_tlu_ctl.scala 1520:10] + node _T_109 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1534:72] + node _T_110 = or(_T_109, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1534:85] + node _T_111 = or(_T_110, io.illegal_r) @[dec_tlu_ctl.scala 1534:113] + node _T_112 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1534:143] + node _T_113 = or(_T_111, _T_112) @[dec_tlu_ctl.scala 1534:128] + node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 1534:148] + node _T_115 = not(_T_114) @[dec_tlu_ctl.scala 1534:58] + node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_115) @[dec_tlu_ctl.scala 1534:56] + node _T_116 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1536:66] + node _T_117 = eq(_T_116, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1536:73] + node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_117) @[dec_tlu_ctl.scala 1536:44] node _T_118 = cat(UInt<31>("h00"), i0_valid_no_ebreak_ecall_r) @[Cat.scala 29:58] - node _T_119 = add(minstretl, _T_118) @[dec_tlu_ctl.scala 1556:29] - minstretl_inc <= _T_119 @[dec_tlu_ctl.scala 1556:16] - node minstretl_cout = bits(minstretl_inc, 32, 32) @[dec_tlu_ctl.scala 1557:36] - node _T_120 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[dec_tlu_ctl.scala 1558:52] - node minstret_enable = bits(_T_120, 0, 0) @[dec_tlu_ctl.scala 1558:70] - node _T_121 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1560:40] - node _T_122 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1560:83] - node minstretl_ns = mux(_T_121, io.dec_csr_wrdata_r, _T_122) @[dec_tlu_ctl.scala 1560:24] - node _T_123 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1561:51] + node _T_119 = add(minstretl, _T_118) @[dec_tlu_ctl.scala 1538:29] + minstretl_inc <= _T_119 @[dec_tlu_ctl.scala 1538:16] + node minstretl_cout = bits(minstretl_inc, 32, 32) @[dec_tlu_ctl.scala 1539:36] + node _T_120 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[dec_tlu_ctl.scala 1540:52] + node minstret_enable = bits(_T_120, 0, 0) @[dec_tlu_ctl.scala 1540:70] + node _T_121 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1542:40] + node _T_122 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1542:83] + node minstretl_ns = mux(_T_121, io.dec_csr_wrdata_r, _T_122) @[dec_tlu_ctl.scala 1542:24] + node _T_123 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1543:51] inst rvclkhdr_3 of rvclkhdr_723 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -73102,26 +73102,26 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_124 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_124 <= minstretl_ns @[lib.scala 374:16] - minstretl <= _T_124 @[dec_tlu_ctl.scala 1561:12] - reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1562:56] - minstret_enable_f <= minstret_enable @[dec_tlu_ctl.scala 1562:56] - node _T_125 = not(wr_minstreth_r) @[dec_tlu_ctl.scala 1563:75] - node _T_126 = and(minstretl_cout, _T_125) @[dec_tlu_ctl.scala 1563:73] - reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1563:56] - minstretl_cout_f <= _T_126 @[dec_tlu_ctl.scala 1563:56] - node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1571:64] - node _T_128 = eq(_T_127, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1571:71] - node _T_129 = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1571:42] - node _T_130 = bits(_T_129, 0, 0) @[dec_tlu_ctl.scala 1571:87] - wr_minstreth_r <= _T_130 @[dec_tlu_ctl.scala 1571:17] + minstretl <= _T_124 @[dec_tlu_ctl.scala 1543:12] + reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1544:56] + minstret_enable_f <= minstret_enable @[dec_tlu_ctl.scala 1544:56] + node _T_125 = not(wr_minstreth_r) @[dec_tlu_ctl.scala 1545:75] + node _T_126 = and(minstretl_cout, _T_125) @[dec_tlu_ctl.scala 1545:73] + reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1545:56] + minstretl_cout_f <= _T_126 @[dec_tlu_ctl.scala 1545:56] + node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1553:64] + node _T_128 = eq(_T_127, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1553:71] + node _T_129 = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1553:42] + node _T_130 = bits(_T_129, 0, 0) @[dec_tlu_ctl.scala 1553:87] + wr_minstreth_r <= _T_130 @[dec_tlu_ctl.scala 1553:17] node _T_131 = cat(UInt<31>("h00"), minstretl_cout_f) @[Cat.scala 29:58] - node _T_132 = add(minstreth, _T_131) @[dec_tlu_ctl.scala 1574:29] - node _T_133 = tail(_T_132, 1) @[dec_tlu_ctl.scala 1574:29] - minstreth_inc <= _T_133 @[dec_tlu_ctl.scala 1574:16] - node _T_134 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1575:41] - node minstreth_ns = mux(_T_134, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1575:25] - node _T_135 = or(minstret_enable_f, wr_minstreth_r) @[dec_tlu_ctl.scala 1577:55] - node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 1577:73] + node _T_132 = add(minstreth, _T_131) @[dec_tlu_ctl.scala 1556:29] + node _T_133 = tail(_T_132, 1) @[dec_tlu_ctl.scala 1556:29] + minstreth_inc <= _T_133 @[dec_tlu_ctl.scala 1556:16] + node _T_134 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1557:41] + node minstreth_ns = mux(_T_134, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1557:25] + node _T_135 = or(minstret_enable_f, wr_minstreth_r) @[dec_tlu_ctl.scala 1559:55] + node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 1559:73] inst rvclkhdr_4 of rvclkhdr_724 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -73130,11 +73130,11 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_137 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_137 <= minstreth_ns @[lib.scala 374:16] - minstreth <= _T_137 @[dec_tlu_ctl.scala 1577:12] - node _T_138 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1585:65] - node _T_139 = eq(_T_138, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1585:72] - node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_139) @[dec_tlu_ctl.scala 1585:43] - node _T_140 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1587:55] + minstreth <= _T_137 @[dec_tlu_ctl.scala 1559:12] + node _T_138 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1567:65] + node _T_139 = eq(_T_138, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1567:72] + node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_139) @[dec_tlu_ctl.scala 1567:43] + node _T_140 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1569:55] inst rvclkhdr_5 of rvclkhdr_725 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -73143,24 +73143,24 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_141 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_141 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mscratch <= _T_141 @[dec_tlu_ctl.scala 1587:11] - node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1596:22] - node _T_143 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1596:47] - node _T_144 = and(_T_142, _T_143) @[dec_tlu_ctl.scala 1596:45] - node sel_exu_npc_r = and(_T_144, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1596:72] - node _T_145 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1597:24] - node _T_146 = and(_T_145, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1597:47] - node _T_147 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1597:75] - node sel_flush_npc_r = and(_T_146, _T_147) @[dec_tlu_ctl.scala 1597:73] - node _T_148 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1598:23] - node _T_149 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1598:40] - node sel_hold_npc_r = and(_T_148, _T_149) @[dec_tlu_ctl.scala 1598:38] - node _T_150 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1601:26] - node _T_151 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1602:13] - node _T_152 = and(_T_151, io.reset_delayed) @[dec_tlu_ctl.scala 1602:35] - node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 1602:55] - node _T_154 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1603:28] - node _T_155 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1604:27] + mscratch <= _T_141 @[dec_tlu_ctl.scala 1569:11] + node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1578:22] + node _T_143 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1578:47] + node _T_144 = and(_T_142, _T_143) @[dec_tlu_ctl.scala 1578:45] + node sel_exu_npc_r = and(_T_144, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1578:72] + node _T_145 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1579:24] + node _T_146 = and(_T_145, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1579:47] + node _T_147 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1579:75] + node sel_flush_npc_r = and(_T_146, _T_147) @[dec_tlu_ctl.scala 1579:73] + node _T_148 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1580:23] + node _T_149 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1580:40] + node sel_hold_npc_r = and(_T_148, _T_149) @[dec_tlu_ctl.scala 1580:38] + node _T_150 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1583:26] + node _T_151 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1584:13] + node _T_152 = and(_T_151, io.reset_delayed) @[dec_tlu_ctl.scala 1584:35] + node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 1584:55] + node _T_154 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1585:28] + node _T_155 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1586:27] node _T_156 = mux(_T_150, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_157 = mux(_T_153, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72] node _T_158 = mux(_T_154, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73170,10 +73170,10 @@ circuit quasar_wrapper : node _T_162 = or(_T_161, _T_159) @[Mux.scala 27:72] wire _T_163 : UInt<31> @[Mux.scala 27:72] _T_163 <= _T_162 @[Mux.scala 27:72] - io.npc_r <= _T_163 @[dec_tlu_ctl.scala 1600:11] - node _T_164 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1606:48] - node _T_165 = or(_T_164, io.reset_delayed) @[dec_tlu_ctl.scala 1606:66] - node _T_166 = bits(_T_165, 0, 0) @[dec_tlu_ctl.scala 1606:86] + io.npc_r <= _T_163 @[dec_tlu_ctl.scala 1582:11] + node _T_164 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1588:48] + node _T_165 = or(_T_164, io.reset_delayed) @[dec_tlu_ctl.scala 1588:66] + node _T_166 = bits(_T_165, 0, 0) @[dec_tlu_ctl.scala 1588:86] inst rvclkhdr_6 of rvclkhdr_726 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -73182,11 +73182,11 @@ circuit quasar_wrapper : rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_167 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_167 <= io.npc_r @[lib.scala 374:16] - io.npc_r_d1 <= _T_167 @[dec_tlu_ctl.scala 1606:14] - node _T_168 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1609:21] - node _T_169 = and(_T_168, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1609:44] - node pc0_valid_r = bits(_T_169, 0, 0) @[dec_tlu_ctl.scala 1609:69] - node _T_170 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1613:22] + io.npc_r_d1 <= _T_167 @[dec_tlu_ctl.scala 1588:14] + node _T_168 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1591:21] + node _T_169 = and(_T_168, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1591:44] + node pc0_valid_r = bits(_T_169, 0, 0) @[dec_tlu_ctl.scala 1591:69] + node _T_170 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1595:22] node _T_171 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_172 = mux(_T_170, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_173 = or(_T_171, _T_172) @[Mux.scala 27:72] @@ -73200,22 +73200,22 @@ circuit quasar_wrapper : rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_174 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_174 <= pc_r @[lib.scala 374:16] - pc_r_d1 <= _T_174 @[dec_tlu_ctl.scala 1615:10] - node _T_175 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1617:61] - node _T_176 = eq(_T_175, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1617:68] - node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_176) @[dec_tlu_ctl.scala 1617:39] - node _T_177 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1620:27] - node _T_178 = or(_T_177, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1620:48] - node _T_179 = bits(_T_178, 0, 0) @[dec_tlu_ctl.scala 1620:80] - node _T_180 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1621:25] - node _T_181 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1622:15] - node _T_182 = and(wr_mepc_r, _T_181) @[dec_tlu_ctl.scala 1622:13] - node _T_183 = bits(_T_182, 0, 0) @[dec_tlu_ctl.scala 1622:39] - node _T_184 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1622:104] - node _T_185 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1623:3] - node _T_186 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1623:16] - node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 1623:14] - node _T_188 = bits(_T_187, 0, 0) @[dec_tlu_ctl.scala 1623:40] + pc_r_d1 <= _T_174 @[dec_tlu_ctl.scala 1597:10] + node _T_175 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1599:61] + node _T_176 = eq(_T_175, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1599:68] + node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_176) @[dec_tlu_ctl.scala 1599:39] + node _T_177 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1602:27] + node _T_178 = or(_T_177, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1602:48] + node _T_179 = bits(_T_178, 0, 0) @[dec_tlu_ctl.scala 1602:80] + node _T_180 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1603:25] + node _T_181 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1604:15] + node _T_182 = and(wr_mepc_r, _T_181) @[dec_tlu_ctl.scala 1604:13] + node _T_183 = bits(_T_182, 0, 0) @[dec_tlu_ctl.scala 1604:39] + node _T_184 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1604:104] + node _T_185 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1605:3] + node _T_186 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1605:16] + node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 1605:14] + node _T_188 = bits(_T_187, 0, 0) @[dec_tlu_ctl.scala 1605:40] node _T_189 = mux(_T_179, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_190 = mux(_T_180, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_191 = mux(_T_183, _T_184, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73225,42 +73225,42 @@ circuit quasar_wrapper : node _T_195 = or(_T_194, _T_192) @[Mux.scala 27:72] wire mepc_ns : UInt<31> @[Mux.scala 27:72] mepc_ns <= _T_195 @[Mux.scala 27:72] - reg _T_196 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1625:47] - _T_196 <= mepc_ns @[dec_tlu_ctl.scala 1625:47] - io.mepc <= _T_196 @[dec_tlu_ctl.scala 1625:10] - node _T_197 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1632:65] - node _T_198 = eq(_T_197, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1632:72] - node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_198) @[dec_tlu_ctl.scala 1632:43] - node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1633:53] - node mcause_sel_nmi_store = and(_T_199, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1633:67] - node _T_200 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1634:52] - node mcause_sel_nmi_load = and(_T_200, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1634:66] - node _T_201 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1635:51] - node _T_202 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1635:84] - node mcause_sel_nmi_ext = and(_T_201, _T_202) @[dec_tlu_ctl.scala 1635:65] - node _T_203 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1641:53] - node _T_204 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1641:76] - node _T_205 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1641:99] - node _T_206 = not(_T_205) @[dec_tlu_ctl.scala 1641:82] - node _T_207 = and(_T_204, _T_206) @[dec_tlu_ctl.scala 1641:80] + reg _T_196 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1607:47] + _T_196 <= mepc_ns @[dec_tlu_ctl.scala 1607:47] + io.mepc <= _T_196 @[dec_tlu_ctl.scala 1607:10] + node _T_197 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1614:65] + node _T_198 = eq(_T_197, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1614:72] + node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_198) @[dec_tlu_ctl.scala 1614:43] + node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1615:53] + node mcause_sel_nmi_store = and(_T_199, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1615:67] + node _T_200 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1616:52] + node mcause_sel_nmi_load = and(_T_200, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1616:66] + node _T_201 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1617:51] + node _T_202 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1617:84] + node mcause_sel_nmi_ext = and(_T_201, _T_202) @[dec_tlu_ctl.scala 1617:65] + node _T_203 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1623:53] + node _T_204 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1623:76] + node _T_205 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1623:99] + node _T_206 = not(_T_205) @[dec_tlu_ctl.scala 1623:82] + node _T_207 = and(_T_204, _T_206) @[dec_tlu_ctl.scala 1623:80] node mcause_fir_error_type = cat(_T_203, _T_207) @[Cat.scala 29:58] - node _T_208 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1644:52] - node _T_209 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1645:51] - node _T_210 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1646:50] + node _T_208 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1626:52] + node _T_209 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1627:51] + node _T_210 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1628:50] node _T_211 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58] node _T_212 = cat(_T_211, mcause_fir_error_type) @[Cat.scala 29:58] - node _T_213 = not(io.take_nmi) @[dec_tlu_ctl.scala 1647:56] - node _T_214 = and(io.exc_or_int_valid_r, _T_213) @[dec_tlu_ctl.scala 1647:54] - node _T_215 = bits(_T_214, 0, 0) @[dec_tlu_ctl.scala 1647:70] + node _T_213 = not(io.take_nmi) @[dec_tlu_ctl.scala 1629:56] + node _T_214 = and(io.exc_or_int_valid_r, _T_213) @[dec_tlu_ctl.scala 1629:54] + node _T_215 = bits(_T_214, 0, 0) @[dec_tlu_ctl.scala 1629:70] node _T_216 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58] node _T_217 = cat(_T_216, io.exc_cause_r) @[Cat.scala 29:58] - node _T_218 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1648:46] - node _T_219 = and(wr_mcause_r, _T_218) @[dec_tlu_ctl.scala 1648:44] - node _T_220 = bits(_T_219, 0, 0) @[dec_tlu_ctl.scala 1648:70] - node _T_221 = not(wr_mcause_r) @[dec_tlu_ctl.scala 1649:32] - node _T_222 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1649:47] - node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 1649:45] - node _T_224 = bits(_T_223, 0, 0) @[dec_tlu_ctl.scala 1649:71] + node _T_218 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1630:46] + node _T_219 = and(wr_mcause_r, _T_218) @[dec_tlu_ctl.scala 1630:44] + node _T_220 = bits(_T_219, 0, 0) @[dec_tlu_ctl.scala 1630:70] + node _T_221 = not(wr_mcause_r) @[dec_tlu_ctl.scala 1631:32] + node _T_222 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1631:47] + node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 1631:45] + node _T_224 = bits(_T_223, 0, 0) @[dec_tlu_ctl.scala 1631:71] node _T_225 = mux(_T_208, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_226 = mux(_T_209, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_227 = mux(_T_210, _T_212, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73274,19 +73274,19 @@ circuit quasar_wrapper : node _T_235 = or(_T_234, _T_230) @[Mux.scala 27:72] wire mcause_ns : UInt<32> @[Mux.scala 27:72] mcause_ns <= _T_235 @[Mux.scala 27:72] - reg _T_236 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1651:49] - _T_236 <= mcause_ns @[dec_tlu_ctl.scala 1651:49] - mcause <= _T_236 @[dec_tlu_ctl.scala 1651:12] - node _T_237 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1658:64] - node _T_238 = eq(_T_237, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1658:71] - node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_238) @[dec_tlu_ctl.scala 1658:42] - node _T_239 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1660:56] + reg _T_236 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1633:49] + _T_236 <= mcause_ns @[dec_tlu_ctl.scala 1633:49] + mcause <= _T_236 @[dec_tlu_ctl.scala 1633:12] + node _T_237 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1640:64] + node _T_238 = eq(_T_237, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1640:71] + node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_238) @[dec_tlu_ctl.scala 1640:42] + node _T_239 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1642:56] node _T_240 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58] - node ifu_mscause = mux(_T_239, UInt<4>("h09"), _T_240) @[dec_tlu_ctl.scala 1660:24] - node _T_241 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1663:36] - node _T_242 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1664:40] - node _T_243 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1665:32] - node _T_244 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1666:34] + node ifu_mscause = mux(_T_239, UInt<4>("h09"), _T_240) @[dec_tlu_ctl.scala 1642:24] + node _T_241 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1645:36] + node _T_242 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1646:40] + node _T_243 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1647:32] + node _T_244 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1648:34] node _T_245 = mux(_T_241, io.lsu_error_pkt_r.bits.mscause, UInt<1>("h00")) @[Mux.scala 27:72] node _T_246 = mux(_T_242, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_247 = mux(_T_243, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -73296,15 +73296,15 @@ circuit quasar_wrapper : node _T_251 = or(_T_250, _T_248) @[Mux.scala 27:72] wire mscause_type : UInt<4> @[Mux.scala 27:72] mscause_type <= _T_251 @[Mux.scala 27:72] - node _T_252 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1670:48] - node _T_253 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1671:40] - node _T_254 = and(wr_mscause_r, _T_253) @[dec_tlu_ctl.scala 1671:38] - node _T_255 = bits(_T_254, 0, 0) @[dec_tlu_ctl.scala 1671:64] - node _T_256 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1671:103] - node _T_257 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1672:25] - node _T_258 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1672:41] - node _T_259 = and(_T_257, _T_258) @[dec_tlu_ctl.scala 1672:39] - node _T_260 = bits(_T_259, 0, 0) @[dec_tlu_ctl.scala 1672:65] + node _T_252 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1652:48] + node _T_253 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1653:40] + node _T_254 = and(wr_mscause_r, _T_253) @[dec_tlu_ctl.scala 1653:38] + node _T_255 = bits(_T_254, 0, 0) @[dec_tlu_ctl.scala 1653:64] + node _T_256 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1653:103] + node _T_257 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1654:25] + node _T_258 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1654:41] + node _T_259 = and(_T_257, _T_258) @[dec_tlu_ctl.scala 1654:39] + node _T_260 = bits(_T_259, 0, 0) @[dec_tlu_ctl.scala 1654:65] node _T_261 = mux(_T_252, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72] node _T_262 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72] node _T_263 = mux(_T_260, mscause, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73312,60 +73312,60 @@ circuit quasar_wrapper : node _T_265 = or(_T_264, _T_263) @[Mux.scala 27:72] wire mscause_ns : UInt<4> @[Mux.scala 27:72] mscause_ns <= _T_265 @[Mux.scala 27:72] - reg _T_266 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1674:47] - _T_266 <= mscause_ns @[dec_tlu_ctl.scala 1674:47] - mscause <= _T_266 @[dec_tlu_ctl.scala 1674:10] - node _T_267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1681:62] - node _T_268 = eq(_T_267, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1681:69] - node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_268) @[dec_tlu_ctl.scala 1681:40] - node _T_269 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1682:83] - node _T_270 = and(io.inst_acc_r, _T_269) @[dec_tlu_ctl.scala 1682:81] - node _T_271 = or(io.ebreak_r, _T_270) @[dec_tlu_ctl.scala 1682:64] - node _T_272 = or(_T_271, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1682:106] - node _T_273 = and(io.exc_or_int_valid_r, _T_272) @[dec_tlu_ctl.scala 1682:49] - node _T_274 = not(io.take_nmi) @[dec_tlu_ctl.scala 1682:140] - node mtval_capture_pc_r = and(_T_273, _T_274) @[dec_tlu_ctl.scala 1682:138] - node _T_275 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1683:72] - node _T_276 = and(io.exc_or_int_valid_r, _T_275) @[dec_tlu_ctl.scala 1683:55] - node _T_277 = not(io.take_nmi) @[dec_tlu_ctl.scala 1683:98] - node mtval_capture_pc_plus2_r = and(_T_276, _T_277) @[dec_tlu_ctl.scala 1683:96] - node _T_278 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1684:51] - node _T_279 = not(io.take_nmi) @[dec_tlu_ctl.scala 1684:68] - node mtval_capture_inst_r = and(_T_278, _T_279) @[dec_tlu_ctl.scala 1684:66] - node _T_280 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1685:50] - node _T_281 = not(io.take_nmi) @[dec_tlu_ctl.scala 1685:73] - node mtval_capture_lsu_r = and(_T_280, _T_281) @[dec_tlu_ctl.scala 1685:71] - node _T_282 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1686:46] - node _T_283 = and(io.exc_or_int_valid_r, _T_282) @[dec_tlu_ctl.scala 1686:44] - node _T_284 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1686:68] - node _T_285 = and(_T_283, _T_284) @[dec_tlu_ctl.scala 1686:66] - node _T_286 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1686:92] - node _T_287 = and(_T_285, _T_286) @[dec_tlu_ctl.scala 1686:90] - node _T_288 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1686:115] - node mtval_clear_r = and(_T_287, _T_288) @[dec_tlu_ctl.scala 1686:113] - node _T_289 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1690:25] + reg _T_266 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1656:47] + _T_266 <= mscause_ns @[dec_tlu_ctl.scala 1656:47] + mscause <= _T_266 @[dec_tlu_ctl.scala 1656:10] + node _T_267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1663:62] + node _T_268 = eq(_T_267, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1663:69] + node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_268) @[dec_tlu_ctl.scala 1663:40] + node _T_269 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1664:83] + node _T_270 = and(io.inst_acc_r, _T_269) @[dec_tlu_ctl.scala 1664:81] + node _T_271 = or(io.ebreak_r, _T_270) @[dec_tlu_ctl.scala 1664:64] + node _T_272 = or(_T_271, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1664:106] + node _T_273 = and(io.exc_or_int_valid_r, _T_272) @[dec_tlu_ctl.scala 1664:49] + node _T_274 = not(io.take_nmi) @[dec_tlu_ctl.scala 1664:140] + node mtval_capture_pc_r = and(_T_273, _T_274) @[dec_tlu_ctl.scala 1664:138] + node _T_275 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1665:72] + node _T_276 = and(io.exc_or_int_valid_r, _T_275) @[dec_tlu_ctl.scala 1665:55] + node _T_277 = not(io.take_nmi) @[dec_tlu_ctl.scala 1665:98] + node mtval_capture_pc_plus2_r = and(_T_276, _T_277) @[dec_tlu_ctl.scala 1665:96] + node _T_278 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1666:51] + node _T_279 = not(io.take_nmi) @[dec_tlu_ctl.scala 1666:68] + node mtval_capture_inst_r = and(_T_278, _T_279) @[dec_tlu_ctl.scala 1666:66] + node _T_280 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1667:50] + node _T_281 = not(io.take_nmi) @[dec_tlu_ctl.scala 1667:73] + node mtval_capture_lsu_r = and(_T_280, _T_281) @[dec_tlu_ctl.scala 1667:71] + node _T_282 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1668:46] + node _T_283 = and(io.exc_or_int_valid_r, _T_282) @[dec_tlu_ctl.scala 1668:44] + node _T_284 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1668:68] + node _T_285 = and(_T_283, _T_284) @[dec_tlu_ctl.scala 1668:66] + node _T_286 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1668:92] + node _T_287 = and(_T_285, _T_286) @[dec_tlu_ctl.scala 1668:90] + node _T_288 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1668:115] + node mtval_clear_r = and(_T_287, _T_288) @[dec_tlu_ctl.scala 1668:113] + node _T_289 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1672:25] node _T_290 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_291 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1691:31] - node _T_292 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1691:83] - node _T_293 = tail(_T_292, 1) @[dec_tlu_ctl.scala 1691:83] + node _T_291 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1673:31] + node _T_292 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1673:83] + node _T_293 = tail(_T_292, 1) @[dec_tlu_ctl.scala 1673:83] node _T_294 = cat(_T_293, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_295 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1692:27] - node _T_296 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1693:26] - node _T_297 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1694:18] - node _T_298 = and(wr_mtval_r, _T_297) @[dec_tlu_ctl.scala 1694:16] - node _T_299 = bits(_T_298, 0, 0) @[dec_tlu_ctl.scala 1694:48] - node _T_300 = not(io.take_nmi) @[dec_tlu_ctl.scala 1695:5] - node _T_301 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1695:20] - node _T_302 = and(_T_300, _T_301) @[dec_tlu_ctl.scala 1695:18] - node _T_303 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1695:34] - node _T_304 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 1695:32] - node _T_305 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1695:56] - node _T_306 = and(_T_304, _T_305) @[dec_tlu_ctl.scala 1695:54] - node _T_307 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1695:80] - node _T_308 = and(_T_306, _T_307) @[dec_tlu_ctl.scala 1695:78] - node _T_309 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1695:97] - node _T_310 = and(_T_308, _T_309) @[dec_tlu_ctl.scala 1695:95] - node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 1695:119] + node _T_295 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1674:27] + node _T_296 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1675:26] + node _T_297 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1676:18] + node _T_298 = and(wr_mtval_r, _T_297) @[dec_tlu_ctl.scala 1676:16] + node _T_299 = bits(_T_298, 0, 0) @[dec_tlu_ctl.scala 1676:48] + node _T_300 = not(io.take_nmi) @[dec_tlu_ctl.scala 1677:5] + node _T_301 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1677:20] + node _T_302 = and(_T_300, _T_301) @[dec_tlu_ctl.scala 1677:18] + node _T_303 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1677:34] + node _T_304 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 1677:32] + node _T_305 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1677:56] + node _T_306 = and(_T_304, _T_305) @[dec_tlu_ctl.scala 1677:54] + node _T_307 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1677:80] + node _T_308 = and(_T_306, _T_307) @[dec_tlu_ctl.scala 1677:78] + node _T_309 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1677:97] + node _T_310 = and(_T_308, _T_309) @[dec_tlu_ctl.scala 1677:95] + node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 1677:119] node _T_312 = mux(_T_289, _T_290, UInt<1>("h00")) @[Mux.scala 27:72] node _T_313 = mux(_T_291, _T_294, UInt<1>("h00")) @[Mux.scala 27:72] node _T_314 = mux(_T_295, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73379,14 +73379,14 @@ circuit quasar_wrapper : node _T_322 = or(_T_321, _T_317) @[Mux.scala 27:72] wire mtval_ns : UInt<32> @[Mux.scala 27:72] mtval_ns <= _T_322 @[Mux.scala 27:72] - reg _T_323 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1697:46] - _T_323 <= mtval_ns @[dec_tlu_ctl.scala 1697:46] - mtval <= _T_323 @[dec_tlu_ctl.scala 1697:8] - node _T_324 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1712:61] - node _T_325 = eq(_T_324, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1712:68] - node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_325) @[dec_tlu_ctl.scala 1712:39] - node _T_326 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1714:39] - node _T_327 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1714:55] + reg _T_323 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1679:46] + _T_323 <= mtval_ns @[dec_tlu_ctl.scala 1679:46] + mtval <= _T_323 @[dec_tlu_ctl.scala 1679:8] + node _T_324 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1694:61] + node _T_325 = eq(_T_324, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1694:68] + node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_325) @[dec_tlu_ctl.scala 1694:39] + node _T_326 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1696:39] + node _T_327 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1696:55] inst rvclkhdr_8 of rvclkhdr_728 @[lib.scala 368:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -73395,26 +73395,26 @@ circuit quasar_wrapper : rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mcgc <= _T_326 @[lib.scala 374:16] - node _T_328 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1716:38] - io.dec_tlu_misc_clk_override <= _T_328 @[dec_tlu_ctl.scala 1716:31] - node _T_329 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1717:38] - io.dec_tlu_dec_clk_override <= _T_329 @[dec_tlu_ctl.scala 1717:31] - node _T_330 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1718:38] - io.dec_tlu_ifu_clk_override <= _T_330 @[dec_tlu_ctl.scala 1718:31] - node _T_331 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1719:38] - io.dec_tlu_lsu_clk_override <= _T_331 @[dec_tlu_ctl.scala 1719:31] - node _T_332 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1720:38] - io.dec_tlu_bus_clk_override <= _T_332 @[dec_tlu_ctl.scala 1720:31] - node _T_333 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1721:38] - io.dec_tlu_pic_clk_override <= _T_333 @[dec_tlu_ctl.scala 1721:31] - node _T_334 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1722:38] - io.dec_tlu_dccm_clk_override <= _T_334 @[dec_tlu_ctl.scala 1722:31] - node _T_335 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1723:38] - io.dec_tlu_icm_clk_override <= _T_335 @[dec_tlu_ctl.scala 1723:31] - node _T_336 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1742:61] - node _T_337 = eq(_T_336, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1742:68] - node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_337) @[dec_tlu_ctl.scala 1742:39] - node _T_338 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1746:39] + node _T_328 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1698:38] + io.dec_tlu_misc_clk_override <= _T_328 @[dec_tlu_ctl.scala 1698:31] + node _T_329 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1699:38] + io.dec_tlu_dec_clk_override <= _T_329 @[dec_tlu_ctl.scala 1699:31] + node _T_330 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1700:38] + io.dec_tlu_ifu_clk_override <= _T_330 @[dec_tlu_ctl.scala 1700:31] + node _T_331 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1701:38] + io.dec_tlu_lsu_clk_override <= _T_331 @[dec_tlu_ctl.scala 1701:31] + node _T_332 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1702:38] + io.dec_tlu_bus_clk_override <= _T_332 @[dec_tlu_ctl.scala 1702:31] + node _T_333 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1703:38] + io.dec_tlu_pic_clk_override <= _T_333 @[dec_tlu_ctl.scala 1703:31] + node _T_334 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1704:38] + io.dec_tlu_dccm_clk_override <= _T_334 @[dec_tlu_ctl.scala 1704:31] + node _T_335 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1705:38] + io.dec_tlu_icm_clk_override <= _T_335 @[dec_tlu_ctl.scala 1705:31] + node _T_336 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1724:61] + node _T_337 = eq(_T_336, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1724:68] + node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_337) @[dec_tlu_ctl.scala 1724:39] + node _T_338 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1728:39] inst rvclkhdr_9 of rvclkhdr_729 @[lib.scala 368:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -73423,1223 +73423,1223 @@ circuit quasar_wrapper : rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_339 <= mfdc_ns @[lib.scala 374:16] - mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1746:11] - node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1751:40] - node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1751:20] - node _T_342 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1751:67] - node _T_343 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1751:95] - node _T_344 = not(_T_343) @[dec_tlu_ctl.scala 1751:75] - node _T_345 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1751:119] - node _T_346 = cat(_T_344, _T_345) @[Cat.scala 29:58] - node _T_347 = cat(_T_341, _T_342) @[Cat.scala 29:58] + mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1728:11] + node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1737:39] + node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1737:19] + node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1737:66] + node _T_343 = cat(_T_341, _T_342) @[Cat.scala 29:58] + mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1737:12] + node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1738:28] + node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1738:19] + node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1738:54] + node _T_347 = cat(_T_345, UInt<4>("h00")) @[Cat.scala 29:58] node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58] - mfdc_ns <= _T_348 @[dec_tlu_ctl.scala 1751:13] - node _T_349 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1752:29] - node _T_350 = not(_T_349) @[dec_tlu_ctl.scala 1752:20] - node _T_351 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1752:55] - node _T_352 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1752:72] - node _T_353 = not(_T_352) @[dec_tlu_ctl.scala 1752:63] - node _T_354 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1752:85] - node _T_355 = cat(_T_353, _T_354) @[Cat.scala 29:58] - node _T_356 = cat(_T_350, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_357 = cat(_T_356, _T_351) @[Cat.scala 29:58] - node _T_358 = cat(_T_357, _T_355) @[Cat.scala 29:58] - mfdc <= _T_358 @[dec_tlu_ctl.scala 1752:13] - node _T_359 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1760:46] - io.dec_tlu_dma_qos_prty <= _T_359 @[dec_tlu_ctl.scala 1760:39] - node _T_360 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1761:46] - io.dec_tlu_external_ldfwd_disable <= _T_360 @[dec_tlu_ctl.scala 1761:39] - node _T_361 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1762:46] - io.dec_tlu_core_ecc_disable <= _T_361 @[dec_tlu_ctl.scala 1762:39] - node _T_362 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1763:46] - io.dec_tlu_sideeffect_posted_disable <= _T_362 @[dec_tlu_ctl.scala 1763:39] - node _T_363 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1764:46] - io.dec_tlu_bpred_disable <= _T_363 @[dec_tlu_ctl.scala 1764:39] - node _T_364 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1765:46] - io.dec_tlu_wb_coalescing_disable <= _T_364 @[dec_tlu_ctl.scala 1765:39] - node _T_365 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1766:46] - io.dec_tlu_pipelining_disable <= _T_365 @[dec_tlu_ctl.scala 1766:39] - node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1775:70] - node _T_367 = eq(_T_366, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1775:77] - node _T_368 = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1775:48] - node _T_369 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1775:89] - node _T_370 = and(_T_368, _T_369) @[dec_tlu_ctl.scala 1775:87] - node _T_371 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1775:113] - node _T_372 = and(_T_370, _T_371) @[dec_tlu_ctl.scala 1775:111] - io.dec_tlu_wr_pause_r <= _T_372 @[dec_tlu_ctl.scala 1775:24] - node _T_373 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1782:61] - node _T_374 = eq(_T_373, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1782:68] - node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_374) @[dec_tlu_ctl.scala 1782:39] - node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1785:39] - node _T_376 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1785:64] - node _T_377 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1785:91] - node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1785:71] - node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1785:69] - node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1786:41] - node _T_381 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1786:66] - node _T_382 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1786:93] - node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1786:73] - node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1786:71] - node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1787:41] - node _T_386 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1787:66] - node _T_387 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1787:93] - node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1787:73] - node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1787:71] - node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1788:41] - node _T_391 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1788:66] - node _T_392 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1788:93] - node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1788:73] - node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1788:71] - node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1789:41] - node _T_396 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1789:66] - node _T_397 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1789:93] - node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1789:73] - node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1789:71] - node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1790:41] - node _T_401 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1790:66] - node _T_402 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1790:93] - node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1790:73] - node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1790:71] - node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1791:41] - node _T_406 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1791:66] - node _T_407 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1791:93] - node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1791:73] - node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1791:71] - node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1792:41] - node _T_411 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1792:66] - node _T_412 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1792:93] - node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1792:73] - node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1792:71] - node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1793:41] - node _T_416 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1793:66] - node _T_417 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1793:93] - node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1793:73] - node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1793:71] - node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1794:41] - node _T_421 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1794:66] - node _T_422 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1794:93] - node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1794:73] - node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1794:71] - node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1795:41] - node _T_426 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1795:66] - node _T_427 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1795:93] - node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1795:73] - node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1795:71] - node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1796:41] - node _T_431 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1796:66] - node _T_432 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1796:93] - node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1796:73] - node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1796:70] - node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1797:41] - node _T_436 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1797:66] - node _T_437 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1797:93] - node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1797:73] - node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1797:70] - node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1798:41] - node _T_441 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1798:66] - node _T_442 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1798:93] - node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1798:73] - node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1798:70] - node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1799:41] - node _T_446 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1799:66] - node _T_447 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1799:93] - node _T_448 = not(_T_447) @[dec_tlu_ctl.scala 1799:73] - node _T_449 = and(_T_446, _T_448) @[dec_tlu_ctl.scala 1799:70] - node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1800:41] - node _T_451 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1800:66] - node _T_452 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1800:93] - node _T_453 = not(_T_452) @[dec_tlu_ctl.scala 1800:73] - node _T_454 = and(_T_451, _T_453) @[dec_tlu_ctl.scala 1800:70] - node _T_455 = cat(_T_450, _T_454) @[Cat.scala 29:58] - node _T_456 = cat(_T_445, _T_449) @[Cat.scala 29:58] + mfdc <= _T_348 @[dec_tlu_ctl.scala 1738:12] + node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1742:46] + io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1742:39] + node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1743:46] + io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1743:39] + node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1744:46] + io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1744:39] + node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1745:46] + io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1745:39] + node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1746:46] + io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1746:39] + node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1747:46] + io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1747:39] + node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1748:46] + io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1748:39] + node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1757:70] + node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1757:77] + node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1757:48] + node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1757:89] + node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1757:87] + node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1757:113] + node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1757:111] + io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1757:24] + node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1764:61] + node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1764:68] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1764:39] + node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:39] + node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1767:64] + node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:91] + node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1767:71] + node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1767:69] + node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:41] + node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1768:66] + node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:93] + node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1768:73] + node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1768:71] + node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:41] + node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1769:66] + node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:93] + node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1769:73] + node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1769:71] + node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:41] + node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1770:66] + node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:93] + node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1770:73] + node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1770:71] + node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:41] + node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1771:66] + node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:93] + node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1771:73] + node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1771:71] + node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:41] + node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1772:66] + node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:93] + node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1772:73] + node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1772:71] + node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:41] + node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1773:66] + node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:93] + node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1773:73] + node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1773:71] + node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:41] + node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1774:66] + node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:93] + node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1774:73] + node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1774:71] + node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:41] + node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1775:66] + node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:93] + node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1775:73] + node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1775:71] + node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:41] + node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1776:66] + node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:93] + node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1776:73] + node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1776:71] + node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:41] + node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1777:66] + node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:93] + node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1777:73] + node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1777:71] + node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:41] + node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1778:66] + node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:93] + node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1778:73] + node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1778:70] + node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:41] + node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1779:66] + node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:93] + node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1779:73] + node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1779:70] + node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:41] + node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1780:66] + node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:93] + node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1780:73] + node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1780:70] + node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:41] + node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1781:66] + node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:93] + node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1781:73] + node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1781:70] + node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:41] + node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1782:66] + node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:93] + node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1782:73] + node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1782:70] + node _T_445 = cat(_T_440, _T_444) @[Cat.scala 29:58] + node _T_446 = cat(_T_435, _T_439) @[Cat.scala 29:58] + node _T_447 = cat(_T_446, _T_445) @[Cat.scala 29:58] + node _T_448 = cat(_T_430, _T_434) @[Cat.scala 29:58] + node _T_449 = cat(_T_425, _T_429) @[Cat.scala 29:58] + node _T_450 = cat(_T_449, _T_448) @[Cat.scala 29:58] + node _T_451 = cat(_T_450, _T_447) @[Cat.scala 29:58] + node _T_452 = cat(_T_420, _T_424) @[Cat.scala 29:58] + node _T_453 = cat(_T_415, _T_419) @[Cat.scala 29:58] + node _T_454 = cat(_T_453, _T_452) @[Cat.scala 29:58] + node _T_455 = cat(_T_410, _T_414) @[Cat.scala 29:58] + node _T_456 = cat(_T_405, _T_409) @[Cat.scala 29:58] node _T_457 = cat(_T_456, _T_455) @[Cat.scala 29:58] - node _T_458 = cat(_T_440, _T_444) @[Cat.scala 29:58] - node _T_459 = cat(_T_435, _T_439) @[Cat.scala 29:58] - node _T_460 = cat(_T_459, _T_458) @[Cat.scala 29:58] - node _T_461 = cat(_T_460, _T_457) @[Cat.scala 29:58] - node _T_462 = cat(_T_430, _T_434) @[Cat.scala 29:58] - node _T_463 = cat(_T_425, _T_429) @[Cat.scala 29:58] - node _T_464 = cat(_T_463, _T_462) @[Cat.scala 29:58] - node _T_465 = cat(_T_420, _T_424) @[Cat.scala 29:58] - node _T_466 = cat(_T_415, _T_419) @[Cat.scala 29:58] - node _T_467 = cat(_T_466, _T_465) @[Cat.scala 29:58] - node _T_468 = cat(_T_467, _T_464) @[Cat.scala 29:58] - node _T_469 = cat(_T_468, _T_461) @[Cat.scala 29:58] - node _T_470 = cat(_T_410, _T_414) @[Cat.scala 29:58] - node _T_471 = cat(_T_405, _T_409) @[Cat.scala 29:58] + node _T_458 = cat(_T_457, _T_454) @[Cat.scala 29:58] + node _T_459 = cat(_T_458, _T_451) @[Cat.scala 29:58] + node _T_460 = cat(_T_400, _T_404) @[Cat.scala 29:58] + node _T_461 = cat(_T_395, _T_399) @[Cat.scala 29:58] + node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58] + node _T_463 = cat(_T_390, _T_394) @[Cat.scala 29:58] + node _T_464 = cat(_T_385, _T_389) @[Cat.scala 29:58] + node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] + node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58] + node _T_467 = cat(_T_380, _T_384) @[Cat.scala 29:58] + node _T_468 = cat(_T_375, _T_379) @[Cat.scala 29:58] + node _T_469 = cat(_T_468, _T_467) @[Cat.scala 29:58] + node _T_470 = cat(_T_370, _T_374) @[Cat.scala 29:58] + node _T_471 = cat(_T_365, _T_369) @[Cat.scala 29:58] node _T_472 = cat(_T_471, _T_470) @[Cat.scala 29:58] - node _T_473 = cat(_T_400, _T_404) @[Cat.scala 29:58] - node _T_474 = cat(_T_395, _T_399) @[Cat.scala 29:58] - node _T_475 = cat(_T_474, _T_473) @[Cat.scala 29:58] - node _T_476 = cat(_T_475, _T_472) @[Cat.scala 29:58] - node _T_477 = cat(_T_390, _T_394) @[Cat.scala 29:58] - node _T_478 = cat(_T_385, _T_389) @[Cat.scala 29:58] - node _T_479 = cat(_T_478, _T_477) @[Cat.scala 29:58] - node _T_480 = cat(_T_380, _T_384) @[Cat.scala 29:58] - node _T_481 = cat(_T_375, _T_379) @[Cat.scala 29:58] - node _T_482 = cat(_T_481, _T_480) @[Cat.scala 29:58] - node _T_483 = cat(_T_482, _T_479) @[Cat.scala 29:58] - node _T_484 = cat(_T_483, _T_476) @[Cat.scala 29:58] - node mrac_in = cat(_T_484, _T_469) @[Cat.scala 29:58] - node _T_485 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1803:38] + node _T_473 = cat(_T_472, _T_469) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_466) @[Cat.scala 29:58] + node mrac_in = cat(_T_474, _T_459) @[Cat.scala 29:58] + node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1785:38] inst rvclkhdr_10 of rvclkhdr_730 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_10.io.en <= _T_485 @[lib.scala 371:17] + rvclkhdr_10.io.en <= _T_475 @[lib.scala 371:17] rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mrac <= mrac_in @[lib.scala 374:16] - io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1805:21] - node _T_486 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1813:62] - node _T_487 = eq(_T_486, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1813:69] - node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_487) @[dec_tlu_ctl.scala 1813:40] - node _T_488 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1823:59] - node _T_489 = and(io.mdseac_locked_f, _T_488) @[dec_tlu_ctl.scala 1823:57] - node _T_490 = or(mdseac_en, _T_489) @[dec_tlu_ctl.scala 1823:35] - io.mdseac_locked_ns <= _T_490 @[dec_tlu_ctl.scala 1823:22] - node _T_491 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1825:49] - node _T_492 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1825:86] - node _T_493 = and(_T_491, _T_492) @[dec_tlu_ctl.scala 1825:84] - node _T_494 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1825:111] - node _T_495 = and(_T_493, _T_494) @[dec_tlu_ctl.scala 1825:109] - mdseac_en <= _T_495 @[dec_tlu_ctl.scala 1825:12] - node _T_496 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1827:64] + io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1787:21] + node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1795:62] + node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1795:69] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1795:40] + node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1805:59] + node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1805:57] + node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1805:35] + io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1805:22] + node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1807:49] + node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1807:86] + node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1807:84] + node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1807:111] + node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1807:109] + mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1807:12] + node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1809:64] inst rvclkhdr_11 of rvclkhdr_731 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_11.io.en <= _T_496 @[lib.scala 371:17] + rvclkhdr_11.io.en <= _T_486 @[lib.scala 371:17] rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mdseac <= io.lsu_imprecise_error_addr_any @[lib.scala 374:16] - node _T_497 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1836:61] - node _T_498 = eq(_T_497, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1836:68] - node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_498) @[dec_tlu_ctl.scala 1836:39] - node _T_499 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1840:51] - node _T_500 = and(wr_mpmc_r, _T_499) @[dec_tlu_ctl.scala 1840:30] - node _T_501 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1840:57] - node _T_502 = and(_T_500, _T_501) @[dec_tlu_ctl.scala 1840:55] - node _T_503 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1840:89] - node _T_504 = and(_T_502, _T_503) @[dec_tlu_ctl.scala 1840:87] - io.fw_halt_req <= _T_504 @[dec_tlu_ctl.scala 1840:17] + node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1818:61] + node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1818:68] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1818:39] + node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1822:51] + node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1822:30] + node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1822:57] + node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1822:55] + node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1822:89] + node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1822:87] + io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1822:17] wire fw_halted_ns : UInt<1> fw_halted_ns <= UInt<1>("h00") - reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1842:48] - fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1842:48] - node _T_505 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1843:34] - node _T_506 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1843:49] - node _T_507 = and(_T_505, _T_506) @[dec_tlu_ctl.scala 1843:47] - fw_halted_ns <= _T_507 @[dec_tlu_ctl.scala 1843:15] - node _T_508 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1844:29] - node _T_509 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1844:57] - node _T_510 = not(_T_509) @[dec_tlu_ctl.scala 1844:37] - node _T_511 = not(mpmc) @[dec_tlu_ctl.scala 1844:62] - node _T_512 = mux(_T_508, _T_510, _T_511) @[dec_tlu_ctl.scala 1844:18] - mpmc_b_ns <= _T_512 @[dec_tlu_ctl.scala 1844:12] - reg _T_513 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1846:44] - _T_513 <= mpmc_b_ns @[dec_tlu_ctl.scala 1846:44] - mpmc_b <= _T_513 @[dec_tlu_ctl.scala 1846:9] - node _T_514 = not(mpmc_b) @[dec_tlu_ctl.scala 1849:10] - mpmc <= _T_514 @[dec_tlu_ctl.scala 1849:7] - node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1858:40] - node _T_516 = gt(_T_515, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1858:48] - node _T_517 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1858:92] - node csr_sat = mux(_T_516, UInt<5>("h01a"), _T_517) @[dec_tlu_ctl.scala 1858:19] - node _T_518 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1860:63] - node _T_519 = eq(_T_518, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1860:70] - node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_519) @[dec_tlu_ctl.scala 1860:41] - node _T_520 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] - node _T_521 = add(micect, _T_520) @[dec_tlu_ctl.scala 1861:23] - node _T_522 = tail(_T_521, 1) @[dec_tlu_ctl.scala 1861:23] - micect_inc <= _T_522 @[dec_tlu_ctl.scala 1861:13] - node _T_523 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1862:35] - node _T_524 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1862:75] - node _T_525 = cat(csr_sat, _T_524) @[Cat.scala 29:58] - node _T_526 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1862:95] - node _T_527 = cat(_T_526, micect_inc) @[Cat.scala 29:58] - node micect_ns = mux(_T_523, _T_525, _T_527) @[dec_tlu_ctl.scala 1862:22] - node _T_528 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1864:42] - node _T_529 = bits(_T_528, 0, 0) @[dec_tlu_ctl.scala 1864:61] + reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1824:48] + fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1824:48] + node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1825:34] + node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1825:49] + node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1825:47] + fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1825:15] + node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1826:29] + node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1826:57] + node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1826:37] + node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1826:62] + node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1826:18] + mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1826:12] + reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1828:44] + _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1828:44] + mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1828:9] + node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1831:10] + mpmc <= _T_504 @[dec_tlu_ctl.scala 1831:7] + node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:40] + node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1840:48] + node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:92] + node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1840:19] + node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1842:63] + node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1842:70] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1842:41] + node _T_510 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] + node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1843:23] + node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1843:23] + micect_inc <= _T_512 @[dec_tlu_ctl.scala 1843:13] + node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1844:35] + node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1844:75] + node _T_515 = cat(csr_sat, _T_514) @[Cat.scala 29:58] + node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1844:95] + node _T_517 = cat(_T_516, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1844:22] + node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1846:42] + node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1846:61] inst rvclkhdr_12 of rvclkhdr_732 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_12.io.en <= _T_529 @[lib.scala 371:17] + rvclkhdr_12.io.en <= _T_519 @[lib.scala 371:17] rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_530 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_530 <= micect_ns @[lib.scala 374:16] - micect <= _T_530 @[dec_tlu_ctl.scala 1864:9] - node _T_531 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1866:48] - node _T_532 = dshl(UInt<32>("h0ffffffff"), _T_531) @[dec_tlu_ctl.scala 1866:39] - node _T_533 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1866:79] - node _T_534 = cat(UInt<5>("h00"), _T_533) @[Cat.scala 29:58] - node _T_535 = and(_T_532, _T_534) @[dec_tlu_ctl.scala 1866:57] - node _T_536 = orr(_T_535) @[dec_tlu_ctl.scala 1866:88] - mice_ce_req <= _T_536 @[dec_tlu_ctl.scala 1866:14] - node _T_537 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1875:69] - node _T_538 = eq(_T_537, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1875:76] - node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_538) @[dec_tlu_ctl.scala 1875:47] - node _T_539 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1876:26] - node _T_540 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1876:70] - node _T_541 = cat(UInt<26>("h00"), _T_540) @[Cat.scala 29:58] - node _T_542 = add(_T_539, _T_541) @[dec_tlu_ctl.scala 1876:33] - node _T_543 = tail(_T_542, 1) @[dec_tlu_ctl.scala 1876:33] - miccmect_inc <= _T_543 @[dec_tlu_ctl.scala 1876:15] - node _T_544 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1877:45] - node _T_545 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1877:85] - node _T_546 = cat(csr_sat, _T_545) @[Cat.scala 29:58] - node _T_547 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1877:107] - node _T_548 = cat(_T_547, miccmect_inc) @[Cat.scala 29:58] - node miccmect_ns = mux(_T_544, _T_546, _T_548) @[dec_tlu_ctl.scala 1877:30] - node _T_549 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1879:48] - node _T_550 = or(_T_549, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1879:69] - node _T_551 = bits(_T_550, 0, 0) @[dec_tlu_ctl.scala 1879:93] + reg _T_520 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_520 <= micect_ns @[lib.scala 374:16] + micect <= _T_520 @[dec_tlu_ctl.scala 1846:9] + node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1848:48] + node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1848:39] + node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1848:79] + node _T_524 = cat(UInt<5>("h00"), _T_523) @[Cat.scala 29:58] + node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1848:57] + node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1848:88] + mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1848:14] + node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1857:69] + node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1857:76] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1857:47] + node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1858:26] + node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1858:70] + node _T_531 = cat(UInt<26>("h00"), _T_530) @[Cat.scala 29:58] + node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1858:33] + node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1858:33] + miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1858:15] + node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1859:45] + node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1859:85] + node _T_536 = cat(csr_sat, _T_535) @[Cat.scala 29:58] + node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1859:107] + node _T_538 = cat(_T_537, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1859:30] + node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1861:48] + node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1861:69] + node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1861:93] inst rvclkhdr_13 of rvclkhdr_733 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_13.io.en <= _T_551 @[lib.scala 371:17] + rvclkhdr_13.io.en <= _T_541 @[lib.scala 371:17] rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_552 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_552 <= miccmect_ns @[lib.scala 374:16] - miccmect <= _T_552 @[dec_tlu_ctl.scala 1879:11] - node _T_553 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1881:51] - node _T_554 = dshl(UInt<32>("h0ffffffff"), _T_553) @[dec_tlu_ctl.scala 1881:40] - node _T_555 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1881:84] - node _T_556 = cat(UInt<5>("h00"), _T_555) @[Cat.scala 29:58] - node _T_557 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 1881:60] - node _T_558 = orr(_T_557) @[dec_tlu_ctl.scala 1881:93] - miccme_ce_req <= _T_558 @[dec_tlu_ctl.scala 1881:15] - node _T_559 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1890:69] - node _T_560 = eq(_T_559, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1890:76] - node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_560) @[dec_tlu_ctl.scala 1890:47] - node _T_561 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1891:26] - node _T_562 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] - node _T_563 = add(_T_561, _T_562) @[dec_tlu_ctl.scala 1891:33] - node _T_564 = tail(_T_563, 1) @[dec_tlu_ctl.scala 1891:33] - mdccmect_inc <= _T_564 @[dec_tlu_ctl.scala 1891:15] - node _T_565 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1892:45] - node _T_566 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1892:85] - node _T_567 = cat(csr_sat, _T_566) @[Cat.scala 29:58] - node _T_568 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1892:107] - node _T_569 = cat(_T_568, mdccmect_inc) @[Cat.scala 29:58] - node mdccmect_ns = mux(_T_565, _T_567, _T_569) @[dec_tlu_ctl.scala 1892:30] - node _T_570 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1894:49] - node _T_571 = bits(_T_570, 0, 0) @[dec_tlu_ctl.scala 1894:81] + reg _T_542 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_542 <= miccmect_ns @[lib.scala 374:16] + miccmect <= _T_542 @[dec_tlu_ctl.scala 1861:11] + node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1863:51] + node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1863:40] + node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1863:84] + node _T_546 = cat(UInt<5>("h00"), _T_545) @[Cat.scala 29:58] + node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1863:60] + node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1863:93] + miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1863:15] + node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1872:69] + node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1872:76] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1872:47] + node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1873:26] + node _T_552 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1873:33] + node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1873:33] + mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1873:15] + node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1874:45] + node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1874:85] + node _T_557 = cat(csr_sat, _T_556) @[Cat.scala 29:58] + node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1874:107] + node _T_559 = cat(_T_558, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1874:30] + node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1876:49] + node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1876:81] inst rvclkhdr_14 of rvclkhdr_734 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_14.io.en <= _T_571 @[lib.scala 371:17] + rvclkhdr_14.io.en <= _T_561 @[lib.scala 371:17] rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_572 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_572 <= mdccmect_ns @[lib.scala 374:16] - mdccmect <= _T_572 @[dec_tlu_ctl.scala 1894:11] - node _T_573 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1896:52] - node _T_574 = dshl(UInt<32>("h0ffffffff"), _T_573) @[dec_tlu_ctl.scala 1896:41] - node _T_575 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1896:85] - node _T_576 = cat(UInt<5>("h00"), _T_575) @[Cat.scala 29:58] - node _T_577 = and(_T_574, _T_576) @[dec_tlu_ctl.scala 1896:61] - node _T_578 = orr(_T_577) @[dec_tlu_ctl.scala 1896:94] - mdccme_ce_req <= _T_578 @[dec_tlu_ctl.scala 1896:16] - node _T_579 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1906:62] - node _T_580 = eq(_T_579, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1906:69] - node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_580) @[dec_tlu_ctl.scala 1906:40] - node _T_581 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1908:32] - node _T_582 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1908:59] - node mfdht_ns = mux(_T_581, _T_582, mfdht) @[dec_tlu_ctl.scala 1908:20] - reg _T_583 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1910:43] - _T_583 <= mfdht_ns @[dec_tlu_ctl.scala 1910:43] - mfdht <= _T_583 @[dec_tlu_ctl.scala 1910:8] - node _T_584 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1919:62] - node _T_585 = eq(_T_584, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1919:69] - node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_585) @[dec_tlu_ctl.scala 1919:40] - node _T_586 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1921:32] - node _T_587 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1921:60] - node _T_588 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1922:43] - node _T_589 = and(io.dbg_tlu_halted, _T_588) @[dec_tlu_ctl.scala 1922:41] - node _T_590 = bits(_T_589, 0, 0) @[dec_tlu_ctl.scala 1922:65] - node _T_591 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1922:78] - node _T_592 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1922:98] - node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58] - node _T_594 = mux(_T_590, _T_593, mfdhs) @[dec_tlu_ctl.scala 1922:21] - node mfdhs_ns = mux(_T_586, _T_587, _T_594) @[dec_tlu_ctl.scala 1921:20] - node _T_595 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1924:71] - node _T_596 = bits(_T_595, 0, 0) @[dec_tlu_ctl.scala 1924:92] - reg _T_597 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_596 : @[Reg.scala 28:19] - _T_597 <= mfdhs_ns @[Reg.scala 28:23] + reg _T_562 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_562 <= mdccmect_ns @[lib.scala 374:16] + mdccmect <= _T_562 @[dec_tlu_ctl.scala 1876:11] + node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1878:52] + node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1878:41] + node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1878:85] + node _T_566 = cat(UInt<5>("h00"), _T_565) @[Cat.scala 29:58] + node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1878:61] + node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1878:94] + mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1878:16] + node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1888:62] + node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1888:69] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1888:40] + node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1890:32] + node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1890:59] + node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1890:20] + reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1892:43] + _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1892:43] + mfdht <= _T_573 @[dec_tlu_ctl.scala 1892:8] + node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1901:62] + node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1901:69] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1901:40] + node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1903:32] + node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1903:60] + node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1904:43] + node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1904:41] + node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1904:65] + node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1904:78] + node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1904:98] + node _T_583 = cat(_T_581, _T_582) @[Cat.scala 29:58] + node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1904:21] + node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1903:20] + node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1906:71] + node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1906:92] + reg _T_587 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_586 : @[Reg.scala 28:19] + _T_587 <= mfdhs_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mfdhs <= _T_597 @[dec_tlu_ctl.scala 1924:8] - node _T_598 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1926:47] - node _T_599 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1926:74] - node _T_600 = tail(_T_599, 1) @[dec_tlu_ctl.scala 1926:74] - node _T_601 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1927:48] - node _T_602 = mux(_T_601, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1927:27] - node force_halt_ctr = mux(_T_598, _T_600, _T_602) @[dec_tlu_ctl.scala 1926:26] - node _T_603 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1929:81] - reg _T_604 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_603 : @[Reg.scala 28:19] - _T_604 <= force_halt_ctr @[Reg.scala 28:23] + mfdhs <= _T_587 @[dec_tlu_ctl.scala 1906:8] + node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1908:47] + node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1908:74] + node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1908:74] + node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1909:48] + node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1909:27] + node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1908:26] + node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1911:81] + reg _T_594 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_593 : @[Reg.scala 28:19] + _T_594 <= force_halt_ctr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - force_halt_ctr_f <= _T_604 @[dec_tlu_ctl.scala 1929:19] - node _T_605 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1931:24] - node _T_606 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1931:79] - node _T_607 = dshl(UInt<32>("h0ffffffff"), _T_606) @[dec_tlu_ctl.scala 1931:71] - node _T_608 = and(force_halt_ctr_f, _T_607) @[dec_tlu_ctl.scala 1931:48] - node _T_609 = orr(_T_608) @[dec_tlu_ctl.scala 1931:87] - node _T_610 = and(_T_605, _T_609) @[dec_tlu_ctl.scala 1931:28] - io.force_halt <= _T_610 @[dec_tlu_ctl.scala 1931:16] - node _T_611 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1939:62] - node _T_612 = eq(_T_611, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1939:69] - node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_612) @[dec_tlu_ctl.scala 1939:40] - node _T_613 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1941:40] - node _T_614 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1941:59] + force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1911:19] + node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1913:24] + node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1913:79] + node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1913:71] + node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1913:48] + node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1913:87] + node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1913:28] + io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1913:16] + node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62] + node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1921:69] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1921:40] + node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1923:40] + node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1923:59] inst rvclkhdr_15 of rvclkhdr_735 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_15.io.en <= _T_614 @[lib.scala 371:17] + rvclkhdr_15.io.en <= _T_604 @[lib.scala 371:17] rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - meivt <= _T_613 @[lib.scala 374:16] - node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1953:49] + meivt <= _T_603 @[lib.scala 374:16] + node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1935:49] inst rvclkhdr_16 of rvclkhdr_736 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_16.io.en <= _T_615 @[lib.scala 371:17] + rvclkhdr_16.io.en <= _T_605 @[lib.scala 371:17] rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] meihap <= io.pic_claimid @[lib.scala 374:16] - node _T_616 = cat(meivt, meihap) @[Cat.scala 29:58] - io.dec_tlu_meihap <= _T_616 @[dec_tlu_ctl.scala 1954:20] - node _T_617 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1963:65] - node _T_618 = eq(_T_617, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1963:72] - node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_618) @[dec_tlu_ctl.scala 1963:43] - node _T_619 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1964:38] - node _T_620 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1964:65] - node meicurpl_ns = mux(_T_619, _T_620, meicurpl) @[dec_tlu_ctl.scala 1964:23] - reg _T_621 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1966:46] - _T_621 <= meicurpl_ns @[dec_tlu_ctl.scala 1966:46] - meicurpl <= _T_621 @[dec_tlu_ctl.scala 1966:11] - io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1968:22] - node _T_622 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1978:66] - node _T_623 = eq(_T_622, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1978:73] - node _T_624 = and(io.dec_csr_wen_r_mod, _T_623) @[dec_tlu_ctl.scala 1978:44] - node wr_meicidpl_r = or(_T_624, io.take_ext_int_start) @[dec_tlu_ctl.scala 1978:88] - node _T_625 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1980:37] - node _T_626 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1981:38] - node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1981:65] - node _T_628 = mux(_T_626, _T_627, meicidpl) @[dec_tlu_ctl.scala 1981:23] - node meicidpl_ns = mux(_T_625, io.pic_pl, _T_628) @[dec_tlu_ctl.scala 1980:23] - reg _T_629 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1983:44] - _T_629 <= meicidpl_ns @[dec_tlu_ctl.scala 1983:44] - meicidpl <= _T_629 @[dec_tlu_ctl.scala 1983:11] - node _T_630 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1990:62] - node _T_631 = eq(_T_630, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1990:69] - node _T_632 = and(io.dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 1990:40] - node _T_633 = or(_T_632, io.take_ext_int_start) @[dec_tlu_ctl.scala 1990:83] - wr_meicpct_r <= _T_633 @[dec_tlu_ctl.scala 1990:15] - node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1999:62] - node _T_635 = eq(_T_634, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 1999:69] - node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 1999:40] - node _T_636 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2000:32] - node _T_637 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2000:59] - node meipt_ns = mux(_T_636, _T_637, meipt) @[dec_tlu_ctl.scala 2000:20] - reg _T_638 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2002:43] - _T_638 <= meipt_ns @[dec_tlu_ctl.scala 2002:43] - meipt <= _T_638 @[dec_tlu_ctl.scala 2002:8] - io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2004:19] - node _T_639 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2030:89] - node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_639) @[dec_tlu_ctl.scala 2030:66] - node _T_640 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2033:31] - node _T_641 = and(io.dcsr_single_step_done_f, _T_640) @[dec_tlu_ctl.scala 2033:29] - node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2033:63] - node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 2033:61] - node _T_644 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2033:98] - node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2033:96] - node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 2033:118] - node _T_647 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2034:48] - node _T_648 = and(io.debug_halt_req, _T_647) @[dec_tlu_ctl.scala 2034:46] - node _T_649 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2034:80] - node _T_650 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 2034:78] - node _T_651 = bits(_T_650, 0, 0) @[dec_tlu_ctl.scala 2034:114] - node _T_652 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:77] - node _T_653 = and(io.ebreak_to_debug_mode_r_d1, _T_652) @[dec_tlu_ctl.scala 2035:75] - node _T_654 = bits(_T_653, 0, 0) @[dec_tlu_ctl.scala 2035:111] - node _T_655 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2036:108] - node _T_656 = mux(_T_646, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_657 = mux(_T_651, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_658 = mux(_T_654, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_659 = mux(_T_655, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_660 = or(_T_656, _T_657) @[Mux.scala 27:72] - node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72] - node _T_662 = or(_T_661, _T_659) @[Mux.scala 27:72] + node _T_606 = cat(meivt, meihap) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1936:20] + node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1945:65] + node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1945:72] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1945:43] + node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1946:38] + node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1946:65] + node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1946:23] + reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1948:46] + _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1948:46] + meicurpl <= _T_611 @[dec_tlu_ctl.scala 1948:11] + io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1950:22] + node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1960:66] + node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1960:73] + node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1960:44] + node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1960:88] + node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1962:37] + node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1963:38] + node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1963:65] + node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1963:23] + node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1962:23] + reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1965:44] + _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1965:44] + meicidpl <= _T_619 @[dec_tlu_ctl.scala 1965:11] + node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1972:62] + node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1972:69] + node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1972:40] + node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1972:83] + wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1972:15] + node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1981:62] + node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 1981:69] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 1981:40] + node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 1982:32] + node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1982:59] + node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 1982:20] + reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1984:43] + _T_628 <= meipt_ns @[dec_tlu_ctl.scala 1984:43] + meipt <= _T_628 @[dec_tlu_ctl.scala 1984:8] + io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 1986:19] + node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2012:89] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2012:66] + node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2015:31] + node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2015:29] + node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2015:63] + node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2015:61] + node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2015:98] + node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2015:96] + node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2015:118] + node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2016:48] + node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2016:46] + node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2016:80] + node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2016:78] + node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2016:114] + node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2017:77] + node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2017:75] + node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2017:111] + node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2018:108] + node _T_646 = mux(_T_636, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_647 = mux(_T_641, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_648 = mux(_T_644, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_649 = mux(_T_645, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_650 = or(_T_646, _T_647) @[Mux.scala 27:72] + node _T_651 = or(_T_650, _T_648) @[Mux.scala 27:72] + node _T_652 = or(_T_651, _T_649) @[Mux.scala 27:72] wire dcsr_cause : UInt<3> @[Mux.scala 27:72] - dcsr_cause <= _T_662 @[Mux.scala 27:72] - node _T_663 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2038:46] - node _T_664 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2038:91] - node _T_665 = eq(_T_664, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2038:98] - node wr_dcsr_r = and(_T_663, _T_665) @[dec_tlu_ctl.scala 2038:69] - node _T_666 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2044:69] - node _T_667 = eq(_T_666, UInt<3>("h03")) @[dec_tlu_ctl.scala 2044:75] - node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_667) @[dec_tlu_ctl.scala 2044:59] - node _T_668 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2045:59] - node _T_669 = or(_T_668, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2045:78] - node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_669) @[dec_tlu_ctl.scala 2045:56] - node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2047:48] - node _T_670 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2048:44] - node _T_671 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2048:64] - node _T_672 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2048:91] + dcsr_cause <= _T_652 @[Mux.scala 27:72] + node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2020:46] + node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2020:91] + node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2020:98] + node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2020:69] + node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2026:69] + node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2026:75] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2026:59] + node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2027:59] + node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2027:78] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2027:56] + node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2029:48] + node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2030:44] + node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2030:64] + node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2030:91] + node _T_663 = cat(_T_662, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_664 = cat(_T_661, dcsr_cause) @[Cat.scala 29:58] + node _T_665 = cat(_T_664, _T_663) @[Cat.scala 29:58] + node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2031:18] + node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2031:49] + node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2031:84] + node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2031:110] + node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2031:154] + node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2031:145] + node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2031:178] node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_674 = cat(_T_671, dcsr_cause) @[Cat.scala 29:58] + node _T_674 = cat(UInt<2>("h00"), _T_671) @[Cat.scala 29:58] node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58] - node _T_676 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2049:18] - node _T_677 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2049:49] - node _T_678 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2049:84] - node _T_679 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2049:110] - node _T_680 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2049:154] - node _T_681 = or(nmi_in_debug_mode, _T_680) @[dec_tlu_ctl.scala 2049:145] - node _T_682 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2049:178] + node _T_676 = cat(UInt<1>("h00"), _T_669) @[Cat.scala 29:58] + node _T_677 = cat(_T_667, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_678 = cat(_T_677, _T_668) @[Cat.scala 29:58] + node _T_679 = cat(_T_678, _T_676) @[Cat.scala 29:58] + node _T_680 = cat(_T_679, _T_675) @[Cat.scala 29:58] + node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2031:211] + node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2031:245] node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_684 = cat(UInt<2>("h00"), _T_681) @[Cat.scala 29:58] + node _T_684 = cat(_T_681, nmi_in_debug_mode) @[Cat.scala 29:58] node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58] - node _T_686 = cat(UInt<1>("h00"), _T_679) @[Cat.scala 29:58] - node _T_687 = cat(_T_677, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_688 = cat(_T_687, _T_678) @[Cat.scala 29:58] - node _T_689 = cat(_T_688, _T_686) @[Cat.scala 29:58] - node _T_690 = cat(_T_689, _T_685) @[Cat.scala 29:58] - node _T_691 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2049:211] - node _T_692 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2049:245] - node _T_693 = cat(_T_692, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_694 = cat(_T_691, nmi_in_debug_mode) @[Cat.scala 29:58] - node _T_695 = cat(_T_694, _T_693) @[Cat.scala 29:58] - node _T_696 = mux(_T_676, _T_690, _T_695) @[dec_tlu_ctl.scala 2049:7] - node dcsr_ns = mux(_T_670, _T_675, _T_696) @[dec_tlu_ctl.scala 2048:19] - node _T_697 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2051:54] - node _T_698 = or(_T_697, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2051:66] - node _T_699 = or(_T_698, io.take_nmi) @[dec_tlu_ctl.scala 2051:94] - node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2051:109] + node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2031:7] + node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2030:19] + node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2033:54] + node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2033:66] + node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2033:94] + node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2033:109] inst rvclkhdr_17 of rvclkhdr_737 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_17.io.en <= _T_700 @[lib.scala 371:17] + rvclkhdr_17.io.en <= _T_690 @[lib.scala 371:17] rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_701 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_701 <= dcsr_ns @[lib.scala 374:16] - io.dcsr <= _T_701 @[dec_tlu_ctl.scala 2051:10] - node _T_702 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2059:45] - node _T_703 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2059:90] - node _T_704 = eq(_T_703, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2059:97] - node wr_dpc_r = and(_T_702, _T_704) @[dec_tlu_ctl.scala 2059:68] - node _T_705 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2060:44] - node _T_706 = and(io.dbg_tlu_halted, _T_705) @[dec_tlu_ctl.scala 2060:42] - node _T_707 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2060:67] - node dpc_capture_npc = and(_T_706, _T_707) @[dec_tlu_ctl.scala 2060:65] - node _T_708 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2064:21] - node _T_709 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2064:39] - node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 2064:37] - node _T_711 = and(_T_710, wr_dpc_r) @[dec_tlu_ctl.scala 2064:56] - node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2064:68] - node _T_713 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2064:97] - node _T_714 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2065:68] - node _T_715 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2066:33] - node _T_716 = and(_T_715, dpc_capture_npc) @[dec_tlu_ctl.scala 2066:49] - node _T_717 = bits(_T_716, 0, 0) @[dec_tlu_ctl.scala 2066:68] - node _T_718 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_719 = mux(_T_714, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_720 = mux(_T_717, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_721 = or(_T_718, _T_719) @[Mux.scala 27:72] - node _T_722 = or(_T_721, _T_720) @[Mux.scala 27:72] + reg _T_691 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_691 <= dcsr_ns @[lib.scala 374:16] + io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2033:10] + node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2041:45] + node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2041:90] + node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2041:97] + node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2041:68] + node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2042:44] + node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2042:42] + node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2042:67] + node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2042:65] + node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2046:21] + node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2046:39] + node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2046:37] + node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2046:56] + node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2046:68] + node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2046:97] + node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2047:68] + node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2048:33] + node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2048:49] + node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2048:68] + node _T_708 = mux(_T_702, _T_703, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_709 = mux(_T_704, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_710 = mux(_T_707, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_711 = or(_T_708, _T_709) @[Mux.scala 27:72] + node _T_712 = or(_T_711, _T_710) @[Mux.scala 27:72] wire dpc_ns : UInt<31> @[Mux.scala 27:72] - dpc_ns <= _T_722 @[Mux.scala 27:72] - node _T_723 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2068:36] - node _T_724 = or(_T_723, dpc_capture_npc) @[dec_tlu_ctl.scala 2068:53] - node _T_725 = bits(_T_724, 0, 0) @[dec_tlu_ctl.scala 2068:72] + dpc_ns <= _T_712 @[Mux.scala 27:72] + node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2050:36] + node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2050:53] + node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2050:72] inst rvclkhdr_18 of rvclkhdr_738 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset rvclkhdr_18.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_18.io.en <= _T_725 @[lib.scala 371:17] + rvclkhdr_18.io.en <= _T_715 @[lib.scala 371:17] rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_726 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_726 <= dpc_ns @[lib.scala 374:16] - io.dpc <= _T_726 @[dec_tlu_ctl.scala 2068:9] - node _T_727 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2082:43] - node _T_728 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2082:68] - node _T_729 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2082:96] - node _T_730 = cat(_T_727, _T_728) @[Cat.scala 29:58] - node dicawics_ns = cat(_T_730, _T_729) @[Cat.scala 29:58] - node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2083:50] - node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2083:95] - node _T_733 = eq(_T_732, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2083:102] - node wr_dicawics_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2083:73] - node _T_734 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2085:50] + reg _T_716 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_716 <= dpc_ns @[lib.scala 374:16] + io.dpc <= _T_716 @[dec_tlu_ctl.scala 2050:9] + node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2064:43] + node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2064:68] + node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2064:96] + node _T_720 = cat(_T_717, _T_718) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_720, _T_719) @[Cat.scala 29:58] + node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2065:50] + node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2065:95] + node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2065:102] + node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2065:73] + node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2067:50] inst rvclkhdr_19 of rvclkhdr_739 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset rvclkhdr_19.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_19.io.en <= _T_734 @[lib.scala 371:17] + rvclkhdr_19.io.en <= _T_724 @[lib.scala 371:17] rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicawics <= dicawics_ns @[lib.scala 374:16] - node _T_735 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2101:48] - node _T_736 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2101:93] - node _T_737 = eq(_T_736, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2101:100] - node wr_dicad0_r = and(_T_735, _T_737) @[dec_tlu_ctl.scala 2101:71] - node _T_738 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2102:34] - node dicad0_ns = mux(_T_738, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2102:21] - node _T_739 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2104:46] - node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2104:79] + node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2083:48] + node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2083:93] + node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2083:100] + node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2083:71] + node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2084:34] + node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2084:21] + node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2086:46] + node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2086:79] inst rvclkhdr_20 of rvclkhdr_740 @[lib.scala 368:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset rvclkhdr_20.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_20.io.en <= _T_740 @[lib.scala 371:17] + rvclkhdr_20.io.en <= _T_730 @[lib.scala 371:17] rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0 <= dicad0_ns @[lib.scala 374:16] - node _T_741 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2114:49] - node _T_742 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2114:94] - node _T_743 = eq(_T_742, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2114:101] - node wr_dicad0h_r = and(_T_741, _T_743) @[dec_tlu_ctl.scala 2114:72] - node _T_744 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2116:36] - node _T_745 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2116:88] - node dicad0h_ns = mux(_T_744, io.dec_csr_wrdata_r, _T_745) @[dec_tlu_ctl.scala 2116:22] - node _T_746 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2118:48] - node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2118:81] + node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2096:49] + node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2096:94] + node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2096:101] + node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2096:72] + node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2098:36] + node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2098:88] + node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2098:22] + node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2100:48] + node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2100:81] inst rvclkhdr_21 of rvclkhdr_741 @[lib.scala 368:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset rvclkhdr_21.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_21.io.en <= _T_747 @[lib.scala 371:17] + rvclkhdr_21.io.en <= _T_737 @[lib.scala 371:17] rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0h <= dicad0h_ns @[lib.scala 374:16] - wire _T_748 : UInt<7> - _T_748 <= UInt<1>("h00") - node _T_749 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2126:48] - node _T_750 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2126:93] - node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2126:100] - node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2126:71] - node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2128:34] - node _T_754 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2128:86] - node _T_755 = mux(_T_753, io.dec_csr_wrdata_r, _T_754) @[dec_tlu_ctl.scala 2128:21] - node _T_756 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2131:78] - node _T_757 = bits(_T_756, 0, 0) @[dec_tlu_ctl.scala 2131:111] - reg _T_758 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_757 : @[Reg.scala 28:19] - _T_758 <= _T_755 @[Reg.scala 28:23] + wire _T_738 : UInt<7> + _T_738 <= UInt<1>("h00") + node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2108:48] + node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2108:93] + node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2108:100] + node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2108:71] + node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2110:34] + node _T_744 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2110:86] + node _T_745 = mux(_T_743, io.dec_csr_wrdata_r, _T_744) @[dec_tlu_ctl.scala 2110:21] + node _T_746 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2113:78] + node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2113:111] + reg _T_748 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_747 : @[Reg.scala 28:19] + _T_748 <= _T_745 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_748 <= _T_758 @[dec_tlu_ctl.scala 2131:13] - node _T_759 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] - dicad1 <= _T_759 @[dec_tlu_ctl.scala 2132:9] - node _T_760 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2154:69] - node _T_761 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2154:83] - node _T_762 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2154:97] - node _T_763 = cat(_T_760, _T_761) @[Cat.scala 29:58] - node _T_764 = cat(_T_763, _T_762) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_764 @[dec_tlu_ctl.scala 2154:56] - io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2157:41] - node _T_765 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2159:52] - node _T_766 = and(_T_765, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2159:75] - node _T_767 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2159:98] - node _T_768 = and(_T_766, _T_767) @[dec_tlu_ctl.scala 2159:96] - node _T_769 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2159:142] - node _T_770 = eq(_T_769, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:149] - node icache_rd_valid = and(_T_768, _T_770) @[dec_tlu_ctl.scala 2159:120] - node _T_771 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2160:52] - node _T_772 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2160:97] - node _T_773 = eq(_T_772, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:104] - node icache_wr_valid = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2160:75] - reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2162:58] - icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2162:58] - reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2163:58] - icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2163:58] - io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2165:41] - io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2166:41] - node _T_774 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2174:62] - node _T_775 = eq(_T_774, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2174:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_775) @[dec_tlu_ctl.scala 2174:40] - node _T_776 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2175:32] - node _T_777 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2175:59] - node mtsel_ns = mux(_T_776, _T_777, mtsel) @[dec_tlu_ctl.scala 2175:20] - reg _T_778 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2177:43] - _T_778 <= mtsel_ns @[dec_tlu_ctl.scala 2177:43] - mtsel <= _T_778 @[dec_tlu_ctl.scala 2177:8] - node _T_779 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2212:38] - node _T_780 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2212:64] - node _T_781 = not(_T_780) @[dec_tlu_ctl.scala 2212:44] - node tdata_load = and(_T_779, _T_781) @[dec_tlu_ctl.scala 2212:42] - node _T_782 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2214:40] - node _T_783 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2214:66] - node _T_784 = not(_T_783) @[dec_tlu_ctl.scala 2214:46] - node tdata_opcode = and(_T_782, _T_784) @[dec_tlu_ctl.scala 2214:44] - node _T_785 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2216:41] - node _T_786 = and(_T_785, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2216:46] - node _T_787 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2216:90] - node tdata_action = and(_T_786, _T_787) @[dec_tlu_ctl.scala 2216:69] - node _T_788 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2218:47] - node _T_789 = and(_T_788, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:52] - node _T_790 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2218:94] - node _T_791 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2218:136] - node _T_792 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2219:43] - node _T_793 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2219:83] - node _T_794 = cat(_T_793, tdata_load) @[Cat.scala 29:58] - node _T_795 = cat(_T_792, tdata_opcode) @[Cat.scala 29:58] - node _T_796 = cat(_T_795, _T_794) @[Cat.scala 29:58] - node _T_797 = cat(tdata_action, _T_791) @[Cat.scala 29:58] - node _T_798 = cat(_T_789, _T_790) @[Cat.scala 29:58] - node _T_799 = cat(_T_798, _T_797) @[Cat.scala 29:58] - node tdata_wrdata_r = cat(_T_799, _T_796) @[Cat.scala 29:58] - node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2222:70] - node _T_803 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2222:121] - node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2222:112] - node _T_805 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2222:138] - node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2222:135] - node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2222:70] - node _T_812 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2222:121] - node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2222:112] - node _T_814 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2222:138] - node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2222:135] - node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2222:70] - node _T_821 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2222:121] - node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2222:112] - node _T_823 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2222:138] - node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2222:135] - node _T_827 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_828 = eq(_T_827, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_829 = and(io.dec_csr_wen_r_mod, _T_828) @[dec_tlu_ctl.scala 2222:70] - node _T_830 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2222:121] - node _T_831 = and(_T_829, _T_830) @[dec_tlu_ctl.scala 2222:112] - node _T_832 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_833 = not(_T_832) @[dec_tlu_ctl.scala 2222:138] - node _T_834 = or(_T_833, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_835 = and(_T_831, _T_834) @[dec_tlu_ctl.scala 2222:135] - wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[0] <= _T_808 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[1] <= _T_817 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[2] <= _T_826 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[3] <= _T_835 @[dec_tlu_ctl.scala 2222:42] - node _T_836 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_837 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_838 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2223:135] - node _T_839 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2223:139] - node _T_841 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58] - node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58] - node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2223:49] - node _T_845 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_846 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_847 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2223:135] - node _T_848 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2223:139] - node _T_850 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58] - node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58] - node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2223:49] - node _T_854 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_855 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_856 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2223:135] - node _T_857 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2223:139] - node _T_859 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58] - node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58] - node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2223:49] - node _T_863 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_864 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_865 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2223:135] - node _T_866 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_867 = or(_T_865, _T_866) @[dec_tlu_ctl.scala 2223:139] - node _T_868 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_869 = cat(_T_864, _T_867) @[Cat.scala 29:58] - node _T_870 = cat(_T_869, _T_868) @[Cat.scala 29:58] - node _T_871 = mux(_T_863, tdata_wrdata_r, _T_870) @[dec_tlu_ctl.scala 2223:49] - wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[0] <= _T_844 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[1] <= _T_853 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[2] <= _T_862 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[3] <= _T_871 @[dec_tlu_ctl.scala 2223:40] - reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_872 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[0] <= _T_872 @[dec_tlu_ctl.scala 2225:39] - reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_873 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[1] <= _T_873 @[dec_tlu_ctl.scala 2225:39] - reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_874 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[2] <= _T_874 @[dec_tlu_ctl.scala 2225:39] - reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_875 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[3] <= _T_875 @[dec_tlu_ctl.scala 2225:39] - node _T_876 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2228:58] - node _T_877 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_878 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_879 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_880 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_881 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_882 = cat(UInt<3>("h00"), _T_881) @[Cat.scala 29:58] - node _T_883 = cat(_T_879, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_884 = cat(_T_883, _T_880) @[Cat.scala 29:58] - node _T_885 = cat(_T_884, _T_882) @[Cat.scala 29:58] - node _T_886 = cat(_T_878, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_887 = cat(UInt<4>("h02"), _T_877) @[Cat.scala 29:58] - node _T_888 = cat(_T_887, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_889 = cat(_T_888, _T_886) @[Cat.scala 29:58] - node _T_890 = cat(_T_889, _T_885) @[Cat.scala 29:58] - node _T_891 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2228:58] - node _T_892 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_893 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_894 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_895 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_896 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_897 = cat(UInt<3>("h00"), _T_896) @[Cat.scala 29:58] - node _T_898 = cat(_T_894, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_899 = cat(_T_898, _T_895) @[Cat.scala 29:58] - node _T_900 = cat(_T_899, _T_897) @[Cat.scala 29:58] - node _T_901 = cat(_T_893, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_902 = cat(UInt<4>("h02"), _T_892) @[Cat.scala 29:58] - node _T_903 = cat(_T_902, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_904 = cat(_T_903, _T_901) @[Cat.scala 29:58] - node _T_905 = cat(_T_904, _T_900) @[Cat.scala 29:58] - node _T_906 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2228:58] - node _T_907 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_908 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_909 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_910 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_911 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_912 = cat(UInt<3>("h00"), _T_911) @[Cat.scala 29:58] - node _T_913 = cat(_T_909, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_914 = cat(_T_913, _T_910) @[Cat.scala 29:58] - node _T_915 = cat(_T_914, _T_912) @[Cat.scala 29:58] - node _T_916 = cat(_T_908, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_917 = cat(UInt<4>("h02"), _T_907) @[Cat.scala 29:58] - node _T_918 = cat(_T_917, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_919 = cat(_T_918, _T_916) @[Cat.scala 29:58] - node _T_920 = cat(_T_919, _T_915) @[Cat.scala 29:58] - node _T_921 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2228:58] - node _T_922 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_923 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_924 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_925 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_926 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_927 = cat(UInt<3>("h00"), _T_926) @[Cat.scala 29:58] - node _T_928 = cat(_T_924, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_929 = cat(_T_928, _T_925) @[Cat.scala 29:58] - node _T_930 = cat(_T_929, _T_927) @[Cat.scala 29:58] - node _T_931 = cat(_T_923, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_932 = cat(UInt<4>("h02"), _T_922) @[Cat.scala 29:58] - node _T_933 = cat(_T_932, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] - node _T_935 = cat(_T_934, _T_930) @[Cat.scala 29:58] - node _T_936 = mux(_T_876, _T_890, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_937 = mux(_T_891, _T_905, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_938 = mux(_T_906, _T_920, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_939 = mux(_T_921, _T_935, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_940 = or(_T_936, _T_937) @[Mux.scala 27:72] - node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] - node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72] + _T_738 <= _T_748 @[dec_tlu_ctl.scala 2113:13] + node _T_749 = cat(UInt<25>("h00"), _T_738) @[Cat.scala 29:58] + dicad1 <= _T_749 @[dec_tlu_ctl.scala 2114:9] + node _T_750 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2136:69] + node _T_751 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2136:83] + node _T_752 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2136:97] + node _T_753 = cat(_T_750, _T_751) @[Cat.scala 29:58] + node _T_754 = cat(_T_753, _T_752) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_754 @[dec_tlu_ctl.scala 2136:56] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2139:41] + node _T_755 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2141:52] + node _T_756 = and(_T_755, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2141:75] + node _T_757 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2141:98] + node _T_758 = and(_T_756, _T_757) @[dec_tlu_ctl.scala 2141:96] + node _T_759 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2141:142] + node _T_760 = eq(_T_759, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2141:149] + node icache_rd_valid = and(_T_758, _T_760) @[dec_tlu_ctl.scala 2141:120] + node _T_761 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2142:52] + node _T_762 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2142:97] + node _T_763 = eq(_T_762, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2142:104] + node icache_wr_valid = and(_T_761, _T_763) @[dec_tlu_ctl.scala 2142:75] + reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2144:58] + icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2144:58] + reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2145:58] + icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2145:58] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2147:41] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2148:41] + node _T_764 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2156:62] + node _T_765 = eq(_T_764, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2156:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_765) @[dec_tlu_ctl.scala 2156:40] + node _T_766 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2157:32] + node _T_767 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2157:59] + node mtsel_ns = mux(_T_766, _T_767, mtsel) @[dec_tlu_ctl.scala 2157:20] + reg _T_768 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2159:43] + _T_768 <= mtsel_ns @[dec_tlu_ctl.scala 2159:43] + mtsel <= _T_768 @[dec_tlu_ctl.scala 2159:8] + node _T_769 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2194:38] + node _T_770 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2194:64] + node _T_771 = not(_T_770) @[dec_tlu_ctl.scala 2194:44] + node tdata_load = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2194:42] + node _T_772 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2196:40] + node _T_773 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2196:66] + node _T_774 = not(_T_773) @[dec_tlu_ctl.scala 2196:46] + node tdata_opcode = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2196:44] + node _T_775 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2198:41] + node _T_776 = and(_T_775, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2198:46] + node _T_777 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2198:90] + node tdata_action = and(_T_776, _T_777) @[dec_tlu_ctl.scala 2198:69] + node _T_778 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2200:47] + node _T_779 = and(_T_778, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2200:52] + node _T_780 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2200:94] + node _T_781 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2200:136] + node _T_782 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2201:43] + node _T_783 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2201:83] + node _T_784 = cat(_T_783, tdata_load) @[Cat.scala 29:58] + node _T_785 = cat(_T_782, tdata_opcode) @[Cat.scala 29:58] + node _T_786 = cat(_T_785, _T_784) @[Cat.scala 29:58] + node _T_787 = cat(tdata_action, _T_781) @[Cat.scala 29:58] + node _T_788 = cat(_T_779, _T_780) @[Cat.scala 29:58] + node _T_789 = cat(_T_788, _T_787) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_789, _T_786) @[Cat.scala 29:58] + node _T_790 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_791 = eq(_T_790, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_792 = and(io.dec_csr_wen_r_mod, _T_791) @[dec_tlu_ctl.scala 2204:70] + node _T_793 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2204:121] + node _T_794 = and(_T_792, _T_793) @[dec_tlu_ctl.scala 2204:112] + node _T_795 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_796 = not(_T_795) @[dec_tlu_ctl.scala 2204:138] + node _T_797 = or(_T_796, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_798 = and(_T_794, _T_797) @[dec_tlu_ctl.scala 2204:135] + node _T_799 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_800 = eq(_T_799, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_801 = and(io.dec_csr_wen_r_mod, _T_800) @[dec_tlu_ctl.scala 2204:70] + node _T_802 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2204:121] + node _T_803 = and(_T_801, _T_802) @[dec_tlu_ctl.scala 2204:112] + node _T_804 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_805 = not(_T_804) @[dec_tlu_ctl.scala 2204:138] + node _T_806 = or(_T_805, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_807 = and(_T_803, _T_806) @[dec_tlu_ctl.scala 2204:135] + node _T_808 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_809 = eq(_T_808, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_810 = and(io.dec_csr_wen_r_mod, _T_809) @[dec_tlu_ctl.scala 2204:70] + node _T_811 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2204:121] + node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 2204:112] + node _T_813 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_814 = not(_T_813) @[dec_tlu_ctl.scala 2204:138] + node _T_815 = or(_T_814, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_816 = and(_T_812, _T_815) @[dec_tlu_ctl.scala 2204:135] + node _T_817 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_818 = eq(_T_817, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_819 = and(io.dec_csr_wen_r_mod, _T_818) @[dec_tlu_ctl.scala 2204:70] + node _T_820 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2204:121] + node _T_821 = and(_T_819, _T_820) @[dec_tlu_ctl.scala 2204:112] + node _T_822 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_823 = not(_T_822) @[dec_tlu_ctl.scala 2204:138] + node _T_824 = or(_T_823, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_825 = and(_T_821, _T_824) @[dec_tlu_ctl.scala 2204:135] + wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2204:42] + wr_mtdata1_t_r[0] <= _T_798 @[dec_tlu_ctl.scala 2204:42] + wr_mtdata1_t_r[1] <= _T_807 @[dec_tlu_ctl.scala 2204:42] + wr_mtdata1_t_r[2] <= _T_816 @[dec_tlu_ctl.scala 2204:42] + wr_mtdata1_t_r[3] <= _T_825 @[dec_tlu_ctl.scala 2204:42] + node _T_826 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_827 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_828 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2205:135] + node _T_829 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_830 = or(_T_828, _T_829) @[dec_tlu_ctl.scala 2205:139] + node _T_831 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_832 = cat(_T_827, _T_830) @[Cat.scala 29:58] + node _T_833 = cat(_T_832, _T_831) @[Cat.scala 29:58] + node _T_834 = mux(_T_826, tdata_wrdata_r, _T_833) @[dec_tlu_ctl.scala 2205:49] + node _T_835 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_836 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_837 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2205:135] + node _T_838 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_839 = or(_T_837, _T_838) @[dec_tlu_ctl.scala 2205:139] + node _T_840 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_841 = cat(_T_836, _T_839) @[Cat.scala 29:58] + node _T_842 = cat(_T_841, _T_840) @[Cat.scala 29:58] + node _T_843 = mux(_T_835, tdata_wrdata_r, _T_842) @[dec_tlu_ctl.scala 2205:49] + node _T_844 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_845 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_846 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2205:135] + node _T_847 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_848 = or(_T_846, _T_847) @[dec_tlu_ctl.scala 2205:139] + node _T_849 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_850 = cat(_T_845, _T_848) @[Cat.scala 29:58] + node _T_851 = cat(_T_850, _T_849) @[Cat.scala 29:58] + node _T_852 = mux(_T_844, tdata_wrdata_r, _T_851) @[dec_tlu_ctl.scala 2205:49] + node _T_853 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_854 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_855 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2205:135] + node _T_856 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_857 = or(_T_855, _T_856) @[dec_tlu_ctl.scala 2205:139] + node _T_858 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_859 = cat(_T_854, _T_857) @[Cat.scala 29:58] + node _T_860 = cat(_T_859, _T_858) @[Cat.scala 29:58] + node _T_861 = mux(_T_853, tdata_wrdata_r, _T_860) @[dec_tlu_ctl.scala 2205:49] + wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2205:40] + mtdata1_t_ns[0] <= _T_834 @[dec_tlu_ctl.scala 2205:40] + mtdata1_t_ns[1] <= _T_843 @[dec_tlu_ctl.scala 2205:40] + mtdata1_t_ns[2] <= _T_852 @[dec_tlu_ctl.scala 2205:40] + mtdata1_t_ns[3] <= _T_861 @[dec_tlu_ctl.scala 2205:40] + reg _T_862 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_862 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[0] <= _T_862 @[dec_tlu_ctl.scala 2207:39] + reg _T_863 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_863 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[1] <= _T_863 @[dec_tlu_ctl.scala 2207:39] + reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_864 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[2] <= _T_864 @[dec_tlu_ctl.scala 2207:39] + reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_865 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[3] <= _T_865 @[dec_tlu_ctl.scala 2207:39] + node _T_866 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2210:58] + node _T_867 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_868 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_869 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_870 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_871 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_872 = cat(UInt<3>("h00"), _T_871) @[Cat.scala 29:58] + node _T_873 = cat(_T_869, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_874 = cat(_T_873, _T_870) @[Cat.scala 29:58] + node _T_875 = cat(_T_874, _T_872) @[Cat.scala 29:58] + node _T_876 = cat(_T_868, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_877 = cat(UInt<4>("h02"), _T_867) @[Cat.scala 29:58] + node _T_878 = cat(_T_877, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_879 = cat(_T_878, _T_876) @[Cat.scala 29:58] + node _T_880 = cat(_T_879, _T_875) @[Cat.scala 29:58] + node _T_881 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2210:58] + node _T_882 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_883 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_884 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_885 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_886 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_887 = cat(UInt<3>("h00"), _T_886) @[Cat.scala 29:58] + node _T_888 = cat(_T_884, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_885) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_887) @[Cat.scala 29:58] + node _T_891 = cat(_T_883, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_892 = cat(UInt<4>("h02"), _T_882) @[Cat.scala 29:58] + node _T_893 = cat(_T_892, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_894 = cat(_T_893, _T_891) @[Cat.scala 29:58] + node _T_895 = cat(_T_894, _T_890) @[Cat.scala 29:58] + node _T_896 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2210:58] + node _T_897 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_898 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_899 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_900 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_901 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_902 = cat(UInt<3>("h00"), _T_901) @[Cat.scala 29:58] + node _T_903 = cat(_T_899, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_900) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_902) @[Cat.scala 29:58] + node _T_906 = cat(_T_898, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_907 = cat(UInt<4>("h02"), _T_897) @[Cat.scala 29:58] + node _T_908 = cat(_T_907, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_909 = cat(_T_908, _T_906) @[Cat.scala 29:58] + node _T_910 = cat(_T_909, _T_905) @[Cat.scala 29:58] + node _T_911 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2210:58] + node _T_912 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_913 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_914 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_915 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_916 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_917 = cat(UInt<3>("h00"), _T_916) @[Cat.scala 29:58] + node _T_918 = cat(_T_914, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, _T_915) @[Cat.scala 29:58] + node _T_920 = cat(_T_919, _T_917) @[Cat.scala 29:58] + node _T_921 = cat(_T_913, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_922 = cat(UInt<4>("h02"), _T_912) @[Cat.scala 29:58] + node _T_923 = cat(_T_922, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_924 = cat(_T_923, _T_921) @[Cat.scala 29:58] + node _T_925 = cat(_T_924, _T_920) @[Cat.scala 29:58] + node _T_926 = mux(_T_866, _T_880, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_927 = mux(_T_881, _T_895, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_928 = mux(_T_896, _T_910, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_929 = mux(_T_911, _T_925, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_930 = or(_T_926, _T_927) @[Mux.scala 27:72] + node _T_931 = or(_T_930, _T_928) @[Mux.scala 27:72] + node _T_932 = or(_T_931, _T_929) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata1_tsel_out <= _T_942 @[Mux.scala 27:72] - node _T_943 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[0].select <= _T_943 @[dec_tlu_ctl.scala 2230:40] - node _T_944 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[0].match_pkt <= _T_944 @[dec_tlu_ctl.scala 2231:43] - node _T_945 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[0].store <= _T_945 @[dec_tlu_ctl.scala 2232:40] - node _T_946 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[0].load <= _T_946 @[dec_tlu_ctl.scala 2233:40] - node _T_947 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[0].execute <= _T_947 @[dec_tlu_ctl.scala 2234:40] - node _T_948 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[0].m <= _T_948 @[dec_tlu_ctl.scala 2235:40] - node _T_949 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[1].select <= _T_949 @[dec_tlu_ctl.scala 2230:40] - node _T_950 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[1].match_pkt <= _T_950 @[dec_tlu_ctl.scala 2231:43] - node _T_951 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[1].store <= _T_951 @[dec_tlu_ctl.scala 2232:40] - node _T_952 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[1].load <= _T_952 @[dec_tlu_ctl.scala 2233:40] - node _T_953 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[1].execute <= _T_953 @[dec_tlu_ctl.scala 2234:40] - node _T_954 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[1].m <= _T_954 @[dec_tlu_ctl.scala 2235:40] - node _T_955 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[2].select <= _T_955 @[dec_tlu_ctl.scala 2230:40] - node _T_956 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[2].match_pkt <= _T_956 @[dec_tlu_ctl.scala 2231:43] - node _T_957 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[2].store <= _T_957 @[dec_tlu_ctl.scala 2232:40] - node _T_958 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[2].load <= _T_958 @[dec_tlu_ctl.scala 2233:40] - node _T_959 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[2].execute <= _T_959 @[dec_tlu_ctl.scala 2234:40] - node _T_960 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[2].m <= _T_960 @[dec_tlu_ctl.scala 2235:40] - node _T_961 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[3].select <= _T_961 @[dec_tlu_ctl.scala 2230:40] - node _T_962 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[3].match_pkt <= _T_962 @[dec_tlu_ctl.scala 2231:43] - node _T_963 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[3].store <= _T_963 @[dec_tlu_ctl.scala 2232:40] - node _T_964 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[3].load <= _T_964 @[dec_tlu_ctl.scala 2233:40] - node _T_965 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[3].execute <= _T_965 @[dec_tlu_ctl.scala 2234:40] - node _T_966 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[3].m <= _T_966 @[dec_tlu_ctl.scala 2235:40] - node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2242:69] - node _T_970 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2242:120] - node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2242:111] - node _T_972 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2242:137] - node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2242:134] - node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2242:69] - node _T_979 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2242:120] - node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2242:111] - node _T_981 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2242:137] - node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2242:134] - node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2242:69] - node _T_988 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2242:120] - node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2242:111] - node _T_990 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2242:137] - node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2242:134] - node _T_994 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_995 = eq(_T_994, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_996 = and(io.dec_csr_wen_r_mod, _T_995) @[dec_tlu_ctl.scala 2242:69] - node _T_997 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2242:120] - node _T_998 = and(_T_996, _T_997) @[dec_tlu_ctl.scala 2242:111] - node _T_999 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_1000 = not(_T_999) @[dec_tlu_ctl.scala 2242:137] - node _T_1001 = or(_T_1000, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_1002 = and(_T_998, _T_1001) @[dec_tlu_ctl.scala 2242:134] - wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[0] <= _T_975 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[1] <= _T_984 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[2] <= _T_993 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[3] <= _T_1002 @[dec_tlu_ctl.scala 2242:42] - node _T_1003 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2243:84] + mtdata1_tsel_out <= _T_932 @[Mux.scala 27:72] + node _T_933 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[0].select <= _T_933 @[dec_tlu_ctl.scala 2212:40] + node _T_934 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[0].match_pkt <= _T_934 @[dec_tlu_ctl.scala 2213:43] + node _T_935 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[0].store <= _T_935 @[dec_tlu_ctl.scala 2214:40] + node _T_936 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[0].load <= _T_936 @[dec_tlu_ctl.scala 2215:40] + node _T_937 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[0].execute <= _T_937 @[dec_tlu_ctl.scala 2216:40] + node _T_938 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[0].m <= _T_938 @[dec_tlu_ctl.scala 2217:40] + node _T_939 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[1].select <= _T_939 @[dec_tlu_ctl.scala 2212:40] + node _T_940 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[1].match_pkt <= _T_940 @[dec_tlu_ctl.scala 2213:43] + node _T_941 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[1].store <= _T_941 @[dec_tlu_ctl.scala 2214:40] + node _T_942 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[1].load <= _T_942 @[dec_tlu_ctl.scala 2215:40] + node _T_943 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[1].execute <= _T_943 @[dec_tlu_ctl.scala 2216:40] + node _T_944 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[1].m <= _T_944 @[dec_tlu_ctl.scala 2217:40] + node _T_945 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[2].select <= _T_945 @[dec_tlu_ctl.scala 2212:40] + node _T_946 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[2].match_pkt <= _T_946 @[dec_tlu_ctl.scala 2213:43] + node _T_947 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[2].store <= _T_947 @[dec_tlu_ctl.scala 2214:40] + node _T_948 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[2].load <= _T_948 @[dec_tlu_ctl.scala 2215:40] + node _T_949 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[2].execute <= _T_949 @[dec_tlu_ctl.scala 2216:40] + node _T_950 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[2].m <= _T_950 @[dec_tlu_ctl.scala 2217:40] + node _T_951 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[3].select <= _T_951 @[dec_tlu_ctl.scala 2212:40] + node _T_952 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[3].match_pkt <= _T_952 @[dec_tlu_ctl.scala 2213:43] + node _T_953 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[3].store <= _T_953 @[dec_tlu_ctl.scala 2214:40] + node _T_954 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[3].load <= _T_954 @[dec_tlu_ctl.scala 2215:40] + node _T_955 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[3].execute <= _T_955 @[dec_tlu_ctl.scala 2216:40] + node _T_956 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[3].m <= _T_956 @[dec_tlu_ctl.scala 2217:40] + node _T_957 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_958 = eq(_T_957, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_959 = and(io.dec_csr_wen_r_mod, _T_958) @[dec_tlu_ctl.scala 2224:69] + node _T_960 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2224:120] + node _T_961 = and(_T_959, _T_960) @[dec_tlu_ctl.scala 2224:111] + node _T_962 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_963 = not(_T_962) @[dec_tlu_ctl.scala 2224:137] + node _T_964 = or(_T_963, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_965 = and(_T_961, _T_964) @[dec_tlu_ctl.scala 2224:134] + node _T_966 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_967 = eq(_T_966, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_968 = and(io.dec_csr_wen_r_mod, _T_967) @[dec_tlu_ctl.scala 2224:69] + node _T_969 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2224:120] + node _T_970 = and(_T_968, _T_969) @[dec_tlu_ctl.scala 2224:111] + node _T_971 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_972 = not(_T_971) @[dec_tlu_ctl.scala 2224:137] + node _T_973 = or(_T_972, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_974 = and(_T_970, _T_973) @[dec_tlu_ctl.scala 2224:134] + node _T_975 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_976 = eq(_T_975, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_977 = and(io.dec_csr_wen_r_mod, _T_976) @[dec_tlu_ctl.scala 2224:69] + node _T_978 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2224:120] + node _T_979 = and(_T_977, _T_978) @[dec_tlu_ctl.scala 2224:111] + node _T_980 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_981 = not(_T_980) @[dec_tlu_ctl.scala 2224:137] + node _T_982 = or(_T_981, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_983 = and(_T_979, _T_982) @[dec_tlu_ctl.scala 2224:134] + node _T_984 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_985 = eq(_T_984, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_986 = and(io.dec_csr_wen_r_mod, _T_985) @[dec_tlu_ctl.scala 2224:69] + node _T_987 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2224:120] + node _T_988 = and(_T_986, _T_987) @[dec_tlu_ctl.scala 2224:111] + node _T_989 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_990 = not(_T_989) @[dec_tlu_ctl.scala 2224:137] + node _T_991 = or(_T_990, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_992 = and(_T_988, _T_991) @[dec_tlu_ctl.scala 2224:134] + wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2224:42] + wr_mtdata2_t_r[0] <= _T_965 @[dec_tlu_ctl.scala 2224:42] + wr_mtdata2_t_r[1] <= _T_974 @[dec_tlu_ctl.scala 2224:42] + wr_mtdata2_t_r[2] <= _T_983 @[dec_tlu_ctl.scala 2224:42] + wr_mtdata2_t_r[3] <= _T_992 @[dec_tlu_ctl.scala 2224:42] + node _T_993 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_22.io.en <= _T_1003 @[lib.scala 371:17] + rvclkhdr_22.io.en <= _T_993 @[lib.scala 371:17] rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1004 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1004 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[0] <= _T_1004 @[dec_tlu_ctl.scala 2243:36] - node _T_1005 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2243:84] + reg _T_994 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_994 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[0] <= _T_994 @[dec_tlu_ctl.scala 2225:36] + node _T_995 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_23.io.en <= _T_1005 @[lib.scala 371:17] + rvclkhdr_23.io.en <= _T_995 @[lib.scala 371:17] rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1006 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1006 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[1] <= _T_1006 @[dec_tlu_ctl.scala 2243:36] - node _T_1007 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2243:84] + reg _T_996 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_996 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[1] <= _T_996 @[dec_tlu_ctl.scala 2225:36] + node _T_997 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_24.io.en <= _T_1007 @[lib.scala 371:17] + rvclkhdr_24.io.en <= _T_997 @[lib.scala 371:17] rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1008 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1008 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[2] <= _T_1008 @[dec_tlu_ctl.scala 2243:36] - node _T_1009 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2243:84] + reg _T_998 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_998 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[2] <= _T_998 @[dec_tlu_ctl.scala 2225:36] + node _T_999 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_25.io.en <= _T_1009 @[lib.scala 371:17] + rvclkhdr_25.io.en <= _T_999 @[lib.scala 371:17] rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1010 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1010 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[3] <= _T_1010 @[dec_tlu_ctl.scala 2243:36] - node _T_1011 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2247:57] - node _T_1012 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2247:57] - node _T_1013 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2247:57] - node _T_1014 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2247:57] - node _T_1015 = mux(_T_1011, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1016 = mux(_T_1012, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1017 = mux(_T_1013, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1018 = mux(_T_1014, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1019 = or(_T_1015, _T_1016) @[Mux.scala 27:72] - node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] - node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72] + reg _T_1000 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1000 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[3] <= _T_1000 @[dec_tlu_ctl.scala 2225:36] + node _T_1001 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:57] + node _T_1002 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:57] + node _T_1003 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:57] + node _T_1004 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:57] + node _T_1005 = mux(_T_1001, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1006 = mux(_T_1002, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1007 = mux(_T_1003, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1008 = mux(_T_1004, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1009 = or(_T_1005, _T_1006) @[Mux.scala 27:72] + node _T_1010 = or(_T_1009, _T_1007) @[Mux.scala 27:72] + node _T_1011 = or(_T_1010, _T_1008) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata2_tsel_out <= _T_1021 @[Mux.scala 27:72] - io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2248:51] - io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2248:51] - io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2248:51] - io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2248:51] - mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2258:15] - mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2259:15] - mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2260:15] - mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2261:15] - node _T_1022 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] - node _T_1023 = mux(_T_1022, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1023) @[dec_tlu_ctl.scala 2267:59] - wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2268:24] - wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2269:27] - node _T_1024 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2273:38] - node _T_1025 = not(_T_1024) @[dec_tlu_ctl.scala 2273:24] - node _T_1026 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1028 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1030 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1031 = bits(_T_1030, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1032 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1034 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1035 = and(io.tlu_i0_commit_cmt, _T_1034) @[dec_tlu_ctl.scala 2277:94] - node _T_1036 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1037 = bits(_T_1036, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1038 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1039 = and(io.tlu_i0_commit_cmt, _T_1038) @[dec_tlu_ctl.scala 2278:94] - node _T_1040 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1041 = and(_T_1039, _T_1040) @[dec_tlu_ctl.scala 2278:115] - node _T_1042 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1044 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1045 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1046 = and(_T_1044, _T_1045) @[dec_tlu_ctl.scala 2279:115] - node _T_1047 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1049 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1051 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1053 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1058 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1062 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1063 = bits(_T_1062, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1064 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1068 = and(_T_1067, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1069 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1072 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2288:101] - node _T_1074 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1077 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1080 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1083 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1086 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1089 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1092 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1095 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1096 = bits(_T_1095, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1097 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1098 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1100 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1101 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1103 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1105 = or(_T_1103, _T_1104) @[dec_tlu_ctl.scala 2298:101] - node _T_1106 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1108 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1111 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1112 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1114 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1115 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1117 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1119 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1121 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1123 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1125 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1127 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1129 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1131 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1132 = or(_T_1131, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1133 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1135 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1136 = or(_T_1135, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1137 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1139 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1141 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1143 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1144 = and(_T_1143, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1149 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1151 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1153 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1155 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1157 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1159 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1160 = bits(_T_1159, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1161 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1162 = bits(_T_1161, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1163 = not(_T_1162) @[dec_tlu_ctl.scala 2321:73] - node _T_1164 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1166 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1168 = not(_T_1167) @[dec_tlu_ctl.scala 2322:73] - node _T_1169 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1170 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1171 = and(_T_1169, _T_1170) @[dec_tlu_ctl.scala 2322:113] - node _T_1172 = orr(_T_1171) @[dec_tlu_ctl.scala 2322:125] - node _T_1173 = and(_T_1168, _T_1172) @[dec_tlu_ctl.scala 2322:98] - node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1186 = bits(_T_1185, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1188 = bits(_T_1187, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1190 = bits(_T_1189, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1192 = bits(_T_1191, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1193 = mux(_T_1027, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1194 = mux(_T_1029, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1195 = mux(_T_1031, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1196 = mux(_T_1033, _T_1035, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1197 = mux(_T_1037, _T_1041, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1198 = mux(_T_1043, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1199 = mux(_T_1048, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1200 = mux(_T_1050, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1201 = mux(_T_1052, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1202 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1203 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1204 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1205 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1206 = mux(_T_1066, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1207 = mux(_T_1070, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1208 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1209 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1210 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1211 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1212 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1213 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1214 = mux(_T_1093, _T_1094, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1215 = mux(_T_1096, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1216 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1217 = mux(_T_1102, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1218 = mux(_T_1107, _T_1108, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1219 = mux(_T_1110, _T_1111, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1220 = mux(_T_1113, _T_1114, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1221 = mux(_T_1116, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1222 = mux(_T_1118, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1223 = mux(_T_1120, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1224 = mux(_T_1122, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1225 = mux(_T_1124, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1226 = mux(_T_1126, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1227 = mux(_T_1128, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1228 = mux(_T_1130, _T_1132, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1229 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1230 = mux(_T_1138, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1231 = mux(_T_1140, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1232 = mux(_T_1142, _T_1144, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1233 = mux(_T_1146, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1234 = mux(_T_1148, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1235 = mux(_T_1150, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1236 = mux(_T_1152, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1237 = mux(_T_1154, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1238 = mux(_T_1156, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1239 = mux(_T_1158, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1240 = mux(_T_1160, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1241 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1242 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1243 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1244 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1245 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1246 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1247 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1248 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1249 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1250 = or(_T_1193, _T_1194) @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1011 @[Mux.scala 27:72] + io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2230:51] + io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2230:51] + io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2230:51] + io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2230:51] + mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2240:15] + mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2241:15] + mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2242:15] + mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2243:15] + node _T_1012 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1013 = mux(_T_1012, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1013) @[dec_tlu_ctl.scala 2249:59] + wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2250:24] + wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2251:27] + node _T_1014 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2255:38] + node _T_1015 = not(_T_1014) @[dec_tlu_ctl.scala 2255:24] + node _T_1016 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1017 = bits(_T_1016, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1018 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1019 = bits(_T_1018, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1020 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1021 = bits(_T_1020, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1022 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1023 = bits(_T_1022, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1024 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1025 = and(io.tlu_i0_commit_cmt, _T_1024) @[dec_tlu_ctl.scala 2259:94] + node _T_1026 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1028 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1029 = and(io.tlu_i0_commit_cmt, _T_1028) @[dec_tlu_ctl.scala 2260:94] + node _T_1030 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1031 = and(_T_1029, _T_1030) @[dec_tlu_ctl.scala 2260:115] + node _T_1032 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1034 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1036 = and(_T_1034, _T_1035) @[dec_tlu_ctl.scala 2261:115] + node _T_1037 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1039 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1040 = bits(_T_1039, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1041 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1042 = bits(_T_1041, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1043 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1045 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1046 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1047 = bits(_T_1046, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1048 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1049 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1051 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1052 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1054 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1055 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1056 = bits(_T_1055, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1057 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1058 = and(_T_1057, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1062 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1063 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2270:101] + node _T_1064 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1065 = bits(_T_1064, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1066 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1067 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1068 = bits(_T_1067, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1069 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1070 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1073 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1074 = bits(_T_1073, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1075 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1076 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1077 = bits(_T_1076, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1078 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1079 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1080 = bits(_T_1079, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1081 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1082 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1083 = bits(_T_1082, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1084 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1085 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1086 = bits(_T_1085, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1087 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1088 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1089 = bits(_T_1088, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1090 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1091 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1092 = bits(_T_1091, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1093 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1095 = or(_T_1093, _T_1094) @[dec_tlu_ctl.scala 2280:101] + node _T_1096 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1098 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1099 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1101 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1102 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1104 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1105 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1106 = bits(_T_1105, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1107 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1111 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1112 = bits(_T_1111, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1113 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1115 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1117 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1119 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1121 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1122 = or(_T_1121, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1123 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1125 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1126 = or(_T_1125, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1127 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1129 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1131 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1132 = bits(_T_1131, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1133 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1134 = and(_T_1133, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1135 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1136 = bits(_T_1135, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1137 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1139 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1141 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1143 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_1144 = bits(_T_1143, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1147 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1149 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1151 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_1153 = not(_T_1152) @[dec_tlu_ctl.scala 2303:73] + node _T_1154 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1156 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_1158 = not(_T_1157) @[dec_tlu_ctl.scala 2304:73] + node _T_1159 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_1160 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_1161 = and(_T_1159, _T_1160) @[dec_tlu_ctl.scala 2304:113] + node _T_1162 = orr(_T_1161) @[dec_tlu_ctl.scala 2304:125] + node _T_1163 = and(_T_1158, _T_1162) @[dec_tlu_ctl.scala 2304:98] + node _T_1164 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1166 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_1167 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1169 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_1170 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_1171 = bits(_T_1170, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1172 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_1173 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_1174 = bits(_T_1173, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1175 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1177 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1179 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_1180 = bits(_T_1179, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1181 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1183 = mux(_T_1017, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1184 = mux(_T_1019, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1185 = mux(_T_1021, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1186 = mux(_T_1023, _T_1025, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1187 = mux(_T_1027, _T_1031, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1188 = mux(_T_1033, _T_1036, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1189 = mux(_T_1038, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1190 = mux(_T_1040, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1191 = mux(_T_1042, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1192 = mux(_T_1044, _T_1045, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1193 = mux(_T_1047, _T_1048, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1194 = mux(_T_1050, _T_1051, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1053, _T_1054, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1056, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1060, _T_1063, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1065, _T_1066, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1068, _T_1069, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1074, _T_1075, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1077, _T_1078, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1080, _T_1081, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1083, _T_1084, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1086, _T_1087, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1089, _T_1090, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1092, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1103, _T_1104, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1106, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1108, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1110, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1112, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1114, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1116, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1118, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1120, _T_1122, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1124, _T_1126, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1128, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1130, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1132, _T_1134, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1136, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1138, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1140, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1142, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1144, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1146, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1148, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1150, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1155, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1165, _T_1166, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1168, _T_1169, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1174, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1176, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1178, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1180, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1182, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = or(_T_1183, _T_1184) @[Mux.scala 27:72] + node _T_1241 = or(_T_1240, _T_1185) @[Mux.scala 27:72] + node _T_1242 = or(_T_1241, _T_1186) @[Mux.scala 27:72] + node _T_1243 = or(_T_1242, _T_1187) @[Mux.scala 27:72] + node _T_1244 = or(_T_1243, _T_1188) @[Mux.scala 27:72] + node _T_1245 = or(_T_1244, _T_1189) @[Mux.scala 27:72] + node _T_1246 = or(_T_1245, _T_1190) @[Mux.scala 27:72] + node _T_1247 = or(_T_1246, _T_1191) @[Mux.scala 27:72] + node _T_1248 = or(_T_1247, _T_1192) @[Mux.scala 27:72] + node _T_1249 = or(_T_1248, _T_1193) @[Mux.scala 27:72] + node _T_1250 = or(_T_1249, _T_1194) @[Mux.scala 27:72] node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72] node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72] node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72] @@ -74685,247 +74685,247 @@ circuit quasar_wrapper : node _T_1293 = or(_T_1292, _T_1237) @[Mux.scala 27:72] node _T_1294 = or(_T_1293, _T_1238) @[Mux.scala 27:72] node _T_1295 = or(_T_1294, _T_1239) @[Mux.scala 27:72] - node _T_1296 = or(_T_1295, _T_1240) @[Mux.scala 27:72] - node _T_1297 = or(_T_1296, _T_1241) @[Mux.scala 27:72] - node _T_1298 = or(_T_1297, _T_1242) @[Mux.scala 27:72] - node _T_1299 = or(_T_1298, _T_1243) @[Mux.scala 27:72] - node _T_1300 = or(_T_1299, _T_1244) @[Mux.scala 27:72] - node _T_1301 = or(_T_1300, _T_1245) @[Mux.scala 27:72] - node _T_1302 = or(_T_1301, _T_1246) @[Mux.scala 27:72] - node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72] - node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72] - node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72] - wire _T_1306 : UInt<1> @[Mux.scala 27:72] - _T_1306 <= _T_1305 @[Mux.scala 27:72] - node _T_1307 = and(_T_1025, _T_1306) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[0] <= _T_1307 @[dec_tlu_ctl.scala 2273:19] - node _T_1308 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2273:38] - node _T_1309 = not(_T_1308) @[dec_tlu_ctl.scala 2273:24] - node _T_1310 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1312 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1314 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1315 = bits(_T_1314, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1316 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1318 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1319 = and(io.tlu_i0_commit_cmt, _T_1318) @[dec_tlu_ctl.scala 2277:94] - node _T_1320 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1321 = bits(_T_1320, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1322 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1323 = and(io.tlu_i0_commit_cmt, _T_1322) @[dec_tlu_ctl.scala 2278:94] - node _T_1324 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1325 = and(_T_1323, _T_1324) @[dec_tlu_ctl.scala 2278:115] - node _T_1326 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1328 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1329 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1330 = and(_T_1328, _T_1329) @[dec_tlu_ctl.scala 2279:115] - node _T_1331 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1333 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1335 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1337 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1342 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1346 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1347 = bits(_T_1346, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1348 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1352 = and(_T_1351, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1353 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1357 = and(_T_1355, _T_1356) @[dec_tlu_ctl.scala 2288:101] - node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1380 = bits(_T_1379, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1389 = or(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2298:101] - node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1444 = bits(_T_1443, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1446 = bits(_T_1445, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1447 = not(_T_1446) @[dec_tlu_ctl.scala 2321:73] - node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1452 = not(_T_1451) @[dec_tlu_ctl.scala 2322:73] - node _T_1453 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1454 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1455 = and(_T_1453, _T_1454) @[dec_tlu_ctl.scala 2322:113] - node _T_1456 = orr(_T_1455) @[dec_tlu_ctl.scala 2322:125] - node _T_1457 = and(_T_1452, _T_1456) @[dec_tlu_ctl.scala 2322:98] - node _T_1458 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1460 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1461 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1463 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1464 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1469 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1470 = bits(_T_1469, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1471 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1472 = bits(_T_1471, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1473 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1474 = bits(_T_1473, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1475 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1476 = bits(_T_1475, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1477 = mux(_T_1311, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1479 = mux(_T_1315, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1480 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1481 = mux(_T_1321, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1482 = mux(_T_1327, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1483 = mux(_T_1332, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1484 = mux(_T_1334, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1485 = mux(_T_1336, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1486 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1487 = mux(_T_1341, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1488 = mux(_T_1344, _T_1345, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1489 = mux(_T_1347, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1490 = mux(_T_1350, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1491 = mux(_T_1354, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1492 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1493 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1494 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1495 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1496 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1497 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1498 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1499 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1500 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1501 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1502 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1503 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1504 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1505 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1506 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1507 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1508 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1509 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1510 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1511 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1512 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1513 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1514 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1515 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1516 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1517 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1518 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1519 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1520 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1521 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1522 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1523 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1524 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1525 = mux(_T_1449, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1526 = mux(_T_1459, _T_1460, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1527 = mux(_T_1462, _T_1463, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1528 = mux(_T_1465, _T_1466, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1529 = mux(_T_1468, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1530 = mux(_T_1470, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1531 = mux(_T_1472, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1532 = mux(_T_1474, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1533 = mux(_T_1476, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1534 = or(_T_1477, _T_1478) @[Mux.scala 27:72] + wire _T_1296 : UInt<1> @[Mux.scala 27:72] + _T_1296 <= _T_1295 @[Mux.scala 27:72] + node _T_1297 = and(_T_1015, _T_1296) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[0] <= _T_1297 @[dec_tlu_ctl.scala 2255:19] + node _T_1298 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2255:38] + node _T_1299 = not(_T_1298) @[dec_tlu_ctl.scala 2255:24] + node _T_1300 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1301 = bits(_T_1300, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1302 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1303 = bits(_T_1302, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1304 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1305 = bits(_T_1304, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1306 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1307 = bits(_T_1306, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1308 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1309 = and(io.tlu_i0_commit_cmt, _T_1308) @[dec_tlu_ctl.scala 2259:94] + node _T_1310 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1312 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1313 = and(io.tlu_i0_commit_cmt, _T_1312) @[dec_tlu_ctl.scala 2260:94] + node _T_1314 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1315 = and(_T_1313, _T_1314) @[dec_tlu_ctl.scala 2260:115] + node _T_1316 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1318 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1320 = and(_T_1318, _T_1319) @[dec_tlu_ctl.scala 2261:115] + node _T_1321 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1323 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1324 = bits(_T_1323, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1325 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1326 = bits(_T_1325, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1327 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1329 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1330 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1331 = bits(_T_1330, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1332 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1333 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1335 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1336 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1338 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1339 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1340 = bits(_T_1339, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1341 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1342 = and(_T_1341, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1346 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1347 = and(_T_1345, _T_1346) @[dec_tlu_ctl.scala 2270:101] + node _T_1348 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1349 = bits(_T_1348, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1350 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1351 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1352 = bits(_T_1351, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1353 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1354 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1357 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1358 = bits(_T_1357, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1359 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1360 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1361 = bits(_T_1360, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1362 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1363 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1364 = bits(_T_1363, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1365 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1366 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1367 = bits(_T_1366, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1368 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1369 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1370 = bits(_T_1369, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1371 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1372 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1373 = bits(_T_1372, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1374 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1375 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1376 = bits(_T_1375, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1377 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1379 = or(_T_1377, _T_1378) @[dec_tlu_ctl.scala 2280:101] + node _T_1380 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1382 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1383 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1385 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1386 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1388 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1389 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1390 = bits(_T_1389, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1391 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1395 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1396 = bits(_T_1395, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1397 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1399 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1401 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1403 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1405 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1406 = or(_T_1405, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1407 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1409 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1410 = or(_T_1409, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1411 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1415 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1416 = bits(_T_1415, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1417 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1418 = and(_T_1417, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1419 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1420 = bits(_T_1419, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1427 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_1428 = bits(_T_1427, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1435 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_1437 = not(_T_1436) @[dec_tlu_ctl.scala 2303:73] + node _T_1438 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1440 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_1442 = not(_T_1441) @[dec_tlu_ctl.scala 2304:73] + node _T_1443 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_1444 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_1445 = and(_T_1443, _T_1444) @[dec_tlu_ctl.scala 2304:113] + node _T_1446 = orr(_T_1445) @[dec_tlu_ctl.scala 2304:125] + node _T_1447 = and(_T_1442, _T_1446) @[dec_tlu_ctl.scala 2304:98] + node _T_1448 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1450 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_1451 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1453 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_1454 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_1455 = bits(_T_1454, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1456 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_1457 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_1458 = bits(_T_1457, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1459 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1461 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1463 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_1464 = bits(_T_1463, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1465 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1467 = mux(_T_1301, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1468 = mux(_T_1303, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1469 = mux(_T_1305, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1307, _T_1309, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = mux(_T_1311, _T_1315, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1472 = mux(_T_1317, _T_1320, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1473 = mux(_T_1322, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1474 = mux(_T_1324, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1475 = mux(_T_1326, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1476 = mux(_T_1328, _T_1329, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1477 = mux(_T_1331, _T_1332, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1334, _T_1335, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1337, _T_1338, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1340, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1344, _T_1347, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1349, _T_1350, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1352, _T_1353, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1355, _T_1356, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1358, _T_1359, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1361, _T_1362, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1364, _T_1365, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1367, _T_1368, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1370, _T_1371, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1373, _T_1374, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1376, _T_1379, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1381, _T_1382, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1384, _T_1385, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1387, _T_1388, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1390, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1392, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1394, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1396, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1398, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1400, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1402, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1404, _T_1406, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1408, _T_1410, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1412, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1414, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1416, _T_1418, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1420, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1422, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1424, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1426, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1428, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1430, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1432, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1434, _T_1437, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1439, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1449, _T_1450, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1452, _T_1453, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1455, _T_1456, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1458, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1460, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1462, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1464, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1466, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = or(_T_1467, _T_1468) @[Mux.scala 27:72] + node _T_1525 = or(_T_1524, _T_1469) @[Mux.scala 27:72] + node _T_1526 = or(_T_1525, _T_1470) @[Mux.scala 27:72] + node _T_1527 = or(_T_1526, _T_1471) @[Mux.scala 27:72] + node _T_1528 = or(_T_1527, _T_1472) @[Mux.scala 27:72] + node _T_1529 = or(_T_1528, _T_1473) @[Mux.scala 27:72] + node _T_1530 = or(_T_1529, _T_1474) @[Mux.scala 27:72] + node _T_1531 = or(_T_1530, _T_1475) @[Mux.scala 27:72] + node _T_1532 = or(_T_1531, _T_1476) @[Mux.scala 27:72] + node _T_1533 = or(_T_1532, _T_1477) @[Mux.scala 27:72] + node _T_1534 = or(_T_1533, _T_1478) @[Mux.scala 27:72] node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72] node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72] node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72] @@ -74971,247 +74971,247 @@ circuit quasar_wrapper : node _T_1577 = or(_T_1576, _T_1521) @[Mux.scala 27:72] node _T_1578 = or(_T_1577, _T_1522) @[Mux.scala 27:72] node _T_1579 = or(_T_1578, _T_1523) @[Mux.scala 27:72] - node _T_1580 = or(_T_1579, _T_1524) @[Mux.scala 27:72] - node _T_1581 = or(_T_1580, _T_1525) @[Mux.scala 27:72] - node _T_1582 = or(_T_1581, _T_1526) @[Mux.scala 27:72] - node _T_1583 = or(_T_1582, _T_1527) @[Mux.scala 27:72] - node _T_1584 = or(_T_1583, _T_1528) @[Mux.scala 27:72] - node _T_1585 = or(_T_1584, _T_1529) @[Mux.scala 27:72] - node _T_1586 = or(_T_1585, _T_1530) @[Mux.scala 27:72] - node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72] - node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72] - node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72] - wire _T_1590 : UInt<1> @[Mux.scala 27:72] - _T_1590 <= _T_1589 @[Mux.scala 27:72] - node _T_1591 = and(_T_1309, _T_1590) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[1] <= _T_1591 @[dec_tlu_ctl.scala 2273:19] - node _T_1592 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2273:38] - node _T_1593 = not(_T_1592) @[dec_tlu_ctl.scala 2273:24] - node _T_1594 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1596 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1598 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1599 = bits(_T_1598, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1600 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1602 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1603 = and(io.tlu_i0_commit_cmt, _T_1602) @[dec_tlu_ctl.scala 2277:94] - node _T_1604 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1605 = bits(_T_1604, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1606 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1607 = and(io.tlu_i0_commit_cmt, _T_1606) @[dec_tlu_ctl.scala 2278:94] - node _T_1608 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1609 = and(_T_1607, _T_1608) @[dec_tlu_ctl.scala 2278:115] - node _T_1610 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1612 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1613 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1614 = and(_T_1612, _T_1613) @[dec_tlu_ctl.scala 2279:115] - node _T_1615 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1617 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1619 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1621 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1626 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1631 = bits(_T_1630, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1636 = and(_T_1635, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1637 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1640 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1641 = and(_T_1639, _T_1640) @[dec_tlu_ctl.scala 2288:101] - node _T_1642 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1645 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1648 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1651 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1654 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1657 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1660 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1663 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1664 = bits(_T_1663, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1665 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1666 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1668 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1669 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1673 = or(_T_1671, _T_1672) @[dec_tlu_ctl.scala 2298:101] - node _T_1674 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1676 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1679 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1680 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1682 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1683 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1685 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1687 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1689 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1691 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1693 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1695 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1697 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1699 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1700 = or(_T_1699, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1701 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1703 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1704 = or(_T_1703, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1705 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1707 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1709 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1711 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1712 = and(_T_1711, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1717 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1719 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1721 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1723 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1725 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1727 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1728 = bits(_T_1727, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1729 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1730 = bits(_T_1729, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1731 = not(_T_1730) @[dec_tlu_ctl.scala 2321:73] - node _T_1732 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1734 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1736 = not(_T_1735) @[dec_tlu_ctl.scala 2322:73] - node _T_1737 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1738 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1739 = and(_T_1737, _T_1738) @[dec_tlu_ctl.scala 2322:113] - node _T_1740 = orr(_T_1739) @[dec_tlu_ctl.scala 2322:125] - node _T_1741 = and(_T_1736, _T_1740) @[dec_tlu_ctl.scala 2322:98] - node _T_1742 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1744 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1745 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1747 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1748 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1750 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1754 = bits(_T_1753, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1756 = bits(_T_1755, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1758 = bits(_T_1757, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1759 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1760 = bits(_T_1759, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1761 = mux(_T_1595, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1762 = mux(_T_1597, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1763 = mux(_T_1599, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1764 = mux(_T_1601, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1765 = mux(_T_1605, _T_1609, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1766 = mux(_T_1611, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1767 = mux(_T_1616, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1768 = mux(_T_1618, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1769 = mux(_T_1620, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1770 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1771 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1772 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1773 = mux(_T_1631, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1774 = mux(_T_1634, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1775 = mux(_T_1638, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1776 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1777 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1778 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1779 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1780 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1781 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1782 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1783 = mux(_T_1664, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1784 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1785 = mux(_T_1670, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1786 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1787 = mux(_T_1678, _T_1679, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1788 = mux(_T_1681, _T_1682, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1789 = mux(_T_1684, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1790 = mux(_T_1686, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1791 = mux(_T_1688, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1792 = mux(_T_1690, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1793 = mux(_T_1692, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1794 = mux(_T_1694, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1795 = mux(_T_1696, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1796 = mux(_T_1698, _T_1700, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1797 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1798 = mux(_T_1706, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1799 = mux(_T_1708, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1800 = mux(_T_1710, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1801 = mux(_T_1714, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1802 = mux(_T_1716, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1803 = mux(_T_1718, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1804 = mux(_T_1720, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1805 = mux(_T_1722, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1806 = mux(_T_1724, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1807 = mux(_T_1726, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1808 = mux(_T_1728, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1809 = mux(_T_1733, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1810 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1811 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1812 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1813 = mux(_T_1752, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1814 = mux(_T_1754, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1815 = mux(_T_1756, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1816 = mux(_T_1758, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1817 = mux(_T_1760, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1818 = or(_T_1761, _T_1762) @[Mux.scala 27:72] + wire _T_1580 : UInt<1> @[Mux.scala 27:72] + _T_1580 <= _T_1579 @[Mux.scala 27:72] + node _T_1581 = and(_T_1299, _T_1580) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[1] <= _T_1581 @[dec_tlu_ctl.scala 2255:19] + node _T_1582 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2255:38] + node _T_1583 = not(_T_1582) @[dec_tlu_ctl.scala 2255:24] + node _T_1584 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1585 = bits(_T_1584, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1586 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1587 = bits(_T_1586, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1588 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1589 = bits(_T_1588, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1590 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1591 = bits(_T_1590, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1592 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1593 = and(io.tlu_i0_commit_cmt, _T_1592) @[dec_tlu_ctl.scala 2259:94] + node _T_1594 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1596 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1597 = and(io.tlu_i0_commit_cmt, _T_1596) @[dec_tlu_ctl.scala 2260:94] + node _T_1598 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1599 = and(_T_1597, _T_1598) @[dec_tlu_ctl.scala 2260:115] + node _T_1600 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1602 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1604 = and(_T_1602, _T_1603) @[dec_tlu_ctl.scala 2261:115] + node _T_1605 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1607 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1608 = bits(_T_1607, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1609 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1610 = bits(_T_1609, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1611 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1613 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1614 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1615 = bits(_T_1614, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1616 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1617 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1619 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1620 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1622 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1623 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1624 = bits(_T_1623, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1625 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1626 = and(_T_1625, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1630 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1631 = and(_T_1629, _T_1630) @[dec_tlu_ctl.scala 2270:101] + node _T_1632 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1633 = bits(_T_1632, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1634 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1635 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1636 = bits(_T_1635, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1637 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1638 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1641 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1642 = bits(_T_1641, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1643 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1644 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1645 = bits(_T_1644, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1646 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1647 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1648 = bits(_T_1647, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1649 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1650 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1651 = bits(_T_1650, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1652 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1653 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1654 = bits(_T_1653, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1655 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1656 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1657 = bits(_T_1656, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1658 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1659 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1660 = bits(_T_1659, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1661 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1663 = or(_T_1661, _T_1662) @[dec_tlu_ctl.scala 2280:101] + node _T_1664 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1666 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1667 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1669 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1670 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1672 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1673 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1674 = bits(_T_1673, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1675 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1679 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1680 = bits(_T_1679, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1681 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1683 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1685 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1687 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1689 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1690 = or(_T_1689, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1691 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1693 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1694 = or(_T_1693, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1695 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1697 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1699 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1700 = bits(_T_1699, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1701 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1702 = and(_T_1701, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1703 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1704 = bits(_T_1703, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1705 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1707 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1709 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1711 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_1712 = bits(_T_1711, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1715 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1717 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1719 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_1721 = not(_T_1720) @[dec_tlu_ctl.scala 2303:73] + node _T_1722 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1724 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_1726 = not(_T_1725) @[dec_tlu_ctl.scala 2304:73] + node _T_1727 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_1728 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_1729 = and(_T_1727, _T_1728) @[dec_tlu_ctl.scala 2304:113] + node _T_1730 = orr(_T_1729) @[dec_tlu_ctl.scala 2304:125] + node _T_1731 = and(_T_1726, _T_1730) @[dec_tlu_ctl.scala 2304:98] + node _T_1732 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1734 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_1735 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1737 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_1738 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_1739 = bits(_T_1738, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1740 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_1741 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_1742 = bits(_T_1741, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1743 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1745 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1747 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_1748 = bits(_T_1747, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1751 = mux(_T_1585, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1752 = mux(_T_1587, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1753 = mux(_T_1589, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1754 = mux(_T_1591, _T_1593, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1755 = mux(_T_1595, _T_1599, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1756 = mux(_T_1601, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1757 = mux(_T_1606, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1758 = mux(_T_1608, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1759 = mux(_T_1610, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1760 = mux(_T_1612, _T_1613, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1761 = mux(_T_1615, _T_1616, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = mux(_T_1618, _T_1619, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1621, _T_1622, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1624, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1628, _T_1631, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1633, _T_1634, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1636, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1639, _T_1640, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1642, _T_1643, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1645, _T_1646, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1648, _T_1649, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1651, _T_1652, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1654, _T_1655, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1660, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1665, _T_1666, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1668, _T_1669, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1671, _T_1672, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1674, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1676, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1678, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1680, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1682, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1684, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1686, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1688, _T_1690, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1692, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1696, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1698, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1700, _T_1702, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1704, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1706, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1708, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1710, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1712, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1714, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1716, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1718, _T_1721, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1723, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1733, _T_1734, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1736, _T_1737, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1739, _T_1740, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1742, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1744, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1746, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1748, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1750, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = or(_T_1751, _T_1752) @[Mux.scala 27:72] + node _T_1809 = or(_T_1808, _T_1753) @[Mux.scala 27:72] + node _T_1810 = or(_T_1809, _T_1754) @[Mux.scala 27:72] + node _T_1811 = or(_T_1810, _T_1755) @[Mux.scala 27:72] + node _T_1812 = or(_T_1811, _T_1756) @[Mux.scala 27:72] + node _T_1813 = or(_T_1812, _T_1757) @[Mux.scala 27:72] + node _T_1814 = or(_T_1813, _T_1758) @[Mux.scala 27:72] + node _T_1815 = or(_T_1814, _T_1759) @[Mux.scala 27:72] + node _T_1816 = or(_T_1815, _T_1760) @[Mux.scala 27:72] + node _T_1817 = or(_T_1816, _T_1761) @[Mux.scala 27:72] + node _T_1818 = or(_T_1817, _T_1762) @[Mux.scala 27:72] node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72] node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72] node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72] @@ -75257,247 +75257,247 @@ circuit quasar_wrapper : node _T_1861 = or(_T_1860, _T_1805) @[Mux.scala 27:72] node _T_1862 = or(_T_1861, _T_1806) @[Mux.scala 27:72] node _T_1863 = or(_T_1862, _T_1807) @[Mux.scala 27:72] - node _T_1864 = or(_T_1863, _T_1808) @[Mux.scala 27:72] - node _T_1865 = or(_T_1864, _T_1809) @[Mux.scala 27:72] - node _T_1866 = or(_T_1865, _T_1810) @[Mux.scala 27:72] - node _T_1867 = or(_T_1866, _T_1811) @[Mux.scala 27:72] - node _T_1868 = or(_T_1867, _T_1812) @[Mux.scala 27:72] - node _T_1869 = or(_T_1868, _T_1813) @[Mux.scala 27:72] - node _T_1870 = or(_T_1869, _T_1814) @[Mux.scala 27:72] - node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72] - node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72] - node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72] - wire _T_1874 : UInt<1> @[Mux.scala 27:72] - _T_1874 <= _T_1873 @[Mux.scala 27:72] - node _T_1875 = and(_T_1593, _T_1874) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[2] <= _T_1875 @[dec_tlu_ctl.scala 2273:19] - node _T_1876 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2273:38] - node _T_1877 = not(_T_1876) @[dec_tlu_ctl.scala 2273:24] - node _T_1878 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1880 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1882 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1883 = bits(_T_1882, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1884 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1886 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[dec_tlu_ctl.scala 2277:94] - node _T_1888 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1889 = bits(_T_1888, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1890 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1891 = and(io.tlu_i0_commit_cmt, _T_1890) @[dec_tlu_ctl.scala 2278:94] - node _T_1892 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1893 = and(_T_1891, _T_1892) @[dec_tlu_ctl.scala 2278:115] - node _T_1894 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1896 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1897 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1898 = and(_T_1896, _T_1897) @[dec_tlu_ctl.scala 2279:115] - node _T_1899 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1901 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1903 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1905 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1910 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1914 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1915 = bits(_T_1914, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1916 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1920 = and(_T_1919, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1921 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1924 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1925 = and(_T_1923, _T_1924) @[dec_tlu_ctl.scala 2288:101] - node _T_1926 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1929 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1932 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1935 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1938 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1941 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1944 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1947 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1948 = bits(_T_1947, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1949 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1950 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1952 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1953 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1955 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1957 = or(_T_1955, _T_1956) @[dec_tlu_ctl.scala 2298:101] - node _T_1958 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1960 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1963 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1964 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1966 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1971 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1973 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1975 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1977 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1979 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1981 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1983 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1984 = or(_T_1983, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1985 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1987 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1988 = or(_T_1987, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1989 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1991 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1993 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1995 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1996 = and(_T_1995, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_2007 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_2009 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_2011 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_2012 = bits(_T_2011, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_2013 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_2014 = bits(_T_2013, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_2015 = not(_T_2014) @[dec_tlu_ctl.scala 2321:73] - node _T_2016 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_2018 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_2020 = not(_T_2019) @[dec_tlu_ctl.scala 2322:73] - node _T_2021 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_2022 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_2023 = and(_T_2021, _T_2022) @[dec_tlu_ctl.scala 2322:113] - node _T_2024 = orr(_T_2023) @[dec_tlu_ctl.scala 2322:125] - node _T_2025 = and(_T_2020, _T_2024) @[dec_tlu_ctl.scala 2322:98] - node _T_2026 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_2028 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_2029 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_2032 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_2034 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_2037 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_2038 = bits(_T_2037, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_2039 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_2040 = bits(_T_2039, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_2041 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_2042 = bits(_T_2041, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_2043 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_2044 = bits(_T_2043, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_2045 = mux(_T_1879, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2046 = mux(_T_1881, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_1883, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_1885, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_1889, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_1895, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_1900, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_1902, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_1904, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_1909, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_1912, _T_1913, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_1915, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = mux(_T_1918, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2059 = mux(_T_1922, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2060 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2061 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2062 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2063 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2064 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2065 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2066 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2067 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2068 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2069 = mux(_T_1954, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2070 = mux(_T_1959, _T_1960, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2071 = mux(_T_1962, _T_1963, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2072 = mux(_T_1965, _T_1966, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2073 = mux(_T_1968, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2074 = mux(_T_1970, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2075 = mux(_T_1972, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2076 = mux(_T_1974, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2077 = mux(_T_1976, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2078 = mux(_T_1978, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2079 = mux(_T_1980, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2080 = mux(_T_1982, _T_1984, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2081 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2082 = mux(_T_1990, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2083 = mux(_T_1992, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2084 = mux(_T_1994, _T_1996, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2085 = mux(_T_1998, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2086 = mux(_T_2000, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2087 = mux(_T_2002, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2088 = mux(_T_2004, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2089 = mux(_T_2006, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2090 = mux(_T_2008, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2091 = mux(_T_2010, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2092 = mux(_T_2012, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2093 = mux(_T_2017, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2094 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2095 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2096 = mux(_T_2033, _T_2034, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2097 = mux(_T_2036, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2098 = mux(_T_2038, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2099 = mux(_T_2040, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2100 = mux(_T_2042, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2101 = mux(_T_2044, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2102 = or(_T_2045, _T_2046) @[Mux.scala 27:72] + wire _T_1864 : UInt<1> @[Mux.scala 27:72] + _T_1864 <= _T_1863 @[Mux.scala 27:72] + node _T_1865 = and(_T_1583, _T_1864) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[2] <= _T_1865 @[dec_tlu_ctl.scala 2255:19] + node _T_1866 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2255:38] + node _T_1867 = not(_T_1866) @[dec_tlu_ctl.scala 2255:24] + node _T_1868 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1869 = bits(_T_1868, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1870 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1871 = bits(_T_1870, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1872 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1873 = bits(_T_1872, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1874 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1875 = bits(_T_1874, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1876 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1877 = and(io.tlu_i0_commit_cmt, _T_1876) @[dec_tlu_ctl.scala 2259:94] + node _T_1878 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1880 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1881 = and(io.tlu_i0_commit_cmt, _T_1880) @[dec_tlu_ctl.scala 2260:94] + node _T_1882 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1883 = and(_T_1881, _T_1882) @[dec_tlu_ctl.scala 2260:115] + node _T_1884 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1886 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1888 = and(_T_1886, _T_1887) @[dec_tlu_ctl.scala 2261:115] + node _T_1889 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1891 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1892 = bits(_T_1891, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1893 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1894 = bits(_T_1893, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1895 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1897 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1898 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1899 = bits(_T_1898, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1900 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1901 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1903 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1904 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1906 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1907 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1908 = bits(_T_1907, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1909 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1910 = and(_T_1909, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1914 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1915 = and(_T_1913, _T_1914) @[dec_tlu_ctl.scala 2270:101] + node _T_1916 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1917 = bits(_T_1916, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1918 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1919 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1920 = bits(_T_1919, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1921 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1922 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1925 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1926 = bits(_T_1925, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1927 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1928 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1929 = bits(_T_1928, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1930 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1931 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1932 = bits(_T_1931, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1933 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1934 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1935 = bits(_T_1934, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1936 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1937 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1938 = bits(_T_1937, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1939 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1940 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1941 = bits(_T_1940, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1942 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1943 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1944 = bits(_T_1943, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1945 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1947 = or(_T_1945, _T_1946) @[dec_tlu_ctl.scala 2280:101] + node _T_1948 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1950 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1951 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1953 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1954 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1956 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1957 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1958 = bits(_T_1957, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1963 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1964 = bits(_T_1963, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1965 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1967 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1969 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1971 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1973 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1974 = or(_T_1973, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1975 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1977 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1978 = or(_T_1977, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1979 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1981 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1983 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1984 = bits(_T_1983, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1985 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1986 = and(_T_1985, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1987 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1988 = bits(_T_1987, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1993 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_1996 = bits(_T_1995, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_2003 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_2005 = not(_T_2004) @[dec_tlu_ctl.scala 2303:73] + node _T_2006 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_2008 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_2010 = not(_T_2009) @[dec_tlu_ctl.scala 2304:73] + node _T_2011 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_2012 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_2013 = and(_T_2011, _T_2012) @[dec_tlu_ctl.scala 2304:113] + node _T_2014 = orr(_T_2013) @[dec_tlu_ctl.scala 2304:125] + node _T_2015 = and(_T_2010, _T_2014) @[dec_tlu_ctl.scala 2304:98] + node _T_2016 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_2018 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_2019 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_2021 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_2022 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_2023 = bits(_T_2022, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_2024 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_2025 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_2026 = bits(_T_2025, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_2027 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_2029 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_2031 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_2032 = bits(_T_2031, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_2033 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_2035 = mux(_T_1869, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2036 = mux(_T_1871, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2037 = mux(_T_1873, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2038 = mux(_T_1875, _T_1877, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2039 = mux(_T_1879, _T_1883, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2040 = mux(_T_1885, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2041 = mux(_T_1890, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2042 = mux(_T_1892, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2043 = mux(_T_1894, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2044 = mux(_T_1896, _T_1897, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2045 = mux(_T_1899, _T_1900, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_1902, _T_1903, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1905, _T_1906, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1908, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1912, _T_1915, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1917, _T_1918, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1920, _T_1921, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1923, _T_1924, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1926, _T_1927, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1929, _T_1930, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1932, _T_1933, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1935, _T_1936, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1938, _T_1939, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1941, _T_1942, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1944, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1955, _T_1956, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1958, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1960, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1962, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1964, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1966, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1968, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1970, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1972, _T_1974, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1976, _T_1978, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1980, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1982, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1984, _T_1986, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1988, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1990, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1992, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1994, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1996, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1998, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_2000, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_2002, _T_2005, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_2007, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_2017, _T_2018, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_2020, _T_2021, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_2023, _T_2024, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2026, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2028, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2030, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2032, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2034, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = or(_T_2035, _T_2036) @[Mux.scala 27:72] + node _T_2093 = or(_T_2092, _T_2037) @[Mux.scala 27:72] + node _T_2094 = or(_T_2093, _T_2038) @[Mux.scala 27:72] + node _T_2095 = or(_T_2094, _T_2039) @[Mux.scala 27:72] + node _T_2096 = or(_T_2095, _T_2040) @[Mux.scala 27:72] + node _T_2097 = or(_T_2096, _T_2041) @[Mux.scala 27:72] + node _T_2098 = or(_T_2097, _T_2042) @[Mux.scala 27:72] + node _T_2099 = or(_T_2098, _T_2043) @[Mux.scala 27:72] + node _T_2100 = or(_T_2099, _T_2044) @[Mux.scala 27:72] + node _T_2101 = or(_T_2100, _T_2045) @[Mux.scala 27:72] + node _T_2102 = or(_T_2101, _T_2046) @[Mux.scala 27:72] node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72] node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72] node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72] @@ -75543,585 +75543,585 @@ circuit quasar_wrapper : node _T_2145 = or(_T_2144, _T_2089) @[Mux.scala 27:72] node _T_2146 = or(_T_2145, _T_2090) @[Mux.scala 27:72] node _T_2147 = or(_T_2146, _T_2091) @[Mux.scala 27:72] - node _T_2148 = or(_T_2147, _T_2092) @[Mux.scala 27:72] - node _T_2149 = or(_T_2148, _T_2093) @[Mux.scala 27:72] - node _T_2150 = or(_T_2149, _T_2094) @[Mux.scala 27:72] - node _T_2151 = or(_T_2150, _T_2095) @[Mux.scala 27:72] - node _T_2152 = or(_T_2151, _T_2096) @[Mux.scala 27:72] - node _T_2153 = or(_T_2152, _T_2097) @[Mux.scala 27:72] - node _T_2154 = or(_T_2153, _T_2098) @[Mux.scala 27:72] - node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72] - node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72] - node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72] - wire _T_2158 : UInt<1> @[Mux.scala 27:72] - _T_2158 <= _T_2157 @[Mux.scala 27:72] - node _T_2159 = and(_T_1877, _T_2158) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[3] <= _T_2159 @[dec_tlu_ctl.scala 2273:19] - reg _T_2160 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] - _T_2160 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2334:53] - mhpmc_inc_r_d1[0] <= _T_2160 @[dec_tlu_ctl.scala 2334:20] - reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] - _T_2161 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2335:53] - mhpmc_inc_r_d1[1] <= _T_2161 @[dec_tlu_ctl.scala 2335:20] - reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] - _T_2162 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2336:53] - mhpmc_inc_r_d1[2] <= _T_2162 @[dec_tlu_ctl.scala 2336:20] - reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] - _T_2163 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2337:53] - mhpmc_inc_r_d1[3] <= _T_2163 @[dec_tlu_ctl.scala 2337:20] - reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:56] - perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2338:56] - node _T_2164 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:53] - node _T_2165 = and(io.dec_tlu_dbg_halted, _T_2164) @[dec_tlu_ctl.scala 2341:44] - node _T_2166 = or(_T_2165, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2341:67] - perfcnt_halted <= _T_2166 @[dec_tlu_ctl.scala 2341:17] - node _T_2167 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:70] - node _T_2168 = and(io.dec_tlu_dbg_halted, _T_2167) @[dec_tlu_ctl.scala 2342:61] - node _T_2169 = not(_T_2168) @[dec_tlu_ctl.scala 2342:37] - node _T_2170 = bits(_T_2169, 0, 0) @[Bitwise.scala 72:15] - node _T_2171 = mux(_T_2170, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2172 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2342:104] - node _T_2173 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2342:120] - node _T_2174 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2342:136] - node _T_2175 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2342:152] - node _T_2176 = cat(_T_2174, _T_2175) @[Cat.scala 29:58] - node _T_2177 = cat(_T_2172, _T_2173) @[Cat.scala 29:58] - node _T_2178 = cat(_T_2177, _T_2176) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2171, _T_2178) @[dec_tlu_ctl.scala 2342:86] - node _T_2179 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2344:88] - node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2344:67] - node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2344:65] - node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2344:45] - node _T_2183 = and(mhpmc_inc_r_d1[0], _T_2182) @[dec_tlu_ctl.scala 2344:43] - io.dec_tlu_perfcnt0 <= _T_2183 @[dec_tlu_ctl.scala 2344:22] - node _T_2184 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2345:88] - node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2345:67] - node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2345:65] - node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2345:45] - node _T_2188 = and(mhpmc_inc_r_d1[1], _T_2187) @[dec_tlu_ctl.scala 2345:43] - io.dec_tlu_perfcnt1 <= _T_2188 @[dec_tlu_ctl.scala 2345:22] - node _T_2189 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2346:88] - node _T_2190 = not(_T_2189) @[dec_tlu_ctl.scala 2346:67] - node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[dec_tlu_ctl.scala 2346:65] - node _T_2192 = not(_T_2191) @[dec_tlu_ctl.scala 2346:45] - node _T_2193 = and(mhpmc_inc_r_d1[2], _T_2192) @[dec_tlu_ctl.scala 2346:43] - io.dec_tlu_perfcnt2 <= _T_2193 @[dec_tlu_ctl.scala 2346:22] - node _T_2194 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2347:88] - node _T_2195 = not(_T_2194) @[dec_tlu_ctl.scala 2347:67] - node _T_2196 = and(perfcnt_halted_d1, _T_2195) @[dec_tlu_ctl.scala 2347:65] - node _T_2197 = not(_T_2196) @[dec_tlu_ctl.scala 2347:45] - node _T_2198 = and(mhpmc_inc_r_d1[3], _T_2197) @[dec_tlu_ctl.scala 2347:43] - io.dec_tlu_perfcnt3 <= _T_2198 @[dec_tlu_ctl.scala 2347:22] - node _T_2199 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2353:65] - node _T_2200 = eq(_T_2199, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2353:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2200) @[dec_tlu_ctl.scala 2353:43] - node _T_2201 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2354:23] - node _T_2202 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2354:61] - node _T_2203 = or(_T_2201, _T_2202) @[dec_tlu_ctl.scala 2354:39] - node _T_2204 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2354:86] - node mhpmc3_wr_en1 = and(_T_2203, _T_2204) @[dec_tlu_ctl.scala 2354:66] - node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2355:36] - node _T_2205 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2358:28] - node _T_2206 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2358:41] - node _T_2207 = cat(_T_2205, _T_2206) @[Cat.scala 29:58] - node _T_2208 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2209 = add(_T_2207, _T_2208) @[dec_tlu_ctl.scala 2358:49] - node _T_2210 = tail(_T_2209, 1) @[dec_tlu_ctl.scala 2358:49] - mhpmc3_incr <= _T_2210 @[dec_tlu_ctl.scala 2358:14] - node _T_2211 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2359:36] - node _T_2212 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2359:76] - node mhpmc3_ns = mux(_T_2211, io.dec_csr_wrdata_r, _T_2212) @[dec_tlu_ctl.scala 2359:21] - node _T_2213 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2361:42] + wire _T_2148 : UInt<1> @[Mux.scala 27:72] + _T_2148 <= _T_2147 @[Mux.scala 27:72] + node _T_2149 = and(_T_1867, _T_2148) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[3] <= _T_2149 @[dec_tlu_ctl.scala 2255:19] + reg _T_2150 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2316:53] + _T_2150 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2316:53] + mhpmc_inc_r_d1[0] <= _T_2150 @[dec_tlu_ctl.scala 2316:20] + reg _T_2151 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2317:53] + _T_2151 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2317:53] + mhpmc_inc_r_d1[1] <= _T_2151 @[dec_tlu_ctl.scala 2317:20] + reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2318:53] + _T_2152 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2318:53] + mhpmc_inc_r_d1[2] <= _T_2152 @[dec_tlu_ctl.scala 2318:20] + reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2319:53] + _T_2153 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2319:53] + mhpmc_inc_r_d1[3] <= _T_2153 @[dec_tlu_ctl.scala 2319:20] + reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2320:56] + perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2320:56] + node _T_2154 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2323:53] + node _T_2155 = and(io.dec_tlu_dbg_halted, _T_2154) @[dec_tlu_ctl.scala 2323:44] + node _T_2156 = or(_T_2155, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2323:67] + perfcnt_halted <= _T_2156 @[dec_tlu_ctl.scala 2323:17] + node _T_2157 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2324:70] + node _T_2158 = and(io.dec_tlu_dbg_halted, _T_2157) @[dec_tlu_ctl.scala 2324:61] + node _T_2159 = not(_T_2158) @[dec_tlu_ctl.scala 2324:37] + node _T_2160 = bits(_T_2159, 0, 0) @[Bitwise.scala 72:15] + node _T_2161 = mux(_T_2160, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2162 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2324:104] + node _T_2163 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2324:120] + node _T_2164 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2324:136] + node _T_2165 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2324:152] + node _T_2166 = cat(_T_2164, _T_2165) @[Cat.scala 29:58] + node _T_2167 = cat(_T_2162, _T_2163) @[Cat.scala 29:58] + node _T_2168 = cat(_T_2167, _T_2166) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2161, _T_2168) @[dec_tlu_ctl.scala 2324:86] + node _T_2169 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2326:88] + node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2326:67] + node _T_2171 = and(perfcnt_halted_d1, _T_2170) @[dec_tlu_ctl.scala 2326:65] + node _T_2172 = not(_T_2171) @[dec_tlu_ctl.scala 2326:45] + node _T_2173 = and(mhpmc_inc_r_d1[0], _T_2172) @[dec_tlu_ctl.scala 2326:43] + io.dec_tlu_perfcnt0 <= _T_2173 @[dec_tlu_ctl.scala 2326:22] + node _T_2174 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2327:88] + node _T_2175 = not(_T_2174) @[dec_tlu_ctl.scala 2327:67] + node _T_2176 = and(perfcnt_halted_d1, _T_2175) @[dec_tlu_ctl.scala 2327:65] + node _T_2177 = not(_T_2176) @[dec_tlu_ctl.scala 2327:45] + node _T_2178 = and(mhpmc_inc_r_d1[1], _T_2177) @[dec_tlu_ctl.scala 2327:43] + io.dec_tlu_perfcnt1 <= _T_2178 @[dec_tlu_ctl.scala 2327:22] + node _T_2179 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2328:88] + node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2328:67] + node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2328:65] + node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2328:45] + node _T_2183 = and(mhpmc_inc_r_d1[2], _T_2182) @[dec_tlu_ctl.scala 2328:43] + io.dec_tlu_perfcnt2 <= _T_2183 @[dec_tlu_ctl.scala 2328:22] + node _T_2184 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2329:88] + node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2329:67] + node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2329:65] + node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2329:45] + node _T_2188 = and(mhpmc_inc_r_d1[3], _T_2187) @[dec_tlu_ctl.scala 2329:43] + io.dec_tlu_perfcnt3 <= _T_2188 @[dec_tlu_ctl.scala 2329:22] + node _T_2189 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2335:65] + node _T_2190 = eq(_T_2189, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2335:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2190) @[dec_tlu_ctl.scala 2335:43] + node _T_2191 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2336:23] + node _T_2192 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2336:61] + node _T_2193 = or(_T_2191, _T_2192) @[dec_tlu_ctl.scala 2336:39] + node _T_2194 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2336:86] + node mhpmc3_wr_en1 = and(_T_2193, _T_2194) @[dec_tlu_ctl.scala 2336:66] + node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2337:36] + node _T_2195 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2340:28] + node _T_2196 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2340:41] + node _T_2197 = cat(_T_2195, _T_2196) @[Cat.scala 29:58] + node _T_2198 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2199 = add(_T_2197, _T_2198) @[dec_tlu_ctl.scala 2340:49] + node _T_2200 = tail(_T_2199, 1) @[dec_tlu_ctl.scala 2340:49] + mhpmc3_incr <= _T_2200 @[dec_tlu_ctl.scala 2340:14] + node _T_2201 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2341:36] + node _T_2202 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2341:76] + node mhpmc3_ns = mux(_T_2201, io.dec_csr_wrdata_r, _T_2202) @[dec_tlu_ctl.scala 2341:21] + node _T_2203 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2343:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_26.io.en <= _T_2213 @[lib.scala 371:17] + rvclkhdr_26.io.en <= _T_2203 @[lib.scala 371:17] rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2214 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2214 <= mhpmc3_ns @[lib.scala 374:16] - mhpmc3 <= _T_2214 @[dec_tlu_ctl.scala 2361:9] - node _T_2215 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2363:66] - node _T_2216 = eq(_T_2215, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2363:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2216) @[dec_tlu_ctl.scala 2363:44] - node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2364:38] - node _T_2217 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2365:38] - node _T_2218 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2365:78] - node mhpmc3h_ns = mux(_T_2217, io.dec_csr_wrdata_r, _T_2218) @[dec_tlu_ctl.scala 2365:22] - node _T_2219 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] + reg _T_2204 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2204 <= mhpmc3_ns @[lib.scala 374:16] + mhpmc3 <= _T_2204 @[dec_tlu_ctl.scala 2343:9] + node _T_2205 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2345:66] + node _T_2206 = eq(_T_2205, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2345:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2206) @[dec_tlu_ctl.scala 2345:44] + node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2346:38] + node _T_2207 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2347:38] + node _T_2208 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2347:78] + node mhpmc3h_ns = mux(_T_2207, io.dec_csr_wrdata_r, _T_2208) @[dec_tlu_ctl.scala 2347:22] + node _T_2209 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2349:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_27.io.en <= _T_2219 @[lib.scala 371:17] + rvclkhdr_27.io.en <= _T_2209 @[lib.scala 371:17] rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2220 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2220 <= mhpmc3h_ns @[lib.scala 374:16] - mhpmc3h <= _T_2220 @[dec_tlu_ctl.scala 2367:10] - node _T_2221 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2372:65] - node _T_2222 = eq(_T_2221, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2372:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2222) @[dec_tlu_ctl.scala 2372:43] - node _T_2223 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2373:23] - node _T_2224 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2373:61] - node _T_2225 = or(_T_2223, _T_2224) @[dec_tlu_ctl.scala 2373:39] - node _T_2226 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2373:86] - node mhpmc4_wr_en1 = and(_T_2225, _T_2226) @[dec_tlu_ctl.scala 2373:66] - node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2374:36] - node _T_2227 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2378:28] - node _T_2228 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2378:41] - node _T_2229 = cat(_T_2227, _T_2228) @[Cat.scala 29:58] - node _T_2230 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2231 = add(_T_2229, _T_2230) @[dec_tlu_ctl.scala 2378:49] - node _T_2232 = tail(_T_2231, 1) @[dec_tlu_ctl.scala 2378:49] - mhpmc4_incr <= _T_2232 @[dec_tlu_ctl.scala 2378:14] - node _T_2233 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2379:36] - node _T_2234 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2379:63] - node _T_2235 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2379:82] - node mhpmc4_ns = mux(_T_2233, _T_2234, _T_2235) @[dec_tlu_ctl.scala 2379:21] - node _T_2236 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] + reg _T_2210 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2210 <= mhpmc3h_ns @[lib.scala 374:16] + mhpmc3h <= _T_2210 @[dec_tlu_ctl.scala 2349:10] + node _T_2211 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] + node _T_2212 = eq(_T_2211, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2354:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2212) @[dec_tlu_ctl.scala 2354:43] + node _T_2213 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] + node _T_2214 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2355:61] + node _T_2215 = or(_T_2213, _T_2214) @[dec_tlu_ctl.scala 2355:39] + node _T_2216 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2355:86] + node mhpmc4_wr_en1 = and(_T_2215, _T_2216) @[dec_tlu_ctl.scala 2355:66] + node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2356:36] + node _T_2217 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2360:28] + node _T_2218 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2360:41] + node _T_2219 = cat(_T_2217, _T_2218) @[Cat.scala 29:58] + node _T_2220 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2221 = add(_T_2219, _T_2220) @[dec_tlu_ctl.scala 2360:49] + node _T_2222 = tail(_T_2221, 1) @[dec_tlu_ctl.scala 2360:49] + mhpmc4_incr <= _T_2222 @[dec_tlu_ctl.scala 2360:14] + node _T_2223 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2361:36] + node _T_2224 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2361:63] + node _T_2225 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2361:82] + node mhpmc4_ns = mux(_T_2223, _T_2224, _T_2225) @[dec_tlu_ctl.scala 2361:21] + node _T_2226 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_28.io.en <= _T_2236 @[lib.scala 371:17] + rvclkhdr_28.io.en <= _T_2226 @[lib.scala 371:17] rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2237 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2237 <= mhpmc4_ns @[lib.scala 374:16] - mhpmc4 <= _T_2237 @[dec_tlu_ctl.scala 2380:9] - node _T_2238 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] - node _T_2239 = eq(_T_2238, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2382:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2239) @[dec_tlu_ctl.scala 2382:44] - node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2383:38] - node _T_2240 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] - node _T_2241 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] - node mhpmc4h_ns = mux(_T_2240, io.dec_csr_wrdata_r, _T_2241) @[dec_tlu_ctl.scala 2384:22] - node _T_2242 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2385:46] + reg _T_2227 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2227 <= mhpmc4_ns @[lib.scala 374:16] + mhpmc4 <= _T_2227 @[dec_tlu_ctl.scala 2362:9] + node _T_2228 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] + node _T_2229 = eq(_T_2228, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2364:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2229) @[dec_tlu_ctl.scala 2364:44] + node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2365:38] + node _T_2230 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] + node _T_2231 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] + node mhpmc4h_ns = mux(_T_2230, io.dec_csr_wrdata_r, _T_2231) @[dec_tlu_ctl.scala 2366:22] + node _T_2232 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_29.io.en <= _T_2242 @[lib.scala 371:17] + rvclkhdr_29.io.en <= _T_2232 @[lib.scala 371:17] rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2243 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2243 <= mhpmc4h_ns @[lib.scala 374:16] - mhpmc4h <= _T_2243 @[dec_tlu_ctl.scala 2385:10] - node _T_2244 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] - node _T_2245 = eq(_T_2244, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2391:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2245) @[dec_tlu_ctl.scala 2391:43] - node _T_2246 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] - node _T_2247 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2392:61] - node _T_2248 = or(_T_2246, _T_2247) @[dec_tlu_ctl.scala 2392:39] - node _T_2249 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2392:86] - node mhpmc5_wr_en1 = and(_T_2248, _T_2249) @[dec_tlu_ctl.scala 2392:66] - node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2393:36] - node _T_2250 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2395:28] - node _T_2251 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2395:41] - node _T_2252 = cat(_T_2250, _T_2251) @[Cat.scala 29:58] - node _T_2253 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2254 = add(_T_2252, _T_2253) @[dec_tlu_ctl.scala 2395:49] - node _T_2255 = tail(_T_2254, 1) @[dec_tlu_ctl.scala 2395:49] - mhpmc5_incr <= _T_2255 @[dec_tlu_ctl.scala 2395:14] - node _T_2256 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] - node _T_2257 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] - node mhpmc5_ns = mux(_T_2256, io.dec_csr_wrdata_r, _T_2257) @[dec_tlu_ctl.scala 2396:21] - node _T_2258 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] + reg _T_2233 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2233 <= mhpmc4h_ns @[lib.scala 374:16] + mhpmc4h <= _T_2233 @[dec_tlu_ctl.scala 2367:10] + node _T_2234 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] + node _T_2235 = eq(_T_2234, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2373:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2235) @[dec_tlu_ctl.scala 2373:43] + node _T_2236 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] + node _T_2237 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2374:61] + node _T_2238 = or(_T_2236, _T_2237) @[dec_tlu_ctl.scala 2374:39] + node _T_2239 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2374:86] + node mhpmc5_wr_en1 = and(_T_2238, _T_2239) @[dec_tlu_ctl.scala 2374:66] + node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2375:36] + node _T_2240 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2377:28] + node _T_2241 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2377:41] + node _T_2242 = cat(_T_2240, _T_2241) @[Cat.scala 29:58] + node _T_2243 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2244 = add(_T_2242, _T_2243) @[dec_tlu_ctl.scala 2377:49] + node _T_2245 = tail(_T_2244, 1) @[dec_tlu_ctl.scala 2377:49] + mhpmc5_incr <= _T_2245 @[dec_tlu_ctl.scala 2377:14] + node _T_2246 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2378:36] + node _T_2247 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2378:76] + node mhpmc5_ns = mux(_T_2246, io.dec_csr_wrdata_r, _T_2247) @[dec_tlu_ctl.scala 2378:21] + node _T_2248 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_30.io.en <= _T_2258 @[lib.scala 371:17] + rvclkhdr_30.io.en <= _T_2248 @[lib.scala 371:17] rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2259 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2259 <= mhpmc5_ns @[lib.scala 374:16] - mhpmc5 <= _T_2259 @[dec_tlu_ctl.scala 2398:9] - node _T_2260 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] - node _T_2261 = eq(_T_2260, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2400:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2261) @[dec_tlu_ctl.scala 2400:44] - node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2401:38] - node _T_2262 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] - node _T_2263 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] - node mhpmc5h_ns = mux(_T_2262, io.dec_csr_wrdata_r, _T_2263) @[dec_tlu_ctl.scala 2402:22] - node _T_2264 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] + reg _T_2249 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2249 <= mhpmc5_ns @[lib.scala 374:16] + mhpmc5 <= _T_2249 @[dec_tlu_ctl.scala 2380:9] + node _T_2250 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] + node _T_2251 = eq(_T_2250, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2382:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2251) @[dec_tlu_ctl.scala 2382:44] + node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2383:38] + node _T_2252 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] + node _T_2253 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] + node mhpmc5h_ns = mux(_T_2252, io.dec_csr_wrdata_r, _T_2253) @[dec_tlu_ctl.scala 2384:22] + node _T_2254 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset rvclkhdr_31.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_31.io.en <= _T_2264 @[lib.scala 371:17] + rvclkhdr_31.io.en <= _T_2254 @[lib.scala 371:17] rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2265 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2265 <= mhpmc5h_ns @[lib.scala 374:16] - mhpmc5h <= _T_2265 @[dec_tlu_ctl.scala 2404:10] - node _T_2266 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2409:65] - node _T_2267 = eq(_T_2266, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2409:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2267) @[dec_tlu_ctl.scala 2409:43] - node _T_2268 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2410:23] - node _T_2269 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2410:61] - node _T_2270 = or(_T_2268, _T_2269) @[dec_tlu_ctl.scala 2410:39] - node _T_2271 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2410:86] - node mhpmc6_wr_en1 = and(_T_2270, _T_2271) @[dec_tlu_ctl.scala 2410:66] - node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2411:36] - node _T_2272 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2413:28] - node _T_2273 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2413:41] - node _T_2274 = cat(_T_2272, _T_2273) @[Cat.scala 29:58] - node _T_2275 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2276 = add(_T_2274, _T_2275) @[dec_tlu_ctl.scala 2413:49] - node _T_2277 = tail(_T_2276, 1) @[dec_tlu_ctl.scala 2413:49] - mhpmc6_incr <= _T_2277 @[dec_tlu_ctl.scala 2413:14] - node _T_2278 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2414:36] - node _T_2279 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2414:76] - node mhpmc6_ns = mux(_T_2278, io.dec_csr_wrdata_r, _T_2279) @[dec_tlu_ctl.scala 2414:21] - node _T_2280 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2416:43] + reg _T_2255 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2255 <= mhpmc5h_ns @[lib.scala 374:16] + mhpmc5h <= _T_2255 @[dec_tlu_ctl.scala 2386:10] + node _T_2256 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] + node _T_2257 = eq(_T_2256, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2391:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2257) @[dec_tlu_ctl.scala 2391:43] + node _T_2258 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] + node _T_2259 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2392:61] + node _T_2260 = or(_T_2258, _T_2259) @[dec_tlu_ctl.scala 2392:39] + node _T_2261 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2392:86] + node mhpmc6_wr_en1 = and(_T_2260, _T_2261) @[dec_tlu_ctl.scala 2392:66] + node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2393:36] + node _T_2262 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2395:28] + node _T_2263 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2395:41] + node _T_2264 = cat(_T_2262, _T_2263) @[Cat.scala 29:58] + node _T_2265 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2266 = add(_T_2264, _T_2265) @[dec_tlu_ctl.scala 2395:49] + node _T_2267 = tail(_T_2266, 1) @[dec_tlu_ctl.scala 2395:49] + mhpmc6_incr <= _T_2267 @[dec_tlu_ctl.scala 2395:14] + node _T_2268 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] + node _T_2269 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] + node mhpmc6_ns = mux(_T_2268, io.dec_csr_wrdata_r, _T_2269) @[dec_tlu_ctl.scala 2396:21] + node _T_2270 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset rvclkhdr_32.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_32.io.en <= _T_2280 @[lib.scala 371:17] + rvclkhdr_32.io.en <= _T_2270 @[lib.scala 371:17] rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2281 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2281 <= mhpmc6_ns @[lib.scala 374:16] - mhpmc6 <= _T_2281 @[dec_tlu_ctl.scala 2416:9] - node _T_2282 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2418:66] - node _T_2283 = eq(_T_2282, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2418:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2283) @[dec_tlu_ctl.scala 2418:44] - node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2419:38] - node _T_2284 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2420:38] - node _T_2285 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2420:78] - node mhpmc6h_ns = mux(_T_2284, io.dec_csr_wrdata_r, _T_2285) @[dec_tlu_ctl.scala 2420:22] - node _T_2286 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2422:46] + reg _T_2271 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2271 <= mhpmc6_ns @[lib.scala 374:16] + mhpmc6 <= _T_2271 @[dec_tlu_ctl.scala 2398:9] + node _T_2272 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] + node _T_2273 = eq(_T_2272, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2400:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2273) @[dec_tlu_ctl.scala 2400:44] + node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2401:38] + node _T_2274 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] + node _T_2275 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] + node mhpmc6h_ns = mux(_T_2274, io.dec_csr_wrdata_r, _T_2275) @[dec_tlu_ctl.scala 2402:22] + node _T_2276 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset rvclkhdr_33.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_33.io.en <= _T_2286 @[lib.scala 371:17] + rvclkhdr_33.io.en <= _T_2276 @[lib.scala 371:17] rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2287 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2287 <= mhpmc6h_ns @[lib.scala 374:16] - mhpmc6h <= _T_2287 @[dec_tlu_ctl.scala 2422:10] - node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:50] - node _T_2289 = gt(_T_2288, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2429:56] - node _T_2290 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2429:93] - node _T_2291 = orr(_T_2290) @[dec_tlu_ctl.scala 2429:102] - node _T_2292 = or(_T_2289, _T_2291) @[dec_tlu_ctl.scala 2429:71] - node _T_2293 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:141] - node event_saturate_r = mux(_T_2292, UInt<10>("h0204"), _T_2293) @[dec_tlu_ctl.scala 2429:28] - node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2431:63] - node _T_2295 = eq(_T_2294, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2431:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2431:41] - node _T_2296 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2433:80] - reg _T_2297 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2296 : @[Reg.scala 28:19] - _T_2297 <= event_saturate_r @[Reg.scala 28:23] + reg _T_2277 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2277 <= mhpmc6h_ns @[lib.scala 374:16] + mhpmc6h <= _T_2277 @[dec_tlu_ctl.scala 2404:10] + node _T_2278 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:50] + node _T_2279 = gt(_T_2278, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2411:56] + node _T_2280 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2411:93] + node _T_2281 = orr(_T_2280) @[dec_tlu_ctl.scala 2411:102] + node _T_2282 = or(_T_2279, _T_2281) @[dec_tlu_ctl.scala 2411:71] + node _T_2283 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:141] + node event_saturate_r = mux(_T_2282, UInt<10>("h0204"), _T_2283) @[dec_tlu_ctl.scala 2411:28] + node _T_2284 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2413:63] + node _T_2285 = eq(_T_2284, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2413:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2285) @[dec_tlu_ctl.scala 2413:41] + node _T_2286 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2415:80] + reg _T_2287 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2286 : @[Reg.scala 28:19] + _T_2287 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2297 @[dec_tlu_ctl.scala 2433:9] - node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2438:63] - node _T_2299 = eq(_T_2298, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2438:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2438:41] - node _T_2300 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2439:80] - reg _T_2301 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2300 : @[Reg.scala 28:19] - _T_2301 <= event_saturate_r @[Reg.scala 28:23] + mhpme3 <= _T_2287 @[dec_tlu_ctl.scala 2415:9] + node _T_2288 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2420:63] + node _T_2289 = eq(_T_2288, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2420:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2289) @[dec_tlu_ctl.scala 2420:41] + node _T_2290 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2421:80] + reg _T_2291 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2290 : @[Reg.scala 28:19] + _T_2291 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2301 @[dec_tlu_ctl.scala 2439:9] - node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2445:63] - node _T_2303 = eq(_T_2302, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2445:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2445:41] - node _T_2304 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2446:80] - reg _T_2305 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2304 : @[Reg.scala 28:19] - _T_2305 <= event_saturate_r @[Reg.scala 28:23] + mhpme4 <= _T_2291 @[dec_tlu_ctl.scala 2421:9] + node _T_2292 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2427:63] + node _T_2293 = eq(_T_2292, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2427:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2293) @[dec_tlu_ctl.scala 2427:41] + node _T_2294 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2428:80] + reg _T_2295 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2294 : @[Reg.scala 28:19] + _T_2295 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2305 @[dec_tlu_ctl.scala 2446:9] - node _T_2306 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2452:63] - node _T_2307 = eq(_T_2306, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2452:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2307) @[dec_tlu_ctl.scala 2452:41] - node _T_2308 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2453:80] - reg _T_2309 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2308 : @[Reg.scala 28:19] - _T_2309 <= event_saturate_r @[Reg.scala 28:23] + mhpme5 <= _T_2295 @[dec_tlu_ctl.scala 2428:9] + node _T_2296 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2434:63] + node _T_2297 = eq(_T_2296, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2434:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2297) @[dec_tlu_ctl.scala 2434:41] + node _T_2298 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2435:80] + reg _T_2299 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2298 : @[Reg.scala 28:19] + _T_2299 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2309 @[dec_tlu_ctl.scala 2453:9] - node _T_2310 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2469:70] - node _T_2311 = eq(_T_2310, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2469:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2311) @[dec_tlu_ctl.scala 2469:48] - node _T_2312 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2471:54] + mhpme6 <= _T_2299 @[dec_tlu_ctl.scala 2435:9] + node _T_2300 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2451:70] + node _T_2301 = eq(_T_2300, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2451:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2301) @[dec_tlu_ctl.scala 2451:48] + node _T_2302 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2453:54] wire temp_ncount0 : UInt<1> - temp_ncount0 <= _T_2312 - node _T_2313 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2472:54] + temp_ncount0 <= _T_2302 + node _T_2303 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2454:54] wire temp_ncount1 : UInt<1> - temp_ncount1 <= _T_2313 - node _T_2314 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2473:55] + temp_ncount1 <= _T_2303 + node _T_2304 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2455:55] wire temp_ncount6_2 : UInt<5> - temp_ncount6_2 <= _T_2314 - node _T_2315 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2474:74] - node _T_2316 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2474:103] - reg _T_2317 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2316 : @[Reg.scala 28:19] - _T_2317 <= _T_2315 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2304 + node _T_2305 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2456:74] + node _T_2306 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2456:103] + reg _T_2307 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2306 : @[Reg.scala 28:19] + _T_2307 <= _T_2305 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2317 @[dec_tlu_ctl.scala 2474:17] - node _T_2318 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2476:72] - node _T_2319 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2476:99] - reg _T_2320 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2319 : @[Reg.scala 28:19] - _T_2320 <= _T_2318 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2307 @[dec_tlu_ctl.scala 2456:17] + node _T_2308 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2458:72] + node _T_2309 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2458:99] + reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2309 : @[Reg.scala 28:19] + _T_2310 <= _T_2308 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2320 @[dec_tlu_ctl.scala 2476:15] - node _T_2321 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2322 = cat(_T_2321, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2322 @[dec_tlu_ctl.scala 2477:16] - node _T_2323 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2484:51] - node _T_2324 = or(_T_2323, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2484:78] - node _T_2325 = or(_T_2324, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2484:104] - node _T_2326 = or(_T_2325, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2484:130] - node _T_2327 = or(_T_2326, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2485:32] - node _T_2328 = or(_T_2327, io.clk_override) @[dec_tlu_ctl.scala 2485:59] - node _T_2329 = bits(_T_2328, 0, 0) @[dec_tlu_ctl.scala 2485:78] + temp_ncount0 <= _T_2310 @[dec_tlu_ctl.scala 2458:15] + node _T_2311 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2312 = cat(_T_2311, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2312 @[dec_tlu_ctl.scala 2459:16] + node _T_2313 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2466:51] + node _T_2314 = or(_T_2313, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2466:78] + node _T_2315 = or(_T_2314, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2466:104] + node _T_2316 = or(_T_2315, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2466:130] + node _T_2317 = or(_T_2316, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2467:32] + node _T_2318 = or(_T_2317, io.clk_override) @[dec_tlu_ctl.scala 2467:59] + node _T_2319 = bits(_T_2318, 0, 0) @[dec_tlu_ctl.scala 2467:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_34.io.en <= _T_2329 @[lib.scala 345:16] + rvclkhdr_34.io.en <= _T_2319 @[lib.scala 345:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] - _T_2330 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2487:62] - io.dec_tlu_i0_valid_wb1 <= _T_2330 @[dec_tlu_ctl.scala 2487:30] - node _T_2331 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2488:91] - node _T_2332 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2488:137] - node _T_2333 = and(io.trigger_hit_r_d1, _T_2332) @[dec_tlu_ctl.scala 2488:135] - node _T_2334 = or(_T_2331, _T_2333) @[dec_tlu_ctl.scala 2488:112] - reg _T_2335 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] - _T_2335 <= _T_2334 @[dec_tlu_ctl.scala 2488:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2335 @[dec_tlu_ctl.scala 2488:30] - reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] - _T_2336 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2489:62] - io.dec_tlu_exc_cause_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2489:30] - reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] - _T_2337 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2490:62] - io.dec_tlu_int_valid_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2490:30] - io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2492:24] - node _T_2338 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2498:61] - node _T_2339 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2499:42] - node _T_2340 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2500:40] - node _T_2341 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2501:39] - node _T_2342 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2502:40] - node _T_2343 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2344 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:40] - node _T_2345 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2503:103] - node _T_2346 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:128] - node _T_2347 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] - node _T_2348 = cat(_T_2347, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2349 = cat(UInt<3>("h00"), _T_2345) @[Cat.scala 29:58] - node _T_2350 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2351 = cat(_T_2350, _T_2349) @[Cat.scala 29:58] - node _T_2352 = cat(_T_2351, _T_2348) @[Cat.scala 29:58] - node _T_2353 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:38] - node _T_2354 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2504:70] - node _T_2355 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:96] - node _T_2356 = cat(_T_2354, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2357 = cat(_T_2356, _T_2355) @[Cat.scala 29:58] - node _T_2358 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2505:36] - node _T_2359 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2505:78] - node _T_2360 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2505:102] - node _T_2361 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2505:123] - node _T_2362 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2505:144] - node _T_2363 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2364 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2365 = cat(_T_2364, _T_2363) @[Cat.scala 29:58] - node _T_2366 = cat(_T_2360, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2367 = cat(UInt<1>("h00"), _T_2359) @[Cat.scala 29:58] - node _T_2368 = cat(_T_2367, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2369 = cat(_T_2368, _T_2366) @[Cat.scala 29:58] - node _T_2370 = cat(_T_2369, _T_2365) @[Cat.scala 29:58] - node _T_2371 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2506:36] - node _T_2372 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2506:75] - node _T_2373 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2506:96] - node _T_2374 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2506:114] - node _T_2375 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2506:132] - node _T_2376 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2377 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2378 = cat(_T_2377, _T_2376) @[Cat.scala 29:58] - node _T_2379 = cat(_T_2373, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2380 = cat(UInt<1>("h00"), _T_2372) @[Cat.scala 29:58] - node _T_2381 = cat(_T_2380, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2382 = cat(_T_2381, _T_2379) @[Cat.scala 29:58] - node _T_2383 = cat(_T_2382, _T_2378) @[Cat.scala 29:58] - node _T_2384 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2507:40] - node _T_2385 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2507:65] - node _T_2386 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2508:40] - node _T_2387 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2508:69] - node _T_2388 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2509:42] - node _T_2389 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2509:72] - node _T_2390 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2510:42] - node _T_2391 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2510:72] - node _T_2392 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2511:41] - node _T_2393 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2511:66] - node _T_2394 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2512:37] - node _T_2395 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2396 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2513:39] - node _T_2397 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2513:64] - node _T_2398 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2514:40] - node _T_2399 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2514:80] - node _T_2400 = cat(UInt<28>("h00"), _T_2399) @[Cat.scala 29:58] - node _T_2401 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2515:38] - node _T_2402 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2515:63] - node _T_2403 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2516:37] - node _T_2404 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2516:62] - node _T_2405 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2517:39] - node _T_2406 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2517:64] - node _T_2407 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2518:38] - node _T_2408 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2409 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2519:39] - node _T_2410 = cat(meivt, meihap) @[Cat.scala 29:58] - node _T_2411 = cat(_T_2410, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2412 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] - node _T_2413 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] - node _T_2414 = cat(UInt<28>("h00"), _T_2413) @[Cat.scala 29:58] - node _T_2415 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] - node _T_2416 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] - node _T_2417 = cat(UInt<28>("h00"), _T_2416) @[Cat.scala 29:58] - node _T_2418 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2522:38] - node _T_2419 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2522:78] - node _T_2420 = cat(UInt<28>("h00"), _T_2419) @[Cat.scala 29:58] - node _T_2421 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2523:37] - node _T_2422 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2523:77] - node _T_2423 = cat(UInt<23>("h00"), _T_2422) @[Cat.scala 29:58] - node _T_2424 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2524:37] - node _T_2425 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2524:77] - node _T_2426 = cat(UInt<13>("h00"), _T_2425) @[Cat.scala 29:58] - node _T_2427 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2525:37] - node _T_2428 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2525:85] - node _T_2429 = cat(UInt<16>("h04000"), _T_2428) @[Cat.scala 29:58] - node _T_2430 = cat(_T_2429, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2431 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2526:36] - node _T_2432 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2433 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2527:39] - node _T_2434 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2527:64] - node _T_2435 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2528:40] - node _T_2436 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2528:65] - node _T_2437 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2529:39] - node _T_2438 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2529:64] - node _T_2439 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2530:41] - node _T_2440 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2530:80] - node _T_2441 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2530:104] - node _T_2442 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2530:131] - node _T_2443 = cat(UInt<3>("h00"), _T_2442) @[Cat.scala 29:58] - node _T_2444 = cat(_T_2443, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2445 = cat(UInt<2>("h00"), _T_2441) @[Cat.scala 29:58] - node _T_2446 = cat(UInt<7>("h00"), _T_2440) @[Cat.scala 29:58] - node _T_2447 = cat(_T_2446, _T_2445) @[Cat.scala 29:58] - node _T_2448 = cat(_T_2447, _T_2444) @[Cat.scala 29:58] - node _T_2449 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2531:38] - node _T_2450 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2531:78] - node _T_2451 = cat(UInt<30>("h00"), _T_2450) @[Cat.scala 29:58] - node _T_2452 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2532:40] - node _T_2453 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] - node _T_2454 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2533:40] - node _T_2455 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] - node _T_2456 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2534:39] - node _T_2457 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2534:64] - node _T_2458 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] - node _T_2459 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] - node _T_2460 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] - node _T_2461 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] - node _T_2462 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2537:39] - node _T_2463 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2537:64] - node _T_2464 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2538:39] - node _T_2465 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2538:64] - node _T_2466 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2539:39] - node _T_2467 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2539:64] - node _T_2468 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2540:39] - node _T_2469 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2540:64] - node _T_2470 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2541:40] - node _T_2471 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2541:65] - node _T_2472 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2542:40] - node _T_2473 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2542:65] - node _T_2474 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2543:40] - node _T_2475 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2543:65] - node _T_2476 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2544:40] - node _T_2477 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2544:65] - node _T_2478 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2545:38] - node _T_2479 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2545:78] - node _T_2480 = cat(UInt<26>("h00"), _T_2479) @[Cat.scala 29:58] - node _T_2481 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2546:38] - node _T_2482 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2546:78] - node _T_2483 = cat(UInt<30>("h00"), _T_2482) @[Cat.scala 29:58] - node _T_2484 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2547:39] - node _T_2485 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2547:79] - node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58] - node _T_2487 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2548:39] - node _T_2488 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2548:79] - node _T_2489 = cat(UInt<22>("h00"), _T_2488) @[Cat.scala 29:58] - node _T_2490 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2549:39] - node _T_2491 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2549:78] - node _T_2492 = cat(UInt<22>("h00"), _T_2491) @[Cat.scala 29:58] - node _T_2493 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2550:39] - node _T_2494 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2550:78] - node _T_2495 = cat(UInt<22>("h00"), _T_2494) @[Cat.scala 29:58] - node _T_2496 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2551:46] - node _T_2497 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2551:86] - node _T_2498 = cat(UInt<25>("h00"), _T_2497) @[Cat.scala 29:58] - node _T_2499 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2552:37] - node _T_2500 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] - node _T_2501 = cat(_T_2500, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2502 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2553:37] - node _T_2503 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2553:76] - node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2507 = mux(_T_2341, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2511 = mux(_T_2358, _T_2370, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2512 = mux(_T_2371, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2513 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2514 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2515 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2516 = mux(_T_2390, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2517 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2518 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2519 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2520 = mux(_T_2398, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2521 = mux(_T_2401, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2522 = mux(_T_2403, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2523 = mux(_T_2405, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2524 = mux(_T_2407, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2525 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2526 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2527 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2528 = mux(_T_2418, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2529 = mux(_T_2421, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2530 = mux(_T_2424, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2531 = mux(_T_2427, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2532 = mux(_T_2431, _T_2432, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2533 = mux(_T_2433, _T_2434, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2534 = mux(_T_2435, _T_2436, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2535 = mux(_T_2437, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2536 = mux(_T_2439, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2537 = mux(_T_2449, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2538 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2539 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2540 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2541 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2542 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2543 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2544 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2545 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2546 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2547 = mux(_T_2470, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2548 = mux(_T_2472, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2549 = mux(_T_2474, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2550 = mux(_T_2476, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2551 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2552 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2553 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2554 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2555 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2556 = mux(_T_2493, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2557 = mux(_T_2496, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2558 = mux(_T_2499, _T_2501, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2559 = mux(_T_2502, _T_2503, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2560 = or(_T_2504, _T_2505) @[Mux.scala 27:72] + reg _T_2320 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2469:62] + _T_2320 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2469:62] + io.dec_tlu_i0_valid_wb1 <= _T_2320 @[dec_tlu_ctl.scala 2469:30] + node _T_2321 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2470:91] + node _T_2322 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2470:137] + node _T_2323 = and(io.trigger_hit_r_d1, _T_2322) @[dec_tlu_ctl.scala 2470:135] + node _T_2324 = or(_T_2321, _T_2323) @[dec_tlu_ctl.scala 2470:112] + reg _T_2325 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2470:62] + _T_2325 <= _T_2324 @[dec_tlu_ctl.scala 2470:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2325 @[dec_tlu_ctl.scala 2470:30] + reg _T_2326 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2471:62] + _T_2326 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2471:62] + io.dec_tlu_exc_cause_wb1 <= _T_2326 @[dec_tlu_ctl.scala 2471:30] + reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2472:62] + _T_2327 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2472:62] + io.dec_tlu_int_valid_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2472:30] + io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2474:24] + node _T_2328 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2480:61] + node _T_2329 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2481:42] + node _T_2330 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2482:40] + node _T_2331 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2483:39] + node _T_2332 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2484:40] + node _T_2333 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2334 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:40] + node _T_2335 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2485:103] + node _T_2336 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:128] + node _T_2337 = cat(UInt<3>("h00"), _T_2336) @[Cat.scala 29:58] + node _T_2338 = cat(_T_2337, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2339 = cat(UInt<3>("h00"), _T_2335) @[Cat.scala 29:58] + node _T_2340 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2341 = cat(_T_2340, _T_2339) @[Cat.scala 29:58] + node _T_2342 = cat(_T_2341, _T_2338) @[Cat.scala 29:58] + node _T_2343 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:38] + node _T_2344 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2486:70] + node _T_2345 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:96] + node _T_2346 = cat(_T_2344, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2347 = cat(_T_2346, _T_2345) @[Cat.scala 29:58] + node _T_2348 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2487:36] + node _T_2349 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2487:78] + node _T_2350 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2487:102] + node _T_2351 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2487:123] + node _T_2352 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2487:144] + node _T_2353 = cat(_T_2352, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2354 = cat(_T_2351, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2355 = cat(_T_2354, _T_2353) @[Cat.scala 29:58] + node _T_2356 = cat(_T_2350, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2357 = cat(UInt<1>("h00"), _T_2349) @[Cat.scala 29:58] + node _T_2358 = cat(_T_2357, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2359 = cat(_T_2358, _T_2356) @[Cat.scala 29:58] + node _T_2360 = cat(_T_2359, _T_2355) @[Cat.scala 29:58] + node _T_2361 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2488:36] + node _T_2362 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2488:75] + node _T_2363 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2488:96] + node _T_2364 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2488:114] + node _T_2365 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2488:132] + node _T_2366 = cat(_T_2365, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2367 = cat(_T_2364, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2368 = cat(_T_2367, _T_2366) @[Cat.scala 29:58] + node _T_2369 = cat(_T_2363, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2370 = cat(UInt<1>("h00"), _T_2362) @[Cat.scala 29:58] + node _T_2371 = cat(_T_2370, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2372 = cat(_T_2371, _T_2369) @[Cat.scala 29:58] + node _T_2373 = cat(_T_2372, _T_2368) @[Cat.scala 29:58] + node _T_2374 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2489:40] + node _T_2375 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2489:65] + node _T_2376 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2490:40] + node _T_2377 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2490:69] + node _T_2378 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2491:42] + node _T_2379 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2491:72] + node _T_2380 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2492:42] + node _T_2381 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2492:72] + node _T_2382 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2493:41] + node _T_2383 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2493:66] + node _T_2384 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2494:37] + node _T_2385 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2386 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2495:39] + node _T_2387 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2495:64] + node _T_2388 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2496:40] + node _T_2389 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2496:80] + node _T_2390 = cat(UInt<28>("h00"), _T_2389) @[Cat.scala 29:58] + node _T_2391 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2497:38] + node _T_2392 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2497:63] + node _T_2393 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2498:37] + node _T_2394 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2498:62] + node _T_2395 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2499:39] + node _T_2396 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2499:64] + node _T_2397 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2500:38] + node _T_2398 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2399 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2501:39] + node _T_2400 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2401 = cat(_T_2400, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2402 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2502:41] + node _T_2403 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2502:81] + node _T_2404 = cat(UInt<28>("h00"), _T_2403) @[Cat.scala 29:58] + node _T_2405 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2503:41] + node _T_2406 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2503:81] + node _T_2407 = cat(UInt<28>("h00"), _T_2406) @[Cat.scala 29:58] + node _T_2408 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2504:38] + node _T_2409 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2504:78] + node _T_2410 = cat(UInt<28>("h00"), _T_2409) @[Cat.scala 29:58] + node _T_2411 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2505:37] + node _T_2412 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2505:77] + node _T_2413 = cat(UInt<23>("h00"), _T_2412) @[Cat.scala 29:58] + node _T_2414 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2506:37] + node _T_2415 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2506:77] + node _T_2416 = cat(UInt<13>("h00"), _T_2415) @[Cat.scala 29:58] + node _T_2417 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2507:37] + node _T_2418 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2507:85] + node _T_2419 = cat(UInt<16>("h04000"), _T_2418) @[Cat.scala 29:58] + node _T_2420 = cat(_T_2419, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2421 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2508:36] + node _T_2422 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2423 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2509:39] + node _T_2424 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2509:64] + node _T_2425 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2510:40] + node _T_2426 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2510:65] + node _T_2427 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2511:39] + node _T_2428 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2511:64] + node _T_2429 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2512:41] + node _T_2430 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2512:80] + node _T_2431 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2512:104] + node _T_2432 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2512:131] + node _T_2433 = cat(UInt<3>("h00"), _T_2432) @[Cat.scala 29:58] + node _T_2434 = cat(_T_2433, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2435 = cat(UInt<2>("h00"), _T_2431) @[Cat.scala 29:58] + node _T_2436 = cat(UInt<7>("h00"), _T_2430) @[Cat.scala 29:58] + node _T_2437 = cat(_T_2436, _T_2435) @[Cat.scala 29:58] + node _T_2438 = cat(_T_2437, _T_2434) @[Cat.scala 29:58] + node _T_2439 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2513:38] + node _T_2440 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2513:78] + node _T_2441 = cat(UInt<30>("h00"), _T_2440) @[Cat.scala 29:58] + node _T_2442 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2514:40] + node _T_2443 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2514:74] + node _T_2444 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2515:40] + node _T_2445 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2515:74] + node _T_2446 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2516:39] + node _T_2447 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2516:64] + node _T_2448 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2517:41] + node _T_2449 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2517:66] + node _T_2450 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2518:41] + node _T_2451 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2518:66] + node _T_2452 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2519:39] + node _T_2453 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2519:64] + node _T_2454 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2520:39] + node _T_2455 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2520:64] + node _T_2456 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2521:39] + node _T_2457 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2521:64] + node _T_2458 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2522:39] + node _T_2459 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2522:64] + node _T_2460 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2523:40] + node _T_2461 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2523:65] + node _T_2462 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2524:40] + node _T_2463 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2524:65] + node _T_2464 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2525:40] + node _T_2465 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2525:65] + node _T_2466 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2526:40] + node _T_2467 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2526:65] + node _T_2468 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2527:38] + node _T_2469 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2527:78] + node _T_2470 = cat(UInt<26>("h00"), _T_2469) @[Cat.scala 29:58] + node _T_2471 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2528:38] + node _T_2472 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2528:78] + node _T_2473 = cat(UInt<30>("h00"), _T_2472) @[Cat.scala 29:58] + node _T_2474 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2529:39] + node _T_2475 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2529:79] + node _T_2476 = cat(UInt<22>("h00"), _T_2475) @[Cat.scala 29:58] + node _T_2477 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2530:39] + node _T_2478 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2530:79] + node _T_2479 = cat(UInt<22>("h00"), _T_2478) @[Cat.scala 29:58] + node _T_2480 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2531:39] + node _T_2481 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2531:78] + node _T_2482 = cat(UInt<22>("h00"), _T_2481) @[Cat.scala 29:58] + node _T_2483 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2532:39] + node _T_2484 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2532:78] + node _T_2485 = cat(UInt<22>("h00"), _T_2484) @[Cat.scala 29:58] + node _T_2486 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2533:46] + node _T_2487 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2533:86] + node _T_2488 = cat(UInt<25>("h00"), _T_2487) @[Cat.scala 29:58] + node _T_2489 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2534:37] + node _T_2490 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2491 = cat(_T_2490, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2492 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2535:37] + node _T_2493 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2535:76] + node _T_2494 = mux(_T_2328, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2495 = mux(_T_2329, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2496 = mux(_T_2330, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2497 = mux(_T_2331, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2498 = mux(_T_2332, _T_2333, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2499 = mux(_T_2334, _T_2342, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2500 = mux(_T_2343, _T_2347, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2501 = mux(_T_2348, _T_2360, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2502 = mux(_T_2361, _T_2373, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2503 = mux(_T_2374, _T_2375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2504 = mux(_T_2376, _T_2377, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2505 = mux(_T_2378, _T_2379, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2380, _T_2381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2382, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2388, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2399, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2402, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2405, _T_2407, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2408, _T_2410, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2411, _T_2413, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2414, _T_2416, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2417, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2421, _T_2422, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2423, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2425, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2427, _T_2428, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2429, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2439, _T_2441, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2442, _T_2443, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2444, _T_2445, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2446, _T_2447, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2448, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2450, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2468, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2471, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2474, _T_2476, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2477, _T_2479, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2480, _T_2482, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2483, _T_2485, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2486, _T_2488, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2489, _T_2491, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2492, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = or(_T_2494, _T_2495) @[Mux.scala 27:72] + node _T_2551 = or(_T_2550, _T_2496) @[Mux.scala 27:72] + node _T_2552 = or(_T_2551, _T_2497) @[Mux.scala 27:72] + node _T_2553 = or(_T_2552, _T_2498) @[Mux.scala 27:72] + node _T_2554 = or(_T_2553, _T_2499) @[Mux.scala 27:72] + node _T_2555 = or(_T_2554, _T_2500) @[Mux.scala 27:72] + node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72] + node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72] + node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72] + node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72] + node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72] node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] @@ -76166,1700 +76166,1690 @@ circuit quasar_wrapper : node _T_2602 = or(_T_2601, _T_2547) @[Mux.scala 27:72] node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72] node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72] - node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72] - node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72] - node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72] - node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72] - node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72] - node _T_2610 = or(_T_2609, _T_2555) @[Mux.scala 27:72] - node _T_2611 = or(_T_2610, _T_2556) @[Mux.scala 27:72] - node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72] - node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72] - node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72] - wire _T_2615 : UInt @[Mux.scala 27:72] - _T_2615 <= _T_2614 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2615 @[dec_tlu_ctl.scala 2497:21] + wire _T_2605 : UInt @[Mux.scala 27:72] + _T_2605 <= _T_2604 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2605 @[dec_tlu_ctl.scala 2479:21] module dec_decode_csr_read : input clock : Clock input reset : AsyncReset output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} - node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2569:198] - node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2569:198] - node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2569:198] - node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2571:57] - node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2569:198] - node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2569:198] - node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2572:57] - node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2569:198] - node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2569:198] - node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2573:57] - node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2569:198] - node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2569:198] - node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2574:57] - node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2569:198] - node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2575:57] - node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2569:198] - node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2569:198] - node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2569:198] - node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2576:57] - node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2569:198] - node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2569:198] - node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2569:198] - node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2577:57] - node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2569:198] - node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2578:65] - node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2569:198] - node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2569:198] - node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2569:198] - node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2579:65] - node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2569:198] - node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2569:198] - node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2569:198] - node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2569:198] - node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2580:57] - node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2569:198] - node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2569:198] - node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2569:198] - node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2569:198] - node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2569:198] - node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2581:57] - node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2569:198] - node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2569:198] - node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2569:198] - node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2569:198] - node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2569:198] - node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2582:57] - node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2569:198] - node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2569:198] - node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2569:198] - node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2569:198] - node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2569:198] - node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2583:57] - node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2569:198] - node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2569:198] - node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2569:198] - node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2584:57] - node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2569:198] - node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2569:198] - node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2585:57] - node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2569:198] - node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2569:198] - node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2586:57] - node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2569:198] - node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2587:57] - node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2569:198] - node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2569:198] - node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2588:57] - node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2569:198] - node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2569:198] - node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2569:198] - node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2569:198] - node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2589:57] - node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2569:198] - node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2569:198] - node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2569:198] - node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2590:57] - node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2569:198] - node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2569:198] - node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2591:57] - node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2569:198] - node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2592:57] - node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2569:198] - node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2569:198] - node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2569:198] - node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2569:198] - node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2593:57] - node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2569:198] - node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2569:198] - node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2594:57] - node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2569:198] - node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2595:57] - node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2569:198] - node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2569:198] - node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2596:57] - node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2569:198] - node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2569:198] - node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2569:198] - node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2597:57] - node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2569:198] - node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2569:198] - node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2598:57] - node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2569:198] - node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2569:198] - node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2569:198] - node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2599:57] - node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2569:198] - node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2569:198] - node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2569:198] - node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2600:65] - node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2569:198] - node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2569:198] - node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2569:198] - node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2601:57] - node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2569:198] - node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2569:198] - node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2602:57] - node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2569:198] - node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2569:198] - node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2603:57] - node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2569:198] - node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2569:198] - node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2569:198] - node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2569:198] - node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2604:57] - node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2569:198] - node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2569:198] - node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2569:198] - node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2569:198] - node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2569:198] - node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2605:57] - node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2569:198] - node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2569:198] - node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2569:198] - node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2569:198] - node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2606:57] - node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2569:198] - node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2569:198] - node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2569:198] - node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2569:198] - node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2569:198] - node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2607:57] - node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2569:198] - node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2569:198] - node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2569:198] - node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2569:198] - node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2608:57] - node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2569:198] - node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2569:198] - node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2569:198] - node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2569:198] - node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2569:198] - node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2609:57] - node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2569:198] - node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2569:198] - node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2569:198] - node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2569:198] - node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2610:57] - node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2569:198] - node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2569:198] - node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2569:198] - node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2569:198] - node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2569:198] - node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2611:57] - node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2569:198] - node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2569:198] - node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2569:198] - node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2569:198] - node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2612:57] - node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2569:198] - node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2569:198] - node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2569:198] - node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2569:198] - node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2613:57] - node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2569:198] - node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2569:198] - node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2569:198] - node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2569:198] - node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2614:57] - node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2569:198] - node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2569:198] - node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2569:198] - node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2569:198] - node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2615:57] - node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2569:198] - node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2569:198] - node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2569:198] - node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2569:198] - node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2616:49] - node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2569:198] - node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2569:198] - node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2569:198] - node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2617:57] - node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2569:198] - node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2569:198] - node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2569:198] - node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2618:57] - node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2569:198] - node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2569:198] - node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2569:198] - node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2619:57] - node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2569:198] - node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2569:198] - node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2569:198] - node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2620:57] - node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2569:198] - node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2569:198] - node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2569:198] - node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2621:57] - node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2569:198] - node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2569:198] - node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2622:57] - node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2569:198] - node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2569:198] - node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2569:198] - node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2623:57] - node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2569:198] - node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2569:198] - node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2569:198] - node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2569:198] - node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2624:57] - node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2569:198] - node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2569:198] - node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2625:57] - node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2569:198] - node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2569:198] - node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2626:57] - node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2569:198] - node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2569:198] - node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2569:198] - node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2627:57] - node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2569:198] - node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2569:198] - node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2628:57] - node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2569:198] - node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2569:198] - node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2629:57] - node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2569:198] - node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2569:198] - node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2569:198] - node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2630:57] - node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2569:198] - node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2569:198] - node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2631:57] - node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2569:198] - node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2569:198] - node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2569:198] - node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2569:198] - node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2632:57] - node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2569:198] - node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2569:198] - node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2633:57] - node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2569:198] - node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2569:198] - node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2569:198] - node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2634:57] - node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2569:198] - node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2569:198] - node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2569:198] - node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2635:57] - node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2569:198] - node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2569:198] - node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2569:198] - node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2569:198] - io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2636:57] - node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2569:198] - node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2569:198] - node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2569:198] - node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2569:198] - node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2569:198] - node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2569:198] - node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2569:198] - node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2569:198] - node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2569:198] - node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2637:81] - node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2569:198] - node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2569:198] - node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2569:198] - node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2569:198] - node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2569:198] - node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2637:121] - node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2569:198] - node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2569:198] - node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2569:198] - node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2569:198] - node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2637:155] - node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2569:198] - node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2569:198] - node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2569:198] - node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2569:198] - node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2638:97] - node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2569:198] - node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2569:198] - node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2569:198] - node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2569:198] - node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2569:198] - node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2638:137] - io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2637:34] - node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2569:198] - node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2569:198] - node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2569:198] - node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2569:198] - node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2569:198] - node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2569:198] - node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2569:198] - node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2569:198] - node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2639:81] - node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2569:198] - node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2569:198] - node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2569:198] - node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2639:121] - node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2569:198] - node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2569:198] - node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2569:198] - node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2639:162] - node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2569:198] - node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2569:198] - node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2569:198] - node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2569:198] - node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2569:198] - node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2569:198] - node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2640:105] - node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2569:198] - node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2569:198] - node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2569:198] - node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2569:198] - node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2569:198] - node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2640:145] - node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2569:198] - node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2569:198] - node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2569:198] - node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2569:198] - node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2640:178] - io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2639:30] - node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2569:198] - node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2569:198] - node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2569:198] - node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2569:198] - node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2569:198] - node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2569:198] - node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2569:198] - node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2569:198] - node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2569:198] - node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2569:198] - node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2569:198] - node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2569:198] - node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2569:198] - node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2569:198] - node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2569:198] - node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2569:198] - node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2569:198] - node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2569:198] - node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2569:198] - node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2642:81] - node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2569:198] - node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2569:198] - node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2569:198] - node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2569:198] - node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2569:198] - node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2569:198] - node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2569:198] - node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2569:198] - node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2642:129] - node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2569:198] - node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2569:198] - node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2569:198] - node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2569:198] - node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2569:198] - node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2569:198] - node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2569:198] - node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2569:198] - node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2569:198] - node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2643:105] - node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2569:198] - node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2569:198] - node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2569:198] - node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2569:198] - node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2569:198] - node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2569:198] - node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2643:153] - node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2569:198] - node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2569:198] - node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2569:198] - node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2569:198] - node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2569:198] - node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2569:198] - node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2569:198] - node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2569:198] - node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2569:198] - node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2569:198] - node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2569:198] - node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2644:105] - node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2569:198] - node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2569:198] - node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2569:198] - node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2569:198] - node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2569:198] - node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2569:198] - node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2569:198] - node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2569:198] - node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2569:198] - node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2644:153] - node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2569:198] - node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2569:198] - node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2569:198] - node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2569:198] - node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2569:198] - node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2569:198] - node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2569:198] - node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2569:198] - node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2569:198] - node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2645:105] - node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2569:198] - node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2569:198] - node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2569:198] - node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2569:198] - node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2569:198] - node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2569:198] - node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2569:198] - node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2569:198] - node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2569:198] - node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2645:161] - node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2569:198] - node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2569:198] - node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2569:198] - node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2569:198] - node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2569:198] - node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2569:198] - node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2569:198] - node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2646:105] - node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2569:198] - node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2569:198] - node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2569:198] - node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2569:198] - node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2569:198] - node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2569:198] - node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2569:198] - node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2569:198] - node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2569:198] - node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2569:198] - node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2646:161] - node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2569:198] - node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2569:198] - node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2569:198] - node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2569:198] - node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2569:198] - node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2569:198] - node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2569:198] - node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2569:198] - node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2569:198] - node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2647:97] - node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2569:198] - node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2569:198] - node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2569:198] - node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2569:198] - node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2569:198] - node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2569:198] - node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2569:198] - node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2569:198] - node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2569:198] - node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2647:153] - node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2569:198] - node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2569:198] - node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2569:198] - node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2569:198] - node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2569:198] - node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2569:198] - node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2569:198] - node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2569:198] - node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2569:198] - node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2648:105] - node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] - node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2569:198] - node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2569:198] - node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2569:198] - node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2569:198] - node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2569:198] - node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2569:198] - node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2569:198] - node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2569:198] - node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2648:161] - node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2569:198] - node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2569:198] - node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2569:198] - node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2569:198] - node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2569:198] - node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2569:198] - node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2569:198] - node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2569:198] - node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2649:105] - node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2569:198] - node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2569:198] - node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2569:198] - node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2569:198] - node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2569:198] - node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2569:198] - node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2569:198] - node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2569:198] - node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2569:198] - node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2649:161] - node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] - node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2569:198] - node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2569:198] - node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2569:198] - node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2569:198] - node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2569:198] - node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2569:198] - node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2650:105] - node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2569:198] - node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2569:198] - node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2569:198] - node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2569:198] - node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2569:198] - node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2569:198] - node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2569:198] - node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2569:198] - node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2569:198] - node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2650:161] - node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2569:198] - node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2569:198] - node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2569:198] - node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2569:198] - node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2569:198] - node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2569:198] - node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2569:198] - node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2569:198] - node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2651:105] - node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2569:198] - node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2569:198] - node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2569:198] - node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2569:198] - node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2569:198] - node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2569:198] - node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2569:198] - node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2569:198] - node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2569:198] - node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2651:161] - node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] - node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] - node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2569:198] - node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2569:198] - node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2569:198] - node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2569:198] - node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2569:198] - node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2569:198] - node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2569:198] - node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2569:198] - node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2569:198] - node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2569:198] - node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2652:105] - node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] - node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2569:198] - node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2569:198] - node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2569:198] - node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2569:198] - node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2569:198] - node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2569:198] - node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2652:153] - node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] - node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] - node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2569:198] - node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2569:198] - node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2569:198] - node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2569:198] - node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2569:198] - node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2569:198] - node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2569:198] - node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2569:198] - node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2569:198] - node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2653:113] - node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] - node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] - node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] - node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] - node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] - node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2569:198] - node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2569:198] - node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2569:198] - node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2569:198] - node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2569:198] - node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2569:198] - node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2569:198] - node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2569:198] - node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2569:198] - node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2653:161] - node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2569:198] - node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2569:198] - node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2569:198] - node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2569:198] - node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2569:198] - node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2569:198] - node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2569:198] - node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2654:97] - node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] - node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2569:198] - node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2569:198] - node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2569:198] - node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2569:198] - node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2569:198] - node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2569:198] - node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2654:153] - node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] - node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] - node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] - node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2569:198] - node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2569:198] - node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2569:198] - node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2569:198] - node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2569:198] - node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2569:198] - node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2569:198] - node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2655:113] - node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] - node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] - node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] - node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] - node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] - node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] - node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] - node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] - node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2569:198] - node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2569:198] - node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2569:198] - node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2569:198] - node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2569:198] - node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2569:198] - node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2655:169] - io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2642:26] + node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2551:198] + node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2551:198] + node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2551:198] + node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2553:57] + node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2551:198] + node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2551:198] + node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2554:57] + node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2551:198] + node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2551:198] + node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2555:57] + node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2551:198] + node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2551:198] + node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2556:57] + node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2551:198] + node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2557:57] + node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2551:198] + node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2551:198] + node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2551:198] + node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2558:57] + node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2551:198] + node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2551:198] + node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2551:198] + node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2559:57] + node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2551:198] + node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2560:65] + node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2551:198] + node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2551:198] + node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2551:198] + node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2561:65] + node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2551:198] + node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2551:198] + node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2551:198] + node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2551:198] + node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2562:57] + node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2551:198] + node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2551:198] + node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2551:198] + node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2551:198] + node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2551:198] + node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2563:57] + node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2551:198] + node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2551:198] + node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2551:198] + node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2551:198] + node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2551:198] + node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2564:57] + node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2551:198] + node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2551:198] + node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2551:198] + node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2551:198] + node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2551:198] + node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2565:57] + node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2551:198] + node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2551:198] + node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2551:198] + node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2566:57] + node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2551:198] + node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2551:198] + node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2567:57] + node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2551:198] + node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2551:198] + node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2568:57] + node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2551:198] + node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2569:57] + node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2551:198] + node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2551:198] + node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2570:57] + node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2551:198] + node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2551:198] + node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2551:198] + node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2551:198] + node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2571:57] + node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2551:198] + node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2551:198] + node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2551:198] + node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2572:57] + node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2551:198] + node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2551:198] + node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2573:57] + node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2551:198] + node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2574:57] + node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2551:198] + node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2551:198] + node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2551:198] + node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2551:198] + node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2575:57] + node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2551:198] + node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2551:198] + node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2576:57] + node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2551:198] + node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2577:57] + node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2551:198] + node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2551:198] + node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2578:57] + node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2551:198] + node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2551:198] + node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2551:198] + node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2579:57] + node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2551:198] + node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2551:198] + node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2580:57] + node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2551:198] + node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2551:198] + node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2551:198] + node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2581:57] + node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2551:198] + node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2551:198] + node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2551:198] + node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2582:65] + node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2551:198] + node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2551:198] + node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2551:198] + node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2583:57] + node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2551:198] + node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2551:198] + node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2584:57] + node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2551:198] + node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2551:198] + node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2585:57] + node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2551:198] + node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2551:198] + node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2551:198] + node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2551:198] + node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2586:57] + node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2551:198] + node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2551:198] + node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2551:198] + node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2551:198] + node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2551:198] + node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2587:57] + node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2551:198] + node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2551:198] + node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2551:198] + node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2551:198] + node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2588:57] + node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2551:198] + node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2551:198] + node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2551:198] + node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2551:198] + node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2551:198] + node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2589:57] + node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2551:198] + node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2551:198] + node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2551:198] + node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2551:198] + node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2590:57] + node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2551:198] + node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2551:198] + node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2551:198] + node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2551:198] + node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2551:198] + node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2591:57] + node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2551:198] + node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2551:198] + node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2551:198] + node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2551:198] + node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2592:57] + node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2551:198] + node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2551:198] + node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2551:198] + node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2551:198] + node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2551:198] + node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2593:57] + node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2551:198] + node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2551:198] + node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2551:198] + node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2551:198] + node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2594:57] + node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2551:198] + node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2551:198] + node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2551:198] + node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2551:198] + node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2595:57] + node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2551:198] + node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2551:198] + node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2551:198] + node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2551:198] + node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2596:57] + node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2551:198] + node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2551:198] + node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2551:198] + node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2551:198] + node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2597:57] + node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2551:198] + node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2551:198] + node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2551:198] + node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2551:198] + node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2598:49] + node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2551:198] + node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2551:198] + node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2551:198] + node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2599:57] + node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2551:198] + node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2551:198] + node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2551:198] + node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2600:57] + node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2551:198] + node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2551:198] + node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2551:198] + node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2601:57] + node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2551:198] + node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2551:198] + node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2551:198] + node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2602:57] + node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2551:198] + node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2551:198] + node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2551:198] + node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2603:57] + node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2551:198] + node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2551:198] + node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2604:57] + node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2551:198] + node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2551:198] + node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2551:198] + node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2605:57] + node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2551:198] + node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2551:198] + node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2551:198] + node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2551:198] + node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2606:57] + node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2551:198] + node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2551:198] + node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2607:57] + node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2551:198] + node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2551:198] + node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2608:57] + node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2551:198] + node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2551:198] + node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2551:198] + node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2609:57] + node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2551:198] + node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2551:198] + node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2610:57] + node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2551:198] + node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2551:198] + node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2611:57] + node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2551:198] + node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2551:198] + node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2551:198] + node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2612:57] + node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2551:198] + node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2551:198] + node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2613:57] + node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2551:198] + node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2551:198] + node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2551:198] + node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2551:198] + node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2614:57] + node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2551:198] + node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2551:198] + node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2615:57] + node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2551:198] + node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2551:198] + node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2551:198] + node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2616:57] + node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2551:198] + node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2551:198] + node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2551:198] + node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2617:57] + node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2551:198] + node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2551:198] + node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2551:198] + node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2551:198] + io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2618:57] + node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2551:198] + node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2551:198] + node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2551:198] + node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2551:198] + node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2551:198] + node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2551:198] + node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2551:198] + node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2551:198] + node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2551:198] + node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2619:81] + node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2551:198] + node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2551:198] + node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2551:198] + node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2551:198] + node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2551:198] + node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2619:121] + node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2551:198] + node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2551:198] + node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2551:198] + node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2551:198] + node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2619:155] + node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2551:198] + node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2551:198] + node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2551:198] + node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2551:198] + node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2620:97] + node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2551:198] + node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2551:198] + node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2551:198] + node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2551:198] + node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2551:198] + node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2620:137] + io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2619:34] + node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2551:198] + node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2551:198] + node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2551:198] + node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2551:198] + node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2551:198] + node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2551:198] + node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2551:198] + node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2551:198] + node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2621:81] + node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2551:198] + node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2551:198] + node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2551:198] + node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2621:121] + node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2551:198] + node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2551:198] + node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2551:198] + node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2621:162] + node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2551:198] + node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2551:198] + node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2551:198] + node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2551:198] + node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2551:198] + node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2551:198] + node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2622:105] + node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2551:198] + node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2551:198] + node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2551:198] + node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2551:198] + node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2551:198] + node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2622:145] + node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2551:198] + node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2551:198] + node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2551:198] + node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2551:198] + node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2622:178] + io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2621:30] + node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2551:198] + node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2551:198] + node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2551:198] + node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2551:198] + node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2551:198] + node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2551:198] + node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2551:198] + node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2551:198] + node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2551:198] + node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2551:198] + node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2551:198] + node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2551:198] + node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2551:198] + node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2551:198] + node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2551:198] + node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2551:198] + node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2551:198] + node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2551:198] + node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2551:198] + node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2624:81] + node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2551:198] + node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2551:198] + node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2551:198] + node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2551:198] + node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2551:198] + node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2551:198] + node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2551:198] + node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2551:198] + node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2624:129] + node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2551:198] + node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2551:198] + node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2551:198] + node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2551:198] + node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2551:198] + node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2551:198] + node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2551:198] + node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2551:198] + node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2551:198] + node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2625:105] + node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2551:198] + node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2551:198] + node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2551:198] + node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2551:198] + node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2551:198] + node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2551:198] + node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2625:153] + node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2551:198] + node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2551:198] + node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2551:198] + node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2551:198] + node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2551:198] + node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2551:198] + node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2551:198] + node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2551:198] + node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2551:198] + node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2551:198] + node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2551:198] + node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2626:105] + node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2551:198] + node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2551:198] + node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2551:198] + node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2551:198] + node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2551:198] + node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2551:198] + node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2551:198] + node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2551:198] + node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2551:198] + node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2626:153] + node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2551:198] + node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2551:198] + node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2551:198] + node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2551:198] + node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2551:198] + node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2551:198] + node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2551:198] + node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2551:198] + node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2551:198] + node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2627:105] + node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2551:198] + node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2551:198] + node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2551:198] + node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2551:198] + node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2551:198] + node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2551:198] + node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2551:198] + node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2551:198] + node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2551:198] + node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2627:161] + node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2551:198] + node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2551:198] + node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2551:198] + node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2551:198] + node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2551:198] + node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2551:198] + node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2551:198] + node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2628:105] + node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2551:198] + node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2551:198] + node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2551:198] + node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2551:198] + node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2551:198] + node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2551:198] + node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2551:198] + node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2551:198] + node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2551:198] + node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2551:198] + node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2628:161] + node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2551:198] + node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2551:198] + node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2551:198] + node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2551:198] + node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2551:198] + node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2551:198] + node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2551:198] + node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2551:198] + node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2551:198] + node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2629:97] + node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2551:198] + node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2551:198] + node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2551:198] + node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2551:198] + node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2551:198] + node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2551:198] + node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2551:198] + node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2551:198] + node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2551:198] + node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2629:153] + node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2551:198] + node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2551:198] + node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2551:198] + node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2551:198] + node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2551:198] + node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2551:198] + node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2551:198] + node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2551:198] + node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2551:198] + node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2630:105] + node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] + node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2551:198] + node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2551:198] + node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2551:198] + node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2551:198] + node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2551:198] + node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2551:198] + node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2551:198] + node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2551:198] + node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2630:161] + node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2551:198] + node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2551:198] + node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2551:198] + node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2551:198] + node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2551:198] + node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2551:198] + node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2551:198] + node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2551:198] + node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2631:105] + node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2551:198] + node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2551:198] + node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2551:198] + node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2551:198] + node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2551:198] + node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2551:198] + node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2551:198] + node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2551:198] + node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2551:198] + node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2631:161] + node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] + node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2551:198] + node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2551:198] + node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2551:198] + node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2551:198] + node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2551:198] + node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2551:198] + node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2632:105] + node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2551:198] + node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2551:198] + node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2551:198] + node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2551:198] + node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2551:198] + node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2551:198] + node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2551:198] + node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2551:198] + node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2551:198] + node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2632:161] + node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2551:198] + node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2551:198] + node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2551:198] + node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2551:198] + node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2551:198] + node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2551:198] + node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2551:198] + node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2551:198] + node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2633:105] + node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2551:198] + node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2551:198] + node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2551:198] + node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2551:198] + node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2551:198] + node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2551:198] + node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2551:198] + node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2551:198] + node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2551:198] + node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2633:161] + node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] + node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] + node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2551:198] + node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2551:198] + node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2551:198] + node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2551:198] + node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2551:198] + node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2551:198] + node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2551:198] + node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2551:198] + node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2551:198] + node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2551:198] + node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2634:105] + node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] + node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2551:198] + node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2551:198] + node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2551:198] + node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2551:198] + node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2551:198] + node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2551:198] + node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2634:153] + node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] + node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2551:198] + node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2551:198] + node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2551:198] + node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2551:198] + node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2551:198] + node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2551:198] + node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2551:198] + node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2551:198] + node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2551:198] + node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2635:113] + node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] + node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] + node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] + node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2551:198] + node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2551:198] + node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2551:198] + node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2551:198] + node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2551:198] + node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2551:198] + node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2551:198] + node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2551:198] + node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2551:198] + node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2635:161] + node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2551:198] + node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2551:198] + node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2551:198] + node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2551:198] + node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2551:198] + node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2551:198] + node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2551:198] + node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2636:97] + node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] + node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2551:198] + node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2551:198] + node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2551:198] + node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2551:198] + node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2551:198] + node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2551:198] + node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2636:153] + node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] + node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] + node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2551:198] + node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2551:198] + node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2551:198] + node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2551:198] + node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2551:198] + node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2551:198] + node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2551:198] + node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2637:113] + node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] + node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] + node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] + node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] + node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] + node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2551:198] + node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2551:198] + node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2551:198] + node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2551:198] + node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2551:198] + node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2551:198] + node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2637:169] + io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2624:26] module dec_tlu_ctl : input clock : Clock @@ -78099,24 +78089,24 @@ circuit quasar_wrapper : node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 274:39] node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 274:57] dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 274:36] - inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 275:30] + inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 275:32] int_timers.clock <= clock int_timers.reset <= reset - int_timers.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 276:57] - int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 277:57] + int_timers.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 276:73] + int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 277:73] int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 278:49] int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 279:49] int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 280:49] int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 281:49] - int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 282:57] - int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 283:57] - int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 284:57] - int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 285:57] - int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 286:57] - int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 287:57] - int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 288:49] + int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 282:73] + int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 283:73] + int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 284:73] + int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 285:73] + int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 286:73] + int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 287:73] + int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 288:57] int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 289:49] - int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 290:47] + int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 290:48] node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58] node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58] node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58] @@ -78127,101 +78117,101 @@ circuit quasar_wrapper : _T_8 <= _T_7 @[lib.scala 37:81] reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:58] syncro_ff <= _T_8 @[lib.scala 37:58] - node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 302:67] - node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 303:59] - node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 304:59] - node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 305:59] - node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 306:59] - node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 307:51] - node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 308:51] - node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 311:58] - node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 311:74] + node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 302:76] + node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 303:68] + node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 304:68] + node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 305:64] + node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 306:66] + node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 307:52] + node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 308:56] + node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 311:64] + node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 311:80] inst rvclkhdr of rvclkhdr_716 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= _T_10 @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 312:67] - node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 312:88] - node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 312:104] + node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 312:71] + node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 312:92] + node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 312:108] inst rvclkhdr_1 of rvclkhdr_717 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= _T_13 @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 315:30] - node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 316:50] - node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 316:69] - node _T_16 = or(_T_15, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 316:89] - node _T_17 = or(_T_16, reset_delayed) @[dec_tlu_ctl.scala 316:112] - node _T_18 = or(_T_17, pause_expired_r) @[dec_tlu_ctl.scala 316:128] - node _T_19 = or(_T_18, pause_expired_wb) @[dec_tlu_ctl.scala 316:146] - node _T_20 = or(_T_19, ic_perr_r) @[dec_tlu_ctl.scala 316:165] - node _T_21 = or(_T_20, ic_perr_r_d1) @[dec_tlu_ctl.scala 316:177] - node _T_22 = or(_T_21, iccm_sbecc_r) @[dec_tlu_ctl.scala 316:192] - node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 316:207] - node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 316:225] - node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 318:49] - node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 318:65] + node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 315:39] + node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 316:55] + node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 316:74] + node _T_16 = or(_T_15, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 316:94] + node _T_17 = or(_T_16, reset_delayed) @[dec_tlu_ctl.scala 316:117] + node _T_18 = or(_T_17, pause_expired_r) @[dec_tlu_ctl.scala 316:133] + node _T_19 = or(_T_18, pause_expired_wb) @[dec_tlu_ctl.scala 316:151] + node _T_20 = or(_T_19, ic_perr_r) @[dec_tlu_ctl.scala 316:170] + node _T_21 = or(_T_20, ic_perr_r_d1) @[dec_tlu_ctl.scala 316:182] + node _T_22 = or(_T_21, iccm_sbecc_r) @[dec_tlu_ctl.scala 316:197] + node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 316:212] + node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 316:230] + node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 318:55] + node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 318:71] inst rvclkhdr_2 of rvclkhdr_718 @[lib.scala 343:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] rvclkhdr_2.io.en <= _T_25 @[lib.scala 345:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 319:53] - node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 319:71] + node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 319:55] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 319:73] inst rvclkhdr_3 of rvclkhdr_719 @[lib.scala 343:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 344:17] rvclkhdr_3.io.en <= _T_27 @[lib.scala 345:16] rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 321:80] - iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 321:80] - reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 322:89] - _T_28 <= ic_perr_r @[dec_tlu_ctl.scala 322:89] - ic_perr_r_d1 <= _T_28 @[dec_tlu_ctl.scala 322:57] - reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 323:89] - _T_29 <= iccm_sbecc_r @[dec_tlu_ctl.scala 323:89] - iccm_sbecc_r_d1 <= _T_29 @[dec_tlu_ctl.scala 323:57] - reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 324:97] - _T_30 <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 324:97] - e5_valid <= _T_30 @[dec_tlu_ctl.scala 324:65] - reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 325:81] - _T_31 <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 325:81] - debug_mode_status <= _T_31 @[dec_tlu_ctl.scala 325:49] - reg lsu_pmu_load_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 326:80] - lsu_pmu_load_external_r <= io.lsu_tlu.lsu_pmu_load_external_m @[dec_tlu_ctl.scala 326:80] - reg lsu_pmu_store_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 327:72] - lsu_pmu_store_external_r <= io.lsu_tlu.lsu_pmu_store_external_m @[dec_tlu_ctl.scala 327:72] - reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 328:80] - tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[dec_tlu_ctl.scala 328:80] - reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 329:73] - _T_32 <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 329:73] + reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 321:90] + iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 321:90] + reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 322:122] + _T_28 <= ic_perr_r @[dec_tlu_ctl.scala 322:122] + ic_perr_r_d1 <= _T_28 @[dec_tlu_ctl.scala 322:89] + reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 323:114] + _T_29 <= iccm_sbecc_r @[dec_tlu_ctl.scala 323:114] + iccm_sbecc_r_d1 <= _T_29 @[dec_tlu_ctl.scala 323:81] + reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 324:138] + _T_30 <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 324:138] + e5_valid <= _T_30 @[dec_tlu_ctl.scala 324:105] + reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 325:90] + _T_31 <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 325:90] + debug_mode_status <= _T_31 @[dec_tlu_ctl.scala 325:57] + reg lsu_pmu_load_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 326:82] + lsu_pmu_load_external_r <= io.lsu_tlu.lsu_pmu_load_external_m @[dec_tlu_ctl.scala 326:82] + reg lsu_pmu_store_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 327:74] + lsu_pmu_store_external_r <= io.lsu_tlu.lsu_pmu_store_external_m @[dec_tlu_ctl.scala 327:74] + reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 328:90] + tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[dec_tlu_ctl.scala 328:90] + reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 329:74] + _T_32 <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 329:74] io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[dec_tlu_ctl.scala 329:41] - reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 330:72] - internal_dbg_halt_mode_f2 <= debug_mode_status @[dec_tlu_ctl.scala 330:72] - reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 331:89] - _T_33 <= force_halt @[dec_tlu_ctl.scala 331:89] - io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 331:57] - io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 333:41] - reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 334:88] - reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 334:88] - reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 335:88] - reset_detected <= reset_detect @[dec_tlu_ctl.scala 335:88] - node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 336:64] - reset_delayed <= _T_34 @[dec_tlu_ctl.scala 336:49] - reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 338:72] - nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 338:72] - reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 339:72] - nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 339:72] - reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:72] - nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 340:72] - reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:72] - nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 341:72] + reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 330:74] + internal_dbg_halt_mode_f2 <= debug_mode_status @[dec_tlu_ctl.scala 330:74] + reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 331:74] + _T_33 <= force_halt @[dec_tlu_ctl.scala 331:74] + io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 331:41] + io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 333:37] + reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 334:106] + reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 334:106] + reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 335:98] + reset_detected <= reset_detect @[dec_tlu_ctl.scala 335:98] + node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 336:89] + reset_delayed <= _T_34 @[dec_tlu_ctl.scala 336:73] + reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 338:81] + nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 338:81] + reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 339:73] + nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 339:73] + reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:73] + nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 340:73] + reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:73] + nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 341:73] node _T_35 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 345:32] node _T_36 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 345:96] node nmi_lsu_detected = and(_T_35, _T_36) @[dec_tlu_ctl.scala 345:49] @@ -78253,30 +78243,30 @@ circuit quasar_wrapper : node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[dec_tlu_ctl.scala 350:162] node _T_61 = or(_T_58, _T_60) @[dec_tlu_ctl.scala 350:138] nmi_lsu_store_type <= _T_61 @[dec_tlu_ctl.scala 350:28] - node _T_62 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 357:69] - node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[dec_tlu_ctl.scala 357:67] - reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 358:72] - mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[dec_tlu_ctl.scala 358:72] - reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 359:72] - mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[dec_tlu_ctl.scala 359:72] - reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 360:89] - _T_63 <= mpc_halt_state_ns @[dec_tlu_ctl.scala 360:89] - mpc_halt_state_f <= _T_63 @[dec_tlu_ctl.scala 360:57] - reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 361:88] - mpc_run_state_f <= mpc_run_state_ns @[dec_tlu_ctl.scala 361:88] - reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 362:80] - debug_brkpt_status_f <= debug_brkpt_status_ns @[dec_tlu_ctl.scala 362:80] - reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 363:80] - mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[dec_tlu_ctl.scala 363:80] - reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 364:80] - mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[dec_tlu_ctl.scala 364:80] - reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 365:89] - _T_64 <= dbg_halt_state_ns @[dec_tlu_ctl.scala 365:89] - dbg_halt_state_f <= _T_64 @[dec_tlu_ctl.scala 365:57] - reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 366:88] - dbg_run_state_f <= dbg_run_state_ns @[dec_tlu_ctl.scala 366:88] - reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 367:81] - _T_65 <= dec_tlu_mpc_halted_only_ns @[dec_tlu_ctl.scala 367:81] + node _T_62 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 357:72] + node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[dec_tlu_ctl.scala 357:70] + reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 358:74] + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[dec_tlu_ctl.scala 358:74] + reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 359:74] + mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[dec_tlu_ctl.scala 359:74] + reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 360:114] + _T_63 <= mpc_halt_state_ns @[dec_tlu_ctl.scala 360:114] + mpc_halt_state_f <= _T_63 @[dec_tlu_ctl.scala 360:81] + reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 361:106] + mpc_run_state_f <= mpc_run_state_ns @[dec_tlu_ctl.scala 361:106] + reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 362:90] + debug_brkpt_status_f <= debug_brkpt_status_ns @[dec_tlu_ctl.scala 362:90] + reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 363:90] + mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[dec_tlu_ctl.scala 363:90] + reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 364:90] + mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[dec_tlu_ctl.scala 364:90] + reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 365:114] + _T_64 <= dbg_halt_state_ns @[dec_tlu_ctl.scala 365:114] + dbg_halt_state_f <= _T_64 @[dec_tlu_ctl.scala 365:81] + reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 366:106] + dbg_run_state_f <= dbg_run_state_ns @[dec_tlu_ctl.scala 366:106] + reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 367:82] + _T_65 <= dec_tlu_mpc_halted_only_ns @[dec_tlu_ctl.scala 367:82] io.dec_tlu_mpc_halted_only <= _T_65 @[dec_tlu_ctl.scala 367:49] node _T_66 = not(mpc_debug_halt_req_sync_f) @[dec_tlu_ctl.scala 371:71] node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[dec_tlu_ctl.scala 371:69] @@ -78429,58 +78419,58 @@ circuit quasar_wrapper : node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 444:64] node _T_184 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 444:95] node request_debug_mode_done = and(_T_183, _T_184) @[dec_tlu_ctl.scala 444:93] - reg _T_185 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 447:81] - _T_185 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec_tlu_ctl.scala 447:81] + reg _T_185 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 447:82] + _T_185 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec_tlu_ctl.scala 447:82] dec_tlu_flush_noredir_r_d1 <= _T_185 @[dec_tlu_ctl.scala 447:49] - reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 448:89] - _T_186 <= halt_taken @[dec_tlu_ctl.scala 448:89] - halt_taken_f <= _T_186 @[dec_tlu_ctl.scala 448:57] - reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 449:89] - _T_187 <= io.lsu_idle_any @[dec_tlu_ctl.scala 449:89] - lsu_idle_any_f <= _T_187 @[dec_tlu_ctl.scala 449:57] - reg _T_188 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 450:81] - _T_188 <= io.tlu_mem.ifu_miss_state_idle @[dec_tlu_ctl.scala 450:81] - ifu_miss_state_idle_f <= _T_188 @[dec_tlu_ctl.scala 450:49] - reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 451:89] - _T_189 <= dbg_tlu_halted @[dec_tlu_ctl.scala 451:89] - dbg_tlu_halted_f <= _T_189 @[dec_tlu_ctl.scala 451:57] - reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 452:81] - _T_190 <= resume_ack_ns @[dec_tlu_ctl.scala 452:81] - io.dec_tlu_resume_ack <= _T_190 @[dec_tlu_ctl.scala 452:49] - reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 453:89] - _T_191 <= debug_halt_req_ns @[dec_tlu_ctl.scala 453:89] - debug_halt_req_f <= _T_191 @[dec_tlu_ctl.scala 453:57] - reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 454:89] - _T_192 <= debug_resume_req @[dec_tlu_ctl.scala 454:89] - debug_resume_req_f <= _T_192 @[dec_tlu_ctl.scala 454:57] - reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 455:81] - _T_193 <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 455:81] - trigger_hit_dmode_r_d1 <= _T_193 @[dec_tlu_ctl.scala 455:49] - reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 456:81] - _T_194 <= dcsr_single_step_done @[dec_tlu_ctl.scala 456:81] - dcsr_single_step_done_f <= _T_194 @[dec_tlu_ctl.scala 456:49] - reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 457:89] - _T_195 <= debug_halt_req @[dec_tlu_ctl.scala 457:89] - debug_halt_req_d1 <= _T_195 @[dec_tlu_ctl.scala 457:57] - reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 458:81] - dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 458:81] - reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 459:81] - dec_pause_state_f <= io.dec_pause_state @[dec_tlu_ctl.scala 459:81] - reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 460:81] - _T_196 <= request_debug_mode_r @[dec_tlu_ctl.scala 460:81] + reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 448:122] + _T_186 <= halt_taken @[dec_tlu_ctl.scala 448:122] + halt_taken_f <= _T_186 @[dec_tlu_ctl.scala 448:89] + reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 449:114] + _T_187 <= io.lsu_idle_any @[dec_tlu_ctl.scala 449:114] + lsu_idle_any_f <= _T_187 @[dec_tlu_ctl.scala 449:81] + reg _T_188 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 450:98] + _T_188 <= io.tlu_mem.ifu_miss_state_idle @[dec_tlu_ctl.scala 450:98] + ifu_miss_state_idle_f <= _T_188 @[dec_tlu_ctl.scala 450:65] + reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 451:114] + _T_189 <= dbg_tlu_halted @[dec_tlu_ctl.scala 451:114] + dbg_tlu_halted_f <= _T_189 @[dec_tlu_ctl.scala 451:81] + reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 452:98] + _T_190 <= resume_ack_ns @[dec_tlu_ctl.scala 452:98] + io.dec_tlu_resume_ack <= _T_190 @[dec_tlu_ctl.scala 452:65] + reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 453:114] + _T_191 <= debug_halt_req_ns @[dec_tlu_ctl.scala 453:114] + debug_halt_req_f <= _T_191 @[dec_tlu_ctl.scala 453:81] + reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 454:106] + _T_192 <= debug_resume_req @[dec_tlu_ctl.scala 454:106] + debug_resume_req_f <= _T_192 @[dec_tlu_ctl.scala 454:73] + reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 455:90] + _T_193 <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 455:90] + trigger_hit_dmode_r_d1 <= _T_193 @[dec_tlu_ctl.scala 455:57] + reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 456:90] + _T_194 <= dcsr_single_step_done @[dec_tlu_ctl.scala 456:90] + dcsr_single_step_done_f <= _T_194 @[dec_tlu_ctl.scala 456:57] + reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 457:114] + _T_195 <= debug_halt_req @[dec_tlu_ctl.scala 457:114] + debug_halt_req_d1 <= _T_195 @[dec_tlu_ctl.scala 457:81] + reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 458:90] + dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 458:90] + reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 459:98] + dec_pause_state_f <= io.dec_pause_state @[dec_tlu_ctl.scala 459:98] + reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 460:82] + _T_196 <= request_debug_mode_r @[dec_tlu_ctl.scala 460:82] request_debug_mode_r_d1 <= _T_196 @[dec_tlu_ctl.scala 460:49] - reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 461:73] - _T_197 <= request_debug_mode_done @[dec_tlu_ctl.scala 461:73] + reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 461:74] + _T_197 <= request_debug_mode_done @[dec_tlu_ctl.scala 461:74] request_debug_mode_done_f <= _T_197 @[dec_tlu_ctl.scala 461:41] - reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 462:73] - _T_198 <= dcsr_single_step_running @[dec_tlu_ctl.scala 462:73] - dcsr_single_step_running_f <= _T_198 @[dec_tlu_ctl.scala 462:41] - reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 463:73] - _T_199 <= io.dec_tlu_flush_pause_r @[dec_tlu_ctl.scala 463:73] + reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 462:66] + _T_198 <= dcsr_single_step_running @[dec_tlu_ctl.scala 462:66] + dcsr_single_step_running_f <= _T_198 @[dec_tlu_ctl.scala 462:33] + reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 463:74] + _T_199 <= io.dec_tlu_flush_pause_r @[dec_tlu_ctl.scala 463:74] dec_tlu_flush_pause_r_d1 <= _T_199 @[dec_tlu_ctl.scala 463:41] - reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 464:81] - _T_200 <= dbg_halt_req_held_ns @[dec_tlu_ctl.scala 464:81] - dbg_halt_req_held <= _T_200 @[dec_tlu_ctl.scala 464:49] + reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 464:98] + _T_200 <= dbg_halt_req_held_ns @[dec_tlu_ctl.scala 464:98] + dbg_halt_req_held <= _T_200 @[dec_tlu_ctl.scala 464:65] io.dec_tlu_debug_stall <= debug_halt_req_f @[dec_tlu_ctl.scala 467:41] io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 468:41] io.dec_tlu_debug_mode <= debug_mode_status @[dec_tlu_ctl.scala 469:41] @@ -78654,314 +78644,314 @@ circuit quasar_wrapper : trigger_hit_dmode_r <= _T_344 @[dec_tlu_ctl.scala 538:24] node _T_345 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 540:55] node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[dec_tlu_ctl.scala 540:53] - node _T_346 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 567:62] - node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[dec_tlu_ctl.scala 567:60] - node _T_348 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 567:87] - node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[dec_tlu_ctl.scala 567:85] - node _T_349 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 568:60] - node _T_350 = and(i_cpu_run_req_sync, _T_349) @[dec_tlu_ctl.scala 568:58] - node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 568:83] - node _T_352 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 568:107] - node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[dec_tlu_ctl.scala 568:105] - reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 570:80] - i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[dec_tlu_ctl.scala 570:80] - reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 571:80] - i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[dec_tlu_ctl.scala 571:80] - reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 572:81] - _T_353 <= cpu_halt_status @[dec_tlu_ctl.scala 572:81] - io.o_cpu_halt_status <= _T_353 @[dec_tlu_ctl.scala 572:49] - reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 573:81] - _T_354 <= cpu_halt_ack @[dec_tlu_ctl.scala 573:81] - io.o_cpu_halt_ack <= _T_354 @[dec_tlu_ctl.scala 573:49] - reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 574:81] - _T_355 <= cpu_run_ack @[dec_tlu_ctl.scala 574:81] - io.o_cpu_run_ack <= _T_355 @[dec_tlu_ctl.scala 574:49] - reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 575:68] - internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 575:68] - reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 576:73] - _T_356 <= pmu_fw_halt_req_ns @[dec_tlu_ctl.scala 576:73] - pmu_fw_halt_req_f <= _T_356 @[dec_tlu_ctl.scala 576:41] - reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 577:73] - _T_357 <= pmu_fw_tlu_halted @[dec_tlu_ctl.scala 577:73] - pmu_fw_tlu_halted_f <= _T_357 @[dec_tlu_ctl.scala 577:41] - reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 578:73] - _T_358 <= int_timer0_int_hold @[dec_tlu_ctl.scala 578:73] - int_timer0_int_hold_f <= _T_358 @[dec_tlu_ctl.scala 578:41] - reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 579:73] - _T_359 <= int_timer1_int_hold @[dec_tlu_ctl.scala 579:73] - int_timer1_int_hold_f <= _T_359 @[dec_tlu_ctl.scala 579:41] - node _T_360 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 583:52] - node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[dec_tlu_ctl.scala 583:50] - node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 584:48] - node _T_361 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 585:72] - node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[dec_tlu_ctl.scala 585:70] - node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[dec_tlu_ctl.scala 585:49] - node _T_364 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 585:95] - node _T_365 = and(_T_363, _T_364) @[dec_tlu_ctl.scala 585:93] - pmu_fw_halt_req_ns <= _T_365 @[dec_tlu_ctl.scala 585:23] - node _T_366 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 586:85] - node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[dec_tlu_ctl.scala 586:83] - node _T_368 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 586:105] - node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 586:103] - node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[dec_tlu_ctl.scala 586:52] - internal_pmu_fw_halt_mode <= _T_370 @[dec_tlu_ctl.scala 586:30] - node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 589:45] - node _T_372 = and(_T_371, halt_taken) @[dec_tlu_ctl.scala 589:58] - node _T_373 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 589:73] - node _T_374 = and(_T_372, _T_373) @[dec_tlu_ctl.scala 589:71] - node _T_375 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 589:121] - node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[dec_tlu_ctl.scala 589:119] - node _T_377 = or(_T_374, _T_376) @[dec_tlu_ctl.scala 589:96] - node _T_378 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 589:143] - node _T_379 = and(_T_377, _T_378) @[dec_tlu_ctl.scala 589:141] - pmu_fw_tlu_halted <= _T_379 @[dec_tlu_ctl.scala 589:22] - node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 591:38] - cpu_halt_ack <= _T_380 @[dec_tlu_ctl.scala 591:17] - node _T_381 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 592:46] - node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[dec_tlu_ctl.scala 592:44] - node _T_383 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 592:91] - node _T_384 = and(io.o_cpu_halt_status, _T_383) @[dec_tlu_ctl.scala 592:89] - node _T_385 = not(debug_mode_status) @[dec_tlu_ctl.scala 592:111] - node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 592:109] - node _T_387 = or(_T_382, _T_386) @[dec_tlu_ctl.scala 592:65] - cpu_halt_status <= _T_387 @[dec_tlu_ctl.scala 592:20] - node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 593:41] - node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 593:88] - node _T_390 = or(_T_388, _T_389) @[dec_tlu_ctl.scala 593:68] - cpu_run_ack <= _T_390 @[dec_tlu_ctl.scala 593:16] - io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 595:27] - node _T_391 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 598:66] - node _T_392 = or(_T_391, soft_int_ready) @[dec_tlu_ctl.scala 598:84] - node _T_393 = or(_T_392, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 598:101] - node _T_394 = or(_T_393, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 598:125] - node _T_395 = and(io.dec_pic.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 598:172] - node _T_396 = or(_T_394, _T_395) @[dec_tlu_ctl.scala 598:149] - node _T_397 = and(_T_396, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 598:191] - node _T_398 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 598:216] - node _T_399 = and(_T_397, _T_398) @[dec_tlu_ctl.scala 598:214] - node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[dec_tlu_ctl.scala 598:45] - i_cpu_run_req_d1 <= _T_400 @[dec_tlu_ctl.scala 598:21] - reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 604:89] - _T_401 <= mdseac_locked_ns @[dec_tlu_ctl.scala 604:89] - mdseac_locked_f <= _T_401 @[dec_tlu_ctl.scala 604:57] - reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 605:72] - lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 605:72] - node _T_402 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 607:57] - node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[dec_tlu_ctl.scala 607:55] - lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 608:21] - node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 609:40] - node _T_404 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 609:64] - node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 609:62] - node _T_406 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 609:84] - node lsu_exc_valid_r = and(_T_405, _T_406) @[dec_tlu_ctl.scala 609:82] - reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 611:74] - _T_407 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 611:74] - lsu_exc_valid_r_d1 <= _T_407 @[dec_tlu_ctl.scala 611:41] - reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 612:73] - lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 612:73] - node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 613:40] - node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[dec_tlu_ctl.scala 613:38] - node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 614:38] - node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 615:38] - node _T_409 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 619:49] - node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[dec_tlu_ctl.scala 619:47] - node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 619:70] - node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 619:105] - node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[dec_tlu_ctl.scala 619:67] - node _T_413 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 622:52] - node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[dec_tlu_ctl.scala 622:50] - node _T_415 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 622:65] - node _T_416 = and(_T_414, _T_415) @[dec_tlu_ctl.scala 622:63] - node _T_417 = not(inst_acc_r) @[dec_tlu_ctl.scala 622:82] - node _T_418 = and(_T_416, _T_417) @[dec_tlu_ctl.scala 622:79] - node _T_419 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 622:96] - node _T_420 = and(_T_418, _T_419) @[dec_tlu_ctl.scala 622:94] - node _T_421 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 622:121] - node _T_422 = and(_T_420, _T_421) @[dec_tlu_ctl.scala 622:119] - node _T_423 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 622:148] - node tlu_i0_commit_cmt = and(_T_422, _T_423) @[dec_tlu_ctl.scala 622:146] - node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 625:38] - node _T_425 = or(_T_424, inst_acc_r) @[dec_tlu_ctl.scala 625:53] - node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 625:79] - node _T_427 = or(_T_425, _T_426) @[dec_tlu_ctl.scala 625:66] - node _T_428 = or(_T_427, i0_trigger_hit_r) @[dec_tlu_ctl.scala 625:104] - tlu_i0_kill_writeb_r <= _T_428 @[dec_tlu_ctl.scala 625:25] - io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 626:37] - node _T_429 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 631:44] - node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[dec_tlu_ctl.scala 631:42] - node _T_431 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 631:98] - node _T_432 = and(_T_430, _T_431) @[dec_tlu_ctl.scala 631:66] - node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 631:154] - node _T_434 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 631:175] - node _T_435 = and(_T_433, _T_434) @[dec_tlu_ctl.scala 631:173] - node _T_436 = or(_T_432, _T_435) @[dec_tlu_ctl.scala 631:137] - node _T_437 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 631:199] - node _T_438 = and(_T_436, _T_437) @[dec_tlu_ctl.scala 631:196] - node _T_439 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 631:220] - node _T_440 = and(_T_438, _T_439) @[dec_tlu_ctl.scala 631:217] - rfpc_i0_r <= _T_440 @[dec_tlu_ctl.scala 631:14] - node _T_441 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 634:70] - node _T_442 = and(iccm_repair_state_d1, _T_441) @[dec_tlu_ctl.scala 634:68] - node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[dec_tlu_ctl.scala 634:44] - iccm_repair_state_ns <= _T_443 @[dec_tlu_ctl.scala 634:25] - node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 640:52] - node _T_445 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 640:88] - node _T_446 = or(_T_445, mret_r) @[dec_tlu_ctl.scala 640:98] - node _T_447 = or(_T_446, take_reset) @[dec_tlu_ctl.scala 640:107] - node _T_448 = or(_T_447, illegal_r) @[dec_tlu_ctl.scala 640:120] - node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 640:176] - node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[dec_tlu_ctl.scala 640:153] - node _T_451 = or(_T_448, _T_450) @[dec_tlu_ctl.scala 640:132] - node _T_452 = not(_T_451) @[dec_tlu_ctl.scala 640:77] - node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[dec_tlu_ctl.scala 640:75] - node _T_453 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 643:59] - node _T_454 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 643:85] - node dec_tlu_br0_error_r = and(_T_453, _T_454) @[dec_tlu_ctl.scala 643:83] - node _T_455 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 644:71] - node _T_456 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 644:97] - node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[dec_tlu_ctl.scala 644:95] - node _T_457 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 645:55] - node _T_458 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 645:81] - node _T_459 = and(_T_457, _T_458) @[dec_tlu_ctl.scala 645:79] - node _T_460 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 645:106] - node _T_461 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 645:135] - node _T_462 = or(_T_460, _T_461) @[dec_tlu_ctl.scala 645:133] - node dec_tlu_br0_v_r = and(_T_459, _T_462) @[dec_tlu_ctl.scala 645:103] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 648:65] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 649:57] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 650:57] - io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 651:57] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 652:65] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 653:65] - node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 656:51] - node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 656:64] - node _T_465 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 656:90] - node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 656:88] - node _T_467 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 656:115] - node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 656:110] - node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 656:108] - node _T_470 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 656:132] - node _T_471 = and(_T_469, _T_470) @[dec_tlu_ctl.scala 656:130] - ebreak_r <= _T_471 @[dec_tlu_ctl.scala 656:13] - node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 657:51] - node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 657:64] - node _T_474 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 657:90] - node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 657:88] - node _T_476 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 657:110] - node _T_477 = and(_T_475, _T_476) @[dec_tlu_ctl.scala 657:108] - ecall_r <= _T_477 @[dec_tlu_ctl.scala 657:13] - node _T_478 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 658:17] - node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 658:46] - node _T_480 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 658:72] - node _T_481 = and(_T_479, _T_480) @[dec_tlu_ctl.scala 658:70] - node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 658:92] - node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 658:90] - illegal_r <= _T_483 @[dec_tlu_ctl.scala 658:13] - node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 659:51] - node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 659:64] - node _T_486 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 659:90] - node _T_487 = and(_T_485, _T_486) @[dec_tlu_ctl.scala 659:88] - node _T_488 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 659:110] - node _T_489 = and(_T_487, _T_488) @[dec_tlu_ctl.scala 659:108] - mret_r <= _T_489 @[dec_tlu_ctl.scala 659:13] - node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 661:50] - node _T_491 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 661:76] - node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 661:74] - node _T_493 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 661:97] - node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 661:95] - fence_i_r <= _T_494 @[dec_tlu_ctl.scala 661:17] - node _T_495 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 662:53] - node _T_496 = and(io.tlu_mem.ifu_ic_error_start, _T_495) @[dec_tlu_ctl.scala 662:51] - node _T_497 = not(debug_mode_status) @[dec_tlu_ctl.scala 662:75] - node _T_498 = or(_T_497, dcsr_single_step_running) @[dec_tlu_ctl.scala 662:101] - node _T_499 = and(_T_496, _T_498) @[dec_tlu_ctl.scala 662:72] - node _T_500 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 662:131] - node _T_501 = and(_T_499, _T_500) @[dec_tlu_ctl.scala 662:129] - ic_perr_r <= _T_501 @[dec_tlu_ctl.scala 662:17] - node _T_502 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 663:61] - node _T_503 = and(io.tlu_mem.ifu_iccm_rd_ecc_single_err, _T_502) @[dec_tlu_ctl.scala 663:59] - node _T_504 = not(debug_mode_status) @[dec_tlu_ctl.scala 663:83] - node _T_505 = or(_T_504, dcsr_single_step_running) @[dec_tlu_ctl.scala 663:109] - node _T_506 = and(_T_503, _T_505) @[dec_tlu_ctl.scala 663:80] - node _T_507 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 663:139] - node _T_508 = and(_T_506, _T_507) @[dec_tlu_ctl.scala 663:137] - iccm_sbecc_r <= _T_508 @[dec_tlu_ctl.scala 663:17] - node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 664:49] - inst_acc_r_raw <= _T_509 @[dec_tlu_ctl.scala 664:20] - node _T_510 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 665:35] - node _T_511 = and(inst_acc_r_raw, _T_510) @[dec_tlu_ctl.scala 665:33] - node _T_512 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 665:48] - node _T_513 = and(_T_511, _T_512) @[dec_tlu_ctl.scala 665:46] - inst_acc_r <= _T_513 @[dec_tlu_ctl.scala 665:15] - node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 668:64] - node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 668:77] - node _T_516 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 668:103] - node _T_517 = and(_T_515, _T_516) @[dec_tlu_ctl.scala 668:101] - node _T_518 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 668:127] - node _T_519 = and(_T_517, _T_518) @[dec_tlu_ctl.scala 668:121] - node _T_520 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 668:144] - node _T_521 = and(_T_519, _T_520) @[dec_tlu_ctl.scala 668:142] - ebreak_to_debug_mode_r <= _T_521 @[dec_tlu_ctl.scala 668:27] - reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 670:64] - _T_522 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 670:64] - ebreak_to_debug_mode_r_d1 <= _T_522 @[dec_tlu_ctl.scala 670:34] - io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 671:39] - node _T_523 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 684:41] - node _T_524 = or(_T_523, illegal_r) @[dec_tlu_ctl.scala 684:51] - node _T_525 = or(_T_524, inst_acc_r) @[dec_tlu_ctl.scala 684:63] - node _T_526 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 684:79] - node _T_527 = and(_T_525, _T_526) @[dec_tlu_ctl.scala 684:77] - node _T_528 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 684:92] - node i0_exception_valid_r = and(_T_527, _T_528) @[dec_tlu_ctl.scala 684:90] - node _T_529 = not(take_nmi) @[dec_tlu_ctl.scala 693:33] - node _T_530 = and(take_ext_int, _T_529) @[dec_tlu_ctl.scala 693:31] - node _T_531 = bits(_T_530, 0, 0) @[dec_tlu_ctl.scala 693:44] - node _T_532 = not(take_nmi) @[dec_tlu_ctl.scala 694:27] - node _T_533 = and(take_timer_int, _T_532) @[dec_tlu_ctl.scala 694:25] - node _T_534 = bits(_T_533, 0, 0) @[dec_tlu_ctl.scala 694:38] - node _T_535 = not(take_nmi) @[dec_tlu_ctl.scala 695:26] - node _T_536 = and(take_soft_int, _T_535) @[dec_tlu_ctl.scala 695:24] - node _T_537 = bits(_T_536, 0, 0) @[dec_tlu_ctl.scala 695:37] - node _T_538 = not(take_nmi) @[dec_tlu_ctl.scala 696:32] - node _T_539 = and(take_int_timer0_int, _T_538) @[dec_tlu_ctl.scala 696:30] - node _T_540 = bits(_T_539, 0, 0) @[dec_tlu_ctl.scala 696:43] - node _T_541 = not(take_nmi) @[dec_tlu_ctl.scala 697:32] - node _T_542 = and(take_int_timer1_int, _T_541) @[dec_tlu_ctl.scala 697:30] - node _T_543 = bits(_T_542, 0, 0) @[dec_tlu_ctl.scala 697:43] - node _T_544 = not(take_nmi) @[dec_tlu_ctl.scala 698:24] - node _T_545 = and(take_ce_int, _T_544) @[dec_tlu_ctl.scala 698:22] - node _T_546 = bits(_T_545, 0, 0) @[dec_tlu_ctl.scala 698:35] - node _T_547 = not(take_nmi) @[dec_tlu_ctl.scala 699:22] - node _T_548 = and(illegal_r, _T_547) @[dec_tlu_ctl.scala 699:20] - node _T_549 = bits(_T_548, 0, 0) @[dec_tlu_ctl.scala 699:33] - node _T_550 = not(take_nmi) @[dec_tlu_ctl.scala 700:21] - node _T_551 = and(ecall_r, _T_550) @[dec_tlu_ctl.scala 700:19] - node _T_552 = bits(_T_551, 0, 0) @[dec_tlu_ctl.scala 700:32] - node _T_553 = not(take_nmi) @[dec_tlu_ctl.scala 701:24] - node _T_554 = and(inst_acc_r, _T_553) @[dec_tlu_ctl.scala 701:22] - node _T_555 = bits(_T_554, 0, 0) @[dec_tlu_ctl.scala 701:35] - node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[dec_tlu_ctl.scala 702:20] - node _T_557 = not(take_nmi) @[dec_tlu_ctl.scala 702:42] - node _T_558 = and(_T_556, _T_557) @[dec_tlu_ctl.scala 702:40] - node _T_559 = bits(_T_558, 0, 0) @[dec_tlu_ctl.scala 702:53] - node _T_560 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 703:25] - node _T_561 = and(lsu_exc_ma_r, _T_560) @[dec_tlu_ctl.scala 703:23] - node _T_562 = not(take_nmi) @[dec_tlu_ctl.scala 703:41] - node _T_563 = and(_T_561, _T_562) @[dec_tlu_ctl.scala 703:39] - node _T_564 = bits(_T_563, 0, 0) @[dec_tlu_ctl.scala 703:52] - node _T_565 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 704:26] - node _T_566 = and(lsu_exc_acc_r, _T_565) @[dec_tlu_ctl.scala 704:24] - node _T_567 = not(take_nmi) @[dec_tlu_ctl.scala 704:42] - node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 704:40] - node _T_569 = bits(_T_568, 0, 0) @[dec_tlu_ctl.scala 704:53] - node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 705:23] - node _T_571 = not(take_nmi) @[dec_tlu_ctl.scala 705:40] - node _T_572 = and(_T_570, _T_571) @[dec_tlu_ctl.scala 705:38] - node _T_573 = bits(_T_572, 0, 0) @[dec_tlu_ctl.scala 705:51] - node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 706:24] - node _T_575 = not(take_nmi) @[dec_tlu_ctl.scala 706:41] - node _T_576 = and(_T_574, _T_575) @[dec_tlu_ctl.scala 706:39] - node _T_577 = bits(_T_576, 0, 0) @[dec_tlu_ctl.scala 706:52] + node _T_346 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 565:62] + node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[dec_tlu_ctl.scala 565:60] + node _T_348 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 565:87] + node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[dec_tlu_ctl.scala 565:85] + node _T_349 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 566:60] + node _T_350 = and(i_cpu_run_req_sync, _T_349) @[dec_tlu_ctl.scala 566:58] + node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 566:83] + node _T_352 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 566:107] + node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[dec_tlu_ctl.scala 566:105] + reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 568:81] + i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[dec_tlu_ctl.scala 568:81] + reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 569:81] + i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[dec_tlu_ctl.scala 569:81] + reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 570:82] + _T_353 <= cpu_halt_status @[dec_tlu_ctl.scala 570:82] + io.o_cpu_halt_status <= _T_353 @[dec_tlu_ctl.scala 570:49] + reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 571:82] + _T_354 <= cpu_halt_ack @[dec_tlu_ctl.scala 571:82] + io.o_cpu_halt_ack <= _T_354 @[dec_tlu_ctl.scala 571:49] + reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 572:82] + _T_355 <= cpu_run_ack @[dec_tlu_ctl.scala 572:82] + io.o_cpu_run_ack <= _T_355 @[dec_tlu_ctl.scala 572:49] + reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 573:70] + internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 573:70] + reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 574:82] + _T_356 <= pmu_fw_halt_req_ns @[dec_tlu_ctl.scala 574:82] + pmu_fw_halt_req_f <= _T_356 @[dec_tlu_ctl.scala 574:49] + reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 575:74] + _T_357 <= pmu_fw_tlu_halted @[dec_tlu_ctl.scala 575:74] + pmu_fw_tlu_halted_f <= _T_357 @[dec_tlu_ctl.scala 575:41] + reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 576:74] + _T_358 <= int_timer0_int_hold @[dec_tlu_ctl.scala 576:74] + int_timer0_int_hold_f <= _T_358 @[dec_tlu_ctl.scala 576:41] + reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 577:74] + _T_359 <= int_timer1_int_hold @[dec_tlu_ctl.scala 577:74] + int_timer1_int_hold_f <= _T_359 @[dec_tlu_ctl.scala 577:41] + node _T_360 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 581:52] + node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[dec_tlu_ctl.scala 581:50] + node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 582:48] + node _T_361 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 583:72] + node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[dec_tlu_ctl.scala 583:70] + node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[dec_tlu_ctl.scala 583:49] + node _T_364 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 583:95] + node _T_365 = and(_T_363, _T_364) @[dec_tlu_ctl.scala 583:93] + pmu_fw_halt_req_ns <= _T_365 @[dec_tlu_ctl.scala 583:23] + node _T_366 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 584:85] + node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[dec_tlu_ctl.scala 584:83] + node _T_368 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 584:105] + node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 584:103] + node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[dec_tlu_ctl.scala 584:52] + internal_pmu_fw_halt_mode <= _T_370 @[dec_tlu_ctl.scala 584:30] + node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 587:45] + node _T_372 = and(_T_371, halt_taken) @[dec_tlu_ctl.scala 587:58] + node _T_373 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 587:73] + node _T_374 = and(_T_372, _T_373) @[dec_tlu_ctl.scala 587:71] + node _T_375 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 587:121] + node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[dec_tlu_ctl.scala 587:119] + node _T_377 = or(_T_374, _T_376) @[dec_tlu_ctl.scala 587:96] + node _T_378 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 587:143] + node _T_379 = and(_T_377, _T_378) @[dec_tlu_ctl.scala 587:141] + pmu_fw_tlu_halted <= _T_379 @[dec_tlu_ctl.scala 587:22] + node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 589:38] + cpu_halt_ack <= _T_380 @[dec_tlu_ctl.scala 589:17] + node _T_381 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 590:46] + node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[dec_tlu_ctl.scala 590:44] + node _T_383 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 590:91] + node _T_384 = and(io.o_cpu_halt_status, _T_383) @[dec_tlu_ctl.scala 590:89] + node _T_385 = not(debug_mode_status) @[dec_tlu_ctl.scala 590:111] + node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 590:109] + node _T_387 = or(_T_382, _T_386) @[dec_tlu_ctl.scala 590:65] + cpu_halt_status <= _T_387 @[dec_tlu_ctl.scala 590:20] + node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 591:41] + node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 591:88] + node _T_390 = or(_T_388, _T_389) @[dec_tlu_ctl.scala 591:68] + cpu_run_ack <= _T_390 @[dec_tlu_ctl.scala 591:16] + io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 593:27] + node _T_391 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 596:66] + node _T_392 = or(_T_391, soft_int_ready) @[dec_tlu_ctl.scala 596:84] + node _T_393 = or(_T_392, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 596:101] + node _T_394 = or(_T_393, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 596:125] + node _T_395 = and(io.dec_pic.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 596:172] + node _T_396 = or(_T_394, _T_395) @[dec_tlu_ctl.scala 596:149] + node _T_397 = and(_T_396, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 596:191] + node _T_398 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 596:216] + node _T_399 = and(_T_397, _T_398) @[dec_tlu_ctl.scala 596:214] + node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[dec_tlu_ctl.scala 596:45] + i_cpu_run_req_d1 <= _T_400 @[dec_tlu_ctl.scala 596:21] + reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 602:89] + _T_401 <= mdseac_locked_ns @[dec_tlu_ctl.scala 602:89] + mdseac_locked_f <= _T_401 @[dec_tlu_ctl.scala 602:57] + reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 603:72] + lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 603:72] + node _T_402 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 605:57] + node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[dec_tlu_ctl.scala 605:55] + lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 606:21] + node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 607:40] + node _T_404 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 607:64] + node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 607:62] + node _T_406 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 607:84] + node lsu_exc_valid_r = and(_T_405, _T_406) @[dec_tlu_ctl.scala 607:82] + reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 609:74] + _T_407 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 609:74] + lsu_exc_valid_r_d1 <= _T_407 @[dec_tlu_ctl.scala 609:41] + reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 610:73] + lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 610:73] + node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 611:40] + node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[dec_tlu_ctl.scala 611:38] + node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 612:38] + node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 613:38] + node _T_409 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 617:49] + node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[dec_tlu_ctl.scala 617:47] + node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 617:70] + node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 617:105] + node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[dec_tlu_ctl.scala 617:67] + node _T_413 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 620:52] + node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[dec_tlu_ctl.scala 620:50] + node _T_415 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 620:65] + node _T_416 = and(_T_414, _T_415) @[dec_tlu_ctl.scala 620:63] + node _T_417 = not(inst_acc_r) @[dec_tlu_ctl.scala 620:82] + node _T_418 = and(_T_416, _T_417) @[dec_tlu_ctl.scala 620:79] + node _T_419 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 620:96] + node _T_420 = and(_T_418, _T_419) @[dec_tlu_ctl.scala 620:94] + node _T_421 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 620:121] + node _T_422 = and(_T_420, _T_421) @[dec_tlu_ctl.scala 620:119] + node _T_423 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 620:148] + node tlu_i0_commit_cmt = and(_T_422, _T_423) @[dec_tlu_ctl.scala 620:146] + node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 623:38] + node _T_425 = or(_T_424, inst_acc_r) @[dec_tlu_ctl.scala 623:53] + node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 623:79] + node _T_427 = or(_T_425, _T_426) @[dec_tlu_ctl.scala 623:66] + node _T_428 = or(_T_427, i0_trigger_hit_r) @[dec_tlu_ctl.scala 623:104] + tlu_i0_kill_writeb_r <= _T_428 @[dec_tlu_ctl.scala 623:25] + io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 624:37] + node _T_429 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 629:44] + node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[dec_tlu_ctl.scala 629:42] + node _T_431 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 629:98] + node _T_432 = and(_T_430, _T_431) @[dec_tlu_ctl.scala 629:66] + node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 629:154] + node _T_434 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 629:175] + node _T_435 = and(_T_433, _T_434) @[dec_tlu_ctl.scala 629:173] + node _T_436 = or(_T_432, _T_435) @[dec_tlu_ctl.scala 629:137] + node _T_437 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 629:199] + node _T_438 = and(_T_436, _T_437) @[dec_tlu_ctl.scala 629:196] + node _T_439 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 629:220] + node _T_440 = and(_T_438, _T_439) @[dec_tlu_ctl.scala 629:217] + rfpc_i0_r <= _T_440 @[dec_tlu_ctl.scala 629:14] + node _T_441 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 632:70] + node _T_442 = and(iccm_repair_state_d1, _T_441) @[dec_tlu_ctl.scala 632:68] + node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[dec_tlu_ctl.scala 632:44] + iccm_repair_state_ns <= _T_443 @[dec_tlu_ctl.scala 632:25] + node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 638:52] + node _T_445 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 638:88] + node _T_446 = or(_T_445, mret_r) @[dec_tlu_ctl.scala 638:98] + node _T_447 = or(_T_446, take_reset) @[dec_tlu_ctl.scala 638:107] + node _T_448 = or(_T_447, illegal_r) @[dec_tlu_ctl.scala 638:120] + node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 638:176] + node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[dec_tlu_ctl.scala 638:153] + node _T_451 = or(_T_448, _T_450) @[dec_tlu_ctl.scala 638:132] + node _T_452 = not(_T_451) @[dec_tlu_ctl.scala 638:77] + node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[dec_tlu_ctl.scala 638:75] + node _T_453 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 641:59] + node _T_454 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 641:85] + node dec_tlu_br0_error_r = and(_T_453, _T_454) @[dec_tlu_ctl.scala 641:83] + node _T_455 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 642:71] + node _T_456 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 642:97] + node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[dec_tlu_ctl.scala 642:95] + node _T_457 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 643:55] + node _T_458 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 643:81] + node _T_459 = and(_T_457, _T_458) @[dec_tlu_ctl.scala 643:79] + node _T_460 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 643:106] + node _T_461 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 643:135] + node _T_462 = or(_T_460, _T_461) @[dec_tlu_ctl.scala 643:133] + node dec_tlu_br0_v_r = and(_T_459, _T_462) @[dec_tlu_ctl.scala 643:103] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 646:65] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 647:57] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 648:57] + io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 649:57] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 650:65] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 651:65] + node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 654:52] + node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 654:65] + node _T_465 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 654:91] + node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 654:89] + node _T_467 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 654:116] + node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 654:111] + node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 654:109] + node _T_470 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 654:133] + node _T_471 = and(_T_469, _T_470) @[dec_tlu_ctl.scala 654:131] + ebreak_r <= _T_471 @[dec_tlu_ctl.scala 654:14] + node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 655:52] + node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 655:65] + node _T_474 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 655:91] + node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 655:89] + node _T_476 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 655:111] + node _T_477 = and(_T_475, _T_476) @[dec_tlu_ctl.scala 655:109] + ecall_r <= _T_477 @[dec_tlu_ctl.scala 655:14] + node _T_478 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 656:18] + node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 656:47] + node _T_480 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 656:73] + node _T_481 = and(_T_479, _T_480) @[dec_tlu_ctl.scala 656:71] + node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 656:93] + node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 656:91] + illegal_r <= _T_483 @[dec_tlu_ctl.scala 656:14] + node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 657:58] + node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 657:71] + node _T_486 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 657:97] + node _T_487 = and(_T_485, _T_486) @[dec_tlu_ctl.scala 657:95] + node _T_488 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 657:117] + node _T_489 = and(_T_487, _T_488) @[dec_tlu_ctl.scala 657:115] + mret_r <= _T_489 @[dec_tlu_ctl.scala 657:20] + node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 659:50] + node _T_491 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 659:76] + node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 659:74] + node _T_493 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 659:97] + node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 659:95] + fence_i_r <= _T_494 @[dec_tlu_ctl.scala 659:17] + node _T_495 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 660:53] + node _T_496 = and(io.tlu_mem.ifu_ic_error_start, _T_495) @[dec_tlu_ctl.scala 660:51] + node _T_497 = not(debug_mode_status) @[dec_tlu_ctl.scala 660:75] + node _T_498 = or(_T_497, dcsr_single_step_running) @[dec_tlu_ctl.scala 660:101] + node _T_499 = and(_T_496, _T_498) @[dec_tlu_ctl.scala 660:72] + node _T_500 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 660:131] + node _T_501 = and(_T_499, _T_500) @[dec_tlu_ctl.scala 660:129] + ic_perr_r <= _T_501 @[dec_tlu_ctl.scala 660:17] + node _T_502 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 661:61] + node _T_503 = and(io.tlu_mem.ifu_iccm_rd_ecc_single_err, _T_502) @[dec_tlu_ctl.scala 661:59] + node _T_504 = not(debug_mode_status) @[dec_tlu_ctl.scala 661:83] + node _T_505 = or(_T_504, dcsr_single_step_running) @[dec_tlu_ctl.scala 661:109] + node _T_506 = and(_T_503, _T_505) @[dec_tlu_ctl.scala 661:80] + node _T_507 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 661:139] + node _T_508 = and(_T_506, _T_507) @[dec_tlu_ctl.scala 661:137] + iccm_sbecc_r <= _T_508 @[dec_tlu_ctl.scala 661:17] + node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 662:49] + inst_acc_r_raw <= _T_509 @[dec_tlu_ctl.scala 662:20] + node _T_510 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 663:35] + node _T_511 = and(inst_acc_r_raw, _T_510) @[dec_tlu_ctl.scala 663:33] + node _T_512 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 663:48] + node _T_513 = and(_T_511, _T_512) @[dec_tlu_ctl.scala 663:46] + inst_acc_r <= _T_513 @[dec_tlu_ctl.scala 663:15] + node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 666:64] + node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 666:77] + node _T_516 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 666:103] + node _T_517 = and(_T_515, _T_516) @[dec_tlu_ctl.scala 666:101] + node _T_518 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 666:127] + node _T_519 = and(_T_517, _T_518) @[dec_tlu_ctl.scala 666:121] + node _T_520 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 666:144] + node _T_521 = and(_T_519, _T_520) @[dec_tlu_ctl.scala 666:142] + ebreak_to_debug_mode_r <= _T_521 @[dec_tlu_ctl.scala 666:27] + reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 668:64] + _T_522 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 668:64] + ebreak_to_debug_mode_r_d1 <= _T_522 @[dec_tlu_ctl.scala 668:34] + io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 669:39] + node _T_523 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 682:41] + node _T_524 = or(_T_523, illegal_r) @[dec_tlu_ctl.scala 682:51] + node _T_525 = or(_T_524, inst_acc_r) @[dec_tlu_ctl.scala 682:63] + node _T_526 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 682:79] + node _T_527 = and(_T_525, _T_526) @[dec_tlu_ctl.scala 682:77] + node _T_528 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 682:92] + node i0_exception_valid_r = and(_T_527, _T_528) @[dec_tlu_ctl.scala 682:90] + node _T_529 = not(take_nmi) @[dec_tlu_ctl.scala 691:33] + node _T_530 = and(take_ext_int, _T_529) @[dec_tlu_ctl.scala 691:31] + node _T_531 = bits(_T_530, 0, 0) @[dec_tlu_ctl.scala 691:44] + node _T_532 = not(take_nmi) @[dec_tlu_ctl.scala 692:27] + node _T_533 = and(take_timer_int, _T_532) @[dec_tlu_ctl.scala 692:25] + node _T_534 = bits(_T_533, 0, 0) @[dec_tlu_ctl.scala 692:38] + node _T_535 = not(take_nmi) @[dec_tlu_ctl.scala 693:26] + node _T_536 = and(take_soft_int, _T_535) @[dec_tlu_ctl.scala 693:24] + node _T_537 = bits(_T_536, 0, 0) @[dec_tlu_ctl.scala 693:37] + node _T_538 = not(take_nmi) @[dec_tlu_ctl.scala 694:32] + node _T_539 = and(take_int_timer0_int, _T_538) @[dec_tlu_ctl.scala 694:30] + node _T_540 = bits(_T_539, 0, 0) @[dec_tlu_ctl.scala 694:43] + node _T_541 = not(take_nmi) @[dec_tlu_ctl.scala 695:32] + node _T_542 = and(take_int_timer1_int, _T_541) @[dec_tlu_ctl.scala 695:30] + node _T_543 = bits(_T_542, 0, 0) @[dec_tlu_ctl.scala 695:43] + node _T_544 = not(take_nmi) @[dec_tlu_ctl.scala 696:24] + node _T_545 = and(take_ce_int, _T_544) @[dec_tlu_ctl.scala 696:22] + node _T_546 = bits(_T_545, 0, 0) @[dec_tlu_ctl.scala 696:35] + node _T_547 = not(take_nmi) @[dec_tlu_ctl.scala 697:22] + node _T_548 = and(illegal_r, _T_547) @[dec_tlu_ctl.scala 697:20] + node _T_549 = bits(_T_548, 0, 0) @[dec_tlu_ctl.scala 697:33] + node _T_550 = not(take_nmi) @[dec_tlu_ctl.scala 698:21] + node _T_551 = and(ecall_r, _T_550) @[dec_tlu_ctl.scala 698:19] + node _T_552 = bits(_T_551, 0, 0) @[dec_tlu_ctl.scala 698:32] + node _T_553 = not(take_nmi) @[dec_tlu_ctl.scala 699:24] + node _T_554 = and(inst_acc_r, _T_553) @[dec_tlu_ctl.scala 699:22] + node _T_555 = bits(_T_554, 0, 0) @[dec_tlu_ctl.scala 699:35] + node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[dec_tlu_ctl.scala 700:20] + node _T_557 = not(take_nmi) @[dec_tlu_ctl.scala 700:42] + node _T_558 = and(_T_556, _T_557) @[dec_tlu_ctl.scala 700:40] + node _T_559 = bits(_T_558, 0, 0) @[dec_tlu_ctl.scala 700:53] + node _T_560 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 701:25] + node _T_561 = and(lsu_exc_ma_r, _T_560) @[dec_tlu_ctl.scala 701:23] + node _T_562 = not(take_nmi) @[dec_tlu_ctl.scala 701:41] + node _T_563 = and(_T_561, _T_562) @[dec_tlu_ctl.scala 701:39] + node _T_564 = bits(_T_563, 0, 0) @[dec_tlu_ctl.scala 701:52] + node _T_565 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 702:26] + node _T_566 = and(lsu_exc_acc_r, _T_565) @[dec_tlu_ctl.scala 702:24] + node _T_567 = not(take_nmi) @[dec_tlu_ctl.scala 702:42] + node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 702:40] + node _T_569 = bits(_T_568, 0, 0) @[dec_tlu_ctl.scala 702:53] + node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 703:23] + node _T_571 = not(take_nmi) @[dec_tlu_ctl.scala 703:40] + node _T_572 = and(_T_570, _T_571) @[dec_tlu_ctl.scala 703:38] + node _T_573 = bits(_T_572, 0, 0) @[dec_tlu_ctl.scala 703:51] + node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 704:24] + node _T_575 = not(take_nmi) @[dec_tlu_ctl.scala 704:41] + node _T_576 = and(_T_574, _T_575) @[dec_tlu_ctl.scala 704:39] + node _T_577 = bits(_T_576, 0, 0) @[dec_tlu_ctl.scala 704:52] node _T_578 = mux(_T_531, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_579 = mux(_T_534, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_580 = mux(_T_537, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -78991,281 +78981,281 @@ circuit quasar_wrapper : node _T_604 = or(_T_603, _T_591) @[Mux.scala 27:72] wire exc_cause_r : UInt<5> @[Mux.scala 27:72] exc_cause_r <= _T_604 @[Mux.scala 27:72] - node _T_605 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 717:24] - node _T_606 = and(_T_605, mstatus_mie_ns) @[dec_tlu_ctl.scala 717:49] - node _T_607 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 717:71] - node _T_608 = and(_T_606, _T_607) @[dec_tlu_ctl.scala 717:66] - node _T_609 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 717:92] - node _T_610 = and(_T_608, _T_609) @[dec_tlu_ctl.scala 717:84] - mhwakeup_ready <= _T_610 @[dec_tlu_ctl.scala 717:20] - node _T_611 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 718:23] - node _T_612 = and(_T_611, mstatus_mie_ns) @[dec_tlu_ctl.scala 718:48] - node _T_613 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 718:70] - node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 718:65] - node _T_615 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 718:91] - node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 718:83] - node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 718:104] - node _T_618 = and(_T_616, _T_617) @[dec_tlu_ctl.scala 718:102] - ext_int_ready <= _T_618 @[dec_tlu_ctl.scala 718:20] - node _T_619 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 719:23] - node _T_620 = and(_T_619, mstatus_mie_ns) @[dec_tlu_ctl.scala 719:48] - node _T_621 = bits(mip, 5, 5) @[dec_tlu_ctl.scala 719:70] - node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 719:65] - node _T_623 = bits(mie_ns, 5, 5) @[dec_tlu_ctl.scala 719:91] - node _T_624 = and(_T_622, _T_623) @[dec_tlu_ctl.scala 719:83] - ce_int_ready <= _T_624 @[dec_tlu_ctl.scala 719:20] - node _T_625 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 720:23] - node _T_626 = and(_T_625, mstatus_mie_ns) @[dec_tlu_ctl.scala 720:48] - node _T_627 = bits(mip, 0, 0) @[dec_tlu_ctl.scala 720:70] - node _T_628 = and(_T_626, _T_627) @[dec_tlu_ctl.scala 720:65] - node _T_629 = bits(mie_ns, 0, 0) @[dec_tlu_ctl.scala 720:91] - node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 720:83] - soft_int_ready <= _T_630 @[dec_tlu_ctl.scala 720:20] - node _T_631 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 721:23] - node _T_632 = and(_T_631, mstatus_mie_ns) @[dec_tlu_ctl.scala 721:48] - node _T_633 = bits(mip, 1, 1) @[dec_tlu_ctl.scala 721:70] - node _T_634 = and(_T_632, _T_633) @[dec_tlu_ctl.scala 721:65] - node _T_635 = bits(mie_ns, 1, 1) @[dec_tlu_ctl.scala 721:91] - node _T_636 = and(_T_634, _T_635) @[dec_tlu_ctl.scala 721:83] - timer_int_ready <= _T_636 @[dec_tlu_ctl.scala 721:20] - node _T_637 = bits(mie_ns, 4, 4) @[dec_tlu_ctl.scala 724:57] - node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[dec_tlu_ctl.scala 724:49] - node _T_638 = bits(mip, 4, 4) @[dec_tlu_ctl.scala 725:34] - node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[dec_tlu_ctl.scala 725:47] - node _T_639 = bits(mie_ns, 3, 3) @[dec_tlu_ctl.scala 726:57] - node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[dec_tlu_ctl.scala 726:49] - node _T_640 = bits(mip, 3, 3) @[dec_tlu_ctl.scala 727:34] - node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[dec_tlu_ctl.scala 727:47] - node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[dec_tlu_ctl.scala 731:52] - node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 731:74] - node int_timer_stalled = or(_T_642, mret_r) @[dec_tlu_ctl.scala 731:98] - node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 733:72] - node _T_644 = and(int_timer0_int_ready, _T_643) @[dec_tlu_ctl.scala 733:49] - node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 733:121] - node _T_646 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 733:147] - node _T_647 = and(_T_645, _T_646) @[dec_tlu_ctl.scala 733:145] - node _T_648 = not(take_ext_int_start) @[dec_tlu_ctl.scala 733:168] - node _T_649 = and(_T_647, _T_648) @[dec_tlu_ctl.scala 733:166] - node _T_650 = not(debug_mode_status) @[dec_tlu_ctl.scala 733:190] - node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 733:188] - node _T_652 = or(_T_644, _T_651) @[dec_tlu_ctl.scala 733:94] - int_timer0_int_hold <= _T_652 @[dec_tlu_ctl.scala 733:24] - node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 734:72] - node _T_654 = and(int_timer1_int_ready, _T_653) @[dec_tlu_ctl.scala 734:49] - node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 734:121] - node _T_656 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 734:147] - node _T_657 = and(_T_655, _T_656) @[dec_tlu_ctl.scala 734:145] - node _T_658 = not(take_ext_int_start) @[dec_tlu_ctl.scala 734:168] - node _T_659 = and(_T_657, _T_658) @[dec_tlu_ctl.scala 734:166] - node _T_660 = not(debug_mode_status) @[dec_tlu_ctl.scala 734:190] - node _T_661 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 734:188] - node _T_662 = or(_T_654, _T_661) @[dec_tlu_ctl.scala 734:94] - int_timer1_int_hold <= _T_662 @[dec_tlu_ctl.scala 734:24] - node _T_663 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 736:59] - node _T_664 = and(debug_mode_status, _T_663) @[dec_tlu_ctl.scala 736:57] - internal_dbg_halt_timers <= _T_664 @[dec_tlu_ctl.scala 736:29] - node _T_665 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 738:55] - node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 738:81] - node _T_667 = and(internal_dbg_halt_mode, _T_666) @[dec_tlu_ctl.scala 738:52] - node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 738:107] - node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 738:135] - node _T_670 = or(_T_669, take_nmi) @[dec_tlu_ctl.scala 738:155] - node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 738:166] - node _T_672 = or(_T_671, synchronous_flush_r) @[dec_tlu_ctl.scala 738:191] - node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 738:214] - node _T_674 = or(_T_673, mret_r) @[dec_tlu_ctl.scala 738:238] - node block_interrupts = or(_T_674, ext_int_freeze_d1) @[dec_tlu_ctl.scala 738:247] - reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 742:62] - _T_675 <= take_ext_int_start @[dec_tlu_ctl.scala 742:62] - take_ext_int_start_d1 <= _T_675 @[dec_tlu_ctl.scala 742:30] - reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 743:62] - _T_676 <= take_ext_int_start_d1 @[dec_tlu_ctl.scala 743:62] - take_ext_int_start_d2 <= _T_676 @[dec_tlu_ctl.scala 743:30] - reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 744:62] - _T_677 <= take_ext_int_start_d2 @[dec_tlu_ctl.scala 744:62] - take_ext_int_start_d3 <= _T_677 @[dec_tlu_ctl.scala 744:30] - reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 745:66] - _T_678 <= ext_int_freeze @[dec_tlu_ctl.scala 745:66] - ext_int_freeze_d1 <= _T_678 @[dec_tlu_ctl.scala 745:34] - node _T_679 = not(block_interrupts) @[dec_tlu_ctl.scala 746:47] - node _T_680 = and(ext_int_ready, _T_679) @[dec_tlu_ctl.scala 746:45] - take_ext_int_start <= _T_680 @[dec_tlu_ctl.scala 746:28] - node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[dec_tlu_ctl.scala 748:46] - node _T_682 = or(_T_681, take_ext_int_start_d2) @[dec_tlu_ctl.scala 748:70] - node _T_683 = or(_T_682, take_ext_int_start_d3) @[dec_tlu_ctl.scala 748:94] - ext_int_freeze <= _T_683 @[dec_tlu_ctl.scala 748:24] - node _T_684 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 749:67] - node _T_685 = not(_T_684) @[dec_tlu_ctl.scala 749:49] - node _T_686 = and(take_ext_int_start_d3, _T_685) @[dec_tlu_ctl.scala 749:47] - take_ext_int <= _T_686 @[dec_tlu_ctl.scala 749:22] - node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 750:49] - fast_int_meicpct <= _T_687 @[dec_tlu_ctl.scala 750:26] - ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 751:41] - node _T_688 = not(ext_int_ready) @[dec_tlu_ctl.scala 764:35] - node _T_689 = and(ce_int_ready, _T_688) @[dec_tlu_ctl.scala 764:33] - node _T_690 = not(block_interrupts) @[dec_tlu_ctl.scala 764:52] - node _T_691 = and(_T_689, _T_690) @[dec_tlu_ctl.scala 764:50] - take_ce_int <= _T_691 @[dec_tlu_ctl.scala 764:17] - node _T_692 = not(ext_int_ready) @[dec_tlu_ctl.scala 765:38] - node _T_693 = and(soft_int_ready, _T_692) @[dec_tlu_ctl.scala 765:36] - node _T_694 = not(ce_int_ready) @[dec_tlu_ctl.scala 765:55] - node _T_695 = and(_T_693, _T_694) @[dec_tlu_ctl.scala 765:53] - node _T_696 = not(block_interrupts) @[dec_tlu_ctl.scala 765:71] - node _T_697 = and(_T_695, _T_696) @[dec_tlu_ctl.scala 765:69] - take_soft_int <= _T_697 @[dec_tlu_ctl.scala 765:18] - node _T_698 = not(soft_int_ready) @[dec_tlu_ctl.scala 766:40] - node _T_699 = and(timer_int_ready, _T_698) @[dec_tlu_ctl.scala 766:38] - node _T_700 = not(ext_int_ready) @[dec_tlu_ctl.scala 766:58] - node _T_701 = and(_T_699, _T_700) @[dec_tlu_ctl.scala 766:56] - node _T_702 = not(ce_int_ready) @[dec_tlu_ctl.scala 766:75] - node _T_703 = and(_T_701, _T_702) @[dec_tlu_ctl.scala 766:73] - node _T_704 = not(block_interrupts) @[dec_tlu_ctl.scala 766:91] - node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 766:89] - take_timer_int <= _T_705 @[dec_tlu_ctl.scala 766:19] - node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 767:49] - node _T_707 = and(_T_706, int_timer0_int_possible) @[dec_tlu_ctl.scala 767:74] - node _T_708 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 767:102] - node _T_709 = and(_T_707, _T_708) @[dec_tlu_ctl.scala 767:100] - node _T_710 = not(timer_int_ready) @[dec_tlu_ctl.scala 767:129] - node _T_711 = and(_T_709, _T_710) @[dec_tlu_ctl.scala 767:127] - node _T_712 = not(soft_int_ready) @[dec_tlu_ctl.scala 767:148] - node _T_713 = and(_T_711, _T_712) @[dec_tlu_ctl.scala 767:146] - node _T_714 = not(ext_int_ready) @[dec_tlu_ctl.scala 767:166] - node _T_715 = and(_T_713, _T_714) @[dec_tlu_ctl.scala 767:164] - node _T_716 = not(ce_int_ready) @[dec_tlu_ctl.scala 767:183] - node _T_717 = and(_T_715, _T_716) @[dec_tlu_ctl.scala 767:181] - node _T_718 = not(block_interrupts) @[dec_tlu_ctl.scala 767:199] - node _T_719 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 767:197] - take_int_timer0_int <= _T_719 @[dec_tlu_ctl.scala 767:24] - node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 768:49] - node _T_721 = and(_T_720, int_timer1_int_possible) @[dec_tlu_ctl.scala 768:74] - node _T_722 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 768:102] - node _T_723 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 768:100] - node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 768:152] - node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 768:129] - node _T_726 = and(_T_723, _T_725) @[dec_tlu_ctl.scala 768:127] - node _T_727 = not(timer_int_ready) @[dec_tlu_ctl.scala 768:179] - node _T_728 = and(_T_726, _T_727) @[dec_tlu_ctl.scala 768:177] - node _T_729 = not(soft_int_ready) @[dec_tlu_ctl.scala 768:198] - node _T_730 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 768:196] - node _T_731 = not(ext_int_ready) @[dec_tlu_ctl.scala 768:216] - node _T_732 = and(_T_730, _T_731) @[dec_tlu_ctl.scala 768:214] - node _T_733 = not(ce_int_ready) @[dec_tlu_ctl.scala 768:233] - node _T_734 = and(_T_732, _T_733) @[dec_tlu_ctl.scala 768:231] - node _T_735 = not(block_interrupts) @[dec_tlu_ctl.scala 768:249] - node _T_736 = and(_T_734, _T_735) @[dec_tlu_ctl.scala 768:247] - take_int_timer1_int <= _T_736 @[dec_tlu_ctl.scala 768:24] - node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 769:32] - take_reset <= _T_737 @[dec_tlu_ctl.scala 769:15] - node _T_738 = not(internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 770:35] - node _T_739 = and(nmi_int_detected, _T_738) @[dec_tlu_ctl.scala 770:33] - node _T_740 = not(internal_dbg_halt_mode) @[dec_tlu_ctl.scala 770:65] - node _T_741 = bits(dcsr, 11, 11) @[dec_tlu_ctl.scala 770:125] - node _T_742 = and(dcsr_single_step_running_f, _T_741) @[dec_tlu_ctl.scala 770:119] - node _T_743 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 770:141] - node _T_744 = and(_T_742, _T_743) @[dec_tlu_ctl.scala 770:139] - node _T_745 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 770:166] - node _T_746 = and(_T_744, _T_745) @[dec_tlu_ctl.scala 770:164] - node _T_747 = or(_T_740, _T_746) @[dec_tlu_ctl.scala 770:89] - node _T_748 = and(_T_739, _T_747) @[dec_tlu_ctl.scala 770:62] - node _T_749 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 770:195] - node _T_750 = and(_T_748, _T_749) @[dec_tlu_ctl.scala 770:193] - node _T_751 = not(mret_r) @[dec_tlu_ctl.scala 770:218] - node _T_752 = and(_T_750, _T_751) @[dec_tlu_ctl.scala 770:216] - node _T_753 = not(take_reset) @[dec_tlu_ctl.scala 770:228] - node _T_754 = and(_T_752, _T_753) @[dec_tlu_ctl.scala 770:226] - node _T_755 = not(ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 770:242] - node _T_756 = and(_T_754, _T_755) @[dec_tlu_ctl.scala 770:240] - node _T_757 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 770:269] - node _T_758 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 770:332] - node _T_759 = and(take_ext_int_start_d3, _T_758) @[dec_tlu_ctl.scala 770:313] - node _T_760 = or(_T_757, _T_759) @[dec_tlu_ctl.scala 770:288] - node _T_761 = and(_T_756, _T_760) @[dec_tlu_ctl.scala 770:266] - take_nmi <= _T_761 @[dec_tlu_ctl.scala 770:13] - node _T_762 = or(take_ext_int, take_timer_int) @[dec_tlu_ctl.scala 773:38] - node _T_763 = or(_T_762, take_soft_int) @[dec_tlu_ctl.scala 773:55] - node _T_764 = or(_T_763, take_nmi) @[dec_tlu_ctl.scala 773:71] - node _T_765 = or(_T_764, take_ce_int) @[dec_tlu_ctl.scala 773:82] - node _T_766 = or(_T_765, take_int_timer0_int) @[dec_tlu_ctl.scala 773:96] - node _T_767 = or(_T_766, take_int_timer1_int) @[dec_tlu_ctl.scala 773:118] - interrupt_valid_r <= _T_767 @[dec_tlu_ctl.scala 773:22] - node _T_768 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 778:34] + node _T_605 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 715:23] + node _T_606 = and(_T_605, mstatus_mie_ns) @[dec_tlu_ctl.scala 715:48] + node _T_607 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 715:70] + node _T_608 = and(_T_606, _T_607) @[dec_tlu_ctl.scala 715:65] + node _T_609 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 715:91] + node _T_610 = and(_T_608, _T_609) @[dec_tlu_ctl.scala 715:83] + mhwakeup_ready <= _T_610 @[dec_tlu_ctl.scala 715:20] + node _T_611 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 716:23] + node _T_612 = and(_T_611, mstatus_mie_ns) @[dec_tlu_ctl.scala 716:48] + node _T_613 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 716:70] + node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 716:65] + node _T_615 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 716:91] + node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 716:83] + node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 716:104] + node _T_618 = and(_T_616, _T_617) @[dec_tlu_ctl.scala 716:102] + ext_int_ready <= _T_618 @[dec_tlu_ctl.scala 716:20] + node _T_619 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 717:23] + node _T_620 = and(_T_619, mstatus_mie_ns) @[dec_tlu_ctl.scala 717:48] + node _T_621 = bits(mip, 5, 5) @[dec_tlu_ctl.scala 717:70] + node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 717:65] + node _T_623 = bits(mie_ns, 5, 5) @[dec_tlu_ctl.scala 717:91] + node _T_624 = and(_T_622, _T_623) @[dec_tlu_ctl.scala 717:83] + ce_int_ready <= _T_624 @[dec_tlu_ctl.scala 717:20] + node _T_625 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 718:23] + node _T_626 = and(_T_625, mstatus_mie_ns) @[dec_tlu_ctl.scala 718:48] + node _T_627 = bits(mip, 0, 0) @[dec_tlu_ctl.scala 718:70] + node _T_628 = and(_T_626, _T_627) @[dec_tlu_ctl.scala 718:65] + node _T_629 = bits(mie_ns, 0, 0) @[dec_tlu_ctl.scala 718:91] + node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 718:83] + soft_int_ready <= _T_630 @[dec_tlu_ctl.scala 718:20] + node _T_631 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 719:23] + node _T_632 = and(_T_631, mstatus_mie_ns) @[dec_tlu_ctl.scala 719:48] + node _T_633 = bits(mip, 1, 1) @[dec_tlu_ctl.scala 719:70] + node _T_634 = and(_T_632, _T_633) @[dec_tlu_ctl.scala 719:65] + node _T_635 = bits(mie_ns, 1, 1) @[dec_tlu_ctl.scala 719:91] + node _T_636 = and(_T_634, _T_635) @[dec_tlu_ctl.scala 719:83] + timer_int_ready <= _T_636 @[dec_tlu_ctl.scala 719:20] + node _T_637 = bits(mie_ns, 4, 4) @[dec_tlu_ctl.scala 722:57] + node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[dec_tlu_ctl.scala 722:49] + node _T_638 = bits(mip, 4, 4) @[dec_tlu_ctl.scala 723:34] + node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[dec_tlu_ctl.scala 723:47] + node _T_639 = bits(mie_ns, 3, 3) @[dec_tlu_ctl.scala 724:57] + node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[dec_tlu_ctl.scala 724:49] + node _T_640 = bits(mip, 3, 3) @[dec_tlu_ctl.scala 725:34] + node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[dec_tlu_ctl.scala 725:47] + node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[dec_tlu_ctl.scala 729:52] + node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 729:74] + node int_timer_stalled = or(_T_642, mret_r) @[dec_tlu_ctl.scala 729:98] + node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 731:72] + node _T_644 = and(int_timer0_int_ready, _T_643) @[dec_tlu_ctl.scala 731:49] + node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 731:121] + node _T_646 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 731:147] + node _T_647 = and(_T_645, _T_646) @[dec_tlu_ctl.scala 731:145] + node _T_648 = not(take_ext_int_start) @[dec_tlu_ctl.scala 731:168] + node _T_649 = and(_T_647, _T_648) @[dec_tlu_ctl.scala 731:166] + node _T_650 = not(debug_mode_status) @[dec_tlu_ctl.scala 731:190] + node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 731:188] + node _T_652 = or(_T_644, _T_651) @[dec_tlu_ctl.scala 731:94] + int_timer0_int_hold <= _T_652 @[dec_tlu_ctl.scala 731:24] + node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 732:72] + node _T_654 = and(int_timer1_int_ready, _T_653) @[dec_tlu_ctl.scala 732:49] + node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 732:121] + node _T_656 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 732:147] + node _T_657 = and(_T_655, _T_656) @[dec_tlu_ctl.scala 732:145] + node _T_658 = not(take_ext_int_start) @[dec_tlu_ctl.scala 732:168] + node _T_659 = and(_T_657, _T_658) @[dec_tlu_ctl.scala 732:166] + node _T_660 = not(debug_mode_status) @[dec_tlu_ctl.scala 732:190] + node _T_661 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 732:188] + node _T_662 = or(_T_654, _T_661) @[dec_tlu_ctl.scala 732:94] + int_timer1_int_hold <= _T_662 @[dec_tlu_ctl.scala 732:24] + node _T_663 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 734:59] + node _T_664 = and(debug_mode_status, _T_663) @[dec_tlu_ctl.scala 734:57] + internal_dbg_halt_timers <= _T_664 @[dec_tlu_ctl.scala 734:29] + node _T_665 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 736:55] + node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 736:81] + node _T_667 = and(internal_dbg_halt_mode, _T_666) @[dec_tlu_ctl.scala 736:52] + node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 736:107] + node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 736:135] + node _T_670 = or(_T_669, take_nmi) @[dec_tlu_ctl.scala 736:155] + node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 736:166] + node _T_672 = or(_T_671, synchronous_flush_r) @[dec_tlu_ctl.scala 736:191] + node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 736:214] + node _T_674 = or(_T_673, mret_r) @[dec_tlu_ctl.scala 736:238] + node block_interrupts = or(_T_674, ext_int_freeze_d1) @[dec_tlu_ctl.scala 736:247] + reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 740:74] + _T_675 <= take_ext_int_start @[dec_tlu_ctl.scala 740:74] + take_ext_int_start_d1 <= _T_675 @[dec_tlu_ctl.scala 740:41] + reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 741:74] + _T_676 <= take_ext_int_start_d1 @[dec_tlu_ctl.scala 741:74] + take_ext_int_start_d2 <= _T_676 @[dec_tlu_ctl.scala 741:41] + reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 742:74] + _T_677 <= take_ext_int_start_d2 @[dec_tlu_ctl.scala 742:74] + take_ext_int_start_d3 <= _T_677 @[dec_tlu_ctl.scala 742:41] + reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 743:90] + _T_678 <= ext_int_freeze @[dec_tlu_ctl.scala 743:90] + ext_int_freeze_d1 <= _T_678 @[dec_tlu_ctl.scala 743:57] + node _T_679 = not(block_interrupts) @[dec_tlu_ctl.scala 744:68] + node _T_680 = and(ext_int_ready, _T_679) @[dec_tlu_ctl.scala 744:66] + take_ext_int_start <= _T_680 @[dec_tlu_ctl.scala 744:49] + node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[dec_tlu_ctl.scala 746:46] + node _T_682 = or(_T_681, take_ext_int_start_d2) @[dec_tlu_ctl.scala 746:70] + node _T_683 = or(_T_682, take_ext_int_start_d3) @[dec_tlu_ctl.scala 746:94] + ext_int_freeze <= _T_683 @[dec_tlu_ctl.scala 746:24] + node _T_684 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 747:67] + node _T_685 = not(_T_684) @[dec_tlu_ctl.scala 747:49] + node _T_686 = and(take_ext_int_start_d3, _T_685) @[dec_tlu_ctl.scala 747:47] + take_ext_int <= _T_686 @[dec_tlu_ctl.scala 747:22] + node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 748:49] + fast_int_meicpct <= _T_687 @[dec_tlu_ctl.scala 748:26] + ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 749:41] + node _T_688 = not(ext_int_ready) @[dec_tlu_ctl.scala 762:35] + node _T_689 = and(ce_int_ready, _T_688) @[dec_tlu_ctl.scala 762:33] + node _T_690 = not(block_interrupts) @[dec_tlu_ctl.scala 762:52] + node _T_691 = and(_T_689, _T_690) @[dec_tlu_ctl.scala 762:50] + take_ce_int <= _T_691 @[dec_tlu_ctl.scala 762:17] + node _T_692 = not(ext_int_ready) @[dec_tlu_ctl.scala 763:38] + node _T_693 = and(soft_int_ready, _T_692) @[dec_tlu_ctl.scala 763:36] + node _T_694 = not(ce_int_ready) @[dec_tlu_ctl.scala 763:55] + node _T_695 = and(_T_693, _T_694) @[dec_tlu_ctl.scala 763:53] + node _T_696 = not(block_interrupts) @[dec_tlu_ctl.scala 763:71] + node _T_697 = and(_T_695, _T_696) @[dec_tlu_ctl.scala 763:69] + take_soft_int <= _T_697 @[dec_tlu_ctl.scala 763:18] + node _T_698 = not(soft_int_ready) @[dec_tlu_ctl.scala 764:40] + node _T_699 = and(timer_int_ready, _T_698) @[dec_tlu_ctl.scala 764:38] + node _T_700 = not(ext_int_ready) @[dec_tlu_ctl.scala 764:58] + node _T_701 = and(_T_699, _T_700) @[dec_tlu_ctl.scala 764:56] + node _T_702 = not(ce_int_ready) @[dec_tlu_ctl.scala 764:75] + node _T_703 = and(_T_701, _T_702) @[dec_tlu_ctl.scala 764:73] + node _T_704 = not(block_interrupts) @[dec_tlu_ctl.scala 764:91] + node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 764:89] + take_timer_int <= _T_705 @[dec_tlu_ctl.scala 764:19] + node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 765:49] + node _T_707 = and(_T_706, int_timer0_int_possible) @[dec_tlu_ctl.scala 765:74] + node _T_708 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 765:102] + node _T_709 = and(_T_707, _T_708) @[dec_tlu_ctl.scala 765:100] + node _T_710 = not(timer_int_ready) @[dec_tlu_ctl.scala 765:129] + node _T_711 = and(_T_709, _T_710) @[dec_tlu_ctl.scala 765:127] + node _T_712 = not(soft_int_ready) @[dec_tlu_ctl.scala 765:148] + node _T_713 = and(_T_711, _T_712) @[dec_tlu_ctl.scala 765:146] + node _T_714 = not(ext_int_ready) @[dec_tlu_ctl.scala 765:166] + node _T_715 = and(_T_713, _T_714) @[dec_tlu_ctl.scala 765:164] + node _T_716 = not(ce_int_ready) @[dec_tlu_ctl.scala 765:183] + node _T_717 = and(_T_715, _T_716) @[dec_tlu_ctl.scala 765:181] + node _T_718 = not(block_interrupts) @[dec_tlu_ctl.scala 765:199] + node _T_719 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 765:197] + take_int_timer0_int <= _T_719 @[dec_tlu_ctl.scala 765:24] + node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 766:49] + node _T_721 = and(_T_720, int_timer1_int_possible) @[dec_tlu_ctl.scala 766:74] + node _T_722 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 766:102] + node _T_723 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 766:100] + node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 766:152] + node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 766:129] + node _T_726 = and(_T_723, _T_725) @[dec_tlu_ctl.scala 766:127] + node _T_727 = not(timer_int_ready) @[dec_tlu_ctl.scala 766:179] + node _T_728 = and(_T_726, _T_727) @[dec_tlu_ctl.scala 766:177] + node _T_729 = not(soft_int_ready) @[dec_tlu_ctl.scala 766:198] + node _T_730 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 766:196] + node _T_731 = not(ext_int_ready) @[dec_tlu_ctl.scala 766:216] + node _T_732 = and(_T_730, _T_731) @[dec_tlu_ctl.scala 766:214] + node _T_733 = not(ce_int_ready) @[dec_tlu_ctl.scala 766:233] + node _T_734 = and(_T_732, _T_733) @[dec_tlu_ctl.scala 766:231] + node _T_735 = not(block_interrupts) @[dec_tlu_ctl.scala 766:249] + node _T_736 = and(_T_734, _T_735) @[dec_tlu_ctl.scala 766:247] + take_int_timer1_int <= _T_736 @[dec_tlu_ctl.scala 766:24] + node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 767:32] + take_reset <= _T_737 @[dec_tlu_ctl.scala 767:15] + node _T_738 = not(internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 768:35] + node _T_739 = and(nmi_int_detected, _T_738) @[dec_tlu_ctl.scala 768:33] + node _T_740 = not(internal_dbg_halt_mode) @[dec_tlu_ctl.scala 768:65] + node _T_741 = bits(dcsr, 11, 11) @[dec_tlu_ctl.scala 768:125] + node _T_742 = and(dcsr_single_step_running_f, _T_741) @[dec_tlu_ctl.scala 768:119] + node _T_743 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 768:141] + node _T_744 = and(_T_742, _T_743) @[dec_tlu_ctl.scala 768:139] + node _T_745 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 768:166] + node _T_746 = and(_T_744, _T_745) @[dec_tlu_ctl.scala 768:164] + node _T_747 = or(_T_740, _T_746) @[dec_tlu_ctl.scala 768:89] + node _T_748 = and(_T_739, _T_747) @[dec_tlu_ctl.scala 768:62] + node _T_749 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 768:195] + node _T_750 = and(_T_748, _T_749) @[dec_tlu_ctl.scala 768:193] + node _T_751 = not(mret_r) @[dec_tlu_ctl.scala 768:218] + node _T_752 = and(_T_750, _T_751) @[dec_tlu_ctl.scala 768:216] + node _T_753 = not(take_reset) @[dec_tlu_ctl.scala 768:228] + node _T_754 = and(_T_752, _T_753) @[dec_tlu_ctl.scala 768:226] + node _T_755 = not(ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 768:242] + node _T_756 = and(_T_754, _T_755) @[dec_tlu_ctl.scala 768:240] + node _T_757 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 768:269] + node _T_758 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 768:332] + node _T_759 = and(take_ext_int_start_d3, _T_758) @[dec_tlu_ctl.scala 768:313] + node _T_760 = or(_T_757, _T_759) @[dec_tlu_ctl.scala 768:288] + node _T_761 = and(_T_756, _T_760) @[dec_tlu_ctl.scala 768:266] + take_nmi <= _T_761 @[dec_tlu_ctl.scala 768:13] + node _T_762 = or(take_ext_int, take_timer_int) @[dec_tlu_ctl.scala 771:38] + node _T_763 = or(_T_762, take_soft_int) @[dec_tlu_ctl.scala 771:55] + node _T_764 = or(_T_763, take_nmi) @[dec_tlu_ctl.scala 771:71] + node _T_765 = or(_T_764, take_ce_int) @[dec_tlu_ctl.scala 771:82] + node _T_766 = or(_T_765, take_int_timer0_int) @[dec_tlu_ctl.scala 771:96] + node _T_767 = or(_T_766, take_int_timer1_int) @[dec_tlu_ctl.scala 771:118] + interrupt_valid_r <= _T_767 @[dec_tlu_ctl.scala 771:22] + node _T_768 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 776:34] node _T_769 = cat(_T_768, UInt<1>("h00")) @[Cat.scala 29:58] node _T_770 = cat(UInt<25>("h00"), exc_cause_r) @[Cat.scala 29:58] node _T_771 = cat(_T_770, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_772 = add(_T_769, _T_771) @[dec_tlu_ctl.scala 778:51] - node vectored_path = tail(_T_772, 1) @[dec_tlu_ctl.scala 778:51] - node _T_773 = bits(take_nmi, 0, 0) @[dec_tlu_ctl.scala 779:38] - node _T_774 = bits(mtvec, 0, 0) @[dec_tlu_ctl.scala 779:67] - node _T_775 = eq(_T_774, UInt<1>("h01")) @[dec_tlu_ctl.scala 779:71] - node _T_776 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 779:104] + node _T_772 = add(_T_769, _T_771) @[dec_tlu_ctl.scala 776:51] + node vectored_path = tail(_T_772, 1) @[dec_tlu_ctl.scala 776:51] + node _T_773 = bits(take_nmi, 0, 0) @[dec_tlu_ctl.scala 777:38] + node _T_774 = bits(mtvec, 0, 0) @[dec_tlu_ctl.scala 777:67] + node _T_775 = eq(_T_774, UInt<1>("h01")) @[dec_tlu_ctl.scala 777:71] + node _T_776 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 777:104] node _T_777 = cat(_T_776, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_778 = mux(_T_775, vectored_path, _T_777) @[dec_tlu_ctl.scala 779:61] - node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[dec_tlu_ctl.scala 779:28] - node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[dec_tlu_ctl.scala 780:36] - node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 780:48] - node _T_781 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 780:96] - node _T_782 = and(i_cpu_run_req_d1, _T_781) @[dec_tlu_ctl.scala 780:94] - node _T_783 = or(_T_780, _T_782) @[dec_tlu_ctl.scala 780:74] - node _T_784 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 780:131] - node _T_785 = and(rfpc_i0_r, _T_784) @[dec_tlu_ctl.scala 780:129] - node sel_npc_r = or(_T_783, _T_785) @[dec_tlu_ctl.scala 780:116] - node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 781:43] - node sel_npc_resume = or(_T_786, pause_expired_r) @[dec_tlu_ctl.scala 781:66] - node _T_787 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 782:65] - node _T_788 = not(_T_787) @[dec_tlu_ctl.scala 782:47] - node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[dec_tlu_ctl.scala 782:45] - node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[dec_tlu_ctl.scala 783:49] - node _T_790 = or(_T_789, lsu_exc_valid_r) @[dec_tlu_ctl.scala 783:61] - node _T_791 = or(_T_790, fence_i_r) @[dec_tlu_ctl.scala 783:79] - node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 783:91] - node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 783:108] - node _T_794 = or(_T_793, debug_resume_req_f) @[dec_tlu_ctl.scala 783:135] - node _T_795 = or(_T_794, sel_npc_resume) @[dec_tlu_ctl.scala 783:157] - node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 783:175] - node _T_797 = or(_T_796, i0_trigger_hit_r) @[dec_tlu_ctl.scala 783:201] - synchronous_flush_r <= _T_797 @[dec_tlu_ctl.scala 783:25] - node _T_798 = or(interrupt_valid_r, mret_r) @[dec_tlu_ctl.scala 784:43] - node _T_799 = or(_T_798, synchronous_flush_r) @[dec_tlu_ctl.scala 784:52] - node _T_800 = or(_T_799, take_halt) @[dec_tlu_ctl.scala 784:74] - node _T_801 = or(_T_800, take_reset) @[dec_tlu_ctl.scala 784:86] - node _T_802 = or(_T_801, take_ext_int_start) @[dec_tlu_ctl.scala 784:99] - tlu_flush_lower_r <= _T_802 @[dec_tlu_ctl.scala 784:22] - node _T_803 = bits(take_reset, 0, 0) @[dec_tlu_ctl.scala 786:42] - node _T_804 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 787:72] - node _T_805 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 788:66] - node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 788:84] - node _T_807 = and(_T_805, _T_806) @[dec_tlu_ctl.scala 788:73] - node _T_808 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 789:66] - node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 789:84] - node _T_810 = and(_T_808, _T_809) @[dec_tlu_ctl.scala 789:73] - node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 789:114] - node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 789:91] - node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 789:132] - node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 789:121] - node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 790:75] - node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 790:96] - node _T_817 = and(_T_815, _T_816) @[dec_tlu_ctl.scala 790:82] - node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 791:80] - node _T_819 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 791:120] - node _T_820 = and(i0_trigger_hit_r, _T_819) @[dec_tlu_ctl.scala 791:118] - node _T_821 = or(_T_818, _T_820) @[dec_tlu_ctl.scala 791:98] - node _T_822 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 791:145] - node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 791:143] - node _T_824 = not(sel_fir_addr) @[dec_tlu_ctl.scala 791:166] - node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 791:164] - node _T_826 = bits(_T_825, 0, 0) @[dec_tlu_ctl.scala 791:181] - node _T_827 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 791:205] + node _T_778 = mux(_T_775, vectored_path, _T_777) @[dec_tlu_ctl.scala 777:61] + node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[dec_tlu_ctl.scala 777:28] + node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[dec_tlu_ctl.scala 778:36] + node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 778:48] + node _T_781 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 778:96] + node _T_782 = and(i_cpu_run_req_d1, _T_781) @[dec_tlu_ctl.scala 778:94] + node _T_783 = or(_T_780, _T_782) @[dec_tlu_ctl.scala 778:74] + node _T_784 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 778:131] + node _T_785 = and(rfpc_i0_r, _T_784) @[dec_tlu_ctl.scala 778:129] + node sel_npc_r = or(_T_783, _T_785) @[dec_tlu_ctl.scala 778:116] + node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 779:43] + node sel_npc_resume = or(_T_786, pause_expired_r) @[dec_tlu_ctl.scala 779:66] + node _T_787 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 780:65] + node _T_788 = not(_T_787) @[dec_tlu_ctl.scala 780:47] + node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[dec_tlu_ctl.scala 780:45] + node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[dec_tlu_ctl.scala 781:49] + node _T_790 = or(_T_789, lsu_exc_valid_r) @[dec_tlu_ctl.scala 781:61] + node _T_791 = or(_T_790, fence_i_r) @[dec_tlu_ctl.scala 781:79] + node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 781:91] + node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 781:108] + node _T_794 = or(_T_793, debug_resume_req_f) @[dec_tlu_ctl.scala 781:135] + node _T_795 = or(_T_794, sel_npc_resume) @[dec_tlu_ctl.scala 781:157] + node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 781:175] + node _T_797 = or(_T_796, i0_trigger_hit_r) @[dec_tlu_ctl.scala 781:201] + synchronous_flush_r <= _T_797 @[dec_tlu_ctl.scala 781:25] + node _T_798 = or(interrupt_valid_r, mret_r) @[dec_tlu_ctl.scala 782:43] + node _T_799 = or(_T_798, synchronous_flush_r) @[dec_tlu_ctl.scala 782:52] + node _T_800 = or(_T_799, take_halt) @[dec_tlu_ctl.scala 782:74] + node _T_801 = or(_T_800, take_reset) @[dec_tlu_ctl.scala 782:86] + node _T_802 = or(_T_801, take_ext_int_start) @[dec_tlu_ctl.scala 782:99] + tlu_flush_lower_r <= _T_802 @[dec_tlu_ctl.scala 782:22] + node _T_803 = bits(take_reset, 0, 0) @[dec_tlu_ctl.scala 784:42] + node _T_804 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 785:72] + node _T_805 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 786:66] + node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 786:84] + node _T_807 = and(_T_805, _T_806) @[dec_tlu_ctl.scala 786:73] + node _T_808 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 787:66] + node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 787:84] + node _T_810 = and(_T_808, _T_809) @[dec_tlu_ctl.scala 787:73] + node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 787:114] + node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 787:91] + node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 787:132] + node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 787:121] + node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 788:75] + node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 788:96] + node _T_817 = and(_T_815, _T_816) @[dec_tlu_ctl.scala 788:82] + node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 789:80] + node _T_819 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 789:120] + node _T_820 = and(i0_trigger_hit_r, _T_819) @[dec_tlu_ctl.scala 789:118] + node _T_821 = or(_T_818, _T_820) @[dec_tlu_ctl.scala 789:98] + node _T_822 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 789:145] + node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 789:143] + node _T_824 = not(sel_fir_addr) @[dec_tlu_ctl.scala 789:166] + node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 789:164] + node _T_826 = bits(_T_825, 0, 0) @[dec_tlu_ctl.scala 789:181] + node _T_827 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 789:205] node _T_828 = cat(_T_827, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_829 = not(take_nmi) @[dec_tlu_ctl.scala 792:58] - node _T_830 = and(_T_829, mret_r) @[dec_tlu_ctl.scala 792:68] - node _T_831 = bits(_T_830, 0, 0) @[dec_tlu_ctl.scala 792:78] - node _T_832 = not(take_nmi) @[dec_tlu_ctl.scala 793:58] - node _T_833 = and(_T_832, debug_resume_req_f) @[dec_tlu_ctl.scala 793:68] - node _T_834 = bits(_T_833, 0, 0) @[dec_tlu_ctl.scala 793:90] - node _T_835 = not(take_nmi) @[dec_tlu_ctl.scala 794:58] - node _T_836 = and(_T_835, sel_npc_resume) @[dec_tlu_ctl.scala 794:68] - node _T_837 = bits(_T_836, 0, 0) @[dec_tlu_ctl.scala 794:86] + node _T_829 = not(take_nmi) @[dec_tlu_ctl.scala 790:58] + node _T_830 = and(_T_829, mret_r) @[dec_tlu_ctl.scala 790:68] + node _T_831 = bits(_T_830, 0, 0) @[dec_tlu_ctl.scala 790:78] + node _T_832 = not(take_nmi) @[dec_tlu_ctl.scala 791:58] + node _T_833 = and(_T_832, debug_resume_req_f) @[dec_tlu_ctl.scala 791:68] + node _T_834 = bits(_T_833, 0, 0) @[dec_tlu_ctl.scala 791:90] + node _T_835 = not(take_nmi) @[dec_tlu_ctl.scala 792:58] + node _T_836 = and(_T_835, sel_npc_resume) @[dec_tlu_ctl.scala 792:68] + node _T_837 = bits(_T_836, 0, 0) @[dec_tlu_ctl.scala 792:86] node _T_838 = mux(_T_804, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72] node _T_839 = mux(_T_807, npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_840 = mux(_T_814, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] @@ -79283,461 +79273,461 @@ circuit quasar_wrapper : node _T_852 = or(_T_851, _T_845) @[Mux.scala 27:72] wire _T_853 : UInt<31> @[Mux.scala 27:72] _T_853 <= _T_852 @[Mux.scala 27:72] - node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[dec_tlu_ctl.scala 786:30] - reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 797:64] - tlu_flush_path_r_d1 <= tlu_flush_path_r @[dec_tlu_ctl.scala 797:64] - io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 799:41] - io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 801:49] - io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 802:49] - node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[dec_tlu_ctl.scala 805:45] - node _T_855 = or(_T_854, interrupt_valid_r) @[dec_tlu_ctl.scala 805:68] - node _T_856 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 805:110] - node _T_857 = and(i0_trigger_hit_r, _T_856) @[dec_tlu_ctl.scala 805:108] - node exc_or_int_valid_r = or(_T_855, _T_857) @[dec_tlu_ctl.scala 805:88] - reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 807:90] - _T_858 <= interrupt_valid_r @[dec_tlu_ctl.scala 807:90] - interrupt_valid_r_d1 <= _T_858 @[dec_tlu_ctl.scala 807:57] - reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 808:89] - i0_exception_valid_r_d1 <= i0_exception_valid_r @[dec_tlu_ctl.scala 808:89] - reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 809:90] - _T_859 <= exc_or_int_valid_r @[dec_tlu_ctl.scala 809:90] - exc_or_int_valid_r_d1 <= _T_859 @[dec_tlu_ctl.scala 809:57] - reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 810:89] - exc_cause_wb <= exc_cause_r @[dec_tlu_ctl.scala 810:89] - node _T_860 = not(illegal_r) @[dec_tlu_ctl.scala 811:119] - node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[dec_tlu_ctl.scala 811:117] - reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 811:97] - i0_valid_wb <= _T_861 @[dec_tlu_ctl.scala 811:97] - reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 812:89] - trigger_hit_r_d1 <= i0_trigger_hit_r @[dec_tlu_ctl.scala 812:89] - reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 813:98] - _T_862 <= take_nmi @[dec_tlu_ctl.scala 813:98] - take_nmi_r_d1 <= _T_862 @[dec_tlu_ctl.scala 813:65] - reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 814:90] - _T_863 <= pause_expired_r @[dec_tlu_ctl.scala 814:90] - pause_expired_wb <= _T_863 @[dec_tlu_ctl.scala 814:57] - inst csr of csr_tlu @[dec_tlu_ctl.scala 816:15] + node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[dec_tlu_ctl.scala 784:30] + reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 795:64] + tlu_flush_path_r_d1 <= tlu_flush_path_r @[dec_tlu_ctl.scala 795:64] + io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 797:41] + io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 798:49] + io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 799:49] + node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[dec_tlu_ctl.scala 802:45] + node _T_855 = or(_T_854, interrupt_valid_r) @[dec_tlu_ctl.scala 802:68] + node _T_856 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 802:110] + node _T_857 = and(i0_trigger_hit_r, _T_856) @[dec_tlu_ctl.scala 802:108] + node exc_or_int_valid_r = or(_T_855, _T_857) @[dec_tlu_ctl.scala 802:88] + reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 804:91] + _T_858 <= interrupt_valid_r @[dec_tlu_ctl.scala 804:91] + interrupt_valid_r_d1 <= _T_858 @[dec_tlu_ctl.scala 804:57] + reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 805:75] + i0_exception_valid_r_d1 <= i0_exception_valid_r @[dec_tlu_ctl.scala 805:75] + reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 806:91] + _T_859 <= exc_or_int_valid_r @[dec_tlu_ctl.scala 806:91] + exc_or_int_valid_r_d1 <= _T_859 @[dec_tlu_ctl.scala 806:57] + reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 807:91] + exc_cause_wb <= exc_cause_r @[dec_tlu_ctl.scala 807:91] + node _T_860 = not(illegal_r) @[dec_tlu_ctl.scala 808:121] + node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[dec_tlu_ctl.scala 808:119] + reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 808:99] + i0_valid_wb <= _T_861 @[dec_tlu_ctl.scala 808:99] + reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 809:83] + trigger_hit_r_d1 <= i0_trigger_hit_r @[dec_tlu_ctl.scala 809:83] + reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 810:107] + _T_862 <= take_nmi @[dec_tlu_ctl.scala 810:107] + take_nmi_r_d1 <= _T_862 @[dec_tlu_ctl.scala 810:73] + reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 811:91] + _T_863 <= pause_expired_r @[dec_tlu_ctl.scala 811:91] + pause_expired_wb <= _T_863 @[dec_tlu_ctl.scala 811:57] + inst csr of csr_tlu @[dec_tlu_ctl.scala 813:15] csr.clock <= clock csr.reset <= reset - csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 817:44] - csr.io.active_clk <= io.active_clk @[dec_tlu_ctl.scala 818:44] - csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 819:44] - csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 820:44] - csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 821:44] - csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 822:44] - csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 823:44] - csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 824:44] - csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 825:44] - csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 826:44] - csr.io.dma_iccm_stall_any <= io.tlu_dma.dma_iccm_stall_any @[dec_tlu_ctl.scala 827:44] - csr.io.dma_dccm_stall_any <= io.tlu_dma.dma_dccm_stall_any @[dec_tlu_ctl.scala 828:44] - csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 829:44] - csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 830:44] - csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 831:44] - csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 832:44] - csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 833:44] - csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 834:44] - csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 834:44] - csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 834:44] - csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 834:44] - csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 834:44] - csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 834:44] - csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 834:44] - csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 834:44] - csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 834:44] - csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 834:44] - csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 835:44] - csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 836:44] - csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 837:44] - csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 838:44] - csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 839:44] - csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 840:44] - csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 841:44] - csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 842:44] - csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 843:44] - csr.io.dma_pmu_dccm_write <= io.tlu_dma.dma_pmu_dccm_write @[dec_tlu_ctl.scala 844:44] - csr.io.dma_pmu_dccm_read <= io.tlu_dma.dma_pmu_dccm_read @[dec_tlu_ctl.scala 845:44] - csr.io.dma_pmu_any_write <= io.tlu_dma.dma_pmu_any_write @[dec_tlu_ctl.scala 846:44] - csr.io.dma_pmu_any_read <= io.tlu_dma.dma_pmu_any_read @[dec_tlu_ctl.scala 847:44] - csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 848:44] - csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 849:44] - csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 850:44] - csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 851:44] - csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 852:44] - csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 853:44] - csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 854:44] - csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 855:44] - csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 856:44] - csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 857:44] - csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 858:44] - csr.io.pic_pl <= io.dec_pic.pic_pl @[dec_tlu_ctl.scala 859:44] - csr.io.pic_claimid <= io.dec_pic.pic_claimid @[dec_tlu_ctl.scala 860:44] - csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 861:44] - csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 862:44] - csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 863:44] - csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 864:44] - csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 865:44] - csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 866:44] - csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 866:44] - csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 866:44] - csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 866:44] - csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 866:44] - csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 866:44] - csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 867:44] - csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 868:44] - csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 869:44] - csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 870:44] - csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 871:44] - csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 872:44] - csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 873:44] - io.dec_pic.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 874:52] - io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 875:52] - io.dec_pic.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 876:52] - io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 877:44] - io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 878:44] - io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 879:44] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 880:52] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 880:52] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 880:52] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 880:52] - io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 881:40] - io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 881:40] - io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 882:40] - io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 883:40] - io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 884:40] - io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 885:40] - io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 886:40] - io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 887:40] - io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 888:40] - io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 889:40] - io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 890:40] - io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 891:40] - io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 892:40] - io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 893:40] - io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 894:40] - io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 895:40] - io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 896:40] - io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 897:40] - io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 898:40] - io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 899:48] - io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 900:52] - io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 901:47] - io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 902:52] - io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 903:48] - io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 904:52] - io.tlu_dma.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 905:48] - csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 906:44] - csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 907:44] - csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 907:44] - csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 907:44] - csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 907:44] - csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 907:44] - csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 907:44] - csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 908:44] - csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 909:44] - csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 910:44] - csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 911:44] - csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 912:44] - csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 913:44] - csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 914:44] - csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 917:39] - csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 918:39] - csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[dec_tlu_ctl.scala 919:39] - csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 920:39] - csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 921:39] - csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 922:39] - csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 923:39] - csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 924:39] - csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 925:39] - csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[dec_tlu_ctl.scala 926:39] - csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 927:39] - csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 928:39] - csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 929:39] - csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 930:39] - csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 931:39] - csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 932:39] - csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 933:39] - csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 934:39] - csr.io.i0_exception_valid_r <= i0_exception_valid_r @[dec_tlu_ctl.scala 935:39] - csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 936:39] - csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 937:39] - csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[dec_tlu_ctl.scala 938:39] - csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 939:39] - csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 940:39] - csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 941:39] - csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 942:39] - csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 943:39] - csr.io.exc_cause_r <= exc_cause_r @[dec_tlu_ctl.scala 944:39] - csr.io.i0_valid_wb <= i0_valid_wb @[dec_tlu_ctl.scala 945:39] - csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 946:39] - csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 947:39] - csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 948:39] - csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 949:39] - csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[dec_tlu_ctl.scala 950:39] - csr.io.exc_cause_wb <= exc_cause_wb @[dec_tlu_ctl.scala 951:39] - csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 952:39] - csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 953:39] - csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 954:39] - csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 955:39] - csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 956:39] - csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 957:39] - csr.io.mdseac_locked_f <= mdseac_locked_f @[dec_tlu_ctl.scala 958:39] - csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 959:39] - csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 960:39] - csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[dec_tlu_ctl.scala 961:39] - csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[dec_tlu_ctl.scala 962:39] - csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[dec_tlu_ctl.scala 963:39] - csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[dec_tlu_ctl.scala 964:39] - csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 965:39] - csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 966:39] - csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 967:39] - csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 968:39] - csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 969:51] - csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 970:47] - csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 971:43] - csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[dec_tlu_ctl.scala 972:43] - csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 973:43] - csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 974:39] - csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 975:51] - csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 976:39] - csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 977:39] - csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 978:39] - csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 979:39] - csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 980:39] - csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 981:39] - csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 982:39] - csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 983:39] - csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 984:39] - csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 985:39] - csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 986:39] - csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 987:39] - csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 988:39] - csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 989:39] - csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 990:39] - csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 991:39] - csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 992:39] - csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 992:39] - npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 994:31] - npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 995:31] - mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 996:31] - mepc <= csr.io.mepc @[dec_tlu_ctl.scala 997:31] - mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 998:31] - force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 999:31] - dpc <= csr.io.dpc @[dec_tlu_ctl.scala 1000:31] - mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 1001:31] - dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 1002:31] - fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 1003:31] - mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 1004:31] - dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 1005:31] - mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 1006:31] - mip <= csr.io.mip @[dec_tlu_ctl.scala 1007:31] - mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 1008:33] - mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 1008:33] - mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 1008:33] - mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 1008:33] - inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1009:22] + csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 814:44] + csr.io.active_clk <= io.active_clk @[dec_tlu_ctl.scala 815:44] + csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 816:44] + csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 817:44] + csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 818:44] + csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 819:44] + csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 820:44] + csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 821:44] + csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 822:44] + csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 823:44] + csr.io.dma_iccm_stall_any <= io.tlu_dma.dma_iccm_stall_any @[dec_tlu_ctl.scala 824:44] + csr.io.dma_dccm_stall_any <= io.tlu_dma.dma_dccm_stall_any @[dec_tlu_ctl.scala 825:44] + csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 826:44] + csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 827:44] + csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 828:44] + csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 829:44] + csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 830:44] + csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 831:44] + csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 831:44] + csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 831:44] + csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 831:44] + csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 831:44] + csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 831:44] + csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 831:44] + csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 831:44] + csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 831:44] + csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 831:44] + csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 832:44] + csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 833:44] + csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 834:44] + csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 835:44] + csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 836:44] + csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 837:44] + csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 838:44] + csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 839:44] + csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 840:44] + csr.io.dma_pmu_dccm_write <= io.tlu_dma.dma_pmu_dccm_write @[dec_tlu_ctl.scala 841:44] + csr.io.dma_pmu_dccm_read <= io.tlu_dma.dma_pmu_dccm_read @[dec_tlu_ctl.scala 842:44] + csr.io.dma_pmu_any_write <= io.tlu_dma.dma_pmu_any_write @[dec_tlu_ctl.scala 843:44] + csr.io.dma_pmu_any_read <= io.tlu_dma.dma_pmu_any_read @[dec_tlu_ctl.scala 844:44] + csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 845:44] + csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 846:44] + csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 847:44] + csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 848:44] + csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 849:44] + csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 850:44] + csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 851:44] + csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 852:44] + csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 853:44] + csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 854:44] + csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 855:44] + csr.io.pic_pl <= io.dec_pic.pic_pl @[dec_tlu_ctl.scala 856:44] + csr.io.pic_claimid <= io.dec_pic.pic_claimid @[dec_tlu_ctl.scala 857:44] + csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 858:44] + csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 859:44] + csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 860:44] + csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 861:44] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 862:44] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 863:44] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 863:44] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 863:44] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 863:44] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 863:44] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 863:44] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 864:44] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 865:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 866:44] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 867:44] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 868:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 869:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 870:44] + io.dec_pic.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 871:44] + io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 872:44] + io.dec_pic.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 873:44] + io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 874:44] + io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 875:44] + io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 876:44] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 877:44] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 877:44] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 877:44] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 877:44] + io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 878:40] + io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 878:40] + io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 879:40] + io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 880:40] + io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 881:40] + io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 882:40] + io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 883:40] + io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 884:40] + io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 885:40] + io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 886:40] + io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 887:40] + io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 888:40] + io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 889:40] + io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 890:40] + io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 891:40] + io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 892:40] + io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 893:40] + io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 894:40] + io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 895:40] + io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 896:48] + io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 897:52] + io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 898:47] + io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 899:52] + io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 900:48] + io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 901:52] + io.tlu_dma.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 902:48] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 903:44] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 904:44] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 904:44] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 904:44] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 904:44] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 904:44] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 904:44] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 905:44] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 906:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 907:44] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 908:44] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 909:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 910:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 911:44] + csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 914:39] + csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 915:39] + csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[dec_tlu_ctl.scala 916:39] + csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 917:39] + csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 918:39] + csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 919:39] + csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 920:39] + csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 921:39] + csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 922:39] + csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[dec_tlu_ctl.scala 923:39] + csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 924:39] + csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 925:39] + csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 926:39] + csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 927:39] + csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 928:39] + csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 929:39] + csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 930:39] + csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 931:39] + csr.io.i0_exception_valid_r <= i0_exception_valid_r @[dec_tlu_ctl.scala 932:39] + csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 933:39] + csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 934:39] + csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[dec_tlu_ctl.scala 935:39] + csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 936:39] + csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 937:39] + csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 938:39] + csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 939:39] + csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 940:39] + csr.io.exc_cause_r <= exc_cause_r @[dec_tlu_ctl.scala 941:39] + csr.io.i0_valid_wb <= i0_valid_wb @[dec_tlu_ctl.scala 942:39] + csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 943:39] + csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 944:39] + csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 945:39] + csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 946:39] + csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[dec_tlu_ctl.scala 947:39] + csr.io.exc_cause_wb <= exc_cause_wb @[dec_tlu_ctl.scala 948:39] + csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 949:39] + csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 950:39] + csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 951:39] + csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 952:39] + csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 953:39] + csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 954:39] + csr.io.mdseac_locked_f <= mdseac_locked_f @[dec_tlu_ctl.scala 955:39] + csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 956:39] + csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 957:39] + csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[dec_tlu_ctl.scala 958:39] + csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[dec_tlu_ctl.scala 959:39] + csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[dec_tlu_ctl.scala 960:39] + csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[dec_tlu_ctl.scala 961:39] + csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 962:39] + csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 963:39] + csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 964:39] + csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 965:39] + csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 966:65] + csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 967:49] + csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 968:49] + csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[dec_tlu_ctl.scala 969:49] + csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 970:49] + csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 971:39] + csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 972:73] + csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 973:39] + csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 974:39] + csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 975:39] + csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 976:39] + csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 977:39] + csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 978:39] + csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 979:39] + csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 980:39] + csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 981:39] + csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 982:39] + csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 983:39] + csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 984:39] + csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 985:39] + csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 986:39] + csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 987:39] + csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 988:39] + csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 989:39] + csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 989:39] + npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 991:31] + npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 992:31] + mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 993:31] + mepc <= csr.io.mepc @[dec_tlu_ctl.scala 994:31] + mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 995:31] + force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 996:31] + dpc <= csr.io.dpc @[dec_tlu_ctl.scala 997:31] + mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 998:31] + dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 999:31] + fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 1000:31] + mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 1001:31] + dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 1002:31] + mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 1003:31] + mip <= csr.io.mip @[dec_tlu_ctl.scala 1004:31] + mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 1005:31] + mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 1005:31] + mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 1005:31] + mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 1005:31] + inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1006:22] csr_read.clock <= clock csr_read.reset <= reset - csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1010:37] - csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1011:16] - csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1011:16] - csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1011:16] - csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1011:16] - node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1013:42] - node _T_865 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1013:67] - node _T_866 = and(_T_864, _T_865) @[dec_tlu_ctl.scala 1013:65] - io.dec_tlu_presync_d <= _T_866 @[dec_tlu_ctl.scala 1013:23] - node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1014:43] - io.dec_tlu_postsync_d <= _T_867 @[dec_tlu_ctl.scala 1014:23] - node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1017:50] - node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1017:72] - node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1017:92] - node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1017:112] - node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1017:134] - node _T_873 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1017:159] - node conditionally_illegal = and(_T_872, _T_873) @[dec_tlu_ctl.scala 1017:157] - node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1018:55] - node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1018:73] - node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1018:92] - node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1018:115] - node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1018:136] - node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1018:158] - node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1018:179] - node _T_881 = not(_T_880) @[dec_tlu_ctl.scala 1018:36] - node _T_882 = or(_T_881, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1018:201] - node _T_883 = and(csr_pkt.legal, _T_882) @[dec_tlu_ctl.scala 1018:33] - node _T_884 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1018:223] - node _T_885 = and(_T_883, _T_884) @[dec_tlu_ctl.scala 1018:221] - node _T_886 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1018:243] - node valid_csr = and(_T_885, _T_886) @[dec_tlu_ctl.scala 1018:241] - node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1020:46] - node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1020:107] - node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1020:129] - node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1020:150] - node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1020:172] - node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1020:193] - node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[dec_tlu_ctl.scala 1020:82] - node _T_894 = not(_T_893) @[dec_tlu_ctl.scala 1020:59] - node _T_895 = and(_T_887, _T_894) @[dec_tlu_ctl.scala 1020:57] - io.dec_csr_legal_d <= _T_895 @[dec_tlu_ctl.scala 1020:20] + csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1007:37] + csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1008:16] + csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1008:16] + csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1008:16] + csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1008:16] + node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1010:42] + node _T_865 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1010:67] + node _T_866 = and(_T_864, _T_865) @[dec_tlu_ctl.scala 1010:65] + io.dec_tlu_presync_d <= _T_866 @[dec_tlu_ctl.scala 1010:23] + node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1011:43] + io.dec_tlu_postsync_d <= _T_867 @[dec_tlu_ctl.scala 1011:23] + node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1014:50] + node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1014:72] + node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1014:92] + node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1014:112] + node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1014:134] + node _T_873 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1014:159] + node conditionally_illegal = and(_T_872, _T_873) @[dec_tlu_ctl.scala 1014:157] + node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1015:55] + node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1015:73] + node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1015:92] + node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1015:115] + node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1015:136] + node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1015:158] + node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1015:179] + node _T_881 = not(_T_880) @[dec_tlu_ctl.scala 1015:36] + node _T_882 = or(_T_881, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1015:201] + node _T_883 = and(csr_pkt.legal, _T_882) @[dec_tlu_ctl.scala 1015:33] + node _T_884 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1015:223] + node _T_885 = and(_T_883, _T_884) @[dec_tlu_ctl.scala 1015:221] + node _T_886 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1015:243] + node valid_csr = and(_T_885, _T_886) @[dec_tlu_ctl.scala 1015:241] + node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1017:46] + node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1017:107] + node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1017:129] + node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1017:150] + node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1017:172] + node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1017:193] + node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[dec_tlu_ctl.scala 1017:82] + node _T_894 = not(_T_893) @[dec_tlu_ctl.scala 1017:59] + node _T_895 = and(_T_887, _T_894) @[dec_tlu_ctl.scala 1017:57] + io.dec_csr_legal_d <= _T_895 @[dec_tlu_ctl.scala 1017:20] module dec_trigger : input clock : Clock @@ -81579,84 +81569,84 @@ circuit quasar_wrapper : tlu.io.dbg_resume_req <= io.dbg_resume_req @[dec.scala 245:45] tlu.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 246:45] tlu.io.dec_div_active <= decode.io.dec_div_active @[dec.scala 247:45] - tlu.io.timer_int <= io.timer_int @[dec.scala 252:45] - tlu.io.soft_int <= io.soft_int @[dec.scala 253:45] - tlu.io.core_id <= io.core_id @[dec.scala 254:45] - tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[dec.scala 255:45] - tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[dec.scala 256:45] - tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec.scala 257:45] - io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[dec.scala 258:28] - io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[dec.scala 259:28] - io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[dec.scala 260:28] - io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[dec.scala 261:28] - io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[dec.scala 262:28] - io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[dec.scala 263:51] - io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 264:29] - io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 264:29] - io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 264:29] - io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 264:29] - io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 264:29] - io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 264:29] - io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 264:29] - io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 264:29] - io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 264:29] - io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 264:29] - io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 264:29] - io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 264:29] - io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 264:29] - io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 264:29] - io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 264:29] - io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 264:29] - io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 264:29] - io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 264:29] - io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 264:29] - io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 264:29] - io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 264:29] - io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 264:29] - io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 264:29] - io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 264:29] - io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 264:29] - io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 264:29] - io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 264:29] - io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 264:29] - io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[dec.scala 265:29] - io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[dec.scala 266:29] - io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[dec.scala 267:29] - io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[dec.scala 268:29] - io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[dec.scala 269:29] - io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[dec.scala 270:29] - io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[dec.scala 271:29] - io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 274:34] - io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[dec.scala 275:29] - io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[dec.scala 276:29] - io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[dec.scala 277:29] - io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[dec.scala 278:29] - dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[dec.scala 279:32] - dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[dec.scala 280:32] - dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 281:32] - dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[dec.scala 282:32] - dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 283:32] - io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[dec.scala 284:35] - io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[dec.scala 285:36] - io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[dec.scala 286:36] - io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[dec.scala 287:36] - io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[dec.scala 288:36] - io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[dec.scala 289:36] - io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[dec.scala 290:36] - io.rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb1 @[dec.scala 294:32] + tlu.io.timer_int <= io.timer_int @[dec.scala 248:45] + tlu.io.soft_int <= io.soft_int @[dec.scala 249:45] + tlu.io.core_id <= io.core_id @[dec.scala 250:45] + tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[dec.scala 251:45] + tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[dec.scala 252:45] + tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec.scala 253:45] + io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[dec.scala 254:28] + io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[dec.scala 255:28] + io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[dec.scala 256:28] + io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[dec.scala 257:28] + io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[dec.scala 258:28] + io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[dec.scala 259:51] + io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 260:29] + io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 260:29] + io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 260:29] + io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 260:29] + io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 260:29] + io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 260:29] + io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 260:29] + io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 260:29] + io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 260:29] + io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 260:29] + io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 260:29] + io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 260:29] + io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 260:29] + io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 260:29] + io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 260:29] + io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 260:29] + io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 260:29] + io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 260:29] + io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 260:29] + io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 260:29] + io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 260:29] + io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 260:29] + io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 260:29] + io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 260:29] + io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 260:29] + io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 260:29] + io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 260:29] + io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 260:29] + io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[dec.scala 261:29] + io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[dec.scala 262:29] + io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[dec.scala 263:29] + io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[dec.scala 264:29] + io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[dec.scala 265:29] + io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[dec.scala 266:29] + io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[dec.scala 267:29] + io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 268:34] + io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[dec.scala 269:29] + io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[dec.scala 270:29] + io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[dec.scala 271:29] + io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[dec.scala 272:29] + dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[dec.scala 273:32] + dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[dec.scala 274:32] + dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 275:32] + dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[dec.scala 276:32] + dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 277:32] + io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[dec.scala 278:35] + io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[dec.scala 279:36] + io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[dec.scala 280:36] + io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[dec.scala 281:36] + io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[dec.scala 282:36] + io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[dec.scala 283:36] + io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[dec.scala 284:36] + io.rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb1 @[dec.scala 288:32] node _T = cat(decode.io.dec_i0_pc_wb1, UInt<1>("h00")) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_address_ip <= _T @[dec.scala 295:35] - node _T_1 = or(tlu.io.dec_tlu_i0_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 296:98] + io.rv_trace_pkt.rv_i_address_ip <= _T @[dec.scala 289:35] + node _T_1 = or(tlu.io.dec_tlu_i0_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 290:98] node _T_2 = cat(tlu.io.dec_tlu_int_valid_wb1, _T_1) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_valid_ip <= _T_2 @[dec.scala 296:33] + io.rv_trace_pkt.rv_i_valid_ip <= _T_2 @[dec.scala 290:33] node _T_3 = cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_exception_ip <= _T_3 @[dec.scala 297:37] - node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[dec.scala 298:65] - io.rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[dec.scala 298:34] + io.rv_trace_pkt.rv_i_exception_ip <= _T_3 @[dec.scala 291:37] + node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[dec.scala 292:65] + io.rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[dec.scala 292:34] node _T_5 = cat(tlu.io.dec_tlu_int_valid_wb1, UInt<1>("h00")) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_interrupt_ip <= _T_5 @[dec.scala 299:37] - io.rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 300:32] - io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[dec.scala 304:21] + io.rv_trace_pkt.rv_i_interrupt_ip <= _T_5 @[dec.scala 293:37] + io.rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 294:32] + io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[dec.scala 298:21] extmodule gated_latch_755 : output Q : Clock @@ -85962,10 +85952,10 @@ circuit quasar_wrapper : wire i0_pred_correct_upper_d : UInt<1> @[exu.scala 48:41] wire i0_flush_upper_d : UInt<1> @[exu.scala 49:45] io.exu_bp.exu_mp_pkt.bits.prett <= UInt<1>("h00") @[exu.scala 50:57] - io.exu_bp.exu_mp_pkt.bits.br_start_error <= UInt<1>("h00") @[exu.scala 51:43] - io.exu_bp.exu_mp_pkt.bits.br_error <= UInt<1>("h00") @[exu.scala 52:49] - io.exu_bp.exu_mp_pkt.valid <= UInt<1>("h00") @[exu.scala 53:55] - i0_pp_r.bits.toffset <= UInt<1>("h00") @[exu.scala 54:33] + io.exu_bp.exu_mp_pkt.bits.br_start_error <= UInt<1>("h00") @[exu.scala 51:44] + io.exu_bp.exu_mp_pkt.bits.br_error <= UInt<1>("h00") @[exu.scala 52:39] + io.exu_bp.exu_mp_pkt.valid <= UInt<1>("h00") @[exu.scala 53:53] + i0_pp_r.bits.toffset <= UInt<1>("h00") @[exu.scala 54:39] node x_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 56:69] node r_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 57:69] node x_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 1, 1) @[exu.scala 58:68] @@ -86370,7 +86360,7 @@ circuit quasar_wrapper : node _T_138 = or(_T_137, _T_136) @[Mux.scala 27:72] wire muldiv_rs2_d : UInt<32> @[Mux.scala 27:72] muldiv_rs2_d <= _T_138 @[Mux.scala 27:72] - node _T_139 = bits(io.dec_exu.dec_alu.dec_csr_ren_d, 0, 0) @[exu.scala 141:63] + node _T_139 = bits(io.dec_exu.dec_alu.dec_csr_ren_d, 0, 0) @[exu.scala 141:62] node _T_140 = mux(_T_139, i0_rs1_d, io.dec_exu.decode_exu.exu_csr_rs1_x) @[exu.scala 141:28] csr_rs1_in_d <= _T_140 @[exu.scala 141:22] inst i_alu of exu_alu_ctl @[exu.scala 144:19] @@ -86439,10 +86429,10 @@ circuit quasar_wrapper : i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[exu.scala 159:41] i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[exu.scala 159:41] i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[exu.scala 160:27] - inst i_mul of exu_mul_ctl @[exu.scala 162:19] + inst i_mul of exu_mul_ctl @[exu.scala 162:21] i_mul.clock <= clock i_mul.reset <= reset - i_mul.io.scan_mode <= io.scan_mode @[exu.scala 163:33] + i_mul.io.scan_mode <= io.scan_mode @[exu.scala 163:25] i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 164:41] i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 164:41] i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 164:41] @@ -86464,7 +86454,7 @@ circuit quasar_wrapper : i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 164:41] i_mul.io.rs1_in <= muldiv_rs1_d @[exu.scala 165:41] i_mul.io.rs2_in <= muldiv_rs2_d @[exu.scala 166:41] - inst i_div of exu_div_ctl @[exu.scala 169:19] + inst i_div of exu_div_ctl @[exu.scala 169:21] i_div.clock <= clock i_div.reset <= reset i_div.io.dec_div.dec_div_cancel <= io.dec_exu.dec_div.dec_div_cancel @[exu.scala 170:20] @@ -86578,31 +86568,31 @@ circuit quasar_wrapper : node _T_178 = eq(_T_177, UInt<1>("h00")) @[exu.scala 215:69] node _T_179 = and(_T_176, _T_178) @[exu.scala 215:67] node after_flush_eghr = mux(_T_179, ghr_d, ghr_x) @[exu.scala 215:42] - io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 218:48] - io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 219:48] - io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 220:48] - io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 221:48] - io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 222:48] - io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 223:48] - io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 224:48] - io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 225:48] - node _T_180 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 226:96] - io.exu_bp.exu_mp_pkt.bits.hist <= _T_180 @[exu.scala 226:66] - node _T_181 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 227:91] - io.exu_bp.exu_mp_pkt.bits.toffset <= _T_181 @[exu.scala 227:58] - io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 228:43] - node _T_182 = bits(final_predpipe_mp, 12, 5) @[exu.scala 229:87] - io.exu_bp.exu_mp_index <= _T_182 @[exu.scala 229:66] - node _T_183 = bits(final_predpipe_mp, 4, 0) @[exu.scala 230:79] - io.exu_bp.exu_mp_btag <= _T_183 @[exu.scala 230:58] - node _T_184 = bits(final_predpipe_mp, 20, 13) @[exu.scala 231:64] - io.exu_bp.exu_mp_eghr <= _T_184 @[exu.scala 231:43] - node _T_185 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 232:98] - node _T_186 = mux(_T_185, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, i0_flush_path_d) @[exu.scala 232:56] - io.exu_flush_path_final <= _T_186 @[exu.scala 232:50] - node _T_187 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 233:96] - node _T_188 = mux(_T_187, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 233:72] - io.dec_exu.tlu_exu.exu_npc_r <= _T_188 @[exu.scala 233:66] + io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 218:37] + io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 219:37] + io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 220:37] + io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 221:37] + io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 222:37] + io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 223:37] + io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 224:37] + io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 225:37] + node _T_180 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 226:79] + io.exu_bp.exu_mp_pkt.bits.hist <= _T_180 @[exu.scala 226:49] + node _T_181 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 227:74] + io.exu_bp.exu_mp_pkt.bits.toffset <= _T_181 @[exu.scala 227:41] + io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 228:37] + node _T_182 = bits(final_predpipe_mp, 12, 5) @[exu.scala 229:88] + io.exu_bp.exu_mp_index <= _T_182 @[exu.scala 229:67] + node _T_183 = bits(final_predpipe_mp, 4, 0) @[exu.scala 230:82] + io.exu_bp.exu_mp_btag <= _T_183 @[exu.scala 230:61] + node _T_184 = bits(final_predpipe_mp, 20, 13) @[exu.scala 231:58] + io.exu_bp.exu_mp_eghr <= _T_184 @[exu.scala 231:37] + node _T_185 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 232:81] + node _T_186 = mux(_T_185, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, i0_flush_path_d) @[exu.scala 232:39] + io.exu_flush_path_final <= _T_186 @[exu.scala 232:33] + node _T_187 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 233:79] + node _T_188 = mux(_T_187, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 233:55] + io.dec_exu.tlu_exu.exu_npc_r <= _T_188 @[exu.scala 233:49] module lsu_addrcheck : input clock : Clock @@ -91451,10 +91441,10 @@ circuit quasar_wrapper : is_ldst_hi_r <= UInt<1>("h00") wire is_ldst_lo_r : UInt<1> is_ldst_lo_r <= UInt<1>("h00") - io.sec_data_hi_m <= UInt<1>("h00") @[lsu_ecc.scala 90:32] - io.sec_data_lo_m <= UInt<1>("h00") @[lsu_ecc.scala 91:32] - io.lsu_single_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 92:30] - io.lsu_double_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 93:30] + io.sec_data_hi_m <= UInt<1>("h00") @[lsu_ecc.scala 88:32] + io.sec_data_lo_m <= UInt<1>("h00") @[lsu_ecc.scala 89:32] + io.lsu_single_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 90:30] + io.lsu_double_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 91:30] wire _T : UInt<1>[18] @[lib.scala 173:18] wire _T_1 : UInt<1>[18] @[lib.scala 174:18] wire _T_2 : UInt<1>[18] @[lib.scala 175:18] @@ -92843,107 +92833,107 @@ circuit quasar_wrapper : node _T_1118 = xorr(_T_1116) @[lib.scala 127:23] node _T_1119 = xor(_T_1117, _T_1118) @[lib.scala 127:18] node dccm_wdata_ecc_hi_any = cat(_T_1119, _T_1116) @[Cat.scala 29:58] - when UInt<1>("h00") : @[lsu_ecc.scala 103:30] - node _T_1120 = bits(io.lsu_addr_r, 2, 2) @[lsu_ecc.scala 104:33] - node _T_1121 = bits(io.end_addr_r, 2, 2) @[lsu_ecc.scala 104:54] - node _T_1122 = neq(_T_1120, _T_1121) @[lsu_ecc.scala 104:37] - ldst_dual_r <= _T_1122 @[lsu_ecc.scala 104:17] - node _T_1123 = or(io.lsu_pkt_r.bits.load, io.lsu_pkt_r.bits.store) @[lsu_ecc.scala 105:63] - node _T_1124 = and(io.lsu_pkt_r.valid, _T_1123) @[lsu_ecc.scala 105:37] - node _T_1125 = and(_T_1124, io.addr_in_dccm_r) @[lsu_ecc.scala 105:90] - node _T_1126 = and(_T_1125, io.lsu_dccm_rden_r) @[lsu_ecc.scala 105:110] - is_ldst_r <= _T_1126 @[lsu_ecc.scala 105:15] - node _T_1127 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 106:33] - node _T_1128 = and(is_ldst_r, _T_1127) @[lsu_ecc.scala 106:31] - is_ldst_lo_r <= _T_1128 @[lsu_ecc.scala 106:18] - node _T_1129 = or(ldst_dual_r, io.lsu_pkt_r.bits.dma) @[lsu_ecc.scala 107:46] - node _T_1130 = and(is_ldst_r, _T_1129) @[lsu_ecc.scala 107:31] - node _T_1131 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 107:73] - node _T_1132 = and(_T_1130, _T_1131) @[lsu_ecc.scala 107:71] - is_ldst_hi_r <= _T_1132 @[lsu_ecc.scala 107:18] - is_ldst_hi_any <= is_ldst_hi_r @[lsu_ecc.scala 108:21] - dccm_rdata_hi_any <= io.dccm_rdata_hi_r @[lsu_ecc.scala 109:24] - dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_r @[lsu_ecc.scala 110:26] - is_ldst_lo_any <= is_ldst_lo_r @[lsu_ecc.scala 111:20] - dccm_rdata_lo_any <= io.dccm_rdata_lo_r @[lsu_ecc.scala 112:25] - dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_r @[lsu_ecc.scala 113:26] - io.sec_data_hi_r <= sec_data_hi_any @[lsu_ecc.scala 114:22] - io.single_ecc_error_hi_r <= single_ecc_error_hi_any @[lsu_ecc.scala 115:31] - double_ecc_error_hi_r <= double_ecc_error_hi_any @[lsu_ecc.scala 116:28] - io.sec_data_lo_r <= sec_data_lo_any @[lsu_ecc.scala 117:25] - io.single_ecc_error_lo_r <= single_ecc_error_lo_any @[lsu_ecc.scala 118:31] - double_ecc_error_lo_r <= double_ecc_error_lo_any @[lsu_ecc.scala 119:28] - node _T_1133 = or(io.single_ecc_error_hi_r, io.single_ecc_error_lo_r) @[lsu_ecc.scala 120:59] - io.lsu_single_ecc_error_r <= _T_1133 @[lsu_ecc.scala 120:31] - node _T_1134 = or(double_ecc_error_hi_r, double_ecc_error_lo_r) @[lsu_ecc.scala 121:56] - io.lsu_double_ecc_error_r <= _T_1134 @[lsu_ecc.scala 121:31] - skip @[lsu_ecc.scala 103:30] - else : @[lsu_ecc.scala 123:16] - node _T_1135 = bits(io.lsu_addr_m, 2, 2) @[lsu_ecc.scala 124:35] - node _T_1136 = bits(io.end_addr_m, 2, 2) @[lsu_ecc.scala 124:56] - node _T_1137 = neq(_T_1135, _T_1136) @[lsu_ecc.scala 124:39] - ldst_dual_m <= _T_1137 @[lsu_ecc.scala 124:19] - node _T_1138 = or(io.lsu_pkt_m.bits.load, io.lsu_pkt_m.bits.store) @[lsu_ecc.scala 125:65] - node _T_1139 = and(io.lsu_pkt_m.valid, _T_1138) @[lsu_ecc.scala 125:39] - node _T_1140 = and(_T_1139, io.addr_in_dccm_m) @[lsu_ecc.scala 125:92] - node _T_1141 = and(_T_1140, io.lsu_dccm_rden_m) @[lsu_ecc.scala 125:112] - is_ldst_m <= _T_1141 @[lsu_ecc.scala 125:17] - node _T_1142 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 126:35] - node _T_1143 = and(is_ldst_m, _T_1142) @[lsu_ecc.scala 126:33] - is_ldst_lo_m <= _T_1143 @[lsu_ecc.scala 126:20] - node _T_1144 = or(ldst_dual_m, io.lsu_pkt_m.bits.dma) @[lsu_ecc.scala 127:48] - node _T_1145 = and(is_ldst_m, _T_1144) @[lsu_ecc.scala 127:33] - node _T_1146 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 127:75] - node _T_1147 = and(_T_1145, _T_1146) @[lsu_ecc.scala 127:73] - is_ldst_hi_m <= _T_1147 @[lsu_ecc.scala 127:20] - is_ldst_hi_any <= is_ldst_hi_m @[lsu_ecc.scala 128:23] - dccm_rdata_hi_any <= io.dccm_rdata_hi_m @[lsu_ecc.scala 129:26] - dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_m @[lsu_ecc.scala 130:28] - is_ldst_lo_any <= is_ldst_lo_m @[lsu_ecc.scala 131:22] - dccm_rdata_lo_any <= io.dccm_rdata_lo_m @[lsu_ecc.scala 132:27] - dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_m @[lsu_ecc.scala 133:28] - io.sec_data_hi_m <= sec_data_hi_any @[lsu_ecc.scala 134:27] - double_ecc_error_hi_m <= double_ecc_error_hi_any @[lsu_ecc.scala 135:30] - io.sec_data_lo_m <= sec_data_lo_any @[lsu_ecc.scala 136:27] - double_ecc_error_lo_m <= double_ecc_error_lo_any @[lsu_ecc.scala 137:30] - node _T_1148 = or(single_ecc_error_hi_any, single_ecc_error_lo_any) @[lsu_ecc.scala 138:60] - io.lsu_single_ecc_error_m <= _T_1148 @[lsu_ecc.scala 138:33] - node _T_1149 = or(double_ecc_error_hi_m, double_ecc_error_lo_m) @[lsu_ecc.scala 139:58] - io.lsu_double_ecc_error_m <= _T_1149 @[lsu_ecc.scala 139:33] - reg _T_1150 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 141:72] - _T_1150 <= io.lsu_single_ecc_error_m @[lsu_ecc.scala 141:72] - io.lsu_single_ecc_error_r <= _T_1150 @[lsu_ecc.scala 141:62] - reg _T_1151 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 142:72] - _T_1151 <= io.lsu_double_ecc_error_m @[lsu_ecc.scala 142:72] - io.lsu_double_ecc_error_r <= _T_1151 @[lsu_ecc.scala 142:62] - reg _T_1152 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 143:72] - _T_1152 <= single_ecc_error_lo_any @[lsu_ecc.scala 143:72] - io.single_ecc_error_lo_r <= _T_1152 @[lsu_ecc.scala 143:62] - reg _T_1153 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 144:72] - _T_1153 <= single_ecc_error_hi_any @[lsu_ecc.scala 144:72] - io.single_ecc_error_hi_r <= _T_1153 @[lsu_ecc.scala 144:62] - reg _T_1154 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 145:72] - _T_1154 <= io.sec_data_hi_m @[lsu_ecc.scala 145:72] - io.sec_data_hi_r <= _T_1154 @[lsu_ecc.scala 145:62] - reg _T_1155 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 146:72] - _T_1155 <= io.sec_data_lo_m @[lsu_ecc.scala 146:72] - io.sec_data_lo_r <= _T_1155 @[lsu_ecc.scala 146:62] - skip @[lsu_ecc.scala 123:16] - node _T_1156 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_ecc.scala 149:56] - node _T_1157 = bits(io.dma_dccm_wen, 0, 0) @[lsu_ecc.scala 149:104] - node _T_1158 = mux(_T_1157, io.dma_dccm_wdata_lo, io.stbuf_data_any) @[lsu_ecc.scala 149:87] - node _T_1159 = mux(_T_1156, io.sec_data_lo_r_ff, _T_1158) @[lsu_ecc.scala 149:27] - dccm_wdata_lo_any <= _T_1159 @[lsu_ecc.scala 149:21] - node _T_1160 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_ecc.scala 150:56] - node _T_1161 = bits(io.dma_dccm_wen, 0, 0) @[lsu_ecc.scala 150:104] - node _T_1162 = mux(_T_1161, io.dma_dccm_wdata_hi, io.stbuf_data_any) @[lsu_ecc.scala 150:87] - node _T_1163 = mux(_T_1160, io.sec_data_hi_r_ff, _T_1162) @[lsu_ecc.scala 150:27] - dccm_wdata_hi_any <= _T_1163 @[lsu_ecc.scala 150:21] - io.sec_data_ecc_hi_r_ff <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 151:28] - io.sec_data_ecc_lo_r_ff <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 152:28] - io.stbuf_ecc_any <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 153:28] - io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 154:28] - io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 155:28] + when UInt<1>("h00") : @[lsu_ecc.scala 101:30] + node _T_1120 = bits(io.lsu_addr_r, 2, 2) @[lsu_ecc.scala 102:33] + node _T_1121 = bits(io.end_addr_r, 2, 2) @[lsu_ecc.scala 102:54] + node _T_1122 = neq(_T_1120, _T_1121) @[lsu_ecc.scala 102:37] + ldst_dual_r <= _T_1122 @[lsu_ecc.scala 102:17] + node _T_1123 = or(io.lsu_pkt_r.bits.load, io.lsu_pkt_r.bits.store) @[lsu_ecc.scala 103:63] + node _T_1124 = and(io.lsu_pkt_r.valid, _T_1123) @[lsu_ecc.scala 103:37] + node _T_1125 = and(_T_1124, io.addr_in_dccm_r) @[lsu_ecc.scala 103:90] + node _T_1126 = and(_T_1125, io.lsu_dccm_rden_r) @[lsu_ecc.scala 103:110] + is_ldst_r <= _T_1126 @[lsu_ecc.scala 103:15] + node _T_1127 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 104:33] + node _T_1128 = and(is_ldst_r, _T_1127) @[lsu_ecc.scala 104:31] + is_ldst_lo_r <= _T_1128 @[lsu_ecc.scala 104:18] + node _T_1129 = or(ldst_dual_r, io.lsu_pkt_r.bits.dma) @[lsu_ecc.scala 105:46] + node _T_1130 = and(is_ldst_r, _T_1129) @[lsu_ecc.scala 105:31] + node _T_1131 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 105:73] + node _T_1132 = and(_T_1130, _T_1131) @[lsu_ecc.scala 105:71] + is_ldst_hi_r <= _T_1132 @[lsu_ecc.scala 105:18] + is_ldst_hi_any <= is_ldst_hi_r @[lsu_ecc.scala 106:21] + dccm_rdata_hi_any <= io.dccm_rdata_hi_r @[lsu_ecc.scala 107:24] + dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_r @[lsu_ecc.scala 108:26] + is_ldst_lo_any <= is_ldst_lo_r @[lsu_ecc.scala 109:20] + dccm_rdata_lo_any <= io.dccm_rdata_lo_r @[lsu_ecc.scala 110:25] + dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_r @[lsu_ecc.scala 111:26] + io.sec_data_hi_r <= sec_data_hi_any @[lsu_ecc.scala 112:22] + io.single_ecc_error_hi_r <= single_ecc_error_hi_any @[lsu_ecc.scala 113:31] + double_ecc_error_hi_r <= double_ecc_error_hi_any @[lsu_ecc.scala 114:28] + io.sec_data_lo_r <= sec_data_lo_any @[lsu_ecc.scala 115:25] + io.single_ecc_error_lo_r <= single_ecc_error_lo_any @[lsu_ecc.scala 116:31] + double_ecc_error_lo_r <= double_ecc_error_lo_any @[lsu_ecc.scala 117:28] + node _T_1133 = or(io.single_ecc_error_hi_r, io.single_ecc_error_lo_r) @[lsu_ecc.scala 118:59] + io.lsu_single_ecc_error_r <= _T_1133 @[lsu_ecc.scala 118:31] + node _T_1134 = or(double_ecc_error_hi_r, double_ecc_error_lo_r) @[lsu_ecc.scala 119:56] + io.lsu_double_ecc_error_r <= _T_1134 @[lsu_ecc.scala 119:31] + skip @[lsu_ecc.scala 101:30] + else : @[lsu_ecc.scala 121:16] + node _T_1135 = bits(io.lsu_addr_m, 2, 2) @[lsu_ecc.scala 122:35] + node _T_1136 = bits(io.end_addr_m, 2, 2) @[lsu_ecc.scala 122:56] + node _T_1137 = neq(_T_1135, _T_1136) @[lsu_ecc.scala 122:39] + ldst_dual_m <= _T_1137 @[lsu_ecc.scala 122:19] + node _T_1138 = or(io.lsu_pkt_m.bits.load, io.lsu_pkt_m.bits.store) @[lsu_ecc.scala 123:65] + node _T_1139 = and(io.lsu_pkt_m.valid, _T_1138) @[lsu_ecc.scala 123:39] + node _T_1140 = and(_T_1139, io.addr_in_dccm_m) @[lsu_ecc.scala 123:92] + node _T_1141 = and(_T_1140, io.lsu_dccm_rden_m) @[lsu_ecc.scala 123:112] + is_ldst_m <= _T_1141 @[lsu_ecc.scala 123:17] + node _T_1142 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 124:35] + node _T_1143 = and(is_ldst_m, _T_1142) @[lsu_ecc.scala 124:33] + is_ldst_lo_m <= _T_1143 @[lsu_ecc.scala 124:20] + node _T_1144 = or(ldst_dual_m, io.lsu_pkt_m.bits.dma) @[lsu_ecc.scala 125:48] + node _T_1145 = and(is_ldst_m, _T_1144) @[lsu_ecc.scala 125:33] + node _T_1146 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 125:75] + node _T_1147 = and(_T_1145, _T_1146) @[lsu_ecc.scala 125:73] + is_ldst_hi_m <= _T_1147 @[lsu_ecc.scala 125:20] + is_ldst_hi_any <= is_ldst_hi_m @[lsu_ecc.scala 126:23] + dccm_rdata_hi_any <= io.dccm_rdata_hi_m @[lsu_ecc.scala 127:26] + dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_m @[lsu_ecc.scala 128:28] + is_ldst_lo_any <= is_ldst_lo_m @[lsu_ecc.scala 129:22] + dccm_rdata_lo_any <= io.dccm_rdata_lo_m @[lsu_ecc.scala 130:27] + dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_m @[lsu_ecc.scala 131:28] + io.sec_data_hi_m <= sec_data_hi_any @[lsu_ecc.scala 132:27] + double_ecc_error_hi_m <= double_ecc_error_hi_any @[lsu_ecc.scala 133:30] + io.sec_data_lo_m <= sec_data_lo_any @[lsu_ecc.scala 134:27] + double_ecc_error_lo_m <= double_ecc_error_lo_any @[lsu_ecc.scala 135:30] + node _T_1148 = or(single_ecc_error_hi_any, single_ecc_error_lo_any) @[lsu_ecc.scala 136:60] + io.lsu_single_ecc_error_m <= _T_1148 @[lsu_ecc.scala 136:33] + node _T_1149 = or(double_ecc_error_hi_m, double_ecc_error_lo_m) @[lsu_ecc.scala 137:58] + io.lsu_double_ecc_error_m <= _T_1149 @[lsu_ecc.scala 137:33] + reg _T_1150 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 139:72] + _T_1150 <= io.lsu_single_ecc_error_m @[lsu_ecc.scala 139:72] + io.lsu_single_ecc_error_r <= _T_1150 @[lsu_ecc.scala 139:62] + reg _T_1151 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 140:72] + _T_1151 <= io.lsu_double_ecc_error_m @[lsu_ecc.scala 140:72] + io.lsu_double_ecc_error_r <= _T_1151 @[lsu_ecc.scala 140:62] + reg _T_1152 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 141:72] + _T_1152 <= single_ecc_error_lo_any @[lsu_ecc.scala 141:72] + io.single_ecc_error_lo_r <= _T_1152 @[lsu_ecc.scala 141:62] + reg _T_1153 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 142:72] + _T_1153 <= single_ecc_error_hi_any @[lsu_ecc.scala 142:72] + io.single_ecc_error_hi_r <= _T_1153 @[lsu_ecc.scala 142:62] + reg _T_1154 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 143:72] + _T_1154 <= io.sec_data_hi_m @[lsu_ecc.scala 143:72] + io.sec_data_hi_r <= _T_1154 @[lsu_ecc.scala 143:62] + reg _T_1155 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 144:72] + _T_1155 <= io.sec_data_lo_m @[lsu_ecc.scala 144:72] + io.sec_data_lo_r <= _T_1155 @[lsu_ecc.scala 144:62] + skip @[lsu_ecc.scala 121:16] + node _T_1156 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_ecc.scala 147:56] + node _T_1157 = bits(io.dma_dccm_wen, 0, 0) @[lsu_ecc.scala 147:104] + node _T_1158 = mux(_T_1157, io.dma_dccm_wdata_lo, io.stbuf_data_any) @[lsu_ecc.scala 147:87] + node _T_1159 = mux(_T_1156, io.sec_data_lo_r_ff, _T_1158) @[lsu_ecc.scala 147:27] + dccm_wdata_lo_any <= _T_1159 @[lsu_ecc.scala 147:21] + node _T_1160 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_ecc.scala 148:56] + node _T_1161 = bits(io.dma_dccm_wen, 0, 0) @[lsu_ecc.scala 148:104] + node _T_1162 = mux(_T_1161, io.dma_dccm_wdata_hi, io.stbuf_data_any) @[lsu_ecc.scala 148:87] + node _T_1163 = mux(_T_1160, io.sec_data_hi_r_ff, _T_1162) @[lsu_ecc.scala 148:27] + dccm_wdata_hi_any <= _T_1163 @[lsu_ecc.scala 148:21] + io.sec_data_ecc_hi_r_ff <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 149:28] + io.sec_data_ecc_lo_r_ff <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 150:28] + io.stbuf_ecc_any <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 151:28] + io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 152:28] + io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 153:28] inst rvclkhdr of rvclkhdr_800 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -92952,7 +92942,7 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_1164 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_1164 <= io.sec_data_hi_r @[lib.scala 374:16] - io.sec_data_hi_r_ff <= _T_1164 @[lsu_ecc.scala 157:23] + io.sec_data_hi_r_ff <= _T_1164 @[lsu_ecc.scala 155:23] inst rvclkhdr_1 of rvclkhdr_801 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -92961,7 +92951,7 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_1165 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_1165 <= io.sec_data_lo_r @[lib.scala 374:16] - io.sec_data_lo_r_ff <= _T_1165 @[lsu_ecc.scala 158:23] + io.sec_data_lo_r_ff <= _T_1165 @[lsu_ecc.scala 156:23] module lsu_trigger : input clock : Clock @@ -95896,7 +95886,7 @@ circuit quasar_wrapper : node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 175:32] node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 174:103] io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 171:24] - node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 177:77] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h01")) @[lsu_bus_buffer.scala 177:77] node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -109054,6 +109044,4831 @@ circuit quasar_wrapper : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_849 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_849 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_849 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_850 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_850 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_850 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_851 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_851 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_851 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_852 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_852 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_852 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_853 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_853 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_853 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_854 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_854 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_854 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_855 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_855 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_855 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_856 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_856 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_856 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_857 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_857 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_857 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_858 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_858 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_858 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module axi4_to_ahb : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] + wire buf_state : UInt<3> + buf_state <= UInt<3>("h00") + wire buf_nxtstate : UInt<3> + buf_nxtstate <= UInt<3>("h00") + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] + node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] + wire slave_valid : UInt<1> + slave_valid <= UInt<1>("h00") + wire slave_ready : UInt<1> + slave_ready <= UInt<1>("h00") + wire slave_tag : UInt<1> + slave_tag <= UInt<1>("h00") + wire slave_rdata : UInt<64> + slave_rdata <= UInt<64>("h00") + wire slave_opc : UInt<4> + slave_opc <= UInt<4>("h00") + wire wrbuf_en : UInt<1> + wrbuf_en <= UInt<1>("h00") + wire wrbuf_data_en : UInt<1> + wrbuf_data_en <= UInt<1>("h00") + wire wrbuf_cmd_sent : UInt<1> + wrbuf_cmd_sent <= UInt<1>("h00") + wire wrbuf_rst : UInt<1> + wrbuf_rst <= UInt<1>("h00") + wire wrbuf_vld : UInt<1> + wrbuf_vld <= UInt<1>("h00") + wire wrbuf_data_vld : UInt<1> + wrbuf_data_vld <= UInt<1>("h00") + wire wrbuf_tag : UInt<1> + wrbuf_tag <= UInt<1>("h00") + wire wrbuf_size : UInt<3> + wrbuf_size <= UInt<3>("h00") + wire wrbuf_addr : UInt<32> + wrbuf_addr <= UInt<32>("h00") + wire wrbuf_data : UInt<64> + wrbuf_data <= UInt<64>("h00") + wire wrbuf_byteen : UInt<8> + wrbuf_byteen <= UInt<8>("h00") + wire bus_write_clk_en : UInt<1> + bus_write_clk_en <= UInt<1>("h00") + wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] + wire master_valid : UInt<1> + master_valid <= UInt<1>("h00") + wire master_ready : UInt<1> + master_ready <= UInt<1>("h00") + wire master_tag : UInt<1> + master_tag <= UInt<1>("h00") + wire master_addr : UInt<32> + master_addr <= UInt<32>("h00") + wire master_wdata : UInt<64> + master_wdata <= UInt<64>("h00") + wire master_size : UInt<3> + master_size <= UInt<3>("h00") + wire master_opc : UInt<3> + master_opc <= UInt<3>("h00") + wire master_byteen : UInt<8> + master_byteen <= UInt<8>("h00") + wire buf_addr : UInt<32> + buf_addr <= UInt<32>("h00") + wire buf_size : UInt<2> + buf_size <= UInt<2>("h00") + wire buf_write : UInt<1> + buf_write <= UInt<1>("h00") + wire buf_byteen : UInt<8> + buf_byteen <= UInt<8>("h00") + wire buf_aligned : UInt<1> + buf_aligned <= UInt<1>("h00") + wire buf_data : UInt<64> + buf_data <= UInt<64>("h00") + wire buf_tag : UInt<1> + buf_tag <= UInt<1>("h00") + wire buf_tag_in : UInt<1> + buf_tag_in <= UInt<1>("h00") + wire buf_addr_in : UInt<32> + buf_addr_in <= UInt<32>("h00") + wire buf_byteen_in : UInt<8> + buf_byteen_in <= UInt<8>("h00") + wire buf_data_in : UInt<64> + buf_data_in <= UInt<64>("h00") + wire buf_write_in : UInt<1> + buf_write_in <= UInt<1>("h00") + wire buf_aligned_in : UInt<1> + buf_aligned_in <= UInt<1>("h00") + wire buf_size_in : UInt<3> + buf_size_in <= UInt<3>("h00") + wire buf_wr_en : UInt<1> + buf_wr_en <= UInt<1>("h00") + wire buf_data_wr_en : UInt<1> + buf_data_wr_en <= UInt<1>("h00") + wire slvbuf_error_en : UInt<1> + slvbuf_error_en <= UInt<1>("h00") + wire wr_cmd_vld : UInt<1> + wr_cmd_vld <= UInt<1>("h00") + wire cmd_done_rst : UInt<1> + cmd_done_rst <= UInt<1>("h00") + wire cmd_done : UInt<1> + cmd_done <= UInt<1>("h00") + wire cmd_doneQ : UInt<1> + cmd_doneQ <= UInt<1>("h00") + wire trxn_done : UInt<1> + trxn_done <= UInt<1>("h00") + wire buf_cmd_byte_ptr : UInt<3> + buf_cmd_byte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptrQ : UInt<3> + buf_cmd_byte_ptrQ <= UInt<3>("h00") + wire buf_cmd_nxtbyte_ptr : UInt<3> + buf_cmd_nxtbyte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptr_en : UInt<1> + buf_cmd_byte_ptr_en <= UInt<1>("h00") + wire found : UInt<1> + found <= UInt<1>("h00") + wire slave_valid_pre : UInt<1> + slave_valid_pre <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_hrdata_q : UInt<64> + ahb_hrdata_q <= UInt<64>("h00") + wire slvbuf_write : UInt<1> + slvbuf_write <= UInt<1>("h00") + wire slvbuf_error : UInt<1> + slvbuf_error <= UInt<1>("h00") + wire slvbuf_tag : UInt<1> + slvbuf_tag <= UInt<1>("h00") + wire slvbuf_error_in : UInt<1> + slvbuf_error_in <= UInt<1>("h00") + wire slvbuf_wr_en : UInt<1> + slvbuf_wr_en <= UInt<1>("h00") + wire bypass_en : UInt<1> + bypass_en <= UInt<1>("h00") + wire rd_bypass_idle : UInt<1> + rd_bypass_idle <= UInt<1>("h00") + wire last_addr_en : UInt<1> + last_addr_en <= UInt<1>("h00") + wire last_bus_addr : UInt<32> + last_bus_addr <= UInt<32>("h00") + wire buf_clken : UInt<1> + buf_clken <= UInt<1>("h00") + wire slvbuf_clken : UInt<1> + slvbuf_clken <= UInt<1>("h00") + wire ahbm_addr_clken : UInt<1> + ahbm_addr_clken <= UInt<1>("h00") + wire ahbm_data_clken : UInt<1> + ahbm_data_clken <= UInt<1>("h00") + wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 141:51] + node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 141:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] + master_size <= _T_22 @[axi4_to_ahb.scala 144:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 151:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 155:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] + inst rvclkhdr of rvclkhdr_849 @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] + inst rvclkhdr_1 of rvclkhdr_850 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] + node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_49 : @[Conditional.scala 40:58] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] + node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] + node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] + node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] + node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_101 : @[Conditional.scala 39:67] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] + node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] + node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_136 : @[Conditional.scala 39:67] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] + node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_175 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] + node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_188 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] + node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] + node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] + node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_281 : @[Conditional.scala 39:67] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] + node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] + node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] + node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] + node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] + node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] + node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] + node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] + node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] + node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] + node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_440 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] + skip @[Conditional.scala 39:67] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] + node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] + node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] + node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] + node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] + node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] + node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] + node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 266:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] + node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] + node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] + node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] + node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] + node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] + node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] + node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] + node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] + node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] + node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] + node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] + node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] + slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] + node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 287:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] + node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 303:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] + reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= _T_645 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] + reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_649 : @[Reg.scala 28:19] + _T_650 <= _T_648 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] + inst rvclkhdr_2 of rvclkhdr_851 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] + inst rvclkhdr_3 of rvclkhdr_852 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] + reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= _T_655 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] + reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= _T_658 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] + reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_661 : @[Reg.scala 28:19] + _T_662 <= buf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 310:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] + reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_664 : @[Reg.scala 28:19] + _T_665 <= _T_663 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] + inst rvclkhdr_4 of rvclkhdr_853 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_669 <= _T_666 @[lib.scala 374:16] + buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] + reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + _T_672 <= _T_670 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] + reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_673 : @[Reg.scala 28:19] + _T_674 <= buf_aligned_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] + reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= _T_675 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] + inst rvclkhdr_5 of rvclkhdr_854 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_681 <= _T_678 @[lib.scala 374:16] + buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= buf_write @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 317:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_685 : @[Reg.scala 28:19] + _T_686 <= _T_684 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] + reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_687 : @[Reg.scala 28:19] + _T_688 <= slvbuf_error_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] + reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_695 : @[Reg.scala 28:19] + _T_696 <= _T_694 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] + inst rvclkhdr_6 of rvclkhdr_855 @[lib.scala 343:22] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] + inst rvclkhdr_7 of rvclkhdr_856 @[lib.scala 343:22] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] + inst rvclkhdr_8 of rvclkhdr_857 @[lib.scala 343:22] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] + inst rvclkhdr_9 of rvclkhdr_858 @[lib.scala 343:22] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] + + extmodule gated_latch_859 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_859 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_859 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_860 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_860 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_860 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_861 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_861 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_861 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_862 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_862 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_862 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_863 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_863 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_863 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_864 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_864 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_864 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_865 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_865 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_865 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_866 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_866 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_866 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_867 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_867 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_867 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_868 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_868 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_868 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module axi4_to_ahb_1 : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] + wire buf_state : UInt<3> + buf_state <= UInt<3>("h00") + wire buf_nxtstate : UInt<3> + buf_nxtstate <= UInt<3>("h00") + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] + node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] + wire slave_valid : UInt<1> + slave_valid <= UInt<1>("h00") + wire slave_ready : UInt<1> + slave_ready <= UInt<1>("h00") + wire slave_tag : UInt<3> + slave_tag <= UInt<3>("h00") + wire slave_rdata : UInt<64> + slave_rdata <= UInt<64>("h00") + wire slave_opc : UInt<4> + slave_opc <= UInt<4>("h00") + wire wrbuf_en : UInt<1> + wrbuf_en <= UInt<1>("h00") + wire wrbuf_data_en : UInt<1> + wrbuf_data_en <= UInt<1>("h00") + wire wrbuf_cmd_sent : UInt<1> + wrbuf_cmd_sent <= UInt<1>("h00") + wire wrbuf_rst : UInt<1> + wrbuf_rst <= UInt<1>("h00") + wire wrbuf_vld : UInt<1> + wrbuf_vld <= UInt<1>("h00") + wire wrbuf_data_vld : UInt<1> + wrbuf_data_vld <= UInt<1>("h00") + wire wrbuf_tag : UInt<3> + wrbuf_tag <= UInt<3>("h00") + wire wrbuf_size : UInt<3> + wrbuf_size <= UInt<3>("h00") + wire wrbuf_addr : UInt<32> + wrbuf_addr <= UInt<32>("h00") + wire wrbuf_data : UInt<64> + wrbuf_data <= UInt<64>("h00") + wire wrbuf_byteen : UInt<8> + wrbuf_byteen <= UInt<8>("h00") + wire bus_write_clk_en : UInt<1> + bus_write_clk_en <= UInt<1>("h00") + wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] + wire master_valid : UInt<1> + master_valid <= UInt<1>("h00") + wire master_ready : UInt<1> + master_ready <= UInt<1>("h00") + wire master_tag : UInt<3> + master_tag <= UInt<3>("h00") + wire master_addr : UInt<32> + master_addr <= UInt<32>("h00") + wire master_wdata : UInt<64> + master_wdata <= UInt<64>("h00") + wire master_size : UInt<3> + master_size <= UInt<3>("h00") + wire master_opc : UInt<3> + master_opc <= UInt<3>("h00") + wire master_byteen : UInt<8> + master_byteen <= UInt<8>("h00") + wire buf_addr : UInt<32> + buf_addr <= UInt<32>("h00") + wire buf_size : UInt<2> + buf_size <= UInt<2>("h00") + wire buf_write : UInt<1> + buf_write <= UInt<1>("h00") + wire buf_byteen : UInt<8> + buf_byteen <= UInt<8>("h00") + wire buf_aligned : UInt<1> + buf_aligned <= UInt<1>("h00") + wire buf_data : UInt<64> + buf_data <= UInt<64>("h00") + wire buf_tag : UInt<3> + buf_tag <= UInt<3>("h00") + wire buf_tag_in : UInt<3> + buf_tag_in <= UInt<3>("h00") + wire buf_addr_in : UInt<32> + buf_addr_in <= UInt<32>("h00") + wire buf_byteen_in : UInt<8> + buf_byteen_in <= UInt<8>("h00") + wire buf_data_in : UInt<64> + buf_data_in <= UInt<64>("h00") + wire buf_write_in : UInt<1> + buf_write_in <= UInt<1>("h00") + wire buf_aligned_in : UInt<1> + buf_aligned_in <= UInt<1>("h00") + wire buf_size_in : UInt<3> + buf_size_in <= UInt<3>("h00") + wire buf_wr_en : UInt<1> + buf_wr_en <= UInt<1>("h00") + wire buf_data_wr_en : UInt<1> + buf_data_wr_en <= UInt<1>("h00") + wire slvbuf_error_en : UInt<1> + slvbuf_error_en <= UInt<1>("h00") + wire wr_cmd_vld : UInt<1> + wr_cmd_vld <= UInt<1>("h00") + wire cmd_done_rst : UInt<1> + cmd_done_rst <= UInt<1>("h00") + wire cmd_done : UInt<1> + cmd_done <= UInt<1>("h00") + wire cmd_doneQ : UInt<1> + cmd_doneQ <= UInt<1>("h00") + wire trxn_done : UInt<1> + trxn_done <= UInt<1>("h00") + wire buf_cmd_byte_ptr : UInt<3> + buf_cmd_byte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptrQ : UInt<3> + buf_cmd_byte_ptrQ <= UInt<3>("h00") + wire buf_cmd_nxtbyte_ptr : UInt<3> + buf_cmd_nxtbyte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptr_en : UInt<1> + buf_cmd_byte_ptr_en <= UInt<1>("h00") + wire found : UInt<1> + found <= UInt<1>("h00") + wire slave_valid_pre : UInt<1> + slave_valid_pre <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_hrdata_q : UInt<64> + ahb_hrdata_q <= UInt<64>("h00") + wire slvbuf_write : UInt<1> + slvbuf_write <= UInt<1>("h00") + wire slvbuf_error : UInt<1> + slvbuf_error <= UInt<1>("h00") + wire slvbuf_tag : UInt<3> + slvbuf_tag <= UInt<3>("h00") + wire slvbuf_error_in : UInt<1> + slvbuf_error_in <= UInt<1>("h00") + wire slvbuf_wr_en : UInt<1> + slvbuf_wr_en <= UInt<1>("h00") + wire bypass_en : UInt<1> + bypass_en <= UInt<1>("h00") + wire rd_bypass_idle : UInt<1> + rd_bypass_idle <= UInt<1>("h00") + wire last_addr_en : UInt<1> + last_addr_en <= UInt<1>("h00") + wire last_bus_addr : UInt<32> + last_bus_addr <= UInt<32>("h00") + wire buf_clken : UInt<1> + buf_clken <= UInt<1>("h00") + wire slvbuf_clken : UInt<1> + slvbuf_clken <= UInt<1>("h00") + wire ahbm_addr_clken : UInt<1> + ahbm_addr_clken <= UInt<1>("h00") + wire ahbm_data_clken : UInt<1> + ahbm_data_clken <= UInt<1>("h00") + wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] + node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] + node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] + master_size <= _T_22 @[axi4_to_ahb.scala 144:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] + node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] + node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] + inst rvclkhdr of rvclkhdr_859 @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] + inst rvclkhdr_1 of rvclkhdr_860 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] + node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_49 : @[Conditional.scala 40:58] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] + node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] + node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] + node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] + node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_101 : @[Conditional.scala 39:67] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] + node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] + node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_136 : @[Conditional.scala 39:67] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] + node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_175 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] + node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_188 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] + node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] + node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] + node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_281 : @[Conditional.scala 39:67] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] + node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] + node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] + node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] + node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] + node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] + node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] + node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] + node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] + node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] + node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_440 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] + skip @[Conditional.scala 39:67] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] + node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] + node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] + node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] + node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] + node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] + node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] + node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] + node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] + node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] + node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] + node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] + node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] + node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] + node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] + node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] + node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] + node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] + node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] + node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] + node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] + slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] + node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] + node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] + node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] + reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= _T_645 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] + reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_649 : @[Reg.scala 28:19] + _T_650 <= _T_648 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] + inst rvclkhdr_2 of rvclkhdr_861 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] + inst rvclkhdr_3 of rvclkhdr_862 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] + reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= _T_655 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] + reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= _T_658 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] + reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_661 : @[Reg.scala 28:19] + _T_662 <= buf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] + node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] + reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_664 : @[Reg.scala 28:19] + _T_665 <= _T_663 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] + inst rvclkhdr_4 of rvclkhdr_863 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_669 <= _T_666 @[lib.scala 374:16] + buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] + reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + _T_672 <= _T_670 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] + reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_673 : @[Reg.scala 28:19] + _T_674 <= buf_aligned_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] + reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= _T_675 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] + inst rvclkhdr_5 of rvclkhdr_864 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_681 <= _T_678 @[lib.scala 374:16] + buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= buf_write @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] + node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_685 : @[Reg.scala 28:19] + _T_686 <= _T_684 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] + reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_687 : @[Reg.scala 28:19] + _T_688 <= slvbuf_error_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] + reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_695 : @[Reg.scala 28:19] + _T_696 <= _T_694 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] + inst rvclkhdr_6 of rvclkhdr_865 @[lib.scala 343:22] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] + inst rvclkhdr_7 of rvclkhdr_866 @[lib.scala 343:22] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] + inst rvclkhdr_8 of rvclkhdr_867 @[lib.scala 343:22] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] + inst rvclkhdr_9 of rvclkhdr_868 @[lib.scala 343:22] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] + + extmodule gated_latch_869 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_869 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_869 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_870 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_870 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_870 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_871 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_871 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_871 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_872 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_872 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_872 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_873 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_873 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_873 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_874 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_874 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_874 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_875 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_875 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_875 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_876 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_876 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_876 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_877 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_877 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_877 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_878 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_878 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_878 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module axi4_to_ahb_2 : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] + wire buf_state : UInt<3> + buf_state <= UInt<3>("h00") + wire buf_nxtstate : UInt<3> + buf_nxtstate <= UInt<3>("h00") + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] + node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] + wire slave_valid : UInt<1> + slave_valid <= UInt<1>("h00") + wire slave_ready : UInt<1> + slave_ready <= UInt<1>("h00") + wire slave_tag : UInt<3> + slave_tag <= UInt<3>("h00") + wire slave_rdata : UInt<64> + slave_rdata <= UInt<64>("h00") + wire slave_opc : UInt<4> + slave_opc <= UInt<4>("h00") + wire wrbuf_en : UInt<1> + wrbuf_en <= UInt<1>("h00") + wire wrbuf_data_en : UInt<1> + wrbuf_data_en <= UInt<1>("h00") + wire wrbuf_cmd_sent : UInt<1> + wrbuf_cmd_sent <= UInt<1>("h00") + wire wrbuf_rst : UInt<1> + wrbuf_rst <= UInt<1>("h00") + wire wrbuf_vld : UInt<1> + wrbuf_vld <= UInt<1>("h00") + wire wrbuf_data_vld : UInt<1> + wrbuf_data_vld <= UInt<1>("h00") + wire wrbuf_tag : UInt<3> + wrbuf_tag <= UInt<3>("h00") + wire wrbuf_size : UInt<3> + wrbuf_size <= UInt<3>("h00") + wire wrbuf_addr : UInt<32> + wrbuf_addr <= UInt<32>("h00") + wire wrbuf_data : UInt<64> + wrbuf_data <= UInt<64>("h00") + wire wrbuf_byteen : UInt<8> + wrbuf_byteen <= UInt<8>("h00") + wire bus_write_clk_en : UInt<1> + bus_write_clk_en <= UInt<1>("h00") + wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] + wire master_valid : UInt<1> + master_valid <= UInt<1>("h00") + wire master_ready : UInt<1> + master_ready <= UInt<1>("h00") + wire master_tag : UInt<3> + master_tag <= UInt<3>("h00") + wire master_addr : UInt<32> + master_addr <= UInt<32>("h00") + wire master_wdata : UInt<64> + master_wdata <= UInt<64>("h00") + wire master_size : UInt<3> + master_size <= UInt<3>("h00") + wire master_opc : UInt<3> + master_opc <= UInt<3>("h00") + wire master_byteen : UInt<8> + master_byteen <= UInt<8>("h00") + wire buf_addr : UInt<32> + buf_addr <= UInt<32>("h00") + wire buf_size : UInt<2> + buf_size <= UInt<2>("h00") + wire buf_write : UInt<1> + buf_write <= UInt<1>("h00") + wire buf_byteen : UInt<8> + buf_byteen <= UInt<8>("h00") + wire buf_aligned : UInt<1> + buf_aligned <= UInt<1>("h00") + wire buf_data : UInt<64> + buf_data <= UInt<64>("h00") + wire buf_tag : UInt<3> + buf_tag <= UInt<3>("h00") + wire buf_tag_in : UInt<3> + buf_tag_in <= UInt<3>("h00") + wire buf_addr_in : UInt<32> + buf_addr_in <= UInt<32>("h00") + wire buf_byteen_in : UInt<8> + buf_byteen_in <= UInt<8>("h00") + wire buf_data_in : UInt<64> + buf_data_in <= UInt<64>("h00") + wire buf_write_in : UInt<1> + buf_write_in <= UInt<1>("h00") + wire buf_aligned_in : UInt<1> + buf_aligned_in <= UInt<1>("h00") + wire buf_size_in : UInt<3> + buf_size_in <= UInt<3>("h00") + wire buf_wr_en : UInt<1> + buf_wr_en <= UInt<1>("h00") + wire buf_data_wr_en : UInt<1> + buf_data_wr_en <= UInt<1>("h00") + wire slvbuf_error_en : UInt<1> + slvbuf_error_en <= UInt<1>("h00") + wire wr_cmd_vld : UInt<1> + wr_cmd_vld <= UInt<1>("h00") + wire cmd_done_rst : UInt<1> + cmd_done_rst <= UInt<1>("h00") + wire cmd_done : UInt<1> + cmd_done <= UInt<1>("h00") + wire cmd_doneQ : UInt<1> + cmd_doneQ <= UInt<1>("h00") + wire trxn_done : UInt<1> + trxn_done <= UInt<1>("h00") + wire buf_cmd_byte_ptr : UInt<3> + buf_cmd_byte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptrQ : UInt<3> + buf_cmd_byte_ptrQ <= UInt<3>("h00") + wire buf_cmd_nxtbyte_ptr : UInt<3> + buf_cmd_nxtbyte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptr_en : UInt<1> + buf_cmd_byte_ptr_en <= UInt<1>("h00") + wire found : UInt<1> + found <= UInt<1>("h00") + wire slave_valid_pre : UInt<1> + slave_valid_pre <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_hrdata_q : UInt<64> + ahb_hrdata_q <= UInt<64>("h00") + wire slvbuf_write : UInt<1> + slvbuf_write <= UInt<1>("h00") + wire slvbuf_error : UInt<1> + slvbuf_error <= UInt<1>("h00") + wire slvbuf_tag : UInt<3> + slvbuf_tag <= UInt<3>("h00") + wire slvbuf_error_in : UInt<1> + slvbuf_error_in <= UInt<1>("h00") + wire slvbuf_wr_en : UInt<1> + slvbuf_wr_en <= UInt<1>("h00") + wire bypass_en : UInt<1> + bypass_en <= UInt<1>("h00") + wire rd_bypass_idle : UInt<1> + rd_bypass_idle <= UInt<1>("h00") + wire last_addr_en : UInt<1> + last_addr_en <= UInt<1>("h00") + wire last_bus_addr : UInt<32> + last_bus_addr <= UInt<32>("h00") + wire buf_clken : UInt<1> + buf_clken <= UInt<1>("h00") + wire slvbuf_clken : UInt<1> + slvbuf_clken <= UInt<1>("h00") + wire ahbm_addr_clken : UInt<1> + ahbm_addr_clken <= UInt<1>("h00") + wire ahbm_data_clken : UInt<1> + ahbm_data_clken <= UInt<1>("h00") + wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] + node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] + node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] + master_size <= _T_22 @[axi4_to_ahb.scala 144:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] + node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] + node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] + inst rvclkhdr of rvclkhdr_869 @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] + inst rvclkhdr_1 of rvclkhdr_870 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] + node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_49 : @[Conditional.scala 40:58] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] + node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] + node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] + node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] + node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_101 : @[Conditional.scala 39:67] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] + node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] + node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_136 : @[Conditional.scala 39:67] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] + node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_175 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] + node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_188 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] + node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] + node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] + node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_281 : @[Conditional.scala 39:67] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] + node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] + node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] + node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] + node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] + node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] + node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] + node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] + node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] + node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] + node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_440 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] + skip @[Conditional.scala 39:67] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] + node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] + node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] + node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] + node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] + node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] + node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] + node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] + node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] + node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] + node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] + node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] + node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] + node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] + node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] + node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] + node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] + node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] + node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] + node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] + node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] + slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] + node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] + node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] + node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] + reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= _T_645 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] + reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_649 : @[Reg.scala 28:19] + _T_650 <= _T_648 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] + inst rvclkhdr_2 of rvclkhdr_871 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] + inst rvclkhdr_3 of rvclkhdr_872 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] + reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= _T_655 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] + reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= _T_658 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] + reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_661 : @[Reg.scala 28:19] + _T_662 <= buf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] + node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] + reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_664 : @[Reg.scala 28:19] + _T_665 <= _T_663 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] + inst rvclkhdr_4 of rvclkhdr_873 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_669 <= _T_666 @[lib.scala 374:16] + buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] + reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + _T_672 <= _T_670 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] + reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_673 : @[Reg.scala 28:19] + _T_674 <= buf_aligned_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] + reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= _T_675 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] + inst rvclkhdr_5 of rvclkhdr_874 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_681 <= _T_678 @[lib.scala 374:16] + buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= buf_write @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] + node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_685 : @[Reg.scala 28:19] + _T_686 <= _T_684 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] + reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_687 : @[Reg.scala 28:19] + _T_688 <= slvbuf_error_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] + reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_695 : @[Reg.scala 28:19] + _T_696 <= _T_694 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] + inst rvclkhdr_6 of rvclkhdr_875 @[lib.scala 343:22] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] + inst rvclkhdr_7 of rvclkhdr_876 @[lib.scala 343:22] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] + inst rvclkhdr_8 of rvclkhdr_877 @[lib.scala 343:22] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] + inst rvclkhdr_9 of rvclkhdr_878 @[lib.scala 343:22] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] + + extmodule gated_latch_879 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_879 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_879 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_880 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_880 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_880 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_881 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_881 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_881 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_882 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_882 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_882 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_883 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_883 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_883 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_884 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_884 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_884 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module ahb_to_axi4 : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}} + + wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25] + _T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10] + _T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10] + _T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10] + _T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10] + _T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10] + io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10] + io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10] + _T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10] + _T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10] + _T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10] + _T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10] + io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10] + io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10] + _T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10] + io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10] + _T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10] + wire master_wstrb : UInt<8> + master_wstrb <= UInt<8>("h00") + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire buf_read_error_in : UInt<1> + buf_read_error_in <= UInt<1>("h00") + wire buf_read_error : UInt<1> + buf_read_error <= UInt<1>("h00") + wire buf_rdata : UInt<64> + buf_rdata <= UInt<64>("h00") + wire ahb_hready : UInt<1> + ahb_hready <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_htrans_in : UInt<2> + ahb_htrans_in <= UInt<2>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hsize_q : UInt<3> + ahb_hsize_q <= UInt<3>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_haddr_q : UInt<32> + ahb_haddr_q <= UInt<32>("h00") + wire ahb_hwdata_q : UInt<64> + ahb_hwdata_q <= UInt<64>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire buf_rdata_en : UInt<1> + buf_rdata_en <= UInt<1>("h00") + wire ahb_bus_addr_clk_en : UInt<1> + ahb_bus_addr_clk_en <= UInt<1>("h00") + wire buf_rdata_clk_en : UInt<1> + buf_rdata_clk_en <= UInt<1>("h00") + wire ahb_clk : Clock @[ahb_to_axi4.scala 43:33] + wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 44:33] + wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 45:33] + wire cmdbuf_wr_en : UInt<1> + cmdbuf_wr_en <= UInt<1>("h00") + wire cmdbuf_rst : UInt<1> + cmdbuf_rst <= UInt<1>("h00") + wire cmdbuf_full : UInt<1> + cmdbuf_full <= UInt<1>("h00") + wire cmdbuf_vld : UInt<1> + cmdbuf_vld <= UInt<1>("h00") + wire cmdbuf_write : UInt<1> + cmdbuf_write <= UInt<1>("h00") + wire cmdbuf_size : UInt<2> + cmdbuf_size <= UInt<2>("h00") + wire cmdbuf_wstrb : UInt<8> + cmdbuf_wstrb <= UInt<8>("h00") + wire cmdbuf_addr : UInt<32> + cmdbuf_addr <= UInt<32>("h00") + wire cmdbuf_wdata : UInt<64> + cmdbuf_wdata <= UInt<64>("h00") + wire bus_clk : Clock @[ahb_to_axi4.scala 57:33] + node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] + node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47] + node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] + node ahb_addr_in_dccm = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 87:29] + node _T_3 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] + node ahb_addr_in_iccm_region_nc = eq(_T_3, UInt<4>("h0e")) @[lib.scala 84:47] + node _T_4 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] + node ahb_addr_in_iccm = eq(_T_4, UInt<16>("h0ee00")) @[lib.scala 87:29] + node _T_5 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] + node ahb_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 84:47] + node _T_6 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14] + node ahb_addr_in_pic = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 87:29] + wire buf_state : UInt<2> + buf_state <= UInt<2>("h00") + wire buf_nxtstate : UInt<2> + buf_nxtstate <= UInt<2>("h00") + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 67:31] + buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 68:31] + buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31] + buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31] + cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31] + node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_7 : @[Conditional.scala 40:58] + node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 75:26] + buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 75:20] + node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 76:57] + node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 76:34] + node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 76:61] + buf_state_en <= _T_11 @[ahb_to_axi4.scala 76:20] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_12 : @[Conditional.scala 39:67] + node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 79:72] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 79:79] + node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 79:48] + node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 79:93] + node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 79:91] + node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 79:107] + node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 79:124] + node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 79:26] + buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 79:20] + node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 80:24] + node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 80:37] + buf_state_en <= _T_22 @[ahb_to_axi4.scala 80:20] + node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 81:23] + node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 81:85] + node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 81:92] + node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 81:110] + node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 81:60] + node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 81:38] + node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 81:36] + cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 81:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_30 : @[Conditional.scala 39:67] + node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 84:26] + buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 84:20] + node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 85:24] + node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 85:37] + buf_state_en <= _T_33 @[ahb_to_axi4.scala 85:20] + node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 86:23] + node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 86:46] + node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 86:44] + cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 86:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_37 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 89:20] + node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 90:40] + node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 90:38] + buf_state_en <= _T_39 @[ahb_to_axi4.scala 90:20] + buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 91:20] + node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 92:61] + node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 92:68] + node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 92:41] + buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 92:25] + skip @[Conditional.scala 39:67] + node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 95:99] + reg _T_44 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_43 : @[Reg.scala 28:19] + _T_44 <= buf_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state <= _T_44 @[ahb_to_axi4.scala 95:31] + node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 97:54] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 97:60] + node _T_47 = bits(_T_46, 0, 0) @[Bitwise.scala 72:15] + node _T_48 = mux(_T_47, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 97:92] + node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 97:78] + node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 97:70] + node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:24] + node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 98:30] + node _T_54 = bits(_T_53, 0, 0) @[Bitwise.scala 72:15] + node _T_55 = mux(_T_54, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:62] + node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 98:48] + node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 98:40] + node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 97:109] + node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24] + node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 99:30] + node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] + node _T_63 = mux(_T_62, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:62] + node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 99:48] + node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 99:40] + node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 98:79] + node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24] + node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 100:30] + node _T_70 = bits(_T_69, 0, 0) @[Bitwise.scala 72:15] + node _T_71 = mux(_T_70, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 100:40] + node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 99:79] + master_wstrb <= _T_73 @[ahb_to_axi4.scala 97:31] + node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 103:80] + node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 103:78] + node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 103:98] + node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 103:124] + node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 103:111] + node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 103:149] + node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 103:168] + node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 103:156] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 103:137] + node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 103:135] + node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 103:181] + node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 103:179] + node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 103:44] + io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 103:38] + node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 104:55] + ahb_hready <= _T_87 @[ahb_to_axi4.scala 104:31] + node _T_88 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15] + node _T_89 = mux(_T_88, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 105:77] + node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 105:54] + ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 105:31] + node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 106:50] + io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 106:38] + node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 107:55] + node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 107:61] + node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 107:83] + node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 107:70] + node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 108:26] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 108:7] + node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 109:46] + node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 109:26] + node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 109:80] + node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 109:86] + node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 109:109] + node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 109:115] + node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 109:95] + node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 109:66] + node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 109:64] + node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 108:47] + node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 110:20] + node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 110:26] + node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 110:48] + node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 110:35] + node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 109:126] + node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20] + node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 111:26] + node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 111:49] + node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 111:56] + node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 111:35] + node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 110:55] + node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20] + node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 112:26] + node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 112:49] + node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 112:56] + node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 112:35] + node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 111:61] + node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 107:94] + node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 112:63] + node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 114:20] + node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 114:18] + node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 113:20] + io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 107:38] + reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 117:66] + _T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 117:66] + buf_rdata <= _T_131 @[ahb_to_axi4.scala 117:31] + reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 118:60] + _T_132 <= buf_read_error_in @[ahb_to_axi4.scala 118:60] + buf_read_error <= _T_132 @[ahb_to_axi4.scala 118:31] + reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 121:60] + _T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 121:60] + ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 121:31] + reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 122:60] + _T_134 <= ahb_hready @[ahb_to_axi4.scala 122:60] + ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 122:31] + reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60] + _T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 123:60] + ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 123:31] + reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:65] + _T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 124:65] + ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 124:31] + reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:65] + _T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 125:65] + ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 125:31] + reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65] + _T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 126:65] + ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 126:31] + node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 129:85] + node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 129:62] + node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 129:48] + ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 129:31] + node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 130:48] + buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 130:31] + inst rvclkhdr of rvclkhdr_879 @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 132:31] + inst rvclkhdr_1 of rvclkhdr_880 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 133:31] + inst rvclkhdr_2 of rvclkhdr_881 @[lib.scala 343:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 345:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 134:31] + node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 136:53] + node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 136:91] + node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 136:72] + node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 136:113] + node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 136:111] + node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 136:153] + node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 136:151] + node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 136:128] + cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 136:31] + node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 137:67] + node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 137:105] + node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 137:86] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 137:48] + node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 137:46] + cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 137:31] + node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 139:86] + node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 139:66] + node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 139:110] + node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 139:108] + reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 139:61] + _T_160 <= _T_159 @[ahb_to_axi4.scala 139:61] + cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 139:31] + node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 143:53] + reg _T_162 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_161 : @[Reg.scala 28:19] + _T_162 <= ahb_hwrite_q @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 142:31] + node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 146:52] + reg _T_164 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_163 : @[Reg.scala 28:19] + _T_164 <= ahb_hsize_q @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 145:31] + node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 149:53] + reg _T_166 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_165 : @[Reg.scala 28:19] + _T_166 <= master_wstrb @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 148:31] + node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 152:57] + inst rvclkhdr_3 of rvclkhdr_882 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_167 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_168 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_168 <= ahb_haddr_q @[lib.scala 374:16] + cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 152:15] + node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 153:68] + inst rvclkhdr_4 of rvclkhdr_883 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_169 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_170 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_170 <= io.ahb.sig.out.hwdata @[lib.scala 374:16] + cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 153:16] + node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 156:42] + io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 156:28] + io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 157:33] + io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 158:33] + node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 159:59] + node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58] + io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 159:33] + node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 160:33] + node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 161:33] + io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 162:33] + node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 164:42] + io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 164:28] + io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 165:33] + io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 166:33] + io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 167:33] + io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 169:28] + node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 171:44] + node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 171:42] + io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 171:28] + io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 172:33] + io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 173:33] + node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 174:59] + node _T_180 = cat(UInt<1>("h00"), _T_179) @[Cat.scala 29:58] + io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 174:33] + node _T_181 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 175:33] + node _T_182 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 176:33] + io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 177:33] + io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 179:28] + inst rvclkhdr_5 of rvclkhdr_884 @[lib.scala 343:22] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 180:27] + module quasar : input clock : Clock input reset : AsyncReset @@ -109553,263 +114368,554 @@ circuit quasar_wrapper : io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 238:11] io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 238:11] io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 238:11] - wire _T_12 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 277:42] - _T_12.out.hwdata <= UInt<64>("h00") @[quasar.scala 277:42] - _T_12.out.hwrite <= UInt<1>("h00") @[quasar.scala 277:42] - _T_12.out.htrans <= UInt<2>("h00") @[quasar.scala 277:42] - _T_12.out.hsize <= UInt<3>("h00") @[quasar.scala 277:42] - _T_12.out.hprot <= UInt<4>("h00") @[quasar.scala 277:42] - _T_12.out.hmastlock <= UInt<1>("h00") @[quasar.scala 277:42] - _T_12.out.hburst <= UInt<3>("h00") @[quasar.scala 277:42] - _T_12.out.haddr <= UInt<32>("h00") @[quasar.scala 277:42] - _T_12.in.hresp <= UInt<1>("h00") @[quasar.scala 277:42] - _T_12.in.hready <= UInt<1>("h00") @[quasar.scala 277:42] - _T_12.in.hrdata <= UInt<64>("h00") @[quasar.scala 277:42] - io.lsu_ahb.out.hwdata <= _T_12.out.hwdata @[quasar.scala 277:27] - io.lsu_ahb.out.hwrite <= _T_12.out.hwrite @[quasar.scala 277:27] - io.lsu_ahb.out.htrans <= _T_12.out.htrans @[quasar.scala 277:27] - io.lsu_ahb.out.hsize <= _T_12.out.hsize @[quasar.scala 277:27] - io.lsu_ahb.out.hprot <= _T_12.out.hprot @[quasar.scala 277:27] - io.lsu_ahb.out.hmastlock <= _T_12.out.hmastlock @[quasar.scala 277:27] - io.lsu_ahb.out.hburst <= _T_12.out.hburst @[quasar.scala 277:27] - io.lsu_ahb.out.haddr <= _T_12.out.haddr @[quasar.scala 277:27] - _T_12.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 277:27] - _T_12.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 277:27] - _T_12.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 277:27] - wire _T_13 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 278:42] - _T_13.out.hwdata <= UInt<64>("h00") @[quasar.scala 278:42] - _T_13.out.hwrite <= UInt<1>("h00") @[quasar.scala 278:42] - _T_13.out.htrans <= UInt<2>("h00") @[quasar.scala 278:42] - _T_13.out.hsize <= UInt<3>("h00") @[quasar.scala 278:42] - _T_13.out.hprot <= UInt<4>("h00") @[quasar.scala 278:42] - _T_13.out.hmastlock <= UInt<1>("h00") @[quasar.scala 278:42] - _T_13.out.hburst <= UInt<3>("h00") @[quasar.scala 278:42] - _T_13.out.haddr <= UInt<32>("h00") @[quasar.scala 278:42] - _T_13.in.hresp <= UInt<1>("h00") @[quasar.scala 278:42] - _T_13.in.hready <= UInt<1>("h00") @[quasar.scala 278:42] - _T_13.in.hrdata <= UInt<64>("h00") @[quasar.scala 278:42] - io.ifu_ahb.out.hwdata <= _T_13.out.hwdata @[quasar.scala 278:27] - io.ifu_ahb.out.hwrite <= _T_13.out.hwrite @[quasar.scala 278:27] - io.ifu_ahb.out.htrans <= _T_13.out.htrans @[quasar.scala 278:27] - io.ifu_ahb.out.hsize <= _T_13.out.hsize @[quasar.scala 278:27] - io.ifu_ahb.out.hprot <= _T_13.out.hprot @[quasar.scala 278:27] - io.ifu_ahb.out.hmastlock <= _T_13.out.hmastlock @[quasar.scala 278:27] - io.ifu_ahb.out.hburst <= _T_13.out.hburst @[quasar.scala 278:27] - io.ifu_ahb.out.haddr <= _T_13.out.haddr @[quasar.scala 278:27] - _T_13.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 278:27] - _T_13.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 278:27] - _T_13.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 278:27] - wire _T_14 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 279:42] - _T_14.out.hwdata <= UInt<64>("h00") @[quasar.scala 279:42] - _T_14.out.hwrite <= UInt<1>("h00") @[quasar.scala 279:42] - _T_14.out.htrans <= UInt<2>("h00") @[quasar.scala 279:42] - _T_14.out.hsize <= UInt<3>("h00") @[quasar.scala 279:42] - _T_14.out.hprot <= UInt<4>("h00") @[quasar.scala 279:42] - _T_14.out.hmastlock <= UInt<1>("h00") @[quasar.scala 279:42] - _T_14.out.hburst <= UInt<3>("h00") @[quasar.scala 279:42] - _T_14.out.haddr <= UInt<32>("h00") @[quasar.scala 279:42] - _T_14.in.hresp <= UInt<1>("h00") @[quasar.scala 279:42] - _T_14.in.hready <= UInt<1>("h00") @[quasar.scala 279:42] - _T_14.in.hrdata <= UInt<64>("h00") @[quasar.scala 279:42] - io.sb_ahb.out.hwdata <= _T_14.out.hwdata @[quasar.scala 279:27] - io.sb_ahb.out.hwrite <= _T_14.out.hwrite @[quasar.scala 279:27] - io.sb_ahb.out.htrans <= _T_14.out.htrans @[quasar.scala 279:27] - io.sb_ahb.out.hsize <= _T_14.out.hsize @[quasar.scala 279:27] - io.sb_ahb.out.hprot <= _T_14.out.hprot @[quasar.scala 279:27] - io.sb_ahb.out.hmastlock <= _T_14.out.hmastlock @[quasar.scala 279:27] - io.sb_ahb.out.hburst <= _T_14.out.hburst @[quasar.scala 279:27] - io.sb_ahb.out.haddr <= _T_14.out.haddr @[quasar.scala 279:27] - _T_14.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 279:27] - _T_14.in.hready <= io.sb_ahb.in.hready @[quasar.scala 279:27] - _T_14.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 279:27] - wire _T_15 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar.scala 280:42] - _T_15.hreadyin <= UInt<1>("h00") @[quasar.scala 280:42] - _T_15.hsel <= UInt<1>("h00") @[quasar.scala 280:42] - _T_15.sig.out.hwdata <= UInt<64>("h00") @[quasar.scala 280:42] - _T_15.sig.out.hwrite <= UInt<1>("h00") @[quasar.scala 280:42] - _T_15.sig.out.htrans <= UInt<2>("h00") @[quasar.scala 280:42] - _T_15.sig.out.hsize <= UInt<3>("h00") @[quasar.scala 280:42] - _T_15.sig.out.hprot <= UInt<4>("h00") @[quasar.scala 280:42] - _T_15.sig.out.hmastlock <= UInt<1>("h00") @[quasar.scala 280:42] - _T_15.sig.out.hburst <= UInt<3>("h00") @[quasar.scala 280:42] - _T_15.sig.out.haddr <= UInt<32>("h00") @[quasar.scala 280:42] - _T_15.sig.in.hresp <= UInt<1>("h00") @[quasar.scala 280:42] - _T_15.sig.in.hready <= UInt<1>("h00") @[quasar.scala 280:42] - _T_15.sig.in.hrdata <= UInt<64>("h00") @[quasar.scala 280:42] - _T_15.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 280:27] - _T_15.hsel <= io.dma_ahb.hsel @[quasar.scala 280:27] - _T_15.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 280:27] - _T_15.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 280:27] - _T_15.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 280:27] - _T_15.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 280:27] - _T_15.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 280:27] - _T_15.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 280:27] - _T_15.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 280:27] - _T_15.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 280:27] - io.dma_ahb.sig.in.hresp <= _T_15.sig.in.hresp @[quasar.scala 280:27] - io.dma_ahb.sig.in.hready <= _T_15.sig.in.hready @[quasar.scala 280:27] - io.dma_ahb.sig.in.hrdata <= _T_15.sig.in.hrdata @[quasar.scala 280:27] - io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 281:27] - io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 281:27] - io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 281:27] - io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 281:27] - io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 281:27] - io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 281:27] - io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 281:27] - io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 281:27] - io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 281:27] - io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 281:27] - dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 281:27] - io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 281:27] - dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 282:27] - dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 282:27] - dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 282:27] - dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 282:27] - dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 282:27] - io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 282:27] - io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 282:27] - io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 282:27] - io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 282:27] - io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 282:27] - io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 282:27] - io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 282:27] - io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 282:27] - io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 282:27] - io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 282:27] - io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 282:27] - io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 282:27] - dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 282:27] - dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 282:27] - dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 282:27] - dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 282:27] - io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 282:27] - io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 282:27] - io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 282:27] - io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 282:27] - io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 282:27] - dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 282:27] - io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 282:27] - io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 282:27] - io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 282:27] - io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 282:27] - io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 282:27] - io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 282:27] - io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 282:27] - io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 282:27] - io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 282:27] - io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 282:27] - io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 282:27] - dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 282:27] - ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 283:27] - ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 283:27] - ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 283:27] - ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 283:27] - ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 283:27] - io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 283:27] - io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 283:27] - io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 283:27] - io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 283:27] - io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 283:27] - io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 283:27] - io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 283:27] - io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 283:27] - io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 283:27] - io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 283:27] - io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 283:27] - io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 283:27] - ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 283:27] - ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 283:27] - ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 283:27] - ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 283:27] - io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 283:27] - io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 283:27] - io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 283:27] - io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 283:27] - io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 283:27] - ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 283:27] - io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 283:27] - io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 283:27] - io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 283:27] - io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 283:27] - io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 283:27] - io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 283:27] - io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 283:27] - io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 283:27] - io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 283:27] - io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 283:27] - io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 283:27] - ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 283:27] - lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 284:27] - lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 284:27] - lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 284:27] - lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 284:27] - lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 284:27] - io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 284:27] - io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 284:27] - io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 284:27] - io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 284:27] - io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 284:27] - io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 284:27] - io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 284:27] - io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 284:27] - io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 284:27] - io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 284:27] - io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 284:27] - io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 284:27] - lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 284:27] - lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 284:27] - lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 284:27] - lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 284:27] - io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 284:27] - io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 284:27] - io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 284:27] - io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 284:27] - io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 284:27] - lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 284:27] - io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 284:27] - io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 284:27] - io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 284:27] - io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 284:27] - io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 284:27] - io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 284:27] - io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 284:27] - io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 284:27] - io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 284:27] - io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 284:27] - io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 284:27] - lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 284:27] + inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 241:32] + axi4_to_ahb.clock <= clock + axi4_to_ahb.reset <= reset + inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 242:33] + axi4_to_ahb_1.clock <= clock + axi4_to_ahb_1.reset <= reset + inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 243:33] + axi4_to_ahb_2.clock <= clock + axi4_to_ahb_2.reset <= reset + inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 244:33] + ahb_to_axi4.clock <= clock + ahb_to_axi4.reset <= reset + axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 246:34] + axi4_to_ahb_2.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 247:35] + axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 248:37] + lsu.io.axi.r.bits.last <= axi4_to_ahb_2.io.axi.r.bits.last @[quasar.scala 249:28] + lsu.io.axi.r.bits.resp <= axi4_to_ahb_2.io.axi.r.bits.resp @[quasar.scala 249:28] + lsu.io.axi.r.bits.data <= axi4_to_ahb_2.io.axi.r.bits.data @[quasar.scala 249:28] + lsu.io.axi.r.bits.id <= axi4_to_ahb_2.io.axi.r.bits.id @[quasar.scala 249:28] + lsu.io.axi.r.valid <= axi4_to_ahb_2.io.axi.r.valid @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 249:28] + lsu.io.axi.ar.ready <= axi4_to_ahb_2.io.axi.ar.ready @[quasar.scala 249:28] + lsu.io.axi.b.bits.id <= axi4_to_ahb_2.io.axi.b.bits.id @[quasar.scala 249:28] + lsu.io.axi.b.bits.resp <= axi4_to_ahb_2.io.axi.b.bits.resp @[quasar.scala 249:28] + lsu.io.axi.b.valid <= axi4_to_ahb_2.io.axi.b.valid @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 249:28] + lsu.io.axi.w.ready <= axi4_to_ahb_2.io.axi.w.ready @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 249:28] + axi4_to_ahb_2.io.axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 249:28] + lsu.io.axi.aw.ready <= axi4_to_ahb_2.io.axi.aw.ready @[quasar.scala 249:28] + io.lsu_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 250:28] + io.lsu_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 250:28] + io.lsu_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 250:28] + io.lsu_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 250:28] + io.lsu_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 250:28] + io.lsu_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 250:28] + io.lsu_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 250:28] + io.lsu_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 250:28] + axi4_to_ahb_2.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 250:28] + axi4_to_ahb_2.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 250:28] + axi4_to_ahb_2.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 250:28] + axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 252:34] + axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 253:35] + axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 254:37] + ifu.io.ifu.r.bits.last <= axi4_to_ahb_1.io.axi.r.bits.last @[quasar.scala 255:28] + ifu.io.ifu.r.bits.resp <= axi4_to_ahb_1.io.axi.r.bits.resp @[quasar.scala 255:28] + ifu.io.ifu.r.bits.data <= axi4_to_ahb_1.io.axi.r.bits.data @[quasar.scala 255:28] + ifu.io.ifu.r.bits.id <= axi4_to_ahb_1.io.axi.r.bits.id @[quasar.scala 255:28] + ifu.io.ifu.r.valid <= axi4_to_ahb_1.io.axi.r.valid @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 255:28] + ifu.io.ifu.ar.ready <= axi4_to_ahb_1.io.axi.ar.ready @[quasar.scala 255:28] + ifu.io.ifu.b.bits.id <= axi4_to_ahb_1.io.axi.b.bits.id @[quasar.scala 255:28] + ifu.io.ifu.b.bits.resp <= axi4_to_ahb_1.io.axi.b.bits.resp @[quasar.scala 255:28] + ifu.io.ifu.b.valid <= axi4_to_ahb_1.io.axi.b.valid @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 255:28] + ifu.io.ifu.w.ready <= axi4_to_ahb_1.io.axi.w.ready @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 255:28] + axi4_to_ahb_1.io.axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 255:28] + ifu.io.ifu.aw.ready <= axi4_to_ahb_1.io.axi.aw.ready @[quasar.scala 255:28] + io.ifu_ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 256:28] + io.ifu_ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 256:28] + io.ifu_ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 256:28] + io.ifu_ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 256:28] + io.ifu_ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 256:28] + io.ifu_ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 256:28] + io.ifu_ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 256:28] + io.ifu_ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 256:28] + axi4_to_ahb_1.io.ahb.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 256:28] + axi4_to_ahb_1.io.ahb.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 256:28] + axi4_to_ahb_1.io.ahb.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 256:28] + axi4_to_ahb_1.io.axi.b.ready <= UInt<1>("h01") @[quasar.scala 257:36] + axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 259:33] + axi4_to_ahb.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 260:34] + axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 261:36] + dbg.io.sb_axi.r.bits.last <= axi4_to_ahb.io.axi.r.bits.last @[quasar.scala 262:27] + dbg.io.sb_axi.r.bits.resp <= axi4_to_ahb.io.axi.r.bits.resp @[quasar.scala 262:27] + dbg.io.sb_axi.r.bits.data <= axi4_to_ahb.io.axi.r.bits.data @[quasar.scala 262:27] + dbg.io.sb_axi.r.bits.id <= axi4_to_ahb.io.axi.r.bits.id @[quasar.scala 262:27] + dbg.io.sb_axi.r.valid <= axi4_to_ahb.io.axi.r.valid @[quasar.scala 262:27] + axi4_to_ahb.io.axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 262:27] + axi4_to_ahb.io.axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 262:27] + axi4_to_ahb.io.axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 262:27] + axi4_to_ahb.io.axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 262:27] + axi4_to_ahb.io.axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 262:27] + axi4_to_ahb.io.axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 262:27] + axi4_to_ahb.io.axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 262:27] + axi4_to_ahb.io.axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 262:27] + axi4_to_ahb.io.axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 262:27] + axi4_to_ahb.io.axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 262:27] + axi4_to_ahb.io.axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 262:27] + axi4_to_ahb.io.axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 262:27] + dbg.io.sb_axi.ar.ready <= axi4_to_ahb.io.axi.ar.ready @[quasar.scala 262:27] + dbg.io.sb_axi.b.bits.id <= axi4_to_ahb.io.axi.b.bits.id @[quasar.scala 262:27] + dbg.io.sb_axi.b.bits.resp <= axi4_to_ahb.io.axi.b.bits.resp @[quasar.scala 262:27] + dbg.io.sb_axi.b.valid <= axi4_to_ahb.io.axi.b.valid @[quasar.scala 262:27] + axi4_to_ahb.io.axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 262:27] + axi4_to_ahb.io.axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 262:27] + axi4_to_ahb.io.axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 262:27] + axi4_to_ahb.io.axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 262:27] + axi4_to_ahb.io.axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 262:27] + dbg.io.sb_axi.w.ready <= axi4_to_ahb.io.axi.w.ready @[quasar.scala 262:27] + axi4_to_ahb.io.axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 262:27] + axi4_to_ahb.io.axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 262:27] + axi4_to_ahb.io.axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 262:27] + axi4_to_ahb.io.axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 262:27] + axi4_to_ahb.io.axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 262:27] + axi4_to_ahb.io.axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 262:27] + axi4_to_ahb.io.axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 262:27] + axi4_to_ahb.io.axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 262:27] + axi4_to_ahb.io.axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 262:27] + axi4_to_ahb.io.axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 262:27] + axi4_to_ahb.io.axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 262:27] + dbg.io.sb_axi.aw.ready <= axi4_to_ahb.io.axi.aw.ready @[quasar.scala 262:27] + io.sb_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 263:27] + io.sb_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 263:27] + io.sb_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 263:27] + io.sb_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 263:27] + io.sb_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 263:27] + io.sb_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 263:27] + io.sb_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 263:27] + io.sb_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 263:27] + axi4_to_ahb.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 263:27] + axi4_to_ahb.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 263:27] + axi4_to_ahb.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 263:27] + ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 265:34] + ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 266:35] + ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 267:37] + ahb_to_axi4.io.axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 268:28] + ahb_to_axi4.io.axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 268:28] + ahb_to_axi4.io.axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 268:28] + ahb_to_axi4.io.axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 268:28] + ahb_to_axi4.io.axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.r.ready <= ahb_to_axi4.io.axi.r.ready @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.ar.bits.qos <= ahb_to_axi4.io.axi.ar.bits.qos @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.ar.bits.prot <= ahb_to_axi4.io.axi.ar.bits.prot @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.ar.bits.cache <= ahb_to_axi4.io.axi.ar.bits.cache @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.ar.bits.lock <= ahb_to_axi4.io.axi.ar.bits.lock @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.ar.bits.burst <= ahb_to_axi4.io.axi.ar.bits.burst @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.ar.bits.size <= ahb_to_axi4.io.axi.ar.bits.size @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.ar.bits.len <= ahb_to_axi4.io.axi.ar.bits.len @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.ar.bits.region <= ahb_to_axi4.io.axi.ar.bits.region @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.ar.bits.addr <= ahb_to_axi4.io.axi.ar.bits.addr @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.ar.bits.id <= ahb_to_axi4.io.axi.ar.bits.id @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.ar.valid <= ahb_to_axi4.io.axi.ar.valid @[quasar.scala 268:28] + ahb_to_axi4.io.axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 268:28] + ahb_to_axi4.io.axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 268:28] + ahb_to_axi4.io.axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 268:28] + ahb_to_axi4.io.axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.b.ready <= ahb_to_axi4.io.axi.b.ready @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.w.bits.last <= ahb_to_axi4.io.axi.w.bits.last @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.w.bits.strb <= ahb_to_axi4.io.axi.w.bits.strb @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.w.bits.data <= ahb_to_axi4.io.axi.w.bits.data @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.w.valid <= ahb_to_axi4.io.axi.w.valid @[quasar.scala 268:28] + ahb_to_axi4.io.axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.aw.bits.qos <= ahb_to_axi4.io.axi.aw.bits.qos @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.aw.bits.prot <= ahb_to_axi4.io.axi.aw.bits.prot @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.aw.bits.cache <= ahb_to_axi4.io.axi.aw.bits.cache @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.aw.bits.lock <= ahb_to_axi4.io.axi.aw.bits.lock @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.aw.bits.burst <= ahb_to_axi4.io.axi.aw.bits.burst @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.aw.bits.size <= ahb_to_axi4.io.axi.aw.bits.size @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.aw.bits.len <= ahb_to_axi4.io.axi.aw.bits.len @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.aw.bits.region <= ahb_to_axi4.io.axi.aw.bits.region @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.aw.bits.addr <= ahb_to_axi4.io.axi.aw.bits.addr @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.aw.bits.id <= ahb_to_axi4.io.axi.aw.bits.id @[quasar.scala 268:28] + dma_ctrl.io.dma_axi.aw.valid <= ahb_to_axi4.io.axi.aw.valid @[quasar.scala 268:28] + ahb_to_axi4.io.axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 268:28] + ahb_to_axi4.io.ahb.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 269:28] + ahb_to_axi4.io.ahb.hsel <= io.dma_ahb.hsel @[quasar.scala 269:28] + ahb_to_axi4.io.ahb.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 269:28] + ahb_to_axi4.io.ahb.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 269:28] + ahb_to_axi4.io.ahb.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 269:28] + ahb_to_axi4.io.ahb.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 269:28] + ahb_to_axi4.io.ahb.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 269:28] + ahb_to_axi4.io.ahb.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 269:28] + ahb_to_axi4.io.ahb.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 269:28] + ahb_to_axi4.io.ahb.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 269:28] + io.dma_ahb.sig.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 269:28] + io.dma_ahb.sig.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 269:28] + io.dma_ahb.sig.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 269:28] + wire _T_12 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 271:36] + _T_12.r.bits.last <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.r.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36] + _T_12.r.bits.data <= UInt<64>("h00") @[quasar.scala 271:36] + _T_12.r.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.r.valid <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.r.ready <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36] + _T_12.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36] + _T_12.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36] + _T_12.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36] + _T_12.ar.bits.size <= UInt<3>("h00") @[quasar.scala 271:36] + _T_12.ar.bits.len <= UInt<8>("h00") @[quasar.scala 271:36] + _T_12.ar.bits.region <= UInt<4>("h00") @[quasar.scala 271:36] + _T_12.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36] + _T_12.ar.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.ar.valid <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.ar.ready <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.b.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.b.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36] + _T_12.b.valid <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.b.ready <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.w.bits.last <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.w.bits.strb <= UInt<8>("h00") @[quasar.scala 271:36] + _T_12.w.bits.data <= UInt<64>("h00") @[quasar.scala 271:36] + _T_12.w.valid <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.w.ready <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36] + _T_12.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36] + _T_12.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36] + _T_12.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36] + _T_12.aw.bits.size <= UInt<3>("h00") @[quasar.scala 271:36] + _T_12.aw.bits.len <= UInt<8>("h00") @[quasar.scala 271:36] + _T_12.aw.bits.region <= UInt<4>("h00") @[quasar.scala 271:36] + _T_12.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36] + _T_12.aw.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.aw.valid <= UInt<1>("h00") @[quasar.scala 271:36] + _T_12.aw.ready <= UInt<1>("h00") @[quasar.scala 271:36] + io.dma_axi.r.bits.last <= _T_12.r.bits.last @[quasar.scala 271:21] + io.dma_axi.r.bits.resp <= _T_12.r.bits.resp @[quasar.scala 271:21] + io.dma_axi.r.bits.data <= _T_12.r.bits.data @[quasar.scala 271:21] + io.dma_axi.r.bits.id <= _T_12.r.bits.id @[quasar.scala 271:21] + io.dma_axi.r.valid <= _T_12.r.valid @[quasar.scala 271:21] + _T_12.r.ready <= io.dma_axi.r.ready @[quasar.scala 271:21] + _T_12.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 271:21] + _T_12.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 271:21] + _T_12.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 271:21] + _T_12.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 271:21] + _T_12.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 271:21] + _T_12.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 271:21] + _T_12.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 271:21] + _T_12.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 271:21] + _T_12.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 271:21] + _T_12.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 271:21] + _T_12.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 271:21] + io.dma_axi.ar.ready <= _T_12.ar.ready @[quasar.scala 271:21] + io.dma_axi.b.bits.id <= _T_12.b.bits.id @[quasar.scala 271:21] + io.dma_axi.b.bits.resp <= _T_12.b.bits.resp @[quasar.scala 271:21] + io.dma_axi.b.valid <= _T_12.b.valid @[quasar.scala 271:21] + _T_12.b.ready <= io.dma_axi.b.ready @[quasar.scala 271:21] + _T_12.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 271:21] + _T_12.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 271:21] + _T_12.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 271:21] + _T_12.w.valid <= io.dma_axi.w.valid @[quasar.scala 271:21] + io.dma_axi.w.ready <= _T_12.w.ready @[quasar.scala 271:21] + _T_12.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 271:21] + _T_12.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 271:21] + _T_12.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 271:21] + _T_12.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 271:21] + _T_12.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 271:21] + _T_12.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 271:21] + _T_12.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 271:21] + _T_12.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 271:21] + _T_12.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 271:21] + _T_12.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 271:21] + _T_12.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 271:21] + io.dma_axi.aw.ready <= _T_12.aw.ready @[quasar.scala 271:21] + wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 272:36] + _T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36] + _T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 272:36] + _T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.r.valid <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.r.ready <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36] + _T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36] + _T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36] + _T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36] + _T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 272:36] + _T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 272:36] + _T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 272:36] + _T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36] + _T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36] + _T_13.b.valid <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.b.ready <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 272:36] + _T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 272:36] + _T_13.w.valid <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.w.ready <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36] + _T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36] + _T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36] + _T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36] + _T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 272:36] + _T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 272:36] + _T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 272:36] + _T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36] + _T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 272:36] + _T_13.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 272:21] + _T_13.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 272:21] + _T_13.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 272:21] + _T_13.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 272:21] + _T_13.r.valid <= io.sb_axi.r.valid @[quasar.scala 272:21] + io.sb_axi.r.ready <= _T_13.r.ready @[quasar.scala 272:21] + io.sb_axi.ar.bits.qos <= _T_13.ar.bits.qos @[quasar.scala 272:21] + io.sb_axi.ar.bits.prot <= _T_13.ar.bits.prot @[quasar.scala 272:21] + io.sb_axi.ar.bits.cache <= _T_13.ar.bits.cache @[quasar.scala 272:21] + io.sb_axi.ar.bits.lock <= _T_13.ar.bits.lock @[quasar.scala 272:21] + io.sb_axi.ar.bits.burst <= _T_13.ar.bits.burst @[quasar.scala 272:21] + io.sb_axi.ar.bits.size <= _T_13.ar.bits.size @[quasar.scala 272:21] + io.sb_axi.ar.bits.len <= _T_13.ar.bits.len @[quasar.scala 272:21] + io.sb_axi.ar.bits.region <= _T_13.ar.bits.region @[quasar.scala 272:21] + io.sb_axi.ar.bits.addr <= _T_13.ar.bits.addr @[quasar.scala 272:21] + io.sb_axi.ar.bits.id <= _T_13.ar.bits.id @[quasar.scala 272:21] + io.sb_axi.ar.valid <= _T_13.ar.valid @[quasar.scala 272:21] + _T_13.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 272:21] + _T_13.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 272:21] + _T_13.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 272:21] + _T_13.b.valid <= io.sb_axi.b.valid @[quasar.scala 272:21] + io.sb_axi.b.ready <= _T_13.b.ready @[quasar.scala 272:21] + io.sb_axi.w.bits.last <= _T_13.w.bits.last @[quasar.scala 272:21] + io.sb_axi.w.bits.strb <= _T_13.w.bits.strb @[quasar.scala 272:21] + io.sb_axi.w.bits.data <= _T_13.w.bits.data @[quasar.scala 272:21] + io.sb_axi.w.valid <= _T_13.w.valid @[quasar.scala 272:21] + _T_13.w.ready <= io.sb_axi.w.ready @[quasar.scala 272:21] + io.sb_axi.aw.bits.qos <= _T_13.aw.bits.qos @[quasar.scala 272:21] + io.sb_axi.aw.bits.prot <= _T_13.aw.bits.prot @[quasar.scala 272:21] + io.sb_axi.aw.bits.cache <= _T_13.aw.bits.cache @[quasar.scala 272:21] + io.sb_axi.aw.bits.lock <= _T_13.aw.bits.lock @[quasar.scala 272:21] + io.sb_axi.aw.bits.burst <= _T_13.aw.bits.burst @[quasar.scala 272:21] + io.sb_axi.aw.bits.size <= _T_13.aw.bits.size @[quasar.scala 272:21] + io.sb_axi.aw.bits.len <= _T_13.aw.bits.len @[quasar.scala 272:21] + io.sb_axi.aw.bits.region <= _T_13.aw.bits.region @[quasar.scala 272:21] + io.sb_axi.aw.bits.addr <= _T_13.aw.bits.addr @[quasar.scala 272:21] + io.sb_axi.aw.bits.id <= _T_13.aw.bits.id @[quasar.scala 272:21] + io.sb_axi.aw.valid <= _T_13.aw.valid @[quasar.scala 272:21] + _T_13.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 272:21] + wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 273:36] + _T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] + _T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] + _T_14.r.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] + _T_14.r.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.r.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] + _T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] + _T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] + _T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] + _T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] + _T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] + _T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] + _T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] + _T_14.ar.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] + _T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.b.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] + _T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] + _T_14.b.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.b.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 273:36] + _T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] + _T_14.w.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.w.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] + _T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] + _T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] + _T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] + _T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] + _T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] + _T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] + _T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] + _T_14.aw.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] + _T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_14.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 273:21] + _T_14.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 273:21] + _T_14.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 273:21] + _T_14.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 273:21] + _T_14.r.valid <= io.ifu_axi.r.valid @[quasar.scala 273:21] + io.ifu_axi.r.ready <= _T_14.r.ready @[quasar.scala 273:21] + io.ifu_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 273:21] + io.ifu_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 273:21] + io.ifu_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 273:21] + io.ifu_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 273:21] + io.ifu_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 273:21] + io.ifu_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 273:21] + io.ifu_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 273:21] + io.ifu_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 273:21] + io.ifu_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 273:21] + io.ifu_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 273:21] + io.ifu_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 273:21] + _T_14.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 273:21] + _T_14.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 273:21] + _T_14.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 273:21] + _T_14.b.valid <= io.ifu_axi.b.valid @[quasar.scala 273:21] + io.ifu_axi.b.ready <= _T_14.b.ready @[quasar.scala 273:21] + io.ifu_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 273:21] + io.ifu_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 273:21] + io.ifu_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 273:21] + io.ifu_axi.w.valid <= _T_14.w.valid @[quasar.scala 273:21] + _T_14.w.ready <= io.ifu_axi.w.ready @[quasar.scala 273:21] + io.ifu_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 273:21] + io.ifu_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 273:21] + io.ifu_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 273:21] + io.ifu_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 273:21] + io.ifu_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 273:21] + io.ifu_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 273:21] + io.ifu_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 273:21] + io.ifu_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 273:21] + io.ifu_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 273:21] + io.ifu_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 273:21] + io.ifu_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 273:21] + _T_14.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 273:21] + wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 274:36] + _T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36] + _T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 274:36] + _T_15.r.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] + _T_15.r.valid <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.r.ready <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36] + _T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36] + _T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36] + _T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36] + _T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 274:36] + _T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 274:36] + _T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 274:36] + _T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36] + _T_15.ar.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] + _T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.b.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] + _T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36] + _T_15.b.valid <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.b.ready <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 274:36] + _T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 274:36] + _T_15.w.valid <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.w.ready <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36] + _T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36] + _T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36] + _T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36] + _T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 274:36] + _T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 274:36] + _T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 274:36] + _T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36] + _T_15.aw.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] + _T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 274:36] + _T_15.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 274:21] + _T_15.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 274:21] + _T_15.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 274:21] + _T_15.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 274:21] + _T_15.r.valid <= io.lsu_axi.r.valid @[quasar.scala 274:21] + io.lsu_axi.r.ready <= _T_15.r.ready @[quasar.scala 274:21] + io.lsu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 274:21] + io.lsu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 274:21] + io.lsu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 274:21] + io.lsu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 274:21] + io.lsu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 274:21] + io.lsu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 274:21] + io.lsu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 274:21] + io.lsu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 274:21] + io.lsu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 274:21] + io.lsu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 274:21] + io.lsu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 274:21] + _T_15.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 274:21] + _T_15.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 274:21] + _T_15.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 274:21] + _T_15.b.valid <= io.lsu_axi.b.valid @[quasar.scala 274:21] + io.lsu_axi.b.ready <= _T_15.b.ready @[quasar.scala 274:21] + io.lsu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 274:21] + io.lsu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 274:21] + io.lsu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 274:21] + io.lsu_axi.w.valid <= _T_15.w.valid @[quasar.scala 274:21] + _T_15.w.ready <= io.lsu_axi.w.ready @[quasar.scala 274:21] + io.lsu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 274:21] + io.lsu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 274:21] + io.lsu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 274:21] + io.lsu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 274:21] + io.lsu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 274:21] + io.lsu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 274:21] + io.lsu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 274:21] + io.lsu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 274:21] + io.lsu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 274:21] + io.lsu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 274:21] + io.lsu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 274:21] + _T_15.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 274:21] module quasar_wrapper : input clock : Clock input reset : AsyncReset - output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} + output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, ifu_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, dma_brg : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} inst mem of mem @[quasar_wrapper.scala 63:19] mem.scan_mode is invalid @@ -109848,345 +114954,455 @@ circuit quasar_wrapper : dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 71:27] dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 72:26] dmi_wrapper.rd_data <= core.io.dmi_reg_rdata @[quasar_wrapper.scala 73:26] - dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 76:29] - core.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 77:25] - core.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 78:24] - core.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 79:22] - core.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 80:25] - core.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 81:26] - io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 82:15] - mem.dccm_clk_override <= core.io.dccm_clk_override @[quasar_wrapper.scala 85:28] - mem.icm_clk_override <= core.io.icm_clk_override @[quasar_wrapper.scala 86:27] - mem.dec_tlu_core_ecc_disable <= core.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 87:35] - core.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 88:15] - core.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 88:15] - mem.dccm.wr_data_hi <= core.io.dccm.wr_data_hi @[quasar_wrapper.scala 88:15] - mem.dccm.wr_data_lo <= core.io.dccm.wr_data_lo @[quasar_wrapper.scala 88:15] - mem.dccm.rd_addr_hi <= core.io.dccm.rd_addr_hi @[quasar_wrapper.scala 88:15] - mem.dccm.rd_addr_lo <= core.io.dccm.rd_addr_lo @[quasar_wrapper.scala 88:15] - mem.dccm.wr_addr_hi <= core.io.dccm.wr_addr_hi @[quasar_wrapper.scala 88:15] - mem.dccm.wr_addr_lo <= core.io.dccm.wr_addr_lo @[quasar_wrapper.scala 88:15] - mem.dccm.rden <= core.io.dccm.rden @[quasar_wrapper.scala 88:15] - mem.dccm.wren <= core.io.dccm.wren @[quasar_wrapper.scala 88:15] - mem.rst_l <= reset @[quasar_wrapper.scala 89:16] - mem.clk <= clock @[quasar_wrapper.scala 90:14] - mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 91:20] - core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 93:21] - mem.ic.sel_premux_data <= core.io.ic.sel_premux_data @[quasar_wrapper.scala 94:14] - mem.ic.premux_data <= core.io.ic.premux_data @[quasar_wrapper.scala 94:14] - mem.ic.debug_way <= core.io.ic.debug_way @[quasar_wrapper.scala 94:14] - mem.ic.debug_tag_array <= core.io.ic.debug_tag_array @[quasar_wrapper.scala 94:14] - mem.ic.debug_wr_en <= core.io.ic.debug_wr_en @[quasar_wrapper.scala 94:14] - mem.ic.debug_rd_en <= core.io.ic.debug_rd_en @[quasar_wrapper.scala 94:14] - core.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 94:14] - core.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 94:14] - core.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 94:14] - core.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 94:14] - core.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 94:14] - core.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 94:14] - core.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 94:14] - mem.ic.debug_addr <= core.io.ic.debug_addr @[quasar_wrapper.scala 94:14] - mem.ic.debug_wr_data <= core.io.ic.debug_wr_data @[quasar_wrapper.scala 94:14] - mem.ic.wr_data[0] <= core.io.ic.wr_data[0] @[quasar_wrapper.scala 94:14] - mem.ic.wr_data[1] <= core.io.ic.wr_data[1] @[quasar_wrapper.scala 94:14] - mem.ic.rd_en <= core.io.ic.rd_en @[quasar_wrapper.scala 94:14] - mem.ic.wr_en <= core.io.ic.wr_en @[quasar_wrapper.scala 94:14] - mem.ic.tag_valid <= core.io.ic.tag_valid @[quasar_wrapper.scala 94:14] - mem.ic.rw_addr <= core.io.ic.rw_addr @[quasar_wrapper.scala 94:14] - core.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 95:16] - core.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 95:16] - mem.iccm.wr_data <= core.io.iccm.wr_data @[quasar_wrapper.scala 95:16] - mem.iccm.wr_size <= core.io.iccm.wr_size @[quasar_wrapper.scala 95:16] - mem.iccm.rden <= core.io.iccm.rden @[quasar_wrapper.scala 95:16] - mem.iccm.wren <= core.io.iccm.wren @[quasar_wrapper.scala 95:16] - mem.iccm.correction_state <= core.io.iccm.correction_state @[quasar_wrapper.scala 95:16] - mem.iccm.buf_correct_ecc <= core.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 95:16] - mem.iccm.rw_addr <= core.io.iccm.rw_addr @[quasar_wrapper.scala 95:16] - wire _T : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 99:36] - _T.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] - _T.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 99:36] - _T.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 99:36] - _T.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] - _T.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] - _T.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hwdata <= core.io.ifu_ahb.out.hwdata @[quasar_wrapper.scala 99:21] - _T.out.hwrite <= core.io.ifu_ahb.out.hwrite @[quasar_wrapper.scala 99:21] - _T.out.htrans <= core.io.ifu_ahb.out.htrans @[quasar_wrapper.scala 99:21] - _T.out.hsize <= core.io.ifu_ahb.out.hsize @[quasar_wrapper.scala 99:21] - _T.out.hprot <= core.io.ifu_ahb.out.hprot @[quasar_wrapper.scala 99:21] - _T.out.hmastlock <= core.io.ifu_ahb.out.hmastlock @[quasar_wrapper.scala 99:21] - _T.out.hburst <= core.io.ifu_ahb.out.hburst @[quasar_wrapper.scala 99:21] - _T.out.haddr <= core.io.ifu_ahb.out.haddr @[quasar_wrapper.scala 99:21] - core.io.ifu_ahb.in.hresp <= _T.in.hresp @[quasar_wrapper.scala 99:21] - core.io.ifu_ahb.in.hready <= _T.in.hready @[quasar_wrapper.scala 99:21] - core.io.ifu_ahb.in.hrdata <= _T.in.hrdata @[quasar_wrapper.scala 99:21] - wire _T_1 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 100:36] - _T_1.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 100:36] - _T_1.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] - _T_1.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] - _T_1.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hwdata <= core.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 100:21] - _T_1.out.hwrite <= core.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 100:21] - _T_1.out.htrans <= core.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 100:21] - _T_1.out.hsize <= core.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 100:21] - _T_1.out.hprot <= core.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 100:21] - _T_1.out.hmastlock <= core.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 100:21] - _T_1.out.hburst <= core.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 100:21] - _T_1.out.haddr <= core.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 100:21] - core.io.lsu_ahb.in.hresp <= _T_1.in.hresp @[quasar_wrapper.scala 100:21] - core.io.lsu_ahb.in.hready <= _T_1.in.hready @[quasar_wrapper.scala 100:21] - core.io.lsu_ahb.in.hrdata <= _T_1.in.hrdata @[quasar_wrapper.scala 100:21] - wire _T_2 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 101:36] - _T_2.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 101:36] - _T_2.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] - _T_2.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] - _T_2.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hwdata <= core.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 101:21] - _T_2.out.hwrite <= core.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 101:21] - _T_2.out.htrans <= core.io.sb_ahb.out.htrans @[quasar_wrapper.scala 101:21] - _T_2.out.hsize <= core.io.sb_ahb.out.hsize @[quasar_wrapper.scala 101:21] - _T_2.out.hprot <= core.io.sb_ahb.out.hprot @[quasar_wrapper.scala 101:21] - _T_2.out.hmastlock <= core.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 101:21] - _T_2.out.hburst <= core.io.sb_ahb.out.hburst @[quasar_wrapper.scala 101:21] - _T_2.out.haddr <= core.io.sb_ahb.out.haddr @[quasar_wrapper.scala 101:21] - core.io.sb_ahb.in.hresp <= _T_2.in.hresp @[quasar_wrapper.scala 101:21] - core.io.sb_ahb.in.hready <= _T_2.in.hready @[quasar_wrapper.scala 101:21] - core.io.sb_ahb.in.hrdata <= _T_2.in.hrdata @[quasar_wrapper.scala 101:21] - wire _T_3 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar_wrapper.scala 102:36] - _T_3.hreadyin <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.hsel <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 102:36] - core.io.dma_ahb.hreadyin <= _T_3.hreadyin @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.hsel <= _T_3.hsel @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hwdata <= _T_3.sig.out.hwdata @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hwrite <= _T_3.sig.out.hwrite @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.htrans <= _T_3.sig.out.htrans @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hsize <= _T_3.sig.out.hsize @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hprot <= _T_3.sig.out.hprot @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hmastlock <= _T_3.sig.out.hmastlock @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hburst <= _T_3.sig.out.hburst @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.haddr <= _T_3.sig.out.haddr @[quasar_wrapper.scala 102:21] - _T_3.sig.in.hresp <= core.io.dma_ahb.sig.in.hresp @[quasar_wrapper.scala 102:21] - _T_3.sig.in.hready <= core.io.dma_ahb.sig.in.hready @[quasar_wrapper.scala 102:21] - _T_3.sig.in.hrdata <= core.io.dma_ahb.sig.in.hrdata @[quasar_wrapper.scala 102:21] - core.io.lsu_axi.r.bits.last <= io.lsu_brg.r.bits.last @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.r.bits.resp <= io.lsu_brg.r.bits.resp @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.r.bits.data <= io.lsu_brg.r.bits.data @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.r.bits.id <= io.lsu_brg.r.bits.id @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.r.valid <= io.lsu_brg.r.valid @[quasar_wrapper.scala 104:21] - io.lsu_brg.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.ar.ready <= io.lsu_brg.ar.ready @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.b.bits.id <= io.lsu_brg.b.bits.id @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.b.bits.resp <= io.lsu_brg.b.bits.resp @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.b.valid <= io.lsu_brg.b.valid @[quasar_wrapper.scala 104:21] - io.lsu_brg.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 104:21] - io.lsu_brg.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 104:21] - io.lsu_brg.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 104:21] - io.lsu_brg.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 104:21] - io.lsu_brg.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.w.ready <= io.lsu_brg.w.ready @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.aw.ready <= io.lsu_brg.aw.ready @[quasar_wrapper.scala 104:21] - core.io.ifu_axi.r.bits.last <= io.ifu_brg.r.bits.last @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.r.bits.resp <= io.ifu_brg.r.bits.resp @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.r.bits.data <= io.ifu_brg.r.bits.data @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.r.bits.id <= io.ifu_brg.r.bits.id @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.r.valid <= io.ifu_brg.r.valid @[quasar_wrapper.scala 105:21] - io.ifu_brg.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.ar.ready <= io.ifu_brg.ar.ready @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.b.bits.id <= io.ifu_brg.b.bits.id @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.b.bits.resp <= io.ifu_brg.b.bits.resp @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.b.valid <= io.ifu_brg.b.valid @[quasar_wrapper.scala 105:21] - io.ifu_brg.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 105:21] - io.ifu_brg.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 105:21] - io.ifu_brg.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 105:21] - io.ifu_brg.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 105:21] - io.ifu_brg.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.w.ready <= io.ifu_brg.w.ready @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.aw.ready <= io.ifu_brg.aw.ready @[quasar_wrapper.scala 105:21] - core.io.sb_axi.r.bits.last <= io.sb_brg.r.bits.last @[quasar_wrapper.scala 106:21] - core.io.sb_axi.r.bits.resp <= io.sb_brg.r.bits.resp @[quasar_wrapper.scala 106:21] - core.io.sb_axi.r.bits.data <= io.sb_brg.r.bits.data @[quasar_wrapper.scala 106:21] - core.io.sb_axi.r.bits.id <= io.sb_brg.r.bits.id @[quasar_wrapper.scala 106:21] - core.io.sb_axi.r.valid <= io.sb_brg.r.valid @[quasar_wrapper.scala 106:21] - io.sb_brg.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 106:21] - core.io.sb_axi.ar.ready <= io.sb_brg.ar.ready @[quasar_wrapper.scala 106:21] - core.io.sb_axi.b.bits.id <= io.sb_brg.b.bits.id @[quasar_wrapper.scala 106:21] - core.io.sb_axi.b.bits.resp <= io.sb_brg.b.bits.resp @[quasar_wrapper.scala 106:21] - core.io.sb_axi.b.valid <= io.sb_brg.b.valid @[quasar_wrapper.scala 106:21] - io.sb_brg.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 106:21] - io.sb_brg.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 106:21] - io.sb_brg.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 106:21] - io.sb_brg.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 106:21] - io.sb_brg.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 106:21] - core.io.sb_axi.w.ready <= io.sb_brg.w.ready @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 106:21] - core.io.sb_axi.aw.ready <= io.sb_brg.aw.ready @[quasar_wrapper.scala 106:21] - io.dma_brg.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 107:21] - io.dma_brg.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 107:21] - io.dma_brg.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 107:21] - io.dma_brg.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 107:21] - io.dma_brg.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 107:21] - core.io.dma_axi.r.ready <= io.dma_brg.r.ready @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.qos <= io.dma_brg.ar.bits.qos @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.prot <= io.dma_brg.ar.bits.prot @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.cache <= io.dma_brg.ar.bits.cache @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.lock <= io.dma_brg.ar.bits.lock @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.burst <= io.dma_brg.ar.bits.burst @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.size <= io.dma_brg.ar.bits.size @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.len <= io.dma_brg.ar.bits.len @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.region <= io.dma_brg.ar.bits.region @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.addr <= io.dma_brg.ar.bits.addr @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.id <= io.dma_brg.ar.bits.id @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.valid <= io.dma_brg.ar.valid @[quasar_wrapper.scala 107:21] - io.dma_brg.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 107:21] - io.dma_brg.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 107:21] - io.dma_brg.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 107:21] - io.dma_brg.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 107:21] - core.io.dma_axi.b.ready <= io.dma_brg.b.ready @[quasar_wrapper.scala 107:21] - core.io.dma_axi.w.bits.last <= io.dma_brg.w.bits.last @[quasar_wrapper.scala 107:21] - core.io.dma_axi.w.bits.strb <= io.dma_brg.w.bits.strb @[quasar_wrapper.scala 107:21] - core.io.dma_axi.w.bits.data <= io.dma_brg.w.bits.data @[quasar_wrapper.scala 107:21] - core.io.dma_axi.w.valid <= io.dma_brg.w.valid @[quasar_wrapper.scala 107:21] - io.dma_brg.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.qos <= io.dma_brg.aw.bits.qos @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.prot <= io.dma_brg.aw.bits.prot @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.cache <= io.dma_brg.aw.bits.cache @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.lock <= io.dma_brg.aw.bits.lock @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.burst <= io.dma_brg.aw.bits.burst @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.size <= io.dma_brg.aw.bits.size @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.len <= io.dma_brg.aw.bits.len @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.region <= io.dma_brg.aw.bits.region @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.addr <= io.dma_brg.aw.bits.addr @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.id <= io.dma_brg.aw.bits.id @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.valid <= io.dma_brg.aw.valid @[quasar_wrapper.scala 107:21] - io.dma_brg.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 107:21] - core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 121:21] - core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 122:19] - core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 123:19] - core.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 124:19] - core.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 127:26] - core.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 128:25] - core.io.core_id <= io.core_id @[quasar_wrapper.scala 129:19] - core.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 132:30] - core.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 133:29] - core.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 134:29] - core.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 136:26] - core.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 137:26] - core.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 138:26] - core.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 139:26] - core.io.timer_int <= io.timer_int @[quasar_wrapper.scala 141:21] - core.io.soft_int <= io.soft_int @[quasar_wrapper.scala 142:20] - core.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 143:25] - io.rv_trace_pkt.rv_i_tval_ip <= core.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 147:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= core.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 147:19] - io.rv_trace_pkt.rv_i_ecause_ip <= core.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 147:19] - io.rv_trace_pkt.rv_i_exception_ip <= core.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 147:19] - io.rv_trace_pkt.rv_i_address_ip <= core.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 147:19] - io.rv_trace_pkt.rv_i_insn_ip <= core.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 147:19] - io.rv_trace_pkt.rv_i_valid_ip <= core.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 147:19] - io.o_cpu_halt_ack <= core.io.o_cpu_halt_ack @[quasar_wrapper.scala 150:21] - io.o_cpu_halt_status <= core.io.o_cpu_halt_status @[quasar_wrapper.scala 151:24] - io.o_cpu_run_ack <= core.io.o_cpu_run_ack @[quasar_wrapper.scala 152:20] - io.o_debug_mode_status <= core.io.o_debug_mode_status @[quasar_wrapper.scala 153:26] - io.mpc_debug_halt_ack <= core.io.mpc_debug_halt_ack @[quasar_wrapper.scala 155:25] - io.mpc_debug_run_ack <= core.io.mpc_debug_run_ack @[quasar_wrapper.scala 156:24] - io.debug_brkpt_status <= core.io.debug_brkpt_status @[quasar_wrapper.scala 157:25] - io.dec_tlu_perfcnt0 <= core.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 159:23] - io.dec_tlu_perfcnt1 <= core.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 160:23] - io.dec_tlu_perfcnt2 <= core.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 161:23] - io.dec_tlu_perfcnt3 <= core.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 162:23] + dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 74:29] + core.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 75:25] + core.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 76:24] + core.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 77:22] + core.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 78:25] + core.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 79:26] + io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 80:15] + mem.dccm_clk_override <= core.io.dccm_clk_override @[quasar_wrapper.scala 83:28] + mem.icm_clk_override <= core.io.icm_clk_override @[quasar_wrapper.scala 84:27] + mem.dec_tlu_core_ecc_disable <= core.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 85:35] + core.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 86:15] + core.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 86:15] + mem.dccm.wr_data_hi <= core.io.dccm.wr_data_hi @[quasar_wrapper.scala 86:15] + mem.dccm.wr_data_lo <= core.io.dccm.wr_data_lo @[quasar_wrapper.scala 86:15] + mem.dccm.rd_addr_hi <= core.io.dccm.rd_addr_hi @[quasar_wrapper.scala 86:15] + mem.dccm.rd_addr_lo <= core.io.dccm.rd_addr_lo @[quasar_wrapper.scala 86:15] + mem.dccm.wr_addr_hi <= core.io.dccm.wr_addr_hi @[quasar_wrapper.scala 86:15] + mem.dccm.wr_addr_lo <= core.io.dccm.wr_addr_lo @[quasar_wrapper.scala 86:15] + mem.dccm.rden <= core.io.dccm.rden @[quasar_wrapper.scala 86:15] + mem.dccm.wren <= core.io.dccm.wren @[quasar_wrapper.scala 86:15] + mem.rst_l <= reset @[quasar_wrapper.scala 87:16] + mem.clk <= clock @[quasar_wrapper.scala 88:14] + mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 89:20] + core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 91:21] + mem.ic.sel_premux_data <= core.io.ic.sel_premux_data @[quasar_wrapper.scala 92:14] + mem.ic.premux_data <= core.io.ic.premux_data @[quasar_wrapper.scala 92:14] + mem.ic.debug_way <= core.io.ic.debug_way @[quasar_wrapper.scala 92:14] + mem.ic.debug_tag_array <= core.io.ic.debug_tag_array @[quasar_wrapper.scala 92:14] + mem.ic.debug_wr_en <= core.io.ic.debug_wr_en @[quasar_wrapper.scala 92:14] + mem.ic.debug_rd_en <= core.io.ic.debug_rd_en @[quasar_wrapper.scala 92:14] + core.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 92:14] + core.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 92:14] + core.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 92:14] + core.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 92:14] + core.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 92:14] + core.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 92:14] + core.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 92:14] + mem.ic.debug_addr <= core.io.ic.debug_addr @[quasar_wrapper.scala 92:14] + mem.ic.debug_wr_data <= core.io.ic.debug_wr_data @[quasar_wrapper.scala 92:14] + mem.ic.wr_data[0] <= core.io.ic.wr_data[0] @[quasar_wrapper.scala 92:14] + mem.ic.wr_data[1] <= core.io.ic.wr_data[1] @[quasar_wrapper.scala 92:14] + mem.ic.rd_en <= core.io.ic.rd_en @[quasar_wrapper.scala 92:14] + mem.ic.wr_en <= core.io.ic.wr_en @[quasar_wrapper.scala 92:14] + mem.ic.tag_valid <= core.io.ic.tag_valid @[quasar_wrapper.scala 92:14] + mem.ic.rw_addr <= core.io.ic.rw_addr @[quasar_wrapper.scala 92:14] + core.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 93:16] + core.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 93:16] + mem.iccm.wr_data <= core.io.iccm.wr_data @[quasar_wrapper.scala 93:16] + mem.iccm.wr_size <= core.io.iccm.wr_size @[quasar_wrapper.scala 93:16] + mem.iccm.rden <= core.io.iccm.rden @[quasar_wrapper.scala 93:16] + mem.iccm.wren <= core.io.iccm.wren @[quasar_wrapper.scala 93:16] + mem.iccm.correction_state <= core.io.iccm.correction_state @[quasar_wrapper.scala 93:16] + mem.iccm.buf_correct_ecc <= core.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 93:16] + mem.iccm.rw_addr <= core.io.iccm.rw_addr @[quasar_wrapper.scala 93:16] + io.ifu_brg.out.hwdata <= core.io.ifu_ahb.out.hwdata @[quasar_wrapper.scala 108:21] + io.ifu_brg.out.hwrite <= core.io.ifu_ahb.out.hwrite @[quasar_wrapper.scala 108:21] + io.ifu_brg.out.htrans <= core.io.ifu_ahb.out.htrans @[quasar_wrapper.scala 108:21] + io.ifu_brg.out.hsize <= core.io.ifu_ahb.out.hsize @[quasar_wrapper.scala 108:21] + io.ifu_brg.out.hprot <= core.io.ifu_ahb.out.hprot @[quasar_wrapper.scala 108:21] + io.ifu_brg.out.hmastlock <= core.io.ifu_ahb.out.hmastlock @[quasar_wrapper.scala 108:21] + io.ifu_brg.out.hburst <= core.io.ifu_ahb.out.hburst @[quasar_wrapper.scala 108:21] + io.ifu_brg.out.haddr <= core.io.ifu_ahb.out.haddr @[quasar_wrapper.scala 108:21] + core.io.ifu_ahb.in.hresp <= io.ifu_brg.in.hresp @[quasar_wrapper.scala 108:21] + core.io.ifu_ahb.in.hready <= io.ifu_brg.in.hready @[quasar_wrapper.scala 108:21] + core.io.ifu_ahb.in.hrdata <= io.ifu_brg.in.hrdata @[quasar_wrapper.scala 108:21] + io.lsu_brg.out.hwdata <= core.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 109:21] + io.lsu_brg.out.hwrite <= core.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 109:21] + io.lsu_brg.out.htrans <= core.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 109:21] + io.lsu_brg.out.hsize <= core.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 109:21] + io.lsu_brg.out.hprot <= core.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 109:21] + io.lsu_brg.out.hmastlock <= core.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 109:21] + io.lsu_brg.out.hburst <= core.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 109:21] + io.lsu_brg.out.haddr <= core.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 109:21] + core.io.lsu_ahb.in.hresp <= io.lsu_brg.in.hresp @[quasar_wrapper.scala 109:21] + core.io.lsu_ahb.in.hready <= io.lsu_brg.in.hready @[quasar_wrapper.scala 109:21] + core.io.lsu_ahb.in.hrdata <= io.lsu_brg.in.hrdata @[quasar_wrapper.scala 109:21] + io.sb_brg.out.hwdata <= core.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 110:20] + io.sb_brg.out.hwrite <= core.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 110:20] + io.sb_brg.out.htrans <= core.io.sb_ahb.out.htrans @[quasar_wrapper.scala 110:20] + io.sb_brg.out.hsize <= core.io.sb_ahb.out.hsize @[quasar_wrapper.scala 110:20] + io.sb_brg.out.hprot <= core.io.sb_ahb.out.hprot @[quasar_wrapper.scala 110:20] + io.sb_brg.out.hmastlock <= core.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 110:20] + io.sb_brg.out.hburst <= core.io.sb_ahb.out.hburst @[quasar_wrapper.scala 110:20] + io.sb_brg.out.haddr <= core.io.sb_ahb.out.haddr @[quasar_wrapper.scala 110:20] + core.io.sb_ahb.in.hresp <= io.sb_brg.in.hresp @[quasar_wrapper.scala 110:20] + core.io.sb_ahb.in.hready <= io.sb_brg.in.hready @[quasar_wrapper.scala 110:20] + core.io.sb_ahb.in.hrdata <= io.sb_brg.in.hrdata @[quasar_wrapper.scala 110:20] + core.io.dma_ahb.hreadyin <= io.dma_brg.hreadyin @[quasar_wrapper.scala 111:21] + core.io.dma_ahb.hsel <= io.dma_brg.hsel @[quasar_wrapper.scala 111:21] + core.io.dma_ahb.sig.out.hwdata <= io.dma_brg.sig.out.hwdata @[quasar_wrapper.scala 111:21] + core.io.dma_ahb.sig.out.hwrite <= io.dma_brg.sig.out.hwrite @[quasar_wrapper.scala 111:21] + core.io.dma_ahb.sig.out.htrans <= io.dma_brg.sig.out.htrans @[quasar_wrapper.scala 111:21] + core.io.dma_ahb.sig.out.hsize <= io.dma_brg.sig.out.hsize @[quasar_wrapper.scala 111:21] + core.io.dma_ahb.sig.out.hprot <= io.dma_brg.sig.out.hprot @[quasar_wrapper.scala 111:21] + core.io.dma_ahb.sig.out.hmastlock <= io.dma_brg.sig.out.hmastlock @[quasar_wrapper.scala 111:21] + core.io.dma_ahb.sig.out.hburst <= io.dma_brg.sig.out.hburst @[quasar_wrapper.scala 111:21] + core.io.dma_ahb.sig.out.haddr <= io.dma_brg.sig.out.haddr @[quasar_wrapper.scala 111:21] + io.dma_brg.sig.in.hresp <= core.io.dma_ahb.sig.in.hresp @[quasar_wrapper.scala 111:21] + io.dma_brg.sig.in.hready <= core.io.dma_ahb.sig.in.hready @[quasar_wrapper.scala 111:21] + io.dma_brg.sig.in.hrdata <= core.io.dma_ahb.sig.in.hrdata @[quasar_wrapper.scala 111:21] + wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 113:36] + _T.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 113:36] + _T.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 113:36] + _T.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] + _T.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] + _T.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 113:36] + _T.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 113:36] + _T.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 113:36] + _T.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + _T.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] + core.io.lsu_axi.r.bits.last <= _T.r.bits.last @[quasar_wrapper.scala 113:21] + core.io.lsu_axi.r.bits.resp <= _T.r.bits.resp @[quasar_wrapper.scala 113:21] + core.io.lsu_axi.r.bits.data <= _T.r.bits.data @[quasar_wrapper.scala 113:21] + core.io.lsu_axi.r.bits.id <= _T.r.bits.id @[quasar_wrapper.scala 113:21] + core.io.lsu_axi.r.valid <= _T.r.valid @[quasar_wrapper.scala 113:21] + _T.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 113:21] + _T.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 113:21] + _T.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 113:21] + _T.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 113:21] + _T.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 113:21] + _T.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 113:21] + _T.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 113:21] + _T.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 113:21] + _T.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 113:21] + _T.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 113:21] + _T.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 113:21] + _T.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 113:21] + core.io.lsu_axi.ar.ready <= _T.ar.ready @[quasar_wrapper.scala 113:21] + core.io.lsu_axi.b.bits.id <= _T.b.bits.id @[quasar_wrapper.scala 113:21] + core.io.lsu_axi.b.bits.resp <= _T.b.bits.resp @[quasar_wrapper.scala 113:21] + core.io.lsu_axi.b.valid <= _T.b.valid @[quasar_wrapper.scala 113:21] + _T.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 113:21] + _T.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 113:21] + _T.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 113:21] + _T.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 113:21] + _T.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 113:21] + core.io.lsu_axi.w.ready <= _T.w.ready @[quasar_wrapper.scala 113:21] + _T.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 113:21] + _T.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 113:21] + _T.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 113:21] + _T.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 113:21] + _T.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 113:21] + _T.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 113:21] + _T.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 113:21] + _T.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 113:21] + _T.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 113:21] + _T.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 113:21] + _T.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 113:21] + core.io.lsu_axi.aw.ready <= _T.aw.ready @[quasar_wrapper.scala 113:21] + wire _T_1 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 114:36] + _T_1.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 114:36] + _T_1.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 114:36] + _T_1.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] + _T_1.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] + _T_1.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 114:36] + _T_1.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 114:36] + _T_1.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 114:36] + _T_1.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + _T_1.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] + core.io.ifu_axi.r.bits.last <= _T_1.r.bits.last @[quasar_wrapper.scala 114:21] + core.io.ifu_axi.r.bits.resp <= _T_1.r.bits.resp @[quasar_wrapper.scala 114:21] + core.io.ifu_axi.r.bits.data <= _T_1.r.bits.data @[quasar_wrapper.scala 114:21] + core.io.ifu_axi.r.bits.id <= _T_1.r.bits.id @[quasar_wrapper.scala 114:21] + core.io.ifu_axi.r.valid <= _T_1.r.valid @[quasar_wrapper.scala 114:21] + _T_1.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 114:21] + _T_1.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 114:21] + _T_1.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 114:21] + _T_1.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 114:21] + _T_1.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 114:21] + _T_1.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 114:21] + _T_1.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 114:21] + _T_1.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 114:21] + _T_1.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 114:21] + _T_1.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 114:21] + _T_1.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 114:21] + _T_1.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 114:21] + core.io.ifu_axi.ar.ready <= _T_1.ar.ready @[quasar_wrapper.scala 114:21] + core.io.ifu_axi.b.bits.id <= _T_1.b.bits.id @[quasar_wrapper.scala 114:21] + core.io.ifu_axi.b.bits.resp <= _T_1.b.bits.resp @[quasar_wrapper.scala 114:21] + core.io.ifu_axi.b.valid <= _T_1.b.valid @[quasar_wrapper.scala 114:21] + _T_1.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 114:21] + _T_1.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 114:21] + _T_1.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 114:21] + _T_1.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 114:21] + _T_1.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 114:21] + core.io.ifu_axi.w.ready <= _T_1.w.ready @[quasar_wrapper.scala 114:21] + _T_1.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 114:21] + _T_1.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 114:21] + _T_1.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 114:21] + _T_1.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 114:21] + _T_1.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 114:21] + _T_1.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 114:21] + _T_1.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 114:21] + _T_1.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 114:21] + _T_1.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 114:21] + _T_1.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 114:21] + _T_1.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 114:21] + core.io.ifu_axi.aw.ready <= _T_1.aw.ready @[quasar_wrapper.scala 114:21] + wire _T_2 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 115:36] + _T_2.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] + _T_2.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 115:36] + _T_2.r.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.b.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] + _T_2.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] + _T_2.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 115:36] + _T_2.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T_2.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + core.io.sb_axi.r.bits.last <= _T_2.r.bits.last @[quasar_wrapper.scala 115:21] + core.io.sb_axi.r.bits.resp <= _T_2.r.bits.resp @[quasar_wrapper.scala 115:21] + core.io.sb_axi.r.bits.data <= _T_2.r.bits.data @[quasar_wrapper.scala 115:21] + core.io.sb_axi.r.bits.id <= _T_2.r.bits.id @[quasar_wrapper.scala 115:21] + core.io.sb_axi.r.valid <= _T_2.r.valid @[quasar_wrapper.scala 115:21] + _T_2.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 115:21] + _T_2.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 115:21] + _T_2.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 115:21] + _T_2.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 115:21] + _T_2.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 115:21] + _T_2.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 115:21] + _T_2.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 115:21] + _T_2.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 115:21] + _T_2.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 115:21] + _T_2.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 115:21] + _T_2.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 115:21] + _T_2.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 115:21] + core.io.sb_axi.ar.ready <= _T_2.ar.ready @[quasar_wrapper.scala 115:21] + core.io.sb_axi.b.bits.id <= _T_2.b.bits.id @[quasar_wrapper.scala 115:21] + core.io.sb_axi.b.bits.resp <= _T_2.b.bits.resp @[quasar_wrapper.scala 115:21] + core.io.sb_axi.b.valid <= _T_2.b.valid @[quasar_wrapper.scala 115:21] + _T_2.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 115:21] + _T_2.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 115:21] + _T_2.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 115:21] + _T_2.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 115:21] + _T_2.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 115:21] + core.io.sb_axi.w.ready <= _T_2.w.ready @[quasar_wrapper.scala 115:21] + _T_2.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 115:21] + _T_2.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 115:21] + _T_2.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 115:21] + _T_2.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 115:21] + _T_2.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 115:21] + _T_2.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 115:21] + _T_2.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 115:21] + _T_2.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 115:21] + _T_2.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 115:21] + _T_2.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 115:21] + _T_2.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 115:21] + core.io.sb_axi.aw.ready <= _T_2.aw.ready @[quasar_wrapper.scala 115:21] + wire _T_3 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 116:36] + _T_3.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] + _T_3.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 116:36] + _T_3.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_3.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_3.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] + _T_3.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] + _T_3.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 116:36] + _T_3.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_3.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 116:21] + _T_3.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 116:21] + _T_3.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 116:21] + _T_3.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 116:21] + _T_3.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 116:21] + core.io.dma_axi.r.ready <= _T_3.r.ready @[quasar_wrapper.scala 116:21] + core.io.dma_axi.ar.bits.qos <= _T_3.ar.bits.qos @[quasar_wrapper.scala 116:21] + core.io.dma_axi.ar.bits.prot <= _T_3.ar.bits.prot @[quasar_wrapper.scala 116:21] + core.io.dma_axi.ar.bits.cache <= _T_3.ar.bits.cache @[quasar_wrapper.scala 116:21] + core.io.dma_axi.ar.bits.lock <= _T_3.ar.bits.lock @[quasar_wrapper.scala 116:21] + core.io.dma_axi.ar.bits.burst <= _T_3.ar.bits.burst @[quasar_wrapper.scala 116:21] + core.io.dma_axi.ar.bits.size <= _T_3.ar.bits.size @[quasar_wrapper.scala 116:21] + core.io.dma_axi.ar.bits.len <= _T_3.ar.bits.len @[quasar_wrapper.scala 116:21] + core.io.dma_axi.ar.bits.region <= _T_3.ar.bits.region @[quasar_wrapper.scala 116:21] + core.io.dma_axi.ar.bits.addr <= _T_3.ar.bits.addr @[quasar_wrapper.scala 116:21] + core.io.dma_axi.ar.bits.id <= _T_3.ar.bits.id @[quasar_wrapper.scala 116:21] + core.io.dma_axi.ar.valid <= _T_3.ar.valid @[quasar_wrapper.scala 116:21] + _T_3.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 116:21] + _T_3.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 116:21] + _T_3.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 116:21] + _T_3.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 116:21] + core.io.dma_axi.b.ready <= _T_3.b.ready @[quasar_wrapper.scala 116:21] + core.io.dma_axi.w.bits.last <= _T_3.w.bits.last @[quasar_wrapper.scala 116:21] + core.io.dma_axi.w.bits.strb <= _T_3.w.bits.strb @[quasar_wrapper.scala 116:21] + core.io.dma_axi.w.bits.data <= _T_3.w.bits.data @[quasar_wrapper.scala 116:21] + core.io.dma_axi.w.valid <= _T_3.w.valid @[quasar_wrapper.scala 116:21] + _T_3.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 116:21] + core.io.dma_axi.aw.bits.qos <= _T_3.aw.bits.qos @[quasar_wrapper.scala 116:21] + core.io.dma_axi.aw.bits.prot <= _T_3.aw.bits.prot @[quasar_wrapper.scala 116:21] + core.io.dma_axi.aw.bits.cache <= _T_3.aw.bits.cache @[quasar_wrapper.scala 116:21] + core.io.dma_axi.aw.bits.lock <= _T_3.aw.bits.lock @[quasar_wrapper.scala 116:21] + core.io.dma_axi.aw.bits.burst <= _T_3.aw.bits.burst @[quasar_wrapper.scala 116:21] + core.io.dma_axi.aw.bits.size <= _T_3.aw.bits.size @[quasar_wrapper.scala 116:21] + core.io.dma_axi.aw.bits.len <= _T_3.aw.bits.len @[quasar_wrapper.scala 116:21] + core.io.dma_axi.aw.bits.region <= _T_3.aw.bits.region @[quasar_wrapper.scala 116:21] + core.io.dma_axi.aw.bits.addr <= _T_3.aw.bits.addr @[quasar_wrapper.scala 116:21] + core.io.dma_axi.aw.bits.id <= _T_3.aw.bits.id @[quasar_wrapper.scala 116:21] + core.io.dma_axi.aw.valid <= _T_3.aw.valid @[quasar_wrapper.scala 116:21] + _T_3.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 116:21] + core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 119:21] + core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 120:19] + core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 121:19] + core.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 122:19] + core.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 125:26] + core.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 126:25] + core.io.core_id <= io.core_id @[quasar_wrapper.scala 127:19] + core.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 130:30] + core.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 131:29] + core.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 132:29] + core.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 134:26] + core.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 135:26] + core.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 136:26] + core.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 137:26] + core.io.timer_int <= io.timer_int @[quasar_wrapper.scala 139:21] + core.io.soft_int <= io.soft_int @[quasar_wrapper.scala 140:20] + core.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 141:25] + io.rv_trace_pkt.rv_i_tval_ip <= core.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 145:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= core.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 145:19] + io.rv_trace_pkt.rv_i_ecause_ip <= core.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 145:19] + io.rv_trace_pkt.rv_i_exception_ip <= core.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 145:19] + io.rv_trace_pkt.rv_i_address_ip <= core.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 145:19] + io.rv_trace_pkt.rv_i_insn_ip <= core.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 145:19] + io.rv_trace_pkt.rv_i_valid_ip <= core.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 145:19] + io.o_cpu_halt_ack <= core.io.o_cpu_halt_ack @[quasar_wrapper.scala 148:21] + io.o_cpu_halt_status <= core.io.o_cpu_halt_status @[quasar_wrapper.scala 149:24] + io.o_cpu_run_ack <= core.io.o_cpu_run_ack @[quasar_wrapper.scala 150:20] + io.o_debug_mode_status <= core.io.o_debug_mode_status @[quasar_wrapper.scala 151:26] + io.mpc_debug_halt_ack <= core.io.mpc_debug_halt_ack @[quasar_wrapper.scala 153:25] + io.mpc_debug_run_ack <= core.io.mpc_debug_run_ack @[quasar_wrapper.scala 154:24] + io.debug_brkpt_status <= core.io.debug_brkpt_status @[quasar_wrapper.scala 155:25] + io.dec_tlu_perfcnt0 <= core.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 157:23] + io.dec_tlu_perfcnt1 <= core.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 158:23] + io.dec_tlu_perfcnt2 <= core.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 159:23] + io.dec_tlu_perfcnt3 <= core.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 160:23] diff --git a/quasar_wrapper.v b/quasar_wrapper.v index e66ba6b6..e90c8a05 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -57,7 +57,6 @@ module ifu_mem_ctl( output io_ifu_axi_ar_valid, output [2:0] io_ifu_axi_ar_bits_id, output [31:0] io_ifu_axi_ar_bits_addr, - output [3:0] io_ifu_axi_ar_bits_region, output io_ifu_axi_r_ready, input io_ifu_axi_r_valid, input [2:0] io_ifu_axi_r_bits_id, @@ -1929,7 +1928,6 @@ module ifu_mem_ctl( wire _T_318 = ~stream_miss_f; // @[ifu_mem_ctl.scala 226:106] reg ifc_region_acc_fault_f; // @[ifu_mem_ctl.scala 232:68] reg [2:0] bus_rd_addr_count; // @[ifu_mem_ctl.scala 540:55] - wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58] wire _T_325 = _T_239 | _T_2268; // @[ifu_mem_ctl.scala 234:55] wire _T_328 = _T_325 & _T_56; // @[ifu_mem_ctl.scala 234:82] wire _T_2289 = ~ifu_bus_rid_ff[0]; // @[ifu_mem_ctl.scala 378:55] @@ -5662,7 +5660,6 @@ module ifu_mem_ctl( assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 497:23] assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2608; // @[ifu_mem_ctl.scala 498:25] assign io_ifu_axi_ar_bits_addr = _T_2610 & _T_2612; // @[ifu_mem_ctl.scala 499:27] - assign io_ifu_axi_ar_bits_region = ifu_ic_req_addr_f[28:25]; // @[ifu_mem_ctl.scala 502:29] assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 504:22] assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 599:19] assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2497; // @[ifu_mem_ctl.scala 395:27] @@ -44533,7 +44530,6 @@ module ifu( output io_ifu_ar_valid, output [2:0] io_ifu_ar_bits_id, output [31:0] io_ifu_ar_bits_addr, - output [3:0] io_ifu_ar_bits_region, input io_ifu_r_valid, input [2:0] io_ifu_r_bits_id, input [63:0] io_ifu_r_bits_data, @@ -44592,7 +44588,6 @@ module ifu( wire mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 34:23] wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 34:23] - wire [3:0] mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 34:23] @@ -44808,7 +44803,6 @@ module ifu( .io_ifu_axi_ar_valid(mem_ctl_io_ifu_axi_ar_valid), .io_ifu_axi_ar_bits_id(mem_ctl_io_ifu_axi_ar_bits_id), .io_ifu_axi_ar_bits_addr(mem_ctl_io_ifu_axi_ar_bits_addr), - .io_ifu_axi_ar_bits_region(mem_ctl_io_ifu_axi_ar_bits_region), .io_ifu_axi_r_ready(mem_ctl_io_ifu_axi_r_ready), .io_ifu_axi_r_valid(mem_ctl_io_ifu_axi_r_valid), .io_ifu_axi_r_bits_id(mem_ctl_io_ifu_axi_r_bits_id), @@ -45049,7 +45043,6 @@ module ifu( assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 103:22] assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 103:22] assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 103:22] - assign io_ifu_ar_bits_region = mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 103:22] assign io_iccm_dma_ecc_error = mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 113:25] assign io_iccm_dma_rvalid = mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 114:22] assign io_iccm_dma_rdata = mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 115:21] @@ -50189,56 +50182,56 @@ module dec_timer_ctl( wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] reg [31:0] mitcnt0; // @[lib.scala 374:16] reg [31:0] mitb0_b; // @[lib.scala 374:16] - wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2712:22] - wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2673:36] + wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2694:22] + wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2655:36] reg [31:0] mitcnt1; // @[lib.scala 374:16] reg [31:0] mitb1_b; // @[lib.scala 374:16] - wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2721:18] - wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2674:36] - wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2684:72] - wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2684:49] - reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2737:67] - reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2736:60] - wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2737:90] + wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2703:18] + wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2656:36] + wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2666:72] + wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2666:49] + reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2719:67] + reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2718:60] + wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2719:90] wire [2:0] mitctl0 = {_T_57,_T_58}; // @[Cat.scala 29:58] - wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2686:56] - wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2686:76] - wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2686:53] - wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2686:112] - wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2686:138] - wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2686:109] - wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2686:173] - wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2686:171] - wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2687:35] - wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2689:59] - wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2696:72] - wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2696:49] - reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2751:52] - reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2750:55] - wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2751:75] + wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2668:56] + wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2668:76] + wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2668:53] + wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2668:112] + wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2668:138] + wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2668:109] + wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2668:173] + wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2668:171] + wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2669:35] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2671:59] + wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2678:72] + wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2678:49] + reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2733:52] + reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2732:55] + wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2733:75] wire [3:0] mitctl1 = {_T_66,_T_67}; // @[Cat.scala 29:58] - wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2698:76] - wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2698:53] - wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2698:138] - wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2698:109] - wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2698:171] - wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2701:60] - wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2701:72] + wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2680:76] + wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2680:53] + wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2680:138] + wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2680:109] + wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2680:171] + wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2683:60] + wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2683:72] wire [31:0] _T_34 = {31'h0,_T_33}; // @[Cat.scala 29:58] - wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2701:35] - wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2703:60] - wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2710:70] - wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2719:69] - wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2732:72] - wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2732:49] - wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2733:31] - wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2747:71] - wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2747:49] - wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2748:31] - wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2753:51] - wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2753:68] - wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2753:83] - wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2753:98] + wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2683:35] + wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2685:60] + wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2692:70] + wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2701:69] + wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2714:72] + wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2714:49] + wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2715:31] + wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2729:71] + wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2729:49] + wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2730:31] + wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2735:51] + wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2735:68] + wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2735:83] + wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2735:98] wire [31:0] _T_81 = {29'h0,_T_57,_T_58}; // @[Cat.scala 29:58] wire [31:0] _T_84 = {28'h0,_T_66,_T_67}; // @[Cat.scala 29:58] wire [31:0] _T_85 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72] @@ -50275,10 +50268,10 @@ module dec_timer_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2754:33] - assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2753:33] - assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2676:31] - assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2677:31] + assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2736:33] + assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2735:33] + assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2658:31] + assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2659:31] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -50524,6 +50517,7 @@ module csr_tlu( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -50546,7 +50540,6 @@ module csr_tlu( input io_lsu_imprecise_error_load_any, input io_lsu_imprecise_error_store_any, output [31:0] io_dec_tlu_mrac_ff, - output io_dec_tlu_wb_coalescing_disable, output io_dec_tlu_bpred_disable, output io_dec_tlu_sideeffect_posted_disable, output io_dec_tlu_core_ecc_disable, @@ -50926,36 +50919,36 @@ module csr_tlu( wire rvclkhdr_34_io_clk; // @[lib.scala 343:22] wire rvclkhdr_34_io_en; // @[lib.scala 343:22] wire rvclkhdr_34_io_scan_mode; // @[lib.scala 343:22] - wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1449:45] - wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1449:43] - wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1449:68] - wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1450:71] - wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1450:42] - wire _T_498 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1836:68] - wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_498; // @[dec_tlu_ctl.scala 1836:39] - wire _T_510 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1844:37] - reg mpmc_b; // @[dec_tlu_ctl.scala 1846:44] - wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1849:10] - wire _T_511 = ~mpmc; // @[dec_tlu_ctl.scala 1844:62] - wire mpmc_b_ns = wr_mpmc_r ? _T_510 : _T_511; // @[dec_tlu_ctl.scala 1844:18] - wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1453:28] - wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1453:39] - wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1456:5] - wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1456:19] + wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1431:45] + wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1431:43] + wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1431:68] + wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1432:71] + wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1432:42] + wire _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1818:68] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1818:39] + wire _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1826:37] + reg mpmc_b; // @[dec_tlu_ctl.scala 1828:44] + wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1831:10] + wire _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1826:62] + wire mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1826:18] + wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1435:28] + wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1435:39] + wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1438:5] + wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1438:19] wire [1:0] _T_12 = {io_mstatus[0],1'h0}; // @[Cat.scala 29:58] - wire _T_13 = wr_mstatus_r & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1457:18] + wire _T_13 = wr_mstatus_r & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1439:18] wire [1:0] _T_16 = {io_dec_csr_wrdata_r[3],1'h0}; // @[Cat.scala 29:58] - wire _T_17 = ~io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1458:17] - wire _T_18 = io_mret_r & _T_17; // @[dec_tlu_ctl.scala 1458:15] + wire _T_17 = ~io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1440:17] + wire _T_18 = io_mret_r & _T_17; // @[dec_tlu_ctl.scala 1440:15] wire [1:0] _T_21 = {1'h1,io_mstatus[1]}; // @[Cat.scala 29:58] wire [1:0] _T_24 = {io_mstatus[1],1'h1}; // @[Cat.scala 29:58] - wire _T_26 = wr_mstatus_r & _T_17; // @[dec_tlu_ctl.scala 1460:18] + wire _T_26 = wr_mstatus_r & _T_17; // @[dec_tlu_ctl.scala 1442:18] wire [1:0] _T_30 = {io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] - wire _T_33 = _T_7 & _T_17; // @[dec_tlu_ctl.scala 1461:19] - wire _T_34 = ~io_mret_r; // @[dec_tlu_ctl.scala 1461:46] - wire _T_35 = _T_33 & _T_34; // @[dec_tlu_ctl.scala 1461:44] - wire _T_36 = ~set_mie_pmu_fw_halt; // @[dec_tlu_ctl.scala 1461:59] - wire _T_37 = _T_35 & _T_36; // @[dec_tlu_ctl.scala 1461:57] + wire _T_33 = _T_7 & _T_17; // @[dec_tlu_ctl.scala 1443:19] + wire _T_34 = ~io_mret_r; // @[dec_tlu_ctl.scala 1443:46] + wire _T_35 = _T_33 & _T_34; // @[dec_tlu_ctl.scala 1443:44] + wire _T_36 = ~set_mie_pmu_fw_halt; // @[dec_tlu_ctl.scala 1443:59] + wire _T_37 = _T_35 & _T_36; // @[dec_tlu_ctl.scala 1443:57] wire [1:0] _T_39 = _T_8 ? _T_12 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_40 = _T_13 ? _T_16 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_41 = _T_18 ? _T_21 : 2'h0; // @[Mux.scala 27:72] @@ -50966,155 +50959,155 @@ module csr_tlu( wire [1:0] _T_46 = _T_45 | _T_41; // @[Mux.scala 27:72] wire [1:0] _T_47 = _T_46 | _T_42; // @[Mux.scala 27:72] wire [1:0] _T_48 = _T_47 | _T_43; // @[Mux.scala 27:72] - wire _T_52 = ~io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 1464:50] - wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1464:81] - reg [1:0] _T_56; // @[dec_tlu_ctl.scala 1466:11] - wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1475:69] + wire _T_52 = ~io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 1446:50] + wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1446:81] + reg [1:0] _T_56; // @[dec_tlu_ctl.scala 1448:11] + wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1457:69] reg [30:0] _T_62; // @[lib.scala 374:16] reg [31:0] mdccmect; // @[lib.scala 374:16] - wire [62:0] _T_574 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1896:41] - wire [31:0] _T_576 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_9 = {{31'd0}, _T_576}; // @[dec_tlu_ctl.scala 1896:61] - wire [62:0] _T_577 = _T_574 & _GEN_9; // @[dec_tlu_ctl.scala 1896:61] - wire mdccme_ce_req = |_T_577; // @[dec_tlu_ctl.scala 1896:94] + wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1878:41] + wire [31:0] _T_566 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1878:61] + wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1878:61] + wire mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1878:94] reg [31:0] miccmect; // @[lib.scala 374:16] - wire [62:0] _T_554 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1881:40] - wire [31:0] _T_556 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_10 = {{31'd0}, _T_556}; // @[dec_tlu_ctl.scala 1881:60] - wire [62:0] _T_557 = _T_554 & _GEN_10; // @[dec_tlu_ctl.scala 1881:60] - wire miccme_ce_req = |_T_557; // @[dec_tlu_ctl.scala 1881:93] - wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1489:30] + wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1863:40] + wire [31:0] _T_546 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1863:60] + wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1863:60] + wire miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1863:93] + wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1471:30] reg [31:0] micect; // @[lib.scala 374:16] - wire [62:0] _T_532 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1866:39] - wire [31:0] _T_534 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_11 = {{31'd0}, _T_534}; // @[dec_tlu_ctl.scala 1866:57] - wire [62:0] _T_535 = _T_532 & _GEN_11; // @[dec_tlu_ctl.scala 1866:57] - wire mice_ce_req = |_T_535; // @[dec_tlu_ctl.scala 1866:88] - wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1489:46] + wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1848:39] + wire [31:0] _T_524 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1848:57] + wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1848:57] + wire mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1848:88] + wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1471:46] wire [2:0] _T_65 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_67 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] - reg [5:0] _T_68; // @[dec_tlu_ctl.scala 1493:11] - wire _T_70 = io_dec_csr_wraddr_r == 12'h304; // @[dec_tlu_ctl.scala 1505:67] - wire wr_mie_r = io_dec_csr_wen_r_mod & _T_70; // @[dec_tlu_ctl.scala 1505:38] + reg [5:0] _T_68; // @[dec_tlu_ctl.scala 1475:11] + wire _T_70 = io_dec_csr_wraddr_r == 12'h304; // @[dec_tlu_ctl.scala 1487:67] + wire wr_mie_r = io_dec_csr_wen_r_mod & _T_70; // @[dec_tlu_ctl.scala 1487:38] wire [5:0] _T_78 = {io_dec_csr_wrdata_r[30:28],io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] - reg [5:0] mie; // @[dec_tlu_ctl.scala 1508:11] - wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[dec_tlu_ctl.scala 1515:54] - wire _T_83 = io_dec_csr_wraddr_r == 12'hb00; // @[dec_tlu_ctl.scala 1517:71] - wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_83; // @[dec_tlu_ctl.scala 1517:42] - wire _T_85 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 1519:71] - wire _T_86 = kill_ebreak_count_r | _T_85; // @[dec_tlu_ctl.scala 1519:46] - wire _T_87 = _T_86 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1519:94] + reg [5:0] mie; // @[dec_tlu_ctl.scala 1490:11] + wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[dec_tlu_ctl.scala 1497:54] + wire _T_83 = io_dec_csr_wraddr_r == 12'hb00; // @[dec_tlu_ctl.scala 1499:71] + wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_83; // @[dec_tlu_ctl.scala 1499:42] + wire _T_85 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 1501:71] + wire _T_86 = kill_ebreak_count_r | _T_85; // @[dec_tlu_ctl.scala 1501:46] + wire _T_87 = _T_86 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1501:94] reg [4:0] temp_ncount6_2; // @[Reg.scala 27:20] reg temp_ncount0; // @[Reg.scala 27:20] wire [6:0] mcountinhibit = {temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire _T_89 = _T_87 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1519:121] - wire mcyclel_cout_in = ~_T_89; // @[dec_tlu_ctl.scala 1519:24] + wire _T_89 = _T_87 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1501:121] + wire mcyclel_cout_in = ~_T_89; // @[dec_tlu_ctl.scala 1501:24] wire [31:0] _T_90 = {31'h0,mcyclel_cout_in}; // @[Cat.scala 29:58] reg [31:0] mcyclel; // @[lib.scala 374:16] - wire [32:0] mcyclel_inc = mcyclel + _T_90; // @[dec_tlu_ctl.scala 1523:25] - wire mcyclel_cout = mcyclel_inc[32]; // @[dec_tlu_ctl.scala 1525:32] - wire _T_101 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1533:68] - wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_101; // @[dec_tlu_ctl.scala 1533:39] - wire _T_98 = ~wr_mcycleh_r; // @[dec_tlu_ctl.scala 1527:71] - reg mcyclel_cout_f; // @[dec_tlu_ctl.scala 1527:54] + wire [32:0] mcyclel_inc = mcyclel + _T_90; // @[dec_tlu_ctl.scala 1505:25] + wire mcyclel_cout = mcyclel_inc[32]; // @[dec_tlu_ctl.scala 1507:32] + wire _T_101 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1515:68] + wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_101; // @[dec_tlu_ctl.scala 1515:39] + wire _T_98 = ~wr_mcycleh_r; // @[dec_tlu_ctl.scala 1509:71] + reg mcyclel_cout_f; // @[dec_tlu_ctl.scala 1509:54] wire [31:0] _T_103 = {31'h0,mcyclel_cout_f}; // @[Cat.scala 29:58] reg [31:0] mcycleh; // @[lib.scala 374:16] - wire [31:0] mcycleh_inc = mcycleh + _T_103; // @[dec_tlu_ctl.scala 1535:28] - wire _T_109 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1552:72] - wire _T_110 = _T_109 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1552:85] - wire _T_111 = _T_110 | io_illegal_r; // @[dec_tlu_ctl.scala 1552:113] - wire _T_113 = _T_111 | mcountinhibit[2]; // @[dec_tlu_ctl.scala 1552:128] - wire _T_115 = ~_T_113; // @[dec_tlu_ctl.scala 1552:58] - wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_115; // @[dec_tlu_ctl.scala 1552:56] - wire _T_117 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1554:73] - wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_117; // @[dec_tlu_ctl.scala 1554:44] + wire [31:0] mcycleh_inc = mcycleh + _T_103; // @[dec_tlu_ctl.scala 1517:28] + wire _T_109 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1534:72] + wire _T_110 = _T_109 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1534:85] + wire _T_111 = _T_110 | io_illegal_r; // @[dec_tlu_ctl.scala 1534:113] + wire _T_113 = _T_111 | mcountinhibit[2]; // @[dec_tlu_ctl.scala 1534:128] + wire _T_115 = ~_T_113; // @[dec_tlu_ctl.scala 1534:58] + wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_115; // @[dec_tlu_ctl.scala 1534:56] + wire _T_117 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1536:73] + wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_117; // @[dec_tlu_ctl.scala 1536:44] wire [31:0] _T_118 = {31'h0,i0_valid_no_ebreak_ecall_r}; // @[Cat.scala 29:58] reg [31:0] minstretl; // @[lib.scala 374:16] - wire [32:0] minstretl_inc = minstretl + _T_118; // @[dec_tlu_ctl.scala 1556:29] - wire minstretl_cout = minstretl_inc[32]; // @[dec_tlu_ctl.scala 1557:36] - reg minstret_enable_f; // @[dec_tlu_ctl.scala 1562:56] - wire _T_128 = io_dec_csr_wraddr_r == 12'hb82; // @[dec_tlu_ctl.scala 1571:71] - wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_128; // @[dec_tlu_ctl.scala 1571:42] - wire _T_125 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1563:75] - reg minstretl_cout_f; // @[dec_tlu_ctl.scala 1563:56] + wire [32:0] minstretl_inc = minstretl + _T_118; // @[dec_tlu_ctl.scala 1538:29] + wire minstretl_cout = minstretl_inc[32]; // @[dec_tlu_ctl.scala 1539:36] + reg minstret_enable_f; // @[dec_tlu_ctl.scala 1544:56] + wire _T_128 = io_dec_csr_wraddr_r == 12'hb82; // @[dec_tlu_ctl.scala 1553:71] + wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_128; // @[dec_tlu_ctl.scala 1553:42] + wire _T_125 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1545:75] + reg minstretl_cout_f; // @[dec_tlu_ctl.scala 1545:56] wire [31:0] _T_131 = {31'h0,minstretl_cout_f}; // @[Cat.scala 29:58] reg [31:0] minstreth; // @[lib.scala 374:16] - wire [31:0] minstreth_inc = minstreth + _T_131; // @[dec_tlu_ctl.scala 1574:29] - wire _T_139 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1585:72] + wire [31:0] minstreth_inc = minstreth + _T_131; // @[dec_tlu_ctl.scala 1556:29] + wire _T_139 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1567:72] reg [31:0] mscratch; // @[lib.scala 374:16] - wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1596:22] - wire _T_143 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1596:47] - wire _T_144 = _T_142 & _T_143; // @[dec_tlu_ctl.scala 1596:45] - wire sel_exu_npc_r = _T_144 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1596:72] - wire _T_146 = _T_142 & io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1597:47] - wire _T_147 = ~io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 1597:75] - wire sel_flush_npc_r = _T_146 & _T_147; // @[dec_tlu_ctl.scala 1597:73] - wire _T_148 = ~sel_exu_npc_r; // @[dec_tlu_ctl.scala 1598:23] - wire _T_149 = ~sel_flush_npc_r; // @[dec_tlu_ctl.scala 1598:40] - wire sel_hold_npc_r = _T_148 & _T_149; // @[dec_tlu_ctl.scala 1598:38] - wire _T_151 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 1602:13] - wire _T_152 = _T_151 & io_reset_delayed; // @[dec_tlu_ctl.scala 1602:35] + wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1578:22] + wire _T_143 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1578:47] + wire _T_144 = _T_142 & _T_143; // @[dec_tlu_ctl.scala 1578:45] + wire sel_exu_npc_r = _T_144 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1578:72] + wire _T_146 = _T_142 & io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1579:47] + wire _T_147 = ~io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 1579:75] + wire sel_flush_npc_r = _T_146 & _T_147; // @[dec_tlu_ctl.scala 1579:73] + wire _T_148 = ~sel_exu_npc_r; // @[dec_tlu_ctl.scala 1580:23] + wire _T_149 = ~sel_flush_npc_r; // @[dec_tlu_ctl.scala 1580:40] + wire sel_hold_npc_r = _T_148 & _T_149; // @[dec_tlu_ctl.scala 1580:38] + wire _T_151 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 1584:13] + wire _T_152 = _T_151 & io_reset_delayed; // @[dec_tlu_ctl.scala 1584:35] wire [30:0] _T_156 = sel_exu_npc_r ? io_exu_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_157 = _T_152 ? io_rst_vec : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_158 = sel_flush_npc_r ? io_tlu_flush_path_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_159 = sel_hold_npc_r ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_160 = _T_156 | _T_157; // @[Mux.scala 27:72] wire [30:0] _T_161 = _T_160 | _T_158; // @[Mux.scala 27:72] - wire _T_164 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1606:48] + wire _T_164 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1588:48] reg [30:0] _T_167; // @[lib.scala 374:16] - wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1609:44] - wire _T_170 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1613:22] + wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1591:44] + wire _T_170 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1595:22] wire [30:0] _T_171 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] reg [30:0] pc_r_d1; // @[lib.scala 374:16] wire [30:0] _T_172 = _T_170 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] pc_r = _T_171 | _T_172; // @[Mux.scala 27:72] - wire _T_176 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1617:68] - wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_176; // @[dec_tlu_ctl.scala 1617:39] - wire _T_177 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1620:27] - wire _T_178 = _T_177 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1620:48] - wire _T_182 = wr_mepc_r & _T_17; // @[dec_tlu_ctl.scala 1622:13] - wire _T_185 = ~wr_mepc_r; // @[dec_tlu_ctl.scala 1623:3] - wire _T_187 = _T_185 & _T_17; // @[dec_tlu_ctl.scala 1623:14] + wire _T_176 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1599:68] + wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_176; // @[dec_tlu_ctl.scala 1599:39] + wire _T_177 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1602:27] + wire _T_178 = _T_177 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1602:48] + wire _T_182 = wr_mepc_r & _T_17; // @[dec_tlu_ctl.scala 1604:13] + wire _T_185 = ~wr_mepc_r; // @[dec_tlu_ctl.scala 1605:3] + wire _T_187 = _T_185 & _T_17; // @[dec_tlu_ctl.scala 1605:14] wire [30:0] _T_189 = _T_178 ? pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_190 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_191 = _T_182 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_192 = _T_187 ? io_mepc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_193 = _T_189 | _T_190; // @[Mux.scala 27:72] wire [30:0] _T_194 = _T_193 | _T_191; // @[Mux.scala 27:72] - reg [30:0] _T_196; // @[dec_tlu_ctl.scala 1625:47] - wire _T_198 = io_dec_csr_wraddr_r == 12'h342; // @[dec_tlu_ctl.scala 1632:72] - wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_198; // @[dec_tlu_ctl.scala 1632:43] - wire _T_199 = io_exc_or_int_valid_r & io_take_nmi; // @[dec_tlu_ctl.scala 1633:53] - wire mcause_sel_nmi_store = _T_199 & io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 1633:67] - wire mcause_sel_nmi_load = _T_199 & io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 1634:66] - wire _T_202 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 1635:84] - wire mcause_sel_nmi_ext = _T_199 & _T_202; // @[dec_tlu_ctl.scala 1635:65] - wire _T_203 = &io_lsu_fir_error; // @[dec_tlu_ctl.scala 1641:53] - wire _T_206 = ~io_lsu_fir_error[0]; // @[dec_tlu_ctl.scala 1641:82] - wire _T_207 = io_lsu_fir_error[1] & _T_206; // @[dec_tlu_ctl.scala 1641:80] + reg [30:0] _T_196; // @[dec_tlu_ctl.scala 1607:47] + wire _T_198 = io_dec_csr_wraddr_r == 12'h342; // @[dec_tlu_ctl.scala 1614:72] + wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_198; // @[dec_tlu_ctl.scala 1614:43] + wire _T_199 = io_exc_or_int_valid_r & io_take_nmi; // @[dec_tlu_ctl.scala 1615:53] + wire mcause_sel_nmi_store = _T_199 & io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 1615:67] + wire mcause_sel_nmi_load = _T_199 & io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 1616:66] + wire _T_202 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 1617:84] + wire mcause_sel_nmi_ext = _T_199 & _T_202; // @[dec_tlu_ctl.scala 1617:65] + wire _T_203 = &io_lsu_fir_error; // @[dec_tlu_ctl.scala 1623:53] + wire _T_206 = ~io_lsu_fir_error[0]; // @[dec_tlu_ctl.scala 1623:82] + wire _T_207 = io_lsu_fir_error[1] & _T_206; // @[dec_tlu_ctl.scala 1623:80] wire [31:0] _T_212 = {30'h3c000400,_T_203,_T_207}; // @[Cat.scala 29:58] - wire _T_213 = ~io_take_nmi; // @[dec_tlu_ctl.scala 1647:56] - wire _T_214 = io_exc_or_int_valid_r & _T_213; // @[dec_tlu_ctl.scala 1647:54] + wire _T_213 = ~io_take_nmi; // @[dec_tlu_ctl.scala 1629:56] + wire _T_214 = io_exc_or_int_valid_r & _T_213; // @[dec_tlu_ctl.scala 1629:54] wire [31:0] _T_217 = {io_interrupt_valid_r,26'h0,io_exc_cause_r}; // @[Cat.scala 29:58] - wire _T_219 = wr_mcause_r & _T_17; // @[dec_tlu_ctl.scala 1648:44] - wire _T_221 = ~wr_mcause_r; // @[dec_tlu_ctl.scala 1649:32] - wire _T_223 = _T_221 & _T_17; // @[dec_tlu_ctl.scala 1649:45] + wire _T_219 = wr_mcause_r & _T_17; // @[dec_tlu_ctl.scala 1630:44] + wire _T_221 = ~wr_mcause_r; // @[dec_tlu_ctl.scala 1631:32] + wire _T_223 = _T_221 & _T_17; // @[dec_tlu_ctl.scala 1631:45] wire [31:0] _T_225 = mcause_sel_nmi_store ? 32'hf0000000 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_226 = mcause_sel_nmi_load ? 32'hf0000001 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_227 = mcause_sel_nmi_ext ? _T_212 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_228 = _T_214 ? _T_217 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_229 = _T_219 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] - reg [31:0] mcause; // @[dec_tlu_ctl.scala 1651:49] + reg [31:0] mcause; // @[dec_tlu_ctl.scala 1633:49] wire [31:0] _T_230 = _T_223 ? mcause : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_231 = _T_225 | _T_226; // @[Mux.scala 27:72] wire [31:0] _T_232 = _T_231 | _T_227; // @[Mux.scala 27:72] wire [31:0] _T_233 = _T_232 | _T_228; // @[Mux.scala 27:72] wire [31:0] _T_234 = _T_233 | _T_229; // @[Mux.scala 27:72] - wire _T_238 = io_dec_csr_wraddr_r == 12'h7ff; // @[dec_tlu_ctl.scala 1658:71] - wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_238; // @[dec_tlu_ctl.scala 1658:42] - wire _T_239 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[dec_tlu_ctl.scala 1660:56] + wire _T_238 = io_dec_csr_wraddr_r == 12'h7ff; // @[dec_tlu_ctl.scala 1640:71] + wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_238; // @[dec_tlu_ctl.scala 1640:42] + wire _T_239 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[dec_tlu_ctl.scala 1642:56] wire [3:0] _T_240 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] - wire [3:0] ifu_mscause = _T_239 ? 4'h9 : _T_240; // @[dec_tlu_ctl.scala 1660:24] + wire [3:0] ifu_mscause = _T_239 ? 4'h9 : _T_240; // @[dec_tlu_ctl.scala 1642:24] wire [3:0] _T_245 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72] wire [1:0] _T_247 = io_ebreak_r ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [3:0] _T_248 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] @@ -51123,482 +51116,488 @@ module csr_tlu( wire [3:0] _GEN_13 = {{2'd0}, _T_247}; // @[Mux.scala 27:72] wire [3:0] _T_250 = _T_249 | _GEN_13; // @[Mux.scala 27:72] wire [3:0] mscause_type = _T_250 | _T_248; // @[Mux.scala 27:72] - wire _T_254 = wr_mscause_r & _T_17; // @[dec_tlu_ctl.scala 1671:38] - wire _T_257 = ~wr_mscause_r; // @[dec_tlu_ctl.scala 1672:25] - wire _T_259 = _T_257 & _T_17; // @[dec_tlu_ctl.scala 1672:39] + wire _T_254 = wr_mscause_r & _T_17; // @[dec_tlu_ctl.scala 1653:38] + wire _T_257 = ~wr_mscause_r; // @[dec_tlu_ctl.scala 1654:25] + wire _T_259 = _T_257 & _T_17; // @[dec_tlu_ctl.scala 1654:39] wire [3:0] _T_261 = io_exc_or_int_valid_r ? mscause_type : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_262 = _T_254 ? io_dec_csr_wrdata_r[3:0] : 4'h0; // @[Mux.scala 27:72] - reg [3:0] mscause; // @[dec_tlu_ctl.scala 1674:47] + reg [3:0] mscause; // @[dec_tlu_ctl.scala 1656:47] wire [3:0] _T_263 = _T_259 ? mscause : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_264 = _T_261 | _T_262; // @[Mux.scala 27:72] - wire _T_268 = io_dec_csr_wraddr_r == 12'h343; // @[dec_tlu_ctl.scala 1681:69] - wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_268; // @[dec_tlu_ctl.scala 1681:40] - wire _T_269 = ~io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1682:83] - wire _T_270 = io_inst_acc_r & _T_269; // @[dec_tlu_ctl.scala 1682:81] - wire _T_271 = io_ebreak_r | _T_270; // @[dec_tlu_ctl.scala 1682:64] - wire _T_272 = _T_271 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1682:106] - wire _T_273 = io_exc_or_int_valid_r & _T_272; // @[dec_tlu_ctl.scala 1682:49] - wire mtval_capture_pc_r = _T_273 & _T_213; // @[dec_tlu_ctl.scala 1682:138] - wire _T_275 = io_inst_acc_r & io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1683:72] - wire _T_276 = io_exc_or_int_valid_r & _T_275; // @[dec_tlu_ctl.scala 1683:55] - wire mtval_capture_pc_plus2_r = _T_276 & _T_213; // @[dec_tlu_ctl.scala 1683:96] - wire _T_278 = io_exc_or_int_valid_r & io_illegal_r; // @[dec_tlu_ctl.scala 1684:51] - wire mtval_capture_inst_r = _T_278 & _T_213; // @[dec_tlu_ctl.scala 1684:66] - wire _T_280 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1685:50] - wire mtval_capture_lsu_r = _T_280 & _T_213; // @[dec_tlu_ctl.scala 1685:71] - wire _T_282 = ~mtval_capture_pc_r; // @[dec_tlu_ctl.scala 1686:46] - wire _T_283 = io_exc_or_int_valid_r & _T_282; // @[dec_tlu_ctl.scala 1686:44] - wire _T_284 = ~mtval_capture_inst_r; // @[dec_tlu_ctl.scala 1686:68] - wire _T_285 = _T_283 & _T_284; // @[dec_tlu_ctl.scala 1686:66] - wire _T_286 = ~mtval_capture_lsu_r; // @[dec_tlu_ctl.scala 1686:92] - wire _T_287 = _T_285 & _T_286; // @[dec_tlu_ctl.scala 1686:90] - wire _T_288 = ~io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1686:115] - wire mtval_clear_r = _T_287 & _T_288; // @[dec_tlu_ctl.scala 1686:113] + wire _T_268 = io_dec_csr_wraddr_r == 12'h343; // @[dec_tlu_ctl.scala 1663:69] + wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_268; // @[dec_tlu_ctl.scala 1663:40] + wire _T_269 = ~io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1664:83] + wire _T_270 = io_inst_acc_r & _T_269; // @[dec_tlu_ctl.scala 1664:81] + wire _T_271 = io_ebreak_r | _T_270; // @[dec_tlu_ctl.scala 1664:64] + wire _T_272 = _T_271 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1664:106] + wire _T_273 = io_exc_or_int_valid_r & _T_272; // @[dec_tlu_ctl.scala 1664:49] + wire mtval_capture_pc_r = _T_273 & _T_213; // @[dec_tlu_ctl.scala 1664:138] + wire _T_275 = io_inst_acc_r & io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1665:72] + wire _T_276 = io_exc_or_int_valid_r & _T_275; // @[dec_tlu_ctl.scala 1665:55] + wire mtval_capture_pc_plus2_r = _T_276 & _T_213; // @[dec_tlu_ctl.scala 1665:96] + wire _T_278 = io_exc_or_int_valid_r & io_illegal_r; // @[dec_tlu_ctl.scala 1666:51] + wire mtval_capture_inst_r = _T_278 & _T_213; // @[dec_tlu_ctl.scala 1666:66] + wire _T_280 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1667:50] + wire mtval_capture_lsu_r = _T_280 & _T_213; // @[dec_tlu_ctl.scala 1667:71] + wire _T_282 = ~mtval_capture_pc_r; // @[dec_tlu_ctl.scala 1668:46] + wire _T_283 = io_exc_or_int_valid_r & _T_282; // @[dec_tlu_ctl.scala 1668:44] + wire _T_284 = ~mtval_capture_inst_r; // @[dec_tlu_ctl.scala 1668:68] + wire _T_285 = _T_283 & _T_284; // @[dec_tlu_ctl.scala 1668:66] + wire _T_286 = ~mtval_capture_lsu_r; // @[dec_tlu_ctl.scala 1668:92] + wire _T_287 = _T_285 & _T_286; // @[dec_tlu_ctl.scala 1668:90] + wire _T_288 = ~io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1668:115] + wire mtval_clear_r = _T_287 & _T_288; // @[dec_tlu_ctl.scala 1668:113] wire [31:0] _T_290 = {pc_r,1'h0}; // @[Cat.scala 29:58] - wire [30:0] _T_293 = pc_r + 31'h1; // @[dec_tlu_ctl.scala 1691:83] + wire [30:0] _T_293 = pc_r + 31'h1; // @[dec_tlu_ctl.scala 1673:83] wire [31:0] _T_294 = {_T_293,1'h0}; // @[Cat.scala 29:58] - wire _T_297 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1694:18] - wire _T_298 = wr_mtval_r & _T_297; // @[dec_tlu_ctl.scala 1694:16] - wire _T_301 = ~wr_mtval_r; // @[dec_tlu_ctl.scala 1695:20] - wire _T_302 = _T_213 & _T_301; // @[dec_tlu_ctl.scala 1695:18] - wire _T_304 = _T_302 & _T_282; // @[dec_tlu_ctl.scala 1695:32] - wire _T_306 = _T_304 & _T_284; // @[dec_tlu_ctl.scala 1695:54] - wire _T_307 = ~mtval_clear_r; // @[dec_tlu_ctl.scala 1695:80] - wire _T_308 = _T_306 & _T_307; // @[dec_tlu_ctl.scala 1695:78] - wire _T_310 = _T_308 & _T_286; // @[dec_tlu_ctl.scala 1695:95] + wire _T_297 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1676:18] + wire _T_298 = wr_mtval_r & _T_297; // @[dec_tlu_ctl.scala 1676:16] + wire _T_301 = ~wr_mtval_r; // @[dec_tlu_ctl.scala 1677:20] + wire _T_302 = _T_213 & _T_301; // @[dec_tlu_ctl.scala 1677:18] + wire _T_304 = _T_302 & _T_282; // @[dec_tlu_ctl.scala 1677:32] + wire _T_306 = _T_304 & _T_284; // @[dec_tlu_ctl.scala 1677:54] + wire _T_307 = ~mtval_clear_r; // @[dec_tlu_ctl.scala 1677:80] + wire _T_308 = _T_306 & _T_307; // @[dec_tlu_ctl.scala 1677:78] + wire _T_310 = _T_308 & _T_286; // @[dec_tlu_ctl.scala 1677:95] wire [31:0] _T_312 = mtval_capture_pc_r ? _T_290 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_313 = mtval_capture_pc_plus2_r ? _T_294 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_314 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_315 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_316 = _T_298 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] - reg [31:0] mtval; // @[dec_tlu_ctl.scala 1697:46] + reg [31:0] mtval; // @[dec_tlu_ctl.scala 1679:46] wire [31:0] _T_317 = _T_310 ? mtval : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_318 = _T_312 | _T_313; // @[Mux.scala 27:72] wire [31:0] _T_319 = _T_318 | _T_314; // @[Mux.scala 27:72] wire [31:0] _T_320 = _T_319 | _T_315; // @[Mux.scala 27:72] wire [31:0] _T_321 = _T_320 | _T_316; // @[Mux.scala 27:72] - wire _T_325 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1712:68] + wire _T_325 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1694:68] reg [8:0] mcgc; // @[lib.scala 374:16] - wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1742:68] + wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1724:68] reg [14:0] mfdc_int; // @[lib.scala 374:16] - wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1751:20] - wire _T_344 = ~io_dec_csr_wrdata_r[6]; // @[dec_tlu_ctl.scala 1751:75] - wire [6:0] _T_346 = {_T_344,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] - wire [7:0] _T_347 = {_T_341,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58] - wire [2:0] _T_350 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1752:20] - wire _T_353 = ~mfdc_int[6]; // @[dec_tlu_ctl.scala 1752:63] - wire [18:0] mfdc = {_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] - wire _T_367 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1775:77] - wire _T_368 = io_dec_csr_wen_r_mod & _T_367; // @[dec_tlu_ctl.scala 1775:48] - wire _T_370 = _T_368 & _T_297; // @[dec_tlu_ctl.scala 1775:87] - wire _T_371 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1775:113] - wire _T_374 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1782:68] - wire _T_378 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1785:71] - wire _T_379 = io_dec_csr_wrdata_r[30] & _T_378; // @[dec_tlu_ctl.scala 1785:69] - wire _T_383 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1786:73] - wire _T_384 = io_dec_csr_wrdata_r[28] & _T_383; // @[dec_tlu_ctl.scala 1786:71] - wire _T_388 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1787:73] - wire _T_389 = io_dec_csr_wrdata_r[26] & _T_388; // @[dec_tlu_ctl.scala 1787:71] - wire _T_393 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1788:73] - wire _T_394 = io_dec_csr_wrdata_r[24] & _T_393; // @[dec_tlu_ctl.scala 1788:71] - wire _T_398 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1789:73] - wire _T_399 = io_dec_csr_wrdata_r[22] & _T_398; // @[dec_tlu_ctl.scala 1789:71] - wire _T_403 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1790:73] - wire _T_404 = io_dec_csr_wrdata_r[20] & _T_403; // @[dec_tlu_ctl.scala 1790:71] - wire _T_408 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1791:73] - wire _T_409 = io_dec_csr_wrdata_r[18] & _T_408; // @[dec_tlu_ctl.scala 1791:71] - wire _T_413 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1792:73] - wire _T_414 = io_dec_csr_wrdata_r[16] & _T_413; // @[dec_tlu_ctl.scala 1792:71] - wire _T_418 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1793:73] - wire _T_419 = io_dec_csr_wrdata_r[14] & _T_418; // @[dec_tlu_ctl.scala 1793:71] - wire _T_423 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1794:73] - wire _T_424 = io_dec_csr_wrdata_r[12] & _T_423; // @[dec_tlu_ctl.scala 1794:71] - wire _T_428 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1795:73] - wire _T_429 = io_dec_csr_wrdata_r[10] & _T_428; // @[dec_tlu_ctl.scala 1795:71] - wire _T_433 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1796:73] - wire _T_434 = io_dec_csr_wrdata_r[8] & _T_433; // @[dec_tlu_ctl.scala 1796:70] - wire _T_438 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1797:73] - wire _T_439 = io_dec_csr_wrdata_r[6] & _T_438; // @[dec_tlu_ctl.scala 1797:70] - wire _T_443 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1798:73] - wire _T_444 = io_dec_csr_wrdata_r[4] & _T_443; // @[dec_tlu_ctl.scala 1798:70] - wire _T_448 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1799:73] - wire _T_449 = io_dec_csr_wrdata_r[2] & _T_448; // @[dec_tlu_ctl.scala 1799:70] - wire _T_454 = io_dec_csr_wrdata_r[0] & _T_510; // @[dec_tlu_ctl.scala 1800:70] - wire [7:0] _T_461 = {io_dec_csr_wrdata_r[7],_T_439,io_dec_csr_wrdata_r[5],_T_444,io_dec_csr_wrdata_r[3],_T_449,io_dec_csr_wrdata_r[1],_T_454}; // @[Cat.scala 29:58] - wire [15:0] _T_469 = {io_dec_csr_wrdata_r[15],_T_419,io_dec_csr_wrdata_r[13],_T_424,io_dec_csr_wrdata_r[11],_T_429,io_dec_csr_wrdata_r[9],_T_434,_T_461}; // @[Cat.scala 29:58] - wire [7:0] _T_476 = {io_dec_csr_wrdata_r[23],_T_399,io_dec_csr_wrdata_r[21],_T_404,io_dec_csr_wrdata_r[19],_T_409,io_dec_csr_wrdata_r[17],_T_414}; // @[Cat.scala 29:58] - wire [15:0] _T_484 = {io_dec_csr_wrdata_r[31],_T_379,io_dec_csr_wrdata_r[29],_T_384,io_dec_csr_wrdata_r[27],_T_389,io_dec_csr_wrdata_r[25],_T_394,_T_476}; // @[Cat.scala 29:58] + wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1737:19] + wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1738:19] + wire [18:0] mfdc = {_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] + wire _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1757:77] + wire _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1757:48] + wire _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1757:87] + wire _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1757:113] + wire _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1764:68] + wire _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1767:71] + wire _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1767:69] + wire _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1768:73] + wire _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1768:71] + wire _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1769:73] + wire _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1769:71] + wire _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1770:73] + wire _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1770:71] + wire _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1771:73] + wire _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1771:71] + wire _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1772:73] + wire _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1772:71] + wire _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1773:73] + wire _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1773:71] + wire _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1774:73] + wire _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1774:71] + wire _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1775:73] + wire _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1775:71] + wire _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1776:73] + wire _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1776:71] + wire _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1777:73] + wire _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1777:71] + wire _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1778:73] + wire _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1778:70] + wire _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1779:73] + wire _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1779:70] + wire _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1780:73] + wire _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1780:70] + wire _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1781:73] + wire _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1781:70] + wire _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1782:70] + wire [7:0] _T_451 = {io_dec_csr_wrdata_r[7],_T_429,io_dec_csr_wrdata_r[5],_T_434,io_dec_csr_wrdata_r[3],_T_439,io_dec_csr_wrdata_r[1],_T_444}; // @[Cat.scala 29:58] + wire [15:0] _T_459 = {io_dec_csr_wrdata_r[15],_T_409,io_dec_csr_wrdata_r[13],_T_414,io_dec_csr_wrdata_r[11],_T_419,io_dec_csr_wrdata_r[9],_T_424,_T_451}; // @[Cat.scala 29:58] + wire [7:0] _T_466 = {io_dec_csr_wrdata_r[23],_T_389,io_dec_csr_wrdata_r[21],_T_394,io_dec_csr_wrdata_r[19],_T_399,io_dec_csr_wrdata_r[17],_T_404}; // @[Cat.scala 29:58] + wire [15:0] _T_474 = {io_dec_csr_wrdata_r[31],_T_369,io_dec_csr_wrdata_r[29],_T_374,io_dec_csr_wrdata_r[27],_T_379,io_dec_csr_wrdata_r[25],_T_384,_T_466}; // @[Cat.scala 29:58] reg [31:0] mrac; // @[lib.scala 374:16] - wire _T_487 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1813:69] - wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_487; // @[dec_tlu_ctl.scala 1813:40] - wire _T_488 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1823:59] - wire _T_489 = io_mdseac_locked_f & _T_488; // @[dec_tlu_ctl.scala 1823:57] - wire _T_491 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1825:49] - wire _T_492 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1825:86] - wire _T_493 = _T_491 & _T_492; // @[dec_tlu_ctl.scala 1825:84] - wire _T_494 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1825:111] - wire mdseac_en = _T_493 & _T_494; // @[dec_tlu_ctl.scala 1825:109] + wire _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1795:69] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1795:40] + wire _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1805:59] + wire _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1805:57] + wire _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1807:49] + wire _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1807:86] + wire _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1807:84] + wire _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1807:111] + wire mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1807:109] reg [31:0] mdseac; // @[lib.scala 374:16] - wire _T_500 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1840:30] - wire _T_501 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1840:57] - wire _T_502 = _T_500 & _T_501; // @[dec_tlu_ctl.scala 1840:55] - wire _T_503 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1840:89] - wire _T_516 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1858:48] - wire [4:0] csr_sat = _T_516 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1858:19] - wire _T_519 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1860:70] - wire wr_micect_r = io_dec_csr_wen_r_mod & _T_519; // @[dec_tlu_ctl.scala 1860:41] - wire [26:0] _T_520 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] - wire [31:0] _GEN_14 = {{5'd0}, _T_520}; // @[dec_tlu_ctl.scala 1861:23] - wire [31:0] _T_522 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1861:23] - wire [31:0] _T_525 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] - wire [26:0] micect_inc = _T_522[26:0]; // @[dec_tlu_ctl.scala 1861:13] - wire [31:0] _T_527 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] - wire _T_538 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1875:76] - wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_538; // @[dec_tlu_ctl.scala 1875:47] - wire _T_540 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1876:70] - wire [26:0] _T_541 = {26'h0,_T_540}; // @[Cat.scala 29:58] - wire [26:0] miccmect_inc = miccmect[26:0] + _T_541; // @[dec_tlu_ctl.scala 1876:33] - wire [31:0] _T_548 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] - wire _T_549 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1879:48] - wire _T_560 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1890:76] - wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_560; // @[dec_tlu_ctl.scala 1890:47] - wire [26:0] _T_562 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] - wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_562; // @[dec_tlu_ctl.scala 1891:33] - wire [31:0] _T_569 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] - wire _T_580 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1906:69] - wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_580; // @[dec_tlu_ctl.scala 1906:40] - reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1910:43] - wire _T_585 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1919:69] - wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_585; // @[dec_tlu_ctl.scala 1919:40] - wire _T_588 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1922:43] - wire _T_589 = io_dbg_tlu_halted & _T_588; // @[dec_tlu_ctl.scala 1922:41] - wire _T_591 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1922:78] - wire _T_592 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1922:98] - wire [1:0] _T_593 = {_T_591,_T_592}; // @[Cat.scala 29:58] + wire _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1822:30] + wire _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1822:57] + wire _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1822:55] + wire _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1822:89] + wire _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1840:48] + wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1840:19] + wire _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1842:70] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1842:41] + wire [26:0] _T_510 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] + wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1843:23] + wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1843:23] + wire [31:0] _T_515 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1843:13] + wire [31:0] _T_517 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1857:76] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1857:47] + wire _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1858:70] + wire [26:0] _T_531 = {26'h0,_T_530}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1858:33] + wire [31:0] _T_538 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1861:48] + wire _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1872:76] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1872:47] + wire [26:0] _T_552 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1873:33] + wire [31:0] _T_559 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1888:69] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1888:40] + reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1892:43] + wire _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1901:69] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1901:40] + wire _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1904:43] + wire _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1904:41] + wire _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1904:78] + wire _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1904:98] + wire [1:0] _T_583 = {_T_581,_T_582}; // @[Cat.scala 29:58] reg [1:0] mfdhs; // @[Reg.scala 27:20] - wire _T_595 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1924:71] + wire _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1906:71] reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] - wire [31:0] _T_600 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1926:74] - wire [62:0] _T_607 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1931:71] - wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1931:48] - wire [62:0] _T_608 = _GEN_15 & _T_607; // @[dec_tlu_ctl.scala 1931:48] - wire _T_609 = |_T_608; // @[dec_tlu_ctl.scala 1931:87] - wire _T_612 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1939:69] + wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1908:74] + wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1913:71] + wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1913:48] + wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1913:48] + wire _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1913:87] + wire _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1921:69] reg [21:0] meivt; // @[lib.scala 374:16] - wire _T_631 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1990:69] - wire _T_632 = io_dec_csr_wen_r_mod & _T_631; // @[dec_tlu_ctl.scala 1990:40] - wire wr_meicpct_r = _T_632 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1990:83] + wire _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1972:69] + wire _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1972:40] + wire wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1972:83] reg [7:0] meihap; // @[lib.scala 374:16] - wire _T_618 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1963:72] - wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_618; // @[dec_tlu_ctl.scala 1963:43] - reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1966:46] - wire _T_623 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1978:73] - wire _T_624 = io_dec_csr_wen_r_mod & _T_623; // @[dec_tlu_ctl.scala 1978:44] - wire wr_meicidpl_r = _T_624 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1978:88] - reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1983:44] - wire _T_635 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 1999:69] - wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_635; // @[dec_tlu_ctl.scala 1999:40] - reg [3:0] meipt; // @[dec_tlu_ctl.scala 2002:43] - wire _T_639 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2030:89] - wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_639; // @[dec_tlu_ctl.scala 2030:66] - wire _T_640 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2033:31] - wire _T_641 = io_dcsr_single_step_done_f & _T_640; // @[dec_tlu_ctl.scala 2033:29] - wire _T_642 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2033:63] - wire _T_643 = _T_641 & _T_642; // @[dec_tlu_ctl.scala 2033:61] - wire _T_644 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2033:98] - wire _T_645 = _T_643 & _T_644; // @[dec_tlu_ctl.scala 2033:96] - wire _T_648 = io_debug_halt_req & _T_640; // @[dec_tlu_ctl.scala 2034:46] - wire _T_650 = _T_648 & _T_642; // @[dec_tlu_ctl.scala 2034:78] - wire _T_653 = io_ebreak_to_debug_mode_r_d1 & _T_642; // @[dec_tlu_ctl.scala 2035:75] - wire [2:0] _T_656 = _T_645 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_657 = _T_650 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_658 = _T_653 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_659 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_660 = _T_656 | _T_657; // @[Mux.scala 27:72] - wire [2:0] _T_661 = _T_660 | _T_658; // @[Mux.scala 27:72] - wire [2:0] dcsr_cause = _T_661 | _T_659; // @[Mux.scala 27:72] - wire _T_663 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2038:46] - wire _T_665 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2038:98] - wire wr_dcsr_r = _T_663 & _T_665; // @[dec_tlu_ctl.scala 2038:69] - wire _T_667 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2044:75] - wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_667; // @[dec_tlu_ctl.scala 2044:59] - wire _T_668 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2045:59] - wire _T_669 = _T_668 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2045:78] - wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_669; // @[dec_tlu_ctl.scala 2045:56] - wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2047:48] - wire [15:0] _T_675 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] - wire _T_681 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2049:145] - wire [15:0] _T_690 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_681,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] - wire [15:0] _T_695 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] - wire _T_697 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2051:54] - wire _T_698 = _T_697 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2051:66] - reg [15:0] _T_701; // @[lib.scala 374:16] - wire _T_704 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2059:97] - wire wr_dpc_r = _T_663 & _T_704; // @[dec_tlu_ctl.scala 2059:68] - wire _T_707 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2060:67] - wire dpc_capture_npc = _T_589 & _T_707; // @[dec_tlu_ctl.scala 2060:65] - wire _T_708 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2064:21] - wire _T_709 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2064:39] - wire _T_710 = _T_708 & _T_709; // @[dec_tlu_ctl.scala 2064:37] - wire _T_711 = _T_710 & wr_dpc_r; // @[dec_tlu_ctl.scala 2064:56] - wire _T_716 = _T_708 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2066:49] - wire [30:0] _T_718 = _T_711 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_719 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_720 = _T_716 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_721 = _T_718 | _T_719; // @[Mux.scala 27:72] - wire _T_723 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2068:36] - reg [30:0] _T_726; // @[lib.scala 374:16] - wire [2:0] _T_730 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] - wire _T_733 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2083:102] + wire _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1945:72] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1945:43] + reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1948:46] + wire _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1960:73] + wire _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1960:44] + wire wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1960:88] + reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1965:44] + wire _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 1981:69] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 1981:40] + reg [3:0] meipt; // @[dec_tlu_ctl.scala 1984:43] + wire _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2012:89] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2012:66] + wire _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2015:31] + wire _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2015:29] + wire _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2015:63] + wire _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2015:61] + wire _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2015:98] + wire _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2015:96] + wire _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2016:46] + wire _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2016:78] + wire _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2017:75] + wire [2:0] _T_646 = _T_635 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_647 = _T_640 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_648 = _T_643 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_649 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_650 = _T_646 | _T_647; // @[Mux.scala 27:72] + wire [2:0] _T_651 = _T_650 | _T_648; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_651 | _T_649; // @[Mux.scala 27:72] + wire _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2020:46] + wire _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2020:98] + wire wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2020:69] + wire _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2026:75] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2026:59] + wire _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2027:59] + wire _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2027:78] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2027:56] + wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2029:48] + wire [15:0] _T_665 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2031:145] + wire [15:0] _T_680 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_671,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_685 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2033:54] + wire _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2033:66] + reg [15:0] _T_691; // @[lib.scala 374:16] + wire _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2041:97] + wire wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2041:68] + wire _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2042:67] + wire dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2042:65] + wire _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2046:21] + wire _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2046:39] + wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2046:37] + wire _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2046:56] + wire _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2048:49] + wire [30:0] _T_708 = _T_701 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_709 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_710 = _T_706 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_711 = _T_708 | _T_709; // @[Mux.scala 27:72] + wire _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2050:36] + reg [30:0] _T_716; // @[lib.scala 374:16] + wire [2:0] _T_720 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] + wire _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2065:102] reg [16:0] dicawics; // @[lib.scala 374:16] - wire _T_737 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2101:100] - wire wr_dicad0_r = _T_663 & _T_737; // @[dec_tlu_ctl.scala 2101:71] + wire _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2083:100] + wire wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2083:71] reg [70:0] dicad0; // @[lib.scala 374:16] - wire _T_743 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2114:101] - wire wr_dicad0h_r = _T_663 & _T_743; // @[dec_tlu_ctl.scala 2114:72] + wire _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2096:101] + wire wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2096:72] reg [31:0] dicad0h; // @[lib.scala 374:16] - wire _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2126:100] - wire _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2126:71] - wire [31:0] _T_755 = _T_752 ? io_dec_csr_wrdata_r : {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; // @[dec_tlu_ctl.scala 2128:21] - wire _T_756 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2131:78] - reg [31:0] _T_758; // @[Reg.scala 27:20] - wire [31:0] dicad1 = {25'h0,_T_758[6:0]}; // @[Cat.scala 29:58] - wire [38:0] _T_763 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] - wire _T_765 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2159:52] - wire _T_766 = _T_765 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2159:75] - wire _T_767 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2159:98] - wire _T_768 = _T_766 & _T_767; // @[dec_tlu_ctl.scala 2159:96] - wire _T_770 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2159:149] - wire _T_773 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2160:104] - reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2162:58] - reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2163:58] - wire _T_775 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2174:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_775; // @[dec_tlu_ctl.scala 2174:40] - reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2177:43] - wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2212:42] - wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2214:44] - wire _T_786 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2216:46] - wire tdata_action = _T_786 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2216:69] - wire [9:0] tdata_wrdata_r = {_T_786,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_801 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2222:99] - wire _T_802 = io_dec_csr_wen_r_mod & _T_801; // @[dec_tlu_ctl.scala 2222:70] - wire _T_803 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2222:121] - wire _T_804 = _T_802 & _T_803; // @[dec_tlu_ctl.scala 2222:112] - wire _T_806 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_0 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2222:135] - wire _T_812 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2222:121] - wire _T_813 = _T_802 & _T_812; // @[dec_tlu_ctl.scala 2222:112] - wire _T_815 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_1 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2222:135] - wire _T_821 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2222:121] - wire _T_822 = _T_802 & _T_821; // @[dec_tlu_ctl.scala 2222:112] - wire _T_824 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_2 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2222:135] - wire _T_830 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2222:121] - wire _T_831 = _T_802 & _T_830; // @[dec_tlu_ctl.scala 2222:112] - wire _T_833 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_834 = _T_833 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_3 = _T_831 & _T_834; // @[dec_tlu_ctl.scala 2222:135] - wire _T_840 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_843 = {io_mtdata1_t_0[9],_T_840,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_849 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_852 = {io_mtdata1_t_1[9],_T_849,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_858 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_861 = {io_mtdata1_t_2[9],_T_858,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_867 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_870 = {io_mtdata1_t_3[9],_T_867,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_872; // @[dec_tlu_ctl.scala 2225:74] - reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2225:74] - reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2225:74] - reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2225:74] - wire [31:0] _T_890 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_905 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_920 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_935 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_936 = _T_803 ? _T_890 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_937 = _T_812 ? _T_905 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_938 = _T_821 ? _T_920 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_939 = _T_830 ? _T_935 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_940 = _T_936 | _T_937; // @[Mux.scala 27:72] - wire [31:0] _T_941 = _T_940 | _T_938; // @[Mux.scala 27:72] - wire [31:0] mtdata1_tsel_out = _T_941 | _T_939; // @[Mux.scala 27:72] - wire _T_968 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2242:98] - wire _T_969 = io_dec_csr_wen_r_mod & _T_968; // @[dec_tlu_ctl.scala 2242:69] - wire _T_971 = _T_969 & _T_803; // @[dec_tlu_ctl.scala 2242:111] - wire _T_980 = _T_969 & _T_812; // @[dec_tlu_ctl.scala 2242:111] - wire _T_989 = _T_969 & _T_821; // @[dec_tlu_ctl.scala 2242:111] - wire _T_998 = _T_969 & _T_830; // @[dec_tlu_ctl.scala 2242:111] + wire _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2108:100] + wire _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2108:71] + wire [31:0] _T_745 = _T_742 ? io_dec_csr_wrdata_r : {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; // @[dec_tlu_ctl.scala 2110:21] + wire _T_746 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2113:78] + reg [31:0] _T_748; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_748[6:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_753 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_755 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2141:52] + wire _T_756 = _T_755 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2141:75] + wire _T_757 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2141:98] + wire _T_758 = _T_756 & _T_757; // @[dec_tlu_ctl.scala 2141:96] + wire _T_760 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2141:149] + wire _T_763 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2142:104] + reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2144:58] + reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2145:58] + wire _T_765 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2156:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_765; // @[dec_tlu_ctl.scala 2156:40] + reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2159:43] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2194:42] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2196:44] + wire _T_776 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2198:46] + wire tdata_action = _T_776 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2198:69] + wire [9:0] tdata_wrdata_r = {_T_776,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_791 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2204:99] + wire _T_792 = io_dec_csr_wen_r_mod & _T_791; // @[dec_tlu_ctl.scala 2204:70] + wire _T_793 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2204:121] + wire _T_794 = _T_792 & _T_793; // @[dec_tlu_ctl.scala 2204:112] + wire _T_796 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_797 = _T_796 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_0 = _T_794 & _T_797; // @[dec_tlu_ctl.scala 2204:135] + wire _T_802 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2204:121] + wire _T_803 = _T_792 & _T_802; // @[dec_tlu_ctl.scala 2204:112] + wire _T_805 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_806 = _T_805 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_1 = _T_803 & _T_806; // @[dec_tlu_ctl.scala 2204:135] + wire _T_811 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2204:121] + wire _T_812 = _T_792 & _T_811; // @[dec_tlu_ctl.scala 2204:112] + wire _T_814 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_815 = _T_814 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_2 = _T_812 & _T_815; // @[dec_tlu_ctl.scala 2204:135] + wire _T_820 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2204:121] + wire _T_821 = _T_792 & _T_820; // @[dec_tlu_ctl.scala 2204:112] + wire _T_823 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_824 = _T_823 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_3 = _T_821 & _T_824; // @[dec_tlu_ctl.scala 2204:135] + wire _T_830 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_833 = {io_mtdata1_t_0[9],_T_830,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_839 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_842 = {io_mtdata1_t_1[9],_T_839,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_848 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_851 = {io_mtdata1_t_2[9],_T_848,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_857 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_860 = {io_mtdata1_t_3[9],_T_857,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_862; // @[dec_tlu_ctl.scala 2207:74] + reg [9:0] _T_863; // @[dec_tlu_ctl.scala 2207:74] + reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2207:74] + reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2207:74] + wire [31:0] _T_880 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_895 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_910 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_925 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_926 = _T_793 ? _T_880 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_927 = _T_802 ? _T_895 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_928 = _T_811 ? _T_910 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_929 = _T_820 ? _T_925 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_930 = _T_926 | _T_927; // @[Mux.scala 27:72] + wire [31:0] _T_931 = _T_930 | _T_928; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_931 | _T_929; // @[Mux.scala 27:72] + wire _T_958 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2224:98] + wire _T_959 = io_dec_csr_wen_r_mod & _T_958; // @[dec_tlu_ctl.scala 2224:69] + wire _T_961 = _T_959 & _T_793; // @[dec_tlu_ctl.scala 2224:111] + wire _T_970 = _T_959 & _T_802; // @[dec_tlu_ctl.scala 2224:111] + wire _T_979 = _T_959 & _T_811; // @[dec_tlu_ctl.scala 2224:111] + wire _T_988 = _T_959 & _T_820; // @[dec_tlu_ctl.scala 2224:111] reg [31:0] mtdata2_t_0; // @[lib.scala 374:16] reg [31:0] mtdata2_t_1; // @[lib.scala 374:16] reg [31:0] mtdata2_t_2; // @[lib.scala 374:16] reg [31:0] mtdata2_t_3; // @[lib.scala 374:16] - wire [31:0] _T_1015 = _T_803 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1016 = _T_812 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1017 = _T_821 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1018 = _T_830 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1019 = _T_1015 | _T_1016; // @[Mux.scala 27:72] - wire [31:0] _T_1020 = _T_1019 | _T_1017; // @[Mux.scala 27:72] - wire [31:0] mtdata2_tsel_out = _T_1020 | _T_1018; // @[Mux.scala 27:72] - wire [3:0] _T_1023 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1023; // @[dec_tlu_ctl.scala 2267:59] - wire _T_1025 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2273:24] + wire [31:0] _T_1005 = _T_793 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1006 = _T_802 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1007 = _T_811 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1008 = _T_820 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1009 = _T_1005 | _T_1006; // @[Mux.scala 27:72] + wire [31:0] _T_1010 = _T_1009 | _T_1007; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1010 | _T_1008; // @[Mux.scala 27:72] + wire [3:0] _T_1013 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1013; // @[dec_tlu_ctl.scala 2249:59] + wire _T_1015 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1026 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1028 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1030 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1032 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1034 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2277:96] - wire _T_1035 = io_tlu_i0_commit_cmt & _T_1034; // @[dec_tlu_ctl.scala 2277:94] - wire _T_1036 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1038 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:96] - wire _T_1039 = io_tlu_i0_commit_cmt & _T_1038; // @[dec_tlu_ctl.scala 2278:94] - wire _T_1041 = _T_1039 & _T_1034; // @[dec_tlu_ctl.scala 2278:115] - wire _T_1042 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1044 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:94] - wire _T_1046 = _T_1044 & _T_1034; // @[dec_tlu_ctl.scala 2279:115] - wire _T_1047 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1049 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1051 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1053 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1055 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2283:91] - wire _T_1056 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1058 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2284:105] - wire _T_1059 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1061 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2285:91] - wire _T_1062 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1064 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2286:91] - wire _T_1065 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1068 = _T_1061 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:100] - wire _T_1069 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1073 = _T_1064 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:101] - wire _T_1074 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1076 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2289:89] - wire _T_1077 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1079 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2290:89] - wire _T_1080 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1082 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2291:89] - wire _T_1083 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1085 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2292:89] - wire _T_1086 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1088 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2293:89] - wire _T_1089 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1091 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2294:89] - wire _T_1092 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1094 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2295:89] - wire _T_1095 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1097 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2296:89] - wire _T_1098 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1100 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2297:89] - wire _T_1101 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1103 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2298:89] - wire _T_1104 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2298:122] - wire _T_1105 = _T_1103 | _T_1104; // @[dec_tlu_ctl.scala 2298:101] - wire _T_1106 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1108 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:95] - wire _T_1109 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1111 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:97] - wire _T_1112 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1114 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:110] - wire _T_1115 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1119 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1121 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1123 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1125 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1127 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1129 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1131 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2309:98] - wire _T_1132 = _T_1131 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2309:120] - wire _T_1133 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1135 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2310:92] - wire _T_1136 = _T_1135 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2310:117] - wire _T_1137 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1139 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1141 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1143 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2313:97] - wire _T_1144 = _T_1143 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2313:129] - wire _T_1145 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1147 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1149 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1151 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1153 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1155 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1157 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1159 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1163 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2321:73] - wire _T_1164 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire [5:0] _T_1171 = io_mip & mie; // @[dec_tlu_ctl.scala 2322:113] - wire _T_1172 = |_T_1171; // @[dec_tlu_ctl.scala 2322:125] - wire _T_1173 = _T_1163 & _T_1172; // @[dec_tlu_ctl.scala 2322:98] - wire _T_1174 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2323:91] - wire _T_1177 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2324:94] - wire _T_1180 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2325:94] - wire _T_1183 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1185 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1187 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1189 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1191 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1194 = _T_1028 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1195 = _T_1030 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1196 = _T_1032 & _T_1035; // @[Mux.scala 27:72] - wire _T_1197 = _T_1036 & _T_1041; // @[Mux.scala 27:72] - wire _T_1198 = _T_1042 & _T_1046; // @[Mux.scala 27:72] - wire _T_1199 = _T_1047 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1200 = _T_1049 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1201 = _T_1051 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1202 = _T_1053 & _T_1055; // @[Mux.scala 27:72] - wire _T_1203 = _T_1056 & _T_1058; // @[Mux.scala 27:72] - wire _T_1204 = _T_1059 & _T_1061; // @[Mux.scala 27:72] - wire _T_1205 = _T_1062 & _T_1064; // @[Mux.scala 27:72] - wire _T_1206 = _T_1065 & _T_1068; // @[Mux.scala 27:72] - wire _T_1207 = _T_1069 & _T_1073; // @[Mux.scala 27:72] - wire _T_1208 = _T_1074 & _T_1076; // @[Mux.scala 27:72] - wire _T_1209 = _T_1077 & _T_1079; // @[Mux.scala 27:72] - wire _T_1210 = _T_1080 & _T_1082; // @[Mux.scala 27:72] - wire _T_1211 = _T_1083 & _T_1085; // @[Mux.scala 27:72] - wire _T_1212 = _T_1086 & _T_1088; // @[Mux.scala 27:72] - wire _T_1213 = _T_1089 & _T_1091; // @[Mux.scala 27:72] - wire _T_1214 = _T_1092 & _T_1094; // @[Mux.scala 27:72] - wire _T_1215 = _T_1095 & _T_1097; // @[Mux.scala 27:72] - wire _T_1216 = _T_1098 & _T_1100; // @[Mux.scala 27:72] - wire _T_1217 = _T_1101 & _T_1105; // @[Mux.scala 27:72] - wire _T_1218 = _T_1106 & _T_1108; // @[Mux.scala 27:72] - wire _T_1219 = _T_1109 & _T_1111; // @[Mux.scala 27:72] - wire _T_1220 = _T_1112 & _T_1114; // @[Mux.scala 27:72] - wire _T_1221 = _T_1115 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1223 = _T_1119 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1224 = _T_1121 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1225 = _T_1123 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1226 = _T_1125 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1227 = _T_1127 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1228 = _T_1129 & _T_1132; // @[Mux.scala 27:72] - wire _T_1229 = _T_1133 & _T_1136; // @[Mux.scala 27:72] - wire _T_1230 = _T_1137 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1231 = _T_1139 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1232 = _T_1141 & _T_1144; // @[Mux.scala 27:72] - wire _T_1233 = _T_1145 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1234 = _T_1147 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1235 = _T_1149 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1236 = _T_1151 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1237 = _T_1153 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1238 = _T_1155 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1239 = _T_1157 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1240 = _T_1159 & _T_1163; // @[Mux.scala 27:72] - wire _T_1241 = _T_1164 & _T_1173; // @[Mux.scala 27:72] - wire _T_1242 = _T_1174 & _T_1176; // @[Mux.scala 27:72] - wire _T_1243 = _T_1177 & _T_1179; // @[Mux.scala 27:72] - wire _T_1244 = _T_1180 & _T_1182; // @[Mux.scala 27:72] - wire _T_1245 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1246 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1247 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1248 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1249 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1250 = _T_1026 | _T_1194; // @[Mux.scala 27:72] + wire _T_1016 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1018 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1020 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1022 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1024 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2259:96] + wire _T_1025 = io_tlu_i0_commit_cmt & _T_1024; // @[dec_tlu_ctl.scala 2259:94] + wire _T_1026 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1028 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2260:96] + wire _T_1029 = io_tlu_i0_commit_cmt & _T_1028; // @[dec_tlu_ctl.scala 2260:94] + wire _T_1031 = _T_1029 & _T_1024; // @[dec_tlu_ctl.scala 2260:115] + wire _T_1032 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1034 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2261:94] + wire _T_1036 = _T_1034 & _T_1024; // @[dec_tlu_ctl.scala 2261:115] + wire _T_1037 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1039 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1041 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1043 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1045 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2265:91] + wire _T_1046 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1048 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2266:105] + wire _T_1049 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1051 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2267:91] + wire _T_1052 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1054 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2268:91] + wire _T_1055 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1058 = _T_1051 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2269:100] + wire _T_1059 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1063 = _T_1054 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2270:101] + wire _T_1064 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1066 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2271:89] + wire _T_1067 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1069 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2272:89] + wire _T_1070 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1072 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2273:89] + wire _T_1073 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1075 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2274:89] + wire _T_1076 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1078 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2275:89] + wire _T_1079 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1081 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2276:89] + wire _T_1082 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1084 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2277:89] + wire _T_1085 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1087 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2278:89] + wire _T_1088 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1090 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2279:89] + wire _T_1091 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1093 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2280:89] + wire _T_1094 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2280:122] + wire _T_1095 = _T_1093 | _T_1094; // @[dec_tlu_ctl.scala 2280:101] + wire _T_1096 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1098 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2281:95] + wire _T_1099 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1101 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2282:97] + wire _T_1102 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1104 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2283:110] + wire _T_1105 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1109 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1111 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1113 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1115 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1117 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1119 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1121 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2291:98] + wire _T_1122 = _T_1121 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2291:120] + wire _T_1123 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1125 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2292:92] + wire _T_1126 = _T_1125 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2292:117] + wire _T_1127 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1129 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1131 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1133 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2295:97] + wire _T_1134 = _T_1133 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2295:129] + wire _T_1135 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1137 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1139 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1141 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1143 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1145 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1147 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1149 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1153 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2303:73] + wire _T_1154 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire [5:0] _T_1161 = io_mip & mie; // @[dec_tlu_ctl.scala 2304:113] + wire _T_1162 = |_T_1161; // @[dec_tlu_ctl.scala 2304:125] + wire _T_1163 = _T_1153 & _T_1162; // @[dec_tlu_ctl.scala 2304:98] + wire _T_1164 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1166 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2305:91] + wire _T_1167 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1169 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2306:94] + wire _T_1170 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1172 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2307:94] + wire _T_1173 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1175 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1177 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1179 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1181 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1184 = _T_1018 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1185 = _T_1020 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1186 = _T_1022 & _T_1025; // @[Mux.scala 27:72] + wire _T_1187 = _T_1026 & _T_1031; // @[Mux.scala 27:72] + wire _T_1188 = _T_1032 & _T_1036; // @[Mux.scala 27:72] + wire _T_1189 = _T_1037 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1190 = _T_1039 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1191 = _T_1041 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1192 = _T_1043 & _T_1045; // @[Mux.scala 27:72] + wire _T_1193 = _T_1046 & _T_1048; // @[Mux.scala 27:72] + wire _T_1194 = _T_1049 & _T_1051; // @[Mux.scala 27:72] + wire _T_1195 = _T_1052 & _T_1054; // @[Mux.scala 27:72] + wire _T_1196 = _T_1055 & _T_1058; // @[Mux.scala 27:72] + wire _T_1197 = _T_1059 & _T_1063; // @[Mux.scala 27:72] + wire _T_1198 = _T_1064 & _T_1066; // @[Mux.scala 27:72] + wire _T_1199 = _T_1067 & _T_1069; // @[Mux.scala 27:72] + wire _T_1200 = _T_1070 & _T_1072; // @[Mux.scala 27:72] + wire _T_1201 = _T_1073 & _T_1075; // @[Mux.scala 27:72] + wire _T_1202 = _T_1076 & _T_1078; // @[Mux.scala 27:72] + wire _T_1203 = _T_1079 & _T_1081; // @[Mux.scala 27:72] + wire _T_1204 = _T_1082 & _T_1084; // @[Mux.scala 27:72] + wire _T_1205 = _T_1085 & _T_1087; // @[Mux.scala 27:72] + wire _T_1206 = _T_1088 & _T_1090; // @[Mux.scala 27:72] + wire _T_1207 = _T_1091 & _T_1095; // @[Mux.scala 27:72] + wire _T_1208 = _T_1096 & _T_1098; // @[Mux.scala 27:72] + wire _T_1209 = _T_1099 & _T_1101; // @[Mux.scala 27:72] + wire _T_1210 = _T_1102 & _T_1104; // @[Mux.scala 27:72] + wire _T_1211 = _T_1105 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1213 = _T_1109 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1214 = _T_1111 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1215 = _T_1113 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1216 = _T_1115 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1217 = _T_1117 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1218 = _T_1119 & _T_1122; // @[Mux.scala 27:72] + wire _T_1219 = _T_1123 & _T_1126; // @[Mux.scala 27:72] + wire _T_1220 = _T_1127 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1221 = _T_1129 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1222 = _T_1131 & _T_1134; // @[Mux.scala 27:72] + wire _T_1223 = _T_1135 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1224 = _T_1137 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1225 = _T_1139 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1226 = _T_1141 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1227 = _T_1143 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1228 = _T_1145 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1229 = _T_1147 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1230 = _T_1149 & _T_1153; // @[Mux.scala 27:72] + wire _T_1231 = _T_1154 & _T_1163; // @[Mux.scala 27:72] + wire _T_1232 = _T_1164 & _T_1166; // @[Mux.scala 27:72] + wire _T_1233 = _T_1167 & _T_1169; // @[Mux.scala 27:72] + wire _T_1234 = _T_1170 & _T_1172; // @[Mux.scala 27:72] + wire _T_1235 = _T_1173 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1236 = _T_1175 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1237 = _T_1177 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1238 = _T_1179 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1239 = _T_1181 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1240 = _T_1016 | _T_1184; // @[Mux.scala 27:72] + wire _T_1241 = _T_1240 | _T_1185; // @[Mux.scala 27:72] + wire _T_1242 = _T_1241 | _T_1186; // @[Mux.scala 27:72] + wire _T_1243 = _T_1242 | _T_1187; // @[Mux.scala 27:72] + wire _T_1244 = _T_1243 | _T_1188; // @[Mux.scala 27:72] + wire _T_1245 = _T_1244 | _T_1189; // @[Mux.scala 27:72] + wire _T_1246 = _T_1245 | _T_1190; // @[Mux.scala 27:72] + wire _T_1247 = _T_1246 | _T_1191; // @[Mux.scala 27:72] + wire _T_1248 = _T_1247 | _T_1192; // @[Mux.scala 27:72] + wire _T_1249 = _T_1248 | _T_1193; // @[Mux.scala 27:72] + wire _T_1250 = _T_1249 | _T_1194; // @[Mux.scala 27:72] wire _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72] wire _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72] wire _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72] @@ -51616,7 +51615,7 @@ module csr_tlu( wire _T_1265 = _T_1264 | _T_1209; // @[Mux.scala 27:72] wire _T_1266 = _T_1265 | _T_1210; // @[Mux.scala 27:72] wire _T_1267 = _T_1266 | _T_1211; // @[Mux.scala 27:72] - wire _T_1268 = _T_1267 | _T_1212; // @[Mux.scala 27:72] + wire _T_1268 = _T_1267 | _T_1191; // @[Mux.scala 27:72] wire _T_1269 = _T_1268 | _T_1213; // @[Mux.scala 27:72] wire _T_1270 = _T_1269 | _T_1214; // @[Mux.scala 27:72] wire _T_1271 = _T_1270 | _T_1215; // @[Mux.scala 27:72] @@ -51626,7 +51625,7 @@ module csr_tlu( wire _T_1275 = _T_1274 | _T_1219; // @[Mux.scala 27:72] wire _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72] wire _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72] - wire _T_1278 = _T_1277 | _T_1201; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72] wire _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72] wire _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72] wire _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72] @@ -51644,131 +51643,131 @@ module csr_tlu( wire _T_1293 = _T_1292 | _T_1237; // @[Mux.scala 27:72] wire _T_1294 = _T_1293 | _T_1238; // @[Mux.scala 27:72] wire _T_1295 = _T_1294 | _T_1239; // @[Mux.scala 27:72] - wire _T_1296 = _T_1295 | _T_1240; // @[Mux.scala 27:72] - wire _T_1297 = _T_1296 | _T_1241; // @[Mux.scala 27:72] - wire _T_1298 = _T_1297 | _T_1242; // @[Mux.scala 27:72] - wire _T_1299 = _T_1298 | _T_1243; // @[Mux.scala 27:72] - wire _T_1300 = _T_1299 | _T_1244; // @[Mux.scala 27:72] - wire _T_1301 = _T_1300 | _T_1245; // @[Mux.scala 27:72] - wire _T_1302 = _T_1301 | _T_1246; // @[Mux.scala 27:72] - wire _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72] - wire _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72] - wire _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1025 & _T_1305; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1309 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2273:24] + wire mhpmc_inc_r_0 = _T_1015 & _T_1295; // @[dec_tlu_ctl.scala 2255:44] + wire _T_1299 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1310 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1312 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1314 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1316 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1320 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1326 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1331 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1333 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1335 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1337 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1340 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1343 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1346 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1349 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1353 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1358 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1361 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1364 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1367 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1370 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1373 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1376 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1379 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1382 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1385 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1390 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1393 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1396 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1399 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1403 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1405 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1407 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1409 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1411 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1413 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1417 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1421 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1423 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1425 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1429 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1431 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1433 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1435 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1437 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1439 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1441 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1443 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1448 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1458 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1461 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1464 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1467 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1469 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1471 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1473 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1475 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1478 = _T_1312 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1479 = _T_1314 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1480 = _T_1316 & _T_1035; // @[Mux.scala 27:72] - wire _T_1481 = _T_1320 & _T_1041; // @[Mux.scala 27:72] - wire _T_1482 = _T_1326 & _T_1046; // @[Mux.scala 27:72] - wire _T_1483 = _T_1331 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1484 = _T_1333 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1485 = _T_1335 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1486 = _T_1337 & _T_1055; // @[Mux.scala 27:72] - wire _T_1487 = _T_1340 & _T_1058; // @[Mux.scala 27:72] - wire _T_1488 = _T_1343 & _T_1061; // @[Mux.scala 27:72] - wire _T_1489 = _T_1346 & _T_1064; // @[Mux.scala 27:72] - wire _T_1490 = _T_1349 & _T_1068; // @[Mux.scala 27:72] - wire _T_1491 = _T_1353 & _T_1073; // @[Mux.scala 27:72] - wire _T_1492 = _T_1358 & _T_1076; // @[Mux.scala 27:72] - wire _T_1493 = _T_1361 & _T_1079; // @[Mux.scala 27:72] - wire _T_1494 = _T_1364 & _T_1082; // @[Mux.scala 27:72] - wire _T_1495 = _T_1367 & _T_1085; // @[Mux.scala 27:72] - wire _T_1496 = _T_1370 & _T_1088; // @[Mux.scala 27:72] - wire _T_1497 = _T_1373 & _T_1091; // @[Mux.scala 27:72] - wire _T_1498 = _T_1376 & _T_1094; // @[Mux.scala 27:72] - wire _T_1499 = _T_1379 & _T_1097; // @[Mux.scala 27:72] - wire _T_1500 = _T_1382 & _T_1100; // @[Mux.scala 27:72] - wire _T_1501 = _T_1385 & _T_1105; // @[Mux.scala 27:72] - wire _T_1502 = _T_1390 & _T_1108; // @[Mux.scala 27:72] - wire _T_1503 = _T_1393 & _T_1111; // @[Mux.scala 27:72] - wire _T_1504 = _T_1396 & _T_1114; // @[Mux.scala 27:72] - wire _T_1505 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1507 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1508 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1509 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1510 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1511 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1512 = _T_1413 & _T_1132; // @[Mux.scala 27:72] - wire _T_1513 = _T_1417 & _T_1136; // @[Mux.scala 27:72] - wire _T_1514 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1515 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1516 = _T_1425 & _T_1144; // @[Mux.scala 27:72] - wire _T_1517 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1518 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1519 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1520 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1521 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1522 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1523 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1524 = _T_1443 & _T_1163; // @[Mux.scala 27:72] - wire _T_1525 = _T_1448 & _T_1173; // @[Mux.scala 27:72] - wire _T_1526 = _T_1458 & _T_1176; // @[Mux.scala 27:72] - wire _T_1527 = _T_1461 & _T_1179; // @[Mux.scala 27:72] - wire _T_1528 = _T_1464 & _T_1182; // @[Mux.scala 27:72] - wire _T_1529 = _T_1467 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1530 = _T_1469 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1531 = _T_1471 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1532 = _T_1473 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1533 = _T_1475 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1534 = _T_1310 | _T_1478; // @[Mux.scala 27:72] + wire _T_1300 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1302 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1304 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1306 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1310 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1316 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1321 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1323 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1325 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1327 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1330 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1333 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1336 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1339 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1343 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1348 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1351 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1354 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1357 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1360 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1363 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1366 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1369 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1372 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1375 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1380 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1383 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1386 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1389 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1393 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1395 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1397 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1399 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1401 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1403 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1407 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1411 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1413 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1415 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1419 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1421 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1423 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1425 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1427 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1429 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1431 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1433 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1438 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1448 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1451 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1454 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1457 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1459 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1461 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1463 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1465 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1468 = _T_1302 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1469 = _T_1304 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1470 = _T_1306 & _T_1025; // @[Mux.scala 27:72] + wire _T_1471 = _T_1310 & _T_1031; // @[Mux.scala 27:72] + wire _T_1472 = _T_1316 & _T_1036; // @[Mux.scala 27:72] + wire _T_1473 = _T_1321 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1474 = _T_1323 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1475 = _T_1325 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1476 = _T_1327 & _T_1045; // @[Mux.scala 27:72] + wire _T_1477 = _T_1330 & _T_1048; // @[Mux.scala 27:72] + wire _T_1478 = _T_1333 & _T_1051; // @[Mux.scala 27:72] + wire _T_1479 = _T_1336 & _T_1054; // @[Mux.scala 27:72] + wire _T_1480 = _T_1339 & _T_1058; // @[Mux.scala 27:72] + wire _T_1481 = _T_1343 & _T_1063; // @[Mux.scala 27:72] + wire _T_1482 = _T_1348 & _T_1066; // @[Mux.scala 27:72] + wire _T_1483 = _T_1351 & _T_1069; // @[Mux.scala 27:72] + wire _T_1484 = _T_1354 & _T_1072; // @[Mux.scala 27:72] + wire _T_1485 = _T_1357 & _T_1075; // @[Mux.scala 27:72] + wire _T_1486 = _T_1360 & _T_1078; // @[Mux.scala 27:72] + wire _T_1487 = _T_1363 & _T_1081; // @[Mux.scala 27:72] + wire _T_1488 = _T_1366 & _T_1084; // @[Mux.scala 27:72] + wire _T_1489 = _T_1369 & _T_1087; // @[Mux.scala 27:72] + wire _T_1490 = _T_1372 & _T_1090; // @[Mux.scala 27:72] + wire _T_1491 = _T_1375 & _T_1095; // @[Mux.scala 27:72] + wire _T_1492 = _T_1380 & _T_1098; // @[Mux.scala 27:72] + wire _T_1493 = _T_1383 & _T_1101; // @[Mux.scala 27:72] + wire _T_1494 = _T_1386 & _T_1104; // @[Mux.scala 27:72] + wire _T_1495 = _T_1389 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1497 = _T_1393 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1498 = _T_1395 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1499 = _T_1397 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1500 = _T_1399 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1501 = _T_1401 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1502 = _T_1403 & _T_1122; // @[Mux.scala 27:72] + wire _T_1503 = _T_1407 & _T_1126; // @[Mux.scala 27:72] + wire _T_1504 = _T_1411 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1505 = _T_1413 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1506 = _T_1415 & _T_1134; // @[Mux.scala 27:72] + wire _T_1507 = _T_1419 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1508 = _T_1421 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1509 = _T_1423 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1510 = _T_1425 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1511 = _T_1427 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1512 = _T_1429 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1513 = _T_1431 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1514 = _T_1433 & _T_1153; // @[Mux.scala 27:72] + wire _T_1515 = _T_1438 & _T_1163; // @[Mux.scala 27:72] + wire _T_1516 = _T_1448 & _T_1166; // @[Mux.scala 27:72] + wire _T_1517 = _T_1451 & _T_1169; // @[Mux.scala 27:72] + wire _T_1518 = _T_1454 & _T_1172; // @[Mux.scala 27:72] + wire _T_1519 = _T_1457 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1520 = _T_1459 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1521 = _T_1461 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1522 = _T_1463 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1523 = _T_1465 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1524 = _T_1300 | _T_1468; // @[Mux.scala 27:72] + wire _T_1525 = _T_1524 | _T_1469; // @[Mux.scala 27:72] + wire _T_1526 = _T_1525 | _T_1470; // @[Mux.scala 27:72] + wire _T_1527 = _T_1526 | _T_1471; // @[Mux.scala 27:72] + wire _T_1528 = _T_1527 | _T_1472; // @[Mux.scala 27:72] + wire _T_1529 = _T_1528 | _T_1473; // @[Mux.scala 27:72] + wire _T_1530 = _T_1529 | _T_1474; // @[Mux.scala 27:72] + wire _T_1531 = _T_1530 | _T_1475; // @[Mux.scala 27:72] + wire _T_1532 = _T_1531 | _T_1476; // @[Mux.scala 27:72] + wire _T_1533 = _T_1532 | _T_1477; // @[Mux.scala 27:72] + wire _T_1534 = _T_1533 | _T_1478; // @[Mux.scala 27:72] wire _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72] wire _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72] wire _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72] @@ -51786,7 +51785,7 @@ module csr_tlu( wire _T_1549 = _T_1548 | _T_1493; // @[Mux.scala 27:72] wire _T_1550 = _T_1549 | _T_1494; // @[Mux.scala 27:72] wire _T_1551 = _T_1550 | _T_1495; // @[Mux.scala 27:72] - wire _T_1552 = _T_1551 | _T_1496; // @[Mux.scala 27:72] + wire _T_1552 = _T_1551 | _T_1475; // @[Mux.scala 27:72] wire _T_1553 = _T_1552 | _T_1497; // @[Mux.scala 27:72] wire _T_1554 = _T_1553 | _T_1498; // @[Mux.scala 27:72] wire _T_1555 = _T_1554 | _T_1499; // @[Mux.scala 27:72] @@ -51796,7 +51795,7 @@ module csr_tlu( wire _T_1559 = _T_1558 | _T_1503; // @[Mux.scala 27:72] wire _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72] wire _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72] - wire _T_1562 = _T_1561 | _T_1485; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72] wire _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72] wire _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72] wire _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72] @@ -51814,131 +51813,131 @@ module csr_tlu( wire _T_1577 = _T_1576 | _T_1521; // @[Mux.scala 27:72] wire _T_1578 = _T_1577 | _T_1522; // @[Mux.scala 27:72] wire _T_1579 = _T_1578 | _T_1523; // @[Mux.scala 27:72] - wire _T_1580 = _T_1579 | _T_1524; // @[Mux.scala 27:72] - wire _T_1581 = _T_1580 | _T_1525; // @[Mux.scala 27:72] - wire _T_1582 = _T_1581 | _T_1526; // @[Mux.scala 27:72] - wire _T_1583 = _T_1582 | _T_1527; // @[Mux.scala 27:72] - wire _T_1584 = _T_1583 | _T_1528; // @[Mux.scala 27:72] - wire _T_1585 = _T_1584 | _T_1529; // @[Mux.scala 27:72] - wire _T_1586 = _T_1585 | _T_1530; // @[Mux.scala 27:72] - wire _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72] - wire _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72] - wire _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1309 & _T_1589; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1593 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2273:24] + wire mhpmc_inc_r_1 = _T_1299 & _T_1579; // @[dec_tlu_ctl.scala 2255:44] + wire _T_1583 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1594 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1596 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1598 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1600 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1604 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1610 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1615 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1617 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1619 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1621 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1624 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1627 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1630 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1633 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1637 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1642 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1645 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1648 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1651 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1654 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1657 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1660 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1663 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1666 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1669 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1674 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1677 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1680 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1683 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1687 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1689 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1691 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1693 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1695 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1697 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1701 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1705 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1707 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1709 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1713 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1715 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1717 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1719 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1721 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1723 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1725 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1727 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1732 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1742 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1745 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1748 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1751 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1753 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1755 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1757 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1759 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1762 = _T_1596 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1763 = _T_1598 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1764 = _T_1600 & _T_1035; // @[Mux.scala 27:72] - wire _T_1765 = _T_1604 & _T_1041; // @[Mux.scala 27:72] - wire _T_1766 = _T_1610 & _T_1046; // @[Mux.scala 27:72] - wire _T_1767 = _T_1615 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1768 = _T_1617 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1769 = _T_1619 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1770 = _T_1621 & _T_1055; // @[Mux.scala 27:72] - wire _T_1771 = _T_1624 & _T_1058; // @[Mux.scala 27:72] - wire _T_1772 = _T_1627 & _T_1061; // @[Mux.scala 27:72] - wire _T_1773 = _T_1630 & _T_1064; // @[Mux.scala 27:72] - wire _T_1774 = _T_1633 & _T_1068; // @[Mux.scala 27:72] - wire _T_1775 = _T_1637 & _T_1073; // @[Mux.scala 27:72] - wire _T_1776 = _T_1642 & _T_1076; // @[Mux.scala 27:72] - wire _T_1777 = _T_1645 & _T_1079; // @[Mux.scala 27:72] - wire _T_1778 = _T_1648 & _T_1082; // @[Mux.scala 27:72] - wire _T_1779 = _T_1651 & _T_1085; // @[Mux.scala 27:72] - wire _T_1780 = _T_1654 & _T_1088; // @[Mux.scala 27:72] - wire _T_1781 = _T_1657 & _T_1091; // @[Mux.scala 27:72] - wire _T_1782 = _T_1660 & _T_1094; // @[Mux.scala 27:72] - wire _T_1783 = _T_1663 & _T_1097; // @[Mux.scala 27:72] - wire _T_1784 = _T_1666 & _T_1100; // @[Mux.scala 27:72] - wire _T_1785 = _T_1669 & _T_1105; // @[Mux.scala 27:72] - wire _T_1786 = _T_1674 & _T_1108; // @[Mux.scala 27:72] - wire _T_1787 = _T_1677 & _T_1111; // @[Mux.scala 27:72] - wire _T_1788 = _T_1680 & _T_1114; // @[Mux.scala 27:72] - wire _T_1789 = _T_1683 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1791 = _T_1687 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1792 = _T_1689 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1793 = _T_1691 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1794 = _T_1693 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1795 = _T_1695 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1796 = _T_1697 & _T_1132; // @[Mux.scala 27:72] - wire _T_1797 = _T_1701 & _T_1136; // @[Mux.scala 27:72] - wire _T_1798 = _T_1705 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1799 = _T_1707 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1800 = _T_1709 & _T_1144; // @[Mux.scala 27:72] - wire _T_1801 = _T_1713 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1802 = _T_1715 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1803 = _T_1717 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1804 = _T_1719 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1805 = _T_1721 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1806 = _T_1723 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1807 = _T_1725 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1808 = _T_1727 & _T_1163; // @[Mux.scala 27:72] - wire _T_1809 = _T_1732 & _T_1173; // @[Mux.scala 27:72] - wire _T_1810 = _T_1742 & _T_1176; // @[Mux.scala 27:72] - wire _T_1811 = _T_1745 & _T_1179; // @[Mux.scala 27:72] - wire _T_1812 = _T_1748 & _T_1182; // @[Mux.scala 27:72] - wire _T_1813 = _T_1751 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1814 = _T_1753 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1815 = _T_1755 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1816 = _T_1757 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1817 = _T_1759 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1818 = _T_1594 | _T_1762; // @[Mux.scala 27:72] + wire _T_1584 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1586 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1588 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1590 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1594 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1600 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1605 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1607 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1609 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1611 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1614 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1617 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1620 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1623 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1627 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1632 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1635 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1638 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1641 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1644 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1647 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1650 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1653 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1656 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1659 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1664 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1667 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1670 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1673 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1677 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1679 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1681 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1683 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1685 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1687 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1691 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1695 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1697 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1699 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1703 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1705 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1707 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1709 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1711 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1713 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1715 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1717 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1722 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1732 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1735 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1738 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1741 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1743 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1745 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1747 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1749 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1752 = _T_1586 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1753 = _T_1588 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1754 = _T_1590 & _T_1025; // @[Mux.scala 27:72] + wire _T_1755 = _T_1594 & _T_1031; // @[Mux.scala 27:72] + wire _T_1756 = _T_1600 & _T_1036; // @[Mux.scala 27:72] + wire _T_1757 = _T_1605 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1758 = _T_1607 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1759 = _T_1609 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1760 = _T_1611 & _T_1045; // @[Mux.scala 27:72] + wire _T_1761 = _T_1614 & _T_1048; // @[Mux.scala 27:72] + wire _T_1762 = _T_1617 & _T_1051; // @[Mux.scala 27:72] + wire _T_1763 = _T_1620 & _T_1054; // @[Mux.scala 27:72] + wire _T_1764 = _T_1623 & _T_1058; // @[Mux.scala 27:72] + wire _T_1765 = _T_1627 & _T_1063; // @[Mux.scala 27:72] + wire _T_1766 = _T_1632 & _T_1066; // @[Mux.scala 27:72] + wire _T_1767 = _T_1635 & _T_1069; // @[Mux.scala 27:72] + wire _T_1768 = _T_1638 & _T_1072; // @[Mux.scala 27:72] + wire _T_1769 = _T_1641 & _T_1075; // @[Mux.scala 27:72] + wire _T_1770 = _T_1644 & _T_1078; // @[Mux.scala 27:72] + wire _T_1771 = _T_1647 & _T_1081; // @[Mux.scala 27:72] + wire _T_1772 = _T_1650 & _T_1084; // @[Mux.scala 27:72] + wire _T_1773 = _T_1653 & _T_1087; // @[Mux.scala 27:72] + wire _T_1774 = _T_1656 & _T_1090; // @[Mux.scala 27:72] + wire _T_1775 = _T_1659 & _T_1095; // @[Mux.scala 27:72] + wire _T_1776 = _T_1664 & _T_1098; // @[Mux.scala 27:72] + wire _T_1777 = _T_1667 & _T_1101; // @[Mux.scala 27:72] + wire _T_1778 = _T_1670 & _T_1104; // @[Mux.scala 27:72] + wire _T_1779 = _T_1673 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1781 = _T_1677 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1782 = _T_1679 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1783 = _T_1681 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1784 = _T_1683 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1785 = _T_1685 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1786 = _T_1687 & _T_1122; // @[Mux.scala 27:72] + wire _T_1787 = _T_1691 & _T_1126; // @[Mux.scala 27:72] + wire _T_1788 = _T_1695 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1789 = _T_1697 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1790 = _T_1699 & _T_1134; // @[Mux.scala 27:72] + wire _T_1791 = _T_1703 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1792 = _T_1705 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1793 = _T_1707 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1794 = _T_1709 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1795 = _T_1711 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1796 = _T_1713 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1797 = _T_1715 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1798 = _T_1717 & _T_1153; // @[Mux.scala 27:72] + wire _T_1799 = _T_1722 & _T_1163; // @[Mux.scala 27:72] + wire _T_1800 = _T_1732 & _T_1166; // @[Mux.scala 27:72] + wire _T_1801 = _T_1735 & _T_1169; // @[Mux.scala 27:72] + wire _T_1802 = _T_1738 & _T_1172; // @[Mux.scala 27:72] + wire _T_1803 = _T_1741 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1804 = _T_1743 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1805 = _T_1745 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1806 = _T_1747 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1807 = _T_1749 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1808 = _T_1584 | _T_1752; // @[Mux.scala 27:72] + wire _T_1809 = _T_1808 | _T_1753; // @[Mux.scala 27:72] + wire _T_1810 = _T_1809 | _T_1754; // @[Mux.scala 27:72] + wire _T_1811 = _T_1810 | _T_1755; // @[Mux.scala 27:72] + wire _T_1812 = _T_1811 | _T_1756; // @[Mux.scala 27:72] + wire _T_1813 = _T_1812 | _T_1757; // @[Mux.scala 27:72] + wire _T_1814 = _T_1813 | _T_1758; // @[Mux.scala 27:72] + wire _T_1815 = _T_1814 | _T_1759; // @[Mux.scala 27:72] + wire _T_1816 = _T_1815 | _T_1760; // @[Mux.scala 27:72] + wire _T_1817 = _T_1816 | _T_1761; // @[Mux.scala 27:72] + wire _T_1818 = _T_1817 | _T_1762; // @[Mux.scala 27:72] wire _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72] wire _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72] wire _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72] @@ -51956,7 +51955,7 @@ module csr_tlu( wire _T_1833 = _T_1832 | _T_1777; // @[Mux.scala 27:72] wire _T_1834 = _T_1833 | _T_1778; // @[Mux.scala 27:72] wire _T_1835 = _T_1834 | _T_1779; // @[Mux.scala 27:72] - wire _T_1836 = _T_1835 | _T_1780; // @[Mux.scala 27:72] + wire _T_1836 = _T_1835 | _T_1759; // @[Mux.scala 27:72] wire _T_1837 = _T_1836 | _T_1781; // @[Mux.scala 27:72] wire _T_1838 = _T_1837 | _T_1782; // @[Mux.scala 27:72] wire _T_1839 = _T_1838 | _T_1783; // @[Mux.scala 27:72] @@ -51966,7 +51965,7 @@ module csr_tlu( wire _T_1843 = _T_1842 | _T_1787; // @[Mux.scala 27:72] wire _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72] wire _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72] - wire _T_1846 = _T_1845 | _T_1769; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72] wire _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72] wire _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72] wire _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72] @@ -51984,131 +51983,131 @@ module csr_tlu( wire _T_1861 = _T_1860 | _T_1805; // @[Mux.scala 27:72] wire _T_1862 = _T_1861 | _T_1806; // @[Mux.scala 27:72] wire _T_1863 = _T_1862 | _T_1807; // @[Mux.scala 27:72] - wire _T_1864 = _T_1863 | _T_1808; // @[Mux.scala 27:72] - wire _T_1865 = _T_1864 | _T_1809; // @[Mux.scala 27:72] - wire _T_1866 = _T_1865 | _T_1810; // @[Mux.scala 27:72] - wire _T_1867 = _T_1866 | _T_1811; // @[Mux.scala 27:72] - wire _T_1868 = _T_1867 | _T_1812; // @[Mux.scala 27:72] - wire _T_1869 = _T_1868 | _T_1813; // @[Mux.scala 27:72] - wire _T_1870 = _T_1869 | _T_1814; // @[Mux.scala 27:72] - wire _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72] - wire _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72] - wire _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1593 & _T_1873; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1877 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2273:24] + wire mhpmc_inc_r_2 = _T_1583 & _T_1863; // @[dec_tlu_ctl.scala 2255:44] + wire _T_1867 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1878 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1880 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1882 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1884 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1888 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1894 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1899 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1901 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1903 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1905 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1908 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1911 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1914 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1917 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1921 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1926 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1929 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1932 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1935 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1938 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1941 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1944 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1947 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1950 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1953 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1958 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1961 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1964 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1967 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1971 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1973 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1975 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1977 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1979 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1981 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1985 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1989 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1991 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1993 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1997 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1999 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_2001 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_2003 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_2005 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_2007 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_2009 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_2011 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_2016 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_2026 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_2029 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_2032 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_2035 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_2037 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_2039 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_2041 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_2043 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_2046 = _T_1880 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_2047 = _T_1882 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_2048 = _T_1884 & _T_1035; // @[Mux.scala 27:72] - wire _T_2049 = _T_1888 & _T_1041; // @[Mux.scala 27:72] - wire _T_2050 = _T_1894 & _T_1046; // @[Mux.scala 27:72] - wire _T_2051 = _T_1899 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_2052 = _T_1901 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_2053 = _T_1903 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_2054 = _T_1905 & _T_1055; // @[Mux.scala 27:72] - wire _T_2055 = _T_1908 & _T_1058; // @[Mux.scala 27:72] - wire _T_2056 = _T_1911 & _T_1061; // @[Mux.scala 27:72] - wire _T_2057 = _T_1914 & _T_1064; // @[Mux.scala 27:72] - wire _T_2058 = _T_1917 & _T_1068; // @[Mux.scala 27:72] - wire _T_2059 = _T_1921 & _T_1073; // @[Mux.scala 27:72] - wire _T_2060 = _T_1926 & _T_1076; // @[Mux.scala 27:72] - wire _T_2061 = _T_1929 & _T_1079; // @[Mux.scala 27:72] - wire _T_2062 = _T_1932 & _T_1082; // @[Mux.scala 27:72] - wire _T_2063 = _T_1935 & _T_1085; // @[Mux.scala 27:72] - wire _T_2064 = _T_1938 & _T_1088; // @[Mux.scala 27:72] - wire _T_2065 = _T_1941 & _T_1091; // @[Mux.scala 27:72] - wire _T_2066 = _T_1944 & _T_1094; // @[Mux.scala 27:72] - wire _T_2067 = _T_1947 & _T_1097; // @[Mux.scala 27:72] - wire _T_2068 = _T_1950 & _T_1100; // @[Mux.scala 27:72] - wire _T_2069 = _T_1953 & _T_1105; // @[Mux.scala 27:72] - wire _T_2070 = _T_1958 & _T_1108; // @[Mux.scala 27:72] - wire _T_2071 = _T_1961 & _T_1111; // @[Mux.scala 27:72] - wire _T_2072 = _T_1964 & _T_1114; // @[Mux.scala 27:72] - wire _T_2073 = _T_1967 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_2075 = _T_1971 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_2076 = _T_1973 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_2077 = _T_1975 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_2078 = _T_1977 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_2079 = _T_1979 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_2080 = _T_1981 & _T_1132; // @[Mux.scala 27:72] - wire _T_2081 = _T_1985 & _T_1136; // @[Mux.scala 27:72] - wire _T_2082 = _T_1989 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_2083 = _T_1991 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_2084 = _T_1993 & _T_1144; // @[Mux.scala 27:72] - wire _T_2085 = _T_1997 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2086 = _T_1999 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2087 = _T_2001 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_2088 = _T_2003 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2089 = _T_2005 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2090 = _T_2007 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2091 = _T_2009 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2092 = _T_2011 & _T_1163; // @[Mux.scala 27:72] - wire _T_2093 = _T_2016 & _T_1173; // @[Mux.scala 27:72] - wire _T_2094 = _T_2026 & _T_1176; // @[Mux.scala 27:72] - wire _T_2095 = _T_2029 & _T_1179; // @[Mux.scala 27:72] - wire _T_2096 = _T_2032 & _T_1182; // @[Mux.scala 27:72] - wire _T_2097 = _T_2035 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_2098 = _T_2037 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_2099 = _T_2039 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_2100 = _T_2041 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_2101 = _T_2043 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_2102 = _T_1878 | _T_2046; // @[Mux.scala 27:72] + wire _T_1868 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1870 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1872 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1874 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1878 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1884 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1889 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1891 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1893 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1895 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1898 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1901 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1904 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1907 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1911 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1916 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1919 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1922 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1925 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1928 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1931 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1934 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1937 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1940 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1943 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1948 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1951 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1954 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1957 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1961 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1963 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1965 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1967 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1969 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1971 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1975 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1979 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1981 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1983 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1987 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1989 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1991 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1993 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1995 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1997 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1999 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_2001 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_2006 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire _T_2016 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_2019 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_2022 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_2025 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_2027 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_2029 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_2031 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_2033 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_2036 = _T_1870 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2037 = _T_1872 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2038 = _T_1874 & _T_1025; // @[Mux.scala 27:72] + wire _T_2039 = _T_1878 & _T_1031; // @[Mux.scala 27:72] + wire _T_2040 = _T_1884 & _T_1036; // @[Mux.scala 27:72] + wire _T_2041 = _T_1889 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2042 = _T_1891 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2043 = _T_1893 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2044 = _T_1895 & _T_1045; // @[Mux.scala 27:72] + wire _T_2045 = _T_1898 & _T_1048; // @[Mux.scala 27:72] + wire _T_2046 = _T_1901 & _T_1051; // @[Mux.scala 27:72] + wire _T_2047 = _T_1904 & _T_1054; // @[Mux.scala 27:72] + wire _T_2048 = _T_1907 & _T_1058; // @[Mux.scala 27:72] + wire _T_2049 = _T_1911 & _T_1063; // @[Mux.scala 27:72] + wire _T_2050 = _T_1916 & _T_1066; // @[Mux.scala 27:72] + wire _T_2051 = _T_1919 & _T_1069; // @[Mux.scala 27:72] + wire _T_2052 = _T_1922 & _T_1072; // @[Mux.scala 27:72] + wire _T_2053 = _T_1925 & _T_1075; // @[Mux.scala 27:72] + wire _T_2054 = _T_1928 & _T_1078; // @[Mux.scala 27:72] + wire _T_2055 = _T_1931 & _T_1081; // @[Mux.scala 27:72] + wire _T_2056 = _T_1934 & _T_1084; // @[Mux.scala 27:72] + wire _T_2057 = _T_1937 & _T_1087; // @[Mux.scala 27:72] + wire _T_2058 = _T_1940 & _T_1090; // @[Mux.scala 27:72] + wire _T_2059 = _T_1943 & _T_1095; // @[Mux.scala 27:72] + wire _T_2060 = _T_1948 & _T_1098; // @[Mux.scala 27:72] + wire _T_2061 = _T_1951 & _T_1101; // @[Mux.scala 27:72] + wire _T_2062 = _T_1954 & _T_1104; // @[Mux.scala 27:72] + wire _T_2063 = _T_1957 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2065 = _T_1961 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2066 = _T_1963 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2067 = _T_1965 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2068 = _T_1967 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2069 = _T_1969 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2070 = _T_1971 & _T_1122; // @[Mux.scala 27:72] + wire _T_2071 = _T_1975 & _T_1126; // @[Mux.scala 27:72] + wire _T_2072 = _T_1979 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2073 = _T_1981 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2074 = _T_1983 & _T_1134; // @[Mux.scala 27:72] + wire _T_2075 = _T_1987 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2076 = _T_1989 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2077 = _T_1991 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2078 = _T_1993 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2079 = _T_1995 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2080 = _T_1997 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2081 = _T_1999 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2082 = _T_2001 & _T_1153; // @[Mux.scala 27:72] + wire _T_2083 = _T_2006 & _T_1163; // @[Mux.scala 27:72] + wire _T_2084 = _T_2016 & _T_1166; // @[Mux.scala 27:72] + wire _T_2085 = _T_2019 & _T_1169; // @[Mux.scala 27:72] + wire _T_2086 = _T_2022 & _T_1172; // @[Mux.scala 27:72] + wire _T_2087 = _T_2025 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2088 = _T_2027 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2089 = _T_2029 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2090 = _T_2031 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2091 = _T_2033 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2092 = _T_1868 | _T_2036; // @[Mux.scala 27:72] + wire _T_2093 = _T_2092 | _T_2037; // @[Mux.scala 27:72] + wire _T_2094 = _T_2093 | _T_2038; // @[Mux.scala 27:72] + wire _T_2095 = _T_2094 | _T_2039; // @[Mux.scala 27:72] + wire _T_2096 = _T_2095 | _T_2040; // @[Mux.scala 27:72] + wire _T_2097 = _T_2096 | _T_2041; // @[Mux.scala 27:72] + wire _T_2098 = _T_2097 | _T_2042; // @[Mux.scala 27:72] + wire _T_2099 = _T_2098 | _T_2043; // @[Mux.scala 27:72] + wire _T_2100 = _T_2099 | _T_2044; // @[Mux.scala 27:72] + wire _T_2101 = _T_2100 | _T_2045; // @[Mux.scala 27:72] + wire _T_2102 = _T_2101 | _T_2046; // @[Mux.scala 27:72] wire _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72] wire _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72] wire _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72] @@ -52126,7 +52125,7 @@ module csr_tlu( wire _T_2117 = _T_2116 | _T_2061; // @[Mux.scala 27:72] wire _T_2118 = _T_2117 | _T_2062; // @[Mux.scala 27:72] wire _T_2119 = _T_2118 | _T_2063; // @[Mux.scala 27:72] - wire _T_2120 = _T_2119 | _T_2064; // @[Mux.scala 27:72] + wire _T_2120 = _T_2119 | _T_2043; // @[Mux.scala 27:72] wire _T_2121 = _T_2120 | _T_2065; // @[Mux.scala 27:72] wire _T_2122 = _T_2121 | _T_2066; // @[Mux.scala 27:72] wire _T_2123 = _T_2122 | _T_2067; // @[Mux.scala 27:72] @@ -52136,7 +52135,7 @@ module csr_tlu( wire _T_2127 = _T_2126 | _T_2071; // @[Mux.scala 27:72] wire _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72] wire _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72] - wire _T_2130 = _T_2129 | _T_2053; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72] wire _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72] wire _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72] wire _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72] @@ -52154,196 +52153,196 @@ module csr_tlu( wire _T_2145 = _T_2144 | _T_2089; // @[Mux.scala 27:72] wire _T_2146 = _T_2145 | _T_2090; // @[Mux.scala 27:72] wire _T_2147 = _T_2146 | _T_2091; // @[Mux.scala 27:72] - wire _T_2148 = _T_2147 | _T_2092; // @[Mux.scala 27:72] - wire _T_2149 = _T_2148 | _T_2093; // @[Mux.scala 27:72] - wire _T_2150 = _T_2149 | _T_2094; // @[Mux.scala 27:72] - wire _T_2151 = _T_2150 | _T_2095; // @[Mux.scala 27:72] - wire _T_2152 = _T_2151 | _T_2096; // @[Mux.scala 27:72] - wire _T_2153 = _T_2152 | _T_2097; // @[Mux.scala 27:72] - wire _T_2154 = _T_2153 | _T_2098; // @[Mux.scala 27:72] - wire _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72] - wire _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72] - wire _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1877 & _T_2157; // @[dec_tlu_ctl.scala 2273:44] - reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2334:53] - reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2335:53] - reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2336:53] - reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2337:53] - reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2338:56] - wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2341:67] - wire _T_2169 = ~_T_85; // @[dec_tlu_ctl.scala 2342:37] - wire [3:0] _T_2171 = _T_2169 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_2178 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2171 & _T_2178; // @[dec_tlu_ctl.scala 2342:86] - wire _T_2180 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2344:67] - wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2344:65] - wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2344:45] - wire _T_2185 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2345:67] - wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2345:65] - wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2345:45] - wire _T_2190 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2346:67] - wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[dec_tlu_ctl.scala 2346:65] - wire _T_2192 = ~_T_2191; // @[dec_tlu_ctl.scala 2346:45] - wire _T_2195 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2347:67] - wire _T_2196 = perfcnt_halted_d1 & _T_2195; // @[dec_tlu_ctl.scala 2347:65] - wire _T_2197 = ~_T_2196; // @[dec_tlu_ctl.scala 2347:45] - wire _T_2200 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2353:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2200; // @[dec_tlu_ctl.scala 2353:43] - wire _T_2201 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2354:23] - wire _T_2203 = _T_2201 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2354:39] - wire _T_2204 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2354:86] - wire mhpmc3_wr_en1 = _T_2203 & _T_2204; // @[dec_tlu_ctl.scala 2354:66] + wire mhpmc_inc_r_3 = _T_1867 & _T_2147; // @[dec_tlu_ctl.scala 2255:44] + reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2316:53] + reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2317:53] + reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2318:53] + reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2319:53] + reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2320:56] + wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2323:67] + wire _T_2159 = ~_T_85; // @[dec_tlu_ctl.scala 2324:37] + wire [3:0] _T_2161 = _T_2159 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2168 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2161 & _T_2168; // @[dec_tlu_ctl.scala 2324:86] + wire _T_2170 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2326:67] + wire _T_2171 = perfcnt_halted_d1 & _T_2170; // @[dec_tlu_ctl.scala 2326:65] + wire _T_2172 = ~_T_2171; // @[dec_tlu_ctl.scala 2326:45] + wire _T_2175 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2327:67] + wire _T_2176 = perfcnt_halted_d1 & _T_2175; // @[dec_tlu_ctl.scala 2327:65] + wire _T_2177 = ~_T_2176; // @[dec_tlu_ctl.scala 2327:45] + wire _T_2180 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2328:67] + wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2328:65] + wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2328:45] + wire _T_2185 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2329:67] + wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2329:65] + wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2329:45] + wire _T_2190 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2335:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2190; // @[dec_tlu_ctl.scala 2335:43] + wire _T_2191 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2336:23] + wire _T_2193 = _T_2191 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2336:39] + wire _T_2194 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2336:86] + wire mhpmc3_wr_en1 = _T_2193 & _T_2194; // @[dec_tlu_ctl.scala 2336:66] reg [31:0] mhpmc3h; // @[lib.scala 374:16] reg [31:0] mhpmc3; // @[lib.scala 374:16] - wire [63:0] _T_2207 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] - wire [63:0] _T_2208 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2207 + _T_2208; // @[dec_tlu_ctl.scala 2358:49] - wire _T_2216 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2363:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2216; // @[dec_tlu_ctl.scala 2363:44] - wire _T_2222 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2372:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2222; // @[dec_tlu_ctl.scala 2372:43] - wire _T_2225 = _T_2201 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2373:39] - wire _T_2226 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2373:86] - wire mhpmc4_wr_en1 = _T_2225 & _T_2226; // @[dec_tlu_ctl.scala 2373:66] + wire [63:0] _T_2197 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2198 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2197 + _T_2198; // @[dec_tlu_ctl.scala 2340:49] + wire _T_2206 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2345:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2206; // @[dec_tlu_ctl.scala 2345:44] + wire _T_2212 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2354:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2212; // @[dec_tlu_ctl.scala 2354:43] + wire _T_2215 = _T_2191 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2355:39] + wire _T_2216 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2355:86] + wire mhpmc4_wr_en1 = _T_2215 & _T_2216; // @[dec_tlu_ctl.scala 2355:66] reg [31:0] mhpmc4h; // @[lib.scala 374:16] reg [31:0] mhpmc4; // @[lib.scala 374:16] - wire [63:0] _T_2229 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] - wire [63:0] _T_2230 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2229 + _T_2230; // @[dec_tlu_ctl.scala 2378:49] - wire _T_2239 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2382:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2239; // @[dec_tlu_ctl.scala 2382:44] - wire _T_2245 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2391:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2245; // @[dec_tlu_ctl.scala 2391:43] - wire _T_2248 = _T_2201 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2392:39] - wire _T_2249 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2392:86] - wire mhpmc5_wr_en1 = _T_2248 & _T_2249; // @[dec_tlu_ctl.scala 2392:66] + wire [63:0] _T_2219 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2220 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2219 + _T_2220; // @[dec_tlu_ctl.scala 2360:49] + wire _T_2229 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2364:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2229; // @[dec_tlu_ctl.scala 2364:44] + wire _T_2235 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2373:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2235; // @[dec_tlu_ctl.scala 2373:43] + wire _T_2238 = _T_2191 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2374:39] + wire _T_2239 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2374:86] + wire mhpmc5_wr_en1 = _T_2238 & _T_2239; // @[dec_tlu_ctl.scala 2374:66] reg [31:0] mhpmc5h; // @[lib.scala 374:16] reg [31:0] mhpmc5; // @[lib.scala 374:16] - wire [63:0] _T_2252 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] - wire [63:0] _T_2253 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2252 + _T_2253; // @[dec_tlu_ctl.scala 2395:49] - wire _T_2261 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2400:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2261; // @[dec_tlu_ctl.scala 2400:44] - wire _T_2267 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2409:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2267; // @[dec_tlu_ctl.scala 2409:43] - wire _T_2270 = _T_2201 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2410:39] - wire _T_2271 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2410:86] - wire mhpmc6_wr_en1 = _T_2270 & _T_2271; // @[dec_tlu_ctl.scala 2410:66] + wire [63:0] _T_2242 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2243 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2242 + _T_2243; // @[dec_tlu_ctl.scala 2377:49] + wire _T_2251 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2382:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2251; // @[dec_tlu_ctl.scala 2382:44] + wire _T_2257 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2391:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2257; // @[dec_tlu_ctl.scala 2391:43] + wire _T_2260 = _T_2191 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2392:39] + wire _T_2261 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2392:86] + wire mhpmc6_wr_en1 = _T_2260 & _T_2261; // @[dec_tlu_ctl.scala 2392:66] reg [31:0] mhpmc6h; // @[lib.scala 374:16] reg [31:0] mhpmc6; // @[lib.scala 374:16] - wire [63:0] _T_2274 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] - wire [63:0] _T_2275 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2274 + _T_2275; // @[dec_tlu_ctl.scala 2413:49] - wire _T_2283 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2418:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2283; // @[dec_tlu_ctl.scala 2418:44] - wire _T_2289 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2429:56] - wire _T_2291 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2429:102] - wire _T_2292 = _T_2289 | _T_2291; // @[dec_tlu_ctl.scala 2429:71] - wire _T_2295 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2431:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2431:41] - wire _T_2299 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2438:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2438:41] - wire _T_2303 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2445:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2445:41] - wire _T_2307 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2452:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2307; // @[dec_tlu_ctl.scala 2452:41] - wire _T_2311 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2469:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2311; // @[dec_tlu_ctl.scala 2469:48] - wire _T_2323 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2484:51] - wire _T_2324 = _T_2323 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2484:78] - wire _T_2325 = _T_2324 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2484:104] - wire _T_2326 = _T_2325 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2484:130] - wire _T_2327 = _T_2326 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2485:32] - reg _T_2330; // @[dec_tlu_ctl.scala 2487:62] - wire _T_2331 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2488:91] - wire _T_2332 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2488:137] - wire _T_2333 = io_trigger_hit_r_d1 & _T_2332; // @[dec_tlu_ctl.scala 2488:135] - reg _T_2335; // @[dec_tlu_ctl.scala 2488:62] - reg [4:0] _T_2336; // @[dec_tlu_ctl.scala 2489:62] - reg _T_2337; // @[dec_tlu_ctl.scala 2490:62] - wire [31:0] _T_2343 = {io_core_id,4'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2352 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2357 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2370 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2383 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2395 = {io_mepc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2400 = {28'h0,mscause}; // @[Cat.scala 29:58] - wire [31:0] _T_2408 = {meivt,10'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2411 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2414 = {28'h0,meicurpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2417 = {28'h0,meicidpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2420 = {28'h0,meipt}; // @[Cat.scala 29:58] - wire [31:0] _T_2423 = {23'h0,mcgc}; // @[Cat.scala 29:58] - wire [31:0] _T_2426 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2430 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] - wire [31:0] _T_2432 = {io_dpc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2448 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2451 = {30'h0,mtsel}; // @[Cat.scala 29:58] - wire [31:0] _T_2480 = {26'h0,mfdht}; // @[Cat.scala 29:58] - wire [31:0] _T_2483 = {30'h0,mfdhs}; // @[Cat.scala 29:58] - wire [31:0] _T_2486 = {22'h0,mhpme3}; // @[Cat.scala 29:58] - wire [31:0] _T_2489 = {22'h0,mhpme4}; // @[Cat.scala 29:58] - wire [31:0] _T_2492 = {22'h0,mhpme5}; // @[Cat.scala 29:58] - wire [31:0] _T_2495 = {22'h0,mhpme6}; // @[Cat.scala 29:58] - wire [31:0] _T_2498 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire [31:0] _T_2501 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2504 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2505 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2506 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2507 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2508 = io_csr_pkt_csr_mhartid ? _T_2343 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2509 = io_csr_pkt_csr_mstatus ? _T_2352 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2510 = io_csr_pkt_csr_mtvec ? _T_2357 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2511 = io_csr_pkt_csr_mip ? _T_2370 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2512 = io_csr_pkt_csr_mie ? _T_2383 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2513 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2514 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2515 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2516 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2517 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2518 = io_csr_pkt_csr_mepc ? _T_2395 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2519 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2520 = io_csr_pkt_csr_mscause ? _T_2400 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2521 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2522 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2523 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2524 = io_csr_pkt_csr_meivt ? _T_2408 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2525 = io_csr_pkt_csr_meihap ? _T_2411 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2526 = io_csr_pkt_csr_meicurpl ? _T_2414 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2527 = io_csr_pkt_csr_meicidpl ? _T_2417 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2528 = io_csr_pkt_csr_meipt ? _T_2420 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2529 = io_csr_pkt_csr_mcgc ? _T_2423 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2530 = io_csr_pkt_csr_mfdc ? _T_2426 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2531 = io_csr_pkt_csr_dcsr ? _T_2430 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2532 = io_csr_pkt_csr_dpc ? _T_2432 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2533 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2535 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2536 = io_csr_pkt_csr_dicawics ? _T_2448 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2537 = io_csr_pkt_csr_mtsel ? _T_2451 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2538 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2540 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2541 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2542 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2551 = io_csr_pkt_csr_mfdht ? _T_2480 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2552 = io_csr_pkt_csr_mfdhs ? _T_2483 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2553 = io_csr_pkt_csr_mhpme3 ? _T_2486 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme4 ? _T_2489 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme5 ? _T_2492 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme6 ? _T_2495 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2557 = io_csr_pkt_csr_mcountinhibit ? _T_2498 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2558 = io_csr_pkt_csr_mpmc ? _T_2501 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2559 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2560 = _T_2504 | _T_2505; // @[Mux.scala 27:72] + wire [63:0] _T_2264 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2265 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2264 + _T_2265; // @[dec_tlu_ctl.scala 2395:49] + wire _T_2273 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2400:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2273; // @[dec_tlu_ctl.scala 2400:44] + wire _T_2279 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2411:56] + wire _T_2281 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2411:102] + wire _T_2282 = _T_2279 | _T_2281; // @[dec_tlu_ctl.scala 2411:71] + wire _T_2285 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2413:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2285; // @[dec_tlu_ctl.scala 2413:41] + wire _T_2289 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2420:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2289; // @[dec_tlu_ctl.scala 2420:41] + wire _T_2293 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2427:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2293; // @[dec_tlu_ctl.scala 2427:41] + wire _T_2297 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2434:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2297; // @[dec_tlu_ctl.scala 2434:41] + wire _T_2301 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2451:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2301; // @[dec_tlu_ctl.scala 2451:48] + wire _T_2313 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2466:51] + wire _T_2314 = _T_2313 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2466:78] + wire _T_2315 = _T_2314 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2466:104] + wire _T_2316 = _T_2315 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2466:130] + wire _T_2317 = _T_2316 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2467:32] + reg _T_2320; // @[dec_tlu_ctl.scala 2469:62] + wire _T_2321 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2470:91] + wire _T_2322 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2470:137] + wire _T_2323 = io_trigger_hit_r_d1 & _T_2322; // @[dec_tlu_ctl.scala 2470:135] + reg _T_2325; // @[dec_tlu_ctl.scala 2470:62] + reg [4:0] _T_2326; // @[dec_tlu_ctl.scala 2471:62] + reg _T_2327; // @[dec_tlu_ctl.scala 2472:62] + wire [31:0] _T_2333 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2342 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2347 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2360 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2373 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2385 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2390 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2398 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2401 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2404 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2407 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2410 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2413 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2416 = {13'h0,_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2420 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2422 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2438 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2441 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2470 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2473 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2476 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2479 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2482 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2485 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2488 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2491 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2494 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2495 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2496 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2497 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2498 = io_csr_pkt_csr_mhartid ? _T_2333 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2499 = io_csr_pkt_csr_mstatus ? _T_2342 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2500 = io_csr_pkt_csr_mtvec ? _T_2347 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2501 = io_csr_pkt_csr_mip ? _T_2360 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2502 = io_csr_pkt_csr_mie ? _T_2373 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2503 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2504 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2505 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mepc ? _T_2385 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_mscause ? _T_2390 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_meivt ? _T_2398 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_meihap ? _T_2401 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_meicurpl ? _T_2404 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_meicidpl ? _T_2407 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_meipt ? _T_2410 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_mcgc ? _T_2413 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_mfdc ? _T_2416 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_dcsr ? _T_2420 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_dpc ? _T_2422 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_dicawics ? _T_2438 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_mtsel ? _T_2441 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_mfdht ? _T_2470 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_mfdhs ? _T_2473 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mhpme3 ? _T_2476 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpme4 ? _T_2479 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpme5 ? _T_2482 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mhpme6 ? _T_2485 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mcountinhibit ? _T_2488 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mpmc ? _T_2491 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = _T_2494 | _T_2495; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = _T_2550 | _T_2496; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = _T_2551 | _T_2497; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = _T_2552 | _T_2498; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = _T_2553 | _T_2499; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = _T_2554 | _T_2500; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72] wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] @@ -52387,16 +52386,6 @@ module csr_tlu( wire [31:0] _T_2601 = _T_2600 | _T_2546; // @[Mux.scala 27:72] wire [31:0] _T_2602 = _T_2601 | _T_2547; // @[Mux.scala 27:72] wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72] - wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72] - wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72] - wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72] - wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72] - wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72] - wire [31:0] _T_2609 = _T_2608 | _T_2554; // @[Mux.scala 27:72] - wire [31:0] _T_2610 = _T_2609 | _T_2555; // @[Mux.scala 27:72] - wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72] - wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72] - wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -52607,84 +52596,84 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_763,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2154:56] - assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2157:41] - assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2165:41] - assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2166:41] - assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2230:40] - assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2231:43] - assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2248:51] - assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2230:40] - assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2231:43] - assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2248:51] - assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2230:40] - assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2231:43] - assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2248:51] - assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2230:40] - assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2231:43] - assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2248:51] - assign io_dec_tlu_int_valid_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2490:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2335; // @[dec_tlu_ctl.scala 2488:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2330; // @[dec_tlu_ctl.scala 2487:30] - assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2492:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2489:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2182; // @[dec_tlu_ctl.scala 2344:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2187; // @[dec_tlu_ctl.scala 2345:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2192; // @[dec_tlu_ctl.scala 2346:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2197; // @[dec_tlu_ctl.scala 2347:22] - assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1716:31] - assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1717:31] - assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1719:31] - assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1721:31] - assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1722:31] - assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1723:31] - assign io_dec_csr_rddata_d = _T_2613 | _T_2559; // @[dec_tlu_ctl.scala 2497:21] - assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1766:39] - assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1775:24] - assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2004:19] - assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1968:22] - assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1954:20] - assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1805:21] - assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[dec_tlu_ctl.scala 1765:39] - assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1764:39] - assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1763:39] - assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1762:39] - assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1761:39] - assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1760:39] - assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1449:23] - assign io_fw_halt_req = _T_502 & _T_503; // @[dec_tlu_ctl.scala 1840:17] - assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1465:13] - assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1464:20] - assign io_dcsr = _T_701; // @[dec_tlu_ctl.scala 2051:10] - assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1477:11] - assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1492:9] - assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1506:12] - assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1600:11] - assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1606:14] - assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1625:10] - assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1823:22] - assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1931:16] - assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2068:9] - assign io_mtdata1_t_0 = _T_872; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_1 = _T_873; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_2 = _T_874; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_3 = _T_875; // @[dec_tlu_ctl.scala 2225:39] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_753,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2136:56] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2139:41] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2147:41] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2148:41] + assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2212:40] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2213:43] + assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2214:40] + assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2215:40] + assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2216:40] + assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2217:40] + assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2230:51] + assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2212:40] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2213:43] + assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2214:40] + assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2215:40] + assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2216:40] + assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2217:40] + assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2230:51] + assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2212:40] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2213:43] + assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2214:40] + assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2215:40] + assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2216:40] + assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2217:40] + assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2230:51] + assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2212:40] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2213:43] + assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2214:40] + assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2215:40] + assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2216:40] + assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2217:40] + assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2230:51] + assign io_dec_tlu_int_valid_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2472:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2325; // @[dec_tlu_ctl.scala 2470:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2320; // @[dec_tlu_ctl.scala 2469:30] + assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2474:24] + assign io_dec_tlu_exc_cause_wb1 = _T_2326; // @[dec_tlu_ctl.scala 2471:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2172; // @[dec_tlu_ctl.scala 2326:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2177; // @[dec_tlu_ctl.scala 2327:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2182; // @[dec_tlu_ctl.scala 2328:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2187; // @[dec_tlu_ctl.scala 2329:22] + assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1698:31] + assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1699:31] + assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1701:31] + assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1702:31] + assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1703:31] + assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1704:31] + assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1705:31] + assign io_dec_csr_rddata_d = _T_2603 | _T_2549; // @[dec_tlu_ctl.scala 2479:21] + assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1748:39] + assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1757:24] + assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 1986:19] + assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1950:22] + assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1936:20] + assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1787:21] + assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1746:39] + assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1745:39] + assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1744:39] + assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1743:39] + assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1742:39] + assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1431:23] + assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1822:17] + assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1447:13] + assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1446:20] + assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2033:10] + assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1459:11] + assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1474:9] + assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1488:12] + assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1582:11] + assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1588:14] + assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1607:10] + assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1805:22] + assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1913:16] + assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2050:9] + assign io_mtdata1_t_0 = _T_862; // @[dec_tlu_ctl.scala 2207:39] + assign io_mtdata1_t_1 = _T_863; // @[dec_tlu_ctl.scala 2207:39] + assign io_mtdata1_t_2 = _T_864; // @[dec_tlu_ctl.scala 2207:39] + assign io_mtdata1_t_3 = _T_865; // @[dec_tlu_ctl.scala 2207:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -52716,34 +52705,34 @@ module csr_tlu( assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_337; // @[lib.scala 371:17] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_374; // @[lib.scala 371:17] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_364; // @[lib.scala 371:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_11_io_en = _T_493 & _T_494; // @[lib.scala 371:17] + assign rvclkhdr_11_io_en = _T_483 & _T_484; // @[lib.scala 371:17] assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[lib.scala 371:17] assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_13_io_en = _T_549 | io_iccm_dma_sb_error; // @[lib.scala 371:17] + assign rvclkhdr_13_io_en = _T_539 | io_iccm_dma_sb_error; // @[lib.scala 371:17] assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[lib.scala 371:17] assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_612; // @[lib.scala 371:17] + assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_602; // @[lib.scala 371:17] assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_16_io_en = _T_632 | io_take_ext_int_start; // @[lib.scala 371:17] + assign rvclkhdr_16_io_en = _T_622 | io_take_ext_int_start; // @[lib.scala 371:17] assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_17_io_en = _T_698 | io_take_nmi; // @[lib.scala 371:17] + assign rvclkhdr_17_io_en = _T_688 | io_take_nmi; // @[lib.scala 371:17] assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_18_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_18_io_en = _T_723 | dpc_capture_npc; // @[lib.scala 371:17] + assign rvclkhdr_18_io_en = _T_713 | dpc_capture_npc; // @[lib.scala 371:17] assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_19_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_19_io_en = _T_663 & _T_733; // @[lib.scala 371:17] + assign rvclkhdr_19_io_en = _T_653 & _T_723; // @[lib.scala 371:17] assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_20_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] @@ -52752,16 +52741,16 @@ module csr_tlu( assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_22_io_en = _T_971 & _T_807; // @[lib.scala 371:17] + assign rvclkhdr_22_io_en = _T_961 & _T_797; // @[lib.scala 371:17] assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_23_io_en = _T_980 & _T_816; // @[lib.scala 371:17] + assign rvclkhdr_23_io_en = _T_970 & _T_806; // @[lib.scala 371:17] assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_24_io_en = _T_989 & _T_825; // @[lib.scala 371:17] + assign rvclkhdr_24_io_en = _T_979 & _T_815; // @[lib.scala 371:17] assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_25_io_en = _T_998 & _T_834; // @[lib.scala 371:17] + assign rvclkhdr_25_io_en = _T_988 & _T_824; // @[lib.scala 371:17] assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17] @@ -52788,7 +52777,7 @@ module csr_tlu( assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17] assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_34_io_en = _T_2327 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_34_io_en = _T_2317 | io_clk_override; // @[lib.scala 345:16] assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -52898,9 +52887,9 @@ initial begin _RAND_35 = {1{`RANDOM}}; meipt = _RAND_35[3:0]; _RAND_36 = {1{`RANDOM}}; - _T_701 = _RAND_36[15:0]; + _T_691 = _RAND_36[15:0]; _RAND_37 = {1{`RANDOM}}; - _T_726 = _RAND_37[30:0]; + _T_716 = _RAND_37[30:0]; _RAND_38 = {1{`RANDOM}}; dicawics = _RAND_38[16:0]; _RAND_39 = {3{`RANDOM}}; @@ -52908,7 +52897,7 @@ initial begin _RAND_40 = {1{`RANDOM}}; dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - _T_758 = _RAND_41[31:0]; + _T_748 = _RAND_41[31:0]; _RAND_42 = {1{`RANDOM}}; icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; @@ -52916,13 +52905,13 @@ initial begin _RAND_44 = {1{`RANDOM}}; mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_872 = _RAND_45[9:0]; + _T_862 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_873 = _RAND_46[9:0]; + _T_863 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_874 = _RAND_47[9:0]; + _T_864 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - _T_875 = _RAND_48[9:0]; + _T_865 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; @@ -52966,13 +52955,13 @@ initial begin _RAND_69 = {1{`RANDOM}}; mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2330 = _RAND_70[0:0]; + _T_2320 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2335 = _RAND_71[0:0]; + _T_2325 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2336 = _RAND_72[4:0]; + _T_2326 = _RAND_72[4:0]; _RAND_73 = {1{`RANDOM}}; - _T_2337 = _RAND_73[0:0]; + _T_2327 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -53083,10 +53072,10 @@ initial begin meipt = 4'h0; end if (reset) begin - _T_701 = 16'h0; + _T_691 = 16'h0; end if (reset) begin - _T_726 = 31'h0; + _T_716 = 31'h0; end if (reset) begin dicawics = 17'h0; @@ -53098,7 +53087,7 @@ initial begin dicad0h = 32'h0; end if (reset) begin - _T_758 = 32'h0; + _T_748 = 32'h0; end if (reset) begin icache_rd_valid_f = 1'h0; @@ -53110,16 +53099,16 @@ initial begin mtsel = 2'h0; end if (reset) begin - _T_872 = 10'h0; + _T_862 = 10'h0; end if (reset) begin - _T_873 = 10'h0; + _T_863 = 10'h0; end if (reset) begin - _T_874 = 10'h0; + _T_864 = 10'h0; end if (reset) begin - _T_875 = 10'h0; + _T_865 = 10'h0; end if (reset) begin mtdata2_t_0 = 32'h0; @@ -53185,16 +53174,16 @@ initial begin mhpmc6 = 32'h0; end if (reset) begin - _T_2330 = 1'h0; + _T_2320 = 1'h0; end if (reset) begin - _T_2335 = 1'h0; + _T_2325 = 1'h0; end if (reset) begin - _T_2336 = 5'h0; + _T_2326 = 5'h0; end if (reset) begin - _T_2337 = 1'h0; + _T_2327 = 1'h0; end `endif // RANDOMIZE end // initial @@ -53206,9 +53195,9 @@ end // initial if (reset) begin mpmc_b <= 1'h0; end else if (wr_mpmc_r) begin - mpmc_b <= _T_510; + mpmc_b <= _T_500; end else begin - mpmc_b <= _T_511; + mpmc_b <= _T_501; end end always @(posedge io_free_clk or posedge reset) begin @@ -53229,27 +53218,27 @@ end // initial if (reset) begin mdccmect <= 32'h0; end else if (wr_mdccmect_r) begin - mdccmect <= _T_525; + mdccmect <= _T_515; end else begin - mdccmect <= _T_569; + mdccmect <= _T_559; end end always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin miccmect <= 32'h0; end else if (wr_miccmect_r) begin - miccmect <= _T_525; + miccmect <= _T_515; end else begin - miccmect <= _T_548; + miccmect <= _T_538; end end always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin if (reset) begin micect <= 32'h0; end else if (wr_micect_r) begin - micect <= _T_525; + micect <= _T_515; end else begin - micect <= _T_527; + micect <= _T_517; end end always @(posedge io_free_clk or posedge reset) begin @@ -53397,14 +53386,14 @@ end // initial if (reset) begin mfdc_int <= 15'h0; end else begin - mfdc_int <= {_T_347,_T_346}; + mfdc_int <= {_T_341,io_dec_csr_wrdata_r[11:0]}; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin mrac <= 32'h0; end else begin - mrac <= {_T_484,_T_469}; + mrac <= {_T_474,_T_459}; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin @@ -53424,11 +53413,11 @@ end // initial always @(posedge io_active_clk or posedge reset) begin if (reset) begin mfdhs <= 2'h0; - end else if (_T_595) begin + end else if (_T_585) begin if (wr_mfdhs_r) begin mfdhs <= io_dec_csr_wrdata_r[1:0]; - end else if (_T_589) begin - mfdhs <= _T_593; + end else if (_T_579) begin + mfdhs <= _T_583; end end end @@ -53437,7 +53426,7 @@ end // initial force_halt_ctr_f <= 32'h0; end else if (mfdht[0]) begin if (io_debug_halt_req_f) begin - force_halt_ctr_f <= _T_600; + force_halt_ctr_f <= _T_590; end else if (io_dbg_tlu_halted_f) begin force_halt_ctr_f <= 32'h0; end @@ -53482,27 +53471,27 @@ end // initial end always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin - _T_701 <= 16'h0; + _T_691 <= 16'h0; end else if (enter_debug_halt_req_le) begin - _T_701 <= _T_675; + _T_691 <= _T_665; end else if (wr_dcsr_r) begin - _T_701 <= _T_690; + _T_691 <= _T_680; end else begin - _T_701 <= _T_695; + _T_691 <= _T_685; end end always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin - _T_726 <= 31'h0; + _T_716 <= 31'h0; end else begin - _T_726 <= _T_721 | _T_720; + _T_716 <= _T_711 | _T_710; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin if (reset) begin dicawics <= 17'h0; end else begin - dicawics <= {_T_730,io_dec_csr_wrdata_r[16:3]}; + dicawics <= {_T_720,io_dec_csr_wrdata_r[16:3]}; end end always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin @@ -53525,12 +53514,12 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_758 <= 32'h0; - end else if (_T_756) begin - if (_T_752) begin - _T_758 <= io_dec_csr_wrdata_r; + _T_748 <= 32'h0; + end else if (_T_746) begin + if (_T_742) begin + _T_748 <= io_dec_csr_wrdata_r; end else begin - _T_758 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; + _T_748 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; end end end @@ -53538,14 +53527,14 @@ end // initial if (reset) begin icache_rd_valid_f <= 1'h0; end else begin - icache_rd_valid_f <= _T_768 & _T_770; + icache_rd_valid_f <= _T_758 & _T_760; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin icache_wr_valid_f <= 1'h0; end else begin - icache_wr_valid_f <= _T_663 & _T_773; + icache_wr_valid_f <= _T_653 & _T_763; end end always @(posedge io_csr_wr_clk or posedge reset) begin @@ -53557,38 +53546,38 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_872 <= 10'h0; + _T_862 <= 10'h0; end else if (wr_mtdata1_t_r_0) begin - _T_872 <= tdata_wrdata_r; + _T_862 <= tdata_wrdata_r; end else begin - _T_872 <= _T_843; + _T_862 <= _T_833; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_873 <= 10'h0; + _T_863 <= 10'h0; end else if (wr_mtdata1_t_r_1) begin - _T_873 <= tdata_wrdata_r; + _T_863 <= tdata_wrdata_r; end else begin - _T_873 <= _T_852; + _T_863 <= _T_842; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_874 <= 10'h0; + _T_864 <= 10'h0; end else if (wr_mtdata1_t_r_2) begin - _T_874 <= tdata_wrdata_r; + _T_864 <= tdata_wrdata_r; end else begin - _T_874 <= _T_861; + _T_864 <= _T_851; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_875 <= 10'h0; + _T_865 <= 10'h0; end else if (wr_mtdata1_t_r_3) begin - _T_875 <= tdata_wrdata_r; + _T_865 <= tdata_wrdata_r; end else begin - _T_875 <= _T_870; + _T_865 <= _T_860; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin @@ -53623,7 +53612,7 @@ end // initial if (reset) begin mhpme3 <= 10'h0; end else if (wr_mhpme3_r) begin - if (_T_2292) begin + if (_T_2282) begin mhpme3 <= 10'h204; end else begin mhpme3 <= io_dec_csr_wrdata_r[9:0]; @@ -53634,7 +53623,7 @@ end // initial if (reset) begin mhpme4 <= 10'h0; end else if (wr_mhpme4_r) begin - if (_T_2292) begin + if (_T_2282) begin mhpme4 <= 10'h204; end else begin mhpme4 <= io_dec_csr_wrdata_r[9:0]; @@ -53645,7 +53634,7 @@ end // initial if (reset) begin mhpme5 <= 10'h0; end else if (wr_mhpme5_r) begin - if (_T_2292) begin + if (_T_2282) begin mhpme5 <= 10'h204; end else begin mhpme5 <= io_dec_csr_wrdata_r[9:0]; @@ -53656,7 +53645,7 @@ end // initial if (reset) begin mhpme6 <= 10'h0; end else if (wr_mhpme6_r) begin - if (_T_2292) begin + if (_T_2282) begin mhpme6 <= 10'h204; end else begin mhpme6 <= io_dec_csr_wrdata_r[9:0]; @@ -53667,28 +53656,28 @@ end // initial if (reset) begin mhpmc_inc_r_d1_0 <= 1'h0; end else begin - mhpmc_inc_r_d1_0 <= _T_1025 & _T_1305; + mhpmc_inc_r_d1_0 <= _T_1015 & _T_1295; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_1 <= 1'h0; end else begin - mhpmc_inc_r_d1_1 <= _T_1309 & _T_1589; + mhpmc_inc_r_d1_1 <= _T_1299 & _T_1579; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_2 <= 1'h0; end else begin - mhpmc_inc_r_d1_2 <= _T_1593 & _T_1873; + mhpmc_inc_r_d1_2 <= _T_1583 & _T_1863; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_3 <= 1'h0; end else begin - mhpmc_inc_r_d1_3 <= _T_1877 & _T_2157; + mhpmc_inc_r_d1_3 <= _T_1867 & _T_2147; end end always @(posedge io_free_clk or posedge reset) begin @@ -53772,30 +53761,30 @@ end // initial end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2330 <= 1'h0; + _T_2320 <= 1'h0; end else begin - _T_2330 <= io_i0_valid_wb; + _T_2320 <= io_i0_valid_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2335 <= 1'h0; + _T_2325 <= 1'h0; end else begin - _T_2335 <= _T_2331 | _T_2333; + _T_2325 <= _T_2321 | _T_2323; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2336 <= 5'h0; + _T_2326 <= 5'h0; end else begin - _T_2336 <= io_exc_cause_wb; + _T_2326 <= io_exc_cause_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2337 <= 1'h0; + _T_2327 <= 1'h0; end else begin - _T_2337 <= io_interrupt_valid_r_d1; + _T_2327 <= io_interrupt_valid_r_d1; end end endmodule @@ -53869,371 +53858,371 @@ module dec_decode_csr_read( output io_csr_pkt_postsync, output io_csr_pkt_legal ); - wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2569:129] - wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:129] - wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:129] - wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:129] - wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2569:198] - wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:129] - wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:129] - wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2569:198] - wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:165] - wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2569:198] - wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:129] - wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:129] - wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2569:198] - wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2569:198] - wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2569:198] - wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2569:129] - wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2637:81] - wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2637:121] - wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2637:155] - wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2638:97] - wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2639:81] - wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2639:121] - wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2639:162] - wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2569:198] - wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2569:198] - wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2640:105] - wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2640:145] - wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2569:198] - wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2569:198] - wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2569:198] - wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2642:81] - wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2642:129] - wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2643:105] - wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2643:153] - wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2644:105] - wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2644:153] - wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2645:105] - wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2645:161] - wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2646:105] - wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2646:161] - wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2647:97] - wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2647:153] - wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2648:105] - wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2648:161] - wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2649:105] - wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2649:161] - wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2650:105] - wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2650:161] - wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2651:105] - wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2651:161] - wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2652:105] - wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2652:153] - wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2653:113] - wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2653:161] - wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2654:97] - wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2654:153] - wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] - wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2655:113] - wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] - assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2571:57] - assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2572:57] - assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2573:57] - assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2574:57] - assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2575:57] - assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2576:57] - assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2577:57] - assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2578:65] - assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2579:65] - assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2580:57] - assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2581:57] - assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2582:57] - assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2583:57] - assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2584:57] - assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2585:57] - assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2586:57] - assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2587:57] - assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2588:57] - assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2589:57] - assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2590:57] - assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2591:57] - assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2592:57] - assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2593:57] - assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2594:57] - assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2595:57] - assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2596:57] - assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2597:57] - assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2598:57] - assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2599:57] - assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2600:65] - assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2601:57] - assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2602:57] - assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2603:57] - assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2604:57] - assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2605:57] - assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2606:57] - assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2607:57] - assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2608:57] - assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2609:57] - assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2610:57] - assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2611:57] - assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2612:57] - assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2613:57] - assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2614:57] - assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2615:57] - assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2616:49] - assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2617:57] - assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2618:57] - assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2619:57] - assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2620:57] - assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2621:57] - assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2622:57] - assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2623:57] - assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2625:57] - assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2627:57] - assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2628:57] - assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2629:57] - assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2630:57] - assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2631:57] - assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2632:57] - assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2633:57] - assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2634:57] - assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2635:57] - assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2636:57] - assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2637:34] - assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2639:30] - assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2642:26] + wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2551:129] + wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:129] + wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:129] + wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:129] + wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2551:198] + wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:129] + wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:129] + wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2551:198] + wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:165] + wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2551:198] + wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:129] + wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:129] + wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2551:198] + wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2551:198] + wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2551:198] + wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2551:129] + wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2619:81] + wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2619:121] + wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2619:155] + wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2620:97] + wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2621:81] + wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2621:121] + wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2621:162] + wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2551:198] + wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2551:198] + wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2622:105] + wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2622:145] + wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2551:198] + wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2551:198] + wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2551:198] + wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2624:81] + wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2624:129] + wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2625:105] + wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2625:153] + wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2626:105] + wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2626:153] + wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2627:105] + wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2627:161] + wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2628:105] + wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2628:161] + wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2629:97] + wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2629:153] + wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2630:105] + wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2630:161] + wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2631:105] + wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2631:161] + wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2632:105] + wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2632:161] + wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2633:105] + wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2633:161] + wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2634:105] + wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2634:153] + wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2635:113] + wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2635:161] + wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2636:97] + wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2636:153] + wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] + wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2637:113] + wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] + assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2553:57] + assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2554:57] + assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2555:57] + assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2556:57] + assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2557:57] + assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2558:57] + assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2559:57] + assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2560:65] + assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2561:65] + assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2562:57] + assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2563:57] + assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2564:57] + assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2565:57] + assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2566:57] + assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2567:57] + assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2568:57] + assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:57] + assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:57] + assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2571:57] + assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2572:57] + assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2573:57] + assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:57] + assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2575:57] + assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2576:57] + assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2577:57] + assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2578:57] + assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2579:57] + assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2580:57] + assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2581:57] + assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2582:65] + assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2583:57] + assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2584:57] + assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2585:57] + assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2586:57] + assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2587:57] + assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2588:57] + assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2589:57] + assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2590:57] + assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2591:57] + assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2592:57] + assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2593:57] + assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2594:57] + assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2595:57] + assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2596:57] + assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2597:57] + assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2598:49] + assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2599:57] + assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2600:57] + assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2601:57] + assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2602:57] + assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2603:57] + assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2604:57] + assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2605:57] + assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2607:57] + assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2609:57] + assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2610:57] + assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2611:57] + assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2612:57] + assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2613:57] + assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2614:57] + assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2615:57] + assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2616:57] + assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2617:57] + assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2618:57] + assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2619:34] + assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2621:30] + assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2624:26] endmodule module dec_tlu_ctl( input clock, @@ -54379,6 +54368,7 @@ module dec_tlu_ctl( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -54419,7 +54409,6 @@ module dec_tlu_ctl( input io_tlu_busbuff_lsu_pmu_bus_error, input io_tlu_busbuff_lsu_pmu_bus_busy, output io_tlu_busbuff_dec_tlu_external_ldfwd_disable, - output io_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_tlu_busbuff_lsu_imprecise_error_load_any, input io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -54510,26 +54499,26 @@ module dec_tlu_ctl( reg [31:0] _RAND_73; reg [31:0] _RAND_74; `endif // RANDOMIZE_REG_INIT - wire int_timers_clock; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_reset; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_free_clk; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_scan_mode; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 275:30] - wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 275:30] - wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 275:30] - wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_clock; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_reset; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_free_clk; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_scan_mode; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 275:32] + wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 275:32] + wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 275:32] + wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 275:32] wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] wire rvclkhdr_io_clk; // @[lib.scala 343:22] wire rvclkhdr_io_en; // @[lib.scala 343:22] @@ -54546,546 +54535,546 @@ module dec_tlu_ctl( wire rvclkhdr_3_io_clk; // @[lib.scala 343:22] wire rvclkhdr_3_io_en; // @[lib.scala 343:22] wire rvclkhdr_3_io_scan_mode; // @[lib.scala 343:22] - wire csr_clock; // @[dec_tlu_ctl.scala 816:15] - wire csr_reset; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_free_clk; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_active_clk; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_scan_mode; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 816:15] - wire [11:0] csr_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 816:15] - wire [11:0] csr_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 816:15] - wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 816:15] - wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 816:15] - wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 816:15] - wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 816:15] - wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 816:15] - wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 816:15] - wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 816:15] - wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 816:15] - wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 816:15] - wire [3:0] csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 816:15] - wire [29:0] csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 816:15] - wire [7:0] csr_io_pic_claimid; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 816:15] - wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_dec_illegal_inst; // @[dec_tlu_ctl.scala 816:15] - wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_mexintpend; // @[dec_tlu_ctl.scala 816:15] - wire [30:0] csr_io_exu_npc_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 816:15] - wire [30:0] csr_io_rst_vec; // @[dec_tlu_ctl.scala 816:15] - wire [27:0] csr_io_core_id; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 816:15] - wire [1:0] csr_io_mstatus; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_mret_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 816:15] - wire [15:0] csr_io_dcsr; // @[dec_tlu_ctl.scala 816:15] - wire [30:0] csr_io_mtvec; // @[dec_tlu_ctl.scala 816:15] - wire [5:0] csr_io_mip; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_timer_int_sync; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_soft_int_sync; // @[dec_tlu_ctl.scala 816:15] - wire [5:0] csr_io_mie_ns; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_wr_clk; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 816:15] - wire [1:0] csr_io_lsu_fir_error; // @[dec_tlu_ctl.scala 816:15] - wire [30:0] csr_io_npc_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire [30:0] csr_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire [30:0] csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_reset_delayed; // @[dec_tlu_ctl.scala 816:15] - wire [30:0] csr_io_mepc; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_e4e5_int_clk; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_inst_acc_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_inst_acc_second_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_take_nmi; // @[dec_tlu_ctl.scala 816:15] - wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[dec_tlu_ctl.scala 816:15] - wire [4:0] csr_io_exc_cause_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_i0_valid_wb; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_clk_override; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire [4:0] csr_io_exc_cause_wb; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ebreak_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ecall_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_illegal_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ic_perr_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_debug_halt_req_f; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_force_halt; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_take_ext_int_start; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_debug_halt_req; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_allow_dbg_halt_csr_write; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_enter_debug_halt_req; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_request_debug_mode_done; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_request_debug_mode_r; // @[dec_tlu_ctl.scala 816:15] - wire [30:0] csr_io_dpc; // @[dec_tlu_ctl.scala 816:15] - wire [3:0] csr_io_update_hit_bit_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_take_timer_int; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_take_ext_int; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 816:15] - wire csr_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 816:15] - wire [9:0] csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 816:15] - wire [9:0] csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 816:15] - wire [9:0] csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 816:15] - wire [9:0] csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 816:15] - wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1009:22] - wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1009:22] - reg dbg_halt_state_f; // @[dec_tlu_ctl.scala 365:89] + wire csr_clock; // @[dec_tlu_ctl.scala 813:15] + wire csr_reset; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_free_clk; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_active_clk; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_scan_mode; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 813:15] + wire [11:0] csr_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 813:15] + wire [11:0] csr_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 813:15] + wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 813:15] + wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 813:15] + wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 813:15] + wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 813:15] + wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 813:15] + wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 813:15] + wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 813:15] + wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 813:15] + wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 813:15] + wire [3:0] csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 813:15] + wire [29:0] csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 813:15] + wire [7:0] csr_io_pic_claimid; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 813:15] + wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_dec_illegal_inst; // @[dec_tlu_ctl.scala 813:15] + wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_mexintpend; // @[dec_tlu_ctl.scala 813:15] + wire [30:0] csr_io_exu_npc_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 813:15] + wire [30:0] csr_io_rst_vec; // @[dec_tlu_ctl.scala 813:15] + wire [27:0] csr_io_core_id; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 813:15] + wire [1:0] csr_io_mstatus; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_mret_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 813:15] + wire [15:0] csr_io_dcsr; // @[dec_tlu_ctl.scala 813:15] + wire [30:0] csr_io_mtvec; // @[dec_tlu_ctl.scala 813:15] + wire [5:0] csr_io_mip; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_timer_int_sync; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_soft_int_sync; // @[dec_tlu_ctl.scala 813:15] + wire [5:0] csr_io_mie_ns; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_wr_clk; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 813:15] + wire [1:0] csr_io_lsu_fir_error; // @[dec_tlu_ctl.scala 813:15] + wire [30:0] csr_io_npc_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire [30:0] csr_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire [30:0] csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_reset_delayed; // @[dec_tlu_ctl.scala 813:15] + wire [30:0] csr_io_mepc; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_e4e5_int_clk; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_inst_acc_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_inst_acc_second_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_take_nmi; // @[dec_tlu_ctl.scala 813:15] + wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[dec_tlu_ctl.scala 813:15] + wire [4:0] csr_io_exc_cause_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_i0_valid_wb; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_clk_override; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire [4:0] csr_io_exc_cause_wb; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ebreak_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ecall_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_illegal_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ic_perr_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_debug_halt_req_f; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_force_halt; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_take_ext_int_start; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_debug_halt_req; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_allow_dbg_halt_csr_write; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_enter_debug_halt_req; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_request_debug_mode_done; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_request_debug_mode_r; // @[dec_tlu_ctl.scala 813:15] + wire [30:0] csr_io_dpc; // @[dec_tlu_ctl.scala 813:15] + wire [3:0] csr_io_update_hit_bit_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_take_timer_int; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_take_ext_int; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 813:15] + wire [9:0] csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 813:15] + wire [9:0] csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 813:15] + wire [9:0] csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 813:15] + wire [9:0] csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 813:15] + wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1006:22] + wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1006:22] + reg dbg_halt_state_f; // @[dec_tlu_ctl.scala 365:114] wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 274:39] - reg mpc_halt_state_f; // @[dec_tlu_ctl.scala 360:89] + reg mpc_halt_state_f; // @[dec_tlu_ctl.scala 360:114] wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] reg [6:0] _T_8; // @[lib.scala 37:81] reg [6:0] syncro_ff; // @[lib.scala 37:58] - wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 302:67] - wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 305:59] - wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 306:59] - wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 307:51] - wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 308:51] - wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1002:31] - reg lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 611:74] - wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 312:67] - reg e5_valid; // @[dec_tlu_ctl.scala 324:97] - wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[dec_tlu_ctl.scala 315:30] - reg debug_mode_status; // @[dec_tlu_ctl.scala 325:81] - reg i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 571:80] - reg nmi_int_delayed; // @[dec_tlu_ctl.scala 338:72] + wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 302:76] + wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 305:64] + wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 306:66] + wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 307:52] + wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 308:56] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 999:31] + reg lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 609:74] + wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 312:71] + reg e5_valid; // @[dec_tlu_ctl.scala 324:138] + wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[dec_tlu_ctl.scala 315:39] + reg debug_mode_status; // @[dec_tlu_ctl.scala 325:90] + reg i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 569:81] + reg nmi_int_delayed; // @[dec_tlu_ctl.scala 338:81] wire _T_37 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 347:45] wire _T_38 = nmi_int_sync & _T_37; // @[dec_tlu_ctl.scala 347:43] - reg mdseac_locked_f; // @[dec_tlu_ctl.scala 604:89] + reg mdseac_locked_f; // @[dec_tlu_ctl.scala 602:89] wire _T_35 = ~mdseac_locked_f; // @[dec_tlu_ctl.scala 345:32] wire _T_36 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 345:96] wire nmi_lsu_detected = _T_35 & _T_36; // @[dec_tlu_ctl.scala 345:49] wire _T_39 = _T_38 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 347:63] - reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 339:72] - reg take_nmi_r_d1; // @[dec_tlu_ctl.scala 813:98] + reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 339:73] + reg take_nmi_r_d1; // @[dec_tlu_ctl.scala 810:107] wire _T_40 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 347:106] wire _T_41 = nmi_int_detected_f & _T_40; // @[dec_tlu_ctl.scala 347:104] wire _T_42 = _T_39 | _T_41; // @[dec_tlu_ctl.scala 347:82] - reg take_ext_int_start_d3; // @[dec_tlu_ctl.scala 744:62] + reg take_ext_int_start_d3; // @[dec_tlu_ctl.scala 742:74] wire _T_43 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 347:165] wire _T_44 = take_ext_int_start_d3 & _T_43; // @[dec_tlu_ctl.scala 347:146] wire nmi_int_detected = _T_42 | _T_44; // @[dec_tlu_ctl.scala 347:122] - wire _T_631 = ~io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 721:23] - wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 1001:31] - wire _T_632 = _T_631 & mstatus_mie_ns; // @[dec_tlu_ctl.scala 721:48] - wire [5:0] mip = csr_io_mip; // @[dec_tlu_ctl.scala 1007:31] - wire _T_634 = _T_632 & mip[1]; // @[dec_tlu_ctl.scala 721:65] - wire [5:0] mie_ns = csr_io_mie_ns; // @[dec_tlu_ctl.scala 996:31] - wire timer_int_ready = _T_634 & mie_ns[1]; // @[dec_tlu_ctl.scala 721:83] - wire _T_391 = nmi_int_detected | timer_int_ready; // @[dec_tlu_ctl.scala 598:66] - wire _T_628 = _T_632 & mip[0]; // @[dec_tlu_ctl.scala 720:65] - wire soft_int_ready = _T_628 & mie_ns[0]; // @[dec_tlu_ctl.scala 720:83] - wire _T_392 = _T_391 | soft_int_ready; // @[dec_tlu_ctl.scala 598:84] - reg int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 578:73] - wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 598:101] - reg int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 579:73] - wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 598:125] - wire _T_608 = _T_632 & mip[2]; // @[dec_tlu_ctl.scala 717:66] - wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[dec_tlu_ctl.scala 717:84] - wire _T_395 = io_dec_pic_mhwakeup & mhwakeup_ready; // @[dec_tlu_ctl.scala 598:172] - wire _T_396 = _T_394 | _T_395; // @[dec_tlu_ctl.scala 598:149] - wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[dec_tlu_ctl.scala 598:191] - reg i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 570:80] - wire _T_398 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 598:216] - wire _T_399 = _T_397 & _T_398; // @[dec_tlu_ctl.scala 598:214] - wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[dec_tlu_ctl.scala 598:45] - wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 316:50] - wire _T_685 = ~_T_43; // @[dec_tlu_ctl.scala 749:49] - wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 749:47] - wire _T_698 = ~soft_int_ready; // @[dec_tlu_ctl.scala 766:40] - wire _T_699 = timer_int_ready & _T_698; // @[dec_tlu_ctl.scala 766:38] - wire _T_617 = ~io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 718:104] - wire ext_int_ready = mhwakeup_ready & _T_617; // @[dec_tlu_ctl.scala 718:102] - wire _T_700 = ~ext_int_ready; // @[dec_tlu_ctl.scala 766:58] - wire _T_701 = _T_699 & _T_700; // @[dec_tlu_ctl.scala 766:56] - wire _T_622 = _T_632 & mip[5]; // @[dec_tlu_ctl.scala 719:65] - wire ce_int_ready = _T_622 & mie_ns[5]; // @[dec_tlu_ctl.scala 719:83] - wire _T_702 = ~ce_int_ready; // @[dec_tlu_ctl.scala 766:75] - wire _T_703 = _T_701 & _T_702; // @[dec_tlu_ctl.scala 766:73] + wire _T_631 = ~io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 719:23] + wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 998:31] + wire _T_632 = _T_631 & mstatus_mie_ns; // @[dec_tlu_ctl.scala 719:48] + wire [5:0] mip = csr_io_mip; // @[dec_tlu_ctl.scala 1004:31] + wire _T_634 = _T_632 & mip[1]; // @[dec_tlu_ctl.scala 719:65] + wire [5:0] mie_ns = csr_io_mie_ns; // @[dec_tlu_ctl.scala 993:31] + wire timer_int_ready = _T_634 & mie_ns[1]; // @[dec_tlu_ctl.scala 719:83] + wire _T_391 = nmi_int_detected | timer_int_ready; // @[dec_tlu_ctl.scala 596:66] + wire _T_628 = _T_632 & mip[0]; // @[dec_tlu_ctl.scala 718:65] + wire soft_int_ready = _T_628 & mie_ns[0]; // @[dec_tlu_ctl.scala 718:83] + wire _T_392 = _T_391 | soft_int_ready; // @[dec_tlu_ctl.scala 596:84] + reg int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 576:74] + wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 596:101] + reg int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 577:74] + wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 596:125] + wire _T_608 = _T_632 & mip[2]; // @[dec_tlu_ctl.scala 715:65] + wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[dec_tlu_ctl.scala 715:83] + wire _T_395 = io_dec_pic_mhwakeup & mhwakeup_ready; // @[dec_tlu_ctl.scala 596:172] + wire _T_396 = _T_394 | _T_395; // @[dec_tlu_ctl.scala 596:149] + wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[dec_tlu_ctl.scala 596:191] + reg i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 568:81] + wire _T_398 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 596:216] + wire _T_399 = _T_397 & _T_398; // @[dec_tlu_ctl.scala 596:214] + wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[dec_tlu_ctl.scala 596:45] + wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 316:55] + wire _T_685 = ~_T_43; // @[dec_tlu_ctl.scala 747:49] + wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 747:47] + wire _T_698 = ~soft_int_ready; // @[dec_tlu_ctl.scala 764:40] + wire _T_699 = timer_int_ready & _T_698; // @[dec_tlu_ctl.scala 764:38] + wire _T_617 = ~io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 716:104] + wire ext_int_ready = mhwakeup_ready & _T_617; // @[dec_tlu_ctl.scala 716:102] + wire _T_700 = ~ext_int_ready; // @[dec_tlu_ctl.scala 764:58] + wire _T_701 = _T_699 & _T_700; // @[dec_tlu_ctl.scala 764:56] + wire _T_622 = _T_632 & mip[5]; // @[dec_tlu_ctl.scala 717:65] + wire ce_int_ready = _T_622 & mie_ns[5]; // @[dec_tlu_ctl.scala 717:83] + wire _T_702 = ~ce_int_ready; // @[dec_tlu_ctl.scala 764:75] + wire _T_703 = _T_701 & _T_702; // @[dec_tlu_ctl.scala 764:73] wire _T_152 = ~debug_mode_status; // @[dec_tlu_ctl.scala 421:37] - reg dbg_halt_req_held; // @[dec_tlu_ctl.scala 464:81] + reg dbg_halt_req_held; // @[dec_tlu_ctl.scala 464:98] wire _T_106 = io_dbg_halt_req | dbg_halt_req_held; // @[dec_tlu_ctl.scala 398:48] - reg ext_int_freeze_d1; // @[dec_tlu_ctl.scala 745:66] + reg ext_int_freeze_d1; // @[dec_tlu_ctl.scala 743:90] wire _T_107 = ~ext_int_freeze_d1; // @[dec_tlu_ctl.scala 398:71] wire dbg_halt_req_final = _T_106 & _T_107; // @[dec_tlu_ctl.scala 398:69] - wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[dec_tlu_ctl.scala 357:67] + wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[dec_tlu_ctl.scala 357:70] wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 401:50] - reg reset_detect; // @[dec_tlu_ctl.scala 334:88] - reg reset_detected; // @[dec_tlu_ctl.scala 335:88] - wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 336:64] + reg reset_detect; // @[dec_tlu_ctl.scala 334:106] + reg reset_detected; // @[dec_tlu_ctl.scala 335:98] + wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 336:89] wire _T_110 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 401:95] wire _T_111 = reset_delayed & _T_110; // @[dec_tlu_ctl.scala 401:93] wire _T_112 = _T_109 | _T_111; // @[dec_tlu_ctl.scala 401:76] wire _T_114 = _T_112 & _T_152; // @[dec_tlu_ctl.scala 401:119] wire debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 401:147] wire _T_153 = _T_152 & debug_halt_req; // @[dec_tlu_ctl.scala 421:63] - reg dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 456:81] + reg dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 456:90] wire _T_154 = _T_153 | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 421:81] - reg trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 455:81] + reg trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 455:90] wire _T_155 = _T_154 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 421:107] - reg ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 670:64] + reg ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 668:64] wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 421:132] - reg debug_halt_req_f; // @[dec_tlu_ctl.scala 453:89] - wire force_halt = csr_io_force_halt; // @[dec_tlu_ctl.scala 999:31] - reg lsu_idle_any_f; // @[dec_tlu_ctl.scala 449:89] + reg debug_halt_req_f; // @[dec_tlu_ctl.scala 453:114] + wire force_halt = csr_io_force_halt; // @[dec_tlu_ctl.scala 996:31] + reg lsu_idle_any_f; // @[dec_tlu_ctl.scala 449:114] wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[dec_tlu_ctl.scala 415:53] wire _T_143 = _T_142 & io_tlu_mem_ifu_miss_state_idle; // @[dec_tlu_ctl.scala 415:70] - reg ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 450:81] + reg ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 450:98] wire _T_144 = _T_143 & ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 415:103] wire _T_145 = ~debug_halt_req; // @[dec_tlu_ctl.scala 415:129] wire _T_146 = _T_144 & _T_145; // @[dec_tlu_ctl.scala 415:127] - reg debug_halt_req_d1; // @[dec_tlu_ctl.scala 457:89] + reg debug_halt_req_d1; // @[dec_tlu_ctl.scala 457:114] wire _T_147 = ~debug_halt_req_d1; // @[dec_tlu_ctl.scala 415:147] wire _T_148 = _T_146 & _T_147; // @[dec_tlu_ctl.scala 415:145] wire _T_149 = ~io_dec_div_active; // @[dec_tlu_ctl.scala 415:168] wire _T_150 = _T_148 & _T_149; // @[dec_tlu_ctl.scala 415:166] wire core_empty = force_halt | _T_150; // @[dec_tlu_ctl.scala 415:34] wire _T_163 = debug_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 431:48] - reg dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 447:81] - reg dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 463:73] + reg dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 447:82] + reg dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 463:74] wire _T_132 = ~dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 411:56] wire _T_133 = dec_tlu_flush_noredir_r_d1 & _T_132; // @[dec_tlu_ctl.scala 411:54] - reg take_ext_int_start_d1; // @[dec_tlu_ctl.scala 742:62] + reg take_ext_int_start_d1; // @[dec_tlu_ctl.scala 740:74] wire _T_134 = ~take_ext_int_start_d1; // @[dec_tlu_ctl.scala 411:84] wire _T_135 = _T_133 & _T_134; // @[dec_tlu_ctl.scala 411:82] - reg halt_taken_f; // @[dec_tlu_ctl.scala 448:89] - reg dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 451:89] + reg halt_taken_f; // @[dec_tlu_ctl.scala 448:122] + reg dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 451:114] wire _T_136 = ~dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 411:126] wire _T_137 = halt_taken_f & _T_136; // @[dec_tlu_ctl.scala 411:124] - reg pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 577:73] + reg pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 575:74] wire _T_138 = ~pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 411:146] wire _T_139 = _T_137 & _T_138; // @[dec_tlu_ctl.scala 411:144] - reg interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 807:90] + reg interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 804:91] wire _T_140 = ~interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 411:169] wire _T_141 = _T_139 & _T_140; // @[dec_tlu_ctl.scala 411:167] wire halt_taken = _T_135 | _T_141; // @[dec_tlu_ctl.scala 411:108] wire _T_164 = _T_163 & halt_taken; // @[dec_tlu_ctl.scala 431:61] - reg debug_resume_req_f; // @[dec_tlu_ctl.scala 454:89] + reg debug_resume_req_f; // @[dec_tlu_ctl.scala 454:106] wire _T_165 = ~debug_resume_req_f; // @[dec_tlu_ctl.scala 431:97] wire _T_166 = dbg_tlu_halted_f & _T_165; // @[dec_tlu_ctl.scala 431:95] wire dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 431:75] wire _T_167 = ~dbg_tlu_halted; // @[dec_tlu_ctl.scala 432:73] wire _T_168 = debug_halt_req_f & _T_167; // @[dec_tlu_ctl.scala 432:71] wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[dec_tlu_ctl.scala 432:51] - wire [15:0] dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 1005:31] + wire [15:0] dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 1002:31] wire _T_157 = ~dcsr[2]; // @[dec_tlu_ctl.scala 424:106] wire _T_158 = debug_resume_req_f & _T_157; // @[dec_tlu_ctl.scala 424:104] wire _T_159 = ~_T_158; // @[dec_tlu_ctl.scala 424:83] wire _T_160 = debug_mode_status & _T_159; // @[dec_tlu_ctl.scala 424:81] wire internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 424:53] wire _T_177 = debug_resume_req_f & dcsr[2]; // @[dec_tlu_ctl.scala 437:60] - reg dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 462:73] + reg dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 462:66] wire _T_178 = ~dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 437:111] wire _T_179 = dcsr_single_step_running_f & _T_178; // @[dec_tlu_ctl.scala 437:109] wire dcsr_single_step_running = _T_177 | _T_179; // @[dec_tlu_ctl.scala 437:79] - wire _T_665 = ~dcsr_single_step_running; // @[dec_tlu_ctl.scala 738:55] - wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 738:81] - wire _T_667 = internal_dbg_halt_mode & _T_666; // @[dec_tlu_ctl.scala 738:52] - wire _T_346 = ~io_dec_tlu_debug_mode; // @[dec_tlu_ctl.scala 567:62] - wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[dec_tlu_ctl.scala 567:60] - wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[dec_tlu_ctl.scala 567:85] - wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[dec_tlu_ctl.scala 583:50] - wire fw_halt_req = csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 1003:31] - wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[dec_tlu_ctl.scala 584:48] - reg pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 576:73] - wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 589:45] - wire _T_372 = _T_371 & halt_taken; // @[dec_tlu_ctl.scala 589:58] - wire _T_373 = ~enter_debug_halt_req; // @[dec_tlu_ctl.scala 589:73] - wire _T_374 = _T_372 & _T_373; // @[dec_tlu_ctl.scala 589:71] - wire _T_375 = ~i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 589:121] - wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[dec_tlu_ctl.scala 589:119] - wire _T_377 = _T_374 | _T_376; // @[dec_tlu_ctl.scala 589:96] - wire _T_378 = ~debug_halt_req_f; // @[dec_tlu_ctl.scala 589:143] - wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[dec_tlu_ctl.scala 589:141] - wire _T_361 = ~pmu_fw_tlu_halted; // @[dec_tlu_ctl.scala 585:72] - wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[dec_tlu_ctl.scala 585:70] - wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[dec_tlu_ctl.scala 585:49] - wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[dec_tlu_ctl.scala 585:93] - reg internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 575:68] - wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[dec_tlu_ctl.scala 586:83] - wire _T_369 = _T_367 & _T_378; // @[dec_tlu_ctl.scala 586:103] - wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[dec_tlu_ctl.scala 586:52] - wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 738:107] - wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 738:135] - wire _T_738 = ~internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 770:35] - wire _T_739 = nmi_int_detected & _T_738; // @[dec_tlu_ctl.scala 770:33] - wire _T_740 = ~internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 770:65] - wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[dec_tlu_ctl.scala 770:119] - wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 770:141] - wire _T_744 = _T_742 & _T_743; // @[dec_tlu_ctl.scala 770:139] - wire _T_746 = _T_744 & _T_178; // @[dec_tlu_ctl.scala 770:164] - wire _T_747 = _T_740 | _T_746; // @[dec_tlu_ctl.scala 770:89] - wire _T_748 = _T_739 & _T_747; // @[dec_tlu_ctl.scala 770:62] - wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 656:51] - wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 656:64] + wire _T_665 = ~dcsr_single_step_running; // @[dec_tlu_ctl.scala 736:55] + wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 736:81] + wire _T_667 = internal_dbg_halt_mode & _T_666; // @[dec_tlu_ctl.scala 736:52] + wire _T_346 = ~io_dec_tlu_debug_mode; // @[dec_tlu_ctl.scala 565:62] + wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[dec_tlu_ctl.scala 565:60] + wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[dec_tlu_ctl.scala 565:85] + wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[dec_tlu_ctl.scala 581:50] + wire fw_halt_req = csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 1000:31] + wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[dec_tlu_ctl.scala 582:48] + reg pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 574:82] + wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 587:45] + wire _T_372 = _T_371 & halt_taken; // @[dec_tlu_ctl.scala 587:58] + wire _T_373 = ~enter_debug_halt_req; // @[dec_tlu_ctl.scala 587:73] + wire _T_374 = _T_372 & _T_373; // @[dec_tlu_ctl.scala 587:71] + wire _T_375 = ~i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 587:121] + wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[dec_tlu_ctl.scala 587:119] + wire _T_377 = _T_374 | _T_376; // @[dec_tlu_ctl.scala 587:96] + wire _T_378 = ~debug_halt_req_f; // @[dec_tlu_ctl.scala 587:143] + wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[dec_tlu_ctl.scala 587:141] + wire _T_361 = ~pmu_fw_tlu_halted; // @[dec_tlu_ctl.scala 583:72] + wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[dec_tlu_ctl.scala 583:70] + wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[dec_tlu_ctl.scala 583:49] + wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[dec_tlu_ctl.scala 583:93] + reg internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 573:70] + wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[dec_tlu_ctl.scala 584:83] + wire _T_369 = _T_367 & _T_378; // @[dec_tlu_ctl.scala 584:103] + wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[dec_tlu_ctl.scala 584:52] + wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 736:107] + wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 736:135] + wire _T_738 = ~internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 768:35] + wire _T_739 = nmi_int_detected & _T_738; // @[dec_tlu_ctl.scala 768:33] + wire _T_740 = ~internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 768:65] + wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[dec_tlu_ctl.scala 768:119] + wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 768:141] + wire _T_744 = _T_742 & _T_743; // @[dec_tlu_ctl.scala 768:139] + wire _T_746 = _T_744 & _T_178; // @[dec_tlu_ctl.scala 768:164] + wire _T_747 = _T_740 | _T_746; // @[dec_tlu_ctl.scala 768:89] + wire _T_748 = _T_739 & _T_747; // @[dec_tlu_ctl.scala 768:62] + wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 654:52] + wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 654:65] wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 518:58] wire [3:0] _T_299 = _T_297 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] wire [3:0] _T_300 = ~_T_299; // @[dec_tlu_ctl.scala 518:23] wire [3:0] _T_292 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 516:53] - wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1008:33] - wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1008:33] - wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1008:33] - wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1008:33] + wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1005:31] + wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1005:31] + wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1005:31] + wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1005:31] wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58] wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58] wire [3:0] _T_279 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 508:57] - wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 664:49] + wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 662:49] wire [3:0] _T_281 = inst_acc_r_raw ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] wire [3:0] _T_282 = _T_279 & _T_281; // @[dec_tlu_ctl.scala 508:72] wire _T_283 = io_tlu_exu_exu_i0_br_error_r | io_tlu_exu_exu_i0_br_start_error_r; // @[dec_tlu_ctl.scala 508:137] @@ -55099,7 +55088,7 @@ module dec_tlu_ctl( wire [3:0] _T_290 = _T_287 & _T_289; // @[dec_tlu_ctl.scala 511:66] wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[dec_tlu_ctl.scala 511:35] wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[dec_tlu_ctl.scala 516:119] - wire [1:0] mstatus = csr_io_mstatus; // @[dec_tlu_ctl.scala 1004:31] + wire [1:0] mstatus = csr_io_mstatus; // @[dec_tlu_ctl.scala 1001:31] wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[dec_tlu_ctl.scala 505:62] wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 505:86] wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[dec_tlu_ctl.scala 505:150] @@ -55123,86 +55112,86 @@ module dec_tlu_ctl( wire _T_324 = i0_trigger_r[0] & _T_323; // @[dec_tlu_ctl.scala 521:261] wire [3:0] i0_trigger_chain_masked_r = {_T_306,_T_312,_T_318,_T_324}; // @[Cat.scala 29:58] wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 524:57] - wire _T_465 = ~i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 656:90] - wire _T_466 = _T_464 & _T_465; // @[dec_tlu_ctl.scala 656:88] - wire _T_468 = ~dcsr[15]; // @[dec_tlu_ctl.scala 656:110] - wire _T_469 = _T_466 & _T_468; // @[dec_tlu_ctl.scala 656:108] - reg tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 328:80] - wire _T_429 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 631:44] - wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[dec_tlu_ctl.scala 631:42] - wire _T_432 = _T_430 & _T_283; // @[dec_tlu_ctl.scala 631:66] - reg ic_perr_r_d1; // @[dec_tlu_ctl.scala 322:89] - reg iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 323:89] - wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 631:154] - wire _T_435 = _T_433 & _T_107; // @[dec_tlu_ctl.scala 631:173] - wire _T_436 = _T_432 | _T_435; // @[dec_tlu_ctl.scala 631:137] - wire _T_438 = _T_436 & _T_465; // @[dec_tlu_ctl.scala 631:196] - wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[dec_tlu_ctl.scala 619:47] - wire _T_411 = ~io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 619:70] - wire _T_412 = _T_411 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec_tlu_ctl.scala 619:105] - wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[dec_tlu_ctl.scala 619:67] - wire _T_439 = ~lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 631:220] - wire rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 631:217] - wire _T_470 = ~rfpc_i0_r; // @[dec_tlu_ctl.scala 656:132] - wire ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 656:130] - wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[dec_tlu_ctl.scala 657:51] - wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 657:64] - wire _T_475 = _T_473 & _T_465; // @[dec_tlu_ctl.scala 657:88] - wire ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 657:108] - wire _T_523 = ebreak_r | ecall_r; // @[dec_tlu_ctl.scala 684:41] - wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[dec_tlu_ctl.scala 658:17] - wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 658:46] - wire _T_481 = _T_479 & _T_465; // @[dec_tlu_ctl.scala 658:70] - wire illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 658:90] - wire _T_524 = _T_523 | illegal_r; // @[dec_tlu_ctl.scala 684:51] - wire _T_511 = inst_acc_r_raw & _T_470; // @[dec_tlu_ctl.scala 665:33] - wire inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 665:46] - wire _T_525 = _T_524 | inst_acc_r; // @[dec_tlu_ctl.scala 684:63] - wire _T_527 = _T_525 & _T_470; // @[dec_tlu_ctl.scala 684:77] - wire _T_528 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 684:92] - wire i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 684:90] - wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[dec_tlu_ctl.scala 783:49] - wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 607:57] - wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[dec_tlu_ctl.scala 607:55] - wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 609:40] - wire _T_405 = _T_403 & _T_465; // @[dec_tlu_ctl.scala 609:62] - wire lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 609:82] - wire _T_790 = _T_789 | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 783:61] - wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 661:50] - wire _T_492 = _T_490 & _T_465; // @[dec_tlu_ctl.scala 661:74] - wire fence_i_r = _T_492 & _T_470; // @[dec_tlu_ctl.scala 661:95] - wire _T_791 = _T_790 | fence_i_r; // @[dec_tlu_ctl.scala 783:79] - wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 783:91] - wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[dec_tlu_ctl.scala 622:50] - wire _T_415 = ~lsu_exc_valid_r; // @[dec_tlu_ctl.scala 622:65] - wire _T_416 = _T_414 & _T_415; // @[dec_tlu_ctl.scala 622:63] - wire _T_417 = ~inst_acc_r; // @[dec_tlu_ctl.scala 622:82] - wire _T_418 = _T_416 & _T_417; // @[dec_tlu_ctl.scala 622:79] - wire _T_420 = _T_418 & _T_528; // @[dec_tlu_ctl.scala 622:94] - reg request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 460:81] - wire _T_421 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 622:121] - wire _T_422 = _T_420 & _T_421; // @[dec_tlu_ctl.scala 622:119] - wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 622:146] - reg iccm_repair_state_d1; // @[dec_tlu_ctl.scala 321:80] - wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 640:52] - wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 659:51] - wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 659:64] - wire _T_487 = _T_485 & _T_465; // @[dec_tlu_ctl.scala 659:88] - wire mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 659:108] - wire _T_446 = _T_523 | mret_r; // @[dec_tlu_ctl.scala 640:98] - wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 769:32] - wire _T_447 = _T_446 | take_reset; // @[dec_tlu_ctl.scala 640:107] - wire _T_448 = _T_447 | illegal_r; // @[dec_tlu_ctl.scala 640:120] - wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 640:176] - wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[dec_tlu_ctl.scala 640:153] - wire _T_451 = _T_448 | _T_450; // @[dec_tlu_ctl.scala 640:132] - wire _T_452 = ~_T_451; // @[dec_tlu_ctl.scala 640:77] - wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[dec_tlu_ctl.scala 640:75] - wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 783:108] - wire _T_794 = _T_793 | debug_resume_req_f; // @[dec_tlu_ctl.scala 783:135] - wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 781:43] + wire _T_465 = ~i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 654:91] + wire _T_466 = _T_464 & _T_465; // @[dec_tlu_ctl.scala 654:89] + wire _T_468 = ~dcsr[15]; // @[dec_tlu_ctl.scala 654:111] + wire _T_469 = _T_466 & _T_468; // @[dec_tlu_ctl.scala 654:109] + reg tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 328:90] + wire _T_429 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 629:44] + wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[dec_tlu_ctl.scala 629:42] + wire _T_432 = _T_430 & _T_283; // @[dec_tlu_ctl.scala 629:66] + reg ic_perr_r_d1; // @[dec_tlu_ctl.scala 322:122] + reg iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 323:114] + wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 629:154] + wire _T_435 = _T_433 & _T_107; // @[dec_tlu_ctl.scala 629:173] + wire _T_436 = _T_432 | _T_435; // @[dec_tlu_ctl.scala 629:137] + wire _T_438 = _T_436 & _T_465; // @[dec_tlu_ctl.scala 629:196] + wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[dec_tlu_ctl.scala 617:47] + wire _T_411 = ~io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 617:70] + wire _T_412 = _T_411 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec_tlu_ctl.scala 617:105] + wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[dec_tlu_ctl.scala 617:67] + wire _T_439 = ~lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 629:220] + wire rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 629:217] + wire _T_470 = ~rfpc_i0_r; // @[dec_tlu_ctl.scala 654:133] + wire ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 654:131] + wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[dec_tlu_ctl.scala 655:52] + wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 655:65] + wire _T_475 = _T_473 & _T_465; // @[dec_tlu_ctl.scala 655:89] + wire ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 655:109] + wire _T_523 = ebreak_r | ecall_r; // @[dec_tlu_ctl.scala 682:41] + wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[dec_tlu_ctl.scala 656:18] + wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 656:47] + wire _T_481 = _T_479 & _T_465; // @[dec_tlu_ctl.scala 656:71] + wire illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 656:91] + wire _T_524 = _T_523 | illegal_r; // @[dec_tlu_ctl.scala 682:51] + wire _T_511 = inst_acc_r_raw & _T_470; // @[dec_tlu_ctl.scala 663:33] + wire inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 663:46] + wire _T_525 = _T_524 | inst_acc_r; // @[dec_tlu_ctl.scala 682:63] + wire _T_527 = _T_525 & _T_470; // @[dec_tlu_ctl.scala 682:77] + wire _T_528 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 682:92] + wire i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 682:90] + wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[dec_tlu_ctl.scala 781:49] + wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 605:57] + wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[dec_tlu_ctl.scala 605:55] + wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 607:40] + wire _T_405 = _T_403 & _T_465; // @[dec_tlu_ctl.scala 607:62] + wire lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 607:82] + wire _T_790 = _T_789 | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 781:61] + wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 659:50] + wire _T_492 = _T_490 & _T_465; // @[dec_tlu_ctl.scala 659:74] + wire fence_i_r = _T_492 & _T_470; // @[dec_tlu_ctl.scala 659:95] + wire _T_791 = _T_790 | fence_i_r; // @[dec_tlu_ctl.scala 781:79] + wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 781:91] + wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[dec_tlu_ctl.scala 620:50] + wire _T_415 = ~lsu_exc_valid_r; // @[dec_tlu_ctl.scala 620:65] + wire _T_416 = _T_414 & _T_415; // @[dec_tlu_ctl.scala 620:63] + wire _T_417 = ~inst_acc_r; // @[dec_tlu_ctl.scala 620:82] + wire _T_418 = _T_416 & _T_417; // @[dec_tlu_ctl.scala 620:79] + wire _T_420 = _T_418 & _T_528; // @[dec_tlu_ctl.scala 620:94] + reg request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 460:82] + wire _T_421 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 620:121] + wire _T_422 = _T_420 & _T_421; // @[dec_tlu_ctl.scala 620:119] + wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 620:146] + reg iccm_repair_state_d1; // @[dec_tlu_ctl.scala 321:90] + wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 638:52] + wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 657:58] + wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 657:71] + wire _T_487 = _T_485 & _T_465; // @[dec_tlu_ctl.scala 657:95] + wire mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 657:115] + wire _T_446 = _T_523 | mret_r; // @[dec_tlu_ctl.scala 638:98] + wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 767:32] + wire _T_447 = _T_446 | take_reset; // @[dec_tlu_ctl.scala 638:107] + wire _T_448 = _T_447 | illegal_r; // @[dec_tlu_ctl.scala 638:120] + wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 638:176] + wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[dec_tlu_ctl.scala 638:153] + wire _T_451 = _T_448 | _T_450; // @[dec_tlu_ctl.scala 638:132] + wire _T_452 = ~_T_451; // @[dec_tlu_ctl.scala 638:77] + wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[dec_tlu_ctl.scala 638:75] + wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 781:108] + wire _T_794 = _T_793 | debug_resume_req_f; // @[dec_tlu_ctl.scala 781:135] + wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 779:43] wire _T_211 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 480:28] - reg dec_pause_state_f; // @[dec_tlu_ctl.scala 459:81] + reg dec_pause_state_f; // @[dec_tlu_ctl.scala 459:98] wire _T_212 = _T_211 & dec_pause_state_f; // @[dec_tlu_ctl.scala 480:48] wire _T_213 = ext_int_ready | ce_int_ready; // @[dec_tlu_ctl.scala 480:86] wire _T_214 = _T_213 | timer_int_ready; // @[dec_tlu_ctl.scala 480:101] @@ -55219,92 +55208,92 @@ module dec_tlu_ctl( wire _T_227 = _T_225 & _T_226; // @[dec_tlu_ctl.scala 480:268] wire _T_228 = ~halt_taken_f; // @[dec_tlu_ctl.scala 480:291] wire pause_expired_r = _T_227 & _T_228; // @[dec_tlu_ctl.scala 480:289] - wire sel_npc_resume = _T_786 | pause_expired_r; // @[dec_tlu_ctl.scala 781:66] - wire _T_795 = _T_794 | sel_npc_resume; // @[dec_tlu_ctl.scala 783:157] - reg dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 458:81] - wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 783:175] - wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 783:201] - wire _T_749 = ~synchronous_flush_r; // @[dec_tlu_ctl.scala 770:195] - wire _T_750 = _T_748 & _T_749; // @[dec_tlu_ctl.scala 770:193] - wire _T_751 = ~mret_r; // @[dec_tlu_ctl.scala 770:218] - wire _T_752 = _T_750 & _T_751; // @[dec_tlu_ctl.scala 770:216] - wire _T_753 = ~take_reset; // @[dec_tlu_ctl.scala 770:228] - wire _T_754 = _T_752 & _T_753; // @[dec_tlu_ctl.scala 770:226] - wire _T_519 = _T_466 & dcsr[15]; // @[dec_tlu_ctl.scala 668:121] - wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 668:142] - wire _T_755 = ~ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 770:242] - wire _T_756 = _T_754 & _T_755; // @[dec_tlu_ctl.scala 770:240] - wire _T_760 = _T_107 | _T_44; // @[dec_tlu_ctl.scala 770:288] - wire take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 770:266] - wire _T_670 = _T_669 | take_nmi; // @[dec_tlu_ctl.scala 738:155] - wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 738:166] - wire _T_672 = _T_671 | synchronous_flush_r; // @[dec_tlu_ctl.scala 738:191] - reg exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 809:90] - wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 738:214] - wire _T_674 = _T_673 | mret_r; // @[dec_tlu_ctl.scala 738:238] - wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 738:247] - wire _T_704 = ~block_interrupts; // @[dec_tlu_ctl.scala 766:91] - wire take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 766:89] - wire _T_762 = take_ext_int | take_timer_int; // @[dec_tlu_ctl.scala 773:38] - wire _T_693 = soft_int_ready & _T_700; // @[dec_tlu_ctl.scala 765:36] - wire _T_695 = _T_693 & _T_702; // @[dec_tlu_ctl.scala 765:53] - wire take_soft_int = _T_695 & _T_704; // @[dec_tlu_ctl.scala 765:69] - wire _T_763 = _T_762 | take_soft_int; // @[dec_tlu_ctl.scala 773:55] - wire _T_764 = _T_763 | take_nmi; // @[dec_tlu_ctl.scala 773:71] - wire _T_689 = ce_int_ready & _T_700; // @[dec_tlu_ctl.scala 764:33] - wire take_ce_int = _T_689 & _T_704; // @[dec_tlu_ctl.scala 764:50] - wire _T_765 = _T_764 | take_ce_int; // @[dec_tlu_ctl.scala 773:82] - wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[dec_tlu_ctl.scala 724:49] - wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[dec_tlu_ctl.scala 725:47] - wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 767:49] - wire _T_707 = _T_706 & int_timer0_int_possible; // @[dec_tlu_ctl.scala 767:74] - wire _T_709 = _T_707 & _T_631; // @[dec_tlu_ctl.scala 767:100] - wire _T_710 = ~timer_int_ready; // @[dec_tlu_ctl.scala 767:129] - wire _T_711 = _T_709 & _T_710; // @[dec_tlu_ctl.scala 767:127] - wire _T_713 = _T_711 & _T_698; // @[dec_tlu_ctl.scala 767:146] - wire _T_715 = _T_713 & _T_700; // @[dec_tlu_ctl.scala 767:164] - wire _T_717 = _T_715 & _T_702; // @[dec_tlu_ctl.scala 767:181] - wire take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 767:197] - wire _T_766 = _T_765 | take_int_timer0_int; // @[dec_tlu_ctl.scala 773:96] - wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[dec_tlu_ctl.scala 726:49] - wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[dec_tlu_ctl.scala 727:47] - wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 768:49] - wire _T_721 = _T_720 & int_timer1_int_possible; // @[dec_tlu_ctl.scala 768:74] - wire _T_723 = _T_721 & _T_631; // @[dec_tlu_ctl.scala 768:100] - wire _T_725 = ~_T_706; // @[dec_tlu_ctl.scala 768:129] - wire _T_726 = _T_723 & _T_725; // @[dec_tlu_ctl.scala 768:127] - wire _T_728 = _T_726 & _T_710; // @[dec_tlu_ctl.scala 768:177] - wire _T_730 = _T_728 & _T_698; // @[dec_tlu_ctl.scala 768:196] - wire _T_732 = _T_730 & _T_700; // @[dec_tlu_ctl.scala 768:214] - wire _T_734 = _T_732 & _T_702; // @[dec_tlu_ctl.scala 768:231] - wire take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 768:247] - wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 773:118] - wire _T_15 = _T_14 | interrupt_valid_r; // @[dec_tlu_ctl.scala 316:69] - wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 316:89] - wire _T_17 = _T_16 | reset_delayed; // @[dec_tlu_ctl.scala 316:112] - wire _T_18 = _T_17 | pause_expired_r; // @[dec_tlu_ctl.scala 316:128] - reg pause_expired_wb; // @[dec_tlu_ctl.scala 814:90] - wire _T_19 = _T_18 | pause_expired_wb; // @[dec_tlu_ctl.scala 316:146] - wire _T_496 = io_tlu_mem_ifu_ic_error_start & _T_107; // @[dec_tlu_ctl.scala 662:51] - wire _T_498 = _T_152 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 662:101] - wire _T_499 = _T_496 & _T_498; // @[dec_tlu_ctl.scala 662:72] - wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 662:131] - wire ic_perr_r = _T_499 & _T_500; // @[dec_tlu_ctl.scala 662:129] - wire _T_20 = _T_19 | ic_perr_r; // @[dec_tlu_ctl.scala 316:165] - wire _T_21 = _T_20 | ic_perr_r_d1; // @[dec_tlu_ctl.scala 316:177] - wire _T_503 = io_tlu_mem_ifu_iccm_rd_ecc_single_err & _T_107; // @[dec_tlu_ctl.scala 663:59] - wire _T_506 = _T_503 & _T_498; // @[dec_tlu_ctl.scala 663:80] - wire iccm_sbecc_r = _T_506 & _T_500; // @[dec_tlu_ctl.scala 663:137] - wire _T_22 = _T_21 | iccm_sbecc_r; // @[dec_tlu_ctl.scala 316:192] - wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 316:207] - wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 316:225] - reg lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 326:80] - reg lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 327:72] - reg _T_32; // @[dec_tlu_ctl.scala 329:73] - reg internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 330:72] - reg _T_33; // @[dec_tlu_ctl.scala 331:89] - reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 340:72] - reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 341:72] + wire sel_npc_resume = _T_786 | pause_expired_r; // @[dec_tlu_ctl.scala 779:66] + wire _T_795 = _T_794 | sel_npc_resume; // @[dec_tlu_ctl.scala 781:157] + reg dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 458:90] + wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 781:175] + wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 781:201] + wire _T_749 = ~synchronous_flush_r; // @[dec_tlu_ctl.scala 768:195] + wire _T_750 = _T_748 & _T_749; // @[dec_tlu_ctl.scala 768:193] + wire _T_751 = ~mret_r; // @[dec_tlu_ctl.scala 768:218] + wire _T_752 = _T_750 & _T_751; // @[dec_tlu_ctl.scala 768:216] + wire _T_753 = ~take_reset; // @[dec_tlu_ctl.scala 768:228] + wire _T_754 = _T_752 & _T_753; // @[dec_tlu_ctl.scala 768:226] + wire _T_519 = _T_466 & dcsr[15]; // @[dec_tlu_ctl.scala 666:121] + wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 666:142] + wire _T_755 = ~ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 768:242] + wire _T_756 = _T_754 & _T_755; // @[dec_tlu_ctl.scala 768:240] + wire _T_760 = _T_107 | _T_44; // @[dec_tlu_ctl.scala 768:288] + wire take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 768:266] + wire _T_670 = _T_669 | take_nmi; // @[dec_tlu_ctl.scala 736:155] + wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 736:166] + wire _T_672 = _T_671 | synchronous_flush_r; // @[dec_tlu_ctl.scala 736:191] + reg exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 806:91] + wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 736:214] + wire _T_674 = _T_673 | mret_r; // @[dec_tlu_ctl.scala 736:238] + wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 736:247] + wire _T_704 = ~block_interrupts; // @[dec_tlu_ctl.scala 764:91] + wire take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 764:89] + wire _T_762 = take_ext_int | take_timer_int; // @[dec_tlu_ctl.scala 771:38] + wire _T_693 = soft_int_ready & _T_700; // @[dec_tlu_ctl.scala 763:36] + wire _T_695 = _T_693 & _T_702; // @[dec_tlu_ctl.scala 763:53] + wire take_soft_int = _T_695 & _T_704; // @[dec_tlu_ctl.scala 763:69] + wire _T_763 = _T_762 | take_soft_int; // @[dec_tlu_ctl.scala 771:55] + wire _T_764 = _T_763 | take_nmi; // @[dec_tlu_ctl.scala 771:71] + wire _T_689 = ce_int_ready & _T_700; // @[dec_tlu_ctl.scala 762:33] + wire take_ce_int = _T_689 & _T_704; // @[dec_tlu_ctl.scala 762:50] + wire _T_765 = _T_764 | take_ce_int; // @[dec_tlu_ctl.scala 771:82] + wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[dec_tlu_ctl.scala 722:49] + wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[dec_tlu_ctl.scala 723:47] + wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 765:49] + wire _T_707 = _T_706 & int_timer0_int_possible; // @[dec_tlu_ctl.scala 765:74] + wire _T_709 = _T_707 & _T_631; // @[dec_tlu_ctl.scala 765:100] + wire _T_710 = ~timer_int_ready; // @[dec_tlu_ctl.scala 765:129] + wire _T_711 = _T_709 & _T_710; // @[dec_tlu_ctl.scala 765:127] + wire _T_713 = _T_711 & _T_698; // @[dec_tlu_ctl.scala 765:146] + wire _T_715 = _T_713 & _T_700; // @[dec_tlu_ctl.scala 765:164] + wire _T_717 = _T_715 & _T_702; // @[dec_tlu_ctl.scala 765:181] + wire take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 765:197] + wire _T_766 = _T_765 | take_int_timer0_int; // @[dec_tlu_ctl.scala 771:96] + wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[dec_tlu_ctl.scala 724:49] + wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[dec_tlu_ctl.scala 725:47] + wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 766:49] + wire _T_721 = _T_720 & int_timer1_int_possible; // @[dec_tlu_ctl.scala 766:74] + wire _T_723 = _T_721 & _T_631; // @[dec_tlu_ctl.scala 766:100] + wire _T_725 = ~_T_706; // @[dec_tlu_ctl.scala 766:129] + wire _T_726 = _T_723 & _T_725; // @[dec_tlu_ctl.scala 766:127] + wire _T_728 = _T_726 & _T_710; // @[dec_tlu_ctl.scala 766:177] + wire _T_730 = _T_728 & _T_698; // @[dec_tlu_ctl.scala 766:196] + wire _T_732 = _T_730 & _T_700; // @[dec_tlu_ctl.scala 766:214] + wire _T_734 = _T_732 & _T_702; // @[dec_tlu_ctl.scala 766:231] + wire take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 766:247] + wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 771:118] + wire _T_15 = _T_14 | interrupt_valid_r; // @[dec_tlu_ctl.scala 316:74] + wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 316:94] + wire _T_17 = _T_16 | reset_delayed; // @[dec_tlu_ctl.scala 316:117] + wire _T_18 = _T_17 | pause_expired_r; // @[dec_tlu_ctl.scala 316:133] + reg pause_expired_wb; // @[dec_tlu_ctl.scala 811:91] + wire _T_19 = _T_18 | pause_expired_wb; // @[dec_tlu_ctl.scala 316:151] + wire _T_496 = io_tlu_mem_ifu_ic_error_start & _T_107; // @[dec_tlu_ctl.scala 660:51] + wire _T_498 = _T_152 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 660:101] + wire _T_499 = _T_496 & _T_498; // @[dec_tlu_ctl.scala 660:72] + wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 660:131] + wire ic_perr_r = _T_499 & _T_500; // @[dec_tlu_ctl.scala 660:129] + wire _T_20 = _T_19 | ic_perr_r; // @[dec_tlu_ctl.scala 316:170] + wire _T_21 = _T_20 | ic_perr_r_d1; // @[dec_tlu_ctl.scala 316:182] + wire _T_503 = io_tlu_mem_ifu_iccm_rd_ecc_single_err & _T_107; // @[dec_tlu_ctl.scala 661:59] + wire _T_506 = _T_503 & _T_498; // @[dec_tlu_ctl.scala 661:80] + wire iccm_sbecc_r = _T_506 & _T_500; // @[dec_tlu_ctl.scala 661:137] + wire _T_22 = _T_21 | iccm_sbecc_r; // @[dec_tlu_ctl.scala 316:197] + wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 316:212] + wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 316:230] + reg lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 326:82] + reg lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 327:74] + reg _T_32; // @[dec_tlu_ctl.scala 329:74] + reg internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 330:74] + reg _T_33; // @[dec_tlu_ctl.scala 331:74] + reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 340:73] + reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 341:73] wire _T_46 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 349:48] wire _T_49 = ~_T_41; // @[dec_tlu_ctl.scala 349:96] wire _T_50 = _T_46 & _T_49; // @[dec_tlu_ctl.scala 349:94] @@ -55312,14 +55301,14 @@ module dec_tlu_ctl( wire _T_54 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 350:49] wire _T_58 = _T_54 & _T_49; // @[dec_tlu_ctl.scala 350:96] wire _T_60 = nmi_lsu_store_type_f & _T_40; // @[dec_tlu_ctl.scala 350:162] - reg mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 358:72] - reg mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 359:72] - reg mpc_run_state_f; // @[dec_tlu_ctl.scala 361:88] - reg debug_brkpt_status_f; // @[dec_tlu_ctl.scala 362:80] - reg mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 363:80] - reg mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 364:80] - reg dbg_run_state_f; // @[dec_tlu_ctl.scala 366:88] - reg _T_65; // @[dec_tlu_ctl.scala 367:81] + reg mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 358:74] + reg mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 359:74] + reg mpc_run_state_f; // @[dec_tlu_ctl.scala 361:106] + reg debug_brkpt_status_f; // @[dec_tlu_ctl.scala 362:90] + reg mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 363:90] + reg mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 364:90] + reg dbg_run_state_f; // @[dec_tlu_ctl.scala 366:106] + reg _T_65; // @[dec_tlu_ctl.scala 367:82] wire _T_66 = ~mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 371:71] wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_66; // @[dec_tlu_ctl.scala 371:69] wire _T_67 = ~mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 372:70] @@ -55376,15 +55365,15 @@ module dec_tlu_ctl( wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 538:45] wire _T_180 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 442:57] wire _T_182 = request_debug_mode_r_d1 & _T_402; // @[dec_tlu_ctl.scala 442:110] - reg request_debug_mode_done_f; // @[dec_tlu_ctl.scala 461:73] + reg request_debug_mode_done_f; // @[dec_tlu_ctl.scala 461:74] wire _T_183 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[dec_tlu_ctl.scala 444:64] - reg _T_190; // @[dec_tlu_ctl.scala 452:81] + reg _T_190; // @[dec_tlu_ctl.scala 452:98] wire _T_201 = fence_i_r & internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 473:71] wire _T_202 = take_halt | _T_201; // @[dec_tlu_ctl.scala 473:58] wire _T_203 = _T_202 | io_dec_tlu_flush_pause_r; // @[dec_tlu_ctl.scala 473:97] wire _T_204 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 473:144] wire _T_205 = _T_203 | _T_204; // @[dec_tlu_ctl.scala 473:124] - wire take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 746:45] + wire take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 744:66] wire _T_207 = ~interrupt_valid_r; // @[dec_tlu_ctl.scala 478:61] wire _T_208 = dec_tlu_wr_pause_r_d1 & _T_207; // @[dec_tlu_ctl.scala 478:59] wire _T_209 = ~take_ext_int_start; // @[dec_tlu_ctl.scala 478:82] @@ -55395,56 +55384,56 @@ module dec_tlu_ctl( wire [3:0] _T_342 = i0_trigger_hit_raw_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] wire _T_345 = ~trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 540:55] wire mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 540:53] - wire _T_350 = i_cpu_run_req_sync & _T_346; // @[dec_tlu_ctl.scala 568:58] - wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 568:83] - wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[dec_tlu_ctl.scala 568:105] - reg _T_353; // @[dec_tlu_ctl.scala 572:81] - reg _T_354; // @[dec_tlu_ctl.scala 573:81] - reg _T_355; // @[dec_tlu_ctl.scala 574:81] - wire _T_384 = io_o_cpu_halt_status & _T_375; // @[dec_tlu_ctl.scala 592:89] - wire _T_386 = _T_384 & _T_152; // @[dec_tlu_ctl.scala 592:109] - wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 593:41] - wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 593:88] - reg lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 605:72] - reg lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 612:73] - wire _T_408 = ~io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 613:40] - wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[dec_tlu_ctl.scala 613:38] - wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 614:38] - wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 615:38] - wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 625:38] - wire _T_425 = _T_424 | inst_acc_r; // @[dec_tlu_ctl.scala 625:53] - wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 625:79] - wire _T_427 = _T_425 | _T_426; // @[dec_tlu_ctl.scala 625:66] - wire _T_441 = ~io_tlu_exu_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 634:70] - wire _T_442 = iccm_repair_state_d1 & _T_441; // @[dec_tlu_ctl.scala 634:68] - wire _T_453 = io_tlu_exu_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 643:59] - wire _T_455 = io_tlu_exu_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 644:71] - wire _T_457 = io_tlu_exu_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 645:55] - wire _T_459 = _T_457 & _T_429; // @[dec_tlu_ctl.scala 645:79] - wire _T_460 = ~io_tlu_exu_exu_i0_br_mp_r; // @[dec_tlu_ctl.scala 645:106] - wire _T_461 = ~io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 645:135] - wire _T_462 = _T_460 | _T_461; // @[dec_tlu_ctl.scala 645:133] - wire _T_529 = ~take_nmi; // @[dec_tlu_ctl.scala 693:33] - wire _T_530 = take_ext_int & _T_529; // @[dec_tlu_ctl.scala 693:31] - wire _T_533 = take_timer_int & _T_529; // @[dec_tlu_ctl.scala 694:25] - wire _T_536 = take_soft_int & _T_529; // @[dec_tlu_ctl.scala 695:24] - wire _T_539 = take_int_timer0_int & _T_529; // @[dec_tlu_ctl.scala 696:30] - wire _T_542 = take_int_timer1_int & _T_529; // @[dec_tlu_ctl.scala 697:30] - wire _T_545 = take_ce_int & _T_529; // @[dec_tlu_ctl.scala 698:22] - wire _T_548 = illegal_r & _T_529; // @[dec_tlu_ctl.scala 699:20] - wire _T_551 = ecall_r & _T_529; // @[dec_tlu_ctl.scala 700:19] - wire _T_554 = inst_acc_r & _T_529; // @[dec_tlu_ctl.scala 701:22] - wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 702:20] - wire _T_558 = _T_556 & _T_529; // @[dec_tlu_ctl.scala 702:40] - wire _T_560 = ~lsu_exc_st_r; // @[dec_tlu_ctl.scala 703:25] - wire _T_561 = lsu_exc_ma_r & _T_560; // @[dec_tlu_ctl.scala 703:23] - wire _T_563 = _T_561 & _T_529; // @[dec_tlu_ctl.scala 703:39] - wire _T_566 = lsu_exc_acc_r & _T_560; // @[dec_tlu_ctl.scala 704:24] - wire _T_568 = _T_566 & _T_529; // @[dec_tlu_ctl.scala 704:40] - wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 705:23] - wire _T_572 = _T_570 & _T_529; // @[dec_tlu_ctl.scala 705:38] - wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 706:24] - wire _T_576 = _T_574 & _T_529; // @[dec_tlu_ctl.scala 706:39] + wire _T_350 = i_cpu_run_req_sync & _T_346; // @[dec_tlu_ctl.scala 566:58] + wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 566:83] + wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[dec_tlu_ctl.scala 566:105] + reg _T_353; // @[dec_tlu_ctl.scala 570:82] + reg _T_354; // @[dec_tlu_ctl.scala 571:82] + reg _T_355; // @[dec_tlu_ctl.scala 572:82] + wire _T_384 = io_o_cpu_halt_status & _T_375; // @[dec_tlu_ctl.scala 590:89] + wire _T_386 = _T_384 & _T_152; // @[dec_tlu_ctl.scala 590:109] + wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 591:41] + wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 591:88] + reg lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 603:72] + reg lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 610:73] + wire _T_408 = ~io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 611:40] + wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[dec_tlu_ctl.scala 611:38] + wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 612:38] + wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 613:38] + wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 623:38] + wire _T_425 = _T_424 | inst_acc_r; // @[dec_tlu_ctl.scala 623:53] + wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 623:79] + wire _T_427 = _T_425 | _T_426; // @[dec_tlu_ctl.scala 623:66] + wire _T_441 = ~io_tlu_exu_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 632:70] + wire _T_442 = iccm_repair_state_d1 & _T_441; // @[dec_tlu_ctl.scala 632:68] + wire _T_453 = io_tlu_exu_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 641:59] + wire _T_455 = io_tlu_exu_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 642:71] + wire _T_457 = io_tlu_exu_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 643:55] + wire _T_459 = _T_457 & _T_429; // @[dec_tlu_ctl.scala 643:79] + wire _T_460 = ~io_tlu_exu_exu_i0_br_mp_r; // @[dec_tlu_ctl.scala 643:106] + wire _T_461 = ~io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 643:135] + wire _T_462 = _T_460 | _T_461; // @[dec_tlu_ctl.scala 643:133] + wire _T_529 = ~take_nmi; // @[dec_tlu_ctl.scala 691:33] + wire _T_530 = take_ext_int & _T_529; // @[dec_tlu_ctl.scala 691:31] + wire _T_533 = take_timer_int & _T_529; // @[dec_tlu_ctl.scala 692:25] + wire _T_536 = take_soft_int & _T_529; // @[dec_tlu_ctl.scala 693:24] + wire _T_539 = take_int_timer0_int & _T_529; // @[dec_tlu_ctl.scala 694:30] + wire _T_542 = take_int_timer1_int & _T_529; // @[dec_tlu_ctl.scala 695:30] + wire _T_545 = take_ce_int & _T_529; // @[dec_tlu_ctl.scala 696:22] + wire _T_548 = illegal_r & _T_529; // @[dec_tlu_ctl.scala 697:20] + wire _T_551 = ecall_r & _T_529; // @[dec_tlu_ctl.scala 698:19] + wire _T_554 = inst_acc_r & _T_529; // @[dec_tlu_ctl.scala 699:22] + wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 700:20] + wire _T_558 = _T_556 & _T_529; // @[dec_tlu_ctl.scala 700:40] + wire _T_560 = ~lsu_exc_st_r; // @[dec_tlu_ctl.scala 701:25] + wire _T_561 = lsu_exc_ma_r & _T_560; // @[dec_tlu_ctl.scala 701:23] + wire _T_563 = _T_561 & _T_529; // @[dec_tlu_ctl.scala 701:39] + wire _T_566 = lsu_exc_acc_r & _T_560; // @[dec_tlu_ctl.scala 702:24] + wire _T_568 = _T_566 & _T_529; // @[dec_tlu_ctl.scala 702:40] + wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 703:23] + wire _T_572 = _T_570 & _T_529; // @[dec_tlu_ctl.scala 703:38] + wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 704:24] + wire _T_576 = _T_574 & _T_529; // @[dec_tlu_ctl.scala 704:39] wire [4:0] _T_578 = _T_530 ? 5'hb : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_579 = _T_533 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_580 = _T_536 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] @@ -55472,66 +55461,66 @@ module dec_tlu_ctl( wire [4:0] _T_602 = _T_601 | _T_589; // @[Mux.scala 27:72] wire [4:0] _T_603 = _T_602 | _T_590; // @[Mux.scala 27:72] wire [4:0] exc_cause_r = _T_603 | _T_591; // @[Mux.scala 27:72] - wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[dec_tlu_ctl.scala 731:52] - wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 731:74] - wire int_timer_stalled = _T_642 | mret_r; // @[dec_tlu_ctl.scala 731:98] - wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[dec_tlu_ctl.scala 733:72] - wire _T_644 = int_timer0_int_ready & _T_643; // @[dec_tlu_ctl.scala 733:49] - wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 733:121] - wire _T_647 = _T_645 & _T_207; // @[dec_tlu_ctl.scala 733:145] - wire _T_649 = _T_647 & _T_209; // @[dec_tlu_ctl.scala 733:166] - wire _T_651 = _T_649 & _T_152; // @[dec_tlu_ctl.scala 733:188] - wire _T_654 = int_timer1_int_ready & _T_643; // @[dec_tlu_ctl.scala 734:49] - wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 734:121] - wire _T_657 = _T_655 & _T_207; // @[dec_tlu_ctl.scala 734:145] - wire _T_659 = _T_657 & _T_209; // @[dec_tlu_ctl.scala 734:166] - wire _T_661 = _T_659 & _T_152; // @[dec_tlu_ctl.scala 734:188] - reg take_ext_int_start_d2; // @[dec_tlu_ctl.scala 743:62] - wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[dec_tlu_ctl.scala 748:46] - wire _T_682 = _T_681 | take_ext_int_start_d2; // @[dec_tlu_ctl.scala 748:70] - wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 750:49] - wire [30:0] mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 1006:31] + wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[dec_tlu_ctl.scala 729:52] + wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 729:74] + wire int_timer_stalled = _T_642 | mret_r; // @[dec_tlu_ctl.scala 729:98] + wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[dec_tlu_ctl.scala 731:72] + wire _T_644 = int_timer0_int_ready & _T_643; // @[dec_tlu_ctl.scala 731:49] + wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 731:121] + wire _T_647 = _T_645 & _T_207; // @[dec_tlu_ctl.scala 731:145] + wire _T_649 = _T_647 & _T_209; // @[dec_tlu_ctl.scala 731:166] + wire _T_651 = _T_649 & _T_152; // @[dec_tlu_ctl.scala 731:188] + wire _T_654 = int_timer1_int_ready & _T_643; // @[dec_tlu_ctl.scala 732:49] + wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 732:121] + wire _T_657 = _T_655 & _T_207; // @[dec_tlu_ctl.scala 732:145] + wire _T_659 = _T_657 & _T_209; // @[dec_tlu_ctl.scala 732:166] + wire _T_661 = _T_659 & _T_152; // @[dec_tlu_ctl.scala 732:188] + reg take_ext_int_start_d2; // @[dec_tlu_ctl.scala 741:74] + wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[dec_tlu_ctl.scala 746:46] + wire _T_682 = _T_681 | take_ext_int_start_d2; // @[dec_tlu_ctl.scala 746:70] + wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 748:49] + wire [30:0] mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 1003:31] wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] wire [30:0] _T_771 = {25'h0,exc_cause_r,1'h0}; // @[Cat.scala 29:58] - wire [30:0] vectored_path = _T_769 + _T_771; // @[dec_tlu_ctl.scala 778:51] - wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[dec_tlu_ctl.scala 779:61] - wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[dec_tlu_ctl.scala 779:28] - wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[dec_tlu_ctl.scala 780:36] - wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 780:48] - wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[dec_tlu_ctl.scala 780:94] - wire _T_783 = _T_780 | _T_782; // @[dec_tlu_ctl.scala 780:74] - wire _T_785 = rfpc_i0_r & _T_743; // @[dec_tlu_ctl.scala 780:129] - wire sel_npc_r = _T_783 | _T_785; // @[dec_tlu_ctl.scala 780:116] - wire _T_798 = interrupt_valid_r | mret_r; // @[dec_tlu_ctl.scala 784:43] - wire _T_799 = _T_798 | synchronous_flush_r; // @[dec_tlu_ctl.scala 784:52] - wire _T_800 = _T_799 | take_halt; // @[dec_tlu_ctl.scala 784:74] - wire _T_801 = _T_800 | take_reset; // @[dec_tlu_ctl.scala 784:86] - wire _T_807 = _T_529 & sel_npc_r; // @[dec_tlu_ctl.scala 788:73] - wire _T_810 = _T_529 & rfpc_i0_r; // @[dec_tlu_ctl.scala 789:73] - wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 789:91] - wire _T_813 = ~sel_npc_r; // @[dec_tlu_ctl.scala 789:132] - wire _T_814 = _T_812 & _T_813; // @[dec_tlu_ctl.scala 789:121] - wire _T_816 = ~take_ext_int; // @[dec_tlu_ctl.scala 790:96] - wire _T_817 = interrupt_valid_r & _T_816; // @[dec_tlu_ctl.scala 790:82] - wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 791:80] - wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 791:98] - wire _T_823 = _T_821 & _T_207; // @[dec_tlu_ctl.scala 791:143] - wire _T_825 = _T_823 & _T_816; // @[dec_tlu_ctl.scala 791:164] - wire _T_830 = _T_529 & mret_r; // @[dec_tlu_ctl.scala 792:68] - wire _T_833 = _T_529 & debug_resume_req_f; // @[dec_tlu_ctl.scala 793:68] - wire _T_836 = _T_529 & sel_npc_resume; // @[dec_tlu_ctl.scala 794:68] + wire [30:0] vectored_path = _T_769 + _T_771; // @[dec_tlu_ctl.scala 776:51] + wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[dec_tlu_ctl.scala 777:61] + wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[dec_tlu_ctl.scala 777:28] + wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[dec_tlu_ctl.scala 778:36] + wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 778:48] + wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[dec_tlu_ctl.scala 778:94] + wire _T_783 = _T_780 | _T_782; // @[dec_tlu_ctl.scala 778:74] + wire _T_785 = rfpc_i0_r & _T_743; // @[dec_tlu_ctl.scala 778:129] + wire sel_npc_r = _T_783 | _T_785; // @[dec_tlu_ctl.scala 778:116] + wire _T_798 = interrupt_valid_r | mret_r; // @[dec_tlu_ctl.scala 782:43] + wire _T_799 = _T_798 | synchronous_flush_r; // @[dec_tlu_ctl.scala 782:52] + wire _T_800 = _T_799 | take_halt; // @[dec_tlu_ctl.scala 782:74] + wire _T_801 = _T_800 | take_reset; // @[dec_tlu_ctl.scala 782:86] + wire _T_807 = _T_529 & sel_npc_r; // @[dec_tlu_ctl.scala 786:73] + wire _T_810 = _T_529 & rfpc_i0_r; // @[dec_tlu_ctl.scala 787:73] + wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 787:91] + wire _T_813 = ~sel_npc_r; // @[dec_tlu_ctl.scala 787:132] + wire _T_814 = _T_812 & _T_813; // @[dec_tlu_ctl.scala 787:121] + wire _T_816 = ~take_ext_int; // @[dec_tlu_ctl.scala 788:96] + wire _T_817 = interrupt_valid_r & _T_816; // @[dec_tlu_ctl.scala 788:82] + wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 789:80] + wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 789:98] + wire _T_823 = _T_821 & _T_207; // @[dec_tlu_ctl.scala 789:143] + wire _T_825 = _T_823 & _T_816; // @[dec_tlu_ctl.scala 789:164] + wire _T_830 = _T_529 & mret_r; // @[dec_tlu_ctl.scala 790:68] + wire _T_833 = _T_529 & debug_resume_req_f; // @[dec_tlu_ctl.scala 791:68] + wire _T_836 = _T_529 & sel_npc_resume; // @[dec_tlu_ctl.scala 792:68] wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r = csr_io_npc_r; // @[dec_tlu_ctl.scala 994:31] + wire [30:0] npc_r = csr_io_npc_r; // @[dec_tlu_ctl.scala 991:31] wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72] - wire [30:0] mepc = csr_io_mepc; // @[dec_tlu_ctl.scala 997:31] + wire [30:0] mepc = csr_io_mepc; // @[dec_tlu_ctl.scala 994:31] wire [30:0] _T_843 = _T_830 ? mepc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] dpc = csr_io_dpc; // @[dec_tlu_ctl.scala 1000:31] + wire [30:0] dpc = csr_io_dpc; // @[dec_tlu_ctl.scala 997:31] wire [30:0] _T_844 = _T_833 ? dpc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 995:31] + wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 992:31] wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72] wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72] @@ -55540,54 +55529,54 @@ module dec_tlu_ctl( wire [30:0] _T_850 = _T_849 | _T_843; // @[Mux.scala 27:72] wire [30:0] _T_851 = _T_850 | _T_844; // @[Mux.scala 27:72] wire [30:0] _T_852 = _T_851 | _T_845; // @[Mux.scala 27:72] - reg [30:0] tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 797:64] - wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[dec_tlu_ctl.scala 805:45] - wire _T_855 = _T_854 | interrupt_valid_r; // @[dec_tlu_ctl.scala 805:68] - reg i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 808:89] - reg [4:0] exc_cause_wb; // @[dec_tlu_ctl.scala 810:89] - wire _T_860 = ~illegal_r; // @[dec_tlu_ctl.scala 811:119] - reg i0_valid_wb; // @[dec_tlu_ctl.scala 811:97] - reg trigger_hit_r_d1; // @[dec_tlu_ctl.scala 812:89] - wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1013:42] - wire _T_865 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1013:67] - wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1018:55] - wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1018:73] - wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1018:92] - wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1018:115] - wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1018:136] - wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1018:158] - wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1018:179] - wire _T_881 = ~_T_880; // @[dec_tlu_ctl.scala 1018:36] - wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1018:201] - wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_883 = csr_pkt_legal & _T_882; // @[dec_tlu_ctl.scala 1018:33] - wire _T_884 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1018:223] - wire valid_csr = _T_883 & _T_884; // @[dec_tlu_ctl.scala 1018:221] - wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1020:46] - wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1020:107] - wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1020:129] - wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1020:150] - wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1020:172] - wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] - wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1020:193] - wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[dec_tlu_ctl.scala 1020:82] - wire _T_894 = ~_T_893; // @[dec_tlu_ctl.scala 1020:59] - dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 275:30] + reg [30:0] tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 795:64] + wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[dec_tlu_ctl.scala 802:45] + wire _T_855 = _T_854 | interrupt_valid_r; // @[dec_tlu_ctl.scala 802:68] + reg i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 805:75] + reg [4:0] exc_cause_wb; // @[dec_tlu_ctl.scala 807:91] + wire _T_860 = ~illegal_r; // @[dec_tlu_ctl.scala 808:121] + reg i0_valid_wb; // @[dec_tlu_ctl.scala 808:99] + reg trigger_hit_r_d1; // @[dec_tlu_ctl.scala 809:83] + wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1010:42] + wire _T_865 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1010:67] + wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1015:55] + wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1015:73] + wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1015:92] + wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1015:115] + wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1015:136] + wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1015:158] + wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1015:179] + wire _T_881 = ~_T_880; // @[dec_tlu_ctl.scala 1015:36] + wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1015:201] + wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_883 = csr_pkt_legal & _T_882; // @[dec_tlu_ctl.scala 1015:33] + wire _T_884 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1015:223] + wire valid_csr = _T_883 & _T_884; // @[dec_tlu_ctl.scala 1015:221] + wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1017:46] + wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1017:107] + wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1017:129] + wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1017:150] + wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1017:172] + wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] + wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1017:193] + wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[dec_tlu_ctl.scala 1017:82] + wire _T_894 = ~_T_893; // @[dec_tlu_ctl.scala 1017:59] + dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 275:32] .clock(int_timers_clock), .reset(int_timers_reset), .io_free_clk(int_timers_io_free_clk), @@ -55633,7 +55622,7 @@ module dec_tlu_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - csr_tlu csr ( // @[dec_tlu_ctl.scala 816:15] + csr_tlu csr ( // @[dec_tlu_ctl.scala 813:15] .clock(csr_clock), .reset(csr_reset), .io_free_clk(csr_io_free_clk), @@ -55719,6 +55708,7 @@ module dec_tlu_ctl( .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(csr_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override), @@ -55741,7 +55731,6 @@ module dec_tlu_ctl( .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any), .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any), .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff), - .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable), .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable), .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable), .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable), @@ -55905,7 +55894,7 @@ module dec_tlu_ctl( .io_mtdata1_t_2(csr_io_mtdata1_t_2), .io_mtdata1_t_3(csr_io_mtdata1_t_3) ); - dec_decode_csr_read csr_read ( // @[dec_tlu_ctl.scala 1009:22] + dec_decode_csr_read csr_read ( // @[dec_tlu_ctl.scala 1006:22] .io_dec_csr_rdaddr_d(csr_read_io_dec_csr_rdaddr_d), .io_csr_pkt_csr_misa(csr_read_io_csr_pkt_csr_misa), .io_csr_pkt_csr_mvendorid(csr_read_io_csr_pkt_csr_mvendorid), @@ -55975,118 +55964,118 @@ module dec_tlu_ctl( .io_csr_pkt_postsync(csr_read_io_csr_pkt_postsync), .io_csr_pkt_legal(csr_read_io_csr_pkt_legal) ); - assign io_tlu_exu_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 875:52] - assign io_tlu_exu_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 801:49] - assign io_tlu_exu_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[dec_tlu_ctl.scala 802:49] - assign io_tlu_dma_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 905:48] + assign io_tlu_exu_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 872:44] + assign io_tlu_exu_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 798:49] + assign io_tlu_exu_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[dec_tlu_ctl.scala 799:49] + assign io_tlu_dma_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 902:48] assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 486:29] assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[dec_tlu_ctl.scala 487:29] assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 468:41] assign io_dec_tlu_debug_mode = debug_mode_status; // @[dec_tlu_ctl.scala 469:41] - assign io_dec_tlu_resume_ack = _T_190; // @[dec_tlu_ctl.scala 452:49] + assign io_dec_tlu_resume_ack = _T_190; // @[dec_tlu_ctl.scala 452:65] assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[dec_tlu_ctl.scala 467:41] assign io_dec_tlu_mpc_halted_only = _T_65; // @[dec_tlu_ctl.scala 367:49] assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 475:33] - assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 881:40] - assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 881:40] - assign io_o_cpu_halt_status = _T_353; // @[dec_tlu_ctl.scala 572:49] - assign io_o_cpu_halt_ack = _T_354; // @[dec_tlu_ctl.scala 573:49] - assign io_o_cpu_run_ack = _T_355; // @[dec_tlu_ctl.scala 574:49] - assign io_o_debug_mode_status = debug_mode_status; // @[dec_tlu_ctl.scala 595:27] + assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 878:40] + assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 878:40] + assign io_o_cpu_halt_status = _T_353; // @[dec_tlu_ctl.scala 570:49] + assign io_o_cpu_halt_ack = _T_354; // @[dec_tlu_ctl.scala 571:49] + assign io_o_cpu_run_ack = _T_355; // @[dec_tlu_ctl.scala 572:49] + assign io_o_debug_mode_status = debug_mode_status; // @[dec_tlu_ctl.scala 593:27] assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 392:31] assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 393:31] assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 394:31] - assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 896:40] - assign io_dec_csr_legal_d = _T_887 & _T_894; // @[dec_tlu_ctl.scala 1020:20] + assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 893:40] + assign io_dec_csr_legal_d = _T_887 & _T_894; // @[dec_tlu_ctl.scala 1017:20] assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[dec_tlu_ctl.scala 329:41] - assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 333:41] - assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 898:40] + assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 333:37] + assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 895:40] assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[dec_tlu_ctl.scala 478:34] - assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[dec_tlu_ctl.scala 1013:23] - assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1014:23] - assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 884:40] - assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 885:40] - assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 886:40] - assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 887:40] - assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 878:44] - assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 879:44] - assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 877:44] - assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 883:40] - assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 882:40] - assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 897:40] - assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 888:40] - assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 889:40] - assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 891:40] - assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 893:40] - assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 894:40] - assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 895:40] - assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 799:41] - assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[dec_tlu_ctl.scala 651:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 648:65] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[dec_tlu_ctl.scala 649:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[dec_tlu_ctl.scala 650:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 652:65] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 653:65] + assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[dec_tlu_ctl.scala 1010:23] + assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1011:23] + assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 881:40] + assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 882:40] + assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 883:40] + assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 884:40] + assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 875:44] + assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 876:44] + assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 874:44] + assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 880:40] + assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 879:40] + assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 894:40] + assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 885:40] + assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 886:40] + assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 888:40] + assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 889:40] + assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 890:40] + assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 891:40] + assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 892:40] + assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 797:41] + assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[dec_tlu_ctl.scala 649:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 646:65] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[dec_tlu_ctl.scala 647:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[dec_tlu_ctl.scala 648:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 650:65] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 651:65] assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_233 & _T_234; // @[dec_tlu_ctl.scala 482:45] - assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 901:47] + assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 898:47] assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_205 | take_ext_int_start; // @[dec_tlu_ctl.scala 473:45] - assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 899:48] + assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 896:48] assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_433; // @[dec_tlu_ctl.scala 483:41] - assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 626:37] - assign io_tlu_mem_dec_tlu_force_halt = _T_33; // @[dec_tlu_ctl.scala 331:57] - assign io_tlu_mem_dec_tlu_fence_i_wb = _T_492 & _T_470; // @[dec_tlu_ctl.scala 671:39] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 880:52] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 880:52] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 880:52] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 880:52] - assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 903:48] - assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 904:52] - assign io_tlu_busbuff_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 900:52] - assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 902:52] - assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 874:52] - assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 876:52] + assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 624:37] + assign io_tlu_mem_dec_tlu_force_halt = _T_33; // @[dec_tlu_ctl.scala 331:41] + assign io_tlu_mem_dec_tlu_fence_i_wb = _T_492 & _T_470; // @[dec_tlu_ctl.scala 669:39] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 877:44] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 877:44] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 877:44] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 877:44] + assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 900:48] + assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 901:52] + assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 899:52] + assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 871:44] + assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 873:44] assign int_timers_clock = clock; assign int_timers_reset = reset; - assign int_timers_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 276:57] - assign int_timers_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 277:57] + assign int_timers_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 276:73] + assign int_timers_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 277:73] assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 278:49] assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 280:49] assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 281:49] - assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 282:57] - assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 283:57] - assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 284:57] - assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 285:57] - assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 286:57] - assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 287:57] - assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 288:49] + assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 282:73] + assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 283:73] + assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 284:73] + assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 285:73] + assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 286:73] + assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 287:73] + assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 288:57] assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 289:49] - assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[dec_tlu_ctl.scala 290:47] + assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[dec_tlu_ctl.scala 290:48] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = dec_csr_wen_r_mod | io_dec_tlu_dec_clk_override; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] @@ -56101,197 +56090,197 @@ module dec_tlu_ctl( assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign csr_clock = clock; assign csr_reset = reset; - assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 817:44] - assign csr_io_active_clk = io_active_clk; // @[dec_tlu_ctl.scala 818:44] - assign csr_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 819:44] - assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 820:44] - assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 821:44] - assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 822:44] - assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 823:44] - assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 824:44] - assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 825:44] - assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 826:44] - assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 827:44] - assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 828:44] - assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 829:44] - assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 830:44] - assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 831:44] - assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 832:44] - assign csr_io_ifu_pmu_fetch_stall = io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 833:44] - assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 834:44] - assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 834:44] - assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 834:44] - assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 834:44] - assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 834:44] - assign csr_io_exu_pmu_i0_br_ataken = io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 835:44] - assign csr_io_exu_pmu_i0_br_misp = io_tlu_exu_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 836:44] - assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 837:44] - assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 838:44] - assign csr_io_exu_pmu_i0_pc4 = io_tlu_exu_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 839:44] - assign csr_io_ifu_pmu_ic_miss = io_tlu_mem_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 840:44] - assign csr_io_ifu_pmu_ic_hit = io_tlu_mem_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 841:44] - assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 842:44] - assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 843:44] - assign csr_io_dma_pmu_dccm_write = io_tlu_dma_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 844:44] - assign csr_io_dma_pmu_dccm_read = io_tlu_dma_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 845:44] - assign csr_io_dma_pmu_any_write = io_tlu_dma_dma_pmu_any_write; // @[dec_tlu_ctl.scala 846:44] - assign csr_io_dma_pmu_any_read = io_tlu_dma_dma_pmu_any_read; // @[dec_tlu_ctl.scala 847:44] - assign csr_io_lsu_pmu_bus_busy = io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 848:44] - assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 849:44] - assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 850:44] - assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 852:44] - assign csr_io_ifu_pmu_bus_busy = io_tlu_mem_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 853:44] - assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 854:44] - assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 855:44] - assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 856:44] - assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 857:44] - assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 858:44] - assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 859:44] - assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 860:44] - assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 861:44] - assign csr_io_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 862:44] - assign csr_io_lsu_imprecise_error_load_any = io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 863:44] - assign csr_io_lsu_imprecise_error_store_any = io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 864:44] - assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[dec_tlu_ctl.scala 865:44 dec_tlu_ctl.scala 906:44] - assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 866:44 dec_tlu_ctl.scala 907:44] - assign csr_io_mexintpend = io_dec_pic_mexintpend; // @[dec_tlu_ctl.scala 867:44 dec_tlu_ctl.scala 908:44] - assign csr_io_exu_npc_r = io_tlu_exu_exu_npc_r; // @[dec_tlu_ctl.scala 868:44 dec_tlu_ctl.scala 909:44] - assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 869:44 dec_tlu_ctl.scala 910:44] - assign csr_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 870:44 dec_tlu_ctl.scala 911:44] - assign csr_io_core_id = io_core_id; // @[dec_tlu_ctl.scala 871:44 dec_tlu_ctl.scala 912:44] - assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 872:44 dec_tlu_ctl.scala 913:44] - assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 873:44 dec_tlu_ctl.scala 914:44] - assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 917:39] - assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 918:39] - assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 919:39] - assign csr_io_mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 920:39] - assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 921:39] - assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 922:39] - assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 923:39] - assign csr_io_timer_int_sync = syncro_ff[5]; // @[dec_tlu_ctl.scala 924:39] - assign csr_io_soft_int_sync = syncro_ff[4]; // @[dec_tlu_ctl.scala 925:39] - assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[dec_tlu_ctl.scala 926:39] - assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 927:39] - assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 928:39] - assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 929:39] - assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 930:39] - assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 931:39] - assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 932:39] - assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 933:39] - assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 934:39] - assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 935:39] - assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 936:39] - assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 937:39] - assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[dec_tlu_ctl.scala 938:39] - assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 939:39] - assign csr_io_inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 940:39] - assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[dec_tlu_ctl.scala 941:39] - assign csr_io_take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 942:39] - assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[dec_tlu_ctl.scala 943:39] - assign csr_io_exc_cause_r = _T_603 | _T_591; // @[dec_tlu_ctl.scala 944:39] - assign csr_io_i0_valid_wb = i0_valid_wb; // @[dec_tlu_ctl.scala 945:39] - assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 946:39] - assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 947:39] - assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 948:39] - assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 949:39] - assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 950:39] - assign csr_io_exc_cause_wb = exc_cause_wb; // @[dec_tlu_ctl.scala 951:39] - assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[dec_tlu_ctl.scala 952:39] - assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[dec_tlu_ctl.scala 953:39] - assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 954:39] - assign csr_io_ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 955:39] - assign csr_io_ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 956:39] - assign csr_io_illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 957:39] - assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[dec_tlu_ctl.scala 958:39] - assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[dec_tlu_ctl.scala 959:39] - assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 960:39] - assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[dec_tlu_ctl.scala 961:39] - assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[dec_tlu_ctl.scala 962:39] - assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 963:39] - assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 964:39] - assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 965:39] - assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[dec_tlu_ctl.scala 966:39] - assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 967:39] - assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 968:39] - assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[dec_tlu_ctl.scala 969:51] - assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 970:47] - assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 971:43] - assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[dec_tlu_ctl.scala 972:43] - assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 973:43] - assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 974:39] - assign csr_io_debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 975:51] - assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 976:39] - assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 977:39] - assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 978:39] - assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 979:39] - assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[dec_tlu_ctl.scala 980:39] - assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[dec_tlu_ctl.scala 981:39] - assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 982:39] - assign csr_io_take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 983:39] - assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 984:39] - assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 985:39] - assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 986:39] - assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 987:39] - assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[dec_tlu_ctl.scala 988:39] - assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 990:39] - assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 991:39] - assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 992:39] - assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1010:37] + assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 814:44] + assign csr_io_active_clk = io_active_clk; // @[dec_tlu_ctl.scala 815:44] + assign csr_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 816:44] + assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 817:44] + assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 818:44] + assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 819:44] + assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 820:44] + assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 821:44] + assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 822:44] + assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 823:44] + assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 824:44] + assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 825:44] + assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 826:44] + assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 827:44] + assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 828:44] + assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 829:44] + assign csr_io_ifu_pmu_fetch_stall = io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 830:44] + assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 831:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 831:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 831:44] + assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 831:44] + assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 831:44] + assign csr_io_exu_pmu_i0_br_ataken = io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 832:44] + assign csr_io_exu_pmu_i0_br_misp = io_tlu_exu_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 833:44] + assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 834:44] + assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 835:44] + assign csr_io_exu_pmu_i0_pc4 = io_tlu_exu_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 836:44] + assign csr_io_ifu_pmu_ic_miss = io_tlu_mem_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 837:44] + assign csr_io_ifu_pmu_ic_hit = io_tlu_mem_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 838:44] + assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 839:44] + assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 840:44] + assign csr_io_dma_pmu_dccm_write = io_tlu_dma_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 841:44] + assign csr_io_dma_pmu_dccm_read = io_tlu_dma_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 842:44] + assign csr_io_dma_pmu_any_write = io_tlu_dma_dma_pmu_any_write; // @[dec_tlu_ctl.scala 843:44] + assign csr_io_dma_pmu_any_read = io_tlu_dma_dma_pmu_any_read; // @[dec_tlu_ctl.scala 844:44] + assign csr_io_lsu_pmu_bus_busy = io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 845:44] + assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 846:44] + assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 847:44] + assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 849:44] + assign csr_io_ifu_pmu_bus_busy = io_tlu_mem_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 850:44] + assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 851:44] + assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 852:44] + assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 853:44] + assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 854:44] + assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 855:44] + assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 856:44] + assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 857:44] + assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 858:44] + assign csr_io_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 859:44] + assign csr_io_lsu_imprecise_error_load_any = io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 860:44] + assign csr_io_lsu_imprecise_error_store_any = io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 861:44] + assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[dec_tlu_ctl.scala 862:44 dec_tlu_ctl.scala 903:44] + assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 863:44 dec_tlu_ctl.scala 904:44] + assign csr_io_mexintpend = io_dec_pic_mexintpend; // @[dec_tlu_ctl.scala 864:44 dec_tlu_ctl.scala 905:44] + assign csr_io_exu_npc_r = io_tlu_exu_exu_npc_r; // @[dec_tlu_ctl.scala 865:44 dec_tlu_ctl.scala 906:44] + assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 866:44 dec_tlu_ctl.scala 907:44] + assign csr_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 867:44 dec_tlu_ctl.scala 908:44] + assign csr_io_core_id = io_core_id; // @[dec_tlu_ctl.scala 868:44 dec_tlu_ctl.scala 909:44] + assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 869:44 dec_tlu_ctl.scala 910:44] + assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 870:44 dec_tlu_ctl.scala 911:44] + assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 914:39] + assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 915:39] + assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 916:39] + assign csr_io_mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 917:39] + assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 918:39] + assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 919:39] + assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 920:39] + assign csr_io_timer_int_sync = syncro_ff[5]; // @[dec_tlu_ctl.scala 921:39] + assign csr_io_soft_int_sync = syncro_ff[4]; // @[dec_tlu_ctl.scala 922:39] + assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[dec_tlu_ctl.scala 923:39] + assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 924:39] + assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 925:39] + assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 926:39] + assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 927:39] + assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 928:39] + assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 929:39] + assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 930:39] + assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 931:39] + assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 932:39] + assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 933:39] + assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 934:39] + assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[dec_tlu_ctl.scala 935:39] + assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 936:39] + assign csr_io_inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 937:39] + assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[dec_tlu_ctl.scala 938:39] + assign csr_io_take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 939:39] + assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[dec_tlu_ctl.scala 940:39] + assign csr_io_exc_cause_r = _T_603 | _T_591; // @[dec_tlu_ctl.scala 941:39] + assign csr_io_i0_valid_wb = i0_valid_wb; // @[dec_tlu_ctl.scala 942:39] + assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 943:39] + assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 944:39] + assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 945:39] + assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 946:39] + assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 947:39] + assign csr_io_exc_cause_wb = exc_cause_wb; // @[dec_tlu_ctl.scala 948:39] + assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[dec_tlu_ctl.scala 949:39] + assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[dec_tlu_ctl.scala 950:39] + assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 951:39] + assign csr_io_ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 952:39] + assign csr_io_ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 953:39] + assign csr_io_illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 954:39] + assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[dec_tlu_ctl.scala 955:39] + assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[dec_tlu_ctl.scala 956:39] + assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 957:39] + assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[dec_tlu_ctl.scala 958:39] + assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[dec_tlu_ctl.scala 959:39] + assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 960:39] + assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 961:39] + assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 962:39] + assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[dec_tlu_ctl.scala 963:39] + assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 964:39] + assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 965:39] + assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[dec_tlu_ctl.scala 966:65] + assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 967:49] + assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 968:49] + assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[dec_tlu_ctl.scala 969:49] + assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 970:49] + assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 971:39] + assign csr_io_debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 972:73] + assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 973:39] + assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 974:39] + assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 975:39] + assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 976:39] + assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[dec_tlu_ctl.scala 977:39] + assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[dec_tlu_ctl.scala 978:39] + assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 979:39] + assign csr_io_take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 980:39] + assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 981:39] + assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 982:39] + assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 984:39] + assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[dec_tlu_ctl.scala 985:39] + assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[dec_tlu_ctl.scala 986:39] + assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 987:39] + assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 988:39] + assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 989:39] + assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1007:37] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -57941,6 +57930,7 @@ module dec( output [31:0] io_rv_trace_pkt_rv_i_tval_ip, output io_dec_tlu_misc_clk_override, output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -58078,7 +58068,6 @@ module dec( input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, output io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, - output io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -58486,6 +58475,7 @@ module dec( wire tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 120:19] @@ -58526,7 +58516,6 @@ module dec( wire tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 120:19] - wire tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 120:19] @@ -58561,7 +58550,7 @@ module dec( wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[dec.scala 121:27] wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[dec.scala 121:27] wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 121:27] - wire _T_1 = tlu_io_dec_tlu_i0_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 296:98] + wire _T_1 = tlu_io_dec_tlu_i0_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 290:98] dec_ib_ctl instbuff ( // @[dec.scala 117:24] .io_ifu_ib_ifu_i0_icaf(instbuff_io_ifu_ib_ifu_i0_icaf), .io_ifu_ib_ifu_i0_icaf_type(instbuff_io_ifu_ib_ifu_i0_icaf_type), @@ -58942,6 +58931,7 @@ module dec( .io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(tlu_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override), @@ -58982,7 +58972,6 @@ module dec( .io_tlu_busbuff_lsu_pmu_bus_error(tlu_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(tlu_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(tlu_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(tlu_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -59021,40 +59010,40 @@ module dec( .io_dec_i0_trigger_match_d(dec_trigger_io_dec_i0_trigger_match_d) ); assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[dec.scala 188:40] - assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[dec.scala 265:29] - assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[dec.scala 266:29] - assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[dec.scala 267:29] - assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[dec.scala 268:29] - assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[dec.scala 269:29] - assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[dec.scala 270:29] - assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[dec.scala 271:29] - assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[dec.scala 260:28] - assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[dec.scala 261:28] - assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[dec.scala 262:28] - assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 263:51] - assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[dec.scala 304:21] - assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[dec.scala 258:28] - assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[dec.scala 259:28] - assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 264:29] - assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 264:29] - assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[dec.scala 264:29] - assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[dec.scala 264:29] - assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 264:29] - assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 264:29] - assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 264:29] - assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[dec.scala 264:29] - assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[dec.scala 264:29] - assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 264:29] - assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 264:29] - assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 264:29] - assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[dec.scala 264:29] - assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[dec.scala 264:29] - assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 264:29] - assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 264:29] - assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 264:29] - assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[dec.scala 264:29] - assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[dec.scala 264:29] - assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 264:29] + assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[dec.scala 261:29] + assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[dec.scala 262:29] + assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[dec.scala 263:29] + assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[dec.scala 264:29] + assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[dec.scala 265:29] + assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[dec.scala 266:29] + assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[dec.scala 267:29] + assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[dec.scala 256:28] + assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[dec.scala 257:28] + assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[dec.scala 258:28] + assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 259:51] + assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[dec.scala 298:21] + assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[dec.scala 254:28] + assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[dec.scala 255:28] + assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 260:29] + assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 260:29] + assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[dec.scala 260:29] + assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[dec.scala 260:29] + assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 260:29] + assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 260:29] + assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 260:29] + assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[dec.scala 260:29] + assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[dec.scala 260:29] + assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 260:29] + assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 260:29] + assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 260:29] + assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[dec.scala 260:29] + assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[dec.scala 260:29] + assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 260:29] + assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 260:29] + assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 260:29] + assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[dec.scala 260:29] + assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[dec.scala 260:29] + assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 260:29] assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[dec.scala 185:40] assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[dec.scala 185:40] assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[dec.scala 185:40] @@ -59066,24 +59055,25 @@ module dec( assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 185:40] assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 185:40] assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[dec.scala 187:40] - assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 274:34] - assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[dec.scala 275:29] - assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[dec.scala 276:29] - assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[dec.scala 277:29] - assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[dec.scala 278:29] + assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 268:34] + assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[dec.scala 269:29] + assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[dec.scala 270:29] + assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[dec.scala 271:29] + assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[dec.scala 272:29] assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[dec.scala 186:40] - assign io_rv_trace_pkt_rv_i_valid_ip = {tlu_io_dec_tlu_int_valid_wb1,_T_1}; // @[dec.scala 296:33] - assign io_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb1; // @[dec.scala 294:32] - assign io_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb1,1'h0}; // @[dec.scala 295:35] - assign io_rv_trace_pkt_rv_i_exception_ip = {tlu_io_dec_tlu_int_valid_wb1,tlu_io_dec_tlu_i0_exc_valid_wb1}; // @[dec.scala 297:37] - assign io_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 298:34] - assign io_rv_trace_pkt_rv_i_interrupt_ip = {tlu_io_dec_tlu_int_valid_wb1,1'h0}; // @[dec.scala 299:37] - assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 300:32] - assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 284:35] - assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 286:36] - assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 288:36] - assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 289:36] - assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 290:36] + assign io_rv_trace_pkt_rv_i_valid_ip = {tlu_io_dec_tlu_int_valid_wb1,_T_1}; // @[dec.scala 290:33] + assign io_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb1; // @[dec.scala 288:32] + assign io_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb1,1'h0}; // @[dec.scala 289:35] + assign io_rv_trace_pkt_rv_i_exception_ip = {tlu_io_dec_tlu_int_valid_wb1,tlu_io_dec_tlu_i0_exc_valid_wb1}; // @[dec.scala 291:37] + assign io_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 292:34] + assign io_rv_trace_pkt_rv_i_interrupt_ip = {tlu_io_dec_tlu_int_valid_wb1,1'h0}; // @[dec.scala 293:37] + assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 294:32] + assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 278:35] + assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 280:36] + assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 281:36] + assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 282:36] + assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 283:36] + assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 284:36] assign io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 133:21] assign io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 202:18] assign io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 202:18] @@ -59168,7 +59158,6 @@ module dec( assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 201:22] assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 201:22] assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 222:26] - assign io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 222:26] assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 222:26] assign io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 206:18] assign io_dec_pic_dec_tlu_meicurpl = tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 224:14] @@ -59343,12 +59332,12 @@ module dec( assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[dec.scala 244:45] assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[dec.scala 245:45] assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[dec.scala 247:45] - assign tlu_io_timer_int = io_timer_int; // @[dec.scala 252:45] - assign tlu_io_soft_int = io_soft_int; // @[dec.scala 253:45] - assign tlu_io_core_id = io_core_id; // @[dec.scala 254:45] - assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[dec.scala 255:45] - assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[dec.scala 256:45] - assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec.scala 257:45] + assign tlu_io_timer_int = io_timer_int; // @[dec.scala 248:45] + assign tlu_io_soft_int = io_soft_int; // @[dec.scala 249:45] + assign tlu_io_core_id = io_core_id; // @[dec.scala 250:45] + assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[dec.scala 251:45] + assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[dec.scala 252:45] + assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec.scala 253:45] assign tlu_io_ifu_pmu_instr_aligned = io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[dec.scala 216:45] assign tlu_io_tlu_ifc_ifu_pmu_fetch_stall = io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[dec.scala 203:18] assign tlu_io_tlu_mem_ifu_pmu_ic_miss = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[dec.scala 202:18] @@ -59418,7 +59407,6 @@ module dbg( input io_sb_axi_aw_ready, output io_sb_axi_aw_valid, output [31:0] io_sb_axi_aw_bits_addr, - output [3:0] io_sb_axi_aw_bits_region, output [2:0] io_sb_axi_aw_bits_size, input io_sb_axi_w_ready, output io_sb_axi_w_valid, @@ -59430,7 +59418,6 @@ module dbg( input io_sb_axi_ar_ready, output io_sb_axi_ar_valid, output [31:0] io_sb_axi_ar_bits_addr, - output [3:0] io_sb_axi_ar_bits_region, output [2:0] io_sb_axi_ar_bits_size, output io_sb_axi_r_ready, input io_sb_axi_r_valid, @@ -60023,7 +60010,6 @@ module dbg( assign io_dmi_reg_rdata = _T_467; // @[dbg.scala 325:20] assign io_sb_axi_aw_valid = _T_558 | _T_559; // @[dbg.scala 412:22] assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 413:26] - assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 418:28] assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 415:26] assign io_sb_axi_w_valid = _T_558 | _T_565; // @[dbg.scala 423:21] assign io_sb_axi_w_bits_data = _T_593 | _T_601; // @[dbg.scala 424:25] @@ -60031,7 +60017,6 @@ module dbg( assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 444:21] assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 433:22] assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 434:26] - assign io_sb_axi_ar_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 439:28] assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 436:26] assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 445:21] assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_480 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 331:35] @@ -62097,27 +62082,27 @@ module exu( wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 144:19] wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 144:19] wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 144:19] - wire i_mul_clock; // @[exu.scala 162:19] - wire i_mul_reset; // @[exu.scala 162:19] - wire i_mul_io_scan_mode; // @[exu.scala 162:19] - wire i_mul_io_mul_p_valid; // @[exu.scala 162:19] - wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 162:19] - wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 162:19] - wire i_mul_io_mul_p_bits_low; // @[exu.scala 162:19] - wire [31:0] i_mul_io_rs1_in; // @[exu.scala 162:19] - wire [31:0] i_mul_io_rs2_in; // @[exu.scala 162:19] - wire [31:0] i_mul_io_result_x; // @[exu.scala 162:19] - wire i_div_clock; // @[exu.scala 169:19] - wire i_div_reset; // @[exu.scala 169:19] - wire i_div_io_scan_mode; // @[exu.scala 169:19] - wire [31:0] i_div_io_dividend; // @[exu.scala 169:19] - wire [31:0] i_div_io_divisor; // @[exu.scala 169:19] - wire [31:0] i_div_io_exu_div_result; // @[exu.scala 169:19] - wire i_div_io_exu_div_wren; // @[exu.scala 169:19] - wire i_div_io_dec_div_div_p_valid; // @[exu.scala 169:19] - wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 169:19] - wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 169:19] - wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 169:19] + wire i_mul_clock; // @[exu.scala 162:21] + wire i_mul_reset; // @[exu.scala 162:21] + wire i_mul_io_scan_mode; // @[exu.scala 162:21] + wire i_mul_io_mul_p_valid; // @[exu.scala 162:21] + wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 162:21] + wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 162:21] + wire i_mul_io_mul_p_bits_low; // @[exu.scala 162:21] + wire [31:0] i_mul_io_rs1_in; // @[exu.scala 162:21] + wire [31:0] i_mul_io_rs2_in; // @[exu.scala 162:21] + wire [31:0] i_mul_io_result_x; // @[exu.scala 162:21] + wire i_div_clock; // @[exu.scala 169:21] + wire i_div_reset; // @[exu.scala 169:21] + wire i_div_io_scan_mode; // @[exu.scala 169:21] + wire [31:0] i_div_io_dividend; // @[exu.scala 169:21] + wire [31:0] i_div_io_divisor; // @[exu.scala 169:21] + wire [31:0] i_div_io_exu_div_result; // @[exu.scala 169:21] + wire i_div_io_exu_div_wren; // @[exu.scala 169:21] + wire i_div_io_dec_div_div_p_valid; // @[exu.scala 169:21] + wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 169:21] + wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 169:21] + wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 169:21] wire [15:0] _T = {io_dec_exu_decode_exu_i0_predict_fghr_d,io_dec_exu_decode_exu_i0_predict_index_d}; // @[Cat.scala 29:58] reg [30:0] i0_flush_path_x; // @[lib.scala 374:16] reg [31:0] _T_3; // @[lib.scala 374:16] @@ -62227,7 +62212,7 @@ module exu( wire _T_179 = i0_flush_upper_x & _T_149; // @[exu.scala 215:67] wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 42:53 exu.scala 157:41] wire [31:0] pred_correct_npc_r = {{1'd0}, _T_23}; // @[exu.scala 47:51 exu.scala 78:41] - wire [31:0] _T_188 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 233:72] + wire [31:0] _T_188 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 233:55] wire [31:0] i0_rs2_d = _T_92; // @[Mux.scala 27:72 Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), @@ -62401,7 +62386,7 @@ module exu( .io_predict_p_out_bits_pja(i_alu_io_predict_p_out_bits_pja), .io_predict_p_out_bits_way(i_alu_io_predict_p_out_bits_way) ); - exu_mul_ctl i_mul ( // @[exu.scala 162:19] + exu_mul_ctl i_mul ( // @[exu.scala 162:21] .clock(i_mul_clock), .reset(i_mul_reset), .io_scan_mode(i_mul_io_scan_mode), @@ -62413,7 +62398,7 @@ module exu( .io_rs2_in(i_mul_io_rs2_in), .io_result_x(i_mul_io_result_x) ); - exu_div_ctl i_div ( // @[exu.scala 169:19] + exu_div_ctl i_div ( // @[exu.scala 169:21] .clock(i_div_clock), .reset(i_div_reset), .io_scan_mode(i_div_io_scan_mode), @@ -62439,29 +62424,29 @@ module exu( assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 182:47] assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 183:47] assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 184:47] - assign io_dec_exu_tlu_exu_exu_npc_r = _T_188[30:0]; // @[exu.scala 233:66] + assign io_dec_exu_tlu_exu_exu_npc_r = _T_188[30:0]; // @[exu.scala 233:49] assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 209:58] assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 204:43] - assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 219:48] - assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 223:48] - assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 224:48] - assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 225:48] - assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 226:66] - assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 227:58] - assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 220:48] - assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 222:48] - assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 221:48] - assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 218:48] - assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 231:43] - assign io_exu_bp_exu_mp_fghr = _T_179 ? ghr_d : ghr_x; // @[exu.scala 228:43] - assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 229:66] - assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 230:58] + assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 219:37] + assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 223:37] + assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 224:37] + assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 225:37] + assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 226:49] + assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 227:41] + assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 220:37] + assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 222:37] + assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 221:37] + assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 218:37] + assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 231:37] + assign io_exu_bp_exu_mp_fghr = _T_179 ? ghr_d : ghr_x; // @[exu.scala 228:37] + assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 229:67] + assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 230:61] assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 158:22] assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 176:33] assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 175:41] assign io_lsu_exu_exu_lsu_rs1_d = _T_106 | _T_105; // @[exu.scala 119:27] assign io_lsu_exu_exu_lsu_rs2_d = _T_117 | _T_118; // @[exu.scala 125:27] - assign io_exu_flush_path_final = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : i0_flush_path_d; // @[exu.scala 232:50] + assign io_exu_flush_path_final = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : i0_flush_path_d; // @[exu.scala 232:33] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -62561,7 +62546,7 @@ module exu( assign i_alu_io_pp_in_bits_way = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[exu.scala 148:41] assign i_mul_clock = clock; assign i_mul_reset = reset; - assign i_mul_io_scan_mode = io_scan_mode; // @[exu.scala 163:33] + assign i_mul_io_scan_mode = io_scan_mode; // @[exu.scala 163:25] assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 164:41] assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 164:41] assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 164:41] @@ -66726,15 +66711,15 @@ module lsu_ecc( wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[lib.scala 193:206] wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58] wire _T_209 = _T_208 != 7'h0; // @[lib.scala 194:44] - wire _T_1131 = ~io_dec_tlu_core_ecc_disable; // @[lsu_ecc.scala 107:73] - wire _T_1138 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[lsu_ecc.scala 125:65] - wire _T_1139 = io_lsu_pkt_m_valid & _T_1138; // @[lsu_ecc.scala 125:39] - wire _T_1140 = _T_1139 & io_addr_in_dccm_m; // @[lsu_ecc.scala 125:92] - wire is_ldst_m = _T_1140 & io_lsu_dccm_rden_m; // @[lsu_ecc.scala 125:112] - wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[lsu_ecc.scala 124:39] - wire _T_1144 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[lsu_ecc.scala 127:48] - wire _T_1145 = is_ldst_m & _T_1144; // @[lsu_ecc.scala 127:33] - wire is_ldst_hi_m = _T_1145 & _T_1131; // @[lsu_ecc.scala 127:73] + wire _T_1131 = ~io_dec_tlu_core_ecc_disable; // @[lsu_ecc.scala 105:73] + wire _T_1138 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[lsu_ecc.scala 123:65] + wire _T_1139 = io_lsu_pkt_m_valid & _T_1138; // @[lsu_ecc.scala 123:39] + wire _T_1140 = _T_1139 & io_addr_in_dccm_m; // @[lsu_ecc.scala 123:92] + wire is_ldst_m = _T_1140 & io_lsu_dccm_rden_m; // @[lsu_ecc.scala 123:112] + wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[lsu_ecc.scala 122:39] + wire _T_1144 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[lsu_ecc.scala 125:48] + wire _T_1145 = is_ldst_m & _T_1144; // @[lsu_ecc.scala 125:33] + wire is_ldst_hi_m = _T_1145 & _T_1131; // @[lsu_ecc.scala 125:73] wire _T_210 = is_ldst_hi_m & _T_209; // @[lib.scala 194:32] wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[lib.scala 194:53] wire _T_215 = ~_T_208[6]; // @[lib.scala 195:55] @@ -66817,7 +66802,7 @@ module lsu_ecc( wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[lib.scala 193:206] wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58] wire _T_587 = _T_586 != 7'h0; // @[lib.scala 194:44] - wire is_ldst_lo_m = is_ldst_m & _T_1131; // @[lsu_ecc.scala 126:33] + wire is_ldst_lo_m = is_ldst_m & _T_1131; // @[lsu_ecc.scala 124:33] wire _T_588 = is_ldst_lo_m & _T_587; // @[lib.scala 194:32] wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[lib.scala 194:53] wire _T_593 = ~_T_586[6]; // @[lib.scala 195:55] @@ -66872,8 +66857,8 @@ module lsu_ecc( wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[lib.scala 202:31] wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58] wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58] - wire [31:0] _T_1158 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[lsu_ecc.scala 149:87] - wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1158; // @[lsu_ecc.scala 149:27] + wire [31:0] _T_1158 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[lsu_ecc.scala 147:87] + wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1158; // @[lsu_ecc.scala 147:27] wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[lib.scala 119:74] wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[lib.scala 119:74] @@ -66962,8 +66947,8 @@ module lsu_ecc( wire _T_935 = ^dccm_wdata_lo_any; // @[lib.scala 127:13] wire _T_936 = ^_T_934; // @[lib.scala 127:23] wire _T_937 = _T_935 ^ _T_936; // @[lib.scala 127:18] - wire [31:0] _T_1162 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[lsu_ecc.scala 150:87] - wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1162; // @[lsu_ecc.scala 150:27] + wire [31:0] _T_1162 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[lsu_ecc.scala 148:87] + wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1162; // @[lsu_ecc.scala 148:27] wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[lib.scala 119:74] wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[lib.scala 119:74] @@ -67052,12 +67037,12 @@ module lsu_ecc( wire _T_1117 = ^dccm_wdata_hi_any; // @[lib.scala 127:13] wire _T_1118 = ^_T_1116; // @[lib.scala 127:23] wire _T_1119 = _T_1117 ^ _T_1118; // @[lib.scala 127:18] - reg _T_1150; // @[lsu_ecc.scala 141:72] - reg _T_1151; // @[lsu_ecc.scala 142:72] - reg _T_1152; // @[lsu_ecc.scala 143:72] - reg _T_1153; // @[lsu_ecc.scala 144:72] - reg [31:0] _T_1154; // @[lsu_ecc.scala 145:72] - reg [31:0] _T_1155; // @[lsu_ecc.scala 146:72] + reg _T_1150; // @[lsu_ecc.scala 139:72] + reg _T_1151; // @[lsu_ecc.scala 140:72] + reg _T_1152; // @[lsu_ecc.scala 141:72] + reg _T_1153; // @[lsu_ecc.scala 142:72] + reg [31:0] _T_1154; // @[lsu_ecc.scala 143:72] + reg [31:0] _T_1155; // @[lsu_ecc.scala 144:72] reg [31:0] _T_1164; // @[lib.scala 374:16] reg [31:0] _T_1165; // @[lib.scala 374:16] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] @@ -67072,23 +67057,23 @@ module lsu_ecc( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - assign io_sec_data_hi_r = _T_1154; // @[lsu_ecc.scala 114:22 lsu_ecc.scala 145:62] - assign io_sec_data_lo_r = _T_1155; // @[lsu_ecc.scala 117:25 lsu_ecc.scala 146:62] - assign io_sec_data_hi_m = {_T_364,_T_362}; // @[lsu_ecc.scala 90:32 lsu_ecc.scala 134:27] - assign io_sec_data_lo_m = {_T_742,_T_740}; // @[lsu_ecc.scala 91:32 lsu_ecc.scala 136:27] - assign io_sec_data_hi_r_ff = _T_1164; // @[lsu_ecc.scala 157:23] - assign io_sec_data_lo_r_ff = _T_1165; // @[lsu_ecc.scala 158:23] - assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[lsu_ecc.scala 154:28] - assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[lsu_ecc.scala 155:28] - assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[lsu_ecc.scala 153:28] - assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[lsu_ecc.scala 151:28] - assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[lsu_ecc.scala 152:28] - assign io_single_ecc_error_hi_r = _T_1153; // @[lsu_ecc.scala 115:31 lsu_ecc.scala 144:62] - assign io_single_ecc_error_lo_r = _T_1152; // @[lsu_ecc.scala 118:31 lsu_ecc.scala 143:62] - assign io_lsu_single_ecc_error_r = _T_1150; // @[lsu_ecc.scala 120:31 lsu_ecc.scala 141:62] - assign io_lsu_double_ecc_error_r = _T_1151; // @[lsu_ecc.scala 121:31 lsu_ecc.scala 142:62] - assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[lsu_ecc.scala 92:30 lsu_ecc.scala 138:33] - assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[lsu_ecc.scala 93:30 lsu_ecc.scala 139:33] + assign io_sec_data_hi_r = _T_1154; // @[lsu_ecc.scala 112:22 lsu_ecc.scala 143:62] + assign io_sec_data_lo_r = _T_1155; // @[lsu_ecc.scala 115:25 lsu_ecc.scala 144:62] + assign io_sec_data_hi_m = {_T_364,_T_362}; // @[lsu_ecc.scala 88:32 lsu_ecc.scala 132:27] + assign io_sec_data_lo_m = {_T_742,_T_740}; // @[lsu_ecc.scala 89:32 lsu_ecc.scala 134:27] + assign io_sec_data_hi_r_ff = _T_1164; // @[lsu_ecc.scala 155:23] + assign io_sec_data_lo_r_ff = _T_1165; // @[lsu_ecc.scala 156:23] + assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[lsu_ecc.scala 152:28] + assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[lsu_ecc.scala 153:28] + assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[lsu_ecc.scala 151:28] + assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[lsu_ecc.scala 149:28] + assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[lsu_ecc.scala 150:28] + assign io_single_ecc_error_hi_r = _T_1153; // @[lsu_ecc.scala 113:31 lsu_ecc.scala 142:62] + assign io_single_ecc_error_lo_r = _T_1152; // @[lsu_ecc.scala 116:31 lsu_ecc.scala 141:62] + assign io_lsu_single_ecc_error_r = _T_1150; // @[lsu_ecc.scala 118:31 lsu_ecc.scala 139:62] + assign io_lsu_double_ecc_error_r = _T_1151; // @[lsu_ecc.scala 119:31 lsu_ecc.scala 140:62] + assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[lsu_ecc.scala 90:30 lsu_ecc.scala 136:33] + assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[lsu_ecc.scala 91:30 lsu_ecc.scala 137:33] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -68191,7 +68176,6 @@ module lsu_bus_buffer( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, - input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -68241,9 +68225,7 @@ module lsu_bus_buffer( output io_lsu_axi_aw_valid, output [2:0] io_lsu_axi_aw_bits_id, output [31:0] io_lsu_axi_aw_bits_addr, - output [3:0] io_lsu_axi_aw_bits_region, output [2:0] io_lsu_axi_aw_bits_size, - output [3:0] io_lsu_axi_aw_bits_cache, input io_lsu_axi_w_ready, output io_lsu_axi_w_valid, output [63:0] io_lsu_axi_w_bits_data, @@ -68256,9 +68238,7 @@ module lsu_bus_buffer( output io_lsu_axi_ar_valid, output [2:0] io_lsu_axi_ar_bits_id, output [31:0] io_lsu_axi_ar_bits_addr, - output [3:0] io_lsu_axi_ar_bits_region, output [2:0] io_lsu_axi_ar_bits_size, - output [3:0] io_lsu_axi_ar_bits_cache, output io_lsu_axi_r_ready, input io_lsu_axi_r_valid, input [2:0] io_lsu_axi_r_bits_id, @@ -68354,9 +68334,9 @@ module lsu_bus_buffer( reg [31:0] _RAND_75; reg [31:0] _RAND_76; reg [31:0] _RAND_77; - reg [31:0] _RAND_78; + reg [63:0] _RAND_78; reg [31:0] _RAND_79; - reg [63:0] _RAND_80; + reg [31:0] _RAND_80; reg [31:0] _RAND_81; reg [31:0] _RAND_82; reg [31:0] _RAND_83; @@ -68381,8 +68361,6 @@ module lsu_bus_buffer( reg [31:0] _RAND_102; reg [31:0] _RAND_103; reg [31:0] _RAND_104; - reg [31:0] _RAND_105; - reg [31:0] _RAND_106; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -69056,74 +69034,26 @@ module lsu_bus_buffer( wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 208:56] wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 208:54] wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 210:36] - reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 253:55] - wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 216:62] - wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 216:48] - wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 235:54] - wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 235:80] - wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 235:93] - wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 235:129] - wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 235:106] - wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 235:152] - wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 235:150] - wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 235:175] - wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 235:173] - wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 236:20] - wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 216:98] - wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 216:82] - wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 216:80] - wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 217:5] wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 211:44] wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 211:42] wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 211:61] wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 211:120] wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 211:100] wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 211:74] - wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 217:16] reg ibuf_sideeffect; // @[Reg.scala 27:20] - wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 217:35] - wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 217:55] - wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 217:53] - wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 217:67] - wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 216:32] - wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 210:34] + wire _T_856 = ibuf_valid & _T_855; // @[lsu_bus_buffer.scala 210:34] wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 210:49] reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 616:49] reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 615:49] reg [1:0] ibuf_tag; // @[Reg.scala 27:20] wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] - wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 226:77] - wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 232:8] - wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 230:46] - wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 232:8] - wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 230:46] - wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 232:8] - wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 230:46] - wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 232:8] - wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 230:46] - wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] - wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 233:59] - wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 233:93] - wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 237:65] - wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 237:63] - wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 237:96] - wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 237:48] - wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 237:96] - wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 237:48] - wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 237:96] - wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 237:48] - wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 237:96] - wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 237:48] - wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] - wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 238:45] - wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 238:45] - wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 238:45] - wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 238:45] - wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire [23:0] _T_922 = {_T_919,_T_910,_T_901}; // @[Cat.scala 29:58] + wire [3:0] ibuf_byteen_out = {ibuf_byteen[3],ibuf_byteen[2],ibuf_byteen[1],ibuf_byteen[0]}; // @[Cat.scala 29:58] + wire [31:0] ibuf_data_out = {ibuf_data[31:24],ibuf_data[23:16],ibuf_data[15:8],ibuf_data[7:0]}; // @[Cat.scala 29:58] wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 240:58] wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 240:93] reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] @@ -69132,24 +69062,10 @@ module lsu_bus_buffer( reg ibuf_nomerge; // @[Reg.scala 27:20] reg ibuf_unsign; // @[Reg.scala 27:20] reg [1:0] ibuf_sz; // @[Reg.scala 27:20] - wire _T_4446 = buf_write[3] & _T_2621; // @[lsu_bus_buffer.scala 522:64] wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 522:91] - wire _T_4448 = _T_4446 & _T_4447; // @[lsu_bus_buffer.scala 522:89] - wire _T_4441 = buf_write[2] & _T_2616; // @[lsu_bus_buffer.scala 522:64] wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 522:91] - wire _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 522:89] - wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[lsu_bus_buffer.scala 522:142] - wire _T_4436 = buf_write[1] & _T_2611; // @[lsu_bus_buffer.scala 522:64] wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 522:91] - wire _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 522:89] - wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[lsu_bus_buffer.scala 522:142] - wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[lsu_bus_buffer.scala 522:142] - wire _T_4431 = buf_write[0] & _T_2606; // @[lsu_bus_buffer.scala 522:64] wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 522:91] - wire _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 522:89] - wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[lsu_bus_buffer.scala 522:142] - wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[lsu_bus_buffer.scala 522:142] - wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 263:43] wire _T_4463 = _T_2621 & _T_4447; // @[lsu_bus_buffer.scala 523:73] wire _T_4460 = _T_2616 & _T_4442; // @[lsu_bus_buffer.scala 523:73] wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[lsu_bus_buffer.scala 523:126] @@ -69160,11 +69076,6 @@ module lsu_bus_buffer( wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[lsu_bus_buffer.scala 523:126] wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[lsu_bus_buffer.scala 523:126] wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 263:72] - wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 263:51] - reg [2:0] obuf_wr_timer; // @[lsu_bus_buffer.scala 361:54] - wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 263:97] - wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 263:80] - wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 263:114] wire _T_1979 = |buf_age_3; // @[lsu_bus_buffer.scala 378:58] wire _T_1980 = ~_T_1979; // @[lsu_bus_buffer.scala 378:45] wire _T_1982 = _T_1980 & _T_2621; // @[lsu_bus_buffer.scala 378:63] @@ -69199,18 +69110,9 @@ module lsu_bus_buffer( wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 264:114] wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 264:114] reg buf_nomerge_0; // @[Reg.scala 27:20] - wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] reg buf_nomerge_1; // @[Reg.scala 27:20] - wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] reg buf_nomerge_2; // @[Reg.scala 27:20] - wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] reg buf_nomerge_3; // @[Reg.scala 27:20] - wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] - wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] - wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] - wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] - wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 264:31] - wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 264:29] reg _T_4330; // @[Reg.scala 27:20] reg _T_4327; // @[Reg.scala 27:20] reg _T_4324; // @[Reg.scala 27:20] @@ -69224,7 +69126,6 @@ module lsu_bus_buffer( wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 265:5] - wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 264:140] wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 267:58] wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 267:72] wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] @@ -69236,12 +69137,6 @@ module lsu_bus_buffer( wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 267:123] wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 267:101] - wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 265:119] - wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 265:117] - wire _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 266:75] - wire _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 266:95] - wire _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 266:79] - wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 266:123] wire _T_4482 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 524:63] wire _T_4486 = _T_4482 | _T_4463; // @[lsu_bus_buffer.scala 524:74] wire _T_4477 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 524:63] @@ -69398,8 +69293,6 @@ module lsu_bus_buffer( reg obuf_nosend; // @[Reg.scala 27:20] wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 288:60] wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 288:29] - wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 288:77] - wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 288:75] reg [31:0] obuf_addr; // @[lib.scala 374:16] wire _T_4804 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 554:56] wire _T_4805 = obuf_valid & _T_4804; // @[lsu_bus_buffer.scala 554:38] @@ -69437,7 +69330,7 @@ module lsu_bus_buffer( wire _T_4851 = _T_4790 & _T_4847; // @[Mux.scala 27:72] wire bus_addr_match_pending = _T_4853 | _T_4851; // @[Mux.scala 27:72] wire _T_1239 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 288:118] - wire _T_1240 = _T_1236 & _T_1239; // @[lsu_bus_buffer.scala 288:116] + wire _T_1240 = _T_1234 & _T_1239; // @[lsu_bus_buffer.scala 288:116] wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 288:142] wire _T_1242 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 290:47] wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 557:40] @@ -69693,6 +69586,7 @@ module lsu_bus_buffer( wire _T_1885 = _T_1875 & _T_1884; // @[lsu_bus_buffer.scala 364:76] wire _T_1886 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 364:65] wire _T_1887 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 365:30] + wire _T_1888 = ibuf_valid & _T_1887; // @[lsu_bus_buffer.scala 365:19] wire _T_1889 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 366:18] wire _T_1890 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 366:57] wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] @@ -69768,17 +69662,15 @@ module lsu_bus_buffer( wire _T_2125 = _T_2123 | _T_2104[7]; // @[lsu_bus_buffer.scala 386:104] wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 444:77] - wire _T_3533 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 444:97] - wire _T_3534 = _T_3532 & _T_3533; // @[lsu_bus_buffer.scala 444:95] wire _T_3535 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3536 = _T_3534 & _T_3535; // @[lsu_bus_buffer.scala 444:112] + wire _T_3536 = _T_3532 & _T_3535; // @[lsu_bus_buffer.scala 444:112] wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 444:144] wire _T_3538 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 444:161] wire _T_3540 = _T_3536 | _T_3539; // @[lsu_bus_buffer.scala 444:132] wire _T_3541 = _T_853 & _T_3540; // @[lsu_bus_buffer.scala 444:63] wire _T_3542 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3543 = ibuf_drain_vld & _T_3542; // @[lsu_bus_buffer.scala 444:201] + wire _T_3543 = ibuf_valid & _T_3542; // @[lsu_bus_buffer.scala 444:201] wire _T_3544 = _T_3541 | _T_3543; // @[lsu_bus_buffer.scala 444:183] wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 451:46] wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] @@ -69846,7 +69738,7 @@ module lsu_bus_buffer( wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] wire _T_2129 = _T_1853 & buf_state_en_0; // @[lsu_bus_buffer.scala 406:94] - wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 408:23] + wire _T_2135 = ibuf_valid & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 408:23] wire _T_2137 = _T_2135 & _T_3532; // @[lsu_bus_buffer.scala 408:41] wire _T_2139 = _T_2137 & _T_1856; // @[lsu_bus_buffer.scala 408:71] wire _T_2141 = _T_2139 & _T_1854; // @[lsu_bus_buffer.scala 408:92] @@ -69878,13 +69770,13 @@ module lsu_bus_buffer( wire _T_2227 = _T_2225 | buf_age_0[3]; // @[lsu_bus_buffer.scala 409:97] wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] wire _T_3728 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3729 = _T_3534 & _T_3728; // @[lsu_bus_buffer.scala 444:112] + wire _T_3729 = _T_3532 & _T_3728; // @[lsu_bus_buffer.scala 444:112] wire _T_3731 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_3732 = _T_3537 & _T_3731; // @[lsu_bus_buffer.scala 444:161] wire _T_3733 = _T_3729 | _T_3732; // @[lsu_bus_buffer.scala 444:132] wire _T_3734 = _T_853 & _T_3733; // @[lsu_bus_buffer.scala 444:63] wire _T_3735 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3736 = ibuf_drain_vld & _T_3735; // @[lsu_bus_buffer.scala 444:201] + wire _T_3736 = ibuf_valid & _T_3735; // @[lsu_bus_buffer.scala 444:201] wire _T_3737 = _T_3734 | _T_3736; // @[lsu_bus_buffer.scala 444:183] wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 469:73] @@ -69968,13 +69860,13 @@ module lsu_bus_buffer( wire _T_2329 = _T_2327 | buf_age_1[3]; // @[lsu_bus_buffer.scala 409:97] wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] wire _T_3921 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3922 = _T_3534 & _T_3921; // @[lsu_bus_buffer.scala 444:112] + wire _T_3922 = _T_3532 & _T_3921; // @[lsu_bus_buffer.scala 444:112] wire _T_3924 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_3925 = _T_3537 & _T_3924; // @[lsu_bus_buffer.scala 444:161] wire _T_3926 = _T_3922 | _T_3925; // @[lsu_bus_buffer.scala 444:132] wire _T_3927 = _T_853 & _T_3926; // @[lsu_bus_buffer.scala 444:63] wire _T_3928 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3929 = ibuf_drain_vld & _T_3928; // @[lsu_bus_buffer.scala 444:201] + wire _T_3929 = ibuf_valid & _T_3928; // @[lsu_bus_buffer.scala 444:201] wire _T_3930 = _T_3927 | _T_3929; // @[lsu_bus_buffer.scala 444:183] wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] wire _T_4020 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 469:73] @@ -70058,13 +69950,13 @@ module lsu_bus_buffer( wire _T_2431 = _T_2429 | buf_age_2[3]; // @[lsu_bus_buffer.scala 409:97] wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] wire _T_4114 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_4115 = _T_3534 & _T_4114; // @[lsu_bus_buffer.scala 444:112] + wire _T_4115 = _T_3532 & _T_4114; // @[lsu_bus_buffer.scala 444:112] wire _T_4117 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_4118 = _T_3537 & _T_4117; // @[lsu_bus_buffer.scala 444:161] wire _T_4119 = _T_4115 | _T_4118; // @[lsu_bus_buffer.scala 444:132] wire _T_4120 = _T_853 & _T_4119; // @[lsu_bus_buffer.scala 444:63] wire _T_4121 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_4122 = ibuf_drain_vld & _T_4121; // @[lsu_bus_buffer.scala 444:201] + wire _T_4122 = ibuf_valid & _T_4121; // @[lsu_bus_buffer.scala 444:201] wire _T_4123 = _T_4120 | _T_4122; // @[lsu_bus_buffer.scala 444:183] wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] wire _T_4213 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 469:73] @@ -70259,11 +70151,7 @@ module lsu_bus_buffer( wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 420:88] wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 420:88] wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] - wire _T_3329 = ibuf_drain_vld & _T_1854; // @[lsu_bus_buffer.scala 426:63] - wire _T_3331 = ibuf_drain_vld & _T_1865; // @[lsu_bus_buffer.scala 426:63] - wire _T_3333 = ibuf_drain_vld & _T_1876; // @[lsu_bus_buffer.scala 426:63] - wire _T_3335 = ibuf_drain_vld & _T_1887; // @[lsu_bus_buffer.scala 426:63] - wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] + wire [3:0] ibuf_drainvec_vld = {_T_1888,_T_1877,_T_1866,_T_1855}; // @[Cat.scala 29:58] wire _T_3343 = _T_3537 & _T_1857; // @[lsu_bus_buffer.scala 428:35] wire _T_3352 = _T_3537 & _T_1868; // @[lsu_bus_buffer.scala 428:35] wire _T_3361 = _T_3537 & _T_1879; // @[lsu_bus_buffer.scala 428:35] @@ -70886,9 +70774,7 @@ module lsu_bus_buffer( assign io_lsu_axi_aw_valid = _T_4876 & _T_1239; // @[lsu_bus_buffer.scala 569:23] assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 570:25] assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 571:27] - assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 575:29] assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 572:27] - assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 574:28] assign io_lsu_axi_w_valid = _T_4888 & _T_1239; // @[lsu_bus_buffer.scala 581:22] assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 583:26] assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4892; // @[lsu_bus_buffer.scala 582:26] @@ -70896,9 +70782,7 @@ module lsu_bus_buffer( assign io_lsu_axi_ar_valid = _T_4897 & _T_1239; // @[lsu_bus_buffer.scala 586:23] assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 587:25] assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 588:27] - assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 592:29] assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 589:27] - assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 591:28] assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 598:22] assign io_lsu_busreq_r = _T_4987; // @[lsu_bus_buffer.scala 617:19] assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 526:30] @@ -71048,151 +70932,147 @@ initial begin _RAND_33 = {1{`RANDOM}}; ibuf_data = _RAND_33[31:0]; _RAND_34 = {1{`RANDOM}}; - ibuf_timer = _RAND_34[2:0]; + ibuf_sideeffect = _RAND_34[0:0]; _RAND_35 = {1{`RANDOM}}; - ibuf_sideeffect = _RAND_35[0:0]; + WrPtr1_r = _RAND_35[1:0]; _RAND_36 = {1{`RANDOM}}; - WrPtr1_r = _RAND_36[1:0]; + WrPtr0_r = _RAND_36[1:0]; _RAND_37 = {1{`RANDOM}}; - WrPtr0_r = _RAND_37[1:0]; + ibuf_tag = _RAND_37[1:0]; _RAND_38 = {1{`RANDOM}}; - ibuf_tag = _RAND_38[1:0]; + ibuf_dualtag = _RAND_38[1:0]; _RAND_39 = {1{`RANDOM}}; - ibuf_dualtag = _RAND_39[1:0]; + ibuf_dual = _RAND_39[0:0]; _RAND_40 = {1{`RANDOM}}; - ibuf_dual = _RAND_40[0:0]; + ibuf_samedw = _RAND_40[0:0]; _RAND_41 = {1{`RANDOM}}; - ibuf_samedw = _RAND_41[0:0]; + ibuf_nomerge = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; - ibuf_nomerge = _RAND_42[0:0]; + ibuf_unsign = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; - ibuf_unsign = _RAND_43[0:0]; + ibuf_sz = _RAND_43[1:0]; _RAND_44 = {1{`RANDOM}}; - ibuf_sz = _RAND_44[1:0]; + buf_nomerge_0 = _RAND_44[0:0]; _RAND_45 = {1{`RANDOM}}; - obuf_wr_timer = _RAND_45[2:0]; + buf_nomerge_1 = _RAND_45[0:0]; _RAND_46 = {1{`RANDOM}}; - buf_nomerge_0 = _RAND_46[0:0]; + buf_nomerge_2 = _RAND_46[0:0]; _RAND_47 = {1{`RANDOM}}; - buf_nomerge_1 = _RAND_47[0:0]; + buf_nomerge_3 = _RAND_47[0:0]; _RAND_48 = {1{`RANDOM}}; - buf_nomerge_2 = _RAND_48[0:0]; + _T_4330 = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; - buf_nomerge_3 = _RAND_49[0:0]; + _T_4327 = _RAND_49[0:0]; _RAND_50 = {1{`RANDOM}}; - _T_4330 = _RAND_50[0:0]; + _T_4324 = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - _T_4327 = _RAND_51[0:0]; + _T_4321 = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; - _T_4324 = _RAND_52[0:0]; + obuf_sideeffect = _RAND_52[0:0]; _RAND_53 = {1{`RANDOM}}; - _T_4321 = _RAND_53[0:0]; + buf_dual_3 = _RAND_53[0:0]; _RAND_54 = {1{`RANDOM}}; - obuf_sideeffect = _RAND_54[0:0]; + buf_dual_2 = _RAND_54[0:0]; _RAND_55 = {1{`RANDOM}}; - buf_dual_3 = _RAND_55[0:0]; + buf_dual_1 = _RAND_55[0:0]; _RAND_56 = {1{`RANDOM}}; - buf_dual_2 = _RAND_56[0:0]; + buf_dual_0 = _RAND_56[0:0]; _RAND_57 = {1{`RANDOM}}; - buf_dual_1 = _RAND_57[0:0]; + buf_samedw_3 = _RAND_57[0:0]; _RAND_58 = {1{`RANDOM}}; - buf_dual_0 = _RAND_58[0:0]; + buf_samedw_2 = _RAND_58[0:0]; _RAND_59 = {1{`RANDOM}}; - buf_samedw_3 = _RAND_59[0:0]; + buf_samedw_1 = _RAND_59[0:0]; _RAND_60 = {1{`RANDOM}}; - buf_samedw_2 = _RAND_60[0:0]; + buf_samedw_0 = _RAND_60[0:0]; _RAND_61 = {1{`RANDOM}}; - buf_samedw_1 = _RAND_61[0:0]; + obuf_write = _RAND_61[0:0]; _RAND_62 = {1{`RANDOM}}; - buf_samedw_0 = _RAND_62[0:0]; + obuf_cmd_done = _RAND_62[0:0]; _RAND_63 = {1{`RANDOM}}; - obuf_write = _RAND_63[0:0]; + obuf_data_done = _RAND_63[0:0]; _RAND_64 = {1{`RANDOM}}; - obuf_cmd_done = _RAND_64[0:0]; + obuf_nosend = _RAND_64[0:0]; _RAND_65 = {1{`RANDOM}}; - obuf_data_done = _RAND_65[0:0]; + obuf_addr = _RAND_65[31:0]; _RAND_66 = {1{`RANDOM}}; - obuf_nosend = _RAND_66[0:0]; + buf_sz_0 = _RAND_66[1:0]; _RAND_67 = {1{`RANDOM}}; - obuf_addr = _RAND_67[31:0]; + buf_sz_1 = _RAND_67[1:0]; _RAND_68 = {1{`RANDOM}}; - buf_sz_0 = _RAND_68[1:0]; + buf_sz_2 = _RAND_68[1:0]; _RAND_69 = {1{`RANDOM}}; - buf_sz_1 = _RAND_69[1:0]; + buf_sz_3 = _RAND_69[1:0]; _RAND_70 = {1{`RANDOM}}; - buf_sz_2 = _RAND_70[1:0]; + obuf_rdrsp_pend = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - buf_sz_3 = _RAND_71[1:0]; + obuf_rdrsp_tag = _RAND_71[2:0]; _RAND_72 = {1{`RANDOM}}; - obuf_rdrsp_pend = _RAND_72[0:0]; + buf_dualhi_3 = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; - obuf_rdrsp_tag = _RAND_73[2:0]; + buf_dualhi_2 = _RAND_73[0:0]; _RAND_74 = {1{`RANDOM}}; - buf_dualhi_3 = _RAND_74[0:0]; + buf_dualhi_1 = _RAND_74[0:0]; _RAND_75 = {1{`RANDOM}}; - buf_dualhi_2 = _RAND_75[0:0]; + buf_dualhi_0 = _RAND_75[0:0]; _RAND_76 = {1{`RANDOM}}; - buf_dualhi_1 = _RAND_76[0:0]; + obuf_sz = _RAND_76[1:0]; _RAND_77 = {1{`RANDOM}}; - buf_dualhi_0 = _RAND_77[0:0]; - _RAND_78 = {1{`RANDOM}}; - obuf_sz = _RAND_78[1:0]; + obuf_byteen = _RAND_77[7:0]; + _RAND_78 = {2{`RANDOM}}; + obuf_data = _RAND_78[63:0]; _RAND_79 = {1{`RANDOM}}; - obuf_byteen = _RAND_79[7:0]; - _RAND_80 = {2{`RANDOM}}; - obuf_data = _RAND_80[63:0]; + buf_rspageQ_0 = _RAND_79[3:0]; + _RAND_80 = {1{`RANDOM}}; + buf_rspageQ_1 = _RAND_80[3:0]; _RAND_81 = {1{`RANDOM}}; - buf_rspageQ_0 = _RAND_81[3:0]; + buf_rspageQ_2 = _RAND_81[3:0]; _RAND_82 = {1{`RANDOM}}; - buf_rspageQ_1 = _RAND_82[3:0]; + buf_rspageQ_3 = _RAND_82[3:0]; _RAND_83 = {1{`RANDOM}}; - buf_rspageQ_2 = _RAND_83[3:0]; + _T_4307 = _RAND_83[0:0]; _RAND_84 = {1{`RANDOM}}; - buf_rspageQ_3 = _RAND_84[3:0]; + _T_4305 = _RAND_84[0:0]; _RAND_85 = {1{`RANDOM}}; - _T_4307 = _RAND_85[0:0]; + _T_4303 = _RAND_85[0:0]; _RAND_86 = {1{`RANDOM}}; - _T_4305 = _RAND_86[0:0]; + _T_4301 = _RAND_86[0:0]; _RAND_87 = {1{`RANDOM}}; - _T_4303 = _RAND_87[0:0]; + buf_ldfwdtag_0 = _RAND_87[1:0]; _RAND_88 = {1{`RANDOM}}; - _T_4301 = _RAND_88[0:0]; + buf_dualtag_0 = _RAND_88[1:0]; _RAND_89 = {1{`RANDOM}}; - buf_ldfwdtag_0 = _RAND_89[1:0]; + buf_ldfwdtag_3 = _RAND_89[1:0]; _RAND_90 = {1{`RANDOM}}; - buf_dualtag_0 = _RAND_90[1:0]; + buf_ldfwdtag_2 = _RAND_90[1:0]; _RAND_91 = {1{`RANDOM}}; - buf_ldfwdtag_3 = _RAND_91[1:0]; + buf_ldfwdtag_1 = _RAND_91[1:0]; _RAND_92 = {1{`RANDOM}}; - buf_ldfwdtag_2 = _RAND_92[1:0]; + buf_dualtag_1 = _RAND_92[1:0]; _RAND_93 = {1{`RANDOM}}; - buf_ldfwdtag_1 = _RAND_93[1:0]; + buf_dualtag_2 = _RAND_93[1:0]; _RAND_94 = {1{`RANDOM}}; - buf_dualtag_1 = _RAND_94[1:0]; + buf_dualtag_3 = _RAND_94[1:0]; _RAND_95 = {1{`RANDOM}}; - buf_dualtag_2 = _RAND_95[1:0]; + _T_4336 = _RAND_95[0:0]; _RAND_96 = {1{`RANDOM}}; - buf_dualtag_3 = _RAND_96[1:0]; + _T_4339 = _RAND_96[0:0]; _RAND_97 = {1{`RANDOM}}; - _T_4336 = _RAND_97[0:0]; + _T_4342 = _RAND_97[0:0]; _RAND_98 = {1{`RANDOM}}; - _T_4339 = _RAND_98[0:0]; + _T_4345 = _RAND_98[0:0]; _RAND_99 = {1{`RANDOM}}; - _T_4342 = _RAND_99[0:0]; + _T_4411 = _RAND_99[0:0]; _RAND_100 = {1{`RANDOM}}; - _T_4345 = _RAND_100[0:0]; + _T_4406 = _RAND_100[0:0]; _RAND_101 = {1{`RANDOM}}; - _T_4411 = _RAND_101[0:0]; + _T_4401 = _RAND_101[0:0]; _RAND_102 = {1{`RANDOM}}; - _T_4406 = _RAND_102[0:0]; + _T_4396 = _RAND_102[0:0]; _RAND_103 = {1{`RANDOM}}; - _T_4401 = _RAND_103[0:0]; + lsu_nonblock_load_valid_r = _RAND_103[0:0]; _RAND_104 = {1{`RANDOM}}; - _T_4396 = _RAND_104[0:0]; - _RAND_105 = {1{`RANDOM}}; - lsu_nonblock_load_valid_r = _RAND_105[0:0]; - _RAND_106 = {1{`RANDOM}}; - _T_4987 = _RAND_106[0:0]; + _T_4987 = _RAND_104[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin buf_addr_0 = 32'h0; @@ -71296,9 +71176,6 @@ initial begin if (reset) begin ibuf_data = 32'h0; end - if (reset) begin - ibuf_timer = 3'h0; - end if (reset) begin ibuf_sideeffect = 1'h0; end @@ -71329,9 +71206,6 @@ initial begin if (reset) begin ibuf_sz = 2'h0; end - if (reset) begin - obuf_wr_timer = 3'h0; - end if (reset) begin buf_nomerge_0 = 1'h0; end @@ -71934,9 +71808,7 @@ end // initial if (reset) begin ibuf_byteen <= 4'h0; end else if (ibuf_wr_en) begin - if (_T_866) begin - ibuf_byteen <= _T_881; - end else if (io_ldst_dual_r) begin + if (io_ldst_dual_r) begin ibuf_byteen <= ldst_byteen_hi_r; end else begin ibuf_byteen <= ldst_byteen_lo_r; @@ -72100,16 +71972,7 @@ end // initial if (reset) begin ibuf_data <= 32'h0; end else begin - ibuf_data <= {_T_922,_T_893}; - end - end - always @(posedge io_lsu_free_c2_clk or posedge reset) begin - if (reset) begin - ibuf_timer <= 3'h0; - end else if (ibuf_wr_en) begin - ibuf_timer <= 3'h0; - end else if (_T_923) begin - ibuf_timer <= _T_926; + ibuf_data <= {_T_922,_T_892}; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -72149,12 +72012,10 @@ end // initial if (reset) begin ibuf_tag <= 2'h0; end else if (ibuf_wr_en) begin - if (!(_T_866)) begin - if (io_ldst_dual_r) begin - ibuf_tag <= WrPtr1_r; - end else begin - ibuf_tag <= WrPtr0_r; - end + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; end end end @@ -72200,15 +72061,6 @@ end // initial ibuf_sz <= ibuf_sz_in; end end - always @(posedge io_lsu_busm_clk or posedge reset) begin - if (reset) begin - obuf_wr_timer <= 3'h0; - end else if (obuf_wr_en) begin - obuf_wr_timer <= 3'h0; - end else if (_T_1058) begin - obuf_wr_timer <= _T_1060; - end - end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_0 <= 1'h0; @@ -72756,7 +72608,6 @@ module lsu_bus_intf( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, - input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -72774,9 +72625,7 @@ module lsu_bus_intf( output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, output [31:0] io_axi_aw_bits_addr, - output [3:0] io_axi_aw_bits_region, output [2:0] io_axi_aw_bits_size, - output [3:0] io_axi_aw_bits_cache, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, @@ -72788,9 +72637,7 @@ module lsu_bus_intf( output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, output [31:0] io_axi_ar_bits_addr, - output [3:0] io_axi_ar_bits_region, output [2:0] io_axi_ar_bits_size, - output [3:0] io_axi_ar_bits_cache, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -72851,7 +72698,6 @@ module lsu_bus_intf( wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 100:39] - wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 100:39] @@ -72901,9 +72747,7 @@ module lsu_bus_intf( wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 100:39] wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 100:39] - wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 100:39] - wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 100:39] wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 100:39] @@ -72916,9 +72760,7 @@ module lsu_bus_intf( wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 100:39] wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 100:39] - wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 100:39] - wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 100:39] @@ -73124,7 +72966,6 @@ module lsu_bus_intf( .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -73174,9 +73015,7 @@ module lsu_bus_intf( .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid), .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id), .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr), - .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region), .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size), - .io_lsu_axi_aw_bits_cache(bus_buffer_io_lsu_axi_aw_bits_cache), .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready), .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid), .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data), @@ -73189,9 +73028,7 @@ module lsu_bus_intf( .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid), .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id), .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr), - .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region), .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size), - .io_lsu_axi_ar_bits_cache(bus_buffer_io_lsu_axi_ar_bits_cache), .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready), .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid), .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id), @@ -73218,18 +73055,14 @@ module lsu_bus_intf( assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 129:43] assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 129:43] assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 129:43] - assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 129:43] assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 129:43] - assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 129:43] assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 129:43] assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 129:43] assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 129:43] - assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 129:43] - assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 129:43] assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 132:38] assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 133:38] assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 134:38] @@ -73247,7 +73080,6 @@ module lsu_bus_intf( assign bus_buffer_reset = reset; assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 102:29] assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 103:18] - assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 103:18] assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 103:18] assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 105:51] assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 106:51] @@ -73428,7 +73260,6 @@ module lsu( output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, input io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, - input io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -73457,9 +73288,7 @@ module lsu( output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, output [31:0] io_axi_aw_bits_addr, - output [3:0] io_axi_aw_bits_region, output [2:0] io_axi_aw_bits_size, - output [3:0] io_axi_aw_bits_cache, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, @@ -73471,9 +73300,7 @@ module lsu( output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, output [31:0] io_axi_ar_bits_addr, - output [3:0] io_axi_ar_bits_region, output [2:0] io_axi_ar_bits_size, - output [3:0] io_axi_ar_bits_cache, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -73898,7 +73725,6 @@ module lsu( wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 68:30] - wire bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 68:30] @@ -73916,9 +73742,7 @@ module lsu( wire bus_intf_io_axi_aw_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_aw_bits_id; // @[lsu.scala 68:30] wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 68:30] - wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_aw_bits_size; // @[lsu.scala 68:30] - wire [3:0] bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_ready; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_valid; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 68:30] @@ -73930,9 +73754,7 @@ module lsu( wire bus_intf_io_axi_ar_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_ar_bits_id; // @[lsu.scala 68:30] wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 68:30] - wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_ar_bits_size; // @[lsu.scala 68:30] - wire [3:0] bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 68:30] wire bus_intf_io_axi_r_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 68:30] @@ -74383,7 +74205,6 @@ module lsu( .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -74401,9 +74222,7 @@ module lsu( .io_axi_aw_valid(bus_intf_io_axi_aw_valid), .io_axi_aw_bits_id(bus_intf_io_axi_aw_bits_id), .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr), - .io_axi_aw_bits_region(bus_intf_io_axi_aw_bits_region), .io_axi_aw_bits_size(bus_intf_io_axi_aw_bits_size), - .io_axi_aw_bits_cache(bus_intf_io_axi_aw_bits_cache), .io_axi_w_ready(bus_intf_io_axi_w_ready), .io_axi_w_valid(bus_intf_io_axi_w_valid), .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data), @@ -74415,9 +74234,7 @@ module lsu( .io_axi_ar_valid(bus_intf_io_axi_ar_valid), .io_axi_ar_bits_id(bus_intf_io_axi_ar_bits_id), .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr), - .io_axi_ar_bits_region(bus_intf_io_axi_ar_bits_region), .io_axi_ar_bits_size(bus_intf_io_axi_ar_bits_size), - .io_axi_ar_bits_cache(bus_intf_io_axi_ar_bits_cache), .io_axi_r_valid(bus_intf_io_axi_r_valid), .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id), .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data), @@ -74502,18 +74319,14 @@ module lsu( assign io_axi_aw_valid = bus_intf_io_axi_aw_valid; // @[lsu.scala 314:49] assign io_axi_aw_bits_id = bus_intf_io_axi_aw_bits_id; // @[lsu.scala 314:49] assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 314:49] - assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 314:49] assign io_axi_aw_bits_size = bus_intf_io_axi_aw_bits_size; // @[lsu.scala 314:49] - assign io_axi_aw_bits_cache = bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 314:49] assign io_axi_w_valid = bus_intf_io_axi_w_valid; // @[lsu.scala 314:49] assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 314:49] assign io_axi_w_bits_strb = bus_intf_io_axi_w_bits_strb; // @[lsu.scala 314:49] assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 314:49] assign io_axi_ar_bits_id = bus_intf_io_axi_ar_bits_id; // @[lsu.scala 314:49] assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 314:49] - assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 314:49] assign io_axi_ar_bits_size = bus_intf_io_axi_ar_bits_size; // @[lsu.scala 314:49] - assign io_axi_ar_bits_cache = bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 314:49] assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 61:19] assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 62:24] assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 75:25] @@ -74748,7 +74561,6 @@ module lsu( assign bus_intf_reset = reset; assign bus_intf_io_scan_mode = io_scan_mode; // @[lsu.scala 285:49] assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 286:26] - assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 286:26] assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 286:26] assign bus_intf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 287:49] assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 288:49] @@ -78534,25 +78346,18 @@ module dma_ctrl( input io_iccm_ready, output io_dma_axi_aw_ready, input io_dma_axi_aw_valid, - input io_dma_axi_aw_bits_id, input [31:0] io_dma_axi_aw_bits_addr, input [2:0] io_dma_axi_aw_bits_size, output io_dma_axi_w_ready, input io_dma_axi_w_valid, input [63:0] io_dma_axi_w_bits_data, input [7:0] io_dma_axi_w_bits_strb, - input io_dma_axi_b_ready, output io_dma_axi_b_valid, - output [1:0] io_dma_axi_b_bits_resp, - output io_dma_axi_b_bits_id, output io_dma_axi_ar_ready, input io_dma_axi_ar_valid, - input io_dma_axi_ar_bits_id, input [31:0] io_dma_axi_ar_bits_addr, input [2:0] io_dma_axi_ar_bits_size, - input io_dma_axi_r_ready, output io_dma_axi_r_valid, - output io_dma_axi_r_bits_id, output [63:0] io_dma_axi_r_bits_data, output [1:0] io_dma_axi_r_bits_resp, output io_lsu_dma_dma_lsc_ctl_dma_dccm_req, @@ -78649,13 +78454,6 @@ module dma_ctrl( reg [63:0] _RAND_69; reg [31:0] _RAND_70; reg [31:0] _RAND_71; - reg [31:0] _RAND_72; - reg [31:0] _RAND_73; - reg [31:0] _RAND_74; - reg [31:0] _RAND_75; - reg [31:0] _RAND_76; - reg [31:0] _RAND_77; - reg [31:0] _RAND_78; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -79052,9 +78850,7 @@ module dma_ctrl( wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75] wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58] - wire _T_1285 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 502:61] - wire _T_1286 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 502:105] - wire bus_rsp_sent = _T_1285 | _T_1286; // @[dma_ctrl.scala 502:83] + wire bus_rsp_sent = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 502:83] wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99] wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120] reg [2:0] RspPtr; // @[Reg.scala 27:20] @@ -79136,14 +78932,6 @@ module dma_ctrl( reg [63:0] fifo_data_2; // @[lib.scala 374:16] reg [63:0] fifo_data_3; // @[lib.scala 374:16] reg [63:0] fifo_data_4; // @[lib.scala 374:16] - reg fifo_tag_0; // @[Reg.scala 27:20] - reg wrbuf_tag; // @[Reg.scala 27:20] - reg rdbuf_tag; // @[Reg.scala 27:20] - wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 467:43] - reg fifo_tag_1; // @[Reg.scala 27:20] - reg fifo_tag_2; // @[Reg.scala 27:20] - reg fifo_tag_3; // @[Reg.scala 27:20] - reg fifo_tag_4; // @[Reg.scala 27:20] wire _T_931 = WrPtr == 3'h4; // @[dma_ctrl.scala 260:30] wire [2:0] _T_934 = WrPtr + 3'h1; // @[dma_ctrl.scala 260:76] wire _T_936 = RdPtr == 3'h4; // @[dma_ctrl.scala 262:30] @@ -79210,8 +78998,7 @@ module dma_ctrl( reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 381:12] wire _T_1212 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44] wire _T_1213 = _T_1212 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 386:65] - wire bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 501:60] - wire _T_1214 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 387:44] + wire _T_1214 = bus_cmd_valid | bus_rsp_sent; // @[dma_ctrl.scala 387:44] wire _T_1215 = _T_1214 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60] wire _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94] wire _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116] @@ -79247,9 +79034,6 @@ module dma_ctrl( wire [4:0] _T_1275 = fifo_write >> RspPtr; // @[dma_ctrl.scala 483:39] wire axi_rsp_write = _T_1275[0]; // @[dma_ctrl.scala 483:39] wire [1:0] _T_1278 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 484:64] - wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 492:33] - wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 492:33] - wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 492:33] wire _T_1281 = ~axi_rsp_write; // @[dma_ctrl.scala 494:46] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), @@ -79361,11 +79145,8 @@ module dma_ctrl( assign io_dma_axi_aw_ready = ~_T_1243; // @[dma_ctrl.scala 453:27] assign io_dma_axi_w_ready = ~_T_1246; // @[dma_ctrl.scala 454:27] assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 490:27] - assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 491:41] - assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 492:33] assign io_dma_axi_ar_ready = ~_T_1249; // @[dma_ctrl.scala 455:27] assign io_dma_axi_r_valid = axi_rsp_valid & _T_1281; // @[dma_ctrl.scala 494:27] - assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 498:37] assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 496:43] assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 495:41] assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40] @@ -79607,23 +79388,9 @@ initial begin _RAND_69 = {2{`RANDOM}}; fifo_data_4 = _RAND_69[63:0]; _RAND_70 = {1{`RANDOM}}; - fifo_tag_0 = _RAND_70[0:0]; + dma_nack_count = _RAND_70[2:0]; _RAND_71 = {1{`RANDOM}}; - wrbuf_tag = _RAND_71[0:0]; - _RAND_72 = {1{`RANDOM}}; - rdbuf_tag = _RAND_72[0:0]; - _RAND_73 = {1{`RANDOM}}; - fifo_tag_1 = _RAND_73[0:0]; - _RAND_74 = {1{`RANDOM}}; - fifo_tag_2 = _RAND_74[0:0]; - _RAND_75 = {1{`RANDOM}}; - fifo_tag_3 = _RAND_75[0:0]; - _RAND_76 = {1{`RANDOM}}; - fifo_tag_4 = _RAND_76[0:0]; - _RAND_77 = {1{`RANDOM}}; - dma_nack_count = _RAND_77[2:0]; - _RAND_78 = {1{`RANDOM}}; - dma_dbg_cmd_done_q = _RAND_78[0:0]; + dma_dbg_cmd_done_q = _RAND_71[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin RdPtr = 3'h0; @@ -79835,27 +79602,6 @@ initial begin if (reset) begin fifo_data_4 = 64'h0; end - if (reset) begin - fifo_tag_0 = 1'h0; - end - if (reset) begin - wrbuf_tag = 1'h0; - end - if (reset) begin - rdbuf_tag = 1'h0; - end - if (reset) begin - fifo_tag_1 = 1'h0; - end - if (reset) begin - fifo_tag_2 = 1'h0; - end - if (reset) begin - fifo_tag_3 = 1'h0; - end - if (reset) begin - fifo_tag_4 = 1'h0; - end if (reset) begin dma_nack_count = 3'h0; end @@ -80474,71 +80220,6 @@ end // initial fifo_data_4 <= _T_500; end end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_0 <= 1'h0; - end else if (fifo_cmd_en[0]) begin - if (axi_mstr_sel) begin - fifo_tag_0 <= wrbuf_tag; - end else begin - fifo_tag_0 <= rdbuf_tag; - end - end - end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - wrbuf_tag <= 1'h0; - end else if (wrbuf_en) begin - wrbuf_tag <= io_dma_axi_aw_bits_id; - end - end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - rdbuf_tag <= 1'h0; - end else if (rdbuf_en) begin - rdbuf_tag <= io_dma_axi_ar_bits_id; - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_1 <= 1'h0; - end else if (fifo_cmd_en[1]) begin - if (axi_mstr_sel) begin - fifo_tag_1 <= wrbuf_tag; - end else begin - fifo_tag_1 <= rdbuf_tag; - end - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_2 <= 1'h0; - end else if (fifo_cmd_en[2]) begin - if (axi_mstr_sel) begin - fifo_tag_2 <= wrbuf_tag; - end else begin - fifo_tag_2 <= rdbuf_tag; - end - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_3 <= 1'h0; - end else if (fifo_cmd_en[3]) begin - if (axi_mstr_sel) begin - fifo_tag_3 <= wrbuf_tag; - end else begin - fifo_tag_3 <= rdbuf_tag; - end - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_4 <= 1'h0; - end else if (fifo_cmd_en[4]) begin - fifo_tag_4 <= bus_cmd_tag; - end - end always @(posedge dma_free_clk or posedge reset) begin if (reset) begin dma_nack_count <= 3'h0; @@ -80560,85 +80241,2676 @@ end // initial end end endmodule +module axi4_to_ahb( + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + output io_axi_aw_ready, + input io_axi_aw_valid, + input [31:0] io_axi_aw_bits_addr, + input [2:0] io_axi_aw_bits_size, + output io_axi_w_ready, + input io_axi_w_valid, + input [63:0] io_axi_w_bits_data, + input [7:0] io_axi_w_bits_strb, + output io_axi_b_valid, + output [1:0] io_axi_b_bits_resp, + output io_axi_ar_ready, + input io_axi_ar_valid, + input [31:0] io_axi_ar_bits_addr, + input [2:0] io_axi_ar_bits_size, + output io_axi_r_valid, + output [63:0] io_axi_r_bits_data, + output [1:0] io_axi_r_bits_resp, + input [63:0] io_ahb_in_hrdata, + input io_ahb_in_hready, + input io_ahb_in_hresp, + output [31:0] io_ahb_out_haddr, + output [2:0] io_ahb_out_hsize, + output [1:0] io_ahb_out_htrans, + output io_ahb_out_hwrite, + output [63:0] io_ahb_out_hwdata +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [63:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [63:0] _RAND_15; + reg [63:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_en; // @[lib.scala 343:22] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_en; // @[lib.scala 343:22] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_en; // @[lib.scala 343:22] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_en; // @[lib.scala 343:22] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] + wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] + wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] + wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] + wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] + wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] + wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] + wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] + wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] + wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] + wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] + wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] + wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] + wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] + reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] + wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] + wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] + wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_3 = _T_281 ? _T_283 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] + wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] + wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] + wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] + wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] + wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] + wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] + wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] + wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] + wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] + wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] + wire _GEN_4 = _T_281 & _T_285; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] + wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] + wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] + wire [2:0] _T_295 = ahb_hresp_q ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] + wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] + wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] + wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] + wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] + wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] + wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] + reg [31:0] wrbuf_addr; // @[lib.scala 374:16] + wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] + reg [2:0] wrbuf_size; // @[Reg.scala 27:20] + wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] + reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] + reg [63:0] wrbuf_data; // @[lib.scala 374:16] + wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] + wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] + wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] + reg slvbuf_write; // @[Reg.scala 27:20] + wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] + reg slvbuf_error; // @[Reg.scala 27:20] + wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] + wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] + wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] + wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] + reg [31:0] last_bus_addr; // @[Reg.scala 27:20] + wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] + reg [63:0] buf_data; // @[lib.scala 374:16] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] + wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] + wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] + wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] + wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] + wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] + wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] + wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] + wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] + wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] + wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] + wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] + wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] + wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] + wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] + wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] + wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] + wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] + wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] + wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] + wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] + wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] + reg [31:0] buf_addr; // @[lib.scala 374:16] + wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] + wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] + wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] + wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] + wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] + wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] + wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] + wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] + wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] + reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] + reg [7:0] buf_byteen; // @[Reg.scala 27:20] + wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] + wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] + wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] + wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] + wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] + wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] + wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] + wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] + wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] + wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] + wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] + wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] + wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] + wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] + wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] + wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] + reg buf_aligned; // @[Reg.scala 27:20] + wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] + wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] + wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] + wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] + wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] + wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] + wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] + wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] + wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] + wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] + wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] + wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] + wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] + wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] + wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] + wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] + wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] + wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] + wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] + wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] + wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] + wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] + wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] + wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] + wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] + wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] + wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] + wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] + wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] + wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] + wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] + wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] + wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] + wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] + wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] + wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] + wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] + wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] + wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] + wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] + wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] + wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] + wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] + wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] + wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] + wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] + wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] + wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] + wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] + wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] + wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] + wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] + wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] + wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] + wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] + wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] + wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] + wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] + wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] + wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] + wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] + wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] + wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] + wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] + wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] + wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] + wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] + wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] + wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] + wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] + wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] + wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] + wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] + wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] + wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] + wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] + wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg [1:0] buf_size; // @[Reg.scala 27:20] + wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] + wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] + reg buf_write; // @[Reg.scala 27:20] + wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] + wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] + wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] + wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] + wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] + wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] + wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] + wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] + wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] + wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] + wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] + wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] + wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] + assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] + assign io_axi_b_valid = slave_valid_pre & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] + assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 150:22] + assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] + assign io_axi_r_valid = slave_valid_pre & _T_35; // @[axi4_to_ahb.scala 153:18] + assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] + assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] + assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] + assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] + assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] + assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] + assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + wrbuf_vld = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + wrbuf_data_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + ahb_hready_q = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ahb_htrans_q = _RAND_4[1:0]; + _RAND_5 = {1{`RANDOM}}; + ahb_hwrite_q = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + ahb_hresp_q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + cmd_doneQ = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + wrbuf_addr = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + wrbuf_size = _RAND_9[2:0]; + _RAND_10 = {1{`RANDOM}}; + wrbuf_byteen = _RAND_10[7:0]; + _RAND_11 = {2{`RANDOM}}; + wrbuf_data = _RAND_11[63:0]; + _RAND_12 = {1{`RANDOM}}; + slvbuf_write = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + slvbuf_error = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + last_bus_addr = _RAND_14[31:0]; + _RAND_15 = {2{`RANDOM}}; + buf_data = _RAND_15[63:0]; + _RAND_16 = {2{`RANDOM}}; + ahb_hrdata_q = _RAND_16[63:0]; + _RAND_17 = {1{`RANDOM}}; + buf_addr = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + buf_cmd_byte_ptrQ = _RAND_18[2:0]; + _RAND_19 = {1{`RANDOM}}; + buf_byteen = _RAND_19[7:0]; + _RAND_20 = {1{`RANDOM}}; + buf_aligned = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + buf_size = _RAND_21[1:0]; + _RAND_22 = {1{`RANDOM}}; + buf_write = _RAND_22[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_state = 3'h0; + end + if (reset) begin + wrbuf_vld = 1'h0; + end + if (reset) begin + wrbuf_data_vld = 1'h0; + end + if (reset) begin + ahb_hready_q = 1'h0; + end + if (reset) begin + ahb_htrans_q = 2'h0; + end + if (reset) begin + ahb_hwrite_q = 1'h0; + end + if (reset) begin + ahb_hresp_q = 1'h0; + end + if (reset) begin + cmd_doneQ = 1'h0; + end + if (reset) begin + wrbuf_addr = 32'h0; + end + if (reset) begin + wrbuf_size = 3'h0; + end + if (reset) begin + wrbuf_byteen = 8'h0; + end + if (reset) begin + wrbuf_data = 64'h0; + end + if (reset) begin + slvbuf_write = 1'h0; + end + if (reset) begin + slvbuf_error = 1'h0; + end + if (reset) begin + last_bus_addr = 32'h0; + end + if (reset) begin + buf_data = 64'h0; + end + if (reset) begin + ahb_hrdata_q = 64'h0; + end + if (reset) begin + buf_addr = 32'h0; + end + if (reset) begin + buf_cmd_byte_ptrQ = 3'h0; + end + if (reset) begin + buf_byteen = 8'h0; + end + if (reset) begin + buf_aligned = 1'h0; + end + if (reset) begin + buf_size = 2'h0; + end + if (reset) begin + buf_write = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_state <= 3'h0; + end else if (buf_state_en) begin + if (_T_49) begin + if (buf_write_in) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else if (_T_101) begin + if (_T_104) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_136) begin + if (ahb_hresp_q) begin + buf_state <= 3'h7; + end else if (_T_152) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_175) begin + buf_state <= 3'h3; + end else if (_T_186) begin + buf_state <= 3'h5; + end else if (_T_188) begin + buf_state <= 3'h4; + end else if (_T_281) begin + if (ahb_hresp_q) begin + buf_state <= 3'h5; + end else if (master_valid) begin + if (_T_51) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else begin + buf_state <= 3'h0; + end + end else begin + buf_state <= 3'h0; + end + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_vld <= 1'h0; + end else begin + wrbuf_vld <= _T_636 & _T_637; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_data_vld <= 1'h0; + end else begin + wrbuf_data_vld <= _T_641 & _T_637; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hready_q <= 1'h0; + end else begin + ahb_hready_q <= io_ahb_in_hready; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_htrans_q <= 2'h0; + end else begin + ahb_htrans_q <= io_ahb_out_htrans; + end + end + always @(posedge ahbm_addr_clk or posedge reset) begin + if (reset) begin + ahb_hwrite_q <= 1'h0; + end else begin + ahb_hwrite_q <= io_ahb_out_hwrite; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hresp_q <= 1'h0; + end else begin + ahb_hresp_q <= io_ahb_in_hresp; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + cmd_doneQ <= 1'h0; + end else begin + cmd_doneQ <= _T_276 & _T_691; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_addr <= 32'h0; + end else begin + wrbuf_addr <= io_axi_aw_bits_addr; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_size <= 3'h0; + end else if (wrbuf_en) begin + wrbuf_size <= io_axi_aw_bits_size; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_byteen <= 8'h0; + end else if (wrbuf_data_en) begin + wrbuf_byteen <= io_axi_w_bits_strb; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else begin + wrbuf_data <= io_axi_w_bits_data; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_write <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_write <= buf_write; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + slvbuf_error <= 1'h0; + end else if (slvbuf_error_en) begin + if (_T_49) begin + slvbuf_error <= 1'h0; + end else if (_T_101) begin + slvbuf_error <= 1'h0; + end else if (_T_136) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_175) begin + slvbuf_error <= 1'h0; + end else if (_T_186) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_188) begin + slvbuf_error <= 1'h0; + end else begin + slvbuf_error <= _GEN_6; + end + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + last_bus_addr <= 32'h0; + end else if (last_addr_en) begin + last_bus_addr <= io_ahb_out_haddr; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_data <= 64'h0; + end else if (_T_489) begin + buf_data <= ahb_hrdata_q; + end else begin + buf_data <= wrbuf_data; + end + end + always @(posedge ahbm_data_clk or posedge reset) begin + if (reset) begin + ahb_hrdata_q <= 64'h0; + end else begin + ahb_hrdata_q <= io_ahb_in_hrdata; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr <= 32'h0; + end else begin + buf_addr <= {master_addr[31:3],_T_485}; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (buf_cmd_byte_ptr_en) begin + if (_T_49) begin + if (buf_write_in) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end + end else if (_T_101) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_136) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_175) begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end else if (_T_186) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_188) begin + if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else if (_T_281) begin + if (bypass_en) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else begin + buf_cmd_byte_ptrQ <= 3'h0; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_byteen <= 8'h0; + end else if (buf_wr_en) begin + buf_byteen <= wrbuf_byteen; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_aligned <= 1'h0; + end else if (buf_wr_en) begin + buf_aligned <= buf_aligned_in; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_size <= 2'h0; + end else if (buf_wr_en) begin + buf_size <= buf_size_in[1:0]; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_write <= 1'h0; + end else if (buf_wr_en) begin + if (_T_49) begin + buf_write <= _T_51; + end else if (_T_101) begin + buf_write <= 1'h0; + end else if (_T_136) begin + buf_write <= 1'h0; + end else if (_T_175) begin + buf_write <= 1'h0; + end else if (_T_186) begin + buf_write <= 1'h0; + end else if (_T_188) begin + buf_write <= 1'h0; + end else begin + buf_write <= _GEN_8; + end + end + end +endmodule +module axi4_to_ahb_1( + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + output io_axi_aw_ready, + input io_axi_aw_valid, + input [2:0] io_axi_aw_bits_id, + input [31:0] io_axi_aw_bits_addr, + input [2:0] io_axi_aw_bits_size, + output io_axi_w_ready, + input io_axi_w_valid, + input [63:0] io_axi_w_bits_data, + input [7:0] io_axi_w_bits_strb, + output io_axi_b_valid, + output [1:0] io_axi_b_bits_resp, + output [2:0] io_axi_b_bits_id, + output io_axi_ar_ready, + input io_axi_ar_valid, + input [2:0] io_axi_ar_bits_id, + input [31:0] io_axi_ar_bits_addr, + input [2:0] io_axi_ar_bits_size, + output io_axi_r_valid, + output [2:0] io_axi_r_bits_id, + output [63:0] io_axi_r_bits_data, + output [1:0] io_axi_r_bits_resp, + input [63:0] io_ahb_in_hrdata, + input io_ahb_in_hready, + input io_ahb_in_hresp, + output [31:0] io_ahb_out_haddr, + output [2:0] io_ahb_out_hsize, + output [1:0] io_ahb_out_htrans, + output io_ahb_out_hwrite, + output [63:0] io_ahb_out_hwdata +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [63:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [63:0] _RAND_17; + reg [63:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_en; // @[lib.scala 343:22] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_en; // @[lib.scala 343:22] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_en; // @[lib.scala 343:22] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_en; // @[lib.scala 343:22] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] + wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] + wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] + wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] + wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] + wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] + wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] + wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] + wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] + wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] + wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] + wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] + wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] + wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] + reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] + wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] + wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] + wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_3 = _T_281 ? _T_283 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] + wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] + wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] + wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] + wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] + wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] + wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] + wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] + wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] + wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] + wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] + wire _GEN_4 = _T_281 & _T_285; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] + wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] + wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] + wire [2:0] _T_295 = ahb_hresp_q ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] + wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] + wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] + wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] + wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] + wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] + wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] + reg [2:0] wrbuf_tag; // @[Reg.scala 27:20] + reg [31:0] wrbuf_addr; // @[lib.scala 374:16] + wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] + reg [2:0] wrbuf_size; // @[Reg.scala 27:20] + wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] + reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] + reg [63:0] wrbuf_data; // @[lib.scala 374:16] + wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] + wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] + wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] + reg slvbuf_write; // @[Reg.scala 27:20] + wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] + reg slvbuf_error; // @[Reg.scala 27:20] + wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] + wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] + wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] + reg [2:0] slvbuf_tag; // @[Reg.scala 27:20] + wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] + reg [31:0] last_bus_addr; // @[Reg.scala 27:20] + wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] + reg [63:0] buf_data; // @[lib.scala 374:16] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] + wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] + wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] + wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] + wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] + wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] + wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] + wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] + wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] + wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] + wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] + wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] + wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] + wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] + wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] + wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] + wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] + wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] + wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] + wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] + wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] + wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] + reg [31:0] buf_addr; // @[lib.scala 374:16] + wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] + wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] + wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] + wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] + wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] + wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] + wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] + wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] + wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] + reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] + reg [7:0] buf_byteen; // @[Reg.scala 27:20] + wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] + wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] + wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] + wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] + wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] + wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] + wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] + wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] + wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] + wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] + wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] + wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] + wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] + wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] + wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] + wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] + reg buf_aligned; // @[Reg.scala 27:20] + wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] + wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] + wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] + wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] + wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] + wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] + wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] + wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] + wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] + wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] + wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] + wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] + wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] + wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] + wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] + wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] + wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] + wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] + wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] + wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] + wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] + wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] + wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] + wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] + wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] + wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] + wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] + wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] + wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] + wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] + wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] + wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] + wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] + wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] + wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] + wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] + wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] + wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] + wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] + wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] + wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] + wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] + wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] + wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] + wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] + wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] + wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] + wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] + wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] + wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] + wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] + wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] + wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] + wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] + wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] + wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] + wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] + wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] + wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] + wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] + wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] + wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] + wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] + wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] + wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] + wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] + wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] + wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] + wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] + wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] + wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] + wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] + wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] + wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] + wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] + wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] + wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg [1:0] buf_size; // @[Reg.scala 27:20] + wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] + wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] + reg buf_write; // @[Reg.scala 27:20] + wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] + wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] + wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] + wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] + wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] + wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] + wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] + reg [2:0] buf_tag; // @[Reg.scala 27:20] + wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] + wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] + wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] + wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] + wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] + wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] + assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] + assign io_axi_b_valid = slave_valid_pre & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] + assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 150:22] + assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 151:20] + assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] + assign io_axi_r_valid = slave_valid_pre & _T_35; // @[axi4_to_ahb.scala 153:18] + assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 155:20] + assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] + assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] + assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] + assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] + assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] + assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] + assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + wrbuf_vld = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + wrbuf_data_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + ahb_hready_q = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ahb_htrans_q = _RAND_4[1:0]; + _RAND_5 = {1{`RANDOM}}; + ahb_hwrite_q = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + ahb_hresp_q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + cmd_doneQ = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + wrbuf_tag = _RAND_8[2:0]; + _RAND_9 = {1{`RANDOM}}; + wrbuf_addr = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + wrbuf_size = _RAND_10[2:0]; + _RAND_11 = {1{`RANDOM}}; + wrbuf_byteen = _RAND_11[7:0]; + _RAND_12 = {2{`RANDOM}}; + wrbuf_data = _RAND_12[63:0]; + _RAND_13 = {1{`RANDOM}}; + slvbuf_write = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + slvbuf_error = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + slvbuf_tag = _RAND_15[2:0]; + _RAND_16 = {1{`RANDOM}}; + last_bus_addr = _RAND_16[31:0]; + _RAND_17 = {2{`RANDOM}}; + buf_data = _RAND_17[63:0]; + _RAND_18 = {2{`RANDOM}}; + ahb_hrdata_q = _RAND_18[63:0]; + _RAND_19 = {1{`RANDOM}}; + buf_addr = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + buf_cmd_byte_ptrQ = _RAND_20[2:0]; + _RAND_21 = {1{`RANDOM}}; + buf_byteen = _RAND_21[7:0]; + _RAND_22 = {1{`RANDOM}}; + buf_aligned = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + buf_size = _RAND_23[1:0]; + _RAND_24 = {1{`RANDOM}}; + buf_write = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + buf_tag = _RAND_25[2:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_state = 3'h0; + end + if (reset) begin + wrbuf_vld = 1'h0; + end + if (reset) begin + wrbuf_data_vld = 1'h0; + end + if (reset) begin + ahb_hready_q = 1'h0; + end + if (reset) begin + ahb_htrans_q = 2'h0; + end + if (reset) begin + ahb_hwrite_q = 1'h0; + end + if (reset) begin + ahb_hresp_q = 1'h0; + end + if (reset) begin + cmd_doneQ = 1'h0; + end + if (reset) begin + wrbuf_tag = 3'h0; + end + if (reset) begin + wrbuf_addr = 32'h0; + end + if (reset) begin + wrbuf_size = 3'h0; + end + if (reset) begin + wrbuf_byteen = 8'h0; + end + if (reset) begin + wrbuf_data = 64'h0; + end + if (reset) begin + slvbuf_write = 1'h0; + end + if (reset) begin + slvbuf_error = 1'h0; + end + if (reset) begin + slvbuf_tag = 3'h0; + end + if (reset) begin + last_bus_addr = 32'h0; + end + if (reset) begin + buf_data = 64'h0; + end + if (reset) begin + ahb_hrdata_q = 64'h0; + end + if (reset) begin + buf_addr = 32'h0; + end + if (reset) begin + buf_cmd_byte_ptrQ = 3'h0; + end + if (reset) begin + buf_byteen = 8'h0; + end + if (reset) begin + buf_aligned = 1'h0; + end + if (reset) begin + buf_size = 2'h0; + end + if (reset) begin + buf_write = 1'h0; + end + if (reset) begin + buf_tag = 3'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_state <= 3'h0; + end else if (buf_state_en) begin + if (_T_49) begin + if (buf_write_in) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else if (_T_101) begin + if (_T_104) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_136) begin + if (ahb_hresp_q) begin + buf_state <= 3'h7; + end else if (_T_152) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_175) begin + buf_state <= 3'h3; + end else if (_T_186) begin + buf_state <= 3'h5; + end else if (_T_188) begin + buf_state <= 3'h4; + end else if (_T_281) begin + if (ahb_hresp_q) begin + buf_state <= 3'h5; + end else if (master_valid) begin + if (_T_51) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else begin + buf_state <= 3'h0; + end + end else begin + buf_state <= 3'h0; + end + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_vld <= 1'h0; + end else begin + wrbuf_vld <= _T_636 & _T_637; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_data_vld <= 1'h0; + end else begin + wrbuf_data_vld <= _T_641 & _T_637; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hready_q <= 1'h0; + end else begin + ahb_hready_q <= io_ahb_in_hready; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_htrans_q <= 2'h0; + end else begin + ahb_htrans_q <= io_ahb_out_htrans; + end + end + always @(posedge ahbm_addr_clk or posedge reset) begin + if (reset) begin + ahb_hwrite_q <= 1'h0; + end else begin + ahb_hwrite_q <= io_ahb_out_hwrite; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hresp_q <= 1'h0; + end else begin + ahb_hresp_q <= io_ahb_in_hresp; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + cmd_doneQ <= 1'h0; + end else begin + cmd_doneQ <= _T_276 & _T_691; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_tag <= 3'h0; + end else if (wrbuf_en) begin + wrbuf_tag <= io_axi_aw_bits_id; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_addr <= 32'h0; + end else begin + wrbuf_addr <= io_axi_aw_bits_addr; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_size <= 3'h0; + end else if (wrbuf_en) begin + wrbuf_size <= io_axi_aw_bits_size; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_byteen <= 8'h0; + end else if (wrbuf_data_en) begin + wrbuf_byteen <= io_axi_w_bits_strb; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else begin + wrbuf_data <= io_axi_w_bits_data; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_write <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_write <= buf_write; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + slvbuf_error <= 1'h0; + end else if (slvbuf_error_en) begin + if (_T_49) begin + slvbuf_error <= 1'h0; + end else if (_T_101) begin + slvbuf_error <= 1'h0; + end else if (_T_136) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_175) begin + slvbuf_error <= 1'h0; + end else if (_T_186) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_188) begin + slvbuf_error <= 1'h0; + end else begin + slvbuf_error <= _GEN_6; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_tag <= 3'h0; + end else if (slvbuf_wr_en) begin + slvbuf_tag <= buf_tag; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + last_bus_addr <= 32'h0; + end else if (last_addr_en) begin + last_bus_addr <= io_ahb_out_haddr; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_data <= 64'h0; + end else if (_T_489) begin + buf_data <= ahb_hrdata_q; + end else begin + buf_data <= wrbuf_data; + end + end + always @(posedge ahbm_data_clk or posedge reset) begin + if (reset) begin + ahb_hrdata_q <= 64'h0; + end else begin + ahb_hrdata_q <= io_ahb_in_hrdata; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr <= 32'h0; + end else begin + buf_addr <= {master_addr[31:3],_T_485}; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (buf_cmd_byte_ptr_en) begin + if (_T_49) begin + if (buf_write_in) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end + end else if (_T_101) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_136) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_175) begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end else if (_T_186) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_188) begin + if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else if (_T_281) begin + if (bypass_en) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else begin + buf_cmd_byte_ptrQ <= 3'h0; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_byteen <= 8'h0; + end else if (buf_wr_en) begin + buf_byteen <= wrbuf_byteen; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_aligned <= 1'h0; + end else if (buf_wr_en) begin + buf_aligned <= buf_aligned_in; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_size <= 2'h0; + end else if (buf_wr_en) begin + buf_size <= buf_size_in[1:0]; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_write <= 1'h0; + end else if (buf_wr_en) begin + if (_T_49) begin + buf_write <= _T_51; + end else if (_T_101) begin + buf_write <= 1'h0; + end else if (_T_136) begin + buf_write <= 1'h0; + end else if (_T_175) begin + buf_write <= 1'h0; + end else if (_T_186) begin + buf_write <= 1'h0; + end else if (_T_188) begin + buf_write <= 1'h0; + end else begin + buf_write <= _GEN_8; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_tag <= 3'h0; + end else if (buf_wr_en) begin + if (wr_cmd_vld) begin + buf_tag <= wrbuf_tag; + end else begin + buf_tag <= io_axi_ar_bits_id; + end + end + end +endmodule +module ahb_to_axi4( + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_axi_aw_ready, + output io_axi_aw_valid, + output [31:0] io_axi_aw_bits_addr, + output [2:0] io_axi_aw_bits_size, + output io_axi_w_valid, + output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, + input io_axi_ar_ready, + output io_axi_ar_valid, + output [31:0] io_axi_ar_bits_addr, + output [2:0] io_axi_ar_bits_size, + input io_axi_r_valid, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + output [63:0] io_ahb_sig_in_hrdata, + output io_ahb_sig_in_hready, + output io_ahb_sig_in_hresp, + input [31:0] io_ahb_sig_out_haddr, + input [2:0] io_ahb_sig_out_hsize, + input [1:0] io_ahb_sig_out_htrans, + input io_ahb_sig_out_hwrite, + input [63:0] io_ahb_sig_out_hwdata, + input io_ahb_hsel, + input io_ahb_hreadyin +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [63:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [63:0] _RAND_14; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_en; // @[lib.scala 343:22] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_en; // @[lib.scala 343:22] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] + wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 44:33 ahb_to_axi4.scala 133:31] + reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 126:65] + wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29] + wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29] + wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 43:33 ahb_to_axi4.scala 132:31] + reg [1:0] buf_state; // @[Reg.scala 27:20] + wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30] + wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 104:55] + wire _T_10 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 76:34] + wire _T_11 = _T_10 & io_ahb_hsel; // @[ahb_to_axi4.scala 76:61] + wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30] + wire _T_14 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 79:79] + wire _T_15 = io_ahb_sig_in_hresp | _T_14; // @[ahb_to_axi4.scala 79:48] + wire _T_16 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 79:93] + wire _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 79:91] + wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 57:33 ahb_to_axi4.scala 180:27] + reg cmdbuf_vld; // @[ahb_to_axi4.scala 139:61] + wire _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 137:67] + wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 137:105] + wire _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 137:86] + wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 137:48] + wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 137:46] + wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 80:24] + wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 80:37] + wire _T_25 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 81:92] + wire _T_26 = _T_25 & io_ahb_hsel; // @[ahb_to_axi4.scala 81:110] + wire _T_27 = io_ahb_sig_in_hresp | _T_26; // @[ahb_to_axi4.scala 81:60] + wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 81:38] + wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 81:36] + wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_34 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 86:23] + wire _T_36 = _T_34 & _T_21; // @[ahb_to_axi4.scala 86:44] + wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30] + reg cmdbuf_write; // @[Reg.scala 27:20] + wire _T_38 = ~cmdbuf_write; // @[ahb_to_axi4.scala 90:40] + wire _T_39 = io_axi_r_valid & _T_38; // @[ahb_to_axi4.scala 90:38] + wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 92:68] + wire _GEN_1 = _T_37 & _T_39; // @[Conditional.scala 39:67] + wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67] + wire buf_state_en = _T_7 ? _T_11 : _GEN_10; // @[Conditional.scala 40:58] + wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 92:41] + wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67] + wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_30 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67] + wire _GEN_11 = _T_12 ? _T_29 : _GEN_6; // @[Conditional.scala 39:67] + wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] + wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] + reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 124:65] + wire _T_46 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 97:60] + wire [7:0] _T_48 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_50 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 97:78] + wire [7:0] _T_51 = _T_48 & _T_50; // @[ahb_to_axi4.scala 97:70] + wire _T_53 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 98:30] + wire [7:0] _T_55 = _T_53 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [8:0] _T_57 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:48] + wire [8:0] _GEN_23 = {{1'd0}, _T_55}; // @[ahb_to_axi4.scala 98:40] + wire [8:0] _T_58 = _GEN_23 & _T_57; // @[ahb_to_axi4.scala 98:40] + wire [8:0] _GEN_24 = {{1'd0}, _T_51}; // @[ahb_to_axi4.scala 97:109] + wire [8:0] _T_59 = _GEN_24 | _T_58; // @[ahb_to_axi4.scala 97:109] + wire _T_61 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 99:30] + wire [7:0] _T_63 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [10:0] _T_65 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 99:48] + wire [10:0] _GEN_25 = {{3'd0}, _T_63}; // @[ahb_to_axi4.scala 99:40] + wire [10:0] _T_66 = _GEN_25 & _T_65; // @[ahb_to_axi4.scala 99:40] + wire [10:0] _GEN_26 = {{2'd0}, _T_59}; // @[ahb_to_axi4.scala 98:79] + wire [10:0] _T_67 = _GEN_26 | _T_66; // @[ahb_to_axi4.scala 98:79] + wire _T_69 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 100:30] + wire [7:0] _T_71 = _T_69 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [10:0] _GEN_27 = {{3'd0}, _T_71}; // @[ahb_to_axi4.scala 99:79] + wire [10:0] _T_73 = _T_67 | _GEN_27; // @[ahb_to_axi4.scala 99:79] + reg ahb_hready_q; // @[ahb_to_axi4.scala 122:60] + wire _T_74 = ~ahb_hready_q; // @[ahb_to_axi4.scala 103:80] + reg ahb_hresp_q; // @[ahb_to_axi4.scala 121:60] + wire _T_75 = ahb_hresp_q & _T_74; // @[ahb_to_axi4.scala 103:78] + wire _T_77 = buf_state == 2'h0; // @[ahb_to_axi4.scala 103:124] + wire _T_78 = _T_21 | _T_77; // @[ahb_to_axi4.scala 103:111] + wire _T_79 = buf_state == 2'h2; // @[ahb_to_axi4.scala 103:149] + wire _T_80 = buf_state == 2'h3; // @[ahb_to_axi4.scala 103:168] + wire _T_81 = _T_79 | _T_80; // @[ahb_to_axi4.scala 103:156] + wire _T_82 = ~_T_81; // @[ahb_to_axi4.scala 103:137] + wire _T_83 = _T_78 & _T_82; // @[ahb_to_axi4.scala 103:135] + reg buf_read_error; // @[ahb_to_axi4.scala 118:60] + wire _T_84 = ~buf_read_error; // @[ahb_to_axi4.scala 103:181] + wire _T_85 = _T_83 & _T_84; // @[ahb_to_axi4.scala 103:179] + wire [1:0] _T_89 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 45:33 ahb_to_axi4.scala 134:31] + reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 117:66] + reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 123:60] + wire _T_94 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 107:61] + wire _T_95 = buf_state != 2'h0; // @[ahb_to_axi4.scala 107:83] + wire _T_96 = _T_94 & _T_95; // @[ahb_to_axi4.scala 107:70] + wire _T_97 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 108:26] + wire _T_98 = ~_T_97; // @[ahb_to_axi4.scala 108:7] + reg ahb_hwrite_q; // @[ahb_to_axi4.scala 125:65] + wire _T_99 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 109:46] + wire _T_100 = ahb_addr_in_iccm | _T_99; // @[ahb_to_axi4.scala 109:26] + wire _T_102 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 109:86] + wire _T_104 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 109:115] + wire _T_105 = _T_102 | _T_104; // @[ahb_to_axi4.scala 109:95] + wire _T_106 = ~_T_105; // @[ahb_to_axi4.scala 109:66] + wire _T_107 = _T_100 & _T_106; // @[ahb_to_axi4.scala 109:64] + wire _T_108 = _T_98 | _T_107; // @[ahb_to_axi4.scala 108:47] + wire _T_112 = _T_53 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 110:35] + wire _T_113 = _T_108 | _T_112; // @[ahb_to_axi4.scala 109:126] + wire _T_117 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 111:56] + wire _T_118 = _T_61 & _T_117; // @[ahb_to_axi4.scala 111:35] + wire _T_119 = _T_113 | _T_118; // @[ahb_to_axi4.scala 110:55] + wire _T_123 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 112:56] + wire _T_124 = _T_69 & _T_123; // @[ahb_to_axi4.scala 112:35] + wire _T_125 = _T_119 | _T_124; // @[ahb_to_axi4.scala 111:61] + wire _T_126 = _T_96 & _T_125; // @[ahb_to_axi4.scala 107:94] + wire _T_127 = _T_126 | buf_read_error; // @[ahb_to_axi4.scala 112:63] + wire _T_146 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 136:113] + wire _T_147 = _T_153 & _T_146; // @[ahb_to_axi4.scala 136:111] + wire _T_149 = io_ahb_sig_in_hresp & _T_38; // @[ahb_to_axi4.scala 136:151] + wire cmdbuf_rst = _T_147 | _T_149; // @[ahb_to_axi4.scala 136:128] + wire _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 139:66] + wire _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 139:110] + reg [2:0] _T_164; // @[Reg.scala 27:20] + reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] + wire [7:0] master_wstrb = _T_73[7:0]; // @[ahb_to_axi4.scala 97:31] + reg [31:0] cmdbuf_addr; // @[lib.scala 374:16] + reg [63:0] cmdbuf_wdata; // @[lib.scala 374:16] + wire [1:0] cmdbuf_size = _T_164[1:0]; // @[ahb_to_axi4.scala 145:31] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 156:28] + assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 158:33] + assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33] + assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 164:28] + assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:33] + assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 166:33] + assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 171:28] + assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 173:33] + assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33] + assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 106:38] + assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_75 : _T_85; // @[ahb_to_axi4.scala 103:38] + assign io_ahb_sig_in_hresp = _T_127 | _T_75; // @[ahb_to_axi4.scala 107:38] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_10; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_3_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_5_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + ahb_haddr_q = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + buf_state = _RAND_1[1:0]; + _RAND_2 = {1{`RANDOM}}; + cmdbuf_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + cmdbuf_write = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ahb_hsize_q = _RAND_4[2:0]; + _RAND_5 = {1{`RANDOM}}; + ahb_hready_q = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + ahb_hresp_q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + buf_read_error = _RAND_7[0:0]; + _RAND_8 = {2{`RANDOM}}; + buf_rdata = _RAND_8[63:0]; + _RAND_9 = {1{`RANDOM}}; + ahb_htrans_q = _RAND_9[1:0]; + _RAND_10 = {1{`RANDOM}}; + ahb_hwrite_q = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_164 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + cmdbuf_wstrb = _RAND_12[7:0]; + _RAND_13 = {1{`RANDOM}}; + cmdbuf_addr = _RAND_13[31:0]; + _RAND_14 = {2{`RANDOM}}; + cmdbuf_wdata = _RAND_14[63:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + ahb_haddr_q = 32'h0; + end + if (reset) begin + buf_state = 2'h0; + end + if (reset) begin + cmdbuf_vld = 1'h0; + end + if (reset) begin + cmdbuf_write = 1'h0; + end + if (reset) begin + ahb_hsize_q = 3'h0; + end + if (reset) begin + ahb_hready_q = 1'h0; + end + if (reset) begin + ahb_hresp_q = 1'h0; + end + if (reset) begin + buf_read_error = 1'h0; + end + if (reset) begin + buf_rdata = 64'h0; + end + if (reset) begin + ahb_htrans_q = 2'h0; + end + if (reset) begin + ahb_hwrite_q = 1'h0; + end + if (reset) begin + _T_164 = 3'h0; + end + if (reset) begin + cmdbuf_wstrb = 8'h0; + end + if (reset) begin + cmdbuf_addr = 32'h0; + end + if (reset) begin + cmdbuf_wdata = 64'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_haddr_q <= 32'h0; + end else begin + ahb_haddr_q <= io_ahb_sig_out_haddr; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + buf_state <= 2'h0; + end else if (buf_state_en) begin + if (_T_7) begin + if (io_ahb_sig_out_hwrite) begin + buf_state <= 2'h1; + end else begin + buf_state <= 2'h2; + end + end else if (_T_12) begin + if (_T_17) begin + buf_state <= 2'h0; + end else if (io_ahb_sig_out_hwrite) begin + buf_state <= 2'h1; + end else begin + buf_state <= 2'h2; + end + end else if (_T_30) begin + if (io_ahb_sig_in_hresp) begin + buf_state <= 2'h0; + end else begin + buf_state <= 2'h3; + end + end else begin + buf_state <= 2'h0; + end + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_vld <= 1'h0; + end else begin + cmdbuf_vld <= _T_157 & _T_158; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_write <= 1'h0; + end else if (cmdbuf_wr_en) begin + cmdbuf_write <= ahb_hwrite_q; + end + end + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_hsize_q <= 3'h0; + end else begin + ahb_hsize_q <= io_ahb_sig_out_hsize; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_hready_q <= 1'h0; + end else begin + ahb_hready_q <= io_ahb_sig_in_hready & io_ahb_hreadyin; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_hresp_q <= 1'h0; + end else begin + ahb_hresp_q <= io_ahb_sig_in_hresp; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + buf_read_error <= 1'h0; + end else if (_T_7) begin + buf_read_error <= 1'h0; + end else if (_T_12) begin + buf_read_error <= 1'h0; + end else if (_T_30) begin + buf_read_error <= 1'h0; + end else begin + buf_read_error <= _GEN_3; + end + end + always @(posedge buf_rdata_clk or posedge reset) begin + if (reset) begin + buf_rdata <= 64'h0; + end else begin + buf_rdata <= io_axi_r_bits_data; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_htrans_q <= 2'h0; + end else begin + ahb_htrans_q <= _T_89 & io_ahb_sig_out_htrans; + end + end + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_hwrite_q <= 1'h0; + end else begin + ahb_hwrite_q <= io_ahb_sig_out_hwrite; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + _T_164 <= 3'h0; + end else if (cmdbuf_wr_en) begin + _T_164 <= ahb_hsize_q; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_wstrb <= 8'h0; + end else if (cmdbuf_wr_en) begin + cmdbuf_wstrb <= master_wstrb; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + cmdbuf_addr <= 32'h0; + end else begin + cmdbuf_addr <= ahb_haddr_q; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + cmdbuf_wdata <= 64'h0; + end else begin + cmdbuf_wdata <= io_ahb_sig_out_hwdata; + end + end +endmodule module quasar( input clock, input reset, - input io_lsu_axi_aw_ready, - output io_lsu_axi_aw_valid, - output [2:0] io_lsu_axi_aw_bits_id, - output [31:0] io_lsu_axi_aw_bits_addr, - output [3:0] io_lsu_axi_aw_bits_region, - output [2:0] io_lsu_axi_aw_bits_size, - output [3:0] io_lsu_axi_aw_bits_cache, - input io_lsu_axi_w_ready, - output io_lsu_axi_w_valid, - output [63:0] io_lsu_axi_w_bits_data, - output [7:0] io_lsu_axi_w_bits_strb, - input io_lsu_axi_b_valid, - input [1:0] io_lsu_axi_b_bits_resp, - input [2:0] io_lsu_axi_b_bits_id, - input io_lsu_axi_ar_ready, - output io_lsu_axi_ar_valid, - output [2:0] io_lsu_axi_ar_bits_id, - output [31:0] io_lsu_axi_ar_bits_addr, - output [3:0] io_lsu_axi_ar_bits_region, - output [2:0] io_lsu_axi_ar_bits_size, - output [3:0] io_lsu_axi_ar_bits_cache, - input io_lsu_axi_r_valid, - input [2:0] io_lsu_axi_r_bits_id, - input [63:0] io_lsu_axi_r_bits_data, - input [1:0] io_lsu_axi_r_bits_resp, - input io_ifu_axi_ar_ready, - output io_ifu_axi_ar_valid, - output [2:0] io_ifu_axi_ar_bits_id, - output [31:0] io_ifu_axi_ar_bits_addr, - output [3:0] io_ifu_axi_ar_bits_region, - input io_ifu_axi_r_valid, - input [2:0] io_ifu_axi_r_bits_id, - input [63:0] io_ifu_axi_r_bits_data, - input [1:0] io_ifu_axi_r_bits_resp, - input io_sb_axi_aw_ready, - output io_sb_axi_aw_valid, - output [31:0] io_sb_axi_aw_bits_addr, - output [3:0] io_sb_axi_aw_bits_region, - output [2:0] io_sb_axi_aw_bits_size, - input io_sb_axi_w_ready, - output io_sb_axi_w_valid, - output [63:0] io_sb_axi_w_bits_data, - output [7:0] io_sb_axi_w_bits_strb, - input io_sb_axi_b_valid, - input [1:0] io_sb_axi_b_bits_resp, - input io_sb_axi_ar_ready, - output io_sb_axi_ar_valid, - output [31:0] io_sb_axi_ar_bits_addr, - output [3:0] io_sb_axi_ar_bits_region, - output [2:0] io_sb_axi_ar_bits_size, - input io_sb_axi_r_valid, - input [63:0] io_sb_axi_r_bits_data, - input [1:0] io_sb_axi_r_bits_resp, - output io_dma_axi_aw_ready, - input io_dma_axi_aw_valid, - input io_dma_axi_aw_bits_id, - input [31:0] io_dma_axi_aw_bits_addr, - input [2:0] io_dma_axi_aw_bits_size, - output io_dma_axi_w_ready, - input io_dma_axi_w_valid, - input [63:0] io_dma_axi_w_bits_data, - input [7:0] io_dma_axi_w_bits_strb, - input io_dma_axi_b_ready, - output io_dma_axi_b_valid, - output [1:0] io_dma_axi_b_bits_resp, - output io_dma_axi_b_bits_id, - output io_dma_axi_ar_ready, - input io_dma_axi_ar_valid, - input io_dma_axi_ar_bits_id, - input [31:0] io_dma_axi_ar_bits_addr, - input [2:0] io_dma_axi_ar_bits_size, - input io_dma_axi_r_ready, - output io_dma_axi_r_valid, - output io_dma_axi_r_bits_id, - output [63:0] io_dma_axi_r_bits_data, - output [1:0] io_dma_axi_r_bits_resp, + input [63:0] io_lsu_ahb_in_hrdata, + input io_lsu_ahb_in_hready, + input io_lsu_ahb_in_hresp, + output [31:0] io_lsu_ahb_out_haddr, + output [2:0] io_lsu_ahb_out_hsize, + output [1:0] io_lsu_ahb_out_htrans, + output io_lsu_ahb_out_hwrite, + output [63:0] io_lsu_ahb_out_hwdata, + input [63:0] io_ifu_ahb_in_hrdata, + input io_ifu_ahb_in_hready, + input io_ifu_ahb_in_hresp, + output [31:0] io_ifu_ahb_out_haddr, + output [2:0] io_ifu_ahb_out_hsize, + output [1:0] io_ifu_ahb_out_htrans, + output io_ifu_ahb_out_hwrite, + output [63:0] io_ifu_ahb_out_hwdata, + input [63:0] io_sb_ahb_in_hrdata, + input io_sb_ahb_in_hready, + input io_sb_ahb_in_hresp, + output [31:0] io_sb_ahb_out_haddr, + output [2:0] io_sb_ahb_out_hsize, + output [1:0] io_sb_ahb_out_htrans, + output io_sb_ahb_out_hwrite, + output [63:0] io_sb_ahb_out_hwdata, + output [63:0] io_dma_ahb_sig_in_hrdata, + output io_dma_ahb_sig_in_hready, + output io_dma_ahb_sig_in_hresp, + input [31:0] io_dma_ahb_sig_out_haddr, + input [2:0] io_dma_ahb_sig_out_hsize, + input [1:0] io_dma_ahb_sig_out_htrans, + input io_dma_ahb_sig_out_hwrite, + input [63:0] io_dma_ahb_sig_out_hwdata, + input io_dma_ahb_hsel, + input io_dma_ahb_hreadyin, input io_dbg_rst_l, input [30:0] io_rst_vec, input io_nmi_int, @@ -80831,7 +83103,6 @@ module quasar( wire ifu_io_ifu_ar_valid; // @[quasar.scala 74:19] wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 74:19] wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 74:19] - wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 74:19] wire ifu_io_ifu_r_valid; // @[quasar.scala 74:19] wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 74:19] wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 74:19] @@ -80952,6 +83223,7 @@ module quasar( wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 75:19] wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 75:19] @@ -81089,7 +83361,6 @@ module quasar( wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 75:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 75:19] @@ -81144,7 +83415,6 @@ module quasar( wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 76:19] wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 76:19] - wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 76:19] wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 76:19] wire dbg_io_sb_axi_w_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_w_valid; // @[quasar.scala 76:19] @@ -81156,7 +83426,6 @@ module quasar( wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 76:19] wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 76:19] - wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 76:19] wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 76:19] wire dbg_io_sb_axi_r_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_r_valid; // @[quasar.scala 76:19] @@ -81311,7 +83580,6 @@ module quasar( wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 78:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 78:19] @@ -81340,9 +83608,7 @@ module quasar( wire lsu_io_axi_aw_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 78:19] wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 78:19] - wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 78:19] - wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 78:19] wire lsu_io_axi_w_ready; // @[quasar.scala 78:19] wire lsu_io_axi_w_valid; // @[quasar.scala 78:19] wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 78:19] @@ -81354,9 +83620,7 @@ module quasar( wire lsu_io_axi_ar_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 78:19] wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 78:19] - wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 78:19] - wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 78:19] wire lsu_io_axi_r_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 78:19] wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 78:19] @@ -81470,25 +83734,18 @@ module quasar( wire dma_ctrl_io_iccm_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 80:24] - wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 80:24] wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 80:24] wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 80:24] wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 80:24] wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 80:24] - wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 80:24] - wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 80:24] - wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 80:24] - wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 80:24] wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 80:24] wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 80:24] - wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 80:24] - wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 80:24] wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 80:24] wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 80:24] wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 80:24] @@ -81519,6 +83776,132 @@ module quasar( wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] wire rvclkhdr_1_io_en; // @[lib.scala 343:22] wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire axi4_to_ahb_clock; // @[quasar.scala 241:32] + wire axi4_to_ahb_reset; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_clk_override; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_axi_aw_valid; // @[quasar.scala 241:32] + wire [31:0] axi4_to_ahb_io_axi_aw_bits_addr; // @[quasar.scala 241:32] + wire [2:0] axi4_to_ahb_io_axi_aw_bits_size; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_axi_w_valid; // @[quasar.scala 241:32] + wire [63:0] axi4_to_ahb_io_axi_w_bits_data; // @[quasar.scala 241:32] + wire [7:0] axi4_to_ahb_io_axi_w_bits_strb; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 241:32] + wire [1:0] axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_axi_ar_valid; // @[quasar.scala 241:32] + wire [31:0] axi4_to_ahb_io_axi_ar_bits_addr; // @[quasar.scala 241:32] + wire [2:0] axi4_to_ahb_io_axi_ar_bits_size; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 241:32] + wire [63:0] axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 241:32] + wire [1:0] axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 241:32] + wire [63:0] axi4_to_ahb_io_ahb_in_hrdata; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_ahb_in_hready; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_ahb_in_hresp; // @[quasar.scala 241:32] + wire [31:0] axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 241:32] + wire [2:0] axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 241:32] + wire [1:0] axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 241:32] + wire axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 241:32] + wire [63:0] axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 241:32] + wire axi4_to_ahb_1_clock; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_reset; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_axi_aw_ready; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_axi_aw_valid; // @[quasar.scala 242:33] + wire [2:0] axi4_to_ahb_1_io_axi_aw_bits_id; // @[quasar.scala 242:33] + wire [31:0] axi4_to_ahb_1_io_axi_aw_bits_addr; // @[quasar.scala 242:33] + wire [2:0] axi4_to_ahb_1_io_axi_aw_bits_size; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_axi_w_ready; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_axi_w_valid; // @[quasar.scala 242:33] + wire [63:0] axi4_to_ahb_1_io_axi_w_bits_data; // @[quasar.scala 242:33] + wire [7:0] axi4_to_ahb_1_io_axi_w_bits_strb; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_axi_b_valid; // @[quasar.scala 242:33] + wire [1:0] axi4_to_ahb_1_io_axi_b_bits_resp; // @[quasar.scala 242:33] + wire [2:0] axi4_to_ahb_1_io_axi_b_bits_id; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_axi_ar_valid; // @[quasar.scala 242:33] + wire [2:0] axi4_to_ahb_1_io_axi_ar_bits_id; // @[quasar.scala 242:33] + wire [31:0] axi4_to_ahb_1_io_axi_ar_bits_addr; // @[quasar.scala 242:33] + wire [2:0] axi4_to_ahb_1_io_axi_ar_bits_size; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 242:33] + wire [2:0] axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 242:33] + wire [63:0] axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 242:33] + wire [1:0] axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 242:33] + wire [63:0] axi4_to_ahb_1_io_ahb_in_hrdata; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_ahb_in_hready; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_ahb_in_hresp; // @[quasar.scala 242:33] + wire [31:0] axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 242:33] + wire [2:0] axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 242:33] + wire [1:0] axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 242:33] + wire axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 242:33] + wire [63:0] axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 242:33] + wire axi4_to_ahb_2_clock; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_reset; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_axi_aw_valid; // @[quasar.scala 243:33] + wire [2:0] axi4_to_ahb_2_io_axi_aw_bits_id; // @[quasar.scala 243:33] + wire [31:0] axi4_to_ahb_2_io_axi_aw_bits_addr; // @[quasar.scala 243:33] + wire [2:0] axi4_to_ahb_2_io_axi_aw_bits_size; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_axi_w_valid; // @[quasar.scala 243:33] + wire [63:0] axi4_to_ahb_2_io_axi_w_bits_data; // @[quasar.scala 243:33] + wire [7:0] axi4_to_ahb_2_io_axi_w_bits_strb; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 243:33] + wire [1:0] axi4_to_ahb_2_io_axi_b_bits_resp; // @[quasar.scala 243:33] + wire [2:0] axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_axi_ar_valid; // @[quasar.scala 243:33] + wire [2:0] axi4_to_ahb_2_io_axi_ar_bits_id; // @[quasar.scala 243:33] + wire [31:0] axi4_to_ahb_2_io_axi_ar_bits_addr; // @[quasar.scala 243:33] + wire [2:0] axi4_to_ahb_2_io_axi_ar_bits_size; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 243:33] + wire [2:0] axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 243:33] + wire [63:0] axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 243:33] + wire [1:0] axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 243:33] + wire [63:0] axi4_to_ahb_2_io_ahb_in_hrdata; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_ahb_in_hready; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_ahb_in_hresp; // @[quasar.scala 243:33] + wire [31:0] axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 243:33] + wire [2:0] axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 243:33] + wire [1:0] axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 243:33] + wire [63:0] axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 243:33] + wire ahb_to_axi4_clock; // @[quasar.scala 244:33] + wire ahb_to_axi4_reset; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_axi_aw_ready; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 244:33] + wire [31:0] ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 244:33] + wire [2:0] ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 244:33] + wire [63:0] ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 244:33] + wire [7:0] ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_axi_ar_ready; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 244:33] + wire [31:0] ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 244:33] + wire [2:0] ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_axi_r_valid; // @[quasar.scala 244:33] + wire [63:0] ahb_to_axi4_io_axi_r_bits_data; // @[quasar.scala 244:33] + wire [1:0] ahb_to_axi4_io_axi_r_bits_resp; // @[quasar.scala 244:33] + wire [63:0] ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 244:33] + wire [31:0] ahb_to_axi4_io_ahb_sig_out_haddr; // @[quasar.scala 244:33] + wire [2:0] ahb_to_axi4_io_ahb_sig_out_hsize; // @[quasar.scala 244:33] + wire [1:0] ahb_to_axi4_io_ahb_sig_out_htrans; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_ahb_sig_out_hwrite; // @[quasar.scala 244:33] + wire [63:0] ahb_to_axi4_io_ahb_sig_out_hwdata; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 244:33] + wire ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 244:33] wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 82:67] wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 82:70] wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 83:23] @@ -81631,7 +84014,6 @@ module quasar( .io_ifu_ar_valid(ifu_io_ifu_ar_valid), .io_ifu_ar_bits_id(ifu_io_ifu_ar_bits_id), .io_ifu_ar_bits_addr(ifu_io_ifu_ar_bits_addr), - .io_ifu_ar_bits_region(ifu_io_ifu_ar_bits_region), .io_ifu_r_valid(ifu_io_ifu_r_valid), .io_ifu_r_bits_id(ifu_io_ifu_r_bits_id), .io_ifu_r_bits_data(ifu_io_ifu_r_bits_data), @@ -81754,6 +84136,7 @@ module quasar( .io_rv_trace_pkt_rv_i_tval_ip(dec_io_rv_trace_pkt_rv_i_tval_ip), .io_dec_tlu_misc_clk_override(dec_io_dec_tlu_misc_clk_override), .io_dec_tlu_lsu_clk_override(dec_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(dec_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(dec_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(dec_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(dec_io_dec_tlu_icm_clk_override), @@ -81891,7 +84274,6 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -81948,7 +84330,6 @@ module quasar( .io_sb_axi_aw_ready(dbg_io_sb_axi_aw_ready), .io_sb_axi_aw_valid(dbg_io_sb_axi_aw_valid), .io_sb_axi_aw_bits_addr(dbg_io_sb_axi_aw_bits_addr), - .io_sb_axi_aw_bits_region(dbg_io_sb_axi_aw_bits_region), .io_sb_axi_aw_bits_size(dbg_io_sb_axi_aw_bits_size), .io_sb_axi_w_ready(dbg_io_sb_axi_w_ready), .io_sb_axi_w_valid(dbg_io_sb_axi_w_valid), @@ -81960,7 +84341,6 @@ module quasar( .io_sb_axi_ar_ready(dbg_io_sb_axi_ar_ready), .io_sb_axi_ar_valid(dbg_io_sb_axi_ar_valid), .io_sb_axi_ar_bits_addr(dbg_io_sb_axi_ar_bits_addr), - .io_sb_axi_ar_bits_region(dbg_io_sb_axi_ar_bits_region), .io_sb_axi_ar_bits_size(dbg_io_sb_axi_ar_bits_size), .io_sb_axi_r_ready(dbg_io_sb_axi_r_ready), .io_sb_axi_r_valid(dbg_io_sb_axi_r_valid), @@ -82119,7 +84499,6 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -82148,9 +84527,7 @@ module quasar( .io_axi_aw_valid(lsu_io_axi_aw_valid), .io_axi_aw_bits_id(lsu_io_axi_aw_bits_id), .io_axi_aw_bits_addr(lsu_io_axi_aw_bits_addr), - .io_axi_aw_bits_region(lsu_io_axi_aw_bits_region), .io_axi_aw_bits_size(lsu_io_axi_aw_bits_size), - .io_axi_aw_bits_cache(lsu_io_axi_aw_bits_cache), .io_axi_w_ready(lsu_io_axi_w_ready), .io_axi_w_valid(lsu_io_axi_w_valid), .io_axi_w_bits_data(lsu_io_axi_w_bits_data), @@ -82162,9 +84539,7 @@ module quasar( .io_axi_ar_valid(lsu_io_axi_ar_valid), .io_axi_ar_bits_id(lsu_io_axi_ar_bits_id), .io_axi_ar_bits_addr(lsu_io_axi_ar_bits_addr), - .io_axi_ar_bits_region(lsu_io_axi_ar_bits_region), .io_axi_ar_bits_size(lsu_io_axi_ar_bits_size), - .io_axi_ar_bits_cache(lsu_io_axi_ar_bits_cache), .io_axi_r_valid(lsu_io_axi_r_valid), .io_axi_r_bits_id(lsu_io_axi_r_bits_id), .io_axi_r_bits_data(lsu_io_axi_r_bits_data), @@ -82282,25 +84657,18 @@ module quasar( .io_iccm_ready(dma_ctrl_io_iccm_ready), .io_dma_axi_aw_ready(dma_ctrl_io_dma_axi_aw_ready), .io_dma_axi_aw_valid(dma_ctrl_io_dma_axi_aw_valid), - .io_dma_axi_aw_bits_id(dma_ctrl_io_dma_axi_aw_bits_id), .io_dma_axi_aw_bits_addr(dma_ctrl_io_dma_axi_aw_bits_addr), .io_dma_axi_aw_bits_size(dma_ctrl_io_dma_axi_aw_bits_size), .io_dma_axi_w_ready(dma_ctrl_io_dma_axi_w_ready), .io_dma_axi_w_valid(dma_ctrl_io_dma_axi_w_valid), .io_dma_axi_w_bits_data(dma_ctrl_io_dma_axi_w_bits_data), .io_dma_axi_w_bits_strb(dma_ctrl_io_dma_axi_w_bits_strb), - .io_dma_axi_b_ready(dma_ctrl_io_dma_axi_b_ready), .io_dma_axi_b_valid(dma_ctrl_io_dma_axi_b_valid), - .io_dma_axi_b_bits_resp(dma_ctrl_io_dma_axi_b_bits_resp), - .io_dma_axi_b_bits_id(dma_ctrl_io_dma_axi_b_bits_id), .io_dma_axi_ar_ready(dma_ctrl_io_dma_axi_ar_ready), .io_dma_axi_ar_valid(dma_ctrl_io_dma_axi_ar_valid), - .io_dma_axi_ar_bits_id(dma_ctrl_io_dma_axi_ar_bits_id), .io_dma_axi_ar_bits_addr(dma_ctrl_io_dma_axi_ar_bits_addr), .io_dma_axi_ar_bits_size(dma_ctrl_io_dma_axi_ar_bits_size), - .io_dma_axi_r_ready(dma_ctrl_io_dma_axi_r_ready), .io_dma_axi_r_valid(dma_ctrl_io_dma_axi_r_valid), - .io_dma_axi_r_bits_id(dma_ctrl_io_dma_axi_r_bits_id), .io_dma_axi_r_bits_data(dma_ctrl_io_dma_axi_r_bits_data), .io_dma_axi_r_bits_resp(dma_ctrl_io_dma_axi_r_bits_resp), .io_lsu_dma_dma_lsc_ctl_dma_dccm_req(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req), @@ -82336,46 +84704,158 @@ module quasar( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 284:27] - assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 284:27] - assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 284:27] - assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 284:27] - assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 284:27] - assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 284:27] - assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 284:27] - assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 284:27] - assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 284:27] - assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 284:27] - assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 284:27] - assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 284:27] - assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 284:27] - assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 284:27] - assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 284:27] - assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 283:27] - assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 283:27] - assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 283:27] - assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 283:27] - assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 282:27] - assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 282:27] - assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 282:27] - assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 282:27] - assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 282:27] - assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 282:27] - assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 282:27] - assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 282:27] - assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 282:27] - assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 282:27] - assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 282:27] - assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 281:27] - assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 281:27] - assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 281:27] - assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 281:27] - assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 281:27] - assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 281:27] - assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 281:27] - assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 281:27] - assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 281:27] - assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 281:27] + axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 241:32] + .clock(axi4_to_ahb_clock), + .reset(axi4_to_ahb_reset), + .io_scan_mode(axi4_to_ahb_io_scan_mode), + .io_bus_clk_en(axi4_to_ahb_io_bus_clk_en), + .io_clk_override(axi4_to_ahb_io_clk_override), + .io_axi_aw_ready(axi4_to_ahb_io_axi_aw_ready), + .io_axi_aw_valid(axi4_to_ahb_io_axi_aw_valid), + .io_axi_aw_bits_addr(axi4_to_ahb_io_axi_aw_bits_addr), + .io_axi_aw_bits_size(axi4_to_ahb_io_axi_aw_bits_size), + .io_axi_w_ready(axi4_to_ahb_io_axi_w_ready), + .io_axi_w_valid(axi4_to_ahb_io_axi_w_valid), + .io_axi_w_bits_data(axi4_to_ahb_io_axi_w_bits_data), + .io_axi_w_bits_strb(axi4_to_ahb_io_axi_w_bits_strb), + .io_axi_b_valid(axi4_to_ahb_io_axi_b_valid), + .io_axi_b_bits_resp(axi4_to_ahb_io_axi_b_bits_resp), + .io_axi_ar_ready(axi4_to_ahb_io_axi_ar_ready), + .io_axi_ar_valid(axi4_to_ahb_io_axi_ar_valid), + .io_axi_ar_bits_addr(axi4_to_ahb_io_axi_ar_bits_addr), + .io_axi_ar_bits_size(axi4_to_ahb_io_axi_ar_bits_size), + .io_axi_r_valid(axi4_to_ahb_io_axi_r_valid), + .io_axi_r_bits_data(axi4_to_ahb_io_axi_r_bits_data), + .io_axi_r_bits_resp(axi4_to_ahb_io_axi_r_bits_resp), + .io_ahb_in_hrdata(axi4_to_ahb_io_ahb_in_hrdata), + .io_ahb_in_hready(axi4_to_ahb_io_ahb_in_hready), + .io_ahb_in_hresp(axi4_to_ahb_io_ahb_in_hresp), + .io_ahb_out_haddr(axi4_to_ahb_io_ahb_out_haddr), + .io_ahb_out_hsize(axi4_to_ahb_io_ahb_out_hsize), + .io_ahb_out_htrans(axi4_to_ahb_io_ahb_out_htrans), + .io_ahb_out_hwrite(axi4_to_ahb_io_ahb_out_hwrite), + .io_ahb_out_hwdata(axi4_to_ahb_io_ahb_out_hwdata) + ); + axi4_to_ahb_1 axi4_to_ahb_1 ( // @[quasar.scala 242:33] + .clock(axi4_to_ahb_1_clock), + .reset(axi4_to_ahb_1_reset), + .io_scan_mode(axi4_to_ahb_1_io_scan_mode), + .io_bus_clk_en(axi4_to_ahb_1_io_bus_clk_en), + .io_clk_override(axi4_to_ahb_1_io_clk_override), + .io_axi_aw_ready(axi4_to_ahb_1_io_axi_aw_ready), + .io_axi_aw_valid(axi4_to_ahb_1_io_axi_aw_valid), + .io_axi_aw_bits_id(axi4_to_ahb_1_io_axi_aw_bits_id), + .io_axi_aw_bits_addr(axi4_to_ahb_1_io_axi_aw_bits_addr), + .io_axi_aw_bits_size(axi4_to_ahb_1_io_axi_aw_bits_size), + .io_axi_w_ready(axi4_to_ahb_1_io_axi_w_ready), + .io_axi_w_valid(axi4_to_ahb_1_io_axi_w_valid), + .io_axi_w_bits_data(axi4_to_ahb_1_io_axi_w_bits_data), + .io_axi_w_bits_strb(axi4_to_ahb_1_io_axi_w_bits_strb), + .io_axi_b_valid(axi4_to_ahb_1_io_axi_b_valid), + .io_axi_b_bits_resp(axi4_to_ahb_1_io_axi_b_bits_resp), + .io_axi_b_bits_id(axi4_to_ahb_1_io_axi_b_bits_id), + .io_axi_ar_ready(axi4_to_ahb_1_io_axi_ar_ready), + .io_axi_ar_valid(axi4_to_ahb_1_io_axi_ar_valid), + .io_axi_ar_bits_id(axi4_to_ahb_1_io_axi_ar_bits_id), + .io_axi_ar_bits_addr(axi4_to_ahb_1_io_axi_ar_bits_addr), + .io_axi_ar_bits_size(axi4_to_ahb_1_io_axi_ar_bits_size), + .io_axi_r_valid(axi4_to_ahb_1_io_axi_r_valid), + .io_axi_r_bits_id(axi4_to_ahb_1_io_axi_r_bits_id), + .io_axi_r_bits_data(axi4_to_ahb_1_io_axi_r_bits_data), + .io_axi_r_bits_resp(axi4_to_ahb_1_io_axi_r_bits_resp), + .io_ahb_in_hrdata(axi4_to_ahb_1_io_ahb_in_hrdata), + .io_ahb_in_hready(axi4_to_ahb_1_io_ahb_in_hready), + .io_ahb_in_hresp(axi4_to_ahb_1_io_ahb_in_hresp), + .io_ahb_out_haddr(axi4_to_ahb_1_io_ahb_out_haddr), + .io_ahb_out_hsize(axi4_to_ahb_1_io_ahb_out_hsize), + .io_ahb_out_htrans(axi4_to_ahb_1_io_ahb_out_htrans), + .io_ahb_out_hwrite(axi4_to_ahb_1_io_ahb_out_hwrite), + .io_ahb_out_hwdata(axi4_to_ahb_1_io_ahb_out_hwdata) + ); + axi4_to_ahb_1 axi4_to_ahb_2 ( // @[quasar.scala 243:33] + .clock(axi4_to_ahb_2_clock), + .reset(axi4_to_ahb_2_reset), + .io_scan_mode(axi4_to_ahb_2_io_scan_mode), + .io_bus_clk_en(axi4_to_ahb_2_io_bus_clk_en), + .io_clk_override(axi4_to_ahb_2_io_clk_override), + .io_axi_aw_ready(axi4_to_ahb_2_io_axi_aw_ready), + .io_axi_aw_valid(axi4_to_ahb_2_io_axi_aw_valid), + .io_axi_aw_bits_id(axi4_to_ahb_2_io_axi_aw_bits_id), + .io_axi_aw_bits_addr(axi4_to_ahb_2_io_axi_aw_bits_addr), + .io_axi_aw_bits_size(axi4_to_ahb_2_io_axi_aw_bits_size), + .io_axi_w_ready(axi4_to_ahb_2_io_axi_w_ready), + .io_axi_w_valid(axi4_to_ahb_2_io_axi_w_valid), + .io_axi_w_bits_data(axi4_to_ahb_2_io_axi_w_bits_data), + .io_axi_w_bits_strb(axi4_to_ahb_2_io_axi_w_bits_strb), + .io_axi_b_valid(axi4_to_ahb_2_io_axi_b_valid), + .io_axi_b_bits_resp(axi4_to_ahb_2_io_axi_b_bits_resp), + .io_axi_b_bits_id(axi4_to_ahb_2_io_axi_b_bits_id), + .io_axi_ar_ready(axi4_to_ahb_2_io_axi_ar_ready), + .io_axi_ar_valid(axi4_to_ahb_2_io_axi_ar_valid), + .io_axi_ar_bits_id(axi4_to_ahb_2_io_axi_ar_bits_id), + .io_axi_ar_bits_addr(axi4_to_ahb_2_io_axi_ar_bits_addr), + .io_axi_ar_bits_size(axi4_to_ahb_2_io_axi_ar_bits_size), + .io_axi_r_valid(axi4_to_ahb_2_io_axi_r_valid), + .io_axi_r_bits_id(axi4_to_ahb_2_io_axi_r_bits_id), + .io_axi_r_bits_data(axi4_to_ahb_2_io_axi_r_bits_data), + .io_axi_r_bits_resp(axi4_to_ahb_2_io_axi_r_bits_resp), + .io_ahb_in_hrdata(axi4_to_ahb_2_io_ahb_in_hrdata), + .io_ahb_in_hready(axi4_to_ahb_2_io_ahb_in_hready), + .io_ahb_in_hresp(axi4_to_ahb_2_io_ahb_in_hresp), + .io_ahb_out_haddr(axi4_to_ahb_2_io_ahb_out_haddr), + .io_ahb_out_hsize(axi4_to_ahb_2_io_ahb_out_hsize), + .io_ahb_out_htrans(axi4_to_ahb_2_io_ahb_out_htrans), + .io_ahb_out_hwrite(axi4_to_ahb_2_io_ahb_out_hwrite), + .io_ahb_out_hwdata(axi4_to_ahb_2_io_ahb_out_hwdata) + ); + ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 244:33] + .clock(ahb_to_axi4_clock), + .reset(ahb_to_axi4_reset), + .io_scan_mode(ahb_to_axi4_io_scan_mode), + .io_bus_clk_en(ahb_to_axi4_io_bus_clk_en), + .io_axi_aw_ready(ahb_to_axi4_io_axi_aw_ready), + .io_axi_aw_valid(ahb_to_axi4_io_axi_aw_valid), + .io_axi_aw_bits_addr(ahb_to_axi4_io_axi_aw_bits_addr), + .io_axi_aw_bits_size(ahb_to_axi4_io_axi_aw_bits_size), + .io_axi_w_valid(ahb_to_axi4_io_axi_w_valid), + .io_axi_w_bits_data(ahb_to_axi4_io_axi_w_bits_data), + .io_axi_w_bits_strb(ahb_to_axi4_io_axi_w_bits_strb), + .io_axi_ar_ready(ahb_to_axi4_io_axi_ar_ready), + .io_axi_ar_valid(ahb_to_axi4_io_axi_ar_valid), + .io_axi_ar_bits_addr(ahb_to_axi4_io_axi_ar_bits_addr), + .io_axi_ar_bits_size(ahb_to_axi4_io_axi_ar_bits_size), + .io_axi_r_valid(ahb_to_axi4_io_axi_r_valid), + .io_axi_r_bits_data(ahb_to_axi4_io_axi_r_bits_data), + .io_axi_r_bits_resp(ahb_to_axi4_io_axi_r_bits_resp), + .io_ahb_sig_in_hrdata(ahb_to_axi4_io_ahb_sig_in_hrdata), + .io_ahb_sig_in_hready(ahb_to_axi4_io_ahb_sig_in_hready), + .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp), + .io_ahb_sig_out_haddr(ahb_to_axi4_io_ahb_sig_out_haddr), + .io_ahb_sig_out_hsize(ahb_to_axi4_io_ahb_sig_out_hsize), + .io_ahb_sig_out_htrans(ahb_to_axi4_io_ahb_sig_out_htrans), + .io_ahb_sig_out_hwrite(ahb_to_axi4_io_ahb_sig_out_hwrite), + .io_ahb_sig_out_hwdata(ahb_to_axi4_io_ahb_sig_out_hwdata), + .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel), + .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin) + ); + assign io_lsu_ahb_out_haddr = axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 250:28] + assign io_lsu_ahb_out_hsize = axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 250:28] + assign io_lsu_ahb_out_htrans = axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 250:28] + assign io_lsu_ahb_out_hwrite = axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 250:28] + assign io_lsu_ahb_out_hwdata = axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 250:28] + assign io_ifu_ahb_out_haddr = axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 256:28] + assign io_ifu_ahb_out_hsize = axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 256:28] + assign io_ifu_ahb_out_htrans = axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 256:28] + assign io_ifu_ahb_out_hwrite = axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 256:28] + assign io_ifu_ahb_out_hwdata = axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 256:28] + assign io_sb_ahb_out_haddr = axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 263:27] + assign io_sb_ahb_out_hsize = axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 263:27] + assign io_sb_ahb_out_htrans = axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 263:27] + assign io_sb_ahb_out_hwrite = axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 263:27] + assign io_sb_ahb_out_hwdata = axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 263:27] + assign io_dma_ahb_sig_in_hrdata = ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 269:28] + assign io_dma_ahb_sig_in_hready = ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 269:28] + assign io_dma_ahb_sig_in_hresp = ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 269:28] assign io_core_rst_l = reset & _T_2; // @[quasar.scala 82:17] assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 218:19] assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 218:19] @@ -82478,11 +84958,11 @@ module quasar( assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 100:13] assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 100:13] assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 100:13] - assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 283:27] - assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 283:27] - assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 283:27] - assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 283:27] - assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 283:27] + assign ifu_io_ifu_ar_ready = axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 255:28] + assign ifu_io_ifu_r_valid = axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 255:28] + assign ifu_io_ifu_r_bits_id = axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 255:28] + assign ifu_io_ifu_r_bits_data = axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 255:28] + assign ifu_io_ifu_r_bits_resp = axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 255:28] assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 98:25] assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 99:18] assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 99:18] @@ -82624,14 +85104,14 @@ module quasar( assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 184:23] assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 185:24] assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 186:24] - assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 282:27] - assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 282:27] - assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 282:27] - assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 282:27] - assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 282:27] - assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 282:27] - assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 282:27] - assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_aw_ready = axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 262:27] + assign dbg_io_sb_axi_w_ready = axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 262:27] + assign dbg_io_sb_axi_b_valid = axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 262:27] + assign dbg_io_sb_axi_b_bits_resp = axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 262:27] + assign dbg_io_sb_axi_ar_ready = axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 262:27] + assign dbg_io_sb_axi_r_valid = axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 262:27] + assign dbg_io_sb_axi_r_bits_data = axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 262:27] + assign dbg_io_sb_axi_r_bits_resp = axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 262:27] assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 200:26] assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 187:25] assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 188:20] @@ -82719,20 +85199,19 @@ module quasar( assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 163:18] assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 163:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 122:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 122:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 122:18] assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 238:11] assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 238:11] - assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 284:27] - assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 284:27] - assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 284:27] - assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 284:27] - assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 284:27] - assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 284:27] - assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 284:27] - assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 284:27] - assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 284:27] - assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 284:27] + assign lsu_io_axi_aw_ready = axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 249:28] + assign lsu_io_axi_w_ready = axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 249:28] + assign lsu_io_axi_b_valid = axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 249:28] + assign lsu_io_axi_b_bits_resp = axi4_to_ahb_2_io_axi_b_bits_resp; // @[quasar.scala 249:28] + assign lsu_io_axi_b_bits_id = axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 249:28] + assign lsu_io_axi_ar_ready = axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 249:28] + assign lsu_io_axi_r_valid = axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 249:28] + assign lsu_io_axi_r_bits_id = axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 249:28] + assign lsu_io_axi_r_bits_data = axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 249:28] + assign lsu_io_axi_r_bits_resp = axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 249:28] assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 159:32] assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 160:35] assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 161:29] @@ -82807,19 +85286,15 @@ module quasar( assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 203:29] assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 204:30] assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 205:26] - assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 281:27] - assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_aw_valid = ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 268:28] + assign dma_ctrl_io_dma_axi_aw_bits_addr = ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 268:28] + assign dma_ctrl_io_dma_axi_aw_bits_size = ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 268:28] + assign dma_ctrl_io_dma_axi_w_valid = ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 268:28] + assign dma_ctrl_io_dma_axi_w_bits_data = ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 268:28] + assign dma_ctrl_io_dma_axi_w_bits_strb = ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 268:28] + assign dma_ctrl_io_dma_axi_ar_valid = ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 268:28] + assign dma_ctrl_io_dma_axi_ar_bits_addr = ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 268:28] + assign dma_ctrl_io_dma_axi_ar_bits_size = ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 268:28] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 171:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 171:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 171:18] @@ -82831,6 +85306,77 @@ module quasar( assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_1_io_en = _T_6 | dec_io_dec_tlu_misc_clk_override; // @[lib.scala 345:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign axi4_to_ahb_clock = clock; + assign axi4_to_ahb_reset = reset; + assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 259:33] + assign axi4_to_ahb_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 260:34] + assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 261:36] + assign axi4_to_ahb_io_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 262:27] + assign axi4_to_ahb_io_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 262:27] + assign axi4_to_ahb_io_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 262:27] + assign axi4_to_ahb_io_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 262:27] + assign axi4_to_ahb_io_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 262:27] + assign axi4_to_ahb_io_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 262:27] + assign axi4_to_ahb_io_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 262:27] + assign axi4_to_ahb_io_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 262:27] + assign axi4_to_ahb_io_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 262:27] + assign axi4_to_ahb_io_ahb_in_hrdata = io_sb_ahb_in_hrdata; // @[quasar.scala 263:27] + assign axi4_to_ahb_io_ahb_in_hready = io_sb_ahb_in_hready; // @[quasar.scala 263:27] + assign axi4_to_ahb_io_ahb_in_hresp = io_sb_ahb_in_hresp; // @[quasar.scala 263:27] + assign axi4_to_ahb_1_clock = clock; + assign axi4_to_ahb_1_reset = reset; + assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 252:34] + assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 253:35] + assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 254:37] + assign axi4_to_ahb_1_io_axi_aw_valid = 1'h0; // @[quasar.scala 255:28] + assign axi4_to_ahb_1_io_axi_aw_bits_id = 3'h0; // @[quasar.scala 255:28] + assign axi4_to_ahb_1_io_axi_aw_bits_addr = 32'h0; // @[quasar.scala 255:28] + assign axi4_to_ahb_1_io_axi_aw_bits_size = 3'h0; // @[quasar.scala 255:28] + assign axi4_to_ahb_1_io_axi_w_valid = 1'h0; // @[quasar.scala 255:28] + assign axi4_to_ahb_1_io_axi_w_bits_data = 64'h0; // @[quasar.scala 255:28] + assign axi4_to_ahb_1_io_axi_w_bits_strb = 8'h0; // @[quasar.scala 255:28] + assign axi4_to_ahb_1_io_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 255:28] + assign axi4_to_ahb_1_io_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 255:28] + assign axi4_to_ahb_1_io_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 255:28] + assign axi4_to_ahb_1_io_axi_ar_bits_size = 3'h3; // @[quasar.scala 255:28] + assign axi4_to_ahb_1_io_ahb_in_hrdata = io_ifu_ahb_in_hrdata; // @[quasar.scala 256:28] + assign axi4_to_ahb_1_io_ahb_in_hready = io_ifu_ahb_in_hready; // @[quasar.scala 256:28] + assign axi4_to_ahb_1_io_ahb_in_hresp = io_ifu_ahb_in_hresp; // @[quasar.scala 256:28] + assign axi4_to_ahb_2_clock = clock; + assign axi4_to_ahb_2_reset = reset; + assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 246:34] + assign axi4_to_ahb_2_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 247:35] + assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 248:37] + assign axi4_to_ahb_2_io_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 249:28] + assign axi4_to_ahb_2_io_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 249:28] + assign axi4_to_ahb_2_io_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 249:28] + assign axi4_to_ahb_2_io_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 249:28] + assign axi4_to_ahb_2_io_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 249:28] + assign axi4_to_ahb_2_io_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 249:28] + assign axi4_to_ahb_2_io_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 249:28] + assign axi4_to_ahb_2_io_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 249:28] + assign axi4_to_ahb_2_io_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 249:28] + assign axi4_to_ahb_2_io_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 249:28] + assign axi4_to_ahb_2_io_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 249:28] + assign axi4_to_ahb_2_io_ahb_in_hrdata = io_lsu_ahb_in_hrdata; // @[quasar.scala 250:28] + assign axi4_to_ahb_2_io_ahb_in_hready = io_lsu_ahb_in_hready; // @[quasar.scala 250:28] + assign axi4_to_ahb_2_io_ahb_in_hresp = io_lsu_ahb_in_hresp; // @[quasar.scala 250:28] + assign ahb_to_axi4_clock = clock; + assign ahb_to_axi4_reset = reset; + assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 265:34] + assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 266:35] + assign ahb_to_axi4_io_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 268:28] + assign ahb_to_axi4_io_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 268:28] + assign ahb_to_axi4_io_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 268:28] + assign ahb_to_axi4_io_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 268:28] + assign ahb_to_axi4_io_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 268:28] + assign ahb_to_axi4_io_ahb_sig_out_haddr = io_dma_ahb_sig_out_haddr; // @[quasar.scala 269:28] + assign ahb_to_axi4_io_ahb_sig_out_hsize = io_dma_ahb_sig_out_hsize; // @[quasar.scala 269:28] + assign ahb_to_axi4_io_ahb_sig_out_htrans = io_dma_ahb_sig_out_htrans; // @[quasar.scala 269:28] + assign ahb_to_axi4_io_ahb_sig_out_hwrite = io_dma_ahb_sig_out_hwrite; // @[quasar.scala 269:28] + assign ahb_to_axi4_io_ahb_sig_out_hwdata = io_dma_ahb_sig_out_hwdata; // @[quasar.scala 269:28] + assign ahb_to_axi4_io_ahb_hsel = io_dma_ahb_hsel; // @[quasar.scala 269:28] + assign ahb_to_axi4_io_ahb_hreadyin = io_dma_ahb_hreadyin; // @[quasar.scala 269:28] endmodule module quasar_wrapper( input clock, @@ -82840,162 +85386,52 @@ module quasar_wrapper( input io_nmi_int, input [30:0] io_nmi_vec, input [30:0] io_jtag_id, - input io_lsu_brg_aw_ready, - output io_lsu_brg_aw_valid, - output [2:0] io_lsu_brg_aw_bits_id, - output [31:0] io_lsu_brg_aw_bits_addr, - output [3:0] io_lsu_brg_aw_bits_region, - output [7:0] io_lsu_brg_aw_bits_len, - output [2:0] io_lsu_brg_aw_bits_size, - output [1:0] io_lsu_brg_aw_bits_burst, - output io_lsu_brg_aw_bits_lock, - output [3:0] io_lsu_brg_aw_bits_cache, - output [2:0] io_lsu_brg_aw_bits_prot, - output [3:0] io_lsu_brg_aw_bits_qos, - input io_lsu_brg_w_ready, - output io_lsu_brg_w_valid, - output [63:0] io_lsu_brg_w_bits_data, - output [7:0] io_lsu_brg_w_bits_strb, - output io_lsu_brg_w_bits_last, - output io_lsu_brg_b_ready, - input io_lsu_brg_b_valid, - input [1:0] io_lsu_brg_b_bits_resp, - input [2:0] io_lsu_brg_b_bits_id, - input io_lsu_brg_ar_ready, - output io_lsu_brg_ar_valid, - output [2:0] io_lsu_brg_ar_bits_id, - output [31:0] io_lsu_brg_ar_bits_addr, - output [3:0] io_lsu_brg_ar_bits_region, - output [7:0] io_lsu_brg_ar_bits_len, - output [2:0] io_lsu_brg_ar_bits_size, - output [1:0] io_lsu_brg_ar_bits_burst, - output io_lsu_brg_ar_bits_lock, - output [3:0] io_lsu_brg_ar_bits_cache, - output [2:0] io_lsu_brg_ar_bits_prot, - output [3:0] io_lsu_brg_ar_bits_qos, - output io_lsu_brg_r_ready, - input io_lsu_brg_r_valid, - input [2:0] io_lsu_brg_r_bits_id, - input [63:0] io_lsu_brg_r_bits_data, - input [1:0] io_lsu_brg_r_bits_resp, - input io_lsu_brg_r_bits_last, - input io_ifu_brg_aw_ready, - output io_ifu_brg_aw_valid, - output [2:0] io_ifu_brg_aw_bits_id, - output [31:0] io_ifu_brg_aw_bits_addr, - output [3:0] io_ifu_brg_aw_bits_region, - output [7:0] io_ifu_brg_aw_bits_len, - output [2:0] io_ifu_brg_aw_bits_size, - output [1:0] io_ifu_brg_aw_bits_burst, - output io_ifu_brg_aw_bits_lock, - output [3:0] io_ifu_brg_aw_bits_cache, - output [2:0] io_ifu_brg_aw_bits_prot, - output [3:0] io_ifu_brg_aw_bits_qos, - input io_ifu_brg_w_ready, - output io_ifu_brg_w_valid, - output [63:0] io_ifu_brg_w_bits_data, - output [7:0] io_ifu_brg_w_bits_strb, - output io_ifu_brg_w_bits_last, - output io_ifu_brg_b_ready, - input io_ifu_brg_b_valid, - input [1:0] io_ifu_brg_b_bits_resp, - input [2:0] io_ifu_brg_b_bits_id, - input io_ifu_brg_ar_ready, - output io_ifu_brg_ar_valid, - output [2:0] io_ifu_brg_ar_bits_id, - output [31:0] io_ifu_brg_ar_bits_addr, - output [3:0] io_ifu_brg_ar_bits_region, - output [7:0] io_ifu_brg_ar_bits_len, - output [2:0] io_ifu_brg_ar_bits_size, - output [1:0] io_ifu_brg_ar_bits_burst, - output io_ifu_brg_ar_bits_lock, - output [3:0] io_ifu_brg_ar_bits_cache, - output [2:0] io_ifu_brg_ar_bits_prot, - output [3:0] io_ifu_brg_ar_bits_qos, - output io_ifu_brg_r_ready, - input io_ifu_brg_r_valid, - input [2:0] io_ifu_brg_r_bits_id, - input [63:0] io_ifu_brg_r_bits_data, - input [1:0] io_ifu_brg_r_bits_resp, - input io_ifu_brg_r_bits_last, - input io_sb_brg_aw_ready, - output io_sb_brg_aw_valid, - output io_sb_brg_aw_bits_id, - output [31:0] io_sb_brg_aw_bits_addr, - output [3:0] io_sb_brg_aw_bits_region, - output [7:0] io_sb_brg_aw_bits_len, - output [2:0] io_sb_brg_aw_bits_size, - output [1:0] io_sb_brg_aw_bits_burst, - output io_sb_brg_aw_bits_lock, - output [3:0] io_sb_brg_aw_bits_cache, - output [2:0] io_sb_brg_aw_bits_prot, - output [3:0] io_sb_brg_aw_bits_qos, - input io_sb_brg_w_ready, - output io_sb_brg_w_valid, - output [63:0] io_sb_brg_w_bits_data, - output [7:0] io_sb_brg_w_bits_strb, - output io_sb_brg_w_bits_last, - output io_sb_brg_b_ready, - input io_sb_brg_b_valid, - input [1:0] io_sb_brg_b_bits_resp, - input io_sb_brg_b_bits_id, - input io_sb_brg_ar_ready, - output io_sb_brg_ar_valid, - output io_sb_brg_ar_bits_id, - output [31:0] io_sb_brg_ar_bits_addr, - output [3:0] io_sb_brg_ar_bits_region, - output [7:0] io_sb_brg_ar_bits_len, - output [2:0] io_sb_brg_ar_bits_size, - output [1:0] io_sb_brg_ar_bits_burst, - output io_sb_brg_ar_bits_lock, - output [3:0] io_sb_brg_ar_bits_cache, - output [2:0] io_sb_brg_ar_bits_prot, - output [3:0] io_sb_brg_ar_bits_qos, - output io_sb_brg_r_ready, - input io_sb_brg_r_valid, - input io_sb_brg_r_bits_id, - input [63:0] io_sb_brg_r_bits_data, - input [1:0] io_sb_brg_r_bits_resp, - input io_sb_brg_r_bits_last, - output io_dma_brg_aw_ready, - input io_dma_brg_aw_valid, - input io_dma_brg_aw_bits_id, - input [31:0] io_dma_brg_aw_bits_addr, - input [3:0] io_dma_brg_aw_bits_region, - input [7:0] io_dma_brg_aw_bits_len, - input [2:0] io_dma_brg_aw_bits_size, - input [1:0] io_dma_brg_aw_bits_burst, - input io_dma_brg_aw_bits_lock, - input [3:0] io_dma_brg_aw_bits_cache, - input [2:0] io_dma_brg_aw_bits_prot, - input [3:0] io_dma_brg_aw_bits_qos, - output io_dma_brg_w_ready, - input io_dma_brg_w_valid, - input [63:0] io_dma_brg_w_bits_data, - input [7:0] io_dma_brg_w_bits_strb, - input io_dma_brg_w_bits_last, - input io_dma_brg_b_ready, - output io_dma_brg_b_valid, - output [1:0] io_dma_brg_b_bits_resp, - output io_dma_brg_b_bits_id, - output io_dma_brg_ar_ready, - input io_dma_brg_ar_valid, - input io_dma_brg_ar_bits_id, - input [31:0] io_dma_brg_ar_bits_addr, - input [3:0] io_dma_brg_ar_bits_region, - input [7:0] io_dma_brg_ar_bits_len, - input [2:0] io_dma_brg_ar_bits_size, - input [1:0] io_dma_brg_ar_bits_burst, - input io_dma_brg_ar_bits_lock, - input [3:0] io_dma_brg_ar_bits_cache, - input [2:0] io_dma_brg_ar_bits_prot, - input [3:0] io_dma_brg_ar_bits_qos, - input io_dma_brg_r_ready, - output io_dma_brg_r_valid, - output io_dma_brg_r_bits_id, - output [63:0] io_dma_brg_r_bits_data, - output [1:0] io_dma_brg_r_bits_resp, - output io_dma_brg_r_bits_last, + input [63:0] io_lsu_brg_in_hrdata, + input io_lsu_brg_in_hready, + input io_lsu_brg_in_hresp, + output [31:0] io_lsu_brg_out_haddr, + output [2:0] io_lsu_brg_out_hburst, + output io_lsu_brg_out_hmastlock, + output [3:0] io_lsu_brg_out_hprot, + output [2:0] io_lsu_brg_out_hsize, + output [1:0] io_lsu_brg_out_htrans, + output io_lsu_brg_out_hwrite, + output [63:0] io_lsu_brg_out_hwdata, + input [63:0] io_ifu_brg_in_hrdata, + input io_ifu_brg_in_hready, + input io_ifu_brg_in_hresp, + output [31:0] io_ifu_brg_out_haddr, + output [2:0] io_ifu_brg_out_hburst, + output io_ifu_brg_out_hmastlock, + output [3:0] io_ifu_brg_out_hprot, + output [2:0] io_ifu_brg_out_hsize, + output [1:0] io_ifu_brg_out_htrans, + output io_ifu_brg_out_hwrite, + output [63:0] io_ifu_brg_out_hwdata, + input [63:0] io_sb_brg_in_hrdata, + input io_sb_brg_in_hready, + input io_sb_brg_in_hresp, + output [31:0] io_sb_brg_out_haddr, + output [2:0] io_sb_brg_out_hburst, + output io_sb_brg_out_hmastlock, + output [3:0] io_sb_brg_out_hprot, + output [2:0] io_sb_brg_out_hsize, + output [1:0] io_sb_brg_out_htrans, + output io_sb_brg_out_hwrite, + output [63:0] io_sb_brg_out_hwdata, + output [63:0] io_dma_brg_sig_in_hrdata, + output io_dma_brg_sig_in_hready, + output io_dma_brg_sig_in_hresp, + input [31:0] io_dma_brg_sig_out_haddr, + input [2:0] io_dma_brg_sig_out_hburst, + input io_dma_brg_sig_out_hmastlock, + input [3:0] io_dma_brg_sig_out_hprot, + input [2:0] io_dma_brg_sig_out_hsize, + input [1:0] io_dma_brg_sig_out_htrans, + input io_dma_brg_sig_out_hwrite, + input [63:0] io_dma_brg_sig_out_hwdata, + input io_dma_brg_hsel, + input io_dma_brg_hreadyin, input io_lsu_bus_clk_en, input io_ifu_bus_clk_en, input io_dbg_bus_clk_en, @@ -83098,82 +85534,40 @@ module quasar_wrapper( wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 64:27] wire core_clock; // @[quasar_wrapper.scala 65:20] wire core_reset; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] - wire [7:0] core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_w_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] - wire [7:0] core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_b_valid; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_r_valid; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_w_valid; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] - wire [7:0] core_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_b_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_r_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_lsu_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_ahb_in_hready; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_lsu_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_lsu_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_lsu_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_ifu_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_ahb_in_hready; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_ifu_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_ifu_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_ifu_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_ifu_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_sb_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_ahb_in_hready; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_sb_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_sb_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_sb_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_sb_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_dma_ahb_sig_in_hrdata; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_ahb_sig_in_hready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_ahb_sig_in_hresp; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_dma_ahb_sig_out_haddr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_dma_ahb_sig_out_hsize; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_dma_ahb_sig_out_htrans; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_ahb_sig_out_hwrite; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_dma_ahb_sig_out_hwdata; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_ahb_hsel; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_ahb_hreadyin; // @[quasar_wrapper.scala 65:20] wire core_io_dbg_rst_l; // @[quasar_wrapper.scala 65:20] wire [30:0] core_io_rst_vec; // @[quasar_wrapper.scala 65:20] wire core_io_nmi_int; // @[quasar_wrapper.scala 65:20] @@ -83326,82 +85720,40 @@ module quasar_wrapper( quasar core ( // @[quasar_wrapper.scala 65:20] .clock(core_clock), .reset(core_reset), - .io_lsu_axi_aw_ready(core_io_lsu_axi_aw_ready), - .io_lsu_axi_aw_valid(core_io_lsu_axi_aw_valid), - .io_lsu_axi_aw_bits_id(core_io_lsu_axi_aw_bits_id), - .io_lsu_axi_aw_bits_addr(core_io_lsu_axi_aw_bits_addr), - .io_lsu_axi_aw_bits_region(core_io_lsu_axi_aw_bits_region), - .io_lsu_axi_aw_bits_size(core_io_lsu_axi_aw_bits_size), - .io_lsu_axi_aw_bits_cache(core_io_lsu_axi_aw_bits_cache), - .io_lsu_axi_w_ready(core_io_lsu_axi_w_ready), - .io_lsu_axi_w_valid(core_io_lsu_axi_w_valid), - .io_lsu_axi_w_bits_data(core_io_lsu_axi_w_bits_data), - .io_lsu_axi_w_bits_strb(core_io_lsu_axi_w_bits_strb), - .io_lsu_axi_b_valid(core_io_lsu_axi_b_valid), - .io_lsu_axi_b_bits_resp(core_io_lsu_axi_b_bits_resp), - .io_lsu_axi_b_bits_id(core_io_lsu_axi_b_bits_id), - .io_lsu_axi_ar_ready(core_io_lsu_axi_ar_ready), - .io_lsu_axi_ar_valid(core_io_lsu_axi_ar_valid), - .io_lsu_axi_ar_bits_id(core_io_lsu_axi_ar_bits_id), - .io_lsu_axi_ar_bits_addr(core_io_lsu_axi_ar_bits_addr), - .io_lsu_axi_ar_bits_region(core_io_lsu_axi_ar_bits_region), - .io_lsu_axi_ar_bits_size(core_io_lsu_axi_ar_bits_size), - .io_lsu_axi_ar_bits_cache(core_io_lsu_axi_ar_bits_cache), - .io_lsu_axi_r_valid(core_io_lsu_axi_r_valid), - .io_lsu_axi_r_bits_id(core_io_lsu_axi_r_bits_id), - .io_lsu_axi_r_bits_data(core_io_lsu_axi_r_bits_data), - .io_lsu_axi_r_bits_resp(core_io_lsu_axi_r_bits_resp), - .io_ifu_axi_ar_ready(core_io_ifu_axi_ar_ready), - .io_ifu_axi_ar_valid(core_io_ifu_axi_ar_valid), - .io_ifu_axi_ar_bits_id(core_io_ifu_axi_ar_bits_id), - .io_ifu_axi_ar_bits_addr(core_io_ifu_axi_ar_bits_addr), - .io_ifu_axi_ar_bits_region(core_io_ifu_axi_ar_bits_region), - .io_ifu_axi_r_valid(core_io_ifu_axi_r_valid), - .io_ifu_axi_r_bits_id(core_io_ifu_axi_r_bits_id), - .io_ifu_axi_r_bits_data(core_io_ifu_axi_r_bits_data), - .io_ifu_axi_r_bits_resp(core_io_ifu_axi_r_bits_resp), - .io_sb_axi_aw_ready(core_io_sb_axi_aw_ready), - .io_sb_axi_aw_valid(core_io_sb_axi_aw_valid), - .io_sb_axi_aw_bits_addr(core_io_sb_axi_aw_bits_addr), - .io_sb_axi_aw_bits_region(core_io_sb_axi_aw_bits_region), - .io_sb_axi_aw_bits_size(core_io_sb_axi_aw_bits_size), - .io_sb_axi_w_ready(core_io_sb_axi_w_ready), - .io_sb_axi_w_valid(core_io_sb_axi_w_valid), - .io_sb_axi_w_bits_data(core_io_sb_axi_w_bits_data), - .io_sb_axi_w_bits_strb(core_io_sb_axi_w_bits_strb), - .io_sb_axi_b_valid(core_io_sb_axi_b_valid), - .io_sb_axi_b_bits_resp(core_io_sb_axi_b_bits_resp), - .io_sb_axi_ar_ready(core_io_sb_axi_ar_ready), - .io_sb_axi_ar_valid(core_io_sb_axi_ar_valid), - .io_sb_axi_ar_bits_addr(core_io_sb_axi_ar_bits_addr), - .io_sb_axi_ar_bits_region(core_io_sb_axi_ar_bits_region), - .io_sb_axi_ar_bits_size(core_io_sb_axi_ar_bits_size), - .io_sb_axi_r_valid(core_io_sb_axi_r_valid), - .io_sb_axi_r_bits_data(core_io_sb_axi_r_bits_data), - .io_sb_axi_r_bits_resp(core_io_sb_axi_r_bits_resp), - .io_dma_axi_aw_ready(core_io_dma_axi_aw_ready), - .io_dma_axi_aw_valid(core_io_dma_axi_aw_valid), - .io_dma_axi_aw_bits_id(core_io_dma_axi_aw_bits_id), - .io_dma_axi_aw_bits_addr(core_io_dma_axi_aw_bits_addr), - .io_dma_axi_aw_bits_size(core_io_dma_axi_aw_bits_size), - .io_dma_axi_w_ready(core_io_dma_axi_w_ready), - .io_dma_axi_w_valid(core_io_dma_axi_w_valid), - .io_dma_axi_w_bits_data(core_io_dma_axi_w_bits_data), - .io_dma_axi_w_bits_strb(core_io_dma_axi_w_bits_strb), - .io_dma_axi_b_ready(core_io_dma_axi_b_ready), - .io_dma_axi_b_valid(core_io_dma_axi_b_valid), - .io_dma_axi_b_bits_resp(core_io_dma_axi_b_bits_resp), - .io_dma_axi_b_bits_id(core_io_dma_axi_b_bits_id), - .io_dma_axi_ar_ready(core_io_dma_axi_ar_ready), - .io_dma_axi_ar_valid(core_io_dma_axi_ar_valid), - .io_dma_axi_ar_bits_id(core_io_dma_axi_ar_bits_id), - .io_dma_axi_ar_bits_addr(core_io_dma_axi_ar_bits_addr), - .io_dma_axi_ar_bits_size(core_io_dma_axi_ar_bits_size), - .io_dma_axi_r_ready(core_io_dma_axi_r_ready), - .io_dma_axi_r_valid(core_io_dma_axi_r_valid), - .io_dma_axi_r_bits_id(core_io_dma_axi_r_bits_id), - .io_dma_axi_r_bits_data(core_io_dma_axi_r_bits_data), - .io_dma_axi_r_bits_resp(core_io_dma_axi_r_bits_resp), + .io_lsu_ahb_in_hrdata(core_io_lsu_ahb_in_hrdata), + .io_lsu_ahb_in_hready(core_io_lsu_ahb_in_hready), + .io_lsu_ahb_in_hresp(core_io_lsu_ahb_in_hresp), + .io_lsu_ahb_out_haddr(core_io_lsu_ahb_out_haddr), + .io_lsu_ahb_out_hsize(core_io_lsu_ahb_out_hsize), + .io_lsu_ahb_out_htrans(core_io_lsu_ahb_out_htrans), + .io_lsu_ahb_out_hwrite(core_io_lsu_ahb_out_hwrite), + .io_lsu_ahb_out_hwdata(core_io_lsu_ahb_out_hwdata), + .io_ifu_ahb_in_hrdata(core_io_ifu_ahb_in_hrdata), + .io_ifu_ahb_in_hready(core_io_ifu_ahb_in_hready), + .io_ifu_ahb_in_hresp(core_io_ifu_ahb_in_hresp), + .io_ifu_ahb_out_haddr(core_io_ifu_ahb_out_haddr), + .io_ifu_ahb_out_hsize(core_io_ifu_ahb_out_hsize), + .io_ifu_ahb_out_htrans(core_io_ifu_ahb_out_htrans), + .io_ifu_ahb_out_hwrite(core_io_ifu_ahb_out_hwrite), + .io_ifu_ahb_out_hwdata(core_io_ifu_ahb_out_hwdata), + .io_sb_ahb_in_hrdata(core_io_sb_ahb_in_hrdata), + .io_sb_ahb_in_hready(core_io_sb_ahb_in_hready), + .io_sb_ahb_in_hresp(core_io_sb_ahb_in_hresp), + .io_sb_ahb_out_haddr(core_io_sb_ahb_out_haddr), + .io_sb_ahb_out_hsize(core_io_sb_ahb_out_hsize), + .io_sb_ahb_out_htrans(core_io_sb_ahb_out_htrans), + .io_sb_ahb_out_hwrite(core_io_sb_ahb_out_hwrite), + .io_sb_ahb_out_hwdata(core_io_sb_ahb_out_hwdata), + .io_dma_ahb_sig_in_hrdata(core_io_dma_ahb_sig_in_hrdata), + .io_dma_ahb_sig_in_hready(core_io_dma_ahb_sig_in_hready), + .io_dma_ahb_sig_in_hresp(core_io_dma_ahb_sig_in_hresp), + .io_dma_ahb_sig_out_haddr(core_io_dma_ahb_sig_out_haddr), + .io_dma_ahb_sig_out_hsize(core_io_dma_ahb_sig_out_hsize), + .io_dma_ahb_sig_out_htrans(core_io_dma_ahb_sig_out_htrans), + .io_dma_ahb_sig_out_hwrite(core_io_dma_ahb_sig_out_hwrite), + .io_dma_ahb_sig_out_hwdata(core_io_dma_ahb_sig_out_hwdata), + .io_dma_ahb_hsel(core_io_dma_ahb_hsel), + .io_dma_ahb_hreadyin(core_io_dma_ahb_hreadyin), .io_dbg_rst_l(core_io_dbg_rst_l), .io_rst_vec(core_io_rst_vec), .io_nmi_int(core_io_nmi_int), @@ -83487,231 +85839,143 @@ module quasar_wrapper( .io_soft_int(core_io_soft_int), .io_scan_mode(core_io_scan_mode) ); - assign io_lsu_brg_aw_valid = core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_id = core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_addr = core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_region = core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_size = core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_cache = core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_valid = core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_bits_data = core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_bits_strb = core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_valid = core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_id = core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_addr = core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_region = core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_size = core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_cache = core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 104:21] - assign io_ifu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_valid = core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_id = core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_addr = core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_region = core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 105:21] - assign io_sb_brg_aw_valid = core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_addr = core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_region = core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_size = core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_valid = core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_bits_data = core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_bits_strb = core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_valid = core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_addr = core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_region = core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_size = core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 106:21] - assign io_dma_brg_aw_ready = core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_w_ready = core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_b_valid = core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_b_bits_resp = core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_b_bits_id = core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_ar_ready = core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_valid = core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_id = core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_data = core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_resp = core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_last = 1'h1; // @[quasar_wrapper.scala 107:21] - assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 159:23] - assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 160:23] - assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 161:23] - assign io_dec_tlu_perfcnt3 = core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 162:23] - assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 82:15] - assign io_mpc_debug_halt_ack = core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 155:25] - assign io_mpc_debug_run_ack = core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 156:24] - assign io_debug_brkpt_status = core_io_debug_brkpt_status; // @[quasar_wrapper.scala 157:25] - assign io_o_cpu_halt_ack = core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 150:21] - assign io_o_cpu_halt_status = core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 151:24] - assign io_o_debug_mode_status = core_io_o_debug_mode_status; // @[quasar_wrapper.scala 153:26] - assign io_o_cpu_run_ack = core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 152:20] - assign io_rv_trace_pkt_rv_i_valid_ip = core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 147:19] - assign io_rv_trace_pkt_rv_i_insn_ip = core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 147:19] - assign io_rv_trace_pkt_rv_i_address_ip = core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 147:19] - assign io_rv_trace_pkt_rv_i_exception_ip = core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 147:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 147:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 147:19] - assign io_rv_trace_pkt_rv_i_tval_ip = core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 147:19] - assign mem_clk = clock; // @[quasar_wrapper.scala 90:14] - assign mem_rst_l = reset; // @[quasar_wrapper.scala 89:16] - assign mem_dccm_clk_override = core_io_dccm_clk_override; // @[quasar_wrapper.scala 85:28] - assign mem_icm_clk_override = core_io_icm_clk_override; // @[quasar_wrapper.scala 86:27] - assign mem_dec_tlu_core_ecc_disable = core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 87:35] - assign mem_dccm_wren = core_io_dccm_wren; // @[quasar_wrapper.scala 88:15] - assign mem_dccm_rden = core_io_dccm_rden; // @[quasar_wrapper.scala 88:15] - assign mem_dccm_wr_addr_lo = core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 88:15] - assign mem_dccm_wr_addr_hi = core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 88:15] - assign mem_dccm_rd_addr_lo = core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 88:15] - assign mem_dccm_rd_addr_hi = core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 88:15] - assign mem_dccm_wr_data_lo = core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 88:15] - assign mem_dccm_wr_data_hi = core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 88:15] - assign mem_iccm_rw_addr = core_io_iccm_rw_addr; // @[quasar_wrapper.scala 95:16] - assign mem_iccm_buf_correct_ecc = core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 95:16] - assign mem_iccm_correction_state = core_io_iccm_correction_state; // @[quasar_wrapper.scala 95:16] - assign mem_iccm_wren = core_io_iccm_wren; // @[quasar_wrapper.scala 95:16] - assign mem_iccm_rden = core_io_iccm_rden; // @[quasar_wrapper.scala 95:16] - assign mem_iccm_wr_size = core_io_iccm_wr_size; // @[quasar_wrapper.scala 95:16] - assign mem_iccm_wr_data = core_io_iccm_wr_data; // @[quasar_wrapper.scala 95:16] - assign mem_ic_rw_addr = core_io_ic_rw_addr; // @[quasar_wrapper.scala 94:14] - assign mem_ic_tag_valid = core_io_ic_tag_valid; // @[quasar_wrapper.scala 94:14] - assign mem_ic_wr_en = core_io_ic_wr_en; // @[quasar_wrapper.scala 94:14] - assign mem_ic_rd_en = core_io_ic_rd_en; // @[quasar_wrapper.scala 94:14] - assign mem_ic_wr_data_0 = core_io_ic_wr_data_0; // @[quasar_wrapper.scala 94:14] - assign mem_ic_wr_data_1 = core_io_ic_wr_data_1; // @[quasar_wrapper.scala 94:14] - assign mem_ic_debug_wr_data = core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 94:14] - assign mem_ic_debug_addr = core_io_ic_debug_addr; // @[quasar_wrapper.scala 94:14] - assign mem_ic_debug_rd_en = core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 94:14] - assign mem_ic_debug_wr_en = core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 94:14] - assign mem_ic_debug_tag_array = core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 94:14] - assign mem_ic_debug_way = core_io_ic_debug_way; // @[quasar_wrapper.scala 94:14] - assign mem_ic_premux_data = core_io_ic_premux_data; // @[quasar_wrapper.scala 94:14] - assign mem_ic_sel_premux_data = core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 94:14] - assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 91:20] + assign io_lsu_brg_out_haddr = core_io_lsu_ahb_out_haddr; // @[quasar_wrapper.scala 109:21] + assign io_lsu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 109:21] + assign io_lsu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 109:21] + assign io_lsu_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 109:21] + assign io_lsu_brg_out_hsize = core_io_lsu_ahb_out_hsize; // @[quasar_wrapper.scala 109:21] + assign io_lsu_brg_out_htrans = core_io_lsu_ahb_out_htrans; // @[quasar_wrapper.scala 109:21] + assign io_lsu_brg_out_hwrite = core_io_lsu_ahb_out_hwrite; // @[quasar_wrapper.scala 109:21] + assign io_lsu_brg_out_hwdata = core_io_lsu_ahb_out_hwdata; // @[quasar_wrapper.scala 109:21] + assign io_ifu_brg_out_haddr = core_io_ifu_ahb_out_haddr; // @[quasar_wrapper.scala 108:21] + assign io_ifu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 108:21] + assign io_ifu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 108:21] + assign io_ifu_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 108:21] + assign io_ifu_brg_out_hsize = core_io_ifu_ahb_out_hsize; // @[quasar_wrapper.scala 108:21] + assign io_ifu_brg_out_htrans = core_io_ifu_ahb_out_htrans; // @[quasar_wrapper.scala 108:21] + assign io_ifu_brg_out_hwrite = core_io_ifu_ahb_out_hwrite; // @[quasar_wrapper.scala 108:21] + assign io_ifu_brg_out_hwdata = core_io_ifu_ahb_out_hwdata; // @[quasar_wrapper.scala 108:21] + assign io_sb_brg_out_haddr = core_io_sb_ahb_out_haddr; // @[quasar_wrapper.scala 110:20] + assign io_sb_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 110:20] + assign io_sb_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 110:20] + assign io_sb_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 110:20] + assign io_sb_brg_out_hsize = core_io_sb_ahb_out_hsize; // @[quasar_wrapper.scala 110:20] + assign io_sb_brg_out_htrans = core_io_sb_ahb_out_htrans; // @[quasar_wrapper.scala 110:20] + assign io_sb_brg_out_hwrite = core_io_sb_ahb_out_hwrite; // @[quasar_wrapper.scala 110:20] + assign io_sb_brg_out_hwdata = core_io_sb_ahb_out_hwdata; // @[quasar_wrapper.scala 110:20] + assign io_dma_brg_sig_in_hrdata = core_io_dma_ahb_sig_in_hrdata; // @[quasar_wrapper.scala 111:21] + assign io_dma_brg_sig_in_hready = core_io_dma_ahb_sig_in_hready; // @[quasar_wrapper.scala 111:21] + assign io_dma_brg_sig_in_hresp = core_io_dma_ahb_sig_in_hresp; // @[quasar_wrapper.scala 111:21] + assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 157:23] + assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 158:23] + assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 159:23] + assign io_dec_tlu_perfcnt3 = core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 160:23] + assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 80:15] + assign io_mpc_debug_halt_ack = core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 153:25] + assign io_mpc_debug_run_ack = core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 154:24] + assign io_debug_brkpt_status = core_io_debug_brkpt_status; // @[quasar_wrapper.scala 155:25] + assign io_o_cpu_halt_ack = core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 148:21] + assign io_o_cpu_halt_status = core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 149:24] + assign io_o_debug_mode_status = core_io_o_debug_mode_status; // @[quasar_wrapper.scala 151:26] + assign io_o_cpu_run_ack = core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 150:20] + assign io_rv_trace_pkt_rv_i_valid_ip = core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 145:19] + assign io_rv_trace_pkt_rv_i_insn_ip = core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 145:19] + assign io_rv_trace_pkt_rv_i_address_ip = core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 145:19] + assign io_rv_trace_pkt_rv_i_exception_ip = core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 145:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 145:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 145:19] + assign io_rv_trace_pkt_rv_i_tval_ip = core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 145:19] + assign mem_clk = clock; // @[quasar_wrapper.scala 88:14] + assign mem_rst_l = reset; // @[quasar_wrapper.scala 87:16] + assign mem_dccm_clk_override = core_io_dccm_clk_override; // @[quasar_wrapper.scala 83:28] + assign mem_icm_clk_override = core_io_icm_clk_override; // @[quasar_wrapper.scala 84:27] + assign mem_dec_tlu_core_ecc_disable = core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 85:35] + assign mem_dccm_wren = core_io_dccm_wren; // @[quasar_wrapper.scala 86:15] + assign mem_dccm_rden = core_io_dccm_rden; // @[quasar_wrapper.scala 86:15] + assign mem_dccm_wr_addr_lo = core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 86:15] + assign mem_dccm_wr_addr_hi = core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 86:15] + assign mem_dccm_rd_addr_lo = core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 86:15] + assign mem_dccm_rd_addr_hi = core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 86:15] + assign mem_dccm_wr_data_lo = core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 86:15] + assign mem_dccm_wr_data_hi = core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 86:15] + assign mem_iccm_rw_addr = core_io_iccm_rw_addr; // @[quasar_wrapper.scala 93:16] + assign mem_iccm_buf_correct_ecc = core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 93:16] + assign mem_iccm_correction_state = core_io_iccm_correction_state; // @[quasar_wrapper.scala 93:16] + assign mem_iccm_wren = core_io_iccm_wren; // @[quasar_wrapper.scala 93:16] + assign mem_iccm_rden = core_io_iccm_rden; // @[quasar_wrapper.scala 93:16] + assign mem_iccm_wr_size = core_io_iccm_wr_size; // @[quasar_wrapper.scala 93:16] + assign mem_iccm_wr_data = core_io_iccm_wr_data; // @[quasar_wrapper.scala 93:16] + assign mem_ic_rw_addr = core_io_ic_rw_addr; // @[quasar_wrapper.scala 92:14] + assign mem_ic_tag_valid = core_io_ic_tag_valid; // @[quasar_wrapper.scala 92:14] + assign mem_ic_wr_en = core_io_ic_wr_en; // @[quasar_wrapper.scala 92:14] + assign mem_ic_rd_en = core_io_ic_rd_en; // @[quasar_wrapper.scala 92:14] + assign mem_ic_wr_data_0 = core_io_ic_wr_data_0; // @[quasar_wrapper.scala 92:14] + assign mem_ic_wr_data_1 = core_io_ic_wr_data_1; // @[quasar_wrapper.scala 92:14] + assign mem_ic_debug_wr_data = core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 92:14] + assign mem_ic_debug_addr = core_io_ic_debug_addr; // @[quasar_wrapper.scala 92:14] + assign mem_ic_debug_rd_en = core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 92:14] + assign mem_ic_debug_wr_en = core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 92:14] + assign mem_ic_debug_tag_array = core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 92:14] + assign mem_ic_debug_way = core_io_ic_debug_way; // @[quasar_wrapper.scala 92:14] + assign mem_ic_premux_data = core_io_ic_premux_data; // @[quasar_wrapper.scala 92:14] + assign mem_ic_sel_premux_data = core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 92:14] + assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 89:20] assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 67:25] assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 68:22] assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 69:22] assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 70:22] - assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 76:29] + assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 74:29] assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 71:27] assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 72:26] assign dmi_wrapper_rd_data = core_io_dmi_reg_rdata; // @[quasar_wrapper.scala 73:26] assign core_clock = clock; assign core_reset = reset; - assign core_io_lsu_axi_aw_ready = io_lsu_brg_aw_ready; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_w_ready = io_lsu_brg_w_ready; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_b_valid = io_lsu_brg_b_valid; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_b_bits_resp = io_lsu_brg_b_bits_resp; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_b_bits_id = io_lsu_brg_b_bits_id; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_ar_ready = io_lsu_brg_ar_ready; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_r_valid = io_lsu_brg_r_valid; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_r_bits_id = io_lsu_brg_r_bits_id; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_r_bits_data = io_lsu_brg_r_bits_data; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_r_bits_resp = io_lsu_brg_r_bits_resp; // @[quasar_wrapper.scala 104:21] - assign core_io_ifu_axi_ar_ready = io_ifu_brg_ar_ready; // @[quasar_wrapper.scala 105:21] - assign core_io_ifu_axi_r_valid = io_ifu_brg_r_valid; // @[quasar_wrapper.scala 105:21] - assign core_io_ifu_axi_r_bits_id = io_ifu_brg_r_bits_id; // @[quasar_wrapper.scala 105:21] - assign core_io_ifu_axi_r_bits_data = io_ifu_brg_r_bits_data; // @[quasar_wrapper.scala 105:21] - assign core_io_ifu_axi_r_bits_resp = io_ifu_brg_r_bits_resp; // @[quasar_wrapper.scala 105:21] - assign core_io_sb_axi_aw_ready = io_sb_brg_aw_ready; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_w_ready = io_sb_brg_w_ready; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_b_valid = io_sb_brg_b_valid; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_b_bits_resp = io_sb_brg_b_bits_resp; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_ar_ready = io_sb_brg_ar_ready; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_r_valid = io_sb_brg_r_valid; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_r_bits_data = io_sb_brg_r_bits_data; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_r_bits_resp = io_sb_brg_r_bits_resp; // @[quasar_wrapper.scala 106:21] - assign core_io_dma_axi_aw_valid = io_dma_brg_aw_valid; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_aw_bits_id = io_dma_brg_aw_bits_id; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_aw_bits_addr = io_dma_brg_aw_bits_addr; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_aw_bits_size = io_dma_brg_aw_bits_size; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_w_valid = io_dma_brg_w_valid; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_w_bits_data = io_dma_brg_w_bits_data; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_w_bits_strb = io_dma_brg_w_bits_strb; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_b_ready = io_dma_brg_b_ready; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_ar_valid = io_dma_brg_ar_valid; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_ar_bits_id = io_dma_brg_ar_bits_id; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_ar_bits_addr = io_dma_brg_ar_bits_addr; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_ar_bits_size = io_dma_brg_ar_bits_size; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_r_ready = io_dma_brg_r_ready; // @[quasar_wrapper.scala 107:21] - assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 93:21 quasar_wrapper.scala 121:21] - assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 122:19] - assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 123:19] - assign core_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 124:19] - assign core_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 127:26] - assign core_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 128:25] - assign core_io_core_id = io_core_id; // @[quasar_wrapper.scala 129:19] - assign core_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 132:30] - assign core_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 133:29] - assign core_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 134:29] - assign core_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 88:15] - assign core_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 88:15] - assign core_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 94:14] - assign core_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 94:14] - assign core_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 94:14] - assign core_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 94:14] - assign core_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 94:14] - assign core_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 94:14] - assign core_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 95:16] - assign core_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 95:16] - assign core_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 136:26] - assign core_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 137:26] - assign core_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 138:26] - assign core_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 139:26] - assign core_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 79:22] - assign core_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 78:24] - assign core_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 80:25] - assign core_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 77:25] - assign core_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 143:25] - assign core_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 141:21] - assign core_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 142:20] + assign core_io_lsu_ahb_in_hrdata = io_lsu_brg_in_hrdata; // @[quasar_wrapper.scala 109:21] + assign core_io_lsu_ahb_in_hready = io_lsu_brg_in_hready; // @[quasar_wrapper.scala 109:21] + assign core_io_lsu_ahb_in_hresp = io_lsu_brg_in_hresp; // @[quasar_wrapper.scala 109:21] + assign core_io_ifu_ahb_in_hrdata = io_ifu_brg_in_hrdata; // @[quasar_wrapper.scala 108:21] + assign core_io_ifu_ahb_in_hready = io_ifu_brg_in_hready; // @[quasar_wrapper.scala 108:21] + assign core_io_ifu_ahb_in_hresp = io_ifu_brg_in_hresp; // @[quasar_wrapper.scala 108:21] + assign core_io_sb_ahb_in_hrdata = io_sb_brg_in_hrdata; // @[quasar_wrapper.scala 110:20] + assign core_io_sb_ahb_in_hready = io_sb_brg_in_hready; // @[quasar_wrapper.scala 110:20] + assign core_io_sb_ahb_in_hresp = io_sb_brg_in_hresp; // @[quasar_wrapper.scala 110:20] + assign core_io_dma_ahb_sig_out_haddr = io_dma_brg_sig_out_haddr; // @[quasar_wrapper.scala 111:21] + assign core_io_dma_ahb_sig_out_hsize = io_dma_brg_sig_out_hsize; // @[quasar_wrapper.scala 111:21] + assign core_io_dma_ahb_sig_out_htrans = io_dma_brg_sig_out_htrans; // @[quasar_wrapper.scala 111:21] + assign core_io_dma_ahb_sig_out_hwrite = io_dma_brg_sig_out_hwrite; // @[quasar_wrapper.scala 111:21] + assign core_io_dma_ahb_sig_out_hwdata = io_dma_brg_sig_out_hwdata; // @[quasar_wrapper.scala 111:21] + assign core_io_dma_ahb_hsel = io_dma_brg_hsel; // @[quasar_wrapper.scala 111:21] + assign core_io_dma_ahb_hreadyin = io_dma_brg_hreadyin; // @[quasar_wrapper.scala 111:21] + assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 91:21 quasar_wrapper.scala 119:21] + assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 120:19] + assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 121:19] + assign core_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 122:19] + assign core_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 125:26] + assign core_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 126:25] + assign core_io_core_id = io_core_id; // @[quasar_wrapper.scala 127:19] + assign core_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 130:30] + assign core_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 131:29] + assign core_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 132:29] + assign core_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 86:15] + assign core_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 86:15] + assign core_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 92:14] + assign core_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 92:14] + assign core_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 92:14] + assign core_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 92:14] + assign core_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 92:14] + assign core_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 92:14] + assign core_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 93:16] + assign core_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 93:16] + assign core_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 134:26] + assign core_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 135:26] + assign core_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 136:26] + assign core_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 137:26] + assign core_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 77:22] + assign core_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 76:24] + assign core_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 78:25] + assign core_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 75:25] + assign core_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 141:25] + assign core_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 139:21] + assign core_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 140:20] assign core_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 66:21] endmodule diff --git a/src/main/scala/dec/dec.scala b/src/main/scala/dec/dec.scala index b4d0c6b7..6ac2dba8 100644 --- a/src/main/scala/dec/dec.scala +++ b/src/main/scala/dec/dec.scala @@ -245,10 +245,6 @@ class dec extends Module with param with RequireAsyncReset{ tlu.io.dbg_resume_req := io.dbg_resume_req tlu.io.lsu_idle_any := io.lsu_idle_any tlu.io.dec_div_active := decode.io.dec_div_active -// tlu.io.pic_claimid := io.dec_pic.pic_claimid -// tlu.io.pic_pl := io.dec_pic.pic_pl -// tlu.io.mhwakeup := io.dec_pic.mhwakeup -// tlu.io.mexintpend := io.mexintpend tlu.io.timer_int := io.timer_int tlu.io.soft_int := io.soft_int tlu.io.core_id := io.core_id @@ -269,8 +265,6 @@ class dec extends Module with param with RequireAsyncReset{ io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack io.debug_brkpt_status := tlu.io.debug_brkpt_status -// io.dec_pic.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl -// io.dec_pic.dec_tlu_meipt := tlu.io.dec_tlu_meipt io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0 io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1 diff --git a/src/main/scala/dec/dec_tlu_ctl.scala b/src/main/scala/dec/dec_tlu_ctl.scala index fb626d31..445472f6 100644 --- a/src/main/scala/dec/dec_tlu_ctl.scala +++ b/src/main/scala/dec/dec_tlu_ctl.scala @@ -153,106 +153,106 @@ class dec_tlu_ctl_IO extends Bundle with lib { class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val io = IO(new dec_tlu_ctl_IO) - val mtdata1_t = Wire(Vec(4,UInt(10.W))) - val pause_expired_wb =WireInit(UInt(1.W), 0.U) - val take_nmi_r_d1 =WireInit(UInt(1.W),0.U) - val exc_or_int_valid_r_d1 =WireInit(UInt(1.W),0.U) - val interrupt_valid_r_d1 =WireInit(UInt(1.W),0.U) - val tlu_flush_lower_r =WireInit(UInt(1.W),0.U) - val synchronous_flush_r =WireInit(UInt(1.W),0.U) - val interrupt_valid_r =WireInit(UInt(1.W),0.U) - val take_nmi =WireInit(UInt(1.W),0.U) - val take_reset =WireInit(UInt(1.W),0.U) - val take_int_timer1_int =WireInit(UInt(1.W),0.U) - val take_int_timer0_int =WireInit(UInt(1.W),0.U) - val take_timer_int =WireInit(UInt(1.W),0.U) - val take_soft_int =WireInit(UInt(1.W),0.U) - val take_ce_int =WireInit(UInt(1.W),0.U) - val take_ext_int_start =WireInit(UInt(1.W),0.U) - val ext_int_freeze =WireInit(UInt(1.W),0.U) - val ext_int_freeze_d1 =WireInit(UInt(1.W),0.U) - val take_ext_int_start_d1 =WireInit(UInt(1.W),0.U) - val take_ext_int_start_d2 =WireInit(UInt(1.W),0.U) - val take_ext_int_start_d3 =WireInit(UInt(1.W),0.U) - val fast_int_meicpct =WireInit(UInt(1.W),0.U) - val ignore_ext_int_due_to_lsu_stall =WireInit(UInt(1.W),0.U) - val take_ext_int =WireInit(UInt(1.W),0.U) - val internal_dbg_halt_timers =WireInit(UInt(1.W),0.U) - val int_timer1_int_hold =WireInit(UInt(1.W),0.U) - val int_timer0_int_hold =WireInit(UInt(1.W),0.U) - val mhwakeup_ready =WireInit(UInt(1.W),0.U) - val ext_int_ready =WireInit(UInt(1.W),0.U) - val ce_int_ready =WireInit(UInt(1.W),0.U) - val soft_int_ready =WireInit(UInt(1.W),0.U) - val timer_int_ready =WireInit(UInt(1.W),0.U) - val ebreak_to_debug_mode_r_d1 =WireInit(UInt(1.W),0.U) - val ebreak_to_debug_mode_r =WireInit(UInt(1.W),0.U) - val inst_acc_r =WireInit(UInt(1.W),0.U) - val inst_acc_r_raw =WireInit(UInt(1.W),0.U) - val iccm_sbecc_r =WireInit(UInt(1.W),0.U) - val ic_perr_r =WireInit(UInt(1.W),0.U) - val fence_i_r =WireInit(UInt(1.W),0.U) - val ebreak_r =WireInit(UInt(1.W),0.U) - val ecall_r =WireInit(UInt(1.W),0.U) - val illegal_r =WireInit(UInt(1.W),0.U) - val mret_r =WireInit(UInt(1.W),0.U) - val iccm_repair_state_ns =WireInit(UInt(1.W),0.U) - val rfpc_i0_r =WireInit(UInt(1.W),0.U) - val tlu_i0_kill_writeb_r =WireInit(UInt(1.W),0.U) - val lsu_exc_valid_r_d1 =WireInit(UInt(1.W),0.U) - val lsu_i0_exc_r_raw =WireInit(UInt(1.W),0.U) - val mdseac_locked_f =WireInit(UInt(1.W),0.U) - val i_cpu_run_req_d1 =WireInit(UInt(1.W),0.U) - val cpu_run_ack =WireInit(UInt(1.W),0.U) - val cpu_halt_status =WireInit(UInt(1.W),0.U) - val cpu_halt_ack =WireInit(UInt(1.W),0.U) - val pmu_fw_tlu_halted =WireInit(UInt(1.W),0.U) - val internal_pmu_fw_halt_mode =WireInit(UInt(1.W),0.U) - val pmu_fw_halt_req_ns =WireInit(UInt(1.W),0.U) - val pmu_fw_halt_req_f =WireInit(UInt(1.W),0.U) - val pmu_fw_tlu_halted_f =WireInit(UInt(1.W),0.U) - val int_timer0_int_hold_f =WireInit(UInt(1.W),0.U) - val int_timer1_int_hold_f =WireInit(UInt(1.W),0.U) - val trigger_hit_dmode_r =WireInit(UInt(1.W),0.U) - val i0_trigger_hit_r =WireInit(UInt(1.W),0.U) - val pause_expired_r =WireInit(UInt(1.W),0.U) - val dec_tlu_pmu_fw_halted =WireInit(UInt(1.W),0.U) - val dec_tlu_flush_noredir_r_d1 =WireInit(UInt(1.W),0.U) - val halt_taken_f =WireInit(UInt(1.W),0.U) - val lsu_idle_any_f =WireInit(UInt(1.W),0.U) - val ifu_miss_state_idle_f =WireInit(UInt(1.W),0.U) - val dbg_tlu_halted_f =WireInit(UInt(1.W),0.U) - val debug_halt_req_f =WireInit(UInt(1.W),0.U) - val debug_resume_req_f =WireInit(UInt(1.W),0.U) - val trigger_hit_dmode_r_d1 =WireInit(UInt(1.W),0.U) - val dcsr_single_step_done_f =WireInit(UInt(1.W),0.U) - val debug_halt_req_d1 =WireInit(UInt(1.W),0.U) - val request_debug_mode_r_d1 =WireInit(UInt(1.W),0.U) - val request_debug_mode_done_f =WireInit(UInt(1.W),0.U) - val dcsr_single_step_running_f =WireInit(UInt(1.W),0.U) - val dec_tlu_flush_pause_r_d1 =WireInit(UInt(1.W),0.U) - val dbg_halt_req_held =WireInit(UInt(1.W),0.U) - val debug_halt_req_ns =WireInit(UInt(1.W),0.U) - val internal_dbg_halt_mode =WireInit(UInt(1.W),0.U) - val core_empty =WireInit(UInt(1.W),0.U) - val dbg_halt_req_final =WireInit(UInt(1.W),0.U) - val debug_brkpt_status_ns =WireInit(UInt(1.W),0.U) - val mpc_debug_halt_ack_ns =WireInit(UInt(1.W),0.U) - val mpc_debug_run_ack_ns =WireInit(UInt(1.W),0.U) - val mpc_halt_state_ns =WireInit(UInt(1.W),0.U) - val mpc_run_state_ns =WireInit(UInt(1.W),0.U) - val dbg_halt_state_ns =WireInit(UInt(1.W),0.U) - val dbg_run_state_ns =WireInit(UInt(1.W),0.U) - val dbg_halt_state_f =WireInit(UInt(1.W),0.U) - val mpc_halt_state_f =WireInit(UInt(1.W),0.U) - val nmi_int_detected =WireInit(UInt(1.W),0.U) - val nmi_lsu_load_type =WireInit(UInt(1.W),0.U) - val nmi_lsu_store_type =WireInit(UInt(1.W),0.U) - val reset_delayed =WireInit(UInt(1.W),0.U) - val internal_dbg_halt_mode_f =WireInit(UInt(1.W),0.U) - val e5_valid =WireInit(UInt(1.W),0.U) - val ic_perr_r_d1 =WireInit(UInt(1.W),0.U) - val iccm_sbecc_r_d1 =WireInit(UInt(1.W),0.U) + val mtdata1_t = Wire(Vec(4,UInt(10.W))) + val pause_expired_wb = WireInit(UInt(1.W), 0.U) + val take_nmi_r_d1 = WireInit(UInt(1.W),0.U) + val exc_or_int_valid_r_d1 = WireInit(UInt(1.W),0.U) + val interrupt_valid_r_d1 = WireInit(UInt(1.W),0.U) + val tlu_flush_lower_r = WireInit(UInt(1.W),0.U) + val synchronous_flush_r = WireInit(UInt(1.W),0.U) + val interrupt_valid_r = WireInit(UInt(1.W),0.U) + val take_nmi = WireInit(UInt(1.W),0.U) + val take_reset = WireInit(UInt(1.W),0.U) + val take_int_timer1_int = WireInit(UInt(1.W),0.U) + val take_int_timer0_int = WireInit(UInt(1.W),0.U) + val take_timer_int = WireInit(UInt(1.W),0.U) + val take_soft_int = WireInit(UInt(1.W),0.U) + val take_ce_int = WireInit(UInt(1.W),0.U) + val take_ext_int_start = WireInit(UInt(1.W),0.U) + val ext_int_freeze = WireInit(UInt(1.W),0.U) + val ext_int_freeze_d1 = WireInit(UInt(1.W),0.U) + val take_ext_int_start_d1 = WireInit(UInt(1.W),0.U) + val take_ext_int_start_d2 = WireInit(UInt(1.W),0.U) + val take_ext_int_start_d3 = WireInit(UInt(1.W),0.U) + val fast_int_meicpct = WireInit(UInt(1.W),0.U) + val ignore_ext_int_due_to_lsu_stall = WireInit(UInt(1.W),0.U) + val take_ext_int = WireInit(UInt(1.W),0.U) + val internal_dbg_halt_timers = WireInit(UInt(1.W),0.U) + val int_timer1_int_hold = WireInit(UInt(1.W),0.U) + val int_timer0_int_hold = WireInit(UInt(1.W),0.U) + val mhwakeup_ready = WireInit(UInt(1.W),0.U) + val ext_int_ready = WireInit(UInt(1.W),0.U) + val ce_int_ready = WireInit(UInt(1.W),0.U) + val soft_int_ready = WireInit(UInt(1.W),0.U) + val timer_int_ready = WireInit(UInt(1.W),0.U) + val ebreak_to_debug_mode_r_d1 = WireInit(UInt(1.W),0.U) + val ebreak_to_debug_mode_r = WireInit(UInt(1.W),0.U) + val inst_acc_r = WireInit(UInt(1.W),0.U) + val inst_acc_r_raw = WireInit(UInt(1.W),0.U) + val iccm_sbecc_r = WireInit(UInt(1.W),0.U) + val ic_perr_r = WireInit(UInt(1.W),0.U) + val fence_i_r = WireInit(UInt(1.W),0.U) + val ebreak_r = WireInit(UInt(1.W),0.U) + val ecall_r = WireInit(UInt(1.W),0.U) + val illegal_r = WireInit(UInt(1.W),0.U) + val mret_r = WireInit(UInt(1.W),0.U) + val iccm_repair_state_ns = WireInit(UInt(1.W),0.U) + val rfpc_i0_r = WireInit(UInt(1.W),0.U) + val tlu_i0_kill_writeb_r = WireInit(UInt(1.W),0.U) + val lsu_exc_valid_r_d1 = WireInit(UInt(1.W),0.U) + val lsu_i0_exc_r_raw = WireInit(UInt(1.W),0.U) + val mdseac_locked_f = WireInit(UInt(1.W),0.U) + val i_cpu_run_req_d1 = WireInit(UInt(1.W),0.U) + val cpu_run_ack = WireInit(UInt(1.W),0.U) + val cpu_halt_status = WireInit(UInt(1.W),0.U) + val cpu_halt_ack = WireInit(UInt(1.W),0.U) + val pmu_fw_tlu_halted = WireInit(UInt(1.W),0.U) + val internal_pmu_fw_halt_mode = WireInit(UInt(1.W),0.U) + val pmu_fw_halt_req_ns = WireInit(UInt(1.W),0.U) + val pmu_fw_halt_req_f = WireInit(UInt(1.W),0.U) + val pmu_fw_tlu_halted_f = WireInit(UInt(1.W),0.U) + val int_timer0_int_hold_f = WireInit(UInt(1.W),0.U) + val int_timer1_int_hold_f = WireInit(UInt(1.W),0.U) + val trigger_hit_dmode_r = WireInit(UInt(1.W),0.U) + val i0_trigger_hit_r = WireInit(UInt(1.W),0.U) + val pause_expired_r = WireInit(UInt(1.W),0.U) + val dec_tlu_pmu_fw_halted = WireInit(UInt(1.W),0.U) + val dec_tlu_flush_noredir_r_d1= WireInit(UInt(1.W),0.U) + val halt_taken_f = WireInit(UInt(1.W),0.U) + val lsu_idle_any_f = WireInit(UInt(1.W),0.U) + val ifu_miss_state_idle_f = WireInit(UInt(1.W),0.U) + val dbg_tlu_halted_f = WireInit(UInt(1.W),0.U) + val debug_halt_req_f = WireInit(UInt(1.W),0.U) + val debug_resume_req_f = WireInit(UInt(1.W),0.U) + val trigger_hit_dmode_r_d1 = WireInit(UInt(1.W),0.U) + val dcsr_single_step_done_f = WireInit(UInt(1.W),0.U) + val debug_halt_req_d1 = WireInit(UInt(1.W),0.U) + val request_debug_mode_r_d1 = WireInit(UInt(1.W),0.U) + val request_debug_mode_done_f = WireInit(UInt(1.W),0.U) + val dcsr_single_step_running_f = WireInit(UInt(1.W),0.U) + val dec_tlu_flush_pause_r_d1 = WireInit(UInt(1.W),0.U) + val dbg_halt_req_held = WireInit(UInt(1.W),0.U) + val debug_halt_req_ns = WireInit(UInt(1.W),0.U) + val internal_dbg_halt_mode = WireInit(UInt(1.W),0.U) + val core_empty = WireInit(UInt(1.W),0.U) + val dbg_halt_req_final = WireInit(UInt(1.W),0.U) + val debug_brkpt_status_ns = WireInit(UInt(1.W),0.U) + val mpc_debug_halt_ack_ns = WireInit(UInt(1.W),0.U) + val mpc_debug_run_ack_ns = WireInit(UInt(1.W),0.U) + val mpc_halt_state_ns = WireInit(UInt(1.W),0.U) + val mpc_run_state_ns = WireInit(UInt(1.W),0.U) + val dbg_halt_state_ns = WireInit(UInt(1.W),0.U) + val dbg_run_state_ns = WireInit(UInt(1.W),0.U) + val dbg_halt_state_f = WireInit(UInt(1.W),0.U) + val mpc_halt_state_f = WireInit(UInt(1.W),0.U) + val nmi_int_detected = WireInit(UInt(1.W),0.U) + val nmi_lsu_load_type = WireInit(UInt(1.W),0.U) + val nmi_lsu_store_type = WireInit(UInt(1.W),0.U) + val reset_delayed = WireInit(UInt(1.W),0.U) + val internal_dbg_halt_mode_f = WireInit(UInt(1.W),0.U) + val e5_valid = WireInit(UInt(1.W),0.U) + val ic_perr_r_d1 = WireInit(UInt(1.W),0.U) + val iccm_sbecc_r_d1 = WireInit(UInt(1.W),0.U) val npc_r = WireInit(UInt(31.W),0.U) val npc_r_d1 = WireInit(UInt(31.W),0.U) @@ -272,73 +272,73 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val dec_tlu_mpc_halted_only_ns = WireInit(UInt(1.W),0.U) // tell dbg we are only MPC halted dec_tlu_mpc_halted_only_ns := ~dbg_halt_state_f & mpc_halt_state_f - val int_timers=Module(new dec_timer_ctl) - int_timers.io.free_clk :=io.free_clk - int_timers.io.scan_mode :=io.scan_mode - int_timers.io.dec_csr_wen_r_mod :=dec_csr_wen_r_mod - int_timers.io.dec_csr_rdaddr_d :=io.dec_csr_rdaddr_d - int_timers.io.dec_csr_wraddr_r :=io.dec_csr_wraddr_r - int_timers.io.dec_csr_wrdata_r :=io.dec_csr_wrdata_r - int_timers.io.csr_mitctl0 :=csr_pkt.csr_mitctl0 - int_timers.io.csr_mitctl1 :=csr_pkt.csr_mitctl1 - int_timers.io.csr_mitb0 :=csr_pkt.csr_mitb0 - int_timers.io.csr_mitb1 :=csr_pkt.csr_mitb1 - int_timers.io.csr_mitcnt0 :=csr_pkt.csr_mitcnt0 - int_timers.io.csr_mitcnt1 :=csr_pkt.csr_mitcnt1 - int_timers.io.dec_pause_state :=io.dec_pause_state - int_timers.io.dec_tlu_pmu_fw_halted :=dec_tlu_pmu_fw_halted - int_timers.io.internal_dbg_halt_timers:=internal_dbg_halt_timers + val int_timers = Module(new dec_timer_ctl) + int_timers.io.free_clk := io.free_clk + int_timers.io.scan_mode := io.scan_mode + int_timers.io.dec_csr_wen_r_mod := dec_csr_wen_r_mod + int_timers.io.dec_csr_rdaddr_d := io.dec_csr_rdaddr_d + int_timers.io.dec_csr_wraddr_r := io.dec_csr_wraddr_r + int_timers.io.dec_csr_wrdata_r := io.dec_csr_wrdata_r + int_timers.io.csr_mitctl0 := csr_pkt.csr_mitctl0 + int_timers.io.csr_mitctl1 := csr_pkt.csr_mitctl1 + int_timers.io.csr_mitb0 := csr_pkt.csr_mitb0 + int_timers.io.csr_mitb1 := csr_pkt.csr_mitb1 + int_timers.io.csr_mitcnt0 := csr_pkt.csr_mitcnt0 + int_timers.io.csr_mitcnt1 := csr_pkt.csr_mitcnt1 + int_timers.io.dec_pause_state := io.dec_pause_state + int_timers.io.dec_tlu_pmu_fw_halted := dec_tlu_pmu_fw_halted + int_timers.io.internal_dbg_halt_timers := internal_dbg_halt_timers - val dec_timer_rddata_d =int_timers.io.dec_timer_rddata_d - val dec_timer_read_d =int_timers.io.dec_timer_read_d - val dec_timer_t0_pulse =int_timers.io.dec_timer_t0_pulse - val dec_timer_t1_pulse =int_timers.io.dec_timer_t1_pulse + val dec_timer_rddata_d = int_timers.io.dec_timer_rddata_d + val dec_timer_read_d = int_timers.io.dec_timer_read_d + val dec_timer_t0_pulse = int_timers.io.dec_timer_t0_pulse + val dec_timer_t1_pulse = int_timers.io.dec_timer_t1_pulse val clk_override = io.dec_tlu_dec_clk_override // Async inputs to the core have to be sync'd to the core clock. - val syncro_ff=rvsyncss(Cat(io.nmi_int, io.timer_int, io.soft_int, io.i_cpu_halt_req, io.i_cpu_run_req, io.mpc_debug_halt_req, io.mpc_debug_run_req),io.free_clk) - val nmi_int_sync =syncro_ff(6) - val timer_int_sync =syncro_ff(5) - val soft_int_sync =syncro_ff(4) - val i_cpu_halt_req_sync =syncro_ff(3) - val i_cpu_run_req_sync =syncro_ff(2) - val mpc_debug_halt_req_sync_raw =syncro_ff(1) - val mpc_debug_run_req_sync =syncro_ff(0) + val syncro_ff = rvsyncss(Cat(io.nmi_int, io.timer_int, io.soft_int, io.i_cpu_halt_req, io.i_cpu_run_req, io.mpc_debug_halt_req, io.mpc_debug_run_req),io.free_clk) + val nmi_int_sync = syncro_ff(6) + val timer_int_sync = syncro_ff(5) + val soft_int_sync = syncro_ff(4) + val i_cpu_halt_req_sync = syncro_ff(3) + val i_cpu_run_req_sync = syncro_ff(2) + val mpc_debug_halt_req_sync_raw = syncro_ff(1) + val mpc_debug_run_req_sync = syncro_ff(0) // for CSRs that have inpipe writes only - val csr_wr_clk=rvclkhdr(clock,(dec_csr_wen_r_mod | clk_override).asBool,io.scan_mode) - val lsu_r_wb_clk=rvclkhdr(clock,(io.lsu_error_pkt_r.valid | lsu_exc_valid_r_d1 | clk_override).asBool,io.scan_mode) + val csr_wr_clk = rvclkhdr(clock,(dec_csr_wen_r_mod | clk_override).asBool,io.scan_mode) + val lsu_r_wb_clk = rvclkhdr(clock,(io.lsu_error_pkt_r.valid | lsu_exc_valid_r_d1 | clk_override).asBool,io.scan_mode) - val e4_valid = io.dec_tlu_i0_valid_r - val e4e5_valid = e4_valid | e5_valid - val flush_clkvalid = internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid_r | interrupt_valid_r_d1 | reset_delayed | pause_expired_r | pause_expired_wb | ic_perr_r | ic_perr_r_d1 | iccm_sbecc_r | iccm_sbecc_r_d1 | clk_override + val e4_valid = io.dec_tlu_i0_valid_r + val e4e5_valid = e4_valid | e5_valid + val flush_clkvalid = internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid_r | interrupt_valid_r_d1 | reset_delayed | pause_expired_r | pause_expired_wb | ic_perr_r | ic_perr_r_d1 | iccm_sbecc_r | iccm_sbecc_r_d1 | clk_override - val e4e5_clk=rvclkhdr(clock,(e4e5_valid | clk_override).asBool,io.scan_mode) - val e4e5_int_clk=rvclkhdr(clock,(e4e5_valid | flush_clkvalid).asBool,io.scan_mode) + val e4e5_clk = rvclkhdr(clock,(e4e5_valid | clk_override).asBool,io.scan_mode) + val e4e5_int_clk = rvclkhdr(clock,(e4e5_valid | flush_clkvalid).asBool,io.scan_mode) - val iccm_repair_state_d1 =withClock(io.free_clk){RegNext(iccm_repair_state_ns,0.U)} - ic_perr_r_d1 :=withClock(io.free_clk){RegNext(ic_perr_r,0.U)} - iccm_sbecc_r_d1 :=withClock(io.free_clk){RegNext(iccm_sbecc_r,0.U)} - e5_valid :=withClock(io.free_clk){RegNext(e4_valid,0.U)} - internal_dbg_halt_mode_f :=withClock(io.free_clk){RegNext(internal_dbg_halt_mode,0.U)} - val lsu_pmu_load_external_r =withClock(io.free_clk){RegNext(io.lsu_tlu.lsu_pmu_load_external_m,0.U)} - val lsu_pmu_store_external_r =withClock(io.free_clk){RegNext(io.lsu_tlu.lsu_pmu_store_external_m,0.U)} - val tlu_flush_lower_r_d1 =withClock(io.free_clk){RegNext(tlu_flush_lower_r,0.U)} - io.dec_tlu_i0_kill_writeb_wb :=withClock(io.free_clk){RegNext(tlu_i0_kill_writeb_r,0.U)} - val internal_dbg_halt_mode_f2 =withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)} - io.tlu_mem.dec_tlu_force_halt :=withClock(io.free_clk){RegNext(force_halt,0.U)} + val iccm_repair_state_d1 = withClock(io.free_clk){RegNext(iccm_repair_state_ns,0.U)} + ic_perr_r_d1 := withClock(io.free_clk){RegNext(ic_perr_r,0.U)} + iccm_sbecc_r_d1 := withClock(io.free_clk){RegNext(iccm_sbecc_r,0.U)} + e5_valid := withClock(io.free_clk){RegNext(e4_valid,0.U)} + internal_dbg_halt_mode_f := withClock(io.free_clk){RegNext(internal_dbg_halt_mode,0.U)} + val lsu_pmu_load_external_r = withClock(io.free_clk){RegNext(io.lsu_tlu.lsu_pmu_load_external_m,0.U)} + val lsu_pmu_store_external_r = withClock(io.free_clk){RegNext(io.lsu_tlu.lsu_pmu_store_external_m,0.U)} + val tlu_flush_lower_r_d1 = withClock(io.free_clk){RegNext(tlu_flush_lower_r,0.U)} + io.dec_tlu_i0_kill_writeb_wb := withClock(io.free_clk){RegNext(tlu_i0_kill_writeb_r,0.U)} + val internal_dbg_halt_mode_f2 = withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)} + io.tlu_mem.dec_tlu_force_halt := withClock(io.free_clk){RegNext(force_halt,0.U)} - io.dec_tlu_i0_kill_writeb_r :=tlu_i0_kill_writeb_r - val reset_detect =withClock(io.free_clk){RegNext(1.U(1.W),0.U)} - val reset_detected =withClock(io.free_clk){RegNext(reset_detect,0.U)} - reset_delayed :=reset_detect ^ reset_detected + io.dec_tlu_i0_kill_writeb_r := tlu_i0_kill_writeb_r + val reset_detect = withClock(io.free_clk){RegNext(1.U(1.W),0.U)} + val reset_detected = withClock(io.free_clk){RegNext(reset_detect,0.U)} + reset_delayed := reset_detect ^ reset_detected - val nmi_int_delayed =withClock(io.free_clk){RegNext(nmi_int_sync,0.U)} - val nmi_int_detected_f =withClock(io.free_clk){RegNext(nmi_int_detected,0.U)} - val nmi_lsu_load_type_f =withClock(io.free_clk){RegNext(nmi_lsu_load_type,0.U)} - val nmi_lsu_store_type_f =withClock(io.free_clk){RegNext(nmi_lsu_store_type,0.U)} + val nmi_int_delayed = withClock(io.free_clk){RegNext(nmi_int_sync,0.U)} + val nmi_int_detected_f = withClock(io.free_clk){RegNext(nmi_int_detected,0.U)} + val nmi_lsu_load_type_f = withClock(io.free_clk){RegNext(nmi_lsu_load_type,0.U)} + val nmi_lsu_store_type_f = withClock(io.free_clk){RegNext(nmi_lsu_store_type,0.U)} // Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared @@ -354,17 +354,17 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ // - can interact with debugger halt and v-v // fast ints in progress have priority - val mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & ~ext_int_freeze_d1 - val mpc_debug_halt_req_sync_f =withClock(io.free_clk){RegNext(mpc_debug_halt_req_sync,0.U)} - val mpc_debug_run_req_sync_f =withClock(io.free_clk){RegNext(mpc_debug_run_req_sync,0.U)} - mpc_halt_state_f :=withClock(io.free_clk){RegNext(mpc_halt_state_ns,0.U)} - val mpc_run_state_f =withClock(io.free_clk){RegNext(mpc_run_state_ns,0.U)} - val debug_brkpt_status_f =withClock(io.free_clk){RegNext(debug_brkpt_status_ns,0.U)} - val mpc_debug_halt_ack_f =withClock(io.free_clk){RegNext(mpc_debug_halt_ack_ns,0.U)} - val mpc_debug_run_ack_f =withClock(io.free_clk){RegNext(mpc_debug_run_ack_ns,0.U)} - dbg_halt_state_f :=withClock(io.free_clk){RegNext(dbg_halt_state_ns,0.U)} - val dbg_run_state_f =withClock(io.free_clk){RegNext(dbg_run_state_ns,0.U)} - io.dec_tlu_mpc_halted_only :=withClock(io.free_clk){RegNext(dec_tlu_mpc_halted_only_ns,0.U)} + val mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & ~ext_int_freeze_d1 + val mpc_debug_halt_req_sync_f = withClock(io.free_clk){RegNext(mpc_debug_halt_req_sync,0.U)} + val mpc_debug_run_req_sync_f = withClock(io.free_clk){RegNext(mpc_debug_run_req_sync,0.U)} + mpc_halt_state_f := withClock(io.free_clk){RegNext(mpc_halt_state_ns,0.U)} + val mpc_run_state_f = withClock(io.free_clk){RegNext(mpc_run_state_ns,0.U)} + val debug_brkpt_status_f = withClock(io.free_clk){RegNext(debug_brkpt_status_ns,0.U)} + val mpc_debug_halt_ack_f = withClock(io.free_clk){RegNext(mpc_debug_halt_ack_ns,0.U)} + val mpc_debug_run_ack_f = withClock(io.free_clk){RegNext(mpc_debug_run_ack_ns,0.U)} + dbg_halt_state_f := withClock(io.free_clk){RegNext(dbg_halt_state_ns,0.U)} + val dbg_run_state_f = withClock(io.free_clk){RegNext(dbg_run_state_ns,0.U)} + io.dec_tlu_mpc_halted_only := withClock(io.free_clk){RegNext(dec_tlu_mpc_halted_only_ns,0.U)} // turn level sensitive requests into pulses @@ -444,24 +444,24 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f - dec_tlu_flush_noredir_r_d1 :=withClock(io.free_clk){RegNext(io.tlu_ifc.dec_tlu_flush_noredir_wb,0.U)} - halt_taken_f :=withClock(io.free_clk){RegNext(halt_taken,0.U)} - lsu_idle_any_f :=withClock(io.free_clk){RegNext(io.lsu_idle_any,0.U)} - ifu_miss_state_idle_f :=withClock(io.free_clk){RegNext(io.tlu_mem.ifu_miss_state_idle,0.U)} - dbg_tlu_halted_f :=withClock(io.free_clk){RegNext(dbg_tlu_halted,0.U)} - io.dec_tlu_resume_ack :=withClock(io.free_clk){RegNext(resume_ack_ns,0.U)} - debug_halt_req_f :=withClock(io.free_clk){RegNext(debug_halt_req_ns,0.U)} - debug_resume_req_f :=withClock(io.free_clk){RegNext(debug_resume_req,0.U)} - trigger_hit_dmode_r_d1 :=withClock(io.free_clk){RegNext(trigger_hit_dmode_r,0.U)} - dcsr_single_step_done_f :=withClock(io.free_clk){RegNext(dcsr_single_step_done,0.U)} - debug_halt_req_d1 :=withClock(io.free_clk){RegNext(debug_halt_req,0.U)} - val dec_tlu_wr_pause_r_d1 =withClock(io.free_clk){RegNext(io.dec_tlu_wr_pause_r,0.U)} - val dec_pause_state_f =withClock(io.free_clk){RegNext(io.dec_pause_state,0.U)} - request_debug_mode_r_d1 :=withClock(io.free_clk){RegNext(request_debug_mode_r,0.U)} - request_debug_mode_done_f :=withClock(io.free_clk){RegNext(request_debug_mode_done,0.U)} - dcsr_single_step_running_f :=withClock(io.free_clk){RegNext(dcsr_single_step_running,0.U)} - dec_tlu_flush_pause_r_d1 :=withClock(io.free_clk){RegNext(io.dec_tlu_flush_pause_r,0.U)} - dbg_halt_req_held :=withClock(io.free_clk){RegNext(dbg_halt_req_held_ns,0.U)} + dec_tlu_flush_noredir_r_d1 := withClock(io.free_clk){RegNext(io.tlu_ifc.dec_tlu_flush_noredir_wb,0.U)} + halt_taken_f := withClock(io.free_clk){RegNext(halt_taken,0.U)} + lsu_idle_any_f := withClock(io.free_clk){RegNext(io.lsu_idle_any,0.U)} + ifu_miss_state_idle_f := withClock(io.free_clk){RegNext(io.tlu_mem.ifu_miss_state_idle,0.U)} + dbg_tlu_halted_f := withClock(io.free_clk){RegNext(dbg_tlu_halted,0.U)} + io.dec_tlu_resume_ack := withClock(io.free_clk){RegNext(resume_ack_ns,0.U)} + debug_halt_req_f := withClock(io.free_clk){RegNext(debug_halt_req_ns,0.U)} + debug_resume_req_f := withClock(io.free_clk){RegNext(debug_resume_req,0.U)} + trigger_hit_dmode_r_d1 := withClock(io.free_clk){RegNext(trigger_hit_dmode_r,0.U)} + dcsr_single_step_done_f := withClock(io.free_clk){RegNext(dcsr_single_step_done,0.U)} + debug_halt_req_d1 := withClock(io.free_clk){RegNext(debug_halt_req,0.U)} + val dec_tlu_wr_pause_r_d1 = withClock(io.free_clk){RegNext(io.dec_tlu_wr_pause_r,0.U)} + val dec_pause_state_f = withClock(io.free_clk){RegNext(io.dec_pause_state,0.U)} + request_debug_mode_r_d1 := withClock(io.free_clk){RegNext(request_debug_mode_r,0.U)} + request_debug_mode_done_f := withClock(io.free_clk){RegNext(request_debug_mode_done,0.U)} + dcsr_single_step_running_f := withClock(io.free_clk){RegNext(dcsr_single_step_running,0.U)} + dec_tlu_flush_pause_r_d1 := withClock(io.free_clk){RegNext(io.dec_tlu_flush_pause_r,0.U)} + dbg_halt_req_held := withClock(io.free_clk){RegNext(dbg_halt_req_held_ns,0.U)} io.dec_tlu_debug_stall := debug_halt_req_f @@ -560,23 +560,21 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ // o_cpu_halt_status _______________|---------------------|_________ // i_cpu_run_req ______|----------|____ // o_cpu_run_ack ____________|------|________ - // - // debug mode has priority, ignore PMU/FW halt/run while in debug mode val i_cpu_halt_req_sync_qual = i_cpu_halt_req_sync & ~io.dec_tlu_debug_mode & ~ext_int_freeze_d1 val i_cpu_run_req_sync_qual = i_cpu_run_req_sync & ~io.dec_tlu_debug_mode & pmu_fw_tlu_halted_f & ~ext_int_freeze_d1 - val i_cpu_halt_req_d1 =withClock(io.free_clk){RegNext(i_cpu_halt_req_sync_qual,0.U)} - val i_cpu_run_req_d1_raw =withClock(io.free_clk){RegNext(i_cpu_run_req_sync_qual,0.U)} - io.o_cpu_halt_status :=withClock(io.free_clk){RegNext(cpu_halt_status,0.U)} - io.o_cpu_halt_ack :=withClock(io.free_clk){RegNext(cpu_halt_ack,0.U)} - io.o_cpu_run_ack :=withClock(io.free_clk){RegNext(cpu_run_ack,0.U)} - val internal_pmu_fw_halt_mode_f=withClock(io.free_clk){RegNext(internal_pmu_fw_halt_mode,0.U)} - pmu_fw_halt_req_f :=withClock(io.free_clk){RegNext(pmu_fw_halt_req_ns,0.U)} - pmu_fw_tlu_halted_f :=withClock(io.free_clk){RegNext(pmu_fw_tlu_halted,0.U)} - int_timer0_int_hold_f :=withClock(io.free_clk){RegNext(int_timer0_int_hold,0.U)} - int_timer1_int_hold_f :=withClock(io.free_clk){RegNext(int_timer1_int_hold,0.U)} + val i_cpu_halt_req_d1 = withClock(io.free_clk){RegNext(i_cpu_halt_req_sync_qual,0.U)} + val i_cpu_run_req_d1_raw = withClock(io.free_clk){RegNext(i_cpu_run_req_sync_qual,0.U)} + io.o_cpu_halt_status := withClock(io.free_clk){RegNext(cpu_halt_status,0.U)} + io.o_cpu_halt_ack := withClock(io.free_clk){RegNext(cpu_halt_ack,0.U)} + io.o_cpu_run_ack := withClock(io.free_clk){RegNext(cpu_run_ack,0.U)} + val internal_pmu_fw_halt_mode_f = withClock(io.free_clk){RegNext(internal_pmu_fw_halt_mode,0.U)} + pmu_fw_halt_req_f := withClock(io.free_clk){RegNext(pmu_fw_halt_req_ns,0.U)} + pmu_fw_tlu_halted_f := withClock(io.free_clk){RegNext(pmu_fw_tlu_halted,0.U)} + int_timer0_int_hold_f := withClock(io.free_clk){RegNext(int_timer0_int_hold,0.U)} + int_timer1_int_hold_f := withClock(io.free_clk){RegNext(int_timer1_int_hold,0.U)} // only happens if we aren't in dgb_halt @@ -653,10 +651,10 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle := io.tlu_exu.exu_i0_br_middle_r - ebreak_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r - ecall_r := (io.dec_tlu_packet_r.pmu_i0_itype === ECALL) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r - illegal_r := ~io.dec_tlu_packet_r.legal & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r - mret_r := (io.dec_tlu_packet_r.pmu_i0_itype === MRET) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r + ebreak_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r + ecall_r := (io.dec_tlu_packet_r.pmu_i0_itype === ECALL) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r + illegal_r := ~io.dec_tlu_packet_r.legal & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r + mret_r := (io.dec_tlu_packet_r.pmu_i0_itype === MRET) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r // fence_i includes debug only fence_i's fence_i_r := (io.dec_tlu_packet_r.fence_i & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r) & ~rfpc_i0_r ic_perr_r := io.tlu_mem.ifu_ic_error_start & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f @@ -690,16 +688,16 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ // 0xb : Environment call M-mode val exc_cause_r = Mux1H(Seq( - (take_ext_int & ~take_nmi).asBool -> 0x0b.U(5.W), - (take_timer_int & ~take_nmi).asBool -> 0x07.U(5.W), - (take_soft_int & ~take_nmi).asBool -> 0x03.U(5.W), - (take_int_timer0_int & ~take_nmi).asBool -> 0x1d.U(5.W), - (take_int_timer1_int & ~take_nmi).asBool -> 0x1c.U(5.W), - (take_ce_int & ~take_nmi).asBool -> 0x1e.U(5.W), - (illegal_r & ~take_nmi).asBool -> 0x02.U(5.W), - (ecall_r & ~take_nmi).asBool -> 0x0b.U(5.W), - (inst_acc_r & ~take_nmi).asBool -> 0x01.U(5.W), - ((ebreak_r | i0_trigger_hit_r) & ~take_nmi).asBool -> 0x03.U(5.W), + (take_ext_int & ~take_nmi).asBool -> 0x0b.U(5.W), + (take_timer_int & ~take_nmi).asBool -> 0x07.U(5.W), + (take_soft_int & ~take_nmi).asBool -> 0x03.U(5.W), + (take_int_timer0_int & ~take_nmi).asBool -> 0x1d.U(5.W), + (take_int_timer1_int & ~take_nmi).asBool -> 0x1c.U(5.W), + (take_ce_int & ~take_nmi).asBool -> 0x1e.U(5.W), + (illegal_r & ~take_nmi).asBool -> 0x02.U(5.W), + (ecall_r & ~take_nmi).asBool -> 0x0b.U(5.W), + (inst_acc_r & ~take_nmi).asBool -> 0x01.U(5.W), + ((ebreak_r | i0_trigger_hit_r) & ~take_nmi).asBool -> 0x03.U(5.W), (lsu_exc_ma_r & ~lsu_exc_st_r & ~take_nmi).asBool -> 0x04.U(5.W), (lsu_exc_acc_r & ~lsu_exc_st_r & ~take_nmi).asBool -> 0x05.U(5.W), (lsu_exc_ma_r & lsu_exc_st_r & ~take_nmi).asBool -> 0x06.U(5.W), @@ -714,7 +712,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ // -in priority order, highest to lowest // -single cycle window where a csr write to MIE/MSTATUS is at E4 when the other conditions for externals are met. // Hold off externals for a cycle to make sure we are consistent with what was just written - mhwakeup_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MEIP) & mie_ns(MIE_MEIE) + mhwakeup_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MEIP) & mie_ns(MIE_MEIE) ext_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MEIP) & mie_ns(MIE_MEIE) & ~ignore_ext_int_due_to_lsu_stall ce_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MCEIP) & mie_ns(MIE_MCEIE) soft_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MSIP) & mie_ns(MIE_MSIE) @@ -739,11 +737,11 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ if(FAST_INTERRUPT_REDIRECT) { - take_ext_int_start_d1:=withClock(io.free_clk){RegNext(take_ext_int_start,0.U)} - take_ext_int_start_d2:=withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)} - take_ext_int_start_d3:=withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)} - ext_int_freeze_d1 :=withClock(io.free_clk){RegNext(ext_int_freeze,0.U)} - take_ext_int_start := ext_int_ready & ~block_interrupts; + take_ext_int_start_d1 := withClock(io.free_clk){RegNext(take_ext_int_start,0.U)} + take_ext_int_start_d2 := withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)} + take_ext_int_start_d3 := withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)} + ext_int_freeze_d1 := withClock(io.free_clk){RegNext(ext_int_freeze,0.U)} + take_ext_int_start := ext_int_ready & ~block_interrupts; ext_int_freeze := take_ext_int_start | take_ext_int_start_d1 | take_ext_int_start_d2 | take_ext_int_start_d3 take_ext_int := take_ext_int_start_d3 & ~io.lsu_fir_error.orR @@ -784,34 +782,33 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ tlu_flush_lower_r := interrupt_valid_r | mret_r | synchronous_flush_r | take_halt | take_reset | take_ext_int_start ///After Combining Code revisit this val tlu_flush_path_r = Mux(take_reset.asBool, io.rst_vec,Mux1H(Seq( - (sel_fir_addr).asBool -> io.lsu_fir_addr, + (sel_fir_addr).asBool -> io.lsu_fir_addr, (take_nmi===0.U & sel_npc_r===1.U) -> npc_r, (take_nmi===0.U & rfpc_i0_r===1.U & io.dec_tlu_i0_valid_r===1.U & sel_npc_r===0.U) -> io.dec_tlu_i0_pc_r, (interrupt_valid_r===1.U & sel_fir_addr===0.U) -> interrupt_path, ((i0_exception_valid_r | lsu_exc_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r)) & ~interrupt_valid_r & ~sel_fir_addr).asBool -> Cat(mtvec(30,1),0.U(1.W)), - (~take_nmi & mret_r).asBool -> mepc, + (~take_nmi & mret_r).asBool -> mepc, (~take_nmi & debug_resume_req_f).asBool -> dpc, - (~take_nmi & sel_npc_resume).asBool -> npc_r_d1 + (~take_nmi & sel_npc_resume).asBool -> npc_r_d1 ))) val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this io.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1 -// io.tlu_mem.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb io.tlu_exu.dec_tlu_flush_lower_r := tlu_flush_lower_r io.tlu_exu.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this // this is used to capture mepc, etc. val exc_or_int_valid_r = lsu_exc_valid_r | i0_exception_valid_r | interrupt_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r) - interrupt_valid_r_d1 :=withClock(e4e5_int_clk){RegNext(interrupt_valid_r,0.U)} - val i0_exception_valid_r_d1 =withClock(e4e5_int_clk){RegNext(i0_exception_valid_r,0.U)} - exc_or_int_valid_r_d1 :=withClock(e4e5_int_clk){RegNext(exc_or_int_valid_r,0.U)} - val exc_cause_wb =withClock(e4e5_int_clk){RegNext(exc_cause_r,0.U)} - val i0_valid_wb =withClock(e4e5_int_clk){RegNext((tlu_i0_commit_cmt & ~illegal_r),0.U)} - val trigger_hit_r_d1 =withClock(e4e5_int_clk){RegNext(i0_trigger_hit_r,0.U)} - take_nmi_r_d1 :=withClock(e4e5_int_clk){RegNext(take_nmi,0.U)} - pause_expired_wb :=withClock(e4e5_int_clk){RegNext(pause_expired_r,0.U)} + interrupt_valid_r_d1 := withClock(e4e5_int_clk){RegNext(interrupt_valid_r,0.U)} + val i0_exception_valid_r_d1 = withClock(e4e5_int_clk){RegNext(i0_exception_valid_r,0.U)} + exc_or_int_valid_r_d1 := withClock(e4e5_int_clk){RegNext(exc_or_int_valid_r,0.U)} + val exc_cause_wb = withClock(e4e5_int_clk){RegNext(exc_cause_r,0.U)} + val i0_valid_wb = withClock(e4e5_int_clk){RegNext((tlu_i0_commit_cmt & ~illegal_r),0.U)} + val trigger_hit_r_d1 = withClock(e4e5_int_clk){RegNext(i0_trigger_hit_r,0.U)} + take_nmi_r_d1 := withClock(e4e5_int_clk){RegNext(take_nmi,0.U)} + pause_expired_wb := withClock(e4e5_int_clk){RegNext(pause_expired_r,0.U)} val csr=Module(new csr_tlu) csr.io.free_clk := io.free_clk @@ -824,21 +821,21 @@ val csr=Module(new csr_tlu) csr.io.dec_i0_decode_d := io.dec_i0_decode_d csr.io.ifu_ic_debug_rd_data_valid := io.tlu_mem.ifu_ic_debug_rd_data_valid csr.io.ifu_pmu_bus_trxn := io.tlu_mem.ifu_pmu_bus_trxn - csr.io.dma_iccm_stall_any :=io.tlu_dma.dma_iccm_stall_any - csr.io.dma_dccm_stall_any :=io.tlu_dma.dma_dccm_stall_any - csr.io.lsu_store_stall_any :=io.lsu_store_stall_any - csr.io.dec_pmu_presync_stall :=io.dec_pmu_presync_stall - csr.io.dec_pmu_postsync_stall :=io.dec_pmu_postsync_stall - csr.io.dec_pmu_decode_stall :=io.dec_pmu_decode_stall - csr.io.ifu_pmu_fetch_stall :=io.tlu_ifc.ifu_pmu_fetch_stall - csr.io.dec_tlu_packet_r :=io.dec_tlu_packet_r - csr.io.exu_pmu_i0_br_ataken :=io.tlu_exu.exu_pmu_i0_br_ataken - csr.io.exu_pmu_i0_br_misp :=io.tlu_exu.exu_pmu_i0_br_misp - csr.io.dec_pmu_instr_decoded :=io.dec_pmu_instr_decoded - csr.io.ifu_pmu_instr_aligned :=io.ifu_pmu_instr_aligned - csr.io.exu_pmu_i0_pc4 :=io.tlu_exu.exu_pmu_i0_pc4 - csr.io.ifu_pmu_ic_miss :=io.tlu_mem.ifu_pmu_ic_miss - csr.io.ifu_pmu_ic_hit :=io.tlu_mem.ifu_pmu_ic_hit + csr.io.dma_iccm_stall_any := io.tlu_dma.dma_iccm_stall_any + csr.io.dma_dccm_stall_any := io.tlu_dma.dma_dccm_stall_any + csr.io.lsu_store_stall_any := io.lsu_store_stall_any + csr.io.dec_pmu_presync_stall := io.dec_pmu_presync_stall + csr.io.dec_pmu_postsync_stall := io.dec_pmu_postsync_stall + csr.io.dec_pmu_decode_stall := io.dec_pmu_decode_stall + csr.io.ifu_pmu_fetch_stall := io.tlu_ifc.ifu_pmu_fetch_stall + csr.io.dec_tlu_packet_r := io.dec_tlu_packet_r + csr.io.exu_pmu_i0_br_ataken := io.tlu_exu.exu_pmu_i0_br_ataken + csr.io.exu_pmu_i0_br_misp := io.tlu_exu.exu_pmu_i0_br_misp + csr.io.dec_pmu_instr_decoded := io.dec_pmu_instr_decoded + csr.io.ifu_pmu_instr_aligned := io.ifu_pmu_instr_aligned + csr.io.exu_pmu_i0_pc4 := io.tlu_exu.exu_pmu_i0_pc4 + csr.io.ifu_pmu_ic_miss := io.tlu_mem.ifu_pmu_ic_miss + csr.io.ifu_pmu_ic_hit := io.tlu_mem.ifu_pmu_ic_hit csr.io.dec_csr_wen_r := io.dec_csr_wen_r csr.io.dec_tlu_dbg_halted := io.dec_tlu_dbg_halted csr.io.dma_pmu_dccm_write := io.tlu_dma.dma_pmu_dccm_write @@ -871,13 +868,13 @@ val csr=Module(new csr_tlu) csr.io.core_id := io.core_id csr.io.dec_timer_rddata_d := dec_timer_rddata_d csr.io.dec_timer_read_d := dec_timer_read_d - io.dec_pic.dec_tlu_meicurpl := csr.io.dec_tlu_meicurpl - io.tlu_exu.dec_tlu_meihap := csr.io.dec_tlu_meihap - io.dec_pic.dec_tlu_meipt := csr.io.dec_tlu_meipt + io.dec_pic.dec_tlu_meicurpl := csr.io.dec_tlu_meicurpl + io.tlu_exu.dec_tlu_meihap := csr.io.dec_tlu_meihap + io.dec_pic.dec_tlu_meipt := csr.io.dec_tlu_meipt io.dec_tlu_int_valid_wb1 := csr.io.dec_tlu_int_valid_wb1 io.dec_tlu_i0_exc_valid_wb1 := csr.io.dec_tlu_i0_exc_valid_wb1 io.dec_tlu_i0_valid_wb1 := csr.io.dec_tlu_i0_valid_wb1 - io.tlu_mem.dec_tlu_ic_diag_pkt := csr.io.dec_tlu_ic_diag_pkt + io.tlu_mem.dec_tlu_ic_diag_pkt := csr.io.dec_tlu_ic_diag_pkt io.trigger_pkt_any := csr.io.trigger_pkt_any io.dec_tlu_mtval_wb1 := csr.io.dec_tlu_mtval_wb1 io.dec_tlu_exc_cause_wb1 := csr.io.dec_tlu_exc_cause_wb1 @@ -966,13 +963,13 @@ val csr=Module(new csr_tlu) csr.io.lsu_idle_any_f := lsu_idle_any_f csr.io.dbg_tlu_halted_f := dbg_tlu_halted_f csr.io.dbg_tlu_halted := dbg_tlu_halted - csr.io.debug_halt_req_f := debug_halt_req_f - csr.io.take_ext_int_start := take_ext_int_start - csr.io.trigger_hit_dmode_r_d1 := trigger_hit_dmode_r_d1 - csr.io.trigger_hit_r_d1 := trigger_hit_r_d1 - csr.io.dcsr_single_step_done_f := dcsr_single_step_done_f + csr.io.debug_halt_req_f := debug_halt_req_f + csr.io.take_ext_int_start := take_ext_int_start + csr.io.trigger_hit_dmode_r_d1 := trigger_hit_dmode_r_d1 + csr.io.trigger_hit_r_d1 := trigger_hit_r_d1 + csr.io.dcsr_single_step_done_f := dcsr_single_step_done_f csr.io.ebreak_to_debug_mode_r_d1 := ebreak_to_debug_mode_r_d1 - csr.io.debug_halt_req := debug_halt_req + csr.io.debug_halt_req := debug_halt_req csr.io.allow_dbg_halt_csr_write := allow_dbg_halt_csr_write csr.io.internal_dbg_halt_mode_f := internal_dbg_halt_mode_f csr.io.enter_debug_halt_req := enter_debug_halt_req @@ -1005,7 +1002,7 @@ val csr=Module(new csr_tlu) dcsr := csr.io.dcsr mtvec := csr.io.mtvec mip := csr.io.mip - mtdata1_t :=csr.io.mtdata1_t + mtdata1_t :=csr.io.mtdata1_t val csr_read=Module(new dec_decode_csr_read) csr_read.io.dec_csr_rdaddr_d:=io.dec_csr_rdaddr_d csr_pkt:=csr_read.io.csr_pkt @@ -1021,152 +1018,150 @@ io.dec_csr_legal_d := ( io.dec_csr_any_unq_d &valid_csr & ~(io.dec_csr_wen_unq_d } trait CSRs{ - val MISA = "h301".U(12.W) - val MVENDORID = "hf11".U(12.W) - val MARCHID = "hf12".U(12.W) - val MIMPID = "hf13".U(12.W) - val MHARTID = "hf14".U(12.W) - val MSTATUS = "h300".U(12.W) - val MTVEC = "h305".U(12.W) - val MIP = "h344".U(12.W) - val MIE = "h304".U(12.W) - val MCYCLEL = "hb00".U(12.W) - val MCYCLEH = "hb80".U(12.W) - val MINSTRETL = "hb02".U(12.W) - val MINSTRETH = "hb82".U(12.W) - val MSCRATCH = "h340".U(12.W) - val MEPC = "h341".U(12.W) - val MCAUSE = "h342".U(12.W) - val MSCAUSE = "h7ff".U(12.W) - val MTVAL = "h343".U(12.W) - val MCGC = "h7f8".U(12.W) - val MFDC = "h7f9".U(12.W) - val MCPC = "h7c2".U(12.W) - val MRAC = "h7c0".U(12.W) - val MDEAU = "hbc0".U(12.W) - val MDSEAC = "hfc0".U(12.W) - val MPMC = "h7c6".U(12.W) - val MICECT = "h7f0".U(12.W) - val MICCMECT = "h7f1".U(12.W) - val MDCCMECT = "h7f2".U(12.W) - val MFDHT = "h7ce".U(12.W) - val MFDHS = "h7cf".U(12.W) - val MEIVT = "hbc8".U(12.W) - val MEIHAP = "hfc8".U(12.W) - val MEICURPL = "hbcc".U(12.W) - val MEICIDPL = "hbcb".U(12.W) - val MEICPCT = "hbca".U(12.W) - val MEIPT = "hbc9".U(12.W) - val DCSR = "h7b0".U(12.W) - val DPC = "h7b1".U(12.W) - val DICAWICS = "h7c8".U(12.W) - val DICAD0 = "h7c9".U(12.W) - val DICAD0H = "h7cc".U(12.W) - val DICAD1 = "h7ca".U(12.W) - val DICAGO = "h7cb".U(12.W) - val MTSEL = "h7a0".U(12.W) - val MTDATA1 = "h7a1".U(12.W) - val MTDATA2 = "h7a2".U(12.W) - val MHPMC3 = "hB03".U(12.W) - val MHPMC3H = "hB83".U(12.W) - val MHPMC4 = "hB04".U(12.W) - val MHPMC4H = "hB84".U(12.W) - val MHPMC5 = "hB05".U(12.W) - val MHPMC5H = "hB85".U(12.W) - val MHPMC6 = "hB06".U(12.W) - val MHPMC6H = "hB86".U(12.W) - val MHPME3 = "h323".U(12.W) - val MHPME4 = "h324".U(12.W) - val MHPME5 = "h325".U(12.W) - val MHPME6 = "h326".U(12.W) - val MCOUNTINHIBIT = "h320".U(12.W) - val MSTATUS_MIE = 0.U - val MIP_MCEIP = 5.U - val MIP_MITIP0 = 4.U - val MIP_MITIP1 = 3.U - val MIP_MEIP = 2 - val MIP_MTIP = 1 - val MIP_MSIP = 0 - val MIE_MCEIE = 5 - val MIE_MITIE0 = 4 - val MIE_MITIE1 = 3 - val MIE_MEIE = 2 - val MIE_MTIE = 1 - val MIE_MSIE = 0 - val DCSR_EBREAKM = 15 - val DCSR_STEPIE = 11 - val DCSR_STOPC = 10 - val DCSR_STEP = 2 - val MTDATA1_DMODE = 9 - val MTDATA1_SEL = 7 - val MTDATA1_ACTION = 6 - val MTDATA1_CHAIN = 5 - val MTDATA1_MATCH = 4 - val MTDATA1_M_ENABLED = 3 - val MTDATA1_EXE = 2 - val MTDATA1_ST = 1 - val MTDATA1_LD = 0 - val MHPME_NOEVENT = 0.U - val MHPME_CLK_ACTIVE = 1.U // OOP - out of pipe - val MHPME_ICACHE_HIT = 2.U // OOP - val MHPME_ICACHE_MISS = 3.U // OOP - val MHPME_INST_COMMIT = 4.U - val MHPME_INST_COMMIT_16B = 5.U - val MHPME_INST_COMMIT_32B = 6.U - val MHPME_INST_ALIGNED = 7.U // OOP - val MHPME_INST_DECODED = 8.U // OOP - val MHPME_INST_MUL = 9.U - val MHPME_INST_DIV = 10.U - val MHPME_INST_LOAD = 11.U - val MHPME_INST_STORE = 12.U - val MHPME_INST_MALOAD = 13.U - val MHPME_INST_MASTORE = 14.U - val MHPME_INST_ALU = 15.U - val MHPME_INST_CSRREAD = 16.U - val MHPME_INST_CSRRW = 17.U - val MHPME_INST_CSRWRITE = 18.U - val MHPME_INST_EBREAK = 19.U - val MHPME_INST_ECALL = 20.U - val MHPME_INST_FENCE = 21.U - val MHPME_INST_FENCEI = 22.U - val MHPME_INST_MRET = 23.U - val MHPME_INST_BRANCH = 24.U - val MHPME_BRANCH_MP = 25.U - val MHPME_BRANCH_TAKEN = 26.U - val MHPME_BRANCH_NOTP = 27.U - val MHPME_FETCH_STALL = 28.U // OOP - val MHPME_ALGNR_STALL = 29.U // OOP - val MHPME_DECODE_STALL = 30.U // OOP - val MHPME_POSTSYNC_STALL = 31.U // OOP - val MHPME_PRESYNC_STALL = 32.U // OOP - val MHPME_LSU_SB_WB_STALL = 34.U // OOP - val MHPME_DMA_DCCM_STALL = 35.U // OOP - val MHPME_DMA_ICCM_STALL = 36.U // OOP - val MHPME_EXC_TAKEN = 37.U - val MHPME_TIMER_INT_TAKEN = 38.U - val MHPME_EXT_INT_TAKEN = 39.U - val MHPME_FLUSH_LOWER = 40.U - val MHPME_BR_ERROR = 41.U - val MHPME_IBUS_TRANS = 42.U // OOP - val MHPME_DBUS_TRANS = 43.U // OOP - val MHPME_DBUS_MA_TRANS = 44.U // OOP - val MHPME_IBUS_ERROR = 45.U // OOP - val MHPME_DBUS_ERROR = 46.U // OOP - val MHPME_IBUS_STALL = 47.U // OOP - val MHPME_DBUS_STALL = 48.U // OOP - val MHPME_INT_DISABLED = 49.U // OOP - val MHPME_INT_STALLED = 50.U // OOP - val MHPME_INST_BITMANIP = 54.U - val MHPME_DBUS_LOAD = 55.U - val MHPME_DBUS_STORE = 56.U + val MISA = "h301".U(12.W) + val MVENDORID = "hf11".U(12.W) + val MARCHID = "hf12".U(12.W) + val MIMPID = "hf13".U(12.W) + val MHARTID = "hf14".U(12.W) + val MSTATUS = "h300".U(12.W) + val MTVEC = "h305".U(12.W) + val MIP = "h344".U(12.W) + val MIE = "h304".U(12.W) + val MCYCLEL = "hb00".U(12.W) + val MCYCLEH = "hb80".U(12.W) + val MINSTRETL = "hb02".U(12.W) + val MINSTRETH = "hb82".U(12.W) + val MSCRATCH = "h340".U(12.W) + val MEPC = "h341".U(12.W) + val MCAUSE = "h342".U(12.W) + val MSCAUSE = "h7ff".U(12.W) + val MTVAL = "h343".U(12.W) + val MCGC = "h7f8".U(12.W) + val MFDC = "h7f9".U(12.W) + val MCPC = "h7c2".U(12.W) + val MRAC = "h7c0".U(12.W) + val MDEAU = "hbc0".U(12.W) + val MDSEAC = "hfc0".U(12.W) + val MPMC = "h7c6".U(12.W) + val MICECT = "h7f0".U(12.W) + val MICCMECT = "h7f1".U(12.W) + val MDCCMECT = "h7f2".U(12.W) + val MFDHT = "h7ce".U(12.W) + val MFDHS = "h7cf".U(12.W) + val MEIVT = "hbc8".U(12.W) + val MEIHAP = "hfc8".U(12.W) + val MEICURPL = "hbcc".U(12.W) + val MEICIDPL = "hbcb".U(12.W) + val MEICPCT = "hbca".U(12.W) + val MEIPT = "hbc9".U(12.W) + val DCSR = "h7b0".U(12.W) + val DPC = "h7b1".U(12.W) + val DICAWICS = "h7c8".U(12.W) + val DICAD0 = "h7c9".U(12.W) + val DICAD0H = "h7cc".U(12.W) + val DICAD1 = "h7ca".U(12.W) + val DICAGO = "h7cb".U(12.W) + val MTSEL = "h7a0".U(12.W) + val MTDATA1 = "h7a1".U(12.W) + val MTDATA2 = "h7a2".U(12.W) + val MHPMC3 = "hB03".U(12.W) + val MHPMC3H = "hB83".U(12.W) + val MHPMC4 = "hB04".U(12.W) + val MHPMC4H = "hB84".U(12.W) + val MHPMC5 = "hB05".U(12.W) + val MHPMC5H = "hB85".U(12.W) + val MHPMC6 = "hB06".U(12.W) + val MHPMC6H = "hB86".U(12.W) + val MHPME3 = "h323".U(12.W) + val MHPME4 = "h324".U(12.W) + val MHPME5 = "h325".U(12.W) + val MHPME6 = "h326".U(12.W) + val MCOUNTINHIBIT = "h320".U(12.W) + val MSTATUS_MIE = 0.U + val MIP_MCEIP = 5.U + val MIP_MITIP0 = 4.U + val MIP_MITIP1 = 3.U + val MIP_MEIP = 2 + val MIP_MTIP = 1 + val MIP_MSIP = 0 + val MIE_MCEIE = 5 + val MIE_MITIE0 = 4 + val MIE_MITIE1 = 3 + val MIE_MEIE = 2 + val MIE_MTIE = 1 + val MIE_MSIE = 0 + val DCSR_EBREAKM = 15 + val DCSR_STEPIE = 11 + val DCSR_STOPC = 10 + val DCSR_STEP = 2 + val MTDATA1_DMODE = 9 + val MTDATA1_SEL = 7 + val MTDATA1_ACTION = 6 + val MTDATA1_CHAIN = 5 + val MTDATA1_MATCH = 4 + val MTDATA1_M_ENABLED = 3 + val MTDATA1_EXE = 2 + val MTDATA1_ST = 1 + val MTDATA1_LD = 0 + val MHPME_NOEVENT = 0.U + val MHPME_CLK_ACTIVE = 1.U // OOP - out of pipe + val MHPME_ICACHE_HIT = 2.U // OOP + val MHPME_ICACHE_MISS = 3.U // OOP + val MHPME_INST_COMMIT = 4.U + val MHPME_INST_COMMIT_16B = 5.U + val MHPME_INST_COMMIT_32B = 6.U + val MHPME_INST_ALIGNED = 7.U // OOP + val MHPME_INST_DECODED = 8.U // OOP + val MHPME_INST_MUL = 9.U + val MHPME_INST_DIV = 10.U + val MHPME_INST_LOAD = 11.U + val MHPME_INST_STORE = 12.U + val MHPME_INST_MALOAD = 13.U + val MHPME_INST_MASTORE = 14.U + val MHPME_INST_ALU = 15.U + val MHPME_INST_CSRREAD = 16.U + val MHPME_INST_CSRRW = 17.U + val MHPME_INST_CSRWRITE = 18.U + val MHPME_INST_EBREAK = 19.U + val MHPME_INST_ECALL = 20.U + val MHPME_INST_FENCE = 21.U + val MHPME_INST_FENCEI = 22.U + val MHPME_INST_MRET = 23.U + val MHPME_INST_BRANCH = 24.U + val MHPME_BRANCH_MP = 25.U + val MHPME_BRANCH_TAKEN = 26.U + val MHPME_BRANCH_NOTP = 27.U + val MHPME_FETCH_STALL = 28.U // OOP + val MHPME_ALGNR_STALL = 29.U // OOP + val MHPME_DECODE_STALL = 30.U // OOP + val MHPME_POSTSYNC_STALL = 31.U // OOP + val MHPME_PRESYNC_STALL = 32.U // OOP + val MHPME_LSU_SB_WB_STALL = 34.U // OOP + val MHPME_DMA_DCCM_STALL = 35.U // OOP + val MHPME_DMA_ICCM_STALL = 36.U // OOP + val MHPME_EXC_TAKEN = 37.U + val MHPME_TIMER_INT_TAKEN = 38.U + val MHPME_EXT_INT_TAKEN = 39.U + val MHPME_FLUSH_LOWER = 40.U + val MHPME_BR_ERROR = 41.U + val MHPME_IBUS_TRANS = 42.U // OOP + val MHPME_DBUS_TRANS = 43.U // OOP + val MHPME_DBUS_MA_TRANS = 44.U // OOP + val MHPME_IBUS_ERROR = 45.U // OOP + val MHPME_DBUS_ERROR = 46.U // OOP + val MHPME_IBUS_STALL = 47.U // OOP + val MHPME_DBUS_STALL = 48.U // OOP + val MHPME_INT_DISABLED = 49.U // OOP + val MHPME_INT_STALLED = 50.U // OOP + val MHPME_INST_BITMANIP = 54.U + val MHPME_DBUS_LOAD = 55.U + val MHPME_DBUS_STORE = 56.U // Counts even during sleep state - val MHPME_SLEEP_CYC = 512.U // OOP - val MHPME_DMA_READ_ALL = 513.U // OOP - val MHPME_DMA_WRITE_ALL = 514.U // OOP - val MHPME_DMA_READ_DCCM = 515.U // OOP - val MHPME_DMA_WRITE_DCCM = 516.U // OOP - - + val MHPME_SLEEP_CYC = 512.U // OOP + val MHPME_DMA_READ_ALL = 513.U // OOP + val MHPME_DMA_WRITE_ALL = 514.U // OOP + val MHPME_DMA_READ_DCCM = 515.U // OOP + val MHPME_DMA_WRITE_DCCM = 516.U // OOP } class CSR_IO extends Bundle with lib { val free_clk = Input(Clock()) @@ -1200,8 +1195,6 @@ class CSR_IO extends Bundle with lib { val dec_tlu_i0_exc_valid_wb1 = Output(UInt(1.W)) val dec_tlu_i0_valid_wb1 = Output(UInt(1.W)) val dec_csr_wen_r = Input(UInt(1.W)) - //val dec_tlu_force_halt = Output(UInt(1.W)) - //val dec_tlu_flush_extint = Output(UInt(1.W)) val dec_tlu_mtval_wb1 = Output(UInt(32.W)) val dec_tlu_exc_cause_wb1 = Output(UInt(5.W)) val dec_tlu_perfcnt0 = Output(UInt(1.W)) @@ -1225,18 +1218,8 @@ class CSR_IO extends Bundle with lib { val dec_tlu_bus_clk_override = Output(UInt(1.W)) val dec_tlu_pic_clk_override = Output(UInt(1.W)) val dec_tlu_dccm_clk_override = Output(UInt(1.W)) - val dec_tlu_icm_clk_override = Output(UInt(1.W)) - //val dec_csr_legal_d = Output(UInt(1.W)) + val dec_tlu_icm_clk_override = Output(UInt(1.W)) val dec_csr_rddata_d = Output(UInt(32.W)) - //val dec_tlu_postsync_d = Output(UInt(1.W)) - //val dec_tlu_presync_d = Output(UInt(1.W)) - //val dec_tlu_flush_pause_r = Output(UInt(1.W)) - //val dec_tlu_flush_lower_r = Output(UInt(1.W)) - //val dec_tlu_i0_kill_writeb_r = Output(UInt(1.W)) - //val dec_tlu_flush_lower_wb = Output(UInt(1.W)) - //val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) - // val dec_tlu_flush_leak_one_wb = Output(UInt(1.W)) - //val dec_tlu_debug_stall = Output(UInt(1.W)) val dec_tlu_pipelining_disable = Output(UInt(1.W)) val dec_tlu_wr_pause_r = Output(UInt(1.W)) val ifu_pmu_bus_busy = Input(UInt(1.W)) @@ -1337,14 +1320,14 @@ class CSR_IO extends Bundle with lib { val lsu_idle_any_f = Input(UInt(1.W)) val dbg_tlu_halted_f = Input(UInt(1.W)) val dbg_tlu_halted = Input(UInt(1.W)) - val debug_halt_req_f = Input(UInt(1.W)) - val force_halt = Output(UInt(1.W)) - val take_ext_int_start = Input(UInt(1.W)) - val trigger_hit_dmode_r_d1 = Input(UInt(1.W)) - val trigger_hit_r_d1 = Input(UInt(1.W)) + val debug_halt_req_f = Input(UInt(1.W)) + val force_halt = Output(UInt(1.W)) + val take_ext_int_start = Input(UInt(1.W)) + val trigger_hit_dmode_r_d1 = Input(UInt(1.W)) + val trigger_hit_r_d1 = Input(UInt(1.W)) val dcsr_single_step_done_f = Input(UInt(1.W)) - val ebreak_to_debug_mode_r_d1 = Input(UInt(1.W)) - val debug_halt_req = Input(UInt(1.W)) + val ebreak_to_debug_mode_r_d1 = Input(UInt(1.W)) + val debug_halt_req = Input(UInt(1.W)) val allow_dbg_halt_csr_write = Input(UInt(1.W)) val internal_dbg_halt_mode_f = Input(UInt(1.W)) val enter_debug_halt_req = Input(UInt(1.W)) @@ -1395,8 +1378,7 @@ val wr_mcycleh_r = WireInit(UInt(1.W), 0.U) val wr_meicpct_r = WireInit(UInt(1.W),0.U) val force_halt_ctr_f = WireInit(UInt(32.W),0.U) val mdccmect_inc = WireInit(UInt(27.W),0.U) - val miccmect_inc = WireInit(UInt(27.W),0.U) - //val fw_halted = WireInit(UInt(1.W),0.U) + val miccmect_inc = WireInit(UInt(27.W),0.U) val micect_inc = WireInit(UInt(27.W),0.U) val mdseac_en = WireInit(UInt(1.W),0.U) val mie = WireInit(UInt(6.W),0.U) diff --git a/src/main/scala/exu/exu.scala b/src/main/scala/exu/exu.scala index 73a47350..d97686e8 100644 --- a/src/main/scala/exu/exu.scala +++ b/src/main/scala/exu/exu.scala @@ -48,10 +48,10 @@ class exu extends Module with lib with RequireAsyncReset{ val i0_pred_correct_upper_d = Wire(UInt(1.W)) val i0_flush_upper_d = Wire(UInt(1.W)) io.exu_bp.exu_mp_pkt.bits.prett :=0.U - io.exu_bp.exu_mp_pkt.bits.br_start_error:=0.U - io.exu_bp.exu_mp_pkt.bits.br_error :=0.U - io.exu_bp.exu_mp_pkt.valid :=0.U - i0_pp_r.bits.toffset := 0.U + io.exu_bp.exu_mp_pkt.bits.br_start_error :=0.U + io.exu_bp.exu_mp_pkt.bits.br_error := 0.U + io.exu_bp.exu_mp_pkt.valid := 0.U + i0_pp_r.bits.toffset := 0.U val x_data_en = io.dec_exu.decode_exu.dec_data_en(1) val r_data_en = io.dec_exu.decode_exu.dec_data_en(0) @@ -138,10 +138,10 @@ class exu extends Module with lib with RequireAsyncReset{ (i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d )) - csr_rs1_in_d := Mux( io.dec_exu.dec_alu.dec_csr_ren_d.asBool, i0_rs1_d, io.dec_exu.decode_exu.exu_csr_rs1_x) + csr_rs1_in_d := Mux(io.dec_exu.dec_alu.dec_csr_ren_d.asBool, i0_rs1_d, io.dec_exu.decode_exu.exu_csr_rs1_x) - val i_alu=Module(new exu_alu_ctl) + val i_alu=Module(new exu_alu_ctl()) i_alu.io.dec_alu <> io.dec_exu.dec_alu i_alu.io.scan_mode :=io.scan_mode i_alu.io.enable :=x_ctl_en @@ -159,21 +159,21 @@ class exu extends Module with lib with RequireAsyncReset{ i0_predict_p_d :=i_alu.io.predict_p_out i0_pred_correct_upper_d :=i_alu.io.pred_correct_out - val i_mul=Module(new exu_mul_ctl) - i_mul.io.scan_mode :=io.scan_mode - i_mul.io.mul_p :=io.dec_exu.decode_exu.mul_p - i_mul.io.rs1_in :=muldiv_rs1_d - i_mul.io.rs2_in :=muldiv_rs2_d - val mul_result_x =i_mul.io.result_x + val i_mul = Module(new exu_mul_ctl()) + i_mul.io.scan_mode := io.scan_mode + i_mul.io.mul_p := io.dec_exu.decode_exu.mul_p + i_mul.io.rs1_in := muldiv_rs1_d + i_mul.io.rs2_in := muldiv_rs2_d + val mul_result_x = i_mul.io.result_x - val i_div=Module(new exu_div_ctl) + val i_div = Module(new exu_div_ctl()) i_div.io.dec_div <> io.dec_exu.dec_div - i_div.io.scan_mode :=io.scan_mode + i_div.io.scan_mode := io.scan_mode - i_div.io.dividend :=muldiv_rs1_d - i_div.io.divisor :=muldiv_rs2_d - io.exu_div_wren :=i_div.io.exu_div_wren - io.exu_div_result :=i_div.io.exu_div_result + i_div.io.dividend := muldiv_rs1_d + i_div.io.divisor := muldiv_rs2_d + io.exu_div_wren := i_div.io.exu_div_wren + io.exu_div_result := i_div.io.exu_div_result io.dec_exu.decode_exu.exu_i0_result_x := Mux(mul_valid_x.asBool, mul_result_x, alu_result_x) i0_predict_newp_d := io.dec_exu.decode_exu.dec_i0_predict_p_d @@ -215,22 +215,22 @@ class exu extends Module with lib with RequireAsyncReset{ val after_flush_eghr = Mux((i0_flush_upper_x===1.U & !(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r===1.U)), ghr_d, ghr_x) - io.exu_bp.exu_mp_pkt.bits.way := final_predict_mp.bits.way - io.exu_bp.exu_mp_pkt.bits.misp := final_predict_mp.bits.misp - io.exu_bp.exu_mp_pkt.bits.pcall := final_predict_mp.bits.pcall - io.exu_bp.exu_mp_pkt.bits.pja := final_predict_mp.bits.pja - io.exu_bp.exu_mp_pkt.bits.pret := final_predict_mp.bits.pret - io.exu_bp.exu_mp_pkt.bits.ataken := final_predict_mp.bits.ataken - io.exu_bp.exu_mp_pkt.bits.boffset := final_predict_mp.bits.boffset - io.exu_bp.exu_mp_pkt.bits.pc4 := final_predict_mp.bits.pc4 - io.exu_bp.exu_mp_pkt.bits.hist := final_predict_mp.bits.hist(1,0) - io.exu_bp.exu_mp_pkt.bits.toffset := final_predict_mp.bits.toffset(11,0) - io.exu_bp.exu_mp_fghr := after_flush_eghr - io.exu_bp.exu_mp_index := final_predpipe_mp(PREDPIPESIZE-BHT_GHR_SIZE-1,BTB_BTAG_SIZE) - io.exu_bp.exu_mp_btag := final_predpipe_mp(BTB_BTAG_SIZE-1,0) - io.exu_bp.exu_mp_eghr := final_predpipe_mp(PREDPIPESIZE-1,BTB_ADDR_HI-BTB_ADDR_LO+BTB_BTAG_SIZE+1) // mp ghr for bht write - io.exu_flush_path_final := Mux(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r.asBool, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, i0_flush_path_d) - io.dec_exu.tlu_exu.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r) + io.exu_bp.exu_mp_pkt.bits.way := final_predict_mp.bits.way + io.exu_bp.exu_mp_pkt.bits.misp := final_predict_mp.bits.misp + io.exu_bp.exu_mp_pkt.bits.pcall := final_predict_mp.bits.pcall + io.exu_bp.exu_mp_pkt.bits.pja := final_predict_mp.bits.pja + io.exu_bp.exu_mp_pkt.bits.pret := final_predict_mp.bits.pret + io.exu_bp.exu_mp_pkt.bits.ataken := final_predict_mp.bits.ataken + io.exu_bp.exu_mp_pkt.bits.boffset := final_predict_mp.bits.boffset + io.exu_bp.exu_mp_pkt.bits.pc4 := final_predict_mp.bits.pc4 + io.exu_bp.exu_mp_pkt.bits.hist := final_predict_mp.bits.hist(1,0) + io.exu_bp.exu_mp_pkt.bits.toffset := final_predict_mp.bits.toffset(11,0) + io.exu_bp.exu_mp_fghr := after_flush_eghr + io.exu_bp.exu_mp_index := final_predpipe_mp(PREDPIPESIZE-BHT_GHR_SIZE-1,BTB_BTAG_SIZE) + io.exu_bp.exu_mp_btag := final_predpipe_mp(BTB_BTAG_SIZE-1,0) + io.exu_bp.exu_mp_eghr := final_predpipe_mp(PREDPIPESIZE-1,BTB_ADDR_HI-BTB_ADDR_LO+BTB_BTAG_SIZE+1) // mp ghr for bht write + io.exu_flush_path_final := Mux(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r.asBool, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, i0_flush_path_d) + io.dec_exu.tlu_exu.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r) } object exu_main extends App { diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala index 5e34bd84..de30db2c 100644 --- a/src/main/scala/include/bundle.scala +++ b/src/main/scala/include/bundle.scala @@ -34,7 +34,6 @@ class tlu_dma extends Bundle{ class dec_bp extends Bundle{ val dec_tlu_br0_r_pkt = Flipped(Valid(new br_tlu_pkt_t)) - // val dec_tlu_flush_lower_wb = Input(Bool()) val dec_tlu_flush_leak_one_wb = Input(Bool()) val dec_tlu_bpred_disable = Input(Bool()) } @@ -71,8 +70,8 @@ class ahb_out extends Bundle{ val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data } class ahb_channel extends Bundle{ - val in = new ahb_in - val out = new ahb_out + val in = new ahb_in() + val out = new ahb_out() } class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{ val aw = Decoupled(new write_addr(BUS_TAG)) @@ -272,13 +271,16 @@ class ifu_dec extends Bundle{ val dec_ifc = new dec_ifc val dec_bp = new dec_bp } + class exu_ifu extends Bundle{ val exu_bp = Flipped(new exu_bp()) } + class ifu_dma extends Bundle{ val dma_ifc = new dma_ifc val dma_mem_ctl = new dma_mem_ctl } + class dma_mem_ctl extends Bundle{ val dma_iccm_req = Input(Bool()) val dma_mem_addr = Input(UInt(32.W)) @@ -287,6 +289,7 @@ class dma_mem_ctl extends Bundle{ val dma_mem_wdata = Input(UInt(64.W)) val dma_mem_tag = Input(UInt(3.W)) } + class dma_ifc extends Bundle{ val dma_iccm_stall_any = Input(Bool()) } @@ -301,14 +304,11 @@ class trace_pkt_t extends Bundle{ val rv_i_tval_ip = Output(UInt(32.W) ) } - - - class dec_dbg extends Bundle{ val dbg_ib = new dbg_ib val dbg_dctl = new dbg_dctl - } + class dbg_ib extends Bundle{ val dbg_cmd_valid = Input(Bool()) // debugger abstract command valid val dbg_cmd_write = Input(Bool()) // command is a write @@ -320,8 +320,6 @@ class dbg_dctl extends Bundle{ val dbg_cmd_wrdata = Input(UInt(32.W)) // command write data, for fence/fence_i } - - class dec_alu extends Bundle { val dec_i0_alu_decode_d = Input(UInt(1.W)) // Valid val dec_csr_ren_d = Input(Bool()) // extra decode @@ -418,7 +416,6 @@ object inst_pkt_t extends Enumeration{ } class load_cam_pkt_t extends Bundle { - //val valid = UInt(1.W) val wb = UInt(1.W) val tag = UInt(3.W) val rd = UInt(5.W) @@ -431,7 +428,6 @@ class rets_pkt_t extends Bundle { } class br_pkt_t extends Bundle { - // val valid = UInt(1.W) val toffset = UInt(12.W) val hist = UInt(2.W) val br_error = UInt(1.W) @@ -444,7 +440,6 @@ class br_pkt_t extends Bundle { class br_tlu_pkt_t extends Bundle { - // val valid = UInt(1.W) val hist = UInt(2.W) val br_error = UInt(1.W) val br_start_error = UInt(1.W) @@ -459,7 +454,6 @@ class predict_pkt_t extends Bundle { val pc4 = UInt(1.W) val hist = UInt(2.W) val toffset = UInt(12.W) - // val valid = UInt(1.W) val br_error = UInt(1.W) val br_start_error = UInt(1.W) val prett = UInt(31.W) @@ -477,7 +471,7 @@ class trap_pkt_t extends Bundle { val icaf_type = UInt(2.W) val fence_i = UInt(1.W) val i0trigger = UInt(4.W) - val pmu_i0_itype =UInt(4.W) //new inst_pkt_t //pmu-instructiontype + val pmu_i0_itype =UInt(4.W) //pmu-instructiontype val pmu_i0_br_unpred = UInt(1.W) //pmu val pmu_divide = UInt(1.W) val pmu_lsu_misaligned = UInt(1.W) @@ -489,7 +483,6 @@ class dest_pkt_t extends Bundle { val i0store = UInt(1.W) val i0div = UInt(1.W) val i0v = UInt(1.W) - // val i0valid = UInt(1.W) val csrwen = UInt(1.W) val csrwonly = UInt(1.W) val csrwaddr = UInt(12.W) @@ -543,11 +536,9 @@ class lsu_pkt_t extends Bundle { val store_data_bypass_d = Bool() val load_ldst_bypass_d = Bool() val store_data_bypass_m = Bool() - // val valid = Bool() } class lsu_error_pkt_t extends Bundle { - // val exc_valid = UInt(1.W) val single_ecc_error = UInt(1.W) val inst_type = UInt(1.W) //0: Load, 1: Store val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault @@ -609,7 +600,6 @@ class dec_pkt_t extends Bundle { } class mul_pkt_t extends Bundle { - // val valid = UInt(1.W) val rs1_sign = UInt(1.W) val rs2_sign = UInt(1.W) val low = UInt(1.W) @@ -631,7 +621,6 @@ class mul_pkt_t extends Bundle { } class div_pkt_t extends Bundle { - // val valid = UInt(1.W) val unsign = UInt(1.W) val rem = UInt(1.W) } @@ -640,7 +629,6 @@ class ccm_ext_in_pkt_t extends Bundle { val TEST1 = UInt(1.W) val RME = UInt(1.W) val RM = UInt(4.W) - val LS = UInt(1.W) val DS = UInt(1.W) val SD = UInt(1.W) diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala index 0917162d..e9af12d3 100644 --- a/src/main/scala/lib/param.scala +++ b/src/main/scala/lib/param.scala @@ -21,8 +21,8 @@ trait param { val BTB_INDEX3_HI = 0x19 val BTB_INDEX3_LO = 0x12 val BTB_SIZE = 0x200 - val BUILD_AHB_LITE = 0x0 - val BUILD_AXI4 = 0x1 + val BUILD_AHB_LITE = 0x1 + val BUILD_AXI4 = 0x0 val BUILD_AXI_NATIVE = 0x1 val BUS_PRTY_DEFAULT = 0x3 val DATA_ACCESS_ADDR0 = 0x00000000 diff --git a/src/main/scala/lsu/lsu_bus_buffer.scala b/src/main/scala/lsu/lsu_bus_buffer.scala index 38741796..99d09070 100644 --- a/src/main/scala/lsu/lsu_bus_buffer.scala +++ b/src/main/scala/lsu/lsu_bus_buffer.scala @@ -10,49 +10,49 @@ import ifu._ @chiselName class lsu_bus_buffer extends Module with RequireAsyncReset with lib { val io = IO(new Bundle { - val scan_mode = Input(Bool()) - val tlu_busbuff = new tlu_busbuff() - val dctl_busbuff = new dctl_busbuff() - val dec_tlu_force_halt = Input(Bool()) - val lsu_c2_r_clk = Input(Clock()) + val scan_mode = Input(Bool()) + val tlu_busbuff = new tlu_busbuff() + val dctl_busbuff = new dctl_busbuff() + val dec_tlu_force_halt = Input(Bool()) + val lsu_c2_r_clk = Input(Clock()) val lsu_bus_ibuf_c1_clk = Input(Clock()) val lsu_bus_obuf_c1_clk = Input(Clock()) - val lsu_bus_buf_c1_clk = Input(Clock()) - val lsu_free_c2_clk = Input(Clock()) - val lsu_busm_clk = Input(Clock()) + val lsu_bus_buf_c1_clk = Input(Clock()) + val lsu_free_c2_clk = Input(Clock()) + val lsu_busm_clk = Input(Clock()) val dec_lsu_valid_raw_d = Input(Bool()) - val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) - val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) - val lsu_addr_m = Input(UInt(32.W)) - val end_addr_m = Input(UInt(32.W)) - val lsu_addr_r = Input(UInt(32.W)) - val end_addr_r = Input(UInt(32.W)) - val store_data_r = Input(UInt(32.W)) - val no_word_merge_r = Input(Bool()) - val no_dword_merge_r = Input(Bool()) - val lsu_busreq_m = Input(Bool()) - val ld_full_hit_m = Input(Bool()) - val flush_m_up = Input(Bool()) - val flush_r = Input(Bool()) - val lsu_commit_r = Input(Bool()) - val is_sideeffects_r = Input(Bool()) - val ldst_dual_d = Input(Bool()) - val ldst_dual_m = Input(Bool()) - val ldst_dual_r = Input(Bool()) - val ldst_byteen_ext_m = Input(UInt(8.W)) - val lsu_axi = new axi_channels(LSU_BUS_TAG) - val lsu_bus_clk_en = Input(Bool()) - val lsu_bus_clk_en_q = Input(Bool()) + val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) + val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) + val lsu_addr_m = Input(UInt(32.W)) + val end_addr_m = Input(UInt(32.W)) + val lsu_addr_r = Input(UInt(32.W)) + val end_addr_r = Input(UInt(32.W)) + val store_data_r = Input(UInt(32.W)) + val no_word_merge_r = Input(Bool()) + val no_dword_merge_r = Input(Bool()) + val lsu_busreq_m = Input(Bool()) + val ld_full_hit_m = Input(Bool()) + val flush_m_up = Input(Bool()) + val flush_r = Input(Bool()) + val lsu_commit_r = Input(Bool()) + val is_sideeffects_r = Input(Bool()) + val ldst_dual_d = Input(Bool()) + val ldst_dual_m = Input(Bool()) + val ldst_dual_r = Input(Bool()) + val ldst_byteen_ext_m = Input(UInt(8.W)) + val lsu_axi = new axi_channels(LSU_BUS_TAG) + val lsu_bus_clk_en = Input(Bool()) + val lsu_bus_clk_en_q = Input(Bool()) - val lsu_busreq_r = Output(Bool()) - val lsu_bus_buffer_pend_any = Output(Bool()) - val lsu_bus_buffer_full_any = Output(Bool()) - val lsu_bus_buffer_empty_any = Output(Bool()) - val lsu_bus_idle_any = Output(Bool()) - val ld_byte_hit_buf_lo = Output((UInt(4.W))) - val ld_byte_hit_buf_hi = Output((UInt(4.W))) - val ld_fwddata_buf_lo = Output((UInt(32.W))) - val ld_fwddata_buf_hi = Output((UInt(32.W))) + val lsu_busreq_r = Output(Bool()) + val lsu_bus_buffer_pend_any = Output(Bool()) + val lsu_bus_buffer_full_any = Output(Bool()) + val lsu_bus_buffer_empty_any = Output(Bool()) + val lsu_bus_idle_any = Output(Bool()) + val ld_byte_hit_buf_lo = Output((UInt(4.W))) + val ld_byte_hit_buf_hi = Output((UInt(4.W))) + val ld_fwddata_buf_lo = Output((UInt(32.W))) + val ld_fwddata_buf_hi = Output((UInt(32.W))) }) def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) diff --git a/src/main/scala/lsu/lsu_ecc.scala b/src/main/scala/lsu/lsu_ecc.scala index cb7e2eee..a9a6cc1e 100644 --- a/src/main/scala/lsu/lsu_ecc.scala +++ b/src/main/scala/lsu/lsu_ecc.scala @@ -71,8 +71,6 @@ class lsu_ecc extends Module with lib with RequireAsyncReset { val dccm_wdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W)) val dccm_rdata_hi_any = WireInit(0.U(DCCM_DATA_WIDTH.W)) val dccm_rdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W)) - // val dccm_wdata_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W)) - //val dccm_wdata_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W)) val dccm_data_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W)) val dccm_data_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W)) val double_ecc_error_hi_m = WireInit(Bool(),init = 0.U) diff --git a/src/main/scala/lsu/lsu_stbuf.scala b/src/main/scala/lsu/lsu_stbuf.scala index 5c8f9503..45a1937c 100644 --- a/src/main/scala/lsu/lsu_stbuf.scala +++ b/src/main/scala/lsu/lsu_stbuf.scala @@ -264,7 +264,4 @@ class lsu_stbuf extends Module with lib with RequireAsyncReset { val stbuf_fwdpipe3_hi = Mux(ld_byte_rhit_hi(2),ld_fwddata_rpipe_hi(23,16),stbuf_fwddata_hi_pre_m(23,16)) val stbuf_fwdpipe4_hi = Mux(ld_byte_rhit_hi(3),ld_fwddata_rpipe_hi(31,24),stbuf_fwddata_hi_pre_m(31,24)) io.stbuf_fwddata_hi_m := Cat(stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi,stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi) - - - } diff --git a/src/main/scala/lsu/lsu_trigger.scala b/src/main/scala/lsu/lsu_trigger.scala index 69cde63c..34d26aa4 100644 --- a/src/main/scala/lsu/lsu_trigger.scala +++ b/src/main/scala/lsu/lsu_trigger.scala @@ -18,5 +18,4 @@ class lsu_trigger extends Module with RequireAsyncReset with lib { io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.bits.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.bits.store)| (io.trigger_pkt_any(i).load & io.lsu_pkt_m.bits.load & !io.trigger_pkt_any(i).select) )& rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_pkt.asBool())).reverse.reduce(Cat(_,_)) - } diff --git a/src/main/scala/quasar_wrapper.scala b/src/main/scala/quasar_wrapper.scala index 33820529..d23325c4 100644 --- a/src/main/scala/quasar_wrapper.scala +++ b/src/main/scala/quasar_wrapper.scala @@ -15,7 +15,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { // AXI Signals val lsu_brg = bridge_gen(LSU_BUS_TAG, false) val ifu_brg = bridge_gen(IFU_BUS_TAG, false) - val sb_brg = bridge_gen(SB_BUS_TAG, false) + val sb_brg = bridge_gen(SB_BUS_TAG , false) val dma_brg = bridge_gen(DMA_BUS_TAG, true) val lsu_bus_clk_en = Input(Bool()) @@ -71,8 +71,6 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { dmi_wrapper.io.core_clk := clock dmi_wrapper.io.jtag_id := io.jtag_id dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata - - dmi_wrapper.io.core_rst_n := io.dbg_rst_l core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr @@ -144,7 +142,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { // Outputs val core_rst_l = core.io.core_rst_l - io.rv_trace_pkt := core.io.rv_trace_pkt + io.rv_trace_pkt <> core.io.rv_trace_pkt // external halt/run interface io.o_cpu_halt_ack := core.io.o_cpu_halt_ack diff --git a/target/scala-2.12/classes/QUASAR_Wrp$.class b/target/scala-2.12/classes/QUASAR_Wrp$.class index 4d6926f6f0533f9814d005ba4531d12bb3e4a290..301d2c4b8a34ac76a0d89efe73a89cb8f79976c3 100644 GIT binary patch delta 99 zcmbO%H(74O4KBvTlW%g_0!ag2@yUAJo={dlw-u0eirWTAvhzUXB`3%6SOEFcd0fG& iBqx94u>`YX7?(`$<@IG`YX7?(}%<@IG<#-Prybn<=P3ZQ5N-);a~P9U@Z diff --git a/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class b/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class index 5c99599132812280567ae2628a6da29099efe1ab..7e440b8b218fee1b70c88bfc58f6306ebf66f521 100644 GIT binary patch delta 19 Zcmcb~dXsg74HM(y$+k=ZK(dd?8vsR}27>?q delta 19 Zcmcb~dXsg74HM(i$+k=ZK(dd?8vsSU28RFu diff --git a/target/scala-2.12/classes/dec/CSR_IO.class b/target/scala-2.12/classes/dec/CSR_IO.class index b5fbe4cbe5ca8cfab831ad3f037eaa5a3c8b2f15..ee18fa7a53d60a1f40c5c5962d4861fa103d73f6 100644 GIT binary patch delta 5818 zcmX}ud0drM8V7J*c+TbC%VoREdvOOeucDwJb8)8y`_nGsE!8n}0OJO?(wwF>a8WZsiEi9 zxaAXS+;(krihMGyK2CXf-lDy;o7MM zr_aN^xbzhLj8hw)@f7NY5g+8a21iJYV$K^>T+slGUuX3WYH@mRnR%BmXbwx zE6dlHM7D#lkGxQ4(l4L?>0F%i`8F z^maM7oK?uW$r_R;=VDp8ta?_zd^tCpm8z>eU*65OL(W9AHnL8zym!jENY)zGA=U%d zn9t>j6|6n1TdbkG^+> zox)nrDra@E#(ynOyu;edy3HDPP|hu3?a+1lpuAiEZ{*B;RwnBb%UL4lX0Vc2Cs{s+ z*xS<%xH7Z7r2|yTi@!GC8x9wUc#&HK1J1EnsD_F0+CT%ehxrn^>n< zmLqa*s;;+>$h#ep&8BbV$VAqAtbMHCb&bffYs0^L_@^sOTmRj|KUQH{9V_gp-1`r! zhSmR=Y*(@>SiO(S_Mfc7EJuZGV;^Z6{s<*iglT>!WV3)(%<`_3?M&8gsZCX~oX*mqWt*a_{G`0vq*Jm$2U<`k6K1hHMj9^{kOU$@agx3V)J!i}+bKYgp%4u3u#P9;=!a{Htu2>AKb& zrX6MV_>EfHTf!=3S(|11ch>$#qPx+#xi{rZAq#HFy;oT~S)Hut7CE<#b(b}@Rkj(d zTdZeq%Ql(yldix!@^0~W%nBqtob(JgYN`cuwb9Vy(_n;(47N#5$d0jrd~I z>BUx(5=lj*YElcyEKuPl)D+TU(t1)JshreE>LP`hQR5AY%{|MkJnnwSfP33$Z!hU8 z={Bj44{De zNO7bzQVFS!)K0Sdqek0MF{I_Bcv2y$l5~?~3_uOBqoPQ$q_w16QYopP)IsX!K#dJV z%_glRrILzB=SeLjn~DmzqM}KQNgGLdq!Xk@lD88TVnaoe=91Qs(n*I%7f26C4m)a0 z5NaA}1u22Fhg3znMKU>1Lwlf}BP}AWBW)*@ks3&yq~M;YaVlyKX%#7rR7|QPwUX?; zP!Ud44CxJ0JSm@4Nopb)d!s^wP*J3Lq_w0BQYq;ose`2UK#lE#noe3tN+cDLs!1&* zb5B%wU(^)RV$yn29;uwvNa`Ym;BQ6u_+F^Fq<2W^q`jmIq}wD%FltzD)HKo(QUYlQ zsfu)+WC}s`?}K`dG@rDNl-UP=vP(jgSS8*)FjV;$MyekBEd7-YidSmDNO$>orN_SF z0gBnFM7c}HE8(l-J*<%6F$5AlA|c6R4s7yR1DZ!JeCkmF$sWJKX2l=e%3w%QUW8O- zEu<;Akggnu4CPnI^z?%)&k>OAIRmzMu7a(eY4Dk6F>Ld!gB;Ix$o1+2+r6HKJg?Uw z-|Iuz;k5&HdR4*aUbkQuSYbDeTn%5qYw#t!4+W47g>V@5Kob-RBNU4vuvfeUUx~M2 zpZFB^i+ylFT!ODf7aTN%z&D0SC^0OALxzu`)UX@M3^h=0xC4j1RXE~37QXeK4c~dM zhNIrw;F$MOIPU#3R2VIA!Z-{njnkmYxB{w;t5e{l@f$d0{1IwQo^aaq7@RRpg|num zaL$wnwWeY?Z>objQ#)KR_l1k*XW)|gZ*bZC5nM6vgzwGO@PoMpe)O@!Ri7u}n$N3H z@AGeH@X3NkpTp4Pa~-Z*%y7dJ4!>HW;Wx`NXtr#Io0bD`%W?%;R$IEE)i)Gw`$oYX z-&pwFcLV(4TL5=`&%r(4dvM>cC$#xZgm%CA@W5|9bogaLr(YR#`87bdzd?BThY7|1 z&%)FHE#c+=sQ~}|Lik@62LEp19S|yv0a3yf5G%|9p9r6T9AODKCVT^a5q^Qb!as1h zSRD{JLj(q{64t;pVGAq~_Q0#cVf7NKb)axsr-~r!64Aq&AbMK&h+fuO(c5}o^s)64 zeQlFOKidKkY+ElvYfc0h%suF7^}93 zaZZ~U?;Is2IA0SJo$rfD&TR3N^RRf@*(9C`GKyz|hKR{QFNw&YSP>PJ5AplTCn=@o F{{ymV45;MWIOlS??03Zt0Za5MXqJj=rQn_dnoaIbGb5Tc&A8=E^TMr~DL3YX z7ZA`Aa48EBw^CUu6;X3?!L1TdQwsqt6=a#;?|FXb{KMz{obS2tynMa9D+FI5c%gT? zCPZ3=QO~;5{88As62utpY!36&blb z^tV5k+fQFRZozkdWlJLb+@b$$+Jf(tR?$HuZhcW#Pw~}O{FGBPZH?AD;A5kUsD;!z zs{0dTpGVE3R#U^b8T)i<2K55fnuohXOw7Z->kuDOPf&TjaXx~YNC_DB1*&zYu}`9|rB+Z)yNrD#bp`bZwV68bQ{&!Z>K^Jn zYOl|XJ%yT2t)X_^ZR|6snbeC^+vmofNL@!gN%j50*yE`ysYj_#sBwkHy(QElYCX00 z9%G+REuhv?BZ`cDCN+y%MYZoW_9W_hY9-ZNZ0rftRn!t{3w6*w$DKAF0adYWoEYV4z_Yp7+^HtLWP*9UnnFs}zggWP=%ifcDitgFR?2mn z(r&5$o|5Bar2?fUr3t6yy)8=jl@iX#HA7d~8To3%zmrRv(ha47XXW~V(ho{~|0mbg zN*9%SelOQ|l)h7nIw#j9N+)zRo|EtP=6QLiOv!#hp3PJGQYrAFT<0k5RWen{^;Mqezor2*IE`X8lhN_~Ei>nf!S zNsQ97g)P$SpbN<~V%R<3{0 zwX#;eTbo*vZpb@%N{^Jr-IQyNQiIaSTXNl`bVq6E&vMz|bllJMQ|bF=QrJA0H^ zy*ztGX_r!~QeuO=w@vAx(%441W-HYzjkqt@bfw$6LLbO?TmL}bsaAUKH+lBH(iNqc z-{rbO>6}vchjLx6E3KlZsC?K%JoVTq{2oP%xzJJ2T=cdABxr0?v{>J46DdvoL?t{I!n65_Q`A8dpzh{qu?jj5S^~|3 zwm_?)gIb&-{7JM}3Y`w!3(bHwKrcXJTAjk$5-k=$CqcJE*FtYVE1;2WPGM?|7PFuu zp_`#ApqHRWppJH@Xoe<32ew70`)N+G7&;2N2f7-14_XTC)gGPR3QcK`_6*hl`G94J z8bC21y{i`OX++Eb#CiiV0k0!20(JmAHVt$Wm57S+0j)#LMx8`uqkO$Vmr?O3Cj+fS zO-3C>ZA3jmokqp^fGixe1T`8}gj$2DN424PGte9}Xg(?jRe-vJsztfrAHoyCK~qpO zQE8|w)EQJ2%HIOAn?PeMn$0uOq`5uo@N7MvokUfleEmUYUr;I3_QHuLEIpq8Lw{6Iyh1*m$|c2w^`&<)glRHOw| z5C|_i-JG`P?e|)D6<1(4TX0e<$!mdgj$VSiz-D`pjuHTD`>D2 zG!nH8wE|U)I)Z9MHKSr(pn*2f>!`)39jHC1o2YxJs4!43J7_j41(l7;M_oqMpqw2* zT^*pws2Qk@s7%yp)J2q~Bgp0ijYcJ+)}Yp*%1|d!Z75$CXhU%gt5EwovfkHd<#)IB<;41<0{Fw6<${MkykI4?iJ5AdCg=Vuazvr zE1zY0Rj@3tU)g3Ym}P4{S&lY=D`)lRUFwO`mL-a%}e_cJWddkV|$3FMj$-eM8#R`4u*&b$PMXY}++s9sI z``J6}0NcV2vT}Ba-DF>KGy977Vu$%ec7*?p9pxXf5`KV{@++*2x3O|lB>UPF&%QCu zW8a!SV8=|m*>TfZcEa?4RrosDN#8-N(su?s<(taR_-r>Te~Uc| zu&~DgF{~vZk+lXaVr>DNSbM-B?iFy2YpDV4+&eIe`vfL%7MQ|$;9719Eabj{=earX z5%&w~$Spy`xPQaZFBiEwl%z; zZ99L~c9K75tKCIicHs%m7x*aWYkaixJwC>{laFOxAo$|gS2_zrHjv}yWi~YH=lnl@Y~}?ls#dj+LJ~JhS7*=+`=-R zVH<;B{KPRGTr(D7W+2Tnl-Y_l@8B`}m|}ipsyRZCr3tp;2(hvWwJHd++L>lOAl!Pv zbn6o{tUpB9!OXPdiL`T>WmhxX?qrVbe?*l1hG_c>bM1e42`7d`V##M7wah2L0v@xF zx5P2bBF0$kM6$$5VX0F{yi?CI=LQK*56hi*tZ;si=$a(C(ImTRtaM9RH_rIV>lsQ6U^rF&tG%)T%7% zR1wEi6~|RGC)8!?)jdwCr<_u+Xi$SRs&6!@5t`KmEjpOf+DofWq)lgXMi*vsR#$RP zH_@)U@awyr*H7rsFS(%K)2Y95QUBtS9;eF_M8Mn;* zqYK&En!~KkjZL=PxNurGE?h{P3vPtpuW!ig8#14KDDYz#QJ6+5mQjLjG=gy*$9Rk| zMv%rglhzBg@ z6-yXnDSwD}B3b67kl+-u+^J`U(?g=uPm=SRWald@g~=)rO^QfkwJ2qcXkx9nL8=%a zO$@V6jIv&gkuE04@QYt;5R+__kSRT6$uP2IB%7p{92v)EnZOpALat0_tIT1W%wxOs zktfT^msRYLb?lT4?2>I1$PNl+fFjw8Pu`t zO?2okF6diy>W5s^&$y)D(4{}ot-lk{lU()$amC~1swasaPd3*)#q@e=?0F2RZwczLO&Z{Y}j$9-c+*l*M?Fg zU7l(x0lc1>o?$j_3l{!YP%%Bl5>|S49nur{$5Jwa>t<5EhP=NQO13VOLOQ-)N+%&2 zjK>2nWey&R-byn(E_y3t#alr>-bX12wxb^PQCg;Rd0(X+*shn~eC=W)c4U&DD6v1P ztFoVxA1eOD!zA7&@f(SYyBz&^iPuW}FoWsi?4&#UJJA+Nd`;q$Ol*GOP zj{esYPmuVa#4OO!uOjhqiMI>B8EChQUGx%JoM`ThU`w!)f|p$Rf$JPyhGx*5|_;B#O*KfZxTP2xImDj|Bb{; zBuawsSw$n=Z3@~;ZD-6B<2#ImDoSGqu)T{A0<8_v6jctuO@MV#JePZFE~8H zDf+h&P7=uyKb5#(UPq^!#J@^>Q{r6t9R1c3&yo0?#F_Iu`VA$XEb&pnFY-G@uU^23 zHcH~%5`U1mOr)bfP~r^|Ka;pnK}Wy4#LFbUC2?pWN5754a|Q1&4HNwRr|#6HCxc?XGqmsl_1=(Lo0t;Am>ZdB6IUncRp3~oe=CKcO1xcS@5+u&dxO zkjaoYCAf;CEhD><~okfHxh5lVCpb-QQFmYR5wWM z`L!c&F7axKKS>;0&(U8h*zSb?NL;7Btz*mQOZ;5oY7HEn*%Chx?BCF-^`9C#sy8Jr z8SBW$OMF@4B5{t+D2dNVoUf6iGgRWgBo1xt=nRnfpv2jm*g7#yoTBd$BD*I1n>tB! zk$9`bnVLB|Z6!{YSZ(g;G?RFh#Q#d%u!W<)MB+CR*KTR+^l#}D{h1KiMUQFaBr!|k z`x2LL?dVLA_=dzK+BiDnB)%kZ;kJ%Wg2bmK&fCt>`A+cSc23cAwNDR@gcS9zMUNY zTH*;3AC#DNcJ!-AJY3@Kf^T+q7UU9LoM`*na!lX#-w4c(lgtKA*dsuGWoc!$JqB`(>+iQ8Y|-z0u4aeP$pyi?+L5|`@h#2p~mIDUktWu-7aqR zAx^YW67QDygT!UNbMyyFyg}k;5*Hfk=y#WRnZ&mw4*lNIZzJ(s!TY~=iXJe`QH_;& zip0kxHikR;H6%`yc#p&%B`!O{i91N*jS@eXxbR3vzlY%IBb}n(mV(0)9M!fG&y)Cq z#DSw6{Wyt#lK8m9W}>5CQ{vGQ@0IvpiOY?)<8~bF6#aK0vO741sGtOQLZC)=i8}G=QO1v_I z$tbm>HJIS2E|&PU#I+_mI`brcDsk0Gj?PSp?@3(lM@MI}#HkV&pX})TAn`@P$`sqi zu!}x&ilcf;;)tId`4EYZNgOiO(dj4g9};Js=IHd0c$dU}(;b~o5^t8+oMG!k&v1(V zn-JNbq0DrWXd>|ni9bkOf0m=aNa9x#e>L0DnJe)ViK`?zIx{4`D{)zF>vZH!(XR`U zUG(TVP7-4!z94bIxsJ{ViBlxbGtbc(Eb&o^gMW5(;w3&HahCaxPItl6=Q~CBUElRMCDRJ)Qj?N&7j|hIT+$nnB6^`nDi33+U@@^9E zkl1IHqtij+-zC;pJ31{TUMukzi5snP^p{EePH^~Ir|7?|byQzSTw|Rh=Mq1XxYBQq z&NPW{OI&)rqcc(Bs}dJWc63Hdd`{v58*H7p4NlQd2$4NX!#6rf43zk=#5sR=boxlV zPvU@0j!svJw@d83+0kh)@kWWYEsjnL!HHX(qJNfx4CXN>l&t(HNt=+gqS90Z zR^I_pGr^;Xn+x7e+(PgNFn7@@U+JAn0e*Zdk{Y-Z;jKmZ2I4k?pMkl#4H|`Zfoc+U zCmKz(jA-vRoP4J4Qi}6`-Q>lK?M6Vk?NI4WG?-`=(eFg}h|-Ai>;V1%>YfH6dz8G@a;Yq7y_HiM;lKvg`uYCTc|V1JP8X14MuALUI4y2b;uy zH>lixP_x|#9l9T(Gl{kkr4YR$^4SB5I)F+UA}Xa1nAaugYNGK(_lf=_iuePh>;-is zs!a3?(J-PbMB9k6{|S0S)Rd_BKF|!Jc%qX;Yl*xMf*umpA)h<(H}&MKuL!H zj}Agq38efiiuyhA0>N8}Hwb=ByisuUVenqTeTnxAUPF9R@B`vYg7Y2$UlH7i_?qB_ z#5V+ACB7v%$5HTY9&;4k^sW%igoxKWg2JX8Rq`?InGpLNqnFR(rS384ygdq?@gPMN z(m#nk1uMtFy5P#hrr=@3mf&r~UV`6%`ESRNV)4Hq%^{@m#G!)M5*HNw5X@Wt1?_x) zLt0o!I}?`?yok7*;A_NH1m`>fjuG6P*gei?5xd9vDX@sVe6iQzO!-7V;M z7VIxH>JjG@Jdrq*Z#au?5++3IIf$YJR|WH@XOZ0ql9m+G9mMXceoI_k$V;AwwmpsZ zJCAB`Po2L(s&o(d*lh|F)?}#4> zd8sSl$ASkCKNYs)#O}t^Qo(J7yc%&k!3o6f zX4*yEQOMsD_vYa@P~q(=DFZ5s^>4Kx8XJ*P_T_Jnu`T zh+4~4%$-6lk;1H(N>R0=E83Rw9VZkYQB==Ykbjq<{hiPrNYbgUqV6=N3h5n^hPk4I z)Cd#OCa)ola20k-BZTx%l6G+w68Z7->G_p>gDM_C6%nZpaJAveH~5f|C0HOc2Jn+_ zl&0zsR~(P)%Yt~df0V2+wOamz8kwJ77Gu6h|G_^x8t$TS)i0b7jUpAwBX| zDUHQp(I+JOtSj?jW(*JeljRcm;-&37rN0{Ms?U{oN`63JsaR$#FY;dLp>}YU7hh<0 z5UE~#kGwi&NIME??GKQ~r+;^$)b#J(_CblpSG3{%N25Df9~ECrK#6_v@rynxKH%_n zC|!ps%#%;mSZ=5e<#D-KK2LMLs~_KRhT$rr#{j9WC z7rN@YYil9bzbL)K7P|6pH79N~f7)Ws*kb*>!NbFYxjx~)?xA>im<#!gFG??r#3+>o z&(6tWfctv_zhf0Wm-u`9L|+v=`z$L%Z@<}ZypY05)9VTGx+JrjozGQRD9N6YEHA&Q zumB|WMq&MwUn%i?c!YbR?bk3Csx0Fho}uLRRF+9yhDMvp@a9qxvRo)H7s`W3v_gnh z2+?H{trVh_B&wvW5^t;cIAoCJSC4PZWgf@OPG7NaJ+zO&n%1a_08onxkG`ec8Pxl$V>CzVDT?RA#L6CtbUdvp5! zr`ePFBApdQ4ruP8{FBZqsT*8PY(?JOVA-(==x4B8cuX}|ucQV@F00AHu-ug~an`tn z|7;?33*TX~HrN29j6u&$yTQD{F&1l}q;SQDMdA_di+*z1V$sSeAv#5(e7sF2RzNu| zM5l%59Er{d(HS9X;Kc&fGp-I|ax>5Hj^4U@lZx=-DQ@;4# zi$Zi!h`#oN=#mg!B2jK$C4d?Hh#zM8OQNAWWQX9r9}06>C|(wEd%IXR^|Gsn7@PQF zov&~~>x$62A|)5%kL0dM$u;nY;#Hw|HA68FBD-(dS-v5iYeMH*hK|AQ#I6a&egP~S zbUK{I@IR876@-y#x9ar_{XmH9G)dL-It@l8nFV`G6U=q)e-`okMWU~s4?w1=B9TdNmO4A#~J)Q+|Z;6mwB5pT1 zE`msHKvpz@S0+}N56Hp_@CR9u`)v`FBO8LoW&};mhM+qlXdeZAN)PfKEGK+dsC3H? zl~Z2n317>O*!M(`Zw{6_$;TbyJ4%jxUubNG2G@PlBNxhv$PXwegg48{vZ@bU-@8Zt z1FFqn{(DYT-6&rc$BP7EggkV$&*&!w_y>|-gdE0y;$>(ra-om8f|18SKUO~}FBXz9 z!RTI(v6|Uazump|kV23Paic?!`cao#bxjB=D&C(pup{Qpg}1Dk-ERx&?M3=qj!?Y4 z4PZrhabK2~&%`S;Uy3$)Nqr_C_X&ea%`8yq6voOj^A$~TL3~PU^p3q@%-hp^g;@@3 zZ4iGH#`5zgq-v+uIh+M}ny;};F8&Tv%DiyqL$8B`@}Y1j&&-;xTqQTMDW5It1=7w`RWe_ehi~WI-ORtP`@QC*q1gBE@o~zfPjp^BJ$6dGUHB zCu_t<5{(N2y(5Ya1`WsuN)1NcKF)`_Z5aY8Q-Jws0S@rmTl`RjUJiP$R0+n9EjyP0+x$riaN3Vii2puJoMM5yb&W=y>RDBf> zQTrI11r>$bsQ@36i$%~ZrSqqe%okE;$_Oop4ss+HijHYn=W_}ooMp_&IzL9?)k59j zeqMQ{53*FD7+(l^ln%oO-7mxn^336&j)jrEA+pbw8|`=n0^U70f|?cq-6A?!ghgO+ zNgjqK^DD}{z(GY>u7r~wgUu9=m*y#@mw8&bW1eB#%(Lo!^PJ~X^Ssv0yrA7QFY2w$ zO9nG98_DJsv$=WI{A^ycE}7RerJAW;hxy?JiN6ou_{mgr= zZ03E}9`k|!ALhf%ea%M!In2iahs`H}G3L|2o#wMFr4r2NS=O6rStHFCS(lnGvxS(i zvb{H7XFq4Y$HiDgD~wXBFI=1JFQm_%7Un1@H+VrD!c`^>Yy-J8rokAd7j4STRWrC2oV zvdUyilCfrQrDm04C19SR%i81G;EzhNEXs0NLj^sTlhqn?0A{nb9A-1dTnHajn)$2C z(-T?FSCwY5>WcLD6(Z4cWmpMyrCZ43pP;tqm0=^5dOSy2R#~afThOBc=Ve(Hxb7~{ zTP)974v#qAlpc-vta1oz%+J!J2@fm}VN>3?Jl>k|ne=GR&(Na<52%1gOWv3st@uoO zwB~2%(S`?9WL0?fve-p-t;h=T=0wXXV%10@x?2(J+xfE0mlwLnET(nf;gwivY(r}D zuzT1TexeyfN>#)-O;oii=~V=cf=ubl*H%Tw@%%A8`tgD>$k?oek`9SMKODeUK>+XM zLwXG4k<}1fv@&83uZDE`672$E!}pMaej`D}>IiyjD-ji`LP|t^s;~h5u{x&dbwm|v zfSwW!BPv`Kw3Dbe(MJ#*ppi9^aU$=52ak*)jhaZQ2hoR`&|OJX{wv5H5DonbvI5mW z+rMIY;4j#J938GoeawfPM{fpWvj$7FmMuu64UoOD=RD>ECiR3`4AY@28;|~hMKWy; zk2}ml{0naJ`c0ZJA)elp1t-;pDFD}0d&DbL8%z4nylQP0g-8F|tQPylXw?@@=~o8wFH@ zx39;Hq`Jr%8fg%AmS9-Mt|Vd0g~ToX``4IAmhhY7(<^L=T)-vL zr*x@@#cc`g$|>^fdMqd6*_P2?^;mwkRIZk#yu;t=2`;s(i1)0Inq0~^v~uLhw6OeH zA2qa;$1HT@N&|fEQurM;OzBPrErqit80e>X$tD1?+&9qCrBRVZ#*#sYhJq$(yf6#=vz!}{i=SbB3t2V_B{Ti()K|E>}b=hmA6A799 znNwS%px2t>yRMO~5ybbjhLz&e40hr*e~$^&Rq}ai*Wf%6Epv@_szLn6W*AO4_^xKG zxq8!;gU6+@oII*I%Y>aph359AVt-rch5d>iI=VT=*)19r1(*BvS-BHrOKtr0PH1NKbX9akn^tUdBHTB2?q+g^vv z1qyEQ4wHw?V`_LreavtEgsA(T(hUEYZ)%CX_EVY?f_Sc0EIS>OIi+pWiusYmDdyBx zER1Ps?sBA2*$Q!29J7=(?rP17(a9RhWW2#-5 zHjc7u)5cl}(kJ+Gki8*lmRH`E9UbdvJfIhVmmdKEvb9blv9$9`2y7teq$5n-tXJ709AK2 z7S^w>Q(L>6>T)|40&_F559%zSJqC`!i?nCGaE4*`zAf$1`~2I73QoNw!dK8urUn&ta-qit1Zq*_o+Ls+AHm|jpUSaF>(VHFg8aZG0n<3eIY zII#+eSP!767J`czYYkk?g=o7G%xiRkv@n)2dj%TO1=WTF&_LB*>`-lmd54!!JJAK> zs~G>%g?*(&@eV!Hi`C;B_-UeCdHD33EXYT$n<)C8>Pj?CLm2jhFszNPEL<(_3gU^q zusvzm6)jkl_vy+?swLrb#)dH5x1XE@PB``>ZdzA(q)Kwvb9;)+?x~k_`SKl9XJy2q z;8!1GcStu>ZW()Z@iXPsQ-`n{!v%h-%`QqM8X|#w+7MJ#72zG++Z}GYDl|4D@vw(x zwjL-|H53)4Dhh~lchYLY8jj7a>ilRAd`@+A0l2s$c-52m!mK@6s9FQds;J`{R8x^k z4Sp(A&CS>L#OzXoyq@J)O+91D&+Mt!M318wM7}(625Q%L2tK+dtsGd|{a7acYcKdr zYe|J~V0S7%?|E{SH4we4fz-Pu!5CK?x=N9cIgB6ejcRIWFB$xGZh@R4yhF%!2`X^?E z^#f5+@l?PNKJ8D;h961LkH1JjiS5$V9K>p<1JO6*2EfO$ZV>FYLGsugL>}E>E-DEj zi|CVRAl4p?1#l4U+%R8LC662oN77()WqTHY9h#ZxgT=%rCY!OuIE3(&zfjr{Xc5m*{vMO<*qRQUB-Wt8Lt!cLg4}_Ow%ZBu46wG%@Gpi6dEFWwMwv zV5(rSP9{4pQk{(X#ojdQlW8XV24BCXKXdU`3Cy2OF@@zjDFI(Ph3xh)oVPNQ=~ILi zNM}}l-mm5HJcW8;B(!Z)$v)INISf02DH#J4L1Yn59fhfN3XOKs#sOV0zb{0#+m4zA zk=naUH^nuCN*BiC6Io>(Pnxv3Du~^VeTb8`5u@T`A{y1+{zT$o&(#e_!xC8}*w&dk z8aj(I)>B`8WHfBrB{UlH(avNn=KruU7y?U$XsHmzkAb!Qs}TJvM7v3}Oo)~Vk=Iy= zmJ88xA!NMDo$>j|tF?oQY(f~}4Z7#rCz-ghGE{wUdr=-bFxJ?ir2Q^#W} zJ0>h%Y)#NpkCApPWau_gc+8lD9&>`mSCF?=Aj4QY!4rQ(>%E=>|CzaT4HOUapZ58U+yya@zUW=YYwNSSC+I$}T!R zwi(aR+;)eK{|WVZM|6-oqKg0c2~B^WxFQ~~d4o9?UduOB9;OJGiVW_H)d>c?57@qz zuzxB{<_9#xhw=|ou@S_P#5A<*10FULF&>a{NDuoy!=`CaekhcmPJ{A8QqIdGrz63K zBE~}z3kSek7D13FT=sQFjYxAl=6lBaELHY)4y3(H@Iv zk43b{8PReoPehF4GZFiV$jHF15^R6R6A|M{Mhs6raTZjcifH=;+Zp{!(VmKEPert+ zQnZn?Sr(>aUq%Jo?0%t$zW#EJKNAT&6A3(%68JWW5_m2WSe^co#G*-P7xuY`^jwP6 zol~SV5ow|O#V+m@PR31|h?yp0rb#i|&Y_quM9f+47dvLk9E$lu#C#!QzK~)znoBWX zikK7KFZP#O@|V683A_{uyrf|e%OI%m}{rXNvh+#C$DczLsJZolh~}h?rg6FLumd=2Of!BIX+r^NkcUYyrjm zN5pLAez9XtTR<`Y5i$P}G5--UVYtG0c~5(zQ0`g`A86-aSfHo=(UpZquf~#vgOcqm z%(sJ7V}>ehqBI!22*+d|%0m{yfbk($RU{tpQVBnvr{RMw6&xJ6&T=2qtKq|UEySYX zM^=&BDekohlZv0cE8^3@svqohd%Ec=LNKWalg04k3m0Jl^5cgVp=j6$FJkp@8Pl0x z+AT(ra?<=#fEhW(1ha85ik6E^C0v-`2+swVR1_r9OHkNc8FrSzM=U`}a*64UN&?38 zW_w6c^j!Sf5>^)b-K4WFfXqWrUOIogN{ar!HlA)!bN^_MgUC zROGM7Jh!ME+hb(p<{f{9sg;`!BXQ$}vc#z^IYIy9u!7$0U*WKd;8~X8!cBg-XkdW_ zWjM5q{Ji}#dD%DPxwDKF!CMzC21Q@OL2!} zm|^c$-~gkftNrY7H6Jg&5*t(Od^4Obez2r9N39W5s5 z3fg1nYApXTVpnJP+8Ao5P=01LtchxH0i$k$d8Re2yi!e!i;ioskEjOEs`%_`e9;>C zF{%qs#iGqHDORn(wyV0ZANsw4$r8O5N8i<5z3h+gyA~f`9UaZ><lrq$Xp~HW4GAF1L9aO~{e0sL{-5!h3AMrJrWl zJ=^`X89%iFR#dYL`z#CC9_RKZ&}b%ns?^ko1FVdzH!R@iYIGBX%My(mhgc|Bi9og{*j*68ng3WY>(*N6My;$Y$LpWMgl8 zBY1^W`rLRlkloV)akPOAaP(&M^L{kW>>aunGx~{bDLPno1lZRAv9r*~_Vn`eIW3p3 zpV$xjZn2ZXnSz)!_`c>lkAG!sbsR4W;Jq8Nbz>O{FB?IZ)Gl=KeiZL*Vc2l@1 z!&_~&_udIx;hi6dUST^0Pmpj3f3+2J?@+PxFTD-kq@fs*c54l#RX2#Q-iFzGD3Y>! z;ZWN_DV#0FP%@E&eRikYzsAt?MoXmHEQ0N=(@u$^0xxcdWjKadSdYFBm z%WSIXRHM#d4*7KlE2d6!1&X$sOBGrK7u;id(~>Y(awmPa6YVpPR=xu%(>#>p*-ysamotggZ2nz$AHYBgn?n-|`L+Fr-w_Fx;bi6`zskv2({vxzE1 zI20%^brZJJ(gM3ljQ8CXF^rGgizR2b6nnR*+H-qRnmsfG+~2-Oi~|?BDJt(nq&-p( z>a!1BXCI%r4^!X)zGWX)Ph989f)5vi@hZ7DW7Sk_^RX`F2ZYc99>V?pKxL%TR?EG* zrP^aS=>WV`siObdi(V?PasXSnR9p|SeP@#o;9TnltzbwFry;cK5jRfl6mQTr9Ibgn z?8B)Lp2iIq?&^}`ZT25HX1_V#iN`%Jv@VYo6N!A>X!X91`DkzDd& zR+<^l$utP&scYaQ&U6HxEl6NSxz9r@A7Ldujpymh!t^67ieCGQRpQ1G7Off2=}Ink z)cKX?yz)_2%9d=TQ?y(>=_tIpl*dsPW6R%&)3uVvSYb*CM-F`3hyZ3fQK?@$I1onmk}W7Ot{FyrtI_A&QL zLE~UKqf`57^)MJ4r(hC3)w){A3EtrTPo^UNoRR->{qI^6f0und#4C zPvL^s;`}IE(kZwD14v&{BYEm6#Lk0mh=CfdbuJ>uisH*E@{Z?m*|@UwQCrSqKCCSEAhsLFteo+MI1IUf zDvIILE@4LPegO?sjZeD(Tk>`~r;Ydg*!9lk%!3@~S6lamhvabMTuwcP*N<;NWt9 z17Xr6{|>)_bqSMV12F~JHXlOMD_P^+FCp7lDne}>XI#3($|)`E`6voED%BQP1MH5` z^D=w_I2ON*DY^yUc$w8#T0*Ua+A>`ub^4zv@ zSFyIV#XM*4#46%VX`A7J##P6*=!@8Nb)z`5&^%g6d z{d|8N7>9dM#dwg|bWIJ_+0%$!A@8uwN6Sz?*$2R{!5*mF`f940DB zv?ZqubYABcQcfbpV7}%i+A4`AJ6uam5(|xW3v0+6GScj93_F542en4Wl6>GT>^bI$ zF|_d(3-g>qHwo-Z5U*}w{J71V{I^+{Iu|W&Pwd@q<1^-q&scXG=`Wzq2;z5dvmv-~ zZ-3r*ci14T@Xzj`KKAp>ckwvDOVi^I-s&!Hu^kn)x$hx*>bkoa@W*({UCa!}_=CHw z6n;{c>mJ^Y^V0WNBiu-vcn?A!zLy@p{0%+)c%l2OE+!yMe7O36Luj&>qHuQ(lXN~j z-rdJ23lv+>s$bB8ff)wB56Q`tn)?71fJGU0EY>I=w9}3OtL>@!JdIs9rkNu zyh5?xLzrQKVqBx_h1IOINwl-iO5Wy3{5T7zfb_60O-*}(d|~j>^b0qp7s(&PO`Gxv zGfuXQxY?M9VIsWtXDCRhkhEa?0}Z6J(hqBW?~6 zH;0IuLyDWji3@#v&u1*t?t}Vl&+t9=L45&cxliitHjIA;PjDE2{t8Fc@&Tt6MwK3k zAX*vu+h^!iVN`!4!ij1qZ}}YEHe5{9H{PN|wg_RUr>tk0m=(bXr=ch1l_ve&X_zPT(grmWkM!veKLdDyRWQHkt7-qh zC7Yl3dx33jBpKyleD@0st4Lvsr$pF{;TOU)zeMp1ii7`J#D$2<;(@JIBp$YNBK0Nu zc@Z%v=@JaHiU_+TMOSG}qAL%6e)2_m3(gVRPvB{{n_Z<>U!h7%P?Z+N!>+{=q87Wn zM%E=nEtU|qc<421v7}Us|Gq{omi^yatojDESoXiQn4ACd2DMREuFA6f_8U}XIjJfO z{=@trfOjX1xB3SjgK{{tw%1atTt>}CDCOx3#N{7ml^3;IQPgVlx2Q=hmehoHtyZK- zErhRq3x7@fm!O+O8@kX8$W*V)<6Ko-@--o=vZ!bLXp^ip)U(bL-a(taVx8dspo-oO8rVy>Q_{$rQr9lFB{ptGU)^A zv(Eq4=j9Km&pQ8GpJhLyKI_Q!S%;7Ki2AH6)#sld(KYLeu30yu0u3JVFFxq(KWq$k zeJ$RyW<2N<%gXhjy4v7w#t9tLQ(FOY40&+74hUvQx(>j#AX{RJ5f{=mX!tGF7q;R7o; zySD1$k3X>bvzNi8(DWm#H2aI{gG&d_C9G&g4d53(q9oH5=*0Ysg74!8|3$$kFcnkZ zClq`SQ?u}{pHT3RO!emrKS8~v3U%ubnP6_2)SLqIctu;)fW*JCrn4~(4RI4k) zh1O_W%lEQmK3k(DZ5*mo!jUEt9wVa66v3lj!KC`xRDIN$;>avN0DITBsF;_g8j0Wa z+DFK-V{l8(n$4?QYDFykk}Qd@u++-9txISA(kY?ExlbmQ?xxqwq(;LtF(i{3i_5l0 z=xvF(TVn6Kg1u0&OT>QD7StC4ER^n@*+>ZJ*M_6{elIoL_k;YIOUY~s=0D+rqMzTV z|AyF?Pi-HiwN#`J>)hm(yw!p@PwwuGf-L9r=&^$TMUR#Iv$vX?d>=k)4D1U`ggB_B zyBTAB)Uvo*Y8xE3;JOdKZKJp;QrZ`RztjDqFh126@=fj=BssC!dg7}#pr5wWm6DU$ zRA1i1Pi+PP?tOgix!K=il(2!G2A~5s3{?GioC`fAk?xEjBOi_*O8Vp1fp#ykFOVK} zsnO~dn6R*ra3`!D)~EdbYA$7~7%9o&YGxitsZI1(10cn65yE%)tHr?R$=C|r!pe8U z54q&ejDfJ#H7uhDxaXEx&Fs0=-(#9Ez{&-xdHK=IYKXG!zscuQx54JM4R@rC`~Lx| zA4GPkLU^j5nv?Glq5&DH7xdib?}57+v}H%a)s*d2EqVCDK-C4tlxlBKb$$ky50xDh zSVGx>J%C$WI}5}+?MA?D9fMEEf~wgm_F%X{WANRiu**^SL<+kkh2mMEu$$)4AW9*# zcT-pBe@uwow0yX;TS3Zugz<)^Xo*X}_7$==*^nwO1V^Cg)3ZSbR|MRxTLMhCYLn97 zRCm$+w5aS**iTD0PTsSty1)KEIqs*iYv)LID_M&6x82Q-Ob(EL(OsIHIgrpFq6DpS zAn*@Sf~h3`Q)Gb4S0+E5L#>aC1$J+&np16oivsk$933NoU(1Hs@oG-hg*yjvqWQwI zW8%#jgj5dyui~&EC?5Wg;&xIzBC;D5i3!$DF=sGZ@QCPYc6u#>p>|Z%ot^Qo!D>F- zI;bz@`HpmsNjfz`pmXd$I&(sxb38-Gi(d^vpEypg^^VG4qD$JtWL_?{p7J++bsnB6 z6s7rFR8QqlByfTnC^sJ&ifTI{^|Rk8@FYblK^GaQK?{UIlpj65I>uxz;^i&h)Ww8fiox&Ka@qF z|F-`bN%%=^hMrLXdZ|)3^Vx7le4uyvvfLg&_hbbcrZo!gSmDd_MA;c8Kyw-ADG zwcchXYB#pbm_QLJ7%;d}o;1Pu}#ox8}h|ZMrO<}0s%NR2-i3+P<xK# zDfhI-ET7hdb=8`(Wm+?KS8J~3)mo_EXf4%cS}XOg*4i_#*2eQ2t*z%Wt)1r`t-ThZ zb6TdZPA?zF+HVC|Wn8s@B~YrS&lOC1^cO53QG3RqJggXnoAR zT3_?C7H?J3`dP!Z{?;ySfb~)PHd6&{V5VW(piDcp!I?g4L%b?z-+2wwhI;MPzW4g5 z4fC#`4fh_Vjqu*7jr9JgCHPd(M)?fW5`A`RqkTSVV|>eNV|~BZe(>F{jq`o4aldog z99M7cXIH{WZGr2y_KW{XZDHoA+M3(DnQ|bR+*z-ON8zxAL#kz4C9?{R{l02SyrtmdJs6 zwt`I0Q81GpT5z!*UdU4~Sm>Z$sPH(wa1obYv`D00tVka{s;HkHU9_=Yyy#**p=i1fcxJtN@s@gx5_$ESB|hje zB|ho3N*31}lsu|8ELB>MEwxmSD_vf1UZ#@XvP_)bs?0LIb(!~io3bPIw&j}Y?aIB@ z+m}DAw=925?^ym{y?ce3de4dt6ZGB{JL!EYZq)l${H(`Us;l>_^t0Z((l7eAl{V-D zE4|SNRo2mP12)AdDPTl$i(Tj)!_UZMZ`b;28c zS-tA|@_N(t74=f}mGz70tLhKacQweY?`tqX|D(YO{b0jO`k}b$`q4(Feyq`T{Y2wp z`pL#4^_0ec>!+Fo>!+La)Xy~8rk`!9>(`p~)$cUd^!qJT{XvU=^oK1U>W^Ao*B`e& zqd#eLM1R_LxBjf%M*VsF6?$5S`TC25j??v*oyO^}IuFxdcj=?Q`KG=8PuJ%9{jRO_ z_g$ChAG;nj)NXAIpYEpN*CVsx-=nROv&U;ASFcDTv{!c{tk-BGymuiZcb{TLM4ygE z{yuArsJ;t~;_)So67k7K$$o2%()}wLWd{s1V!q96RQvXcQGMV8qvoL1My0*yTr)*1UIq#6e%GUMvRc;ouS z(MIZ|d&Z3)pBpzPFEDOR{$yOA;$hsGa>RJ_(*Wb~RNZ(wwVLs4T4v+n*xvHdwsUj9q-yj9Ze|Y_U`^TQ0q8w*J-2Y`d(Z*=~8H*uMXn$37_Gv}{KGZ(BaU@lx+ z#ayzsx4Crf7&Ce8PIJTB)8^*2U(7A*vYPwWl{fdVYiAxy_F-%TsqCLb&N=FCFRbsbhmE2vy zD!ZqcRc_BeR{6cntcrV|T9x+Yu`2J|V^!Io%c{A5v-Q=1g;uQt=d3z^9JT8H+1aZ1 z=O0#sgRQKF2d7!FhYDGZ4*h5~Kb$+kYH`HdYI&rZ)%s{@tIg3AtKG3EtHZIwR>xzX ztWL-0SY3|4vwHnK*y?k_$BI8u#Tt0xyfx^gX$?EM&>DX7lr=h~yEP_do;CASv^D$G zY%A&1dyAiLZ_PP9-I{m$59{YMf!2~UA^6*BEj_ab&xh91vkBIcv!ktLXA?GA%g^4k zR-DUjtvpxPT79mMwf@|AEBV|_Ys2~S*2eQQt>4c-wl-a8Z*9If)7o;Wr?vHpm$mKc zB5V7#EY^-|ldPTBzF51i543h)e`xJVZD;LGJ!9>=F~Hh?gEStiSGiS%2RjWu3VH#ya_+ryLIYO z3+wcwzpXQmt666sZ?(=nDQum8ve>%tG^=&->5tZ>XCBt&XM?OO&mLJtG zdo7XzU3yh58f;OvMK3KX9pnnp*P`VX-L)txk4vwUMe{7WWKnQlmtISYW?FQ@BHw&2 zy?PdnvuK}1EWb;ynngn_+GNoyi^>GMLZn)>!lHW?MTfZbI$Jc~qJJ$433chUvM9r% zlNR}fx%BE=G~S~97Rd!%dWjYdwP>?NuPrJY?h4V*qLmiiwc} zUTcdoEjne9qo7N#fkhK6I$)7!A(vi~MZ+xGV$mCm$`y8n=x@;~iyl}MTg0W;#iHLV zx?)jSluNITMcks(7WqfJ^cq?;(V~MEDKRd+>K3J0wAG@w7A3^GLJY8IwM7ptDq7T~ z*VUrmExKw^fnqMbFD;s7(HV;Zio5h0S@fethb&S{xb$jRG~A+X7QM5md`VY`fflW? z=#fRmO1bp9S+u~SYZisax%ApvG~1%TEy^8lPSBC%uyS>cH&+ysH`~~!v|FBH<3DVy zmT~K}w()Wsf3k6tvTpqaHhyDq6Raj?R(>hxR()#Ynh9<>xA8q2S1Iq-nQG(fHct4= ztux-n7j0asf?H>VjnCLPrlP5nTv4*JepHCeVnkMQM={XG2W%W%*{##t#yf4CyNX+< zi;Xwg*t@D*r@f8W+E}UP)@da;y_!4gA8ntL6Wyx6+xWGO>n6E%=Gyp)jcZhQ>tx#a zu8k|#aO+I5@iiNltLfGmCwNUwch*bRa(_-2e6bqyS!q|-t-8j>p7q@FmNs5$;~X0|uJ6|WO|aPs zU)i`$15?M8|7_#OHm=^#t&?HnJA(ZixodrLBe&{R8<%bDmXEdZc^j8VcIync@hKZe zHF4{FZ{xpg9NyHe)8EGXY@Dx|sgu;qo%QWPWY&a#b9WS-ZM@OOxmvh&zOwOZ8_O-- zIxTFx#Ks?N+^CgX|5qEowDA|MO`U$N-C2JmL}u2L+PI^bY2({AuK1-}XOfMt*tkqv zx6T+F|6}9gU%7SCY<$wjMcTP_z7ssZojdCV+Pgl-@>H;Gv$LkXR9x&8p0zi3DkoB~ z%c_|oRl-0qIm6;AV(jGSF&(5N!LfWs2iNj<+#;WjE?HfR##*%3BB_&0uc}3ZEy}j& zrA4JXyF&D}Xt_mqEsFZurPs-#c@|x=D7cGDucbvZEjnS5Z&#OIJ&VR!w9g{e&81h( zq9GP-vgnmXWxBgUq*}DXqI(ua_i*WTwrIXZ|5_B%)1}wSq6~{pTIAQurB~mg@fPj3 zNbc>@OSEXHMVl>pZBf}it`Pk!T4~XJi(>k^^uD&}SBoxN6q@SNYi&`cMW-xs^mFMo zuxNrs2Q2dJ@6t=MXqZJ?EP7*6xdE;a{ViH$(F2QO2fFmSSoE7kS1bzq#--QBB5u)X zi~I+<^cq?;(V~MEDc`#Es#}z1(N>GzT9ojeE5rbcR$KJYqN3ls^txK~yG2(mD)56# z?@NnjS#-vtfWa=kMi%{O(IJb}Auhcd77e#(n?>&|DnHZ}VxUE9EP7;7v0*N~ZWb-D z=$b|0X)e9C7R|QkZ;Nsdcj+~@Xp%*TEz;6mdNnOdw`jXX?=AXlge$~17Ol1Du|>s4 zy7anRw9umK7DbG5>3wC<9E;9c6gb+Ymu%5wi~h7oA7gH4PK<@Y*LIA#!kE0u#%!!x z-rUBEEhdA^4AyX*TXnvTU)cEb@ot?tHhyU1#0hSl88*IU;|deqIzQU@vW-js=++r+ z<8y+gN#^=$W_{Qsx9SNS7oO~ve{18zHV&KO)=9PT9vkPG>elIQGaJ{M@79?m zc-MS)&a3|F{yfdbH*8$~H@D6N8(*?<-0yCkkv9I@#<2_BIzw!H%*F*5x^=#>@j<~) z7rL|FXOUZVmyH7#yX9SNyxGP+OWZmsHvYrL>Qc8(Ya1`O@h2NMS?1PXVByT=>QfunT;Y~;8{e~Wm6dLtsW!fD7G0?^bY#jWDTc@{;ciK4jI=4<28*j3)_jY5dAluA9)5MB6wQOSf(m4Vnh@pY0%ZGpH_64Wh9`!-@71Z6lI)fZh>RB`UuKG?-{0Q8v*U zqL)OEh)VAS7268xOVo{MIne^5yF0}RSZN-$OOO{YwGAIS?Se`#qIpD1h%OP`A`0FO zDzqImlPHDg1kqd~-#wu7MD>XB?f{J=YDTn=Xc`gQ3pz?vjmT>!Xb904M4O046TKqZ zO;lzd=o3*YQRQ8r6-3_?-6PrnlE(6o!=@KH#c3TaE?6u~pWVtgMx zii6sYLh5@A8l42!1B($mj-)+>bRY2#g4uEK5W&@mhY21+JX-K3;%WTqaa6RkPn9_V zk+V;w5Ej6j8kYx z%}a<+l1h+ZztiACg6k6(7d)Ogp07EL%I1ASP zC5D~@J1ed=aTZTMhx(o`R8Ns;nPA61;N^lF5N{Sdfq1Ln1H{J!d!7d$7n}sl8Oi^CoU)WG;xAp|9`=s32sR2Y{ZGg&PF^) z>}*8kGGd?g&ebf{@hYW?;AzDD1#cxDAowluFdlgY)$VM!0aqaUU3^|myio8%;>CiC zUPVgg^wja#N;NSv;(-Z*MC*iN$!p-aVh6j2MJT|_g8 zJ`x=#s&ohBa}V?#QC*_-L}Q7b5y9FB;wA4QXFWv9z3xJ~m%c9nNqzWkgRzu#Y;C#$qhcGJPYFmpWw#OYu@jr6v`7DFdy*ht}K*i zK9K_D*Ny~!C5{zf%4>e)iPS(2c6=rTYOsi~?Nh0k9O9_Qr~S^bJcjV}4hVeoDFTOB zx*-%ef){xvm5^IIN|`b6mB%C>J~*BQ@|n-1lJWpYyffwjB4*F$kWO%FGj)QH4kYP( zM@gsdd?CF-($bDNA=OF?X|orQCOC>ar3pg1m!yLn#hlVXLR$7EI>0EZhFE!&qb--d zMlpt!VS!8=#gDy|n#T1vnYF)s&^KI+1JnBJ5}>}3T+x_J5Ojnq%>=xD&DH&Qg9k1bnzM_%Hs z)LriHs3=OJ_ZP9AdyBLNSW;(ge(?^{bXN}abfKI5PKrkv+VXxQ&=rjLk}qbS^gby1 zy!Vn1II-0J z3WHG_A^dobr0{k*Qn2SL3W7F>;6LX`dFl0Mcd}5woFi4mqrgY0EFMpeBBH(@asO%+ zAN5gcFRyXbHLHqG(wGnT|0H#QD4O@zSPY;033uAo@i>`zXr(p_-u)Vlk5@6itwuv%Z;dBN-R~{K#@n`5$TC0 zUdC9sw2`lQggn-lSuS}a+GYyFn?uHzY@wVjl)oX-CL!7+MCVDgS%@~1sEV{jylvrQ zkU-D|kFWKO9*6a8sg%A+nyGJ=-s)TUCQsH5t4Hz_Bve*m{@}!YEQaa3d8)#aciv#}d}bc;T7PeAAI4<}Cdt z@8FGy+lMfPukvCA`S^UUfY8)9`Mzkglzb4p^+QTm zLZR8q!Sc!v9Non@LJ3s9$bpY-!d!vF{1Nz}EpS7Bd_V2{9wyz(S_9^2Tsnp^L5h7qY>A48=XAr^! zL^`AM?P?G6La6l5gR;Fe%Z5k4AQbUV9;6BprJ6r4V(3=Tm7ytl@#&TLw39wvbA9q1 zWRLu{Q0bZvk-rgmeompE5cZFv;0~wILBb;ZeiW6(-zoGL!tyaJK=#Mn ziK@!)=jCndKTz#34V`31G>d^hLR5c%Em*++9V|cun-;@@Fa)J&L9^^|>)hS`P~#YN#~6Y1rq^a|2!q4I~Z%oiWbxxk#P!i!>T1UfYX zNi&LLT2=Y1qRN#6coR-(o0nUZ-|mQR3UhkgI%7Sw11_ zP#m)SPFa2-yFjvFrz}{=nwNkq#3>6AvSTG!VXQT)2csMLm1JJvkdmxG+EtH1`ZbSd z`gN(NenYyU-(=bPE%~;7+w-A*N9n5HRj%sy)Gzh>8q*(WtM!L^OZ}1lQGaawqd&=Y zS%2y^Mt|mALVxakT7Tg)SbynTP=DonNPq2@s=smM)!#a{>+k&c=7N3(7#>08(hMnRmBI4F8gicB49~n_hLZQKq2@bdX!#o%dj3O(5xmgI6%t{1 zh0HO$Ljw(;(8-2xm~QxmjW8Tx9}NEjM~#4pbR&0Uj1d@l$_Oer%*b2tjghZVeBy zHzhpZ4eXb_;#m;?EDq8Lp%-E5EhkB&kVHb#KrSeD3E|k6V$ae{O6T*3W6By*1}jZE z_bP+P^Ot62;RbL{XQ-M{5H?KK8 zI`NqmST$a!^p?qEYU7RbuC?(ti!Z9p%E3pl>rZsHY7H=nF5&U( z!Put3SpD1-q|@HV+|DoIN$;>gqmqoY)`xU1bgBJd|IFku~1FKGQPmB4ubifiPt%Y>kq2 zSt2~Ued}T&TI=vL#}QN3@?Fyq$LdJgi{Gt_IeM+wsQy`>`SZ%DSU|nD*faEpBbfJd z$T(uE$9&~K9HqIGi9Hx1H~1g*Fo~?=SI4?4Y@I!W>ug2oTp!EhI@*m>;Eeh#7~xE7 z?63MPnyt52%X*%2#1-Lsvx<0+2B^vPd`%m-++0}pHb4!n=Sf*^Id(#^@_P6i*5rcu z*tj99fXO0KtilT#V#&@%5uQFr^PI;UCY~o0AR7TNyF@Vs+s0L>pZ1NgWM%W7jZnf( zd|o4T`aQhECTy1;G(s=I{!4K-_8u;M2XW2DnE&L z2hLQ@9bG7&-vpbyYkX%D%+1%xdJf^kv#}S;*OZ0G*Bq^QI!A;}o3cFk43i|3k7r)PX?3)WJ8?#R!RpRiya*OKMJj;2ye zJ4njF&$5fD>!gLi~|)Z|dRBgq_obuxnP zd`Q!G4qw-rHG~r%GeQV2(1zt>s)sGJZQC$ElDKm@r45T)_Q2;A5HVAi_|I*zRtIo@CWrG2ZBZ+x{cC!;yqOw6gFKAKf5mF^87UyNguyqZU@}?x z6}of~m9Lzf$5B?aqMC=Mo3eDe7bu7EE9)@t{?Lx)mh(B93fo!DNA2uvrt|Gs7%b5A z-l(wL?J;Qb^Ahdh@hBvE-iG$*d42a)<@3qE`4~<| zFkH4}@z_9*crI6@a&H0ua&96 zvAOR`Tf0t(6)tOb=I!d1j*aEGcQLfwI)Tm?>LtTS*b zSE0>HD6iQW(yCa(%+=@H&ZxGk)B@&0hia?JQ=UQXXlIPAB>t&0t1VUMDLq`->i#u) zM0E#h`YH?YvDZy?Do+im22DX>Jn_9$v||6K_Cqzjx=wYlT5IX&j{RBJnY`DUuKI$}ZaYk+b4ZC6xo9dl*z)9ov# z3Sn24A~m4e>?}2+;StEEev7KYT0pMC9o^uwgRiI?+9g?x%e>u@t7gb5a#a!#=j^1- zgcaPlpseyk-BFz8=mKzS7v_n_P{KStSh(B*ORA{j7F1KQQVV_}TrS9$_rT23f?S{# zSWDGf?gKp4mgsR5f(X0ZH`qq`e2eyONvj5ybw8Gi|K1Z0)Yi7lr2{6Lt4vuoU$Klf#&VgDZM%O=ZxG4+Tek-lQFNxg%W zN9{{92PT+0SWC}iKLrCB^I~Y`5&D=a=Ap!NbfQ$DXm-ZM{V-(v(L5i@Z}mgVz=o#5 z<@f>B(2vFzdMyR&CysH4IV|Ofvb2pTWO2U_Uh{-Jb7lW|)jintM zW^1bCVS`v+&W7SU#u7XZx|Qc33TvVRNgex z1aeNh)2IvAk*8x4r*0(#l`*eQ%J0vun4jIDu@xL&j zhN3k*r~7;SXogl)-~_Sy4Ei1>(hRZ16eXNNGmdGo>wMS`h;N2)tC%f1gNOgXDq$0V zK3zzB2E(8iy=127_ouP0$r-Q%%@IL~W4}O$Z$c}BnmLU3fa?Mq2zMXLq&`*xB6ozD zVux^NILzBj_}!@R_)`MAt|EL~Z>IT4d?L$m%5Y4xSv2xV8wYfu{I(F8E=6i41ZwZhU6$ip z%3TESo6f4@a8jpDR#EJF%qjcHT8xnQ>1bqg8x)I&X-_p80h?s4U{hzx2dDB za0G1Ibu==fXooTiYeB?F42ShXv|fn%j)aM_L5Ma8(KZro6rznn9Sn5vlr=wv>oa9ks zV9}qYhBdbnK47z%7LP&WpA{4Pq~kaVe>4V5^I6mUyNg=aBISB5bSt-z}U}5@IK>F^%uxsgnfsE^&)9E zh77$X4v*;*&|$97a0~G^Vl2Du3QwPi#(O;hCAeyS%^YcZ6HRgLi4b3Ni?5M(G&U|2 zjj4EDgugKnt#iXIz9Gb=e}wp^TYOW9hm-i0TYO81kN$}D@3Gh~H*Srt={*UZ`7yS& znEWy6J;qQorH`&+ll$59jZu zU_Xe{kf~_dcRXSSLcAk8ksjt{hILb+{9Y(OoC@Xlq+Eo@PD6z6MTqwz#Cs89(KLkk zKp_(FFqOlmL-~VH{veb;2<53WPe7Q z1j};1n7O{dVea6I2+N#dnJw&BvnZ@A!p?NQm|>5jfb>O#m7QT_Ti7PEDXgamJKp(X zme{bD*wYz>rx}H$@d&ca%mRNthhk7f48xo+X6l>gQ0j^^sNzf=f8VDay0RIz@=w^j zYFIw0zWY005VkO1{u6~&oncjHSk)G`SCc?KuXmyiBHRhgXhKqRswHrX|<%=j##eXH+_YA|7szY>Y6-4g-c}a zLKL_rb%+o?FBcXzttL;>uvWfU$i9$kVarYK2By{GofjeY+SH`0aa*J|ZP96MPFW4J z?9Cz^YSebL&xn+xcBx1Z9Zn+4*u1N-9m_2}dyXo#5`cU&?WA$F|jUHS0Ayb*{^hC+6zm!Ho`d*()n zt)lM+Gb$W2m>E@g)<&%S>9(AIzXAKIQ9O$tV}!@x$_8|iF?0+X!V7K002oUfD_qp! zZ8n-)^0bX`*pES%FnxtbNjRQA--u~3hds{tV|)$!1t- z^F@yueu@R~-#4>T@~;kDF+fA{mD|t~5nC|UmeEcC3&Jv+qv^XXXrkrhFD%UGZG+Ns zzH19Ivz$NP0=MBxp0E}3+-gT2(dwH`&#|AcV$a8BT1cI}YcrpBn-$EYm^O32ZP@*6 zB~QHRz}I+}ZAfjKEwydJ$$Av}@;1z_=^N3two=*!dGYP2^Bp{SJ2oc!dHQzbYQL?D z_EWV8j{_wq@5lbyw!H2aL;e^AjNrp|V9hyZ3w=yf@R=RR&~X|C&f*^zL%~6QjH){k z=(w#P_1=jNbdt~5iCOS8->?(Q=ObDuo$ea#5&1qF%TKZI$HEj12%`lY4w^lvkEgWx zaxQOA&0(Cm8!oJ;q8FP>?NeTDH#T)oar4AA`D zXwYY3V@{KTr}oUzUj)wBgVW{b*v^=Fc}{ytnirqbcBP5@!qH2pW$tC4({6>L#wEwR zOnW6Rt(4q{Rs9v^jt))GH^cbYeJJ?{a~3@Sls_QSX`2u!wgO}?n4a-6`!ODKsBebx z-up4v=D08RdTKeYlZXRQlRu$s=DCD?07jecVY-4j27fMI^#FVukYI0=WIpMp=IR41 zf$0(%2ci7(GOXUY4zd7}!1!>UlvX{+%6jUOYiXEvkj2q!AF)zgImqG_U7~xsbRi5y}{ru?Nicq@CD6{naq>ZZ87=V3DG=$3x40|k;pFYAIo;n>Jk?)CA;3_j+;lkb50R z*D5GxtEu%dBAXt^d{~h8JC2@R5cg1B?vPyk*l|`sE+m|Q@qqSx%{ErRx0AivaDaRQ zSt%r@tIQK{8y2Auk{rt~pFsF>=#3b!@%X_E43SXY@FYe+IlAN-i-+k(TyzpgJ@^d` z`E#EzITyc4Itf&X&Sf&+DU6ZNXgtMu>YrhKFyo(k3eJY=R2NPsspAB~Ri_0!lz%#9 zGEUIRc*P_g%3Ges`d3rbk$Ltx^EB*{ny~J$+@LLL+6>A!r*Wo1r!iEA0Mnd^<$cef znj7%NXRwepbd{{3C|R9zNU@a_HrucQd$ zX7wL%C>Z}>ZcGs~k!k(mtE-X~-t8YG+mW*H1&%!a`G-}IdYIEv90rEm151I~HF}(f zv!Dl!mN-1to@WiDo=__z_jGAA9*1t#;sR=;r%>z3XJ5c9-<$8afSI_j>!8K!B9@rG znC{FCS!KN8Vvl(NkOrHl-WR>m{KPLZf6u;j?Uy0i);05o z3d6*@CS67Y!bGEW4VITL*fQ~WcOh_FcC#;|#OZv;W%!lTN3sH$R}lJl;gvG)3FyD` z#4G5W_~{nzJMht0a2aBuFiXg5#o>JMX8J;M;5hH4FBA((D%?Nx!JL+=|5N> zH;eb(4fYL|`A0XfVLrtJZsKv8C(z>zZ*vp(+b)R8+<6!Mbj3{!_lx}aP0R}y`JJ1% zk#va{xP`Y%JmD5=g4==PZ$TK&chDn(zobVbFLs;N#q@)Tk5(b02-!_>_@M-*=_owj z+{PG-5*yLPPiVj>%kcLhIhji0V*bjRt9>QSE{ByK)Nwv`h|DXi{$s=y*+*p^G&Q3 zHdcg<6=7p-VbNLFBcEni$nWFoKv63ge!xXZ78SvY+JY6e1%sTDJpTYm7PG<@6Jd*q zu*Ga)i@C!>KMzm(2!qmjl%Mwz%3~hobp2-Lvh@CbP< zZLW>{^&|AE(o}yW!kKG0Z~YkEwv3pjue?Tgn1TauEC(?4op*O|aY*N<9%F(@pq`Ik zimZlf$?pj+uq6na{rD=Dix~-g&=d5e^0p~|+Y`)^oOzAHs6^v0j0ZeJ{ws^S0iT2U-q$o-8SajaeTEEH zAv-OWeoRdk#pP$14Ss&ZI${~3n-G3}_Urlv{35iOz|(AFvmP%#M?Kb}dMt^DS#`BU z)pdS>q-%+)t0k&#{|i)IZCllSc!8>``@dC}_!2p*``@Z7$bWf>DyVC(zqQc?EYtJsf45%coJ#s?NeZ=>r?dTfWAr_K6RyE?@bYVY8Eiwe7}h z+}!PwgWJ_(_>>&>6;FGERI$3!ghls}lLg=7?vi}DNam?NW=+<<@fo`q%Xma9l} zG9|ezKkyzdrJ52x6#jtp+fjv!^!YVOZsfbzX5$zs?sn&08P4WIa!}13M58y%L8G5y zatxoG!~D6oj5r_Upbrd^<{68MoGbp1#%dKFr4uF zH*=))&bTKR#O(t2y|8#m&JBS%Q2JOctMO?P+zN5)Q9#jJsbZYq*R4!0L5>m{k79`Q z7eizWL-7ZQ+S)=qkT{yZXUN(>F+Onp**QK`-daZP2Dy8Lr!fd#NnAwA$M?&!uRIj? zC3;*Ke<90}c*9i)az>W+MASotd1M+l#!#|Nu{oq)77P{VJzG5GlAc5TJtjH(>`+l% zaf%#;<=pJm-zu^X*mPG8e~s2kBUef|KdQ)uv7no?!WdF5L4FT%YMNSOgcet!HCAX% z5)m32BAjGXokXfNaAVhuYo@8?d*0sTX4WDZ)1Xx@Obh9OsmJz$~xiN0&9;CN*;!=vaAq(|F-L4aRQB%-B2ynN@xn&y$0sUri1mEQ) zNBX|A7jr!sQ=z7(-p?=RzhBH7tELOnSTEv-$*%J%-f~eKK6mp*MzZ-FdTio<(PK0J z=#4%M*NBgt1hWHEC60CT;8MpZANezBkC@v{!M{Ez+g@?SB*7OS_tC|q2tLIZ^8L=M zC&9A9ANa}*@q59ibQk4VUfGv-_mf*dfD0q_JP*)aLDMvPm|MnQtqGL{y``5^3Cgu`XB`dGH2{pAAEAu;k+N6G;_kYXF}kKuQS z3LeHc`^%-k=*-w3UBiNS#Sf`O2Vg85atyYzfD3W~a)9R{e~+ocE~^kI7vYBjFq#hk zH~J{~Ff3uynn&FD!9Z@=41QGYA;qMnESJw{m(SC{^zYAM9C0%Zpn ztC_iRRrx90T9p2xk7cC4%>4uQvnu~02;w7VBjB2k#>WMrYL1AF8Lr-Fd>bj?PixTS zUsA{+g`+lw(s`h8jHWVEA;7!2Bm6&>#W9+LoVi#;%EyIGhc<7Go5SYav$lB=>j}Q5 zFtR=^FSN@P#DtEvEd%S6F5+fBfydoJ*V^LpA&OHpSK*W%MetYuC%scNa?SL}m?iVk z%=pcGNa8g4ADwv#&X0)Bi1gd!$Hy}w{V62>TO@!xTRK0PAB)G3!pKl!u-pn)3aG3c zogz2ClvfVIFF9ogZYLy*ri;iYJ9uyi;`rx(6$ghv@t^-FZX(6=BC+AIvcHHiI25gS zUUV}vzE+`7yCCY#O!)UuISTg^8raf&Lpm32IyJ+fbMZeqv%;Wr$(eR0d z@C_FxD5Kwy{I=DT`Fi?x+tz#Uk-{CfLeaudxMNdjUl!GdA7n2-6=#4@F?na@Z;HI?( zeONR;;%B_{v0XGi;%bNWaXNj(FL?3MKl^{i&=Z@U76ZMfwl3NHJ*ODvA|LzhcmMWz*P48n1;(gP)@Wkc%fbFI*gb_qDlqbk90p z7l-N_Yv4ri?ZxGKxT4~mUU0R(1lsB?Pbwi-kaqFGCFE*ptv!O3HXg;5uRMAx?L3w$ z?LF=)DN?M`LF%S-lolzSq+3d77Nva6x+q=P0;MavsdSTzDBb0+l^*f}rKfyT>E&5O z>FxQo(#Law(%18blByI|`Y8jH{>pA;fGQ~i)go4`ryHs0`E7lr(*ZGF<44*B^OrQ5khHphB z)At93`)*QZ`My<__?=OfI(jK99BIdtRgUY*YX4)(nt&Lr2R2#+ZR+Hmft4-s3sm)3U zsLe~aR$G)QqP8saPHkEyM{QlUw3<@(klLYKg4(g%Z)&H6ifZ@rRn(s4lht137pT3< zzg7EuHcahXp}Cq`;f30-;sLd1#lz}=iXYS;D$P)bRBn`}4y)WzO{=_C9bWmPnqH-@ zI-<%?>aZ%msH3Z_QO8tysgA9>Qyo`rhB~@hraGb8L3LVUdv$u!dUZziq3X;UfoevL zWol-v{OaslCDb{!W~o2buCD%EdyG1__F?sx&u6Gvb@r*V>l{?)*LkO|t~*U#ThCC} z)oZ1$ueV6uP%rJJy0Lx@HM{;abyNMz>gEO|)GZALt4A9Ks3#ltSI;yYs-A81k9sb- zhI*liu3l{NuX?3vDfMd8Vd}M}N7U=hLe(41dZ;&>WvjQEtLozxebiSi74>Z^S$)^) zmHNK*UG+nof7P5XPpKc<9#lVlwN3MAw^ozdFVa}b&zhXpVVdUIag3&P8my_Edu!U) z?KQniOZ9D+HkwzLUp1dD`?R30ZME=jx)#|zKr7V!E3J6<7g}7;SS`M1H?4Hf5n7pE z#k8`$OKAzcJ7^VpFVm{`nXA?8TUM*pcePeKb-DIMzbabY{)4rq0|K;W10HD22j0*74gktO11a07uLfW7q&9$^4547~5$=Zlv zow<=*K5yRt$#6hi{4=F8@=H#+w{g+&GqE0 zPI}XIV%lcRILiKj@uIVZB7waA8U(`GOT14;ho22*r?WW%QcQ3u~f)0A>!dSik z!W#O3g`r@T^^`*;7>&up{$1_`B zx$KF)YI%&lW_dMz-SS@g`sE|_-OIP=dzPQn4=n$rA6$_~Ke?i!eriQK{q%|v`k56A z^$RN==oeR3)Gw_Zr(ao_WfWL>#t2{KWkjq>G9p)fYZP2H%_y?ErV+JPHe&wJjo5WQ zM$z>FMq05Ad5!oDD~-|{XBlNS9yJoOcN^t5wKXbi+GhI>PGKF2}Yko$Bop( zaYp~c2aExSbBuw1&N2r5`NkM}WRQ_|)W=9aTFn@9^lxMAG2NJSEX$aD?1VA%csC>C z_#9)wiFjkti40@$iMPg*lkJVAC#M<9Pwp{RoC-A7oeIOhjmG*@+wr_>tUsM*tUEoz z*myc^osoU|ma*wfK4bHly2jQsy^URG#u~fNTs8LmUD4S4_Y7m--}jCEXWJVG&do3m z{?o%abivCwd~u%f=cORyuS*k*BbPoINBp%FjZ;@{8>g?f zHO^c;Vf=lqrg8S#Hsjp&w#Gl#-y7#|%rP$9tY}z47?*Y2(S0I>yr{cZ_FG#~RO{MH?@k9WY)#?`phyp&74VEHd7_j5prCTxINf zc|d86-;ndA<>c?-fFG71m*B|>FmYEAx5maCkCI$1FBijx*yI%A1H{EQW|x=e=J|g} Ch!&>+ diff --git a/target/scala-2.12/classes/dec/dec.class b/target/scala-2.12/classes/dec/dec.class index 5bdff0f4f86374cab4d7c3c6c0ae4b46ddf0a971..8a0b1c88c25260b7023631aebac9fac65af249ef 100644 GIT binary patch delta 643 zcmXAkJ!n%=7>3WA+or8)?M<4$HkBsl{%6QvZz5W75|q*@pe{P7LnmvBV<~Rp;2@;r zLmeE9s|komrw+OZX4XZ5PNgWKL+p=DJ)d_u&vV}Qe1~)Td*S|Gxcjk#Y_r$dLauqM zyM_GgKi#EG?9GI15R?e3Ue)=YsHD z6+R4FtD*#xo>yUOrY?i-3wIWGDe`LSRld*Ptf7kh+lMurS-Zb4g*cF&IFxm9Bsaug z*%rsLCx&t$PK*Tz<1%2ZBV;^`cWn~yPJZsU~s4G}AXNz2ES zbpxlZ2bi`x(5=siT0_Ka6EpTQ;&uZGyM?5^gOt5nLE4F8);W(k=Qc9VBg{K*kaa`I bxpyJmpD?^7m|hc>*N2^tsE1#Di3$B5P$!={ delta 645 zcmXAkJxo(k6vyAc4+`~xK1x4;Qrf=n_aNo9yw)fQlYf9^f^-tKX{ivX6!SnSFfVjgr{>mN&a> z-`Hxx5U0(Om^m4qXmXSYy~Caiy~my+r3_Pivc#C8>x^mIW6aQVMut9=#k5)a!^l!* zNnnmHF>-X9k*5ZuK!*&Cj+U?{TWX%RE8@1b09R#O)x+u_zPmHJvuI@NX|X-z=u zAfojk>p2YRmocpGAgVvXi2e?v`VYj6B+eKsP>fBC8ILh;9N?_+9p_91aWlZAxq*cF z07hK49 z7$=ElM?DH=9S%5r*g-t)h~qxuf+K);i5aI4?X=g3Gr&qHp^KIBoKlw`1*;zWUG?}9 zaoiPTT7H6ut`LGvj}dnOpC|5i`|&98hC7ZAh}xg~dPE$9duwVvk3Um;FH;BQBGlA+`i!nDo+IpcX$OP6vW4$~SPEi(t9l5E98w(?A*($1U zrO&Cz5Njsgf*(d}NR7taI33Nf7Cx7WJx6LZHpE)#WG+h0$7@M1z8u$5Wh$}(Z;@)_ z*WPUKU?^cEm&@3ZXk+bE_t6$ge3;0R%hhw6>`ZD|2lYC!J1*g0+~s;V8}hL(m1Lc~ zHyxAk>y(aMu9u0aFhAYHy7;|vDaX=Ua#N8Sd?91NrL0D;ie6AF5b_k$AS#Uj z%1w~3yaWZxWhhj&L6K??6svv)joJc|dJ~kWPeG~rUnt9qLV4Z@X!C}@1D&V^y|@t! z;&G@D=fMa)V1hBIggG$hw}K`AC|L6!f~}w#>;(tGQSb*i3q#;4`~cjAKSEWJ6{?E{ z!BcbvyhTsJSKJLX#iLMLd=LDZS_o*iL!IU-)JtjzO1%)05W>=ZXee<&<8aA#h?Gn~ zv{VkU(msfn9)U#ZI3&t;L$d5N@eU-*M<7vt1XAVWkkY;hY3%{xB&2maA)^~7eh(?# z1IX%TAgezMP5N2L8Vt~6*bl1=*NHQ*s$u||E6x({LbI_0T8yK_&tbU5WPw)GW@s@T zhSo|ov{kMq?jrsT?Pedenb#A)gbs@c?UoP`q0@2?I;=|Qv~Ghg>m>0{=(25uZrefP xHR!h2Ly!Gk;tA++h|ufE5(kO5q0gy;US}O-o$cZr`vwP_)Aavw>C}8{dQ=-uHAa>)^pcxYrA!8#||8}cIOj2NusC|!4V9>2+Qz7 zIb6&aY%uEh#nl?;@E zWSXbfbXh!2@^oIO;c4!%-btPWeK<9_ML)5Jl246N*uza!(thb3+WQ^l};&x-4 zsqvgugI`j`U>DJBs=&>}ttKzNOT1|E;UnVTCI|MEiWoI}@h#$Bb2UCBeq#<|vP?vS z#g8Y6Pg|ULpLp65!B&Tee_6aZLyTLUxJ=w@^N9wg@5yv)vbFkmZ3hfBm+ zTY#1EJ>Rnhae*o!yALzmBJQz!v730sUX5=M)ul1KOMJdGf>j<77bx#07M4Zu6XNEw z7^=J?epnX9UShT*hDV7{IwJTB@scBqZl8!UX9#x_yPaYDn0Ufj&BFMja|8DIMXYxP z@EGxcE68g2PQP;nSd^R5UBPO(ZE<^89k+AtAd7MP$6d|h+>#z2tLHZD@v}ADZhL~P z0R?XpYvg&W*UOr?UGxT6Gq*=nTg$D{7h&tTP5V4-J+~!afNkJr^#@rCw{89aYvnfQ ze~Km0P(F~JQ0<~GlNo2qz0!mrd2=-spe&$cNi+opq)9=tkIK5tdCBxZ-eCa}Dl@Xu zLYxbXur``v#c0rx-nKevf6ysy6C|^=#DXhvIo=6YvUc1QvSGBMf^58^TiPy2&ObJ@ zO;y5YN-K}EPMT@MtCdaCPC=6Taaiz&IyuIwnpqd0vl6%B^(qae#gHAdLtU(!>f7jZ zF*MG4$Q$w1u$ycuV#lR$jP>$$u}C}FRAij>(aCHyH4_)2P8_OMQ)MwUh}X#a`L$Oo z9T=?9QA*8tv8I^~P~Anlkm0?WIHgoQwUeDuHQPwN_1ID^;IBNTdRHqm(O(;7gS@vC z5%9BG4W(2s7Lj9ST`L>n_exDUR;Q-47;n8*dLFjkFKs-iC0TU1p+&ei}4V2BI_pS}8)2bP04a9q477 zpjdVRN@S0~Aa4ev{53GizX!9z02ak2uqsZ0P4NfVGr~}sF$rZE6JLQtsRpNV7+lKZ z;8xxT543_8X21u3fkw3C-G!>`AcV4CfpGS>5Xmt@bQy^njp_qv5ERfTB%nz^Xclh6+B^%ao5+|Md zLw-86)ToQ)A*{1~TjUxEL9@xR@C9xR@C{xELq*u;&8+HZ2QO diff --git a/target/scala-2.12/classes/dec/dec_main$.class b/target/scala-2.12/classes/dec/dec_main$.class index d34fba6cf9b50ff59969fd53657ceb6f409e8e44..e02f5700d3be6353778403e952cd3e5359b24b92 100644 GIT binary patch delta 99 zcmZpXYmwVV!Z diff --git a/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class b/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class index d85a14e867952c83d062d8fbcc71cd78fef194f6..280044c6c965d1f02928cd9351ad29e52879b3f2 100644 GIT binary patch delta 19 Zcmcb`dW&^~Efb^eWILt+Alc944FEoS1)Kl? delta 19 Zcmcb`dW&^~Efb^hWILt+Alc944FEpd1*iZ3 diff --git a/target/scala-2.12/classes/dec/dec_timer_ctl.class b/target/scala-2.12/classes/dec/dec_timer_ctl.class index ecdd9b4555d7dc37314df027fe1a67115ab0591c..15916c2f22ce4a69a23438c91c748e58eb422455 100644 GIT binary patch delta 5199 zcmZwKdt6mT9sqC-2NxXy4{+~ALtbio1yMoQ^^u9_s+eUfpd~(dh@!~L5WL01LZDW; zA`ZJD2!vU@RNkcdK-5YQ(3_%wFHjy@*=lZoq`B?PaDTt(^VxsS`Of@)Gv_xm=WsQr zU(V^5E6X=XzSJdFMbB<P7mK;8n>PSh#XFGlhDc^$E_Fs>5y2<5gNqG71Rs2-GK z9OSJ*<)GS8Ht~@6CMpBfB=jU6YFoGivfoFYMmrr{A4wO0#@_bR5s20?Sbe`v#4z=wPZC=}1)C<&{4`J3Fs9Mw$)Rd1P zZ!4+<)rT7Q56BBd9Yl2sNxPvozul0%57mkydmy?5m5ORa{TKC028__5>QFzSrs^Rt z0#zzx&_iwG_d-q(Dj(H_vde@#e^eH#4K;Efs7jRl zF+^9PN>RU}-pql#L#UroJ_mSo+X1NUN73fBdFR5oY}5d1P98+{sBYBsgAh$eb)ww! zA-WUwE$Zb0i0Xuj3ZOQ}LWpcbT|n7=0?}~PX_Qg~(G942)QCe6U5lzfnSKh3T&^23l*g!&I^$!8GFMLj~z{~V$e)sLE84ABhKUDUJ^h^C=BgrriaEx8nO45$fZ z(61~bp&1pQE-qkciXehTsmQ9q#; zorY+RP~&MRZQdD(WTARdGaDef8+9AyaTcPxP}fnejSx*lT}F*N2hljxMWH9>pth*< zkkg1#U4XtY)R!pBuOJ#^lq;=f@)Q3ke*BeI@)w%?wN_dw6wb6tsF>+(pThK_5|(wpoa*rJtkMC2e-u23ga9+g_>O8KJg*Q%wLFKOt$R;^SbdRm!Eg-Dy0 zrnhM5k~XbWE_zZ~&-oTxdZx{deTom;27jDw>Fmq=zi9_9zr(H;SNL`3l?8HvGM5G! zoY?#p^tnMz%?uOeLS;GaX@7|>HK?RQy58VIEm|z-9>W6ph%%FBOGoHqgO7Yv@q#?& zzwpTZR-R}>OTXR0kL~I_eq>i|Y3x;Zeq>BFOzg;*o-(l`W14==ogW#`yQYx?l?i-W zCA!*d(n&LAwXK=8H3?LvQ132#YPdF94*GuyLB<5nb~`DAE^QwtZJ-hDK61F?BZ>^X zYbk}(yX`Zi2wK?X!LC=joav_P)^dchk`}S4oo-q%zfQe7?PeV?}jvi7@w6ac&tnIX8(UwjhIey5};;C1cD|=7x zwmZ>}x-{%P<%`s@MS9A*Aq&(EnNc@nfjZ*?A9b12@|%`yBwwU%=puDukvg$R9b2R` z-E+%}eFiJ~$I|(ImU6=2QdHl&)te;`J-Y;BonE)?SkmCW#NHk)CDPzt2evB;J#pJo zPE?lR&U}AcVeMCOXA%|1!QH&0m6Ov4aQ=(9UMa;maejN(V1 zN~^k^XvWmIew4Ou^~0p0Ri-IR#P}IK3YEIma=N17c?4gDP_i|kiIc;xiS%-QqC62=L+xhmyXhgJ`Z+%+&5LK zpw9gs?7E`gL#|N#*oipMn0_yLq0eulsAa|InaFi);h#;~1qp^*a$ zv%7e3?trsgtvHMRI|I&A4gGCkp;XJRlZlWAm?$xQOLNjzC?Qbz(zekN5<@qFH*g_IHY&VJeQy_^pw)rTb0%0P0gejvG{R*^i#p5!Y!QlRW7h1SDKiS>9= zYON<_Hom0Xrh*)?X(C5$y-0;BfK;lslPXmosaCs^8g(S8RacQZjh57Fib6T8V7LN#zjlO24)70f}mzc5EXP?j~J1-MvT#{iso4pZv^EO5j93Rymxd& zELQM{iZMaF0I#TAf){wBqJkGFhbA%6xcLwhH(OoI`(N@r`=$F={eP?at?mXivr)}# zRP*-FQbM_Ryn&yd;tSdr%To2>oJ{-oM^Qd_2v|gPuda3n&eT_CR%zX9CrI z0%bx~kn2LK`v_VORY<*DNWBeTMAgYq5%d}wu$bx=K>5%QP|we(ZVvPn^cd>0gz7$p zwn&vOq2Am+r<%V*R_G$+u$1cl2Bkp7(67+IWi%rJIt={?`6W`_T&c7~>g@>ZU^5pu3Q971fQ0QlZOG+tqqqz-sDkg&ga>orc~(gV)fii=d;>OQ`o+s*8m7LJd&Y ze^T8vXggFbrC6x92^Ol}2wj2LI!Z@EE1^>8KhQhtX~tsc81xg=$4YfkP>xikm3r&8 zfoi5hUqCgGdn(n1KxxobsNF`Y3x-xfWzg@?kTja{nN(I9_4W#h|0b%5hW0^CPNJzf6`5tOd~?Fvfw<;CgxZ+TrV|00D#-#~0LrBk3hNX?*h5|jh|27Q!C zb-SUTq2Mig8n=ad`$3NN-h#H$ymY7u8oZ5CD^v^h+fM0fs2cM7g3=`D2K4q0N*7CI z?V#Q~cTy4uorT&8y@tl*QQa=+74&{SrCXryp}@nG zZh{)1fk*Uo#u4i6p&aYI1stV$E1^4(?=ec3LD!*f$0=P1RY0A;p)?jMgN!FAogMiCB)s#Ypvve&SIt4kMqjb7WKK!uI zZ26Dk7w61Mm{hOxW+hxI;=Gw3FE{aQaegJv^&*LsiT4FF_pdPVsp1?h&fCO!pE%#W zU{+#fg|XbM#7T`8nlF_qv_$H1xtZU)XyR=v%t|5;s2HLo$?Ge`I9ckn&>E>XLTjZ4 zUoXlH8RKHt(`g_ysZkg0Lt-HRe7JJyfXMw%;4>x-k7Z#`W=0P=` zc;&4Q>iqv#FyB@XQ01;H;G?R#DhWKQDp*~r1D^?m5NL4 z@9RqryYDNGb$3RpNm@5KdBoigYO?0Xm8YHf=XX7XKaftWci=^LH8CC{>%Nutkan*& zD=9p%x|f>LqMa0Nikx}0+FhiVtAo|GEw;9n2iEwA5A{)17rwT}BtBGqlNPbb0M*iB zgO(O6T3T$-V%y;J8VA1ro|BlVZ_?6olNPy2i`=9|Y|@LbyC0}n`MAc;d{~2%YHi+% z;XB{s_K7Xuoz>Q7-~)G2)cjoHA9PSQ@EP?U;;Cr-YO1(RP_-wwK6DZuL+?O%DxOa&fBi66-K@PYXX&qgGtaN>!q-3QsAgz?)?cNY z@A1}3%Puptk#c_jI*lu}Mm1A2>2(aBU?v}08?5fsMqtsMV$p%>F3m%J8xD1v@KD<# zZ>w3F>mL`$;>+uT)dMZw+5!2#43CY`MPZ)}KLvyxZt{qxfYpqrR_N zXv^~I-GnFNE`_$cu!fFmk=6ruDH0pi*NSKeQA&78gTFYwXy~Jqa<4{zaU9p^ua;^P z#2fM8^BV27kd}|PRGW$5<39%R`aAsJb1voWnue-pw2tCQdh_TeP1sM~cx#iFdRFt2 z*B>@{Dd+g_O~aM*;@FLcJ@ryA$jp;_JagcOo{m+^F&?j!@p;cYlS1uGY_?qw7G~Fr zh1>OIbLV=S(fk_&KaZGd1F4iU^26EQ#LCzm9WqwvESyj`7g4L BpkM$1 diff --git a/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class b/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class index 813911d5fd684cb5dff0ec2c93c58ff04e3a5050..e0446870323234ff0aa092441d1ae06238f489fa 100644 GIT binary patch delta 271 zcmW;AEpNh57{&4XT!A>Dg(joHPuzqml1T`9Vq$_!?i&!W1cyO$HCV*V5)u&QrKA){ zTEaGqoIx?O55U8t{=aj=APhbS4lQh_P_kpk&{A|}twd$l&|1`FMWP{VBRa8SQNCbk zD|%)ntQzfP$GrD<4U2{ja@AR>sLRSkbJkJxUou-KYvPLRbSYMPLMz>pxz zKLK`WfGmrsqNW$nVbuG4lNn`4+0VBa&22N0wB4Ao87F1Gxm9jDZfu8J=B~NzxS@@F zE?8SpG+}5bDzNq}mps`M-u_+f2SW!rF3gVpm{lnh5S3M$HbHdvKbI zo46RAh}xFRP~5?KUO?I~ReLhyFopLso~ZEOj3+DHWI1q*!lM~aQFuEr{kR+!pD}ld z;<~H=_hlGnWbg{i&Q8T$3$Auq;cUiN6t21w+UHilMn6U+R{{}`c1y{xGR{`mxC*$G z!rd5KD?AsNnyo_3GmIh`S*-@z$*3)mW>A_@j2#s|z__}??^*ldYG{9#1hn_4c@D>L zv04%YDU6mJGYg(`G3A80=(+~R3Y4*-jNdA}j`6#+^J}zrLhDC8k~L@YoP%1e*K6Nv zzbHo1dd*iGt*~)}R@czSqLhVZVPR2!XNerw)ROjeDMc%1`MuF%j;>_;y?s?k%P1X+ z-Jp4!ZNJ>0_11bSQ@?UMp*yhl?w9blqXCoRj^`z@2U=#mfF|`i*BKP05aF8TLj9XCZOfibQWHOpUwt@_&OHBHa*EXH( zP~_|Fy2=73!%0g4=}8eOTBLa-C3c`0(`1d^q4}97>&Xs`R_~891?_~6X%a6mHu2l+ z`j@|*u|5`Oa^4MWnuqzt@IQ=AcEb0dEtAdz#wMHH7GY-J?7+;9P1PEhdwDVyHBGbG zBn`N&n(_5%sA=L?+6%tP%B;OwH?0{R<%#S^nk`LAhQ+V;Y4tdyfGb3Eib#fZHh8jy zL0?xVdbbyD`<_`X&8(sOz#5hgRx2~>2D5H4tF@s$cf^T0q=VIIKUf}Stu$usV^$l3 z-bE*>y&o)>17LZYS;VZR%%w>PuHcsA2`O)`1hys;kV`rEgDSL)N3PlURoWN<66@)V!(BDa}LkBU0qL zA`Yj)3?P3dezZuHE;AWJ#xo$H#h{tj~e?P)8=- zG*gjNidg-jYktq9DNSWEkd85FN!oc3AM#Wrib((+V&X@i6={{BmnJHb&ZH5&XVQ|I z{Rt94a*2r_8E)##?o3)zER#l*p-N?L z=_)=7QN5IqrSsY-GFg#>Onm5* zA}#NrG?0E_(vtQu38lXkv*}%w0@B9b)uvj~xH%01L-;1p^05LrVf3VEoV1^N0B zVxnh`R?duv6~haQ;r+#MPBCoz2z8sY9Usk&Mm*9ov@VpCt5u~wxiIbCPB_x6T&jKdwxIW#9b$dbTwzjLmWP;7o3znjJjm0&BKPW0^PMNG=y1F!BeYhO{RJV( zvrx05j!!gutv?<82ie28Cz>6FywoZuL_l}l6Qnk6|JEw&ipJ_YOIhqM@w#uh5`P)B zRz?e=qMlDzM_Gvysn%-M| zP#zRB-8`rto?=KvA{;55D5f9gq3|&x*TturCz4&`GtFJ=LEcP;Q6vcUe8V}}Gc8?n zp-IoR>RL^zR-jd+)aP1T)W8H+ww+KkEMG&XG>G3?(aTUwncH8Oft_Q}O2A)QAS^>x znXde$MVWBgh&P(8BkW8x2yS^R6EC`_N=Bn-j8c1}E*sCJ6D2cgPFafBmDOdQWyM*H z+@_ousClK0EGPCk$|eR6ifAHgqRf?Bi5g7Ail!Y0SbJ%do=;B<0i@i2m7I7wU?S@{1L3X0Av5ZiV=+=-0mj&Yc0sm9bIin-XLV_E(}z! z0Mok2UAWOWE?#jL)wMSC)?K*Mad%Ocnl}{H=nad8H5BD>89CAp*5aB9TiMRgP<8Hf zLs5aRCO@Ig=#QEueQqeKY8|LB)ZB>VzVjbNvPAxNJ9 zfI#ZuD{7!>K_lTRJ7VG})C_w+72?sIUeuU{*K!dcSF^fK%E6yQPW}4yC_!O|`C4Y}<%# zIEs0kvYVkVMU;dc=MlmVrEoR;Zsco+V_$TmYRz=R9h#xH-6^6O7PC8D^fC7um=(Iy zyJo@_Zd$!LX3^i!mLeJnC;C!Bl(7{427gujwj#TVKe_cpgMBIrdoFlYM&YmKqO#^s z_AP{~rN7Z4UhUt0EihB48^HtNsr{{muw(g6)k}X`&7$B&@J@eTfm$GyT8dVj{qpV{ z)l#(40x6}Xa1nt9-s6t+wxw`HR4Us_d?SMlb@b6E^upkSkWuM#5`^uspsT104jSiu z5=7aS=%s8e>S`g>ptWc(2Xa-G4diw3(grbcCe1@sr&X=t!QLL&Kf~DbOwK#Z(107O zMw>lEMZU;-h~^-?SCpF$qp$POY0oxr<*;I29|o`2*JxuK3^a_F#Iz;DD7y`u48+pB z?qPJ_3te6HD}245r>^hy+T4XOLw_EblbvUAXTUw0eK8Ea=*%-=8D_LttOf^bPf$4+ zCUJSf2puVSE-bI~f>VZ*u_hRL^gr)~ts2g4yU1`}evZFge-pNrBHZv3-5-NJ7EZx! zMNMrK&1j3}BH2Mf5`s)_N}t+dWg@9sd-T75Wl`EvM6xA#X9epT@Zeg-I~{4XNaR+W zs4xPpptxOiIgVgqjnldY>z*L5nmA!r{l{Wfk-{w%79#1| z_rgsZ&x=(x!A+C_bZduhkLTW-V!(KcX(v4J?0~S~4uajG2b;3M7)(771V?8Y(H>ql z*)U#B&a(F6E6d47ixk?i5C?*N9Pf?El-(X%0PJaefYf4+TOaeq^J(U z8Lu0wI*58Q#vHX`RMaZh5g~O-QOL2RLml7dn7z@fx@ z47vtvWZk!?7IUT!ov<0F(xn$z*s+}uey7p}&I|OjVJdn44L`xriUpsFK&cxSov}Y= zkZWgAU(Pf%r*At8Cz{Y1eVIkGI*U5g2bd0ZhHuPat!gBF;6`()l8>mb#i}qnySs1z zhSOJ}{oRF8#+qYSEMgaXGZp&i?4R+Jg^(7DAjXF;wYKLejpa~=4bdCJisf#)SczDp z#Z-NPp=?LDx`=PJ`NdkBU#zwH=GNw`*6Pan<{&v=S>^}~rX3l&iCQwwP?lmIV2-jq zFqyuiaN5MFjbD}bmKLWDgt(&Bv7+p5x>BG%=gkAs)6(bAcnW)DZmZLf<7Z}DUGYbsmX}mAIWRWS1=)rE0p^IALMVzpire~2d=;^B) z#JO0DCig(dTg)3>MKNHv0la+yasF5%GJK5uM80bC9-Y%2-kHc7(vi};i?WamRffRq2_{BtrMxlG5T$z~)Dc{((8}JJuS81e zjoqDSw20N$1`PQFJbgJe`~iV+1@-wse4`=FGCwjp|GDmz?^FPdtZdE-4p}9 z+->+uB|5uR#D_u)xyMjhA1Xj4CEY_&{e-`kN|yrBBRveHQubnC{XkBoh!+S6qk=?9 z@(B_rkvJDtjq!U*0ZvGJU}GveMKqi94H!!bOULwST#N1r5nmAwRG-9Z@J&p3SIsYfgM?*rPyE8 zMt^kU0PON1W?!m8ac?|;DCWB`2#a=*S5(bC z6l$xg2UWn)t4;_;)kEePKE!?FoGc>*;qjmTVmwU@5e?}|5Ej>zbsXlUF=dX2**|*I zwP2*wquF(;g$R3GY4mA1Qq+tSwH*jY_=7uE4+K76!_K4l;J`!9Orv5rZvLV241E*( z42HA+fxyH8mMw7df02{XKWNe*xbAsn^!)#06uf_pp8v1W^Jb&4z(&^%Mkqgzj6t8o z^OQXpN!@uWIRuSls75mMMks0sydU^q;~B+_Umt=VXTbQSfx?AC{4gurUz#`wHw>Sl zqC6!H68ygTW{?OVyPt$D1r8P+^>ms_pfXMV2}<7%fl@b$9wGwp^&@MD7(v^IiAwk+ z5H}n<=(36}_QS!tLWRR|f^{5@V15M=-|H_#oyg&Ez|+G-XSy|9RG`|!;lhScG}eoC zTZbY=yrmY%b2>uDIEcW|uh6)ylm*tap^KpiWSJaQT|f}eoT+&j#F;9%bQ=jL%cS6u z$a^wrB>DeDP^9)o%(a$o6kpz3g~t@#e14hJH}uu=BvrcrxHJ7eV_6zpbB;Q8Lse@ zmjO3iYtEye!m0GT>QnmtXKdtW%K7vQ;4}K?XXJd(sd^+L?F;G^DH>>nG@Z#y+QZ}( zJ!0~j9L9ggeSOVb3pIXfKLymY-B|qMP}ICmlVa zqRR$6QnK^G79MH%?*ED6e?f0QtI5_kV%9I1{m-V<=vPrzh|d&f3)^nv5n2bSOVq~V zYl+&N*yzoD#^HZ-vT(H$pNno%pVduDAAj>GcDm2(hS;5-smCOE-DirPgyaA<_7wHi zj*F&S3(!f`-_KO&UsT6aCg>g4XW`SY!pPO_Cv*ESQ`GY> z=sBm<#{U`H7o){4wPC+dn|wH@K8kyj`C0|pDP3j>bVB9hJU(4wx~G3p_jJA1-3d6; zlA;8%a8!6)Y^W%{FS7Jb4fP9ki{^KTe^l2g`PI@QTxGEdm&<=1uuw`{wgCaC};`} zd<*p?;6$6JU@M~9alLIuN0l=;6m+an(|7pB9%CE;bj#P|$`l!mcfRBGJ4=o(~joM!|`B1@``ha7wp13QAacKVXvp?mQ*Pg zSH!ZIApNE@AXYe{uESd)u5aN6WdhvKop9E=tVly^ArgKB+LM%;A;G4FCK37tKBzi_4{ z3-Q|EK-(6I5d3>WKUlt91XrxUCp^A`R-o0N;7-Wet!UOF@ipH2b){3RR8d#5lofIF zf;A_qz8LwQ{UT9Klvzpci$pWp!A_6MjwKyfjJuwJ??K&=C^m@4c5|X$Oq^+AJY?0` z2dmP7cpO>P`I!}33vdCgPXEMX4yyBK8LTGzI>h|uq`!oZPC&0}@cUT`h$R z5=0Qb%61}OLh?|TekHU~kCI5V*6Pzefah%o>!>Bjh)XU( z=;wzmlI>w^DOGG7lhI%xGk;78-^E;MfdVuNb5}>f9nA>KGyOg;uOQCym zDQ6;#3K+#Os+fo#v{IU$z;vCt!xCZDLviDoTPG2j^sYoKTaQG@^I7htEo0#jdoJYWDI1v9Qf~_Vnx7KoS zk1^`WsDR~NmAvu_)K6xvH>2x}!WfAaK=D9$Wz#JkT7mlh%*_YF2TPq>VI{a5nA?`o zWkw@`wBAad$XwTz;GSaCo6##qQy4j|f_=P#b5A?00{1p^$1p0f3TPD&UdDC#uN$D- zU*QeFG;n_&)xB~K1|78O$0piiR|z6VU>*PzcCYjOE6#qy*zXwse0IY#{$y=F8ONQ>l(<>>dd zV6@|(Ys?*|%za^9;-6aUAUeXRJEJFz#xp9*KWo;Z&Lm~&95V*-&tJ^NKhW5ImGxkx zf%=3u^u(1(gT)FBfAYC)2RiBoMCVyZ5dSb6`J|) z3gP{9FYC=#EPa9ID9j5)X&W#Zfy+c`wMGv&nAd1tu{CP8(X>VsvJtEKd?OOXg>-+D zsA%89HMLYZ^QTL>NM}-uO^7s$6%J+`ukZ|Ds=f)vwlL}lWbf&kYUfpCU7_-Kt>L@-7ZQe+}onb^o;@84k}gV8V``yr_Pwn%ZSQv7NQ#Cuq= z4Uo27=URoL|4#Jx?`UW)E7abC`XkX$cv1bGs{RcYkAavzGg``uW6@B@BE>yQvC~$F zAF*OM5Z>f?cC9A3rj}kyb+)3R{jBiAR@9$}`X7txr>puUw?VuXVyegJEGtH#N6|%! z2bJOk7CUT%;wm8Ruxe;3f5xFc+tAQcR+tF|`S=A>NH`;;v2O0GRvS00*TIQP~#cN8@dMCu|S+N0-c0)C^7B*{A-VQW0krgWL zME&(x*0V+RZ>##JSv(M8dd_GzD{jGlUst4fhpO*F8gh?1GRdZqOzzWS5bCfC;pN;e zMC*r?&5T96aQs)?jg7mHMXh#2luJE#Lu9oZj9JXcqm^K2Pv`{m$1(o{^PiGo4;aUH z!$yZau<>L!0@qJ_@O`v^-*{W&DdP|{@RX6Whu<*F9}COlIYa+g8k~wbc%^QAxE+?E?^nFn^gIITYfjk6U9C}MK4o~ zukG;yy$}D6IghgCTcgDcz9m$l4{3R2? zZI>;zF4ZpYe3h##>+zXuKW6Kz1GsNMepEI3UjJOq7idfQ9&dg6-R!-3>+}4iSqu3- zE#rU~Xc^UHcxCZjs1(gYtBU5KO+|~)FwrtJNwf;RE?S2c3XibrqD`2;@C=(Fyu$X1 zb|Wf@_9ME94kNpWj^Uk!&!{h=YeW~(ZS;E4eM~RmJ0?){7!xi0@ut-`GDh@^+$91c zGsKUP_eJ2?&Z7U=Q6gwuZxKAMzX%yOFG>s;w@wTkZxDmV_Y{N2FBZcl#EY6|`m_6NI%$e>b z=1w0gVrMoH^Jj&LxY;Yjf;m^kqPdx3@x10DK9)p6Y=NNphs2Wk=SAXzs1UJyL7Z5z zAXOwU{3v!VvKPA+?Gw8f4-|Xi%ZSwYRFRetEcQ}qv5)qM^d-S!|56)qVCe&KFfm6Q zT9zvgFF!1ftXL;@uGlF4Sb1BVUp-i4BrOqtuK7b;So=j>UN=BoS$9fYUGFNct&bJA zHhd#8H(86U%`e2=sN|s{drP=@xaAj-vt^5TwB@eI#XpT6Z*42`wx)~xZG*(q?bhPi z_CWD``&98_`z}$q{h@f7Qck=|@fNRB#)!XC)`~YNSH#;LQoP$SQGD3xBR=jLBR=hZ zEk38s6<^Y~h=0;QON+xlN_iwsmO2_Ft&gQkn-dLWROu6oWSNuIr0uB(((ZJgG@NNH zjc3NovS(|`a_3ga@_%%e4jEl!g^XNT@y}>k>B2YCaKTSHUKlQ`UYIAHF6@%d7jDVw z7mv#t7hlPmm#k&2OU-2MOWkFiOGBi~rC+7%r7g1VrA%4xa(P+*a%GH>0xiau}S=s+~OBr-~kPN;ZCqr%@kOOW%k^?jC>{0?m5U`?|I0{_lC--dvP-Q z-T@hNFHcU%E-$BMd&+6qVRCx*5;-ILgq)fET+X^*LC(J4R?fLUQqH|k^0)g(c7OM3W~T=KAuT>5aZOnf+3E_=8`E`NAK zu6X!auFR<=SLJk(t8+%nq?{#kP0k^?HYZ1}dt@WmKXQ{B9`%+RA5D^*9<7m^ADxlO zj|$}Px#i`S+!k_cZm`^zJ40^I-6B(RFUuXdf6JYZoucHf$KT7{kB7@WkK<(O<5ZdU zI7{x$6LMc(9hsijP43V8Ssutsln3*U$U}L#^6--~^2n2h^5~O3^4OEf^7xZ=^2C#K z^5m03c`CnxJe}W4p2;5|&*smP=kmA7Kk~22^Z6fS#?xx@&!_F>g{NWi;?srl($l^2 z^3$lh^2#$ydG(pAy!OmjUVk=L-gvfL-h6gU-g=fNZ$Gz_na>-`tmpmYo#)Z=-t!GI z`}ui!|M@HVprDd`Sl}UZ3I@qX1#@I>L5h4_a9!pVe3DOIRG0ZLI?AUnM#^U|7R%=^ q(q+Mm*YZVS6TBj1*KwOzh@(-Yx%>nYLI;r{@Q#)^ah delta 13345 zcmZvCcU)D+^EPJ|Vg>HSUeOp8F%~e!ULaO%poVCy*dvOfi7hce>>VtOV#QdZqJRYy zjXfr6ELgCDU_}&c-TCot>SX%fHFRUMCj|-)&T8qY)no zHcIhlY}DjedyV4!XRuL}L*?_@KKUek?vT%pDfZ7t@>%47{nKN)QPXJ8M+ka`3htos zdcoZ_z6H!De?^yWE1V#ckF=L8hPxL6z1(EKRq6E%=JYEck}TmjvI| z*t!-ycdkXxu7aKjnkVSfbwGar8O~bLX&tbO#=e5xG!7G7N#g^+TqPDgUkQp4^m#1W zJ$3td!L>C`5d5jexq|C!?71HJna0BfztVUEFdN}UiR6s+MgubZ*=MKW&aLNSuUc$0 z+8DhxBX*Q18y|Gdel$49mTJ>O&m+I3D9 zouhWbzvgT<8p6NKkuo+zv2E0@zW{k{L%)MSc8R)MJ`BBPi!spXB|S^9+g78M#_qgh z9&}IL3VUs89|4$*_>=5tShtJYXrn`RTO(FddHA#m?oTI$J+I1E#_ z3hRNLbyZm94}+C$V-aQRzH^29(Bf;;_)v3S3%8Pe992nkM;?JqH92(?EbSX>xAZ!= z%ELb2^T+IbzoU?@rKMXR$HMG8YSdMpcEJQ;)jDR>Hfk@6rHY*S+$c_}HU~Y!hO9nj zxT)Iu{8#2Gzd>jEF~e7VYU@qvQ!&Y%gN_?@jXLa)ttVAS^HPOZ*BqD>sL1*JhJoty z=-*(|GhX?d@hdj6_X(q=;m6B``0^D^O8;(teW}S(O)d)YW4Av{5+KBvBQ-gvnJy>I zwl12?7vjsO^;gkT=2u5eW^3}hCLf(P+u92GoTm%%<6}aaGW}_``DhX@#E%c@uXmcX zIAeFiDeSOe7 zq$#h|bmJ?@FW$yS8Ny3Fr7<1i2!;vREG%Utgj?IDOMqqwk z6Uxp%G)fwa+4_%B*;-_0VTb)6z35%yqyJfr=2nM|rXH71{=?=&Kf>brq2y#O{+|Y` z!(lycWDW*8Cj-?rvN+2d;*WC>$0!7*418s{;F77@7~H215V8h5LZEzB*WT2MgWT!&qqPiO-g$EVRQxSo z$&i2PWVGdg*GRyIve&m5zwiHye&}why7WII%!ZRg{xX~^;Nu4i$-p~=cyXrwa>~;cAKS#$Gn!)EY2hOg*v! zN7SQQX#0|_Pmp<@sz>Fp*$}9}k&Va&I6&OQvp$3yb5IXpm+537!pHs(LaG146B6oE zf1cz;7Ow0?)p5bM@uJW8xG?JGA<0mO~-e~y9n?6QxsO1g2zu-RJ zR85{EZK+~(eR2jo{9YWhB{}jR-c%ZSUg{8x`r4bS8Xfsru-$@=d}KKK6s6)s9oYy0 z-+vA{abyE>Rvj$^%$Wo99mHPtR=NXPBiQV=^8@e$h4U8vVqg z3cPMK6+?6GXH>)J!ijUK5~mdo4b`2E;owhCc*Y zYH>saOkUcU-0;;n2S?O~oB4(9%VylUa9oY9gh0n5SBZW}C- z!RG62TR{V!y!LYtqR&BI1VvWs+EW3G8bi3C7d9 zU`Sl%Gd@&Og<^Q|7XV-OnopiYq5A$XPf#ca`64`w<5|8q8xzH2g%|_uj{DXZdo_`( zw!`Y6nn{B`AX@Gg$ zRN_`_ZNbTdf79N3M;mzgL{4i%^^GYyq(~T=!d`7*;}kK~=5$l|r?%8m$`5VHONHZv z$Qf{{Tu^hkOrZ{B5Gma`q#e#(xMh;Q23NPEvX0?ahXjsTNHvJUIjbEk2WL7*^?()O z?A6P5aG{_*#+t_K+QUDmA!tQ)Bo7_3N_K$Xq1@3GBOGdv5vC(6H{E$UFX})o)eM{f zbLq_18I}OE6>OV}bm)knG{Z8It4f@i+>uJ6Vsd^S_QH(+GuY=Jgm&DWICV43km!d) zJDY3!QC&3$XReMPPSO-V3_VwWm9Z3Y^Gqss+I|VrJl^St@IGJqRAI+X7-9jJ>qK>p zNcI|p6`k9SN~uVk!_+Tv)*`ueb(`dhmq#4fg2^%8X%iv?SZfSVseki>kri5BbQEq4JYbb+Od**_b1n7NvZWkemi zp~9JcyTP(0`IePZOYDoV8yQVnIv|VcwHb_)H0i603bMGZrr3NS$SaqRWzdI2Jt=4~C#sc(_tnHN(u-|UXLF(=l>KADqe@!tykGyvBU zi}%(6!R=GQ=3UIzzp+sHsvX(tFwdNapgH>HW^US(>KV%=y4vo*oN$$#G}A6eKGY2XZI$Wfa`4gA9ZhE3 zecB0E;VMfQ2MtANTZNEmI?O6g48*}*Wp!An)vsd5ub_1eH~0!sZY}rz3Rg}XF4TZ_ z@UJ+%yeoaMq;V3s%|zuRe*F~{hZGK_q-c=pg%A{1z;)uZ>ul)--Fsw)dRBWZ?)q-t zql44f0aTc~^(JqXWT{{(11P6Ol62%YMd}Qu((L**RaD8A@*L3zTU%C3C3E=K)Kl%X zRMEEV<*cPtL9Sg#+H0w8X1M&M4~FT|2cd7DU2b0ixqSuXny3^@S*W4`ku$0o1I$$Ybihxt4fFA$em{#%r znAWfML4PeU=&uC^EyU~kL*qe=Wj;*)9!N8I(g3gyVZqF8IK)A6Ri6%`63C`)tjs}J zt3x^?G!2_F5Pc5IDoSQBYY>uL8bBV#VXhYh(Zl+BG(~?1B5&hJzE-O`VoNB%G?O|r z9XujF5~z-128c1W0c?XGWpnVO1qR1H`l>UKG{blJaJcUoIU6XZ4u*@Jkv9$E*%@4* zQNs~Py9_nCW=I+vA<^>;@*OiAG#!r2eBlr($peQ|54@Ci52rp{c?dak#SzqjHw`6= zaaJyJ9VyOo)=;X!qeq}yxnbzGWCZo#@L`aDF@n1BO+nqhp&<4fj=bl*OuG&UPUI&p zeg!Ye^Aa;_p~*~Y%+ppBTERf_Dtz{M9p7V4hvb2sPkriG>&KB?zv2(&mDvuulqDI1yG#z!W zj-;~qE#TQmOy>%_2UBDDH9%enW2Yi4P6|fkxS^la@(B5FQgB1(HL1bmZlp^vtp#Fk zShG>MSke(!VjE$jMvsD)bPfu^ZJW+x3Smd%La@8(99xKL5v6n0#S#G<;+{Fw$ds)& z+LUcQ#w1AgYCt+pm>GJY3>nBvW&CH13_V6hfiW^{V`TilV`Q*7Mh2T>WJp3;1IibV z0m+o`u011Dmdm!rnOt-%0^n^)LnOm6ug}{^L(D7(znrv1to~&zW_DZWNog7*1*zgv zxOBmt<+bIpFzd$Sm35;a|F)P}Q9t+=5g{YIEpG^%>PkE@*wl=dLtPATUX%Bs)C~pM z${a9`>Y)rjFyTU?%b+TG0iG%xx)BzjM{ z+INT`&p7ZqT!PPerjQq$1j216;5L8x9o*_KE=IQM} z3F+WlY`M93ZzTd&;`tL1Ki*0}GCQCh)grl&-*V~682%k%;j1 z_u_}OoCxd<+S>OV@dJ_rF!pfhL}aKy`Z)sOF*!)A&Bc7rb*EBwQV#i+TIECMZd1uk zKEzD32=AyIV5k|)-%Uj&25puf5fMPe(tMdPb28R~lTi*!!eurfJgLF6@0uYu&;lR zxXP(YCJ64`58T^2RPUXpH9r3^m1zh!#8swKLkwkf))`8dZ&49Z#1Yd?D^UkQZMB9d z#joRfS%}|Hhs!$IGBsQ$mZ}B3Q90pENw(rrFfb}7UAYtwcd7Xwaj6N|uBG!c;QCIw z(qx{6cVIx_1W{OlU7Jy1f~E#DalICm%dG;RhCB1>nbaK&^PyI37775xv~j2fR{};D ztH6_I;YKW`t=K*b4~k;?y>BXTnT@kiOg{uZpN+{DmuXfq20|JgTJd1%*#_V=39olkWgU9Ao$3vP)k&zKLFu<#h7 zPf1yHreT`$dOmEkd0QZQSR9nn)eql~sfRj=} z5(K>TmZEN0VIgwPl2|Uhjwxd10woqfpp+IUr3FG4 z;T9^zQH#*0lwOjwMO4wTl)TST@2H91lXYFLX(TEGr6s6W;8~IIoYLAuT_bUzfyI3v zMnX>+c^$fQ?lQc>%Aks(qedAX6J<75ZHFo2R|ppfB3aU|;iSq)Ays0f%g+V3ql}Ie zXw{Lz5onLBlldHR;uVWgpDe@ii;=vxSxQy7{t|NGaZBk_UjGI{Name*&Jq-%%gG&8 zg-o3Dmtjd8xKIR{mp*CJ!*F8Ov8W|@ysBgI;Q+>WUH*}gqt&;#N}aDfA7rG#UoXd$a~Y*LZ_Z>Y!&R2! z>^5NU<+!3RFQ>9@&pneqI-68@rM=Lj8nO|CEIMX6UId;i(B+t*KtYcM{UoT=3ao7t zku1Z$EAVW%vVzKT2vBqkK#Z_z2|BR?89;YIPk`_qK^G6+9D`Sda|{(L{E0cdb9Fuy z19L~lUHCKUq zL{JYwxsXKh-!!}QD&S5Uw^}7r5Q$(xYBdl88C`YzG2wnG+$X~I*W3!LG45vJwh?qu z&}bkO)y)y21^3kW&}wM-Y7HbF37RIT%o^zWO1FO@7$qWE&@sSVXe}gG3ioTx{atV$ zjbDhwY>{wZi;;H=>aZ5={dN1df(K~44w${yLE^_vuqQ}!Hv{vmby(fsHsPEP*4#In zAbU+@JvKvjsOGL+2ifYe_+wd#9~Y-c({QuNHQqDHIU(P5Mriqyo8fd@Vxg)@ER|Iw zEuV4ESU7bsK)8TW0CBO1hokvoEFRe*{6@$auD%{oYb;uOtVe4oPgxK4IL_LD-{z9m zQz>ruGyY_*$Lzk<+`__G{xin%5_ClV^pVdTLDL15*nmHA_%tT#K9{9wsBqs2_j}=% zWDoh1ya7!Cf-(h75maO&{;ZczZ$YPlP}oHu4x2cRJ4l zL1DHYTQ{NqS@bt%@*QcL#jcw`W^*$T)L`p#BF>cFqq%w=%{^+e*|tYKXfyUjb_j)6 z>t>vyL}8elb7eE!X7XlSxsm_BeTn+8FQ{a~$4YbFW^zT%F=#85acb(BRJa7s{{;uI z*)IsbsOt&4xo1*Q{6CPeXMxRywqUsJA`oK=xVH98a`DOE{FNq?Uy0~s5p~}J(bZa4 zCx~|DLt9|xr`xC~2TR*p-PRSu|H{R-Vw~hHaI&Ub(K!4&`9HM4RtTt*mInN63mo~pe4T>lXT{@II*oMBWLHc8`%l}K zH43}pNB!-S%_b|NghE+StiQrYN4m~}y0Py?7ZfyteP zd&%TFt%R|${7`x=7lE=nA#hLxu4sXEo=L^4ai5(KD7q5@b48#&ka1n>4HRygaDNc) zO_S@o5x_HmwOsc6ZPqsh7<$>m9qQh+G#$q(Sa*jiqEXnCf8i6#7^hCIPe>*L$o&b-hLEf-pH@-mH7N#Wc=k0zyh=% zu^IM8^6p9;xfBn#H)dJS_R@Nz3wu>cQxQ^clFuHX!H!{#MwX|>!HSv&SE6RYji`C> zC~6TLOD%)bs8#S&YCY;>@)^~Wd`HcsFGlU9_M^*EhtXZBV@PN68{x!auaK&vp6mypjue?u3Rvn_Ft2fZ@)tl+en(K6S-B3CgyPVFi zKTWAWzoSbV2GQjWCn#;BCtcaNkZx?MM(Mv4p^Pn0C^Ky9aJn5ghVI2pq5E-h^dK&S zvbS64;dWoj*`7j=cMPH2_#%`S-;bWePorn?yXblR9eR;ag8rBA1^tyUo?a&WOn)a_ zq<<0>y-NI^-t6o|Z+DHSce`KE`{a4bAtg>3DQ^`W>Z_a%N2;Pn2B>03Q&jQe^;DSi z@g>UTw<^l@#BF8yJzKf`@tG>|$0SwqWOY^Q)M{1ww4W+-rn4%0=DsR-He8iIS53K{ z>!B*08>!sSEl^d@?NT3~yQZq2Kc;G)f37@Ii>O+ujg@C=H&r`znEEtzs;ZM3r|PEO zQ1vgAR9+WaDDMlyRD%nP)Mpp=hN*@Zvef4ni>gK!8>q$?`>G}vXRD?ccdKR>Ggb3T z#Z`+-4OPoa{Z*?=vsCL#3CicvP33#pNquqIOSQS&Pqn=~Q?T|7$>U(Xd>UV9S>VGXo4Y+n+4ZQBAg044HgRT!zgRe)b zA=eM6q1W%JVK-dV@EeWPh#URXH#erKkvHO1@QoX4)XhR_^v(JzcF5N+mPp_rE4NLE?zDxgJO-SFMCZ?ZJlhR+R$rO1q)nmdVV?VT%X-JQ28_HGTe{%&XW^WAZ3!`%AY;wtMSU+`T{4_Ir71$NiEj{(e)HaDSjmygyUzydS4_-M^rA-~UJL zc~Ch_B|T`Pk{^szdmluqeGigU%7dF~e>SND*&gcG?5^ry_P6R#c8ofleOMjIzORlx zEUu0{^j60o_ENt+{862FxIz8?@Ra)F;Zt=or?fhi(_Ed-8KnNqnXS&`>`-TOE~#@l zuhscSRaEMucIv{TQR?EO#p=?dz3TF#und*<*il`1?5VCk_E*;)Pf*t%uTnQ2A5}LW zXRGvF7nPCwnYxwxwaUy5SGRLFsXMuUs=K+*)xEs3>V95J^&oGE%Fdgs9_A&eoV+yk zDDRDW{N!Vm`=o=)dlI6aJXxxqK1or}p1e@cpH@^ap8Bf4p8ik0eAY?5D*QZNz5c5^ M!tst1)TPw_0YTbiga7~l diff --git a/target/scala-2.12/classes/exu/exu.class b/target/scala-2.12/classes/exu/exu.class index 3db0817c9896453253df54f3022b847938e59c8c..9d627eac3dad52af572804b68fcfa79ace62c901 100644 GIT binary patch delta 387 zcmeydjOWKPo`x-q?7fUS(>Zz>Lm1Vk$M!P%F`7Go$BxtJdb7=moeVDv%~d@P_j zz3?<+0L=EQr-3F!z!mT?IzwC-e}>VWF$gZs#r#ab79#WT3}YCh6_U(z0jRHv&N7xT z27+WHr=4T;0frhlG_npb@-n{=P@GZz>Ll_OG$M!P%F`7?b)61yKsJQ)BFJp@Wqy6-YGZ`hP zH%wq;*m*B(}{-gqrzCY^GBP@zhg5hbDlWBsJas3?mowBLOFnZ5fQwNP>?Atfm*9 zW()xO4D6Dtr-3Gf!xiu_g7pYbk3Ylc&gc&p=VE>a)Ckt`@C;)ZqXUx6a{;JXMQ0gH z7?VIUlGDyH`Y>8RLL=({BQNs{0i)^V=NOYAE|i@9I5A`~I5YGzxG-#BaAmm6;KuNV!JScn K!G7{lSi diff --git a/target/scala-2.12/classes/include/ahb_out_dma.class b/target/scala-2.12/classes/include/ahb_out_dma.class index 2d71d62897296f451460e69d5fbf4c1d49d827ce..36a5a7aa402beda9994df3d64c14e19dc8e37aac 100644 GIT binary patch delta 116 zcmeAb?-k#0pPkWUvLL7E6HaQATnr`*dJLuvfedC0Sq$b3y$lu%8yGAZE;Cp$ykW3r M6ksr({DW&M0HLBD%m4rY delta 116 zcmeAb?-k#0pMA0nhuGw=?CO&vfwU2a`s8UqIv+@12GVPQv;e2rZ4V8w8m!J6R>gAJnq KgURF{TvGw0Y#xgM diff --git a/target/scala-2.12/classes/include/aln_dec.class b/target/scala-2.12/classes/include/aln_dec.class index 6bde25b96fb6349d9e74f31e6634ad9950e3bf88..0363a5cd0635fff3246530add08c9ab7fb020f97 100644 GIT binary patch delta 39 vcmaFQ|DJ!tIyOe;$?Mr{Ca+@?o6N|b#mmIN#mLN{%*evv&d4;mg1sC7=|Bl% delta 43 zcmaFQ|DJ!tI=0EL*~BIvVN+*hoxGk+bTT7*7B4dc7b6RUG9xR4J0tVt3ifgUGRO-9 diff --git a/target/scala-2.12/classes/include/aln_ib.class b/target/scala-2.12/classes/include/aln_ib.class index a7680c85edf93f9f873e1343a28d123e9dbac385..2176c40f0bf76b41fd08fbb3efbde3b7892eb3e4 100644 GIT binary patch delta 3486 zcmYk;c~F#P90&0CWhS*!nt-1{2G+gggV>o}gT&!V};gm*4gelLOBP`C&Gm(y2!>S{b zlxL%n_0BuCs9;6EMU`Q8XI0UB$>sSaTsqE-X{lK8)6i*jQ#jC@O-aivI9 zY>$zDF=vfY%IEAD{+Su$=+9w&F)Nf=F7{&!O#D`jNyRcvK05KuZ(ptrqAwGzLAFM7{M;J9G`2mrT7R zs1f=}NH)`MMl-dmq3@taQYc*wl|lW`BovrRH?}}0pqr3?8uhZE4xzy`+HL+@)JcY# zpr0YlTI$6>HPAWe(RAv)29-mnpebls2HhwWYR#bC#*qYMQYRbgghn9mb<{IM&Cq3N z_Im1>AS-kpnwdqt5TOlOwA*P)tl3lvg0@1RKogKIhi>FRUC^JV~chJzhY&r4~@z1`R`= zn<$NiYN0{Mbu;z!P$hH*a?Rr@B(wtw+p!OSz2h#XxP)Jt(}KdNybr zdi5Qink%*JAoLd$TtTT7x(2;i=}7r*{0+Z2XD!q1qI+e~MM%4w((TX%X#O5bH$z`R zbN5o33!Q>g`zXy2s@X@ox$dXL3>}B2S5X=d*-6%F3XRY)=q?miL%kO0CbY^*X}wUt zl~!BMD5-(2LW^rD-3<*x0q;^;3jGNA9iX%bIuFgOqjVGWrO;R%?UqwdoqovUAU#Wm zK7(d8P?`+&LemaW8V7YlQ;?yNdPkuCS`A%+7TGA> z1r0&|t(2BPKR~{Rc^Z9~b~`6#{!8KY9^ET|&O)9?D9wiYAort`u7yrQGmlZ41bqZO z)JEwVp`C5C+a!|ccIq5~ZbP9Rlr}-5&?}vk9)PY3@&BaWoWsf)(Cx!KyVWdPIb)TxQ#osub3{1@mDAhq!(8oZW>!wUayHwaW)*e~yR6J- z?Cwm}lc9XS$9hzZ^&|-8i%<7n%ljSj3lox?bW2(w{Ub$4x21IHjCbcCZ$rEVY#T)OehLmD;6hB5v@!OE})kSqLi|kh{_T!h~iCI6iH?I zNO0jorh>qw1+{FN2^Ggym1#;UsAgP9r)EIJErrfG-|u~=f9~^q-}9a`@7x*g(9!SG z(eLtcPPjTKRJ%z8MtF+aaDSY-!)Nk+m}bEiZ&4HxVc0Y=!eTZo2{VnBP?6f~A?{eF z7&qRcH_}7IM#{IzQ^WsG`n!WICNU$*0y`L`zgx9?i=im0*62v>&Jmr9ndcYCv$rT; zkf`1DEvUgW^$TZf_UFPPK6{8VtG=Tn+FNv5m%v_&S*GpjB~HWy@T9wNwfP&{&#{FV zwbZ6>aNf31`y3Oif2POk-+^i$E81gUH7r0(j?gGa$D;B$-Q{Zep0cp3DJ zm)#2P0lx!X7t1~uEC9a(AA-}D$hi$*8`uZFkRbaiumQXZ`n)OoGVlP{1$w^^D`bxaE5HljlWDTQ0TzR2 zz+rIaN;#JYo&*QLpmf^axN2W2LA#lX33rc)`8vN*lgJsfdae)j($h>2yh430jfE&&jL4tpM!&7 z$XYp<1-5`Uz)9<5PX+729&p@x+2g?~uoHCKAiD)D0ndRhxw6j&^TAW#9dOD16YLm+o@ezGZuME7feavuvhqRMXkMWP7TBY6{y4HrGPE1{cz9t;Sik zn}u3L&&9GeusvXlDyF%5wgI+z+x41UVix<@{$`uKgK8z)HMW;aWYu@m-|#!mW)ZxT zo-1Oz%w{g7x`pi$+l2S1ZeaU{?U`Lvv)InCdF`gU(y)r%w42)=D#>ie*+!O8O<;49 zRhCnFk8$)nmfXF z&oG}_+Raf*GyQC@JLs;O?Iv4T9o2HSD{NEisqSR!W()j)Y606%Z2pJzYCS}|T`M6RMW>pozwlU)A))egaGl_QbXs;U+# LgKcr2WR3g}SNv7V diff --git a/target/scala-2.12/classes/include/alu_pkt_t.class b/target/scala-2.12/classes/include/alu_pkt_t.class index 865ce003c616302888b56522688d1df3b73dde23..63a8a4d84ce1245b71b8b532677e45f9fa59e1c2 100644 GIT binary patch delta 267 zcmW;8ElWdT7zW_ye*Bo{eVt>7r#XkggW80xTMPzqb%;@x7WM-Sf)+77pqRy=MZqYT zEL$AIEC!Q5;Oy+n`@HG8y47y=bth5`t>M>fKiX1cq33x=q3?Oep=sVpXw9+H&`#c2 z=!;8iH;V0#w&=D`?2(?)ANoKyTx{R;gsv|qc2Ar1i{8;yAKQQ)({eGf8+t^0K7P9{ zKB19{!%!;7WDg@bz*w4?NE=hRz)WschP`MMHmqZ?u%N6i7>$O3b)cX{+X4LmCM^m^ zVQJ-7(QY#N0c3`GeADw(?W+B}m&k`HrJr=9u%*n@BlT6iQGe7*?V66%T`5y_pgx%( z=dLB+>RjEmL4MT}^}x5}UOiJkZD1#3yD3{Pu#cPQ(zrWa7Wb}e#^pY69(SlK{`Ye2 zA9%bX1EOs(?E^H#8ck56Q>@bk>U4_+Jz|6ANaziQzF=ty$03;;=|29y8* delta 19 Zcmey${FQk_EhD4v3;;>D29^K- diff --git a/target/scala-2.12/classes/include/axi_channels.class b/target/scala-2.12/classes/include/axi_channels.class index 97c7a1d3bb9356b089c7c46d09499e378f4d83db..22cbcddeba8c0a130141259de4d36e3aa9740412 100644 GIT binary patch delta 3414 zcmX}vYfzL`90u@BCCX}w>xw0~ABww86PlvVgxU-&%ibUX5s>7fC=_?Gkc*_E0@@J) zFBG>#E(X#}rG`3Tnpq!Erpq)XT2nzOJ56aO)q4*6JYU}Tch2*icmJ~k^Ue-W%ov`S z(f>!}114cJd5iuiPvILC;9Mm~E#v-jO;)2`xEPH}Y3jOIj2qDoj9#kkIeO-ZvglAv zHdBxojh;?}M1W~pvFe<+IBkk{YF>PRn zYI}K>ChaQEOj$idm^DOOrCF=FC#Ur@>xJEx=+q~+6ioy1o??+bkUe)%W0!NusW02* zQ)J_jSUE>ztW~=r;^Z1RH{tE zY*(2)u@;>eYBzO}nw5-R1htJiP2Hsyrr<2>USzA9cdQTL5)$q8R#WZP1Gpm zo{64?+Dm<=#juaFv`Zc)J-(c3_EQa32SZ1mPr%}VF9F`LIG zbgWb@b(wPAjNU4$k{Y7^p%&-hL=kn8x=n@TqPJ0Le=cUb$z=Yk=p<8zsIMr`*U+<3 zb=2q7LwV@EL{(8|sr%HDe0d@*AF~arwftY0q(Teu)NJY)^&@2{L@$LpOnpsx6`^OR z>ZvQ#!^N`qTrpwmP)G6w*H;}HQ2B`S)PIzH8+x78T_r;~W@{-&$3d;C zz+NLYPA#uQx{ta^EviCVLw!d*yB%p2HA)3k%hXnl*}hb3`P~}c#JNK1A~kmh(j4j> z<*^fKrcz~1kobstbeBx!UMh8xa;ZU@;FO$Aw*O^f+l@{Kb%!$UL3)&$q*m@ldXV~+ zT2_m+p1MITtV6m>X`l|XEvQFQNnNA-_aWU%eL>CNkF1OIIOf@-NTrZJbM|KA>j5gEX1yr)IVy zT}>UQ?o*aF^xCLDsmOMj=CxzCTWT$5i|D|)1Jut{cqh_Y>N@rOyGVCX-%ugPkd{*; z)YDx^wtb|)I$j4PB7GpTUFni8y3EYuHhxjV=r0irBsg0i@PB4EVgg2rJj zMcGQ>Vh|r(+eT1pT2Ve!R$?DiD3dA0nylXUJ^$zV^8SA3{GM~~8HTy@4vxDIj=T5$ z5#?qP4zrKwi=HL?ql2(YiC)V45vtiu2H{~c>6WfPUld~|nhuUxA_9ASMM=y8{ghFR z#K>k8L1t;O`Y9iA)*J(yW6?g(VK#_Ti}r1HlaCm-m{kj~Zo|6QD%S?#X-iZ0@@&oO zQ#J}_qaoQ0m4P12{Wg_ElgV_%%2qLH1~{ z5oLC`Hl z_GRD>@Dz9#d_GmqZ3123EpT3%?CZdz;E$l+8rc)TdhlEDk#yN(z-n*^bYCm`%ivD% zGg-2(0bFM?Ay${q>s0?&f?!SEb8mk+)V z{t5=?%AN&wfY-n|n`B=NHi1__&&{%1!M)%m&?8Uw;jG;VwTh-4){I6cg&Jy3M7% x#`nAO_2=W_rQQ_XyhV5KfUiX{C{`s{u_=ocyOOLplpMvW)GC&NttYGx{SUL#ye|L% diff --git a/target/scala-2.12/classes/include/br_pkt_t.class b/target/scala-2.12/classes/include/br_pkt_t.class index ddae048637b95e24f85919105285f5a0413d92de..4855b61ab84a483bb365e2b727eeba0e998b9a74 100644 GIT binary patch delta 117 zcmew={8f0vW;Vw4lRvVFPCm(|&bR@{vSHi^<~y^iGj0O28ran*Z)OvlycbA+0MfsJ zv@W~YWOEMn$yq?UgyX#GItDJr^$hZi8yJikH!`?0ZeoaL+{}>AxP_sGaVx_N#%&C1 L7}rhC;Oqqe(TpdZ delta 121 zcmew={8f0vX12-8*~KQGWK*B~1W2>7t4~(s5S#1_q~m~e1G_ro_Q@aFL?`bBvUY%3 zzksZrV3s+DI^!-dtAyjc>P7}G#?1`!j9VCt8MiXHGj3yuX57w@&$xr3g>fgt48~my MYZy09&fx3?0QM>oAyg9mqNYWG$22$H2vSfI*J& aAcGO(AqF?b!wgZ3M;P)L_f6i%UIzfuiX5u| diff --git a/target/scala-2.12/classes/include/cache_debug_pkt_t.class b/target/scala-2.12/classes/include/cache_debug_pkt_t.class index ea910e043db0919d2d1811c0c9ab8ac7e24a1ef4..e98dc733e6647bce68cccd669244b56db28a7aae 100644 GIT binary patch delta 69 zcmbOvFiBv81smgr$sgE6C;PFfGj0U4x`C`sVAcsBYcr5FMRYv_7t;m?d8UmFCQO?c QJeW2!#4xR&Jd?c=06Fj$#Q*>R delta 69 zcmbOvFiBv81smg@$sgE6C;PFfGwubmx`C{HVAcsBYd?@RMRYd<7tH)GU!K{-&RuzzC!&nXG zJ9DTr)__?JKvpf7wU^_eW(flqQz?TSQyGI1Q#pehQw2j5Qzb(lQx!uKQ#HdhrW%G- POtlRAm`Wxe=bQup?T{>U delta 139 zcmca9a#Li(em2I2$sgH8Ctqb#XKVzsgxJ*?o4_o8Agcw;>H)G^!K{-&RvVCI!`Key zJ9DTrc7Rz8KvpN1wU^_eW<3KJQv-t>QzL^BQxk(5Qwu{BQ!7IrQyW7QQ#->nrVfTx POq~q-nCd4V=bQupA8RdJ diff --git a/target/scala-2.12/classes/include/class_pkt_t.class b/target/scala-2.12/classes/include/class_pkt_t.class index d003361fa45a400ec20bb321fa1d0b5c4d89bbe1..7e14e0a1b74262c3018dfea98a08fd87e37e36e1 100644 GIT binary patch delta 47 zcmcc4d!2VfBrD^a$x*B}jBh7T2a@k5Utz5ie9gec_=Z7_@hyW9<2wd7#@CaR*-8Ma CTM*^| delta 47 zcmcc4d!2VfBrD_R$x*B}j9(^C2a;bWUtz5i{KUY;_?bbD@e6|y<5vbZ#!r)z*-8Me C*AX57 diff --git a/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class b/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class index f80966562dc52c6858f4fe4f0473bee1e187bb00..88513b08c98c94593fe178e8e4cb88ba1c7fb58d 100644 GIT binary patch delta 139 zcmca3az|vtAvVUw$%Y)FlW(x8Gd6))qU`F7&0tm#kktZa^#fV0VAdHRs}0QJ7Nzvw?w&sgXgBsfodeshPozsf8hmsg)s*sg0qDshwdOQwPH; PrcQ=^ObwGyaZUmNyyhm8 delta 139 zcmca3az|vtAvVU|$%Y)FlW(x8GxmX5qU`F7{a{uQkTn6!>IbqWf>~#PtVv)NCx<%Y zWFX6iaSE8<4CGG*vkq`P)a+s4V(Mj(W9nltV(MpbW17Ga#Way2k7*J^6VqgdX-rcX QRxwRw*vHf}`4s0Q0Pv0{g8%>k diff --git a/target/scala-2.12/classes/include/dctl_busbuff.class b/target/scala-2.12/classes/include/dctl_busbuff.class index c848d5b4fa06b576b4e9351e557b8232ac04fa70..6227e042e76608d2459eda6a666b227a50a428e7 100644 GIT binary patch delta 3431 zcmYM%X;76_90u_BVv|y$hAdIkObEkblb}wSvd&QKJ1B_BrlFv~r3BQAN`O}o3pk*- z0oRfpszJ+`nhBKLFt|2Tsi|$INqsSD&Y}r)`p@?;{_8b(!7!_>djiq*JL zMxCVYQH#>i+eCG1GN)s<1#8gBq>fToDd*SFOQssAFR91Zq8Cn8QzO(v%0B})wrVnE zV7B{Ad^6G6O!ZK=DfcY&vZz+-8ues0dMQ*RHBQaWK`%m+J_oa%M$)(rl>llR^)WR~ z`K`x|0;-p~LwUT8UN+T6eMh!M33#7JFr>H-u z#d)|EyOqEkZ)B|eio4BE; z2B=BOYYTeosbkbl%C!W&G))yHnC&Yj^GeZ)p=znK)FWlG7n0y0g3BylT|T0z%<@I$ zBW_d6x8iIc^*yy@8`9m>73%rzNOw|~DGvkEGOH5RiA)9`@oYH~J#~h1-hnia`iz>l z6KM|h5oNmz=^E;N%BBKo3e}~_T!GnQ-$KVkO;cf&NDooJQ^8e81@#N{ay8OA>L#^# zH_~eATTMEnoK0u+5j%{sBW0%C_u#CQxtC&s*|Z- z9cCNQ_Hs7eKHN*DI;p>@n77eur|wg)zJv52^&1sbkF=4xMJ;QPX;uSfyP@snY<`Wn zS4Dk8`3R)t)C9Gl326y+o^owQT1bshj{A{r(A2OWv&}hxB#Syh&1^xsn(Bud4=tJnWQTM1<4kK;RG<+DN1s*}tK>bX;bQEbVb)E8UMOsOHO?kH=HBjS}TRYM% z)HzL4?U=2=gw8PKa13X;)DUI&F49bDkb3kzq-j(i^^i(Dj^1(VPfgEtV7Ar{bf&1# zPMjT}?ot6=Nb9Mes297D)@YJ{rC;mz628e!!llPk%;<3vE7dhvU4^=qtLuci4ymhM zucvsRu951xwAV=()m7i?AVzxS{~2z5#p<(JJ_l#@hw3~=6?^3iWubCbNl?xydCGaE bUb&!jD;Jd!WlXuFT++=}MhEo+=`;TWG$AJ^ delta 3167 zcmYM0c~Dhl7>CcrCZ$9jwi{*5gb;9RlEo=gHfK!WvagDoY#NHnVkxK>mjDsM0zN?8 zfNRNifto?hn3@SR+>pg)DmAsqT$1_&rL1Pk&N<)jef#G;&-Xp=xxB+4cka-*-O#w* zr;g!{cCQo6J|DUwa9*b}lS0f`~fl=CLTP;S>6h(C+DoVWzjxNN^P_#T7g>Oun zdRHCOh<8F`LsZ)pTgqoAF*nYno`R!|q9866_EX#{bx#+O9Ix%K{k70oN6{Ydt#5xT z-e0e#1Z{)tggEtiN`KlXYX1YP#Z9CqF4E0MTujv7auxPTUOJb6CE!=!Kj4C7IadfC z2PeQ+Q)FKcwu84p_ocF@frr5>pzAW(6Txcm68KcA>|tOj*bn{-E?h3>iog@#190vN z**Ab4;2m(zO4-xFBj8og_?GNRU=277KD|ozaIg#<03U;aX>x8WcoKXF`lidi5$pu- zf*u*NXMj!MHSn2C*^|Lqa0Hy5C3^(82RtoVyISTTa2xm;I0^c#k#o7A4ZH_>zAbwu z*bM#vx@F6r0t#>xbXY6987v3SfQEIl2ZP(eQ{eBQe~z5X1G~Uqz?as`o&~mm*TH8u z$i5V;1ING_8)c6K_kv%8cDb^LfEMs`@DDH`PtN6o-Qa!DD_{22pcT9UK35?7GO!-J z49?sndlXm!4uVtOkv$YF2K&HA;JkO`Tmjevj)UHtWnTjx1#g10x5%CfHh|xNvkGO8 z1}nj{;1fk!cM+jQ@~hA!>WbtSv`O4$TdH;eq#$Qr7GC&u)R@6wTkT~oBtlFWo+N;W+>NoGnAXej&f~AvoSW0y>wT| zc7g5r3aa^Rr`cR9sjg%Df^FveR5RI5uuZGds$UiD)}x=b-3KBRhp?N_#tYO1wtx7p^`Xf>mTcDtdUwcY$`>Ah06@7PR&YBAd=+nhS8TiDLC z&90}K$2P#`(m-{sZZ!?G+l>8GGT4r@O>LyQoUNOz_5j61wpO;k*rE>7Tr=APwl@z^ zZPcy*5Umz`m`V-X&up(Bp<2myoz1t2Y6;u7Y(C9YEo>uf?k!X|vz^mzqJ?(LwbD#K zoAXh+%Vz6ibNGmAI$JN>lOIz}W$R*l%$9JB=8m!bsoRUKv|Cdv%}lT@Zlk;XZ1>rM z+NoBv-C}#KgKC9tR*R3g*5NHe)!(LWonE3?Ws1r^l|tnsm7^->*<6K#%}W%hG^^~f zIg2uzk6~CWigywNHtiR-d)FrQS+6~Nr*$tjcn&I#%30-Q<(v|)oL6#`3re+eQRz^I VlmX?Ea!(mHOjibb3wl;e{SSTA)@}d* diff --git a/target/scala-2.12/classes/include/dec_aln.class b/target/scala-2.12/classes/include/dec_aln.class index 70f2098d71cc4046f1f59a4cf45dc664a7f213e1..06c24759f7ed036f5f1e575442d817432c9639e9 100644 GIT binary patch delta 3371 zcmYk;YfzL`90qU}8v(N^kc&*2Mk zMB}2(6q}iSNQtawGOZ|PLTd&!N}DN#G(VtJ?|FBhr@kD1=RD7O_s;;!TE-kLV~zul zhihgEtI1Q0hPw-GxSxGz4iDw|8bv{RPZ1CiW!FT6j~Iwp!d;}j8?Rlhs6iW{?!82_ zZjPAN+Ma3K8Fl~d7QoY{6SL{WqG32`q*P9)P6 zvGR3?Vm*X8R(>Btu}1seH_kS-x5$YLQ_ifWC1ON9n>2a|H>0m|CKX53Q(xL8pDjCU zx=6XC%U*CgX4|9g zrv9XYwxE|!olrHr1+zW96`gddle$8A<)D{HwNPJE59gw%r_9u+)IU^c z9&S{q>dwP#cbGhrk4^z~lDa`HEI==VIzs(O&E1Ax64gq5L(SffoQHNU7~v?!r)N`{&>< zI!kSD_x@snT3d#*HtIJjbO+KV>N@qD3F$t&5|p{DCV#Q497#1bLitu8t)wnd3o4P8 zP+w5quOZE+1}V3lNH zdXT!Q%C!cwHP)bWje2$u&g!TuRA4RAD(ZV`u^DLvbx~DVoxhmBSEf?M)aTUPI$J7d zlbv(+y}xkXhkM!78EV#kq$$(@HRBDW>!}me11j!K^o~(~QTlqB7S&_6Tk2j;8PMFIO3F%(yG8NE_bT{=KwWtMYxvK6K%=Tm}k|OFe%1a>4rOr~19YC5z zeMq?+M4C*!M>)13O``f$4Yy&o*tgK>rtVU@Lr6QQKd2YmkqYWpYE=i)dTNYXei*5l z8dasSV76TrbcU&goj5a57pQqhkQP$sDbFsXIn>A0qeqcuQl}~BZkYymW43qIz5IRC z9K*dts*jqYVveJCl)6J{-$vR_{Z75mgS1tZ{Fpx8<0mGJp2DZsSIqA96luy=L$AB& r=uJ~5o$4)C)`C8{UhS)Jo$27FadMcaadz<2xHu>u^-tyYFL(ME+pK!F2f3djL9?n_DV zAfjcDexy`ZGZ|JEQ)tbQMrubtyguBB_^cusp z9fN2yd5LMGe5za}oBms=zY%6Oh)I+BgfMe1?iw&txnov;(`2zK*AYvea`lg`P_A9E zdz9<2)gXEkJjKemP-V3vuKs^}i{j@gtNi#9#hMD-Zn3rLbD_Y(z4QQC8Y#8{Ggudnb-4$zncHi4gm_ov9d46Ff9 zfVaU#sdBCi90sp~^OnoL4(tang0s?O&jh=`??A6~*^|L$@HFU>A$v4f3!Vh;fX}Ru zbLHT>;59Jh1=$Ng2lz8M`$gHaz;5t+(EBCXQ@|GR3($3?>@i>+I0D`U7iY@33h)Rx z1%_tHUI-3=li*|7vS)*P!Ew+hNA^^(6&wZKa%DGy+rSUOX)t1yoU?-Of!D$Ld9tqu z2f<%J|9shVKs$I2^j$6ca12>NZ3 zJp&Zr*WiO?YWESAGWlW*7CmM1B^NBF*p`*kUMJhHY>^dITiGtMJ#D4B9hRz7U%|m* zekGM!wlTJVDyr3NXV_*}Q{BY&8Jpj$REyX~*gQ8=UBmXiW*0Wo*|J}wnPIkjx6s}S zw!>`GY{^?`?jYMOHcJgvJKHt3=WD6%X1k)9M;)E5rH*DUusyYn_8QsFvxU}Etzr9? z?Fk#zDz;J0q8fw6tOm8Jwvp{qwi%7Gs%KMYPGTJ_Jhsz)tJ#jT>32}gVjE(+XD8JR zwnJ=p*^*wTxdUu}v6-9HTG~WsyQ;0#Q${t@eY@B$vqiK}ZD#w4ExeU#1KT;akT$AY z*}h?$+fKDov%YpZ+oK&+O4&YPGYG1MY$wCb9!jc z%66J<=02(=Y^T_Kd#M(%eZcn6eyVwFN7-Ea)ViRL&i1ypR{!602k5>uwgI-=YzYTx zZa>=%HshOAyV!nbd$ylyhi1dpATik=C@jjyslOvYG&sCPmLo`~7uS=$M7JYH`>efh jV6DbV@V9|t4;Lp-ovYJKotsmjPVc0A=pHE?T0ML$ diff --git a/target/scala-2.12/classes/include/dec_alu.class b/target/scala-2.12/classes/include/dec_alu.class index 62b75a3b73b44cb04202372de9040e5cef2d65b5..d9d54684ffe98dc427f37782b235c67969c3ecbe 100644 GIT binary patch delta 69 zcmeAc?iSuq&d%sES)W66axc3&qbrzoid}tjIlI_ob`JH)TY$6+$3{_S1};Vy23*$sO!slW()Pv#K&UGpJ2Y=O_RGt}6-7 delta 31 ncmcaEcwKNq2m9os>|&GWv8ywxPd>&zhgFTinL&MWI!6Hjw=@b5 diff --git a/target/scala-2.12/classes/include/dec_div.class b/target/scala-2.12/classes/include/dec_div.class index a0861ef332ee26a4cb0b12a54ef2c27503efb431..3c2c5762d3baca2c60351fa870fc043ddb318b90 100644 GIT binary patch delta 37 tcmX>gctCJNB|D?ngctCJNB|D?fFxvw z1650%p_Hf5TS{%GMyQ+A{1luhqF$jcYw}6OY`LjucTwL`_pd^lMm1Ao)V*owB~f+M zS;{LNy(nr2^_C`AI%bQ=K)aZFmAXQOu0}79>ZZP<9$153I@Lm*r>141XQb*iIWsZa zlq__jsY>c?>J}B5jT0r*5OtLbTZ>*k)kBR_Gjh<&(B#O$Y!{eJe+C^BwU_#k@?M8t z3{^$FL;XoD$i<0L>Nxci6`m)1);!GCtF7gyVuA|E$Fo*bt<*)zXFYmmY9Doux?=-+ z%cyGVB=wi32MaJ;Spm)sQ`abcA<_+0ALXKEZbWYl)kb|r`EEilnQEXu()7zF%(i?p z+IH#`b(?zPS@gD0PU<=}_c`QR0s7rMOzi;CQhy;|xk>d`$ijj7iQJ9UA2q!y`-`k0zkhqRPBOWjxRPUUR! z`KLW=z3|zKb9vMW>h66=v#4QeN(0hW)FAZ_mE4G44|S7DXp(736K1=vt>u(4`*E(B z`hj}#0MbTkf{HkZbPx3NO0<@-(P z!?_fypSn$%j-uB^{YJ&TjI>>o{GEPPRh9O;JiI?tL|X&JdiCztA1Hd&yG6ZEsP{(o z9x@OrM*ICm`hfi3Vq~CHz0Mt!*UrI)kV>7eQl$$~s&!$CT^FG^bW4?;xfL7m delta 3504 zcmY+HYfzMB7>4&lf@-FeU7)B?$8iPJ`T=NZB%rdu!Y)f72RW4-6tm)li*LVWn4P73!lit| zWq3}6Fb%kg5wnLFkMIO91?s2E(+L&QeQ*BUXa#ZWXgiayrSBT>FOh4M?@?YuEk=#@ z_n{HDje(ARX5-7m0 zz(-z`yB@3tPk>5-+?Rpdz)|oH7?>!#jo>@rRdC)axo3l&;7{NaNpepH8^JT+qselQ z0c*gMpi7F}L&5Ffhu~c>C{=a^;Je^8&~LTebHFa}BKTyQ+*80N@GLkzUGA}9EqDr? zmLc~ra0mDicn=KDlwBb>1YQUIv*ex&c7x;KQ!mLq6>J92fiqr~y8+w-eg?X(k$X5; z27V0w2`w%f?tE`SL7ZC)`6dcZX4vj0xSoQf%m~@UzOb^ z@Gy82T=1IQ*MWWD6>!!@xu=6|-~~`qAa@g34~~KEg>qjBR)ELBzrp8<1^n*_-5^0k(tRfSx7x-AkBCralq1qPJw~Q(Y_WG1qUV^8?I(W4@x4nr7x# znTKqlW*_q_%omxdsd2gipSxP|%vRbfn4f3vw~d;u%)ewldpkA7%ug}**+I<)=ASTE zmr;|;d=x%eM)#g+q4qFy*K#^fW`2K!922^ns(+ln1{VZjbJ{> ze93-l>X?r+4?I9k74vW5ZXI;*WgXO>VLtb5Ixl5D#@x4)ngZsZGWYJHCZG9H=F_{W zS;PDT<`4GBW^oVQ`w-6TfA2~!T_chC0Q39I4Sm#iGQZ7S*H29w-2Q$3y3Olt-{%7c z{KS}zc{aLRy+x0WE3Ka5;y{2>DZ=Bugs;_4sS@!0~do9gEE6QgFAx`Ljr^5 IN0KK9O?f?J) delta 55 zcmaDP_(*Vr6Z_WsRR8`woBUt(_-)MDUb&}L9(&|z?A&}B$q K(3+gaQ3C+iMh;mJL0zupk{js} zMUaZa01McKE)(48(9-M=6(_2h0CVURX~vR_j^}yV-}j&Q_j%v%_j&gRjFOX&z^^%}==zHkN-PAKcP0$U?0kk2G zPGmy;(67+ycucA z8i0O-ypm*3pG3QLD);hVcLH)trg!avPC=uP!#?VTK{e19(4zg++X@vy!_Z%fJW^=4 z>=Zg@hVDY%sg&-Ax}ZsDWg7K%L(R}F$ngO6v`{T{MbYmEXt%(F)Gmfbpofs}E7Z$@ zEYLKx=2hyYKxd)bkb64yVxZHCK2E3IoHD4RgX*BG(Be$$1wkh0BJ?-3DT_`Vf(D^` z(AsS3r7CL7rrmx(vMPrx56IkT!)_OrDu82 zRmkler5Vttkos*(Q=wtV{vAs9K<`0I`eeGUPtPX|YTn$Z;U#@)eoIWNn2!A#J}0JD zOuv3LuN5;_%qwCJiTTKYhR=u@D5lSVniq?iCgzBk-C{lz^NyIlW)1f+t9g!?abjA; zY!!1_%rUbw_p->pQmQOj;yNddsCxuU5(GarOwApfUsE=tY&6#kS*J72PVKdZeQnZ&` z8D>1I%__UYjCaz>+o7Md$ykT+$<9!lJnb;vYfOxD>d&&t6laLK*Xi7bnc#4J_L6Pk z3F_YHh-y636){)Ye-Qd5J4ZH_cHxE1MCSN|yES`ziLIqxm6MFpB>{Jl0=5^Xnm4s?sr=eb}8cnW*~&WP1> zDPRluJ7`~~`&zIL{0V$&x$ZGw6?hpOy+Zd8uoUbDhs5bV56lEV1s{SlAoIp1pC18 z$+|BGtHGA9`oN$?&xZL{u4;4$!LaN-u-p5J8<9g}>z)iYfj7ZPJ9Li+4}-m+=T6-tz&+qa zaMUi{Ujg$?ddjX{#`j=umanvC7~jx_tz$dI_IM`M1h$iG!?LKxz#{Ojf4PKb(@Z1V zL$<{^RBPG#*@AMZ9$@>8ZB8E5J#07FX5~{YG0l}vyFFJxC6}#-&0a`#C)+n{6N{*B zX6t72E~dKCw7wEw*~R8jVpQW^BHJf0V>hG3m(q-jZRl>g7tMBp?H@L08O=4YJz#sS zoazy_du;P7s8+H4YMOf`?N(VyGkt6`_t3p!wjbF1_EODZyTUekAJrXf7uhDfMKz7> z9NUx9sDYApJ8Pbe|DgMRdTuS-$83*PQH^73XB%>WY7|>D+aR0cAkEdY{mJ%fwNX>6 zX}7!P+1M@c5Iwh_?H9HeYp7PRU1ytdm}(K*_iWRSP|aq$%=T<8)$OL$)zWU`-=>nv z_63{QJ5-a|I@!j&OLYy~M{J|&sIFjZV{@yg8p(Ftv`h80TUZ0l)Un-XThvIkhV2g9 zyrWbl+by<$V^qu8uCYyTqFTt-YntUa?Ur?%W-hTk(@giav0Y#rcYXG3xUz;j&BpGOcd0%R$AfiUF-Q>CtMJ>52};4#jfCe#P^Oer+~6 zyv;6?6@wI;6mt}BDt0PPYPZQpit&p6?RI%saf@QFqD#@!HCEnk_py}Az8I_YaT&kO zOI>N|I%r%wHl4g>S(qU_M5dT3vcv+BE#gFuNEf+cugDY4B42za3dE11P}~AUec~b>P-uT`B_R$ zH0-RMcG8PAdr!5oaw?Z>@BQo}rKE6Z)IZ(YhFqan6p@L3*D)ptJNlT^0A1 zh&nq+57V3UHvL3rXmo|Qc+6Rj_S37>=o|WuE-Cf4Ebgp>X6YrGkGqMf(v>)ukOEXl z7+%Vdlq4#p5mk~#wX`86-Kdd$sFfqAlR?zW5E|q>8s#$9$Th5$J6I=UXp%{+muJ`@ zudq?xqgiIqBC|-#PqfNkY|=&8tjm$n7`A9RwrUF7vM<1eFpJK00p+~3Ds~?clFX+=B=+`+6=sXe=<7ET-ABNef Axc~qF delta 637 zcmW;9Nl4Uj7{>AUedv;{>dbFu91ybN*C8~gvT|$M#-%dTaT|4JiVi_x&?TuLXwgfM z`9g^TibV;I9gsNJTUh9=gQn;xJxAZrr*v`1*&o_OtBbr1(G&DJohb67VP`+Mb+o+L+evza zKBjl*9Q{HoowKr#w*i`?_vtnIm42YBBhFmd+dqDSc@y-R=5S(=DDTN(3qjOOVBdOhZ~ z+bRpg_L0>SRHVdfCa5&4H>k_3zMx*S`h!{&_nHl=k(CST0xSQ&#;4*daHd=eP$40# zlTuX58YCov^-_xslEOx5MU`Z*Ne*GN3}A~4qFTNNWFJ^J-Cvic1I$pDsXL$&zawrrt7 z&(L1lO8tXv`A1V}VwjdfdV;poYN|qPnWaf|ZMc?`^eC;R<#e7-P;aO$(Ggm*=>b|n zOX(CHqMk5YRz+&bpu1@qEukZ{hX#e)vMfr=9=erYpary#w$XqHyCho6wg_7`(IT2l zJ7^6>q%CtanXZe`l1H;>9lb>t=pu3dC zpi^{xY@m1&Jd#5*Xk~0*Raru@E5F+CLyZxNTEmMvBL($F8txfcxNn?BgK-IsMmd^{ zMl>7!XfejoYAm8n1)yC;qC;&!r%J^GwGR)~F+5TQ=u(&QSlz}G)rzNT0NrXDJ?bxd zu>yVYpdTCY3_I`~>3D(T`53@CyhJHp;VxdI6NB6kW-x35Bc_c}GahfuB)m0u;+=U2 zV`eVio9FStypE4%HO9>@OqipXG=E^qT7qdS2%oGq_-t*)7t4nk>oC4rr|``x!FTHh sepvOGwYo89jbYw$FJQstho7!c{Bn8m+m(VvR~r7fvQS->>TOj20eJc)k^lez delta 876 zcmW;ANog&_sgjLZW{x zB&IGTC=rsP3yW%tq7#Zv=IUTxSJGqjIIW~LbU?I~!7)Y_&_(nh&7~!@jP_H+ z8ksrX${f0z?xjWaHtnK4bkYPXQ{s$lquc2vdWC+Z?KD2dij6n2j&7i5=y}>eo9U=n zD}e+fE9fekPfyS)T1yAUSs4;EvXCyOhv*S{mzD=je!LZJjm)BRX*S(QZ_;AgO@GqK z309^i8p)(P=w*79w$cuo5VVq*WMnho(4tKY9%NkM4G&mZAbeuk2n@G~o%+Rwsp zx_-8W)01H-GoT~eMMbS6A^umEfhSL%nK8 zgX%*ghNB5VG-EnmVJTi?J>Fnf4&EXU?{Eh1aUCB}juzD8Bfg+j18v%%T_>YM&&DUc z44?HTe9_tXs*mEEF2HwPgic+7F5Qf7-H9J=1bW;t_~}l>FLxe(yJ`62Zoyx7KYHDK u{Btj$&n-s3Td5uQtyXTJN5hNK+Kbk%7t)?LUq^W9I?~HT$&J*|9rYh^avbRZ diff --git a/target/scala-2.12/classes/include/decode_exu.class b/target/scala-2.12/classes/include/decode_exu.class index 7d678f15961fd849549755f11895369593473ff4..8972404adf113ed54340e2544410ad8931a9db0a 100644 GIT binary patch delta 3601 zcmYk0|S(~JC(UR zdB2z;lBIClaW+dL`j6zxyHC?4`QTc(+is+7gh-{5c zQfCupR;Z_NhsblYEVA>gL2CEhtRkL`S89t2k^N@J2DEv0qEcwQRd$KdpQGb$4;de$ zC)J;zI!3=mH?G9!IeNuLsAq=pY>L%y6z(UbCGHhNVX`nz-wcfpmQ8W?fbImO@9QKd z9*LK_K{@6iO`&S2U#Mpi(2J)ks0&n&MD)U`_0&m2ZHbs|LK505siV|gYSdixa;bXi zFKVC*y;N#9^(*!4JoM&Jm4;g8VK&Q~=tNK@)F~?HE%YW*tEkVYf2q-L<3=9UK;5JU zC8L*Ss5BX~wKD0Qf=&WeMO~zOB#BUsMXZx)IDlUy1wB`$80`hufOwd zQG+w^)^w_tx=Mx4M=z1uLS3SQGtrBrHd1G(u35S_JPWhAjlG_&nfi|!y8v&^r~FhK zHDn=r8Ps0t8r5eJdP!6@^_?M+joG5I(cVOTMLn8>bP82OwNUq|7jki93Drp5riSLB zH=o*P=zJb#>$@18xztwbdnzO!y=bbGI!kq1g5GOXF?Ec3K#eQFjRHeE3ou(dlVMBI z$)xsEzft|(LC-~Pqkf=zE<`)zG5lnC&0a;~xVaG29 zhn%vaz0*X{WF2e1Qg>H1tQ~io?mQS6c zo-RhZkUCD;-bI>5HBnEzhjbp*NOf7G)8T9MY_1ZAJZS8-#9EzbMN_rZUFwZ>=URsaTLtUdrmvp3XAC6F@{#v zVYd5BoCnaUq5h_(9Yng7xxJ2lR$Q{fJi8LU9WuBRA>LF50&x=%3j7T$Oi*%DmWSBk`^G(-8rsyWJ z#1OGSIK@JdCl-lHku8pj9PzWrHFpwu=Kf-_d9uhir;8Dn1csYlUrKTxK!GP%j9H={85@|=ljm@eaC;k=XuZbesK7MJGb1`sod46 z@vBK9O$wJ?UYryG8xTcyaZ-RRj|x-gEm5iF(=Mx{d&$ITeP&GK&9{Q&z336LqtPad zJ$^FE*$<~9Vr;VB8T!z4_o2!7JuOjoSsL>;>}Cx8JZCJ`+Sm!Iw#OD=XIY${gJfG= ziaHxLxl%oaD@dN1Vv~MT!qxQBloCE0sjNLVNcNeU0NXTmy1Hwi>=JMM9s14gGATZk z|ALzMaC75Qym5;j3DN4AX+94n7(Y+Ao{_f1H%tqYMTy3nc6lf<#N-`tNRpm&z(()} z=$NMaY_Jym4SYUX_av|qJPUT8u6q=?4m=L}rRY8iECvsQcfp}E^jOLA=4t@dt3l4iv@8y9_;7u@mmhS0b9oPo; zoUMB@SPh;B1JZPNg6qMPV3%~=$ABxqFTs1@@C?0|4>p6hzw-EG!x4{8lw}3x_K?SHN5BVQ#3H@72;2{LfCCrno(1j!uYrA*=$;C01%CpcF4TQ8=myV#-InS; z4qOEu)pQr>JQ7?Cer7UIb`;JOS>&Rf@7Vg3&{+Z73AX1}Qk~Csl+C`1YC78?wkO`FI+M-E)@8L(2dy^l zmRjnN`^?!evBoHd#j(}1-DR7&miD%@b+AQ#K(&hPPqx?AQFXIjVH;MeE8Xp9%nmtd zJ-t`LcAm|#f$CDWZ`pcpq?*rmobA~%s`J>6um!rQrkPgern@~Zsid-b+5A7Gn#i`7 z%)N1;OJLAJ-XQJulo%;vY9Y64pW+XJ?kk7#cv z+drlS@1VPF-9bC;Y@vkJEBY$I!_Ze(j?8?uw?8n%mU1L~-*U^~keT5nWmJ>BiJ zIUE0+!Mo_aT(+;-dhDi}#n!@R+e390+X1$2pHNLT>&|{aU8bf53M}0r`IAoKWBRwJVrkaaA zgJpP=T^>_&x?<<15Lu`Ared4oGR2btFCvf>@ZYQ-VVA@aOpj$(k_8& sM3u-Dhn4**@~xdjf%QeP&>ATgSu@09t4l1g){8>xNs-q4;6R1{|BM)f!2kdN diff --git a/target/scala-2.12/classes/include/dest_pkt_t.class b/target/scala-2.12/classes/include/dest_pkt_t.class index 3156e41d080206f8a1b597ce3f6779803445c344..8fecb6595e393a7b0b8fc0f6dd8a87471f419542 100644 GIT binary patch delta 121 zcmew^{9Sm%Ha5nGlMUHLC!b+cXM6-^ak8s3J_fRE7@vUo%|QNBFzW!2^$g7V%dS3o z8=KfWnWZ8?xIlz5lbeD3*I?EGAnPrd^%ux` z2WDAus58C?v&uQnsXk-iVtmdZ$M}N5i18(Z8{;d6D8|yx;jDWS7gGU)98)2K5mWx;YpnSI?TiY@ delta 41 vcmX@gbChR;A}eF{yx;j5R=37H=g37gIHZ98(R05mV*lYpnSI@xluT diff --git a/target/scala-2.12/classes/include/dma_dccm_ctl.class b/target/scala-2.12/classes/include/dma_dccm_ctl.class index 14de3ec79b0eddf6c726c7a640276bc2c7162ff5..9dc2a765ea01479b599869e14c5c9b2748a9d484 100644 GIT binary patch delta 91 zcmbOvHc4!QDF@?<$s0ICCwp_KPd4Qco7@4Ui-7b|AiW+)GjXa q;e02%f`N-+C4(NrDuy72)ePATYZzJ>)-o(-SjTXhVa4Qju5JJY7aSJ= diff --git a/target/scala-2.12/classes/include/dma_ifc.class b/target/scala-2.12/classes/include/dma_ifc.class index b4cdafa85abce4593c4915d9b65727131d621a80..49261f34b849cf3faccba4692ea27ee6fb211070 100644 GIT binary patch delta 27 jcmcb~b(3quBo;=s$&*>4IaL|B7}Xe*8C55LXGsD8a^nY4 delta 27 jcmcb~b(3quBo;>H$&*>4Ih7c=7?l~68I>k~XGsD8a#;sO diff --git a/target/scala-2.12/classes/include/dma_lsc_ctl.class b/target/scala-2.12/classes/include/dma_lsc_ctl.class index 8bb2517fd495943d8fc8e248fba86fd9ca21e42f..28699ed64a3f26fbe77833e6f59acef7f45ee809 100644 GIT binary patch delta 79 zcmaDW{8o5F6+7d?$@v_jlP9pNPp)DYn|u~XZwJy`9O{$50BLt1ZO9=uxrO7D|&EAu&Yo00;JCZX+sXN$y^-jlksvdQ@z_azrHa4{@m dP-a-n;LfmwA&X%tLo>rNhUE+kC#Q3^0RX;M7oq?F diff --git a/target/scala-2.12/classes/include/dma_mem_ctl.class b/target/scala-2.12/classes/include/dma_mem_ctl.class index f5d960d4e7478527bc58192ade11f85551eb933c..8182a6e817d2530e69b5dc39ca28078c1a6265a6 100644 GIT binary patch delta 89 zcmZ1>xXQ!u=@=mW7f8?KP-j$}e2~M2Q3*(jP8Q~T nD=Wjm#VE_5%qYj;&M422#i+p0%&5q)oKcD46r;>!S*~sXyrUOi delta 93 zcmZ1>x=LUaCCwPl_EzIiF0= z8RhFHhS>|}F!??b!$K|l(_!ZK;3TZW{nRsKv8%`pH{Y`thr?aev!)1paf5P?z}b3> zf%=+yBnrKiR5>+B-Jv|A<&DH>%yvZE%PA)*kJs_k zRO$fr8#VV0^x~-9)DM*Xo9Km6+o@s7I!5-E#9+29+Fs6fg1Sq2#p0>?)W_6KYGE9D z8>k*?oSGMpUOd%KUC^W?V7BlCv>T~2)bvE8{!|6^1vN#jNWzT*>J#cuYEd$JX;iPK z(PYf_%o=nOs1E8P<(PtA1l2^Hr5;_2UI0}|4N>e=<^B~p8+AE{ZX=tWY^)Ce_W1A2j)vNmA0FOf8-q2faoQAep;)RJ`E*huwJ*C^+W z=p|8|)FsL(L-zbKFq+Wz@>k&->ak2bOHWl(Cn+Thy_cwB>KJvKTAGa;8B{+tp=o9g zW=qaNdoT49H9Hq+6xBkFQjc#!&p_2srzopD^n9rjYCzLi9%fsXk9H>Yfkk#=BH#Sa z!AU(NIu{jM>f1bu-H*waocN23KPB--rr7uU?K}}MxZb7<(nxMQZ zkZz}brCz8+TBGSuC1zV#g`|x7PSaSen{cU?sZ7_%a@vYCjT)qEYLTW; z$1IYw$=8hAhRz}CfjXQ;Q6}mx6hJn604^oiXb9 zCY)7M7b%Zsq@~n3YQ8{PNDWg@w;;`?PEoU3W$M?8*^X;_`5m0O1NYWYN2%%WB8{aE zQqy)KT}|~;cc_qE=_A5m7_NF%8pO{3kI zE%-fjx~N-}|NBVWsNboV4x?kSsBF0U2BBw82ecrjgY;}FD zUtNz3^k*v0l{y=xO6RLo>r#{&U5&C;w@azj4JzAo<4T=kqtq+Q)oSpE;Sc{0z>rcY delta 3186 zcmYk8X;4*V7{~9yHi?>K6+e_(tbv+TBM1>S%5o97tX3)tqKTj&$X)`1AhN$e$|9nq z+zXXTxlEIqVSWfDv&J-A%m5ju#8R6kq|Q0-|9QqQ=l6Tx-*e7+FCWg(b#1A}Z8_S7DgF9lB7Ane9Yin2)~W zB<30IL`Rr>s$7jfu+rW!WONc`M(qhh#+A4$IGjpbxc1J`@LctpxFkuvo?eopUVS5W zs#jB?lL$1~ihm=#)s;tN*#mo*BA-`RQ=&4|Yj)IT^;`~OGDnlIwLv(fT*IE$$%jfsb#P{! z?90Jc@DgYrFS`k>1-}9xOOSmLSPGs5CqUn&axMq#2ggD0H)Kx*4}iacv)+__1=t3D z4?4Uhdo)-F4uVsc$-Wre3Z4S*gMQ29TrT)AcpIFvLiY7w4>%0YPLw?nYzHrcjw@x4 z0qenYp!F)*gTXTJb8r$|m?Y=&z)!$G!MVw@r-5d01blY2>?^?z@CxXZB6}>@0G2H`?`_%BK?^tvKDSQxRp4&$2XK0->~UZtI0V|Pmpv5R z27V#gm?m=oSO6Xc?|?6)%ef6;FL(oV*&uro*a=<*oj1xJ4+`*W@QDoB!@vq~08}z% ze+4WAkAZi=`J3e2Mz9YY16{LZPX_mZKY}x|WlsQ`zzg7$n`JkGmEalBDo6G}un0U3 z-UEGdQaw}5IX+jng4g|bE~+9%jk zoX6Tz%qpV$vf0kE&3K1uI@>8WyLYLsVLQ%dvxRCR+hMkci>WTvt)!UFHp#_QLNncL zf3t;^Qtent{dYZY$_F@C=Rj^%Q^KPVC%yyB@RZz`m8)SQ?iRvb{ zGi=kFwHnk+XFH*__oyysJIFR=C)Id1Gus4PZG$hy@yIB z+W?zW7u8g@&)A;YOEsD82;0ri<+kTkw9Wt!%%u zy?TJEU>jlc?V(!D_A}djvsO)o9-_?bE?g~+;ldL5wMrm$T&q0Qx8k5dZ)H diff --git a/target/scala-2.12/classes/include/ib_exu.class b/target/scala-2.12/classes/include/ib_exu.class index 2ffedfc746c9ec4620413427344a29737c94dd47..377e3e025d3cd013fb7e551216a2b3a7f4cbd370 100644 GIT binary patch delta 37 tcmZ3(w}x-SOIF7C$*)*#7!xL|vvu;uF>o=)Gw3lUFa$EjP2S6v4*=l_3bX(K delta 37 tcmZ3(w}x-SOIF6j$*)*#7?UQevvu+&FmN#@GUzcTF$6LuOy0|u4*=oG3cvsW diff --git a/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class b/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class index ecea3f794c2eec290423f96eb3b1b93b9ebcdc17..b730b92ddd3348a1b3b935c5200b1042c965d4e3 100644 GIT binary patch delta 139 zcmaDR@=RpI88*hg$p_g*CqH6SXY2>F; z0kZ;ttf^pDFOW42%sR#KP_vhTi>Z%6j;Wu)h-m_Y8`DIFD5gmac}$ZTnwX|AOk z0L%&ivKE3_y+GC?FzXb@L(Q2CTuieV_du)pNd`H&BhM6})WCuq-r9{X3 z{L^Q+wm$VGXnlT<4=dQpDqZ`7Z4 z1c`SfDg&rl)PCv#)pHbXOrdsBO;opJ^iru}>H-xyTKDXuv6?i`ddXj?m&f3!EWPH(B4e_PPI=(nnbOlPEoDLp%+c%Q^zPH z4ZVR>4pnQaAq~6rN=Ms6`KTL|Z9IBuR0&m2b(nzO2x>KTnrbrVO>IbUDH1q~j zbE$*W-=?}u$8OW6<6b3on~L}p=>%#E)j)On482iQA$5)l%0@4aDxgl7x}S~RhRi^F z9(9QNhkAP^def;Y>JHU?7J3t@tyCk`c{X~<)H+k&&3?XHunfx4zYOwnBjorT{ZG4A zE!Aoc-i@WIsTR3NNBEWC|Ac>;IOn3Xg?da4orkoDxgYsr0LWFzw~bUJI5?R zr;2L66z`I#ozycbei?dY)FUdY0O>~RE;V>L($!RxslXN3ZN&<78mQhY@oq8o8`a|r zr1PjV)azd&ok{&fb@n37qK;ARq)zP;yB#*q`cE)$74D@``>B^!BOOguQq9&NO{8{E zPpP=I=#^3rsSgWvnpue5?wDu2n|&Sbt)i|`{njI0PFMZq)uF=oKHBFYw zHQV-dGFG}4QEU*GMZLIUF~lF12yxZo5Z5eOqRFyGT(=w)H!O|f orqNQ|GP;P{Mn7@K7$)u-8RDMd759yO;!oqGsIO_izxaj!0HpZ=8vp^QN9LMoH4_fU}B4HvF?Kzkvs^>`1Qp)f`BgrHaCJ};)#8xEdmeCPSy$y{FKq~?WD^TMdS z7HzAQZjW6)i|&hZ#ZWzqZYB4}gsJDwSi5{2W1e-!j7w0y7ZUgXJM-r|V}qqHZV0MHd=x&J5l`#!c=P)L+%s{e#I4^4OCw>7 zdX}0{WPK(~b{g7ERl?B4`n`8pR}}&7U^!@5GHTzj(dvq=rNd+XbKD-cb>aP<2AgS9hBfdBj7-<( zGN2FMf{yWePlKiK3T!t)@5A9*cow#psP`DS44#CICh2_uoCm*zPhpSA`dlU~hqqzq zM|w|(Wv~{$K1J`zun?Yu0Uzr<7A}Y1z{XSc?u0q;EBF`eIZdC-f)(%%49n2_c(@f_ zh3zx-J_4?T=V8k%y}RHF_$_QQUGD?oe0UiC4SUVd=cdC-co&9$qW1}K8?1vJKGpk3 zSOhP?z?piFg9Y#ud})^62f+pK2>b`WGh3gV0juCW*maKHC&KNp9(J6o_Y}Au{$$x& z24n2ygF4uW3#}ad`%MX`xxPIVzBahbUTqn6g zmeM+f>uavSd|K1F4x!Auncq2j8J(%(YP_7DC2{TMdchUHg3fK_dcqY|Kah>35BhA$* z>261@_vZg#%Qf`5G_HeOudbza6jvozqe5B}xpr|q=ZafL=gPPqbA3=`u9-!2w|mxm z^KQ=d^tm-$H@Nz2pminJRj$a5wB~XB%=OkLTIX|}ny8Ei|KA1Hq(;Hb(|}> zgx1MiN4NsE&^nIm0M{#}w5D)Xa2aK^dboC4b*7B&=GsbUO1U0!4c)*x0t+KzeO{GI-D?Q2@rC0exd0H7+WtYvW95O>0rSvKD zl(&?}ln%e$>vzaBe=GT(Kg{+}W+n&8S$^{m_KW^3^%`Amz8tJ@wddHFvykNal; diff --git a/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class b/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class index f0ab0bd338a47e6e60b7cd9a937521a59b959d86..5c9951f2a5c00d77ca9e5e83ed920c91c5f459ef 100644 GIT binary patch delta 139 zcmaDX@>pcUNjAn=lN;GZC*NmNXPgaY$*`+4&H=L`fvmYemJQ=PF#j@;KOf8z;815= z0A~3DSqs6eE+A_Wn01`vq2^2mE~Z%wa!j)sjF{#yxG~LTh+>+@kjFHip^0e$!!)La R46B$HG3;ZSIr$>zBmgd?D_Q^m delta 139 zcmaDX@>pcUNjAo1lN;GZC*NmNXIu_u$*`+4t^l(lfvlB4mJQ=7F#j@;zZ%RE;815= z17`UGS!=a{p| z!xo3x+O@s>?haA2R3kM&%}78mjygi!r1UoQtW-JmEj2Mw_WTktTZy)pvz@0# zsReK0sku}KHB8NU8@&xw6LpW8nS@?Eb(HGUq)WzZQORgmP~Fs|6r{maDb+=dQ43RX zBaix!dO*!hLoc0b*7RK(W}CGhodl|exK1oP*JXwwFH&SE(sm@GLX6gZf;P&f?+7b$)D_ zM0Bq6L&_u?sYlfEJfz2{5o+01q*c`K)S`T(4(cA|U*Jrw@;6U`N&M*An}pvs+$*Je zDbseO+o`M6tap)ap)OI=-b1>Px^nm*i-2|N8q#?9>1?e+Sat)DP6Wok&Zl8NNF)vX-OQK>e+0Mg?Z8tw3j( z3bNzuF!d`H=s;RQ-KAa?NOw{F)Z7C|i>d3B&q0|+9>i>ywY~iA&Nzg7+0>WR^M{dU zQ0FQ4N~Fou$JFF1r18{QYJ4@)HJXa5G20lE$Rp^~Q-4wBqeyG0A!rnWlFHs=_UBI+7tJdQM<>ZZI;Al*!TL3y1-nof06Q|pl?Q6FjgsUEY% zHK5Z*J#`9atEm=hl(ICUcar*(3T=|9{3HEHlaCm(8bn`{QCw^?2t%{c(QFV=%|;QZ zt`+KOCa~DQemuF1s5|GlJGEyXA$N(iE~r<+30y3!<1@)3( z7SSJ*s_r@G9gz2UV`r)IMr;W!jpA;sU0n=CTSUnGB-qjUDe5Ur!sOIWuYQ&{cAUs` z2J1&Z=6p$ycbwYCTjQMSb%TCwkJG*YcYc5fbiJvYP3&-KcbP@I%c^rkyyR@K0Q>@c z08UGgbL+qs@DK2X1+r&?b>J;3? z8^K<1Lb~j!;9;-}G%u4q9;^U6z|k49M}Q?@8#n~c%#?E*z>mRu;FRUEXMs)NFW|%# zvZsMn;C0ZlQuYMU16}~1%#uA4ECtVjkHOGYa&9B|2{;H&&6a%?=mUQRpIa@v8>|Lz zfKR_G`vTAlUIfRyCwmmQ1w1e5T_bZCmk*(8)OULNcAAw?`*U3sCwCY z*{0{q>eAnNee4YUpf} zk5DOO>twTjNHveGgDvnV)wOJ2vjrTZn#Fd8ZCowYbhb}*`?;3RmQqJEEo@KJ)80Zh zAKN1~X9LY0WBZdWs!^-%e49Ab80>8_i>^ki2vccpvWh&F@hVTNtWbGhWrxZTpIMCd zSw*(W2$jt~e^KPK8M=kRX%uIC+Mn$4&1>|lNi;Mk8#-HuA5S;fI+bzCWo3qPMTu9g jDp|@krBvxss+H?Xn{q?xRc;zaDcy!iN@uG$k>>XwGtQZ= diff --git a/target/scala-2.12/classes/include/ifu_dec.class b/target/scala-2.12/classes/include/ifu_dec.class index 9eea1f952d6a7c3864688c62812fd7e68276ba00..afee3c693fe286a6a2150842f09a6192cfd9eb4f 100644 GIT binary patch delta 63 zcmX@YcZ6@l0#-)e$qQL+CNE$WoBWwoeezu(ZNR2JS&B_;axPn>C=UY{BQJv}BOikT SBR_*SqX2^$BhTd9Y?%N_st*YO delta 67 zcmX@YcZ6@l0@lfQS;Z!AV^yCl#U?iSGms7k(gtkmjDnLFvWia5Ws4N$W#D4uV-RKJ VXHZ}iV9;h1WH4jooqU@u69Atj5E%df diff --git a/target/scala-2.12/classes/include/ifu_dma.class b/target/scala-2.12/classes/include/ifu_dma.class index c710d821483c286680b85cf5f0657e7d719df04c..8c473b40775000008ea4aa5bb0b592bc0584955b 100644 GIT binary patch delta 43 zcmaFF^@wXj0?XvNEMk+(SkxIMCnvIqPTtJo%qz~o#VElb$|%X8z$iYMnKd2&5`hWF delta 39 vcmaFF^@wXj0t=(~pX*LApDDnf=O0gv*;(VENPad1-X2u@6@}gw{99JE(ybO z#bDew5Tlrf{xCgHnoslJzJ*Y$c1~xO!SKF6%cyU8n#&m7(H6bZfIeqD-P1Sf+D13@ zgAlgh0#L_y){@KbZgk delta 214 zcmWN@Eo(wy7zW_y7LMmV7}cX-5(X~=8462c)wZI)z+%!YONMc>=rg~jo@rf@37Q0( zWnoe92MnVui{9zF4yi+G6*zixe4RR0OHp5s^pz%~RyVXt|7n-zU0;7_i+ZlrFIu60 z^o>3kU-z_5uQa4ZWA#MaH0>qy+dN{S1vjY|W3lAo>zubkxhDpF$wH-wcd20@O$;T# lNJ5Ndi;4W=L(Z5Yf*CTH;~61d@QDT%=wOL4dioTb+yNCuKaKzZ diff --git a/target/scala-2.12/classes/include/load_cam_pkt_t.class b/target/scala-2.12/classes/include/load_cam_pkt_t.class index 120fd433ee1d602ca6282de8c1997e9781be32b2..84018bd2a75b925e7faa231bf5c3c96c464fc850 100644 GIT binary patch delta 47 zcmcb{dyRKP1S{j>$&su!j7ug@1CmQ8UuLZnT*Sb|xR^nXaS4MF<5C7U#zm8p*h&C; Cu@092 delta 47 zcmcb{dyRKP1S{jR$&su!jLRoa1ClEyUuLZnT*AP`xQs!LaXEt#;|c~h#wC-J*h&C= CgAT0# diff --git a/target/scala-2.12/classes/include/lsu_dec.class b/target/scala-2.12/classes/include/lsu_dec.class index 5ecab4eba4c6e0682c758846fbbdc17f5687770b..84caf041a82f7db183e9ac84dfdcc60eab698785 100644 GIT binary patch delta 39 vcmZqYZs*?6%EGv1avO`yc{ej~F>GNFW!TD~z_59;25US3`Th%v delta 39 vcmZqYZs*?6$};&7i`eAZEb5HgCLd;r;N8N&#juq@lwli#0>hTc8m#dE0GtcW diff --git a/target/scala-2.12/classes/include/lsu_dma.class b/target/scala-2.12/classes/include/lsu_dma.class index 9a0a6e9547251a4accf6e117d7dd0a7f3e27bf3f..33f933656cc976739c02c4dac0097ee735285410 100644 GIT binary patch delta 67 zcmZn_X%*R^%)vNwaw3Q5WJ?b9$;upJlgof~0+8Meq~`+Z4;=NPGZ?rSW-^E}%wkYr Sn9X3xFoz+AVaDVZ&PD)-*%HD4 delta 67 zcmZn_X%*R^%rQBELu|4ohx+8XK)MV_-vZK`In){FPEOk diff --git a/target/scala-2.12/classes/include/lsu_error_pkt_t.class b/target/scala-2.12/classes/include/lsu_error_pkt_t.class index bc57f17865014108a91dd9c22c5418eedf6e4a95..c9f92bd3325493dc455ae30ebbee82b3f5e0d754 100644 GIT binary patch delta 83 zcmaDN@I+vPAseIIK$?k0GjPgL14Wj~>e-Ox51hf7DSxR7*HTxti~iB6F>j} delta 83 zcmaDN@I+vPAseImK$?k0Gj2b|e4WlNQe-Oym0<-=BS=wNhHTxtj01z6RH3J diff --git a/target/scala-2.12/classes/include/lsu_exu.class b/target/scala-2.12/classes/include/lsu_exu.class index 401e908efc2f53158ab2c6e16f88745116638ddf..fcc4be2ef5ac9059c5734bbdf9090a03d5d8fa85 100644 GIT binary patch delta 39 xcmV+?0NDSX4xJ9L*#!ZxliCG5li39plPm^x4X*$S0I&cq0I>j40I!p-25%Qr4G{nU delta 39 xcmV+?0NDSX4xJ9L*#(mp1{Ra=1t$TrlNSbx4X^+T0I>ir0I~p50I-v;25$g#3{?OC diff --git a/target/scala-2.12/classes/include/lsu_pic.class b/target/scala-2.12/classes/include/lsu_pic.class index e8be850ea7d4b3efeacba19177015bb6d1a04745..4c947741e2ab774374ce8950c470212d2a443158 100644 GIT binary patch delta 104 zcmaDU_EKzv4hLiZWJONV$xa;VlXW=6Cf5V$Od!1nNG}7@KY{dPAZ^B}K3RcNY;rM> zj^z~Fyn&O0QL&GKi=m%EnPCEh4Z}o+P=-kil?;;^<}yrSILI)S;VDDkt8^9D{1M#X*xE`|vV$_x`3Y#1gngfdKKsAQPJFqdH}!$F2=3{M&QC*S0n005yE BA7lUk diff --git a/target/scala-2.12/classes/include/lsu_pkt_t.class b/target/scala-2.12/classes/include/lsu_pkt_t.class index 7fabebb5cb1cdf54d9e4679dd70c24dbbf8c0934..d9b8624d91d0ccaba363556c6c0f57a401ae46bf 100644 GIT binary patch delta 171 zcmW;8D-Oay6a~=RE9g+s&$JyrA=s%V!Byi3SkPe6Sdaww6cQ3Vx*H&97Qj|`8FfzQ zI`^`1l*!4|(!@T>!}hu&?4h$^KV2C%F+QroHo98ZijAFojhB_0_q|-zrTS4XYR@=% q_n-3=2{Tm8F=c^<7BiM;Sz*B%YdUN>z>Y&4IKq)*oSDi!x%~nAfh9Nq delta 171 zcmdlbwo7b-5c}l49Ac9-*wrWh0@A5K+MH8t@**Hz0;KN)>5V{IhC`iEdU7L&=;TNs zO9sfYVUz{)F9Z2J1{!Y2pW@<(em+M?4QwPaVLFz6sCh@JUFBDqmB6J9JzUYT=kVrQX z`yKocT}tOtrylO~{GP0mRr0{$uGy(8({VIMRx44@>LiM-T%|d&x)Y^V@1nlwh6nZw zMa@I2hG=BimB=m%o-q5Et2DHJDju_DiWBS59o$|@F;%s9rJUl5w6`}q$Y C2Sw5V delta 254 zcmW;8JxfAi7zW_yxt%KApeKJwbqASN(AOgj^c+L2W26}xc2->c E1G)J}(*OVf diff --git a/target/scala-2.12/classes/include/predict_pkt_t.class b/target/scala-2.12/classes/include/predict_pkt_t.class index d112e57b87686cea1df762859d95faabac0a00a4..058a48eca627ca8a8cd6b8fa9a6ac652dc313382 100644 GIT binary patch delta 182 zcmW;DEepa>7{&4DB)5w}1aDZd-el1r1DjyA?;{vYVjfs+Pw*R9EXuMVdv(6d;)gJa zR$1`jrvHxvC-g#ZUpJ8O*XeNEF-WbZqReV7%B@OKAsTVr&^&ex`;O*Nx|ANJk@P41 zNQcUB&(*w829^CEWSO}-daD8am=qG~BBeeunjohD1RA=aK+X<5r^VK^lgopKUR|uvc&8w zOU?R9BQu-JaRJQjUyX$f-nu JIzskps~?LnKR5sY diff --git a/target/scala-2.12/classes/include/read_addr$.class b/target/scala-2.12/classes/include/read_addr$.class index 2f6efed271e7175d0509fa9e2c7547eb433ce55d..f3c1cf446f38186367570e9c53e37f2f6a25cbac 100644 GIT binary patch delta 19 ZcmaFQ{GNG3IU{56s{rSPFNv&(y4_Iai+dw%CU&w2O1!@v$*!{fS! z$933Nx-qy+|RO4eQ%3v-Z%^F~F`tEw&qt^x}Doyfb9ei8_n?JiQjH`s!v4aGq|k z%J*%tTGZDE+N(LjSM_NA4AB_jr^zIyM9R-JWScI`kw&M=sEgD%8`9UP0_vPo@*U-~ zd{&{og=(j6Q^wWkrBDsj_tY~{=tWbtR6jK}8odyzT$3XjvyG2IXBkyUou}?m3)bL9 zCUu$`raWTNOQjmAAE=pe=*4I%j>Bx%m^>MePAFADU8W`^pyx;Jpe|7NsfCHSkwu-M zex*!FvS&@gY)#r;{&WYaS;=_T8mf-EPPx90UKq89x2zR0cu)0dg0Vws!!8sI%e}_X3Tbr$($|d#8Zc;8 zor9;Yr%q5mQtr9vB~XW{uc_%<(Tkv}sH@bYd9wFX-q>t9QIaRW4My`l#aDUqZ@ZLf z8&p7jNj;a3G?%*KRD|;ho3^9VOX=RkSvqx|no@u?iRz>#6(WtHPEr3-5j)U3PTkk! zUWD0>6`?aq1=w*`N8P4;i;?c9Zc&R$kd|w*mU@css2AUosXQy81}Klxu~g0`J6|~W zp2B@6?&VOIsi$`#-AH{zx$Q=pMxCP`FGHG0ouww0BaPNnT#niPVPdU7rhqQ{iNiD2ITBgZSiP`2?At|P=Q^x&Bw^N@}bE=VMQKgUJ5v2LlRciK8q*>HO>ZxNg^*e^yy0yLht#Ew@_fn|$ zsmI<$8c%gl;~S8!rdp_nRCptLjnwZ{V3SNUn=soQZ7*l@YsS4A>L==z<4E^WgOtyE zNOw`+Q1eb8Eu#9VxhIis)6{TM&NiBF60=%lBEM~7Ta04RrWf_BNOL`9Fk9yPKGQ3Tlw* zbZMXJ;vK0N6r19utWuUKt5roQ>y&7vP>E5hl{Ly?C0043#3`RB@yZP)veWl;(d7RC D3%ei< delta 3193 zcmYk8X;4*V7{?E&SWRYl;gY4PHFmiuHWO-EGKp9$m*rl(vM*XJqG*ULV(gKE0%|Xt zq7<75xPW{pl{9KxD61JFB4vddHX|4!N`_4pgb42uO;VA0;Y-|8lYEL6RMg4DaBpd8FR5iHMcA|p6K zy&DX!*Pk(q>JU%WJ_{+uIX!fqYDGbAqBk^3H=}sonxO9JD(bA--_vik=^M|ry```DXco}>$PWE7MCwKvz7%#gISOA^|AApMznh;NnC%w*~A5e+NC1WKRKG!C~;( zWZ7fDdhjYZEk*WFumT(aoz}_j3l@Q&fDgf!Q{`MH*aO}H=dG809oPom1ZQoKJr>*t zUIPtjvRlDQ@C$JAM%h<_#o!t6FL22wIhO^V0PlkH-yRaOoB~mksuUqo8M|?CZgH@F#FimhACh19$^;&6Yh3+znm= zAI*{d4V|u{BuD!W9Lx0(*K)M)XwA%9$@18~VS6r@Y8Kl?SQy@6(>9vvXLEUn?o!xJ zu}#UNx`wTn%_*O16x$KDf7!wcXs(Uzfo^jOX}88gni*qTSwwerY`59Gi>dBmyT!J+ zglf5Nwo(uAJ==@#YE`={VY|xaUMj1$n>O<`&K_dUd-Pl;+Xc3#w^QB7_9>fT2i0V@ zlWdQdQB7bw!8WO!YNT$(<+R&BTx>gOrj_kJTi`CL2iZp1d@HEdvi-`otdi<(wwr8= zs;HLf)>B2hE!a(^nC%LiX%E$HY+td>-b-~0+j+L>?^8`ty?z&00%yEo}GL0_vz9V7tqgUM%wL+e%AggoIjxF64^dtd+bB1actde z6Pl=ovvshIvxPR(Tr=ArZ2m1;-P}UE-O-KG83b~tJf3yzRAY1Zp-bgF}= yU2#)ZEAy0aWw{ce*p)~nRf$sam1t$J5~DOIvC45JPWfDkSFS7eUhiXtlm7$4U;Q`$ diff --git a/target/scala-2.12/classes/include/read_data$.class b/target/scala-2.12/classes/include/read_data$.class index 8befaf96bff90e57fe924479eb18181a0667d2a5..697d4857b29f94de073517ec9285a1d2938c297e 100644 GIT binary patch delta 19 ZcmaFQ{GNG3IU{5IQ*joa=5#YGShSujOV!Ad|` zju*fSE}<;URD@8IqZZ}|u`Auwnu-i_nn??-51Ll*IqdUHU*7$l_j&&B{$Usvh9pD%2LG7bl~FwA&L=cJ1np4i~l2MkSl4JkPvbQ>J<9DJkl% zQTWF!_NXF8&fkkMh{2dxrKw4SsEUy0gr-dM9C0pDZYNW( zB)P+QlCMZjl3#~Zk4H~yXOrVm5uR*P3KHGPQ**vzJULLi7m)5N=B7Xy)B)-%YE~+G z7OIIlPfbfhZxvNXouY1gB=?tlRHkEYfVxf@S0gQ;dZ?c$|261kQti~&)aY4N|{TAvW}il$*nEx=Jlrhn|%>L|s<$D#324C1|%&pHMSP zkw#Mu)ClztwR}A$YN%oACiO%adL>k!(pVXGTUd^cjXF$yOBpKAOQW3Br_}u$&@)qw z)LH6ZYDFa`HYvF(vD+;sOE#iYO7&CMs6|!i*{LJccOL15!682(Ob+?kWpWtB8HfBW zFEy(g%BS9?X4W9hrUt0{HX&V2^-*`J#Fx?Qrv9SLn`K(D8N1z3XSthc3+DDx*QkhE zq%G7q_0(3RJE_Z5NFCBT>I>?zdZaZqz-D7n$v-_j5NXXB1idcm zCKcI*v|VYW3#&bI6p53Xpu$~9cTwL{OS+NnpuVAkUProx`ixr8gS3h|uQb_%-PRvN zXN1xp$GrmTB=tZqQk#;=5hMnc)So83fnt8Tp9pma3WM8E6lU8VH6}SBN pVpZP;?K-Tki~INcT6G4UO&6@Q>sIP=b!oahU5?Ir;>&)!&wse-x|aX| delta 3109 zcmYk8Yfw~W7{?bHLutAwEIZ94=B0sMpd@EP!OFE*mfLbyLoT~OaZwah7EBQouo6(< z^#XW72-t-gix6yb)WZBAR+e47)Kp}vPBUp<>Vu}$Ip_U9&-CT|e((7`XZM-?aArq5 z-Xk9Gq2Hpt?4sKm&}LaEMWm6nS^ULOi&44lu{e~gJ0?O@$Cxy;V|a!&N*LUJqSQK1 zyOXM2O(HNh7*-yue!_!TgBXsD(@Z{V5EXIiSE^+^E?%*4n?Z!etF<{k4`-i*T*V3# z+Ldd!)gVffrU_$Wm~vX0SpUC!lWZZ%Dcn}3T@B(RTaL1qUW6v8-!7kw#HPODR8p{3 zy^_@pCX)3cEjbF-3wu#Ho1IUJh!nGCM$wa^J{2G)Qi3#2PnFCB_kiDmQ`2O(fsNp4 za8kPLi@_T37~q zfVJRp@E#bEDd*OKAAmQ&kma%$fqmd*a7LEwSzrfv9`wtWJsE5U&wxHTvcC#$22X&0 zgY$FcTm?7`{sD&CWiJN%!C%3r9kOSGo!|w~KTq})a69-JI5}VTXmAVoF?b(bP$1`= z;9>A481}mCC7=uRfHU8aJqO$iUIg`pvZsPOz|X-cMY3DKI`9+l0T@{<=PJPw@D})N ziR>#tH+Th{wLa36RH3|J|98rTAU0s5B89s|~cW8gnv)G9ew1&)HZ!RJ=Xz7iY& zuY$A7WVeI+!S6vsx$Nm+D|i-sWR2`rumL;?{tGT#E9cgON5DJa+;y^-f`i~Sa88Bn z4)6f@gGRkDIMsKe*{Qy(%}$dz;Z)z%s!gpVD`5MO&9{nbHro)}L+hz7VH;q(&zAHi z&GoST#b({0*76Os+YRlk?q=Rd&+TNp#uiykwV7>#ZQdrTTiGtLh1O85Vf&ixnOdq< znswLGZh@Prl(U^;Gi;$+!giePi8{5OYcPp?wj*p)>ZxY2z0c;|KsAHS4O4ehKh?IC zX1dw_WQ%!=YA4%uwncAK6>L}87Q92XiS1{$=eJR9V7sW9S0nAVsgY*RvCV0sdzEZw z*rqpAEo1wXEnqvIgV;AlAlXg~j3*Sx8)w5k-Gwq>T&Gr@B>~^Y7wsE$n zI;gH@JISW+q*|m|YbWjY*j_3Qwh=a;eN;2q4w1F(rKrt!y5)h;FLe*nVW2+e5XE?L3?DU8)<|zGR!#OSOXSv}U(@X}48Y{4b%7$#twYjH@Q^29m2M|6r{XT*1J_xRODRaTS9R<7x&s#uby>*-8MP C#}CQ? delta 47 zcmey(`)p<2nX6#?_PC*-8MR Cvk&3` diff --git a/target/scala-2.12/classes/include/tlu_busbuff.class b/target/scala-2.12/classes/include/tlu_busbuff.class index 40c8f92f1cbabf1f2b4634d47b15df19e88a3bc4..d6168d4b13aed13c12f7ed3b2aabe77391800bfe 100644 GIT binary patch delta 139 zcmWN`D-Oay6a~;bmCP$BCRH_vQ5digGz;i98t`cFeU=0^Kth7)F#K6S6P8gtnyZdD zF^~B%u_owJ`kGm%$8Qfn!ZE<3c^~t{ zEM}*kmbrE^)?PNe;(^!v$6tJAoEYO}#TUHcTmIpRd+TcJRg$$ColBdmX+R$>CWt7| bp~3}AT(QFqN8Azcz#C6|k<<`D_JhM8j_@kc diff --git a/target/scala-2.12/classes/include/tlu_exu.class b/target/scala-2.12/classes/include/tlu_exu.class index 4f54d85c5526d601e6676738a9159367308096a2..1001d7ea399830086ece6ec9c0d1a0c7c7ec256d 100644 GIT binary patch delta 3505 zcmYk^{%%&v}36d!BFiWrp$6e9No( zme;`-!xgJ=ISnE;e6C0RRBE`Nm=Ix-=X$F_Bt%#|3bX`?%RCRXM0jqNTb`2|v@Fuz z1H{otUtx+29`#l>>P`JVy){7SqtyGVilW@x1c>ud?leQO*2e~j8tYO|#VcAap&n&L zr^%yJ(M|H{at4TVu|A?YW`=xwCuYN_vrOAG_k~WILq&M->?_0$sd z3aB3Hx<~3)tDlu=N4t%>LQP6QYNvKkpHt%<=vk;u)G5j<5xwWBGHOuMP$G7FItlGn zR4;XdGA5(9jM__mO+B1~UINuXeL+2xie4nOSyO*1cDpAHofoKb>Iik4nz_MiF&@`k69i zt36vbc5Bz()!)2tsYi0~S&395b%FBEMbAprQfH{KdFaijDyXB>T}@M$W4GevxOb2m zrpzxP&7t;FL)4=y&`YA4sEd?OK6=sA7V4~~oB7yn!Ai6%srRTqso4eSt)}{^U#MxT z(95MdsH@cELiCcUU7Ai5VmIF+bYiHj)JN2~V)PbLRn#%+FKW(e+$f<2s1a&<33_>& zTqW4;8j~q6qmx24Ql&Uw=I zdN#GzEOMwL)PtLlE~O4p_ije&pn9nPsMs3xI;cAysk^D)zNZ$Qo7BQBIBTSCQ1iAT z-A-MjLh6uirY=)YY(u(^x=00YS5w<|?Dnblu5LNig?p>1)6}GTr1{kQl&?UVO$|~H z>_D1E4NzknkS1uVYQS#)GO_JMXFqkDifBZ-oBEYn(1dg+b)A~K3+XoMDmAMa=_XD6 z&Dibn*O63F7bs&3(lyj4)Rf&wi>VK(iF=T)ppH{Mtw^(|!J&AhOHISNu-h^1-Q_e1eRr@Dt^H%#+HDkiyFt{-Ij7qo&d6CJ=hz;j z7?5+moFj5p$T_{oAdbqJC+A%`JLL@NHHvF;7Rx!M*B}ncnIh+~oXv8Y`;6jJub;^3 z)Ba!5S0p!@b3i^1bsq@xnrGGdDABqQB}V5^Y`StKR@bJ)={`{6bw4PJ6<=kE5~A1@ dhmxR_$!DvQsGL-il<$>fulwakm<9^R{SS2tmnZ-L delta 3241 zcmYk8c~Dhl7>Dm6m1@e^QKLlu@N!YBNkuE6K%IvD-iyd0n<4_GA|Mq4vbX|@!Y7M_ zqOw%1f;FQ?nl^6HGUYbYXr)$@nvprFw14M(zxN%7ne#m7d){-;%RhH+(;bJVI}ZC_ z4biNkrqDwqhs=TXvn7YPiE*J8dF~YHA>u;AU|wN9;u4>Gg@xkD;;@%QewV8l3Y%`6 zc#6SrS78bFec-O>fjj+;PLZC%DMJ4Q-Et$;KAz%igsMw4YpvZ=R7R#^#34$qp&zA3 zrO2ZbQH}CiQ|Kv%>@H%Hb(*~Uz`Fi{vozZj^+1O$UYC5iqr0fI>;IQ}?nP|vF4zbD0$P@-z6@*yzXzYnP(1-`0MCKW znW{&ERp4oGbe8JDU76#NMM6P%T;=2nCK;IH76RjOx#?ch~#Vvg#G;7;%Y=$fm#72FDb3OeSg zJ`XGdkAQ!HvsbIRd~g692B+q$o&|P**Ff(#R8In%z>A>Uo2uKuYH$dA_$}4vgXQ2+ z@Ne*i0)5V1pc>EC&GsLg zy^`kI+3v&i-SoHbuA-USZ1c9zSp(Y*wt%fvx3gVi^RK2_!FGx5*=6O$oo!A zZCs~bgF0!qBgTDAp+z`#`HBJg!!)wXEQTekB&T+Jh|`i;lB2uLqC+xR@|t9cq<4>p z7?ezs9Fc62^zSi?i;{VgZoM92zof0#P2B9UXi363)?N7ZnzdwUt|GnH_%+^}D|edR zC$9&(`hpw+tR@%DX7bnUrg$ydRIDv9?a^XPpJ)qBKWVX=s}`sEYw_|gK`YW0X)Ri! Uc3ex+e$|&Gqfb>5geHutxbBImm z;8dSn!6CNUl~a{bQH_C%QJq1TQG+3nQInyRQHx;)qc+2CMjeKGjJk|WjB1m+xjFy` Ccp2#c diff --git a/target/scala-2.12/classes/include/trap_pkt_t.class b/target/scala-2.12/classes/include/trap_pkt_t.class index ace0b32c65a2ef97142496bea559a9e19c1dd016..9823780c9f0059f59fc1de8db4e51ca85189d3bf 100644 GIT binary patch delta 149 zcmW;8D-Oay6a~PT1shW`0%f`BEwj5;Sv zvgA}4R&sD7xf;(pEV7RO%JSaLO0-|jmp5wXIU eHD+wEV2c$yr0lWb9Xmd7XYXKX?Gxf2S~SYs59Q1yns`5@qaAUm75XE?pA&>Ds dLlffzhG~os8CEeqV%W#{nBfxR&B-F%(*Y-$GFbos diff --git a/target/scala-2.12/classes/include/trigger_pkt_t.class b/target/scala-2.12/classes/include/trigger_pkt_t.class index 0fc2a02c07602b93de20988d96ebd0ba93dc0a4e..4629fcc2c1938f0f1c4ebf016914a08108bc5ead 100644 GIT binary patch delta 111 zcmcaDbX#ac2^-_G$?w@jCwH-_GcE_SjssaMfGiuvm0-RjyE@}4Fsly8S`B9H2C~+G wSwGl!DK2H;Vp_%^$F!Wmh-n3b8`DaLD5g~mc}%MrnwZuwOlMj;`7%cb0NxlThyVZp delta 111 zcmcaDbX#ac2^-_4$?w@jCwH-_Gj0a6jssa+fGiuvtzf<*yE@}GFsly8+74#z2C{a5 wSwGl!DQ;xoV%o$Y$F!Njh-nLh8`D;XD5h-;c}&|GnwWMlOlR6S`7%cb0RN~bNB{r; diff --git a/target/scala-2.12/classes/include/write_addr$.class b/target/scala-2.12/classes/include/write_addr$.class index 49b1cfd891efbf5ab917bf17cec118e1f5f84bc4..75cb0d9799287e10c8e4269fbef07bbe1281087b 100644 GIT binary patch delta 19 Zcmey!{E>M>B_m_%M>B_m_ny6_Ozol9C@lOv!OzSwt3G0h9Yh9vVf^sDIdxkWHX_L)r6NWH033yq*D8W)O!y5Jkv09&hNa>b6);44D4|Fmh0(T zu7{U~xnv5La6eHSHciP>oDB<7iq+QwvxmqHH#-$znj&t8`|=c_dPdP~3f9$cTA;7C zD5JO#;U+>NMJ>_SFQV2f`-zf8e!Aq1o<#{t9>O;|S<31z+M?ymwkTgQ94)8nH$5X}S)^oI zY?0sB5@Qg(mf21jV#YK_p6#BZBPLYISGdKF-7^SFtdIUI)oKup)R)vFi;*s%s;Lvy z2o+=zXWg1p$<^LP+oE9B~d%5LCO%1UJTVl^;6>#WN$_SW~)(W zIps;}J{7zaZ!MudqW+|&zkyyZ)j|DAO<9IsGPRSsq~wx_*R&1( z12^nS?HQQuZziu~qLWW`QrD>$vd~MVc2QTTNz2i*QZ3X4YC<-8CM8=oW;=tVWd$m8 zs50spb%&afgBt}@7j=W0nu}fMVa1zM>w>$Gak^da9RlDM0Tv zY7KRqx=YP0#En9#o4Tnqu?VxJ7ooj}`ktC>LmEf5QUlcE#ps!-2C9#8U5VaYs+{Uk z8d{0j0#~73L>;7lqkP^(FN12QexROSjb1#pg}O*RQG#BiQ|_XnM1DY6?0({EiTv{} z6;KLQQ{Ph4>|<$+vwhxq_7h%ZxVMTrOHE#bG@m+2xs@Z$qI#$aYmp{XA5srhAdOe5 zs=#ccOe~e??5F;rBGw^oqlT&ZRYr?nq)kdkYW&2{)T|nr%4ZEu$=T$2`g$Z) z)Hjq*Ez&aT9QAx1(v{TblxIECJn97XR0GmX>bTNS17=IwfX)%>!ME@%j_RcDQ_*ju zw~x9bVxA z#Z(_PNys!*V7AZHS^jh7_>dU6labm|joTszWb)FH}sFH$Sjp){};vqkMgr=7Y(h3!YWo%)@c_a0I~U892D zN4k;vk(zk`X)QIVh!&+%Uzu6lK)nCbr-AEAROI^ zN^WBE!4dyV&8TH*FKNrQd0Mu%SX-fgG}xa=A`2+9r`n+UQ~DF`nZ$)cbo za3M8I7HQ|zFQ>Zy5mC_fa&N=V@d8RMt_j}LpIfrM4nLB6Xw&loe%fst^ zEz*RApR1_#bKbD zOx`N3MQoUr7&WbAw+$orP@guHIEcP5AKi??CR}^gPME@-bvA-uf%78d{nx=N@FX}3 zu85R#h2T+e8gz@2Jp()l{sJzHmOUQq04G7)7}>+XCh#0Mf1T`afYsnB@IL6ZUd|PP zpMZaY%ifed6YK+j1sBE2o&a`&mq5EX*~7tI;Caw0UUpxw20RVUfh!Z_Trv15_!sD& zD0>#z4^DwjNwOz`UEpQVkSu!y*bH6(A4!qj53B`8z<)vSR5@1y9s~adU)&&jHaGy@ z0H05jJqhdvuYmUHvPXg~;5cZ#QFec@4m=~-vPtGwz*6uyco%#rL(b)ZX7DDsI8*jy za4&cjbjXrD3KZbi;G@~H2Y~h9C}@!*`>Wtq@C0}d^vIQSx!@pp3tW;XdkVM@`~h^# zmpvM61t-AA3ScCneoOXLum`*bK3yn#4A=%< z1RpPwJxHgmXeiQt7)>Rv;%brhW38EcFtvW8*$0?w{tVJSVgh3zbx<5sHK zY^T_4%BZHX4YOHqqng0>G227sRAY3jET`S(xR@$v<^bD2YysP;cCk&ft*NBCo9z~x zcNNtp-Huedil5n*S8G+f*8tOY)6UCks8q6j%jR55wUq5V+jDhPH?w`g=1@;Hi|r)a zlMPfiu$|EDdIRki|2EAWVSDf$x);qhz;>T4^j(_U&o;y6zk_Ng+a0#oc2aF)yQ$lP zM%t~hk!G&5z1&3i>e(){x$UC5o$VX8CCyYz*v_#%+d{Q~ZH&!cXw^s1ZlCLC?Z3OA zm7YswJI-d+Mm3J@FxvyWsYbE&v(2)Fyhn4rZ1>pw+O?YBPP_e~pS9h5-lykU*>13T z?V-Ap?I$+R4ytu*m)MqeQmtUS$hNqPYO!uTU9{UX-Bj|~M%fH|sb;W!#`eTMswr&8 z*yi_8jb%H;X4y+MlC4j-iC)?*ct6ebu-#?zJwSC2+wW|vKcFhurr1_|NOcF>k8BSobLyOsCR%!F>H5~FbHmmj7{{mx=c{Xp$jX*pmguBcq4(tf~Ml&OqVIjpip z<&4U4m7ZohVQqF6c`E%?4w;`4HD;qlo=A$c5vR@C$F#LrI+zYxiT=Sj_&nh_H0ze8 x7?gD71!beMTG^yTC>iQCQ`x3uDa}f@(xK!ihm>69jFP8(ucRGa^HIga{{ilaC4&F} diff --git a/target/scala-2.12/classes/include/write_data.class b/target/scala-2.12/classes/include/write_data.class index b7e68ea95d8a0ee884db4809ab1a26d079c72635..b2b6efa9eccf30bb002eb4da4ebf774ba50affc3 100644 GIT binary patch delta 3355 zcmYk#jI<_4CCop-PMXT2>G-`b`#jS>FQ4~)o_BxW-5J=Scig3S z+~w#!##uHo66q!Uj3G|hDL@CbOG98M^b?yzZ*_s++yR>yA z(p$8|dx)60rP^*wT>byf7Mqu7JBztgt={5WbC#y?6i;D}m(QQM`;?}NNMCV1UQQ=d z{{(G@_C&p~Cuna&;`9tcwSv{*BT^H?l>)`7#F(q|Ef>=NF!$7s9#Mi}Tc+XYg9FR0DOIn)NJtVN?Zmoce=$>^a;h zp^i{fO75wcZCxtb2dFF5f;6P5)E??fYHm7uaa1Gq3FVT3-b$*HI-xX?f!Q98QeD(V%A*LqL~18>R%yBjv#l;hyN3FJx z1JpI@K^uB&sC`N!Hq17^44ovZh5C$gv!iFEYN-#Yznt0t-LG{!(RM2LmRn&QE(H5kesk4;ti%3hTQE2%H2 zhw6}SqDGab>o8k!Jvt*w{!Kx`^CfvERY0Aj=DdtFhdM^x-GDTmIzs(RB{!lsK;3dm z&L*GU(}d16Wo*V-Cv}4g-GOvB^*!~(PNYrLW$KX@q}!>BR6wgtEv=aCoZ8DN{deJ> zgE~Vk*p0M^`k0#EhBTi#LEYPqG@E*xnk|r~Db)(h_74-w9(4Mtn^bHE(r)TkYV}^E zd#NcZq!Z~b>Ke783u&X$a2IBKcps8l>H=kW1!+0;Ipy~%Qakl2<+C5@M(QKVqZ?@+ zbzEtp8?$BgpfgOl_Tns+dY$^4N;-gEAN3~{a}eo%>K7{F5Yi56Qpvp!v$gi2GeIry z$5{h)iCQ{p_He8`X$moLmvcE5N)8oRl%rC>-9-}tK`;&lg`XUj zuqv=NB_-KRYA22O;3v+lkz@n%Ek1O=x4>fem~J1JzqUZ zRi6eC5u<~(#wa&t#s-Ozn0VFX-5}8(t9(-_33^AK+YzoGS+3 z0V zH-a_b$KYQo14NiZ`C+s=lpk!X!yv9Wlpk!x=9ZDwv3<*CSWmT*?F`#v8>p^lJIyxZ z6{;m{$JqilQY})gbtCOIwVaBT?L9W{O;oek2FThfD5kNw*zU5KD{0Qj_8Xh2ifWf? zLshg|#AYh3Y}eSrs;M@yU1oc#hH5R_c{cqPsugTsu{~N#wTx|8wVSoHTX7xD45=2{ zXb}Eel{3W(*^aSId6jA|+hMke^;9$24zm5rmfApb{cLw&%5KWndm3rxCY!N|&N|s{ zur1z3btl{RY>T#2ZDhN|_GB~FEo|r5bS+A?w9sx}s_)8{p*!fFgY6XC^qo}KvVF?t z*Gjd3?I_#iHmW&n@3Ku0R5Mho5wzPsTr9h2rjPA5TYNj!Znj_9mUd9>U>j!(@1(ke z?JC>CE~*Wx4R+CPPwb{r!*-TU`x@19wlCO1UZ-kjJINNjhw2)(PuP6BsphjCQEjZ7 zcFXRenL#!$C!M9Uy~*}BTgqOV>t(ye7PpV;9=2cDqV`j5XS=SNPcQA((n~XAYzzA6 zte)*6+nj!?)v8$?dNIKa5*bc9JBg*?f0$2{X diff --git a/target/scala-2.12/classes/include/write_resp.class b/target/scala-2.12/classes/include/write_resp.class index aabd9d2b4800d1a7c426da885a64fe28cc5a93ff..0f6590b50c4e2e0f7474daa1b431807c53d32a50 100644 GIT binary patch delta 3355 zcmYM$YfzL`90u@(yv(F%+$4+-i8a7FBUoBZfJCrd7Lc0=SO^QEl-zL_M9@G)pc2>v zipfP3&`c|mCbem5jj}$7Qc;sB4wVzghr%rFL)v=|`#gO)^E>Bx&c6TI*_n68#vRAT z9pC>X%)ug@!#zcHxU-lH^HsYfo;|N=G;)a;36HTW!0^Ak#gJk4hKIOgkX`=>gSMK? z9^yuXtLTZ4>Fh3$autS1KW#S}=^^SPjY?VeG&(BCo^(aY=S)SF%OpBmTZf}9+8Su= zkSE#`ri~$*R>ahC?<%gw=(XM4*kWz9#G19$7UwP;;xNaw(M2SyoqvRv=uoo7C1^dD zb#l#7>(IJj%_g&_SP&noig@-rNg+{IA5k6km=$^@KkqfSsaDepw|GO14LN4w;A zAfJ?+gmw#ciF!C0X(Uxg*{J(e;CkGspgyE-Q~oLF#0_1gj$e>UKF*LxFq%+% z`NO+HIc4LsjMP4Am~zNLZ!NWxI!paUJ+&D(il|f6l#+8UX3NP%`v`TNTDk>kD%D1f zQj4~t7eh5rUr>&D=!H;K)H$VzJk0j=D`*!}r>R?%&#UNdrh2Jy>alI;rBUtFH`L;M z^kS(-rNMm6_D}&jFHqIgdFn2;x)3)?sCTJp%C`u;T9)#-AFr>Y`Zbq+Sib@QomBq)*x-7u2TWENcT|RQ+|7p zR#BHJ?>eMr>MNz0Iyu|2CcP-!D?3s)%B>z}TdDJu(>|nG)ER1C1JZQr6!m~gYDBM} zx@Q+=>uy44h6;ZjX9uZURPY-}Tc}^CXWm5GNL{1+_am*P#wg!rnI<-4wh^_L-`lbl z+}loFq?WcKEucQ5T&+mAQ0J(H0%<1o0X4S`X_`_^8)m!DB(WWxKI$%IJb<)|`hyBP zi1Yw8MFn*rZKi&v)*M3Gpfq?0v#op!Ne%TK<#QNmC3T5gmce3a_bmh7g Qx(Z#0&T?kniTL^d0XP+Xl>h($ delta 3101 zcmYM0TTs+x7>5_~FoR&>3L9iIi50u+j3Q|@f|9{$VFkMc9FFI|Mz>}ZuWV;?|J{b?{Kl~;E?;^ zkoyOpg}W6B?+8Cp7U3<1!}aPZk?$6|Y#_>4^hd#YPTY*tijGKSMxH|0w89jnObtZoL}ip&wRF^&=unilXywyJq6?K0li_;p zi?O?2L(DD8jq4Le&0#K^9b3U?t+*Czbe$%~<-1<(aW>apJ`M}5G-{qEk}P^G8>~bz zXbE-EQ#`%Yq%s#gzcg5VTR$-+eu-)ZVUJgy^%XtwfhxzqIm_gEBX}IV4F)90o(8sp zKZ3rAvL}J{;APMwN%knP0_+7Jfg#J~ToL#Yco&?zLiTL%9q>1B)=Jsa!8Y(3s7sc8 zIoJU9gHuvuj|O*v7r=2aG*!+OgCB!`fkCTe&jC+>zk|=dCc71E2Y&*ed|mbxpaZ-D zdajl|2CM|XkaVn(c@bCwegfVD=cUQHT<~3R7ii~N2z3J2S5wwGA4EFAJ~kARLj_| zvdt=@YG?bJZALNGJhlsLJ|$E)sMb(IyG`9n#md&hHo27QDz;N(jxvf#Y+Y>su*Geo zxem6wY^Lp0TU6`aPOB|`i%J9AuWT=sQ>|gU!4|ZG>Q1)r*$g|Wma<)83#g!KWBW?A zu?l6knKed{yGxl-te0(iCEaDQon!ObO*NhEG~1*qs;O)z*~Zxtt7*>3_7Fz9wb#(h z7+b_1y4%Nghi%c@RO{J(VS8~e)oQluY;$X=?qC~a)7L3Ap^kRzSI^4dZDu_^w}tHz zn|}k<9JbHdv<|B4+0L?g3aV*rAF@qsq?)2yc_Z!ih)Y5f&2+LoU^6#UZDaeBEqou< zX0{Qw&=#t7Y(KLt*iW@eweJ12+nfVb%GthS3p_}*gzYlhGp$q$*e4F YY_CF%PE(|rttr-oX$ntIIvzjyKPy@fhX4Qo diff --git a/target/scala-2.12/classes/lib/param.class b/target/scala-2.12/classes/lib/param.class index 4343daa9e97c1b8c82ac49e3789d48d6658cae46..2d41b73300aa7d21a3542aba39012c1626392247 100644 GIT binary patch delta 23 fcmZ3zjdArh#tn^r94tE-Gng2(m^XL&E#d(HX#oe> delta 23 fcmZ3zjdArh#tn^r9LzfzGng2(ST=Y1E#d(HX!-}) diff --git a/target/scala-2.12/classes/lsu/lsu_bus_buffer.class b/target/scala-2.12/classes/lsu/lsu_bus_buffer.class index 8c5bb75008289b915003062d3d5c6e11dd8e8318..0eafb8ca1f2f67255e1ed5b248071782c475d217 100644 GIT binary patch delta 84 zcmexED delta 85 zcmex%Q1Sag#SM={81pAT7Rh6@*c>F9t;T4+d7ri7WFYUsIW0y;%gx*uLbw^lCMVn$ iVKOvmF1_7edYci5nShuXh*^M`6^Plkm)>S?Yy|-0A0vtY diff --git a/target/scala-2.12/classes/lsu/lsu_ecc.class b/target/scala-2.12/classes/lsu/lsu_ecc.class index 14440275148dc11af14a4dcc07673dceaad5d633..c8e3e981f30cc7a08d01a6694f226c16cdf33516 100644 GIT binary patch delta 2655 zcmZ9Mc~DjN701tc_uU1;ySXMV0a=5}{y;3LbwiX@G#Y{%2rA0vf=dJoC`gRCpeX9^ z%0W@Y1q`?aQC`$$rrL2@JFT@dN$tcgv16Ldn9?-UC27-6&wURkwtu|u_xwKR_xs)R z-hA&99m=5&<=s9f#)^Jt3C$K{Ow>gn3vOvBJbn;)<|Du+T-mW#Sg` z8_N<8EnPGmF>#wv+AXXRonB2MyS~G^T@-X!xKI4qt8X2(uvG*ev-Q$3OAL4DVo|3l ze$l6kPdZI(6C00Ptd0|w_`2UE&YWoW`qZvwtP{7oEY>9_Evy$$yt=E~uE(6Rwco3$ zr!DcrE?qo2ZHmTjUDTZM`EzGY@$WOb=ss)WE)m^hiKrf3{Iti!-6F5o5{XXB!Tl?*qT|znE%+t1=x2M&`SFAWi5;SA$P(I+E@pd7>=ZxoSgb|w+4`kd&FdB( z7r{4d9q?-AO|AzY-c&YVDg7Y|%cL?Rf=;Dl5S2z_GOu3ou3Q6G&{u%PQdll6_0ap13ls%ZfsA$IZ~AoNUd2sOGyGoN}G%z zx}SxCbSeR(a5LTIEx3gO+`NA)#kqO)236U%jRtI3P50e+NUAZW`$la@L_e&d=0wbq zwi{D@a8nLy4r9CLt3;gZmr({EL%CxIR7hi>(wPG5ocXZcNwC5B5o~mR4OQ|C*d#Z? zX8AU3QDoSvOn^6(a@eNyL$z`jYSbp!?%DM{%yHm83ZISR*b-*q_t^?(;B{>E!B!t^ zrQVs?L3gKP43*EqWHGJJpU%v}dKx`*1mOXyOT`|VHH*Q_nOK2sG%y>lQ)uc_aFD)9 z!#uw-@Q29&S`{swgHxnBBhvQ`&&}c7)Qx=K=bz0@oe|~R5;m8AnL3J@%kil<(tOa4 z53jsi##2x_-&t?0uzTL@OyMa{rgQA-=}tO_X78M*q1iE#*l$C#gNidaG&_wX-__pG z?0gz*4$XJCm+Q;RP7aQp_is<{q=rlkaTpEMm5FIiqmhHq9nVk0EDp{tnv{iM*hHCG zI2Yffy|(S9du-H_g|5-c3$a7W`}_$S$?z!HL&@2^>usvZ#xR|o8uOlgNag$G0itR=fxjeJaswPjZ~0?Mv*L!l>_BkIY%y#i`ZM_WAX|1 zKgs`5P_9*8Q%aOl_8%!9C=cXXb*h@9&S&4KHmFVPr`17qi2Z^3nfgSo)dI8-Eu1|~ z%hMKn%v}7^L48wj*i*g`{nW*E9MO7?=njtPPL5~;N3@Y6y36?xnwU@dtSn?WfnkL5fZ;^mI6=9^Y!b6bbw0BwW|P!c zm_;+2$S<6x#xRRk*E5S{7Nrg`i(?k6b~B4-7Nb64mcT4t{g9cPS)3NmERmU8^Jf;4 z#4tfy%y2TpBrTO;GP6Yct?~>k!wn9cN1=t7iMdo-h^aWAdTd)jpRm!{LL5aYD=?8B z+f_AJxQKdIaBJ-f27j|b9!)G_@Yn{`MGW$(#|CSQ>>Ui~tX-uPb3m6-Z82u!a=L9> z0X?^ptECoMMV9d2obbK&ffT+LRcb52 z0!9^fl1EU$8eGa~sSh=-!BHsa&>D!m#Z z5hB~#=^-1nm-2g-T!u;XkzLi;RcIMkH_GrbcG9|Xyp6{_2^Dy6OyfL9K4^||$aQqG zUxN9LhwQ_!KpGF4sO*Jer5#o(j~k&_P2nI+V^3qxXXgWI6?-*% zGkY8R30S4}!D{s%uu97YOYF-vDv_lV#;9?E5totUDaaZX7RTcQ-lepXlpe@rs)(3!VnLc?+F99iTS1}s@k05 zbJM^bVr!czQpqVsv>RA0y4p>yF0$%fu5OXvVPcc`!dLfon&Qjz4l({ngO9hEhb}n8 z;;sgf*y9wx>oTxKY(8powRM}=D#%xpdQ7YlcYJk4uPMInbBgD^hL26h{ERy8r+0`8 zPZ(G$?w>HxBR2F|_1|3Ugg9x6@11grsizF_`_oSGqf-X%7fVl@V%Hg``1@%?=x3ec zz!?J@MetcuJnL|Zt7i>9!}N3h-T&&Gf7e^jTf24$wV4-;Yu8BpW`jRPrea$IC`VAlZhnR8MfB#^Jl>-L0i+>E5Tn}Ec>bR>`z3!{u zzGez-&?%l=GekGD?z(}UB4E(OBcf-}6oogOVvg6qZt+8}$+hT)RsZU%#!VA@MA$8> z4)|*3ZN9$x@V2rE%jmbUSV|uz;8XTXQF23~r{LB%F(t^eOjnOM5cTwO8q5sBu1@yf_)7?OXK_ z`e;6mq2tLIi`(cP55esel)~fRro-3bxp*_36IN zP;Dv(U^O+Q@@d`r>(*JKY`WX~JQdRe=9R-E*kG%HjrNgHAx(u%QZ8(k2r8vt!WQXE zsFG*ER@npFwQkm_gSQEZ`cb8r+Rc_vmf2Ik;R zZ1u}lzig$i(r{@&IRwH)0IiDh=Hg^~jUMek^O?DvpBg@_m7ig+=BGxF^$&?i=YLBL z#iw(OcI#<=X~l@|d_zJhB!k!7truE7Uxp^*ZtBh8`0b{<8JLZ=G;AKm*=spN)(5?e zPA#pP$ICH`D1V>7b(#Op4Sn;$P)`~2F&+0&gN6O{A%nJO;c(yB5Ngcggr#SpE4o1s zeYuh{oL9N?N``{rfF4fCDV)ImEKJ2l`b`!;B8_~2DoaLYvph&kvT*_)^j2r%G4!mK zs-*3*Tk4apNnY74tMX_$l(|4Ilvgtk%17m1<`)VmcG;~gQ`RYE%)83Zln1g~ou)2O zbC_GyJ!(Dkqlehh~-8CtYy&`KYyz@K=w zgQkvBT=1Gy1d-}!aKT8)%We$2(b92tA?!xUq3lB0g~&3yFm_|))$GQy3zM_ig|iEl zd)Y;>3zrYD8^>;}VrLi0Zk+s-T@A0C2CRZ zQrV?wLF~r5SSD+EEGM#bX=yAcu}ig{PjCN9++@Rr6jp$lxQI#$a5m;ppM}Nr*ut9> zUC3BMB^H)apM_=g*g`Hv7crJoiG>x^XCaRsTUbfat8f|S)6P|xg$48j3xyQ0no;Ck zx*7*;;bnUG%ebre6K<)$0C@4j+(nVa{BCUH*F{SShET*hRH&&K^RbQgtivb@EWtc( z=UMG=3R%xTHEq;fg7J)-B|NqLm8om6-J0cQ`Rasr|Acm0vYsDJqP3+sg3hi-7p*D9 zZ_*R%>ZEn$Dn%C_vHI!QNo z&tS2g^JPzgH|+(?N?2m&zWov`wR7M843h%w_TfwUW7m*}!aOc0;jx z4ocL2La~+wnzo3^8`sL1mCQP31G9^Hf_WX*X+LHD5!MH2par}JWdSo_SHN4)7Wfxv k4>|x8^ke97j0lEK$8tF0=!7oEC(!LY20h+D52}v;0w1|M1ONa4 diff --git a/target/scala-2.12/classes/lsu/lsu_stbuf.class b/target/scala-2.12/classes/lsu/lsu_stbuf.class index 4b69755680828ee16262b1b7d71fd958bdb2a637..e23ffed74e76c5166c4dcd717263416bed5af68d 100644 GIT binary patch delta 37 tcmbRFmV4$~?hP4SjLDNTx$+o|Hs9cq5MwlJ{;1IYQGs#$M+K%8R{<3}4!!^Y delta 37 tcmbRFmV4$~?hP4SjK-5Qx$+pLHs9cq5MwlM{;1IYQGs#$M+K%8R{;(Q4s!qi diff --git a/target/scala-2.12/classes/quasar_wrapper.class b/target/scala-2.12/classes/quasar_wrapper.class index 0ebd3f7093430647bf87a0398b65ba82d835747f..f79edf05e235440815793b7db77e6f87b6ede707 100644 GIT binary patch literal 86838 zcmd^o2VfM(_4n-F?wxcRm6JqSxjeBp{ zVBCA}-G9e%i5<7Z4so2siJka+Z)SII?{0K#w2n)@#Jrh(``&MUGxK(~+|20Nf8YBc zA!M>AUm{7Hy91qpj+(6y^eb_TmV#3PaP@FFI5)&*Ju5*bp; zGT9x$hL&JmS9TSutC}0z0$tr5!C4YfYqxg=J0;H{Zb@yemt;?pNr<&rbBi~`98H5(r2EBRd`eM{m&pQr1mfj(m(*Q5P%UB4Rj zLzsSZk{a)7=labVGkm@jDML;x$@CY_*iukVN4Kw--C2;YtSB4omItdd{9{&4+uYpH zHCgg|RjFuurK-wlGiLa5MtI^}W7jtOGTd(0ghS#3Qp(ItHI-fI!=*$yIkB)`+uFR= z#*w~^`eG?A;2tz>;>yVleN=yHzCU@Wsx@~ft(w)kXdImP#Jl{78+;k@Zn;R+{1XS} zdR3oyL_nIhp(x)M2rl%<(?Q0?&Yd$|k?x z7f{Pp*Tz;~z`tZxdr5AVr#633j;erXh2$;q&fZ$Oc4qh7+^p1$8YU-~3|i3Me|AIhviQw$sytd6YSa$Nd?M66A$eWZ}^NHZ(^N+}7p0#y3KJYm9bDTT;4w;((d!t7c}#)yg>rUVP)6$;Iv1Uc+Z(BM<2~f2Y*J=x}2uD zm6={XLClnkHYPtke%i>7S`-pk8Y&T5)FoE9goo7A~zKJXc)^YO>G z1)$y&2IOw3*p;@TVhuYF5*JNve-oEq;_r$~DJ zGhD0k>NXD9IjU^!)XmMi1}@0fW^HL4?)UjzM!Usrn46@mXzxFzb|vyyH3R&Y8vaX$ zubxyNfVj2rOEmZmK4j{5FLBpHJmu6c2izr!S^rHI+^Naya=JH`7ef8xjryn8 z80|N8XYqtple(JSnJd}{L;V&R^=sbTwjy`)M&5q4(BI&nVE8Aj_LfddUN@<&CN;}5 zyuja&@$&ooyK;O@?fqwU79?eDrE8~lkB^U!S5%igSq)a^`~3s^#K+Ib^eY?ICe<%b zUX|yKS6fq;cx2kVkWK?0o0nHYyt-6*o}Y~eMXr(B^aWfzgr}+}%R9Bj}d88uCrDJ_QUx})^hI&_yl$4H*?m_*_*23{<@7VdwuiBpxNS901 zj3qE`X1FH6II()twxC;y%N{VZuc~&tT>1VBc#0xcerDv{&}D-TJRNJ^xsL`H51 zYzbty1lk(mfn-bj#$a|?u&b%PenFtEz9rb1S=!#dv3rw;^aIMVO+7@Dh@0C>#HT;Q zWOi(+YuVUT-;wDdgCr7f9sWYfm4e)?Bt9P0?03BByXslV@-cc_R zsRVkZV~gItt?Y>u!mu>dQTi!x13SHAMRxirteW1ThLz8P#(ElT67m;R*Z2zyD{B@2 zgV0fF1(d_iRaW{}))W>ku3i9*gPP(6VC=72P?IAOYAC8oRzc&%;UUi^$ zj7L`BM6}MY_7~U8uP7}9>gF*=OUGk8m0MF%URbn(5zx(;B8Ty3Zu&766gtk0IG%U=hsAORN%>1lN(*cJ3-TdQs-do4U9qBMG6bx7P*d)&E?EZWK~+_=xUw1> zZ@zzNX*EPGi#2~iK~Yr|Ynw>|9kgncU9LcvC(r?tDBmdp-Bf{Y8ibpbUs1U~zqAM# z3bepcpaqr!E$|d*fvG?XTm@QSE6@Vpu)3D{s}@DJC+Z^G6Lpd8iMq)4L|tTiqAs#M zQ5V^sr~`gUg#`s=HTnMXMK$>))m1Qpas|sL^Zd%{qMGF;g?M#w4eJA4!vTs43JjA3 z=ES=OLW~{Fw|a04evR-lIY#+XP6SABjLM?ol8SPJQkB23(#*3*%Rn;u_1E(~@tjKQ}@=Qb2@)k4j zSi9;YU%Kwhbi8@3MO(YTtD8c%g(_%tS*m_Aywh|g$Hh8QT~k_KQ?)A8EUXuSD6~|v zZhuQsVFan+8Xt$Dkv|kDTVeA8SnwkU{Y1>uZEF|SKaW!kyx*}(QK#+Rov(} z)M7&zodQ%A`wJE^MR@E(l?(;e5Q;YrL#Xjw$*vEm4j35i#*cUnS>@pz_tT@CSzDr< zL-DrY&Su0jQ$6B&o<+R3Wd2f!Z#|xk13jLNLl)1zl5&XWh;ckphvQD94#%BHU7kRP z<4&XaG~i{p5-7RT{uE$|d*fvG@?<9IXzj^oi<9LKF%96NCw zkJLrBC)!1}C+Z^G6Lpd8iMq)4L|tTiq7M0$R`?5Rsw--iRu$DOE?rs$Ts);!OLJkA zg9ib~h2q9I(BsB9WO0*(M;N2!`G|a9_S5y|lsKNY`WUN`{*azR-i7zKPW%>|-O=6F z)!Z7)uIlROu7i)VftG?mOG_2J!g-TX+ZwH! zFvsfcn}V@VTIuVq2EkdBd_X?*lK08)lHKGZ_?Qfzw_CPLBoiuqu-bw1@5v{r@QM6W zcw1^{ZmXx{bMg+NeIb#75$@PjmECRC&{FXF_eY5MvWmi`rA3+WAw9Avt1XoB75P&< z`H~!fwgk|&8h8N-#*we#rm!i{5oisrReZ54Atw6k@mYV+u$dW9%pmih#9uuG~o7(FO0(DJ6i2UJ^ z{Sp=6aFKYp510?=xqKY+B3d3?`-fEFd_7Wv=n{tE+1-V&-)(VHQaD>Ur4xZ%^u-T@ zc*2G*csn-S)56{1yzUOUXm=RzU0rn>p&?gqJN zw;5)U=nHXREfP-ZzK~19Ugj5?F(|{GIgWi*fzJ$a5>zSC8iIIM4=>0H+@UlNYvJbl zI0+&u%o|P`-jEe|L#Tu~z_H-~S%CwFNk@H6eV{84C*jk$l`Nbzydf*_h8PKbL4pv5 zSF|tyIBx(zRsaBj5?^22$iG0vNo5iK7;buNK~~@o&705>Y=qBVdKD@o5Wv7dfUE!k z;>JLLL8v26S{{J_1_lCT1qcvAZsZVz23Ql}4Cf4I$O@bxhT`=Kpg;UN8rFaqiFyMF zqb(PLC<#CEH3gs-JMfp+IH@5V1Z{K>%tn*Q#jxU6b$xrBv@yax6m)1PaEHi(s|-9h zMR>f*7%R2Xo%5Jh1Qp#Z~E0&WmCo|ew;n%a)WIO)&`?@)N<3d1WG zLdMhFpnD$?;T;Msv=fvK;o|PBBc&zsXW}{2UgHQ-_2t^5=5;#BvggJzQBTpC{c@e>Z#|9-~aO6P* zc<^4jC0G|HT^3PXC{oZ)zz-v(4Xz}Z`Vc2w72zF z2!W*Lnz~Kha2>aF!F9YjPP!!mBor}u!idR(NJ!)$@c7O#_C#QW;s&h+L?Adk?B<1c zpSvTxLqU`$45G;pDXFcS>T2qPwcU-Ds@xwAgm!vQVm6w_WQZVN2*|9?BM~^Em_rW% z4g?m%VFP20iSuLxPAC*73qx@-#9I;@MY=m{;I__&`sX4*Lg9(#0x}SGNo+8&fV><5 z5{lBv!YG{#(U*ib%vuY`8xbI(U`2BQ69_`MX~5WG0eL3^Bowogg)uuBf-oLm51ye&fvIy1b!}af;^e*&Frg5hA`Iav5R{QHIdSs92$)b5qeC>C zsSucvFu8H^uy7c((jytO0vHI*NSM4hd1M4kD3+%}*3-I?&Gv)eu;J^9@gsHEug7t^ z349dE8DpA6%@>5vRswe_kC(F&NSr(YKF4&y+(h80|9EZu(haXj2`~uc!Y8SgV4w}` z#*~bO9|WXYxVSARp!~!!#?QO6z=X<^;4lOV)$X-Qj`g;+im0mXSu zW5668!Za%&a-;H0c@~y78wQMUOL$5Qbhfm&HFE9?p;`HHB;|!v_RIMQ0xxPxM{pDT zW^QV-Q+5eN4%!P!Z;I z1Q&dXfB*|L)z);ucPr?VkQ0Mk+cX8*+JY^e&cm&+>kTu+>6rjjx_M2P)UgL8Jfi&IZBsFtyinD$*|0dxS$Vmy|}S4njzF(0HK#_fI)SqgjzNnDEugN zjp&s>RNje|KMX3`u_d@A*j58ydYikp!*|I#c;oiq7Z`XHg0YC}Sw1b=6l!`DhdLS} zEbKhHKz)%aa5#=P&GGoHVM}cXv|12q=5B9jfbRuxftyOOJ(+`_!XAw}VCq#+XEVnu`CT*UY< zk)wVjsL<6cDAlaK;2d7*GDg1}>yFLf=?ua*=wQ9sAiUbpkxK*}DS(VsTtov<`62mX z>?Qb`0GD5=`D>=aD-DjQW-oyT`s8umCr_B>oE$T^IVLd1QCEUqmI(*d{ZFrc5ipgX zk)Op1!WRmtU}(&Q=O^}yvGJfSXvdPU#=B@vxT-TVfFqdXPj~2jyh8T=3q4JyZTZsEMyEAlc zZSSmuS=0C{!4~5Hg5ozkDBh)H3Yi*DWcfWxrjr?%`v4wt!E(Nk0@nMr1$ z@yB3c7-zQZ*p6j&cLniRdSJec%Ad%edcp292FhoyMuKu}Cj6{Cn;e3me`KJ#+6qeL zuQ=SF;Ns(RU-1dp%8*ZcrDP77i%@^TcSSzyIUMM(9O!TGn<`W<6aUq~(**o*U6aY? zdKnXjYchlI_~siEHc5Ea*kuw~9j^NkpM?>9a1?}^JOna4ZrUzGTH?gvWp zSDNfs`!fxxthy;kludRPtN~B~?5(f|6>U8%fDho*PZcGM*bt$#R|> zPss|Nn?T7*p3A0W70=~RvYO}eC|SdEQz%)>bJHkU$8$3%so^;Yx%E7E2qgiYn@dS8 z&-p2-Upk+k|56&Q_{e5C6qMs+#*Vvc&?0+W}d5{WCPDFp=2Y^RZ-Hyb4w{{ z<+t(5HIx$Tr3&U1%Sas z3eTNO$*DYdJ|(B|+=Y~!&T|)2at6;`O39f#cR3|z@!S=ZoXvArQF0E?T|>#aJa-)> z=keSPl$_6VH&Jo{&)q`Fg*CD-xXbCg`qb1zVG1JAug z$&Ebs3MDu3+-sEF%yVy0atqJBMaiu^_kWb!#&f@+EhTsG-20U5;kgefxs&HU zqU0`~`#mLldG1q6_VL{3l-$j8f1qSP&wWYBJv{d(O77*kKT~oa&;5mx`+4rKlsv$5 zf2ZU@p8E$S5Aoc0lswFH|Dxm(p8J84M_EphD0z(MT$DV{b1EfI@SKN|CwVTOlBaks zfs&_rE|HRFcrKZeXL-&?$#XoHM#=L$*N2i9c&;BMFY=s5$xA#pkdl{qZZIXU@Z3;J zUgfzAN?zl+5tO{nb0aBvgXcz5@+QxXrQ|K18&ApGJO>{X*?o&mw+h|4aCL^h)`QGYZ_D%JsvQw=o_ED$WH=V{!#~q|y^~vu4iLu_c_K@|~wP&oiuRUYEh3y&Z zZEVk2Z)JPNdOIJiqj6&VBzwJwrZ(djO>M?6n%azCG_@JOXlgTl(bQ)AqN(1lqH&9_ z12Yzh@kSjcigWyCj7tKziRiW*v83!EhM`4E+^|P-<^nWsC%UCt)}?VH(Wn}^Tph{kueW-fFG6?ZYfS);l~BRv?{ z6(SC2K;oQ2MfTVp5x1}&*@t4UM`8!N%bCkxc^CCqR46WmgM_(Qmcs~pP`8PFSF$Xv z=MNebX2ZpVl>|_|+iB!)K&vjEB!i(-;q*k)|;oJ|j(IJbXr)#&~(MnjZA! zDcU&3%Tu&*jF+cqW4(QagO?>1IOiBIPtnLRUY??jW4t^?8^?HgvKr(2K#Z5CNK>2f zi>Nl^7fo%(FPhqnUo^EDzi4VRe$g~WyGE_d=HtQ;!LtY~qs9f>+(0y>;W}%+cA49V zhBU(__K;>+;VqNhAVlLn8sV_d7lU&<(Q{seo#hEubPGUhed#!d6y2McQD{XuHxv!K zQ47tvsi^fr>(9B3=t&}MSvofped{w;tH%a17qQ3YWW62sR9NU%*Awf|%6HbEqG3s} zK%O%bb$1eCO93jRTm{=$wWN;Jpb`Ma-%LvvdJVo{}N0=0C#=2E=qDpE~;OpB#%tS-0S$m zdZ>6d7kd_!$I9bi&Vce3FWn$l2~&wW>SqBt+ezi=vBT%lkp)=#vMvD%HO?!^)2ix5Sn5WZVIy`urL1UC5rMLOkIQ_JDdHq;!$8-hdUEH59Y5V z@%bz440HKGB?-#ERf#G;D8GfdEUGJPa<5?WJ(Tl#v21pMuEi!- z)8f@sHJvISE6*Wd-(P!{Y8Gz99p+B>#;)FHqSR^3^25;@Mg6+zhM6ybXhTDPgNv#W)5-vxc&4eJ&O zQF~da!_*9~I#eAFl^(%I3trXv-EDOk?vtR2ey@&9C6YP{X3z1Hi#via0}9%73^cSp z??%_L79AI_j#bA?WR%efu=;^-_uSdu-BA~8Zfj`Iu438J=C+_moe)Q$-}_k`MXzlM zPNGrXRVR7Xi7H&!-sV=m)g*4YG0N&7sIIP}YMwgT3zT5_j}1yCz|Nz>%ACFi{qU>C zqvDd8`t}-q;}4h%8rf!Mob_CBEG0A{ExZIvum`un0w7og*VYA_W#V@)j7sBq?re+mCYiO~#nN&SpJp)7QOez&~x3ggw zHtH6dH||l-rBW%kINt)i6@jUGAxF80N=vxSC0=!>+6?tK7~tH0s$S0Rc2j8?x4ROC z8p9;mM%Al%q+dg&)!g7ZYhfKQ?V74LaGM*cw4U4COr-{{yOl~ouDhK|8+dLHmD+jk zE_h<&H=li>2fDIgtM$U%505hIC|6NLE$S~lFkqkisHzd&+IGpjG| zY85hp=Hw`URKG-&uMp)cY-oK!89JefNBy%`{aS^|UDfg%Se0+6oFnIA4kovUz>68;I`#sy$(f9z4ehsv2_j-h6E;eW@g|5AT|U5;TQYLrFf zX2{^t*DZO~f4OB?B)62h6}Tcunp=f##9Lh_ZWmS2Adz)H_IPJfW5XwPd)#qwjk@7^ zAWhI59(RJ*O|e(lwj0n;)SblI#|=+?xE%&l`M4?-7e2v4bf!y(*AlhD-3M<&rvEk= z3;J6+Hf$Lnb@z8`=re#yJ6J%u;h`_xq-9w$=y4D6x`#4cT!RlV)Sbbdhg0cr?hMb; zj3J&J#ZQi=(lPwxSc5B`9na5ZQRzf}b|RHdS#n5o0Is{5$^*IXS}G6a zy6dStjO%WsawgZ^Oy!YWcPoq>Ij{o6vTxZz-=AU4h6<0GE#N2R>Ul^dSXsgJkV=#F zJfspl!ZSUjxc3#yLn^`JI?F>U!D@Jxhg5<`b(V)z&VhyL__E)E8Tca?#t~%X94M5Z zgN&R5#quM_$T?6jKZ1;$14Z*A$jCWRI6s1noCC%4Bgn`(K!6`XM$Q2W{0O<=PD$(t zGcs;`#E*~*Zf3-fkPB{F#E*~*ZbQV6kPB`r#E*~*ZWF|hkPGhn!;g>)?&HIckPB|o z!;g>)?!d#2FeBskI{XN^;NCg>2)W=MIs6E@;6^w62)W?KHT(#<2b`_z`l!4O`d|X5bHp7)QtjH&5Z`kPGgD!jF&(ZfC-ekPGfh!jF&(ZZN`+ zkPB`X!jF&(?*74#kPGhP!Hk;0_u52)W>17yJmh;C>bS2)W>< z6Z{Cd;MNiR2)W??5BvzZ;5H8Y2)W>H4EzYW;HC=f2s1M7jlho}la^Tzk4pT@M38@f zfE&#;>&uh=-fw)r2-b5mc+ZS{1B2^vD1V!UEk4*Do!qoARD{O^lbg>Lz{3}grpP~@ z;N$~_;JZi|qL2XYc1@S$u+5^@ENdW87vybV_liTE56v+S+f&fFG^q| zfe!ZWi<@kE`Nxj=@V7BwHCZKZ*=5aagG+x~TRUvXf`2dr9`N9;lka@WF+r7Fg?oFJ zw6y>i{Ad7gv`ho^Nd}RL0{`434wfRM;%8y_V3msBe_0COd07e{c3BFaby*5)%82Bd z3VE4K1N-S@2ITW`(HKi%ofk`Ckrt$>xQL0Rem%|C(*iv$)YBq8ov)|Gdb&VQOZ0T1 zo-WeUQavrx({eqn(9^|wxqo^I6B7Cmj%(>6VA z*V9dUx>-*<^t4k?yY#eMPq*mlRz2OOr?8}m)dv<7u@sgQu@n{)u@sgPu@n{(u@sgO zvGfQ%JyK7P($k~$^cX!oR!@)9)8qB@1U)@bPfya*llAlzJv~)VPt()W_4EuqJyTE5 z($ll`^c+1sS5ME=)ARN80zHK#L99NoAc&=~9Ehc`7>K2?6o{p;5QwF)42Y$>_4Eoo zy;4uF($lN;^cp?AR!^_f)9dy020gt|PjAxGoAvY-J-t;=Z`0G;_4E!s-J_>>>gip2 zx>ry4>FM2ix?fLWNe`FLvY`i!1FtEbQD>GOK}f}Xypr!VR0%X<2Xp1!K5uj%RQdisW*zNx2g z>FL{;O1nusetaadXByP%P#8J!^M2O7J1UU?VRrvcmZVCSC zA(&=JaT5HT24}L!ZzM1Lu7JZVyjuT;q`-%7_^PLK+NpDzAm)@NCHIC@frZo>~B=nbi&u$Ia+NsWv}3O+I0B{jx5sj()haj{6j*KWI{CiI5X{IHgqXp+i~ zMG8K=+a;CjoK&7kYH}=6@Ed?#Qqy`vsyM8rrkkW@#3BVhG}t9IyEmj3gpoSLBsC`% zDfrFfCnPn`B;}7q3VwdEORBIpEmacMQbi`I`LRgBk2`irmGp+x!Z1<`O;U?uk%Hfo z?2;;XPO8ErwKx_j_yNlu}HzMWp+ue=nbjTFj6Z`QmbN-f?w$D zl3LpvQe|PJ)|sSgVv&NM1nrWl?G35&Fj93Usrp!?;5SLTq#Aoesv?Y3lS!&M7Ag37 z)Gn!(-jG@xMyk~$)fS5s{8DR|)Mn?TI!scXu}HxWpE{}k%FE13OGAy8x^+$&(iWYQ z@MQ*mc(vP5y&5}LTS$$OwwVpJJyt`(k9T%S?d(nOHH48m%p|od7Ag2q&@QPXdqb)* zjMPyksiR|&f*&L8k~*$8q?*D=9dD94Ar>k44b(2FlY2v|IgHdPCaF_nk%FIN?UL$M z_qBwPI^867Ml4eB%dlNiy$bZ!Fj8lkq|S~-3Vx)vOR85f)fPtTT$9v!u}H!1<#tK+ zDyG`QNL^r(x-b?g`03s*sa_49Tf<0QY?8Vp7AcrJV3*Y8y}A0fg^}8AlDZ-mDVV%q zm()HNolYh#gu*%Nk2-Ow9SJHklaXp*`q7Acs%VVBgcy&-j27^&M#Qn$w< z1@lMjlDe}uq;`doy2~WBHx?gX_1kC~(%k3|aR5ZNX5RBuQf6GrN3lhiY@NWml~yQH4)4XNY8 zNWEZ^dNCF$m_=om)GNIqb$l49S4~o{#UcgMxa^X8vp1wp2qX2DN$Txbq(VOz9rUM} z-}HvmiD9JPHA($87Acs>X1Aq2=nbip!$^H-lKNdNQZSRwE~(%5hSVuxq&_i8eHx1t zOy#pn>WkixIyH>cA52nzj7928`=tKV8&YS6kvd?K`g1H&Fe%Y)OMTNDQs;z``m0Im zZ?Q=I-9D**^oG>AVWj?PlKL(dDVUaNx268w8&c6gkh(C8RJ=*b8;caojJ4ZRiM=6pQ5dNtlT>mnQZO~wE~(Vskh(aG zRGLXDJr*gL8*GlY#lav;V)ByXW2K9#2WnrWSo1})sA_cRf?Y2}#Z%ADp zMryc8YD6qjFg@EYsZqTlwL6T|Xp_{Ko=Hi#avUZe;`Ezrm>GjJX4G-}<%u}2Mz&0& z@i1)44diSYXE92+YDTZoOqfiA(`nq}2JV-q-7NI(%Pn+ou$A**7LcS*y@7)ifSfMR zh=LryUp_=kNB}9%iG-Xh&x?WtmW8+Uo@J3dUxzG$nMG`2^0@rSsTR5*amVjYll*~EV_h2`{gRTC6r^^vJxuf>QD*gP(lSOVX3@KSi-6w zt%TL`8oh+D@K`S{Ai6J+xEUUtbU?1vA+6!sC`JqmS3bE`u7enBlAEJ=L5#JDQKETm zu*TR1)|l;L$PNdPonpu>4j{M6+oHOBJcR8oF=lkwZpWIlpxR*#+wBlkJ6Jm$-a`q; z*e&4*vxFn9B^&`I9LY*JR@^Knhzp4BJXU})<^U|j!-+kRK2?kv-7G91ShJjDB@Lk= zpTtTyO+Fo_DdH%*7$y`dkj9N0IB3Ft`FwE^r<`UE&DcFD4cpp?k4Cj0oM!An%dy)#GOka6vX+Ug!Ptqhi>}+{&!4 zSH53wX0MC|V12#v1CYb|dgTWpr|7YCA1mCa$oE5?fPnk}{CkiQc}!flC&eUe)$J+y zX>kBOF9wYcAfsk+X3gSw&5QuD)B`T}7vvYCF2?a$gZIm?*)0$+Jbp2rsW&CRERBot zC8J=t2#pI83VvOF13EVHS?mAAPfKApFK~WG-15H_bGFm+WQyQsdYAmZ7%_}b=w?c$ z3o3P&{Gq){{Z9T!Z;=9MP;Anaad*kTe~Ng<-7SBPStP?Jc)N&{(8CjHiXP^Y{Du4n z0pOP$@BjdQ`5yxQS^io8_zegAI{<$39|C?W|3i<{^xHXb_!ruM2t==Vmk+Tc_kcz0LVethe z=L?--sI}uv8o=Y>M& zRC~^ggwE;qoJ)nyeeF4y37z}fb1oM;53uK4A#@&O&v~)Xd5AsdB|_(6_M9t)&cp3F zR|%an?K#6PA5pj6yIiB}IWHADkFn>xOz1q$p7U~{bCx~l6+-8U_MBG=ohR9IUL|zS zwdcHA=sek;^BSS^RC~^Ah0fFMIj<8s&$Q=UBXpi^&w0Jjd5%5jfY5oKJ?C1XbG|+2 zI-zr+J?DC%^L%^GL80>kd(I6)=Y{s18->oL_MDr9&gJ%;n}yDc?Ky7{I#=3r-Y9gg zw&&a;bY5o9xmD=A!k%-R(0P?T=XRm<8hg&0gwE^iId2v^ueayiA#|>_=iDiDuD9ph zC3J4E=iDuHZnEdRMd-Z2p7U0rbBjIaZ9?ZZd(PX1&YSEx?+`k7*mFKq=-g$`d8g2M zi#_MVgwEUSIqwoW@37~5xX^j0J?A5Y&b#b6A1QP`!k+U{Lg%CGIUg-_KE|H&F+%6# z>^UDRbUwkJ^KnAwlk7PkFLXY|p7RMp=hN&tpD1)b!=Cd=Lg%yWIiD^Yw*biTlz^Jzloi|jd{E_A-cp7R+(=gaIlpDA?SZO{2Eq4SmYoX-|IUv1C%9HH~I z_MFcZI$v+k`8=WXjrN?+7dqc;&-ntO^R4!rFBCf8ZqNB5q4OSl&KC=v@3QB7iO_kU zJ?Be>&im~-UnX?E*Pip`Lg)MKIqw!aKWNYS3Ze7E_MER2IzMX9`6{9F-L;)7COIa z&-oUi^V{~EZxuSfW6$|Eq4T@;oNpI8zh}?+4x#f0_MG5;}ik z&v~!V`7?XY`-IM4*mJ&H==?`}&ijSVU)giMN9cUOp7Xsz=dbNK-zRkb#-8*2Lg&BP zbACYR{H;Cb2Zhf6wCDVg(D{3N&JPQn|839t5s|Y(>^VOwbe8QoKPGfm>^VO!bavZw zenRLRXV3Xbp|jVX^HV}+YR~y;p>vWw=Vye@DfXP76*{NdbAC?foNmwgd7*P(d(JNi zo%`E!eo^Q=z@GC~UF{IZ4^9iV#qZPAZx^s>l{F?7elUh02vTN);fT!6+_lLfUFZkHaLK+7eh8VfDDQuH#mT7 z5JR>&fNT^)wmE=o5<_ls0NE^t>~H|NK@8dD0CJ-ka*G4V7BS>D2av5|$Q=$K+r*GN z9YD5=A$K`|+$4rP!U5!FG2~GWAUnj6$2frO6hj{80J2LAd4dDTZZYIZ4j{LPAy07t zxm65#nghsfV#qTbKyDX9p5*{?hZyo42atz~AAS40ptZ@$d?^JUMPlq)dA#1V#wDWKwd0{eA5BsC1S|89Y9_xhJ42XJAiyZ3^~97GzgPbK_{Xjz?(vU3bO&s^tB`(V5ZLlPmlKKWd(zKC ze|;2|F-jk%O_w-|dyZ{Lza1YmY_39?e+fFf8(;z4A9d zPLU~^^067l!&tMzR{ZyoQ7i9OKEaNWEPGVX1?x}ExD8n=pM&)mk=FCT`VVHHTCBeW z>#riM{X|mUH7dWjn8cGq3F&j&xIM~W_bLClTls$6epQBl3jFhogN7In4WWAXsYws3 zDSMS?$L&%3+^dczWRIG4pE_}6nwp(5HznZCOBoo;Px*YW@-p{Z5a#DkNssCG?t>#Fu65Q)?f3Sgn6pZ7?d5pV9|_4gMPdqh+7kT0Vg}w@)yg6J{!!5^~29 zW~!RX%rr^BzDOpQq2uEni z7K9WnC88vs=3{n8X+Dcxs+JmE(tL4AX<8aXI7UmeAf#*Q9D%o7*Oc@-(np3$L zNZ~~>bEr0yVO^>XwO|d?hK2YWSc}5q{W7y!R~T3sS_Z?qO3Scd4cCT8W0j`#x9|#K zU29;C&_*z<>$MRUtV}I48mlZUlJIh0$eQ~m18bxAxW1_Jt!g?97V0am;jb-k4YGW<#<1~ObMlqwL@fsiP_G+QwE@5Vt zrVn^{bsIgiI3?NAns^o5y-&S&pZXBw7P7W@*f6b18DufV3UbrOOw-2=)9SEmD`fhV zY5KHbx-?~k5cPS}^aaCoSs2$>O#*K~?rlq*mZzjxApg&_`wisG%YQ{mlEvs<)9AOX zu_tJJ$bVn6j`Bz4nooZRxd1+9VEy7p4KUI_%zq zv=_1t_|)X~nPIvnjQk%=(?6M}2Mp7-VU6*ZabWS+ed^yYly5b?zT4v_u6=I!&u!6# z?(TtqMS+wM6IT$VO!CHgLe7wd}EYZ>s1~kkB8o_|_ zv^)khQp>XdP1Yty12y&lG=>39(WWqkfv%HrI9|xEh3^>F3~dI(%F$+6ux4uTuo>A*En!%ekYqr!v{?)&Pn%@{nyt-_ z25RjAD2)Lfq8-A3rf7#)faYj(qJi41C1rTYI7OTG;OX0Xr4AN8mK*tktLJ_ zu{zKatD9rTs(YvrtDD0Lu!NYPfDx7gI_wtE(L(`a1O<$-6wqn6fX*HYm>?*?+C*J; z3+NITpz^`rulZSL&d~gp&dk^Hd1qP&|E*Ra)g1iYvshFVXax-D5Us!hRHzklAnOf% z8+#QqZb#R+TlG^t%?CvXcY`-sa9bDTC6ROV&o%7r3|q=j)Yo! zIYU~aEn!G2wIvp$O080WbadErdkASYL#ooM7}8p;%7Rp_RSS@g=>e&RAuZLGGNgdE z)Pl53TP8p{u7{qhV@S)j=8&{hbLj_(1fks+=FxHH5U4AqBJmL)xwdEJ(FlEl0A9Cq8m&*u`?$IOAUIK6I}F zPu}omQm551w8OMI3tGKa&(Pe5!&8gtbd-KE`^cHrYsY;wLkem^hIFhJv>-KT4WSyE zNXMH<=Y+Kyyu$#eMy-({ov1Zhkeak60n*7P(z#*pmK>>BYi3BNYRwj;4cZ0)(&;AB zd139(kv3`@8Pb{BMhjAl25-|wbegq0+eA7)EV?*StJcbp&ed8iNNrl10O@=a>B6v{ zd-m_NSB*P7YjIbYMl(}3a!(E z)TMO^kghV3E=}oY89{mNy0vbGbdA<+LE55i5g=V>B3&jx+Ny13NH=I(ElAt6Z33j5 zOr*;NNZYmT4Cxkay9H^7wnKn)n~AhL9O({n2>F2giF~abkOoUxQZ}RoQnj=k(qpCb zqzfUvMS4(r1kyjjU)Xjj2jqV87VPA=k^U*C74W^{wkW<$#i>6e`7#9%xli*bjB+N}%oKOYn2?-Y_T%sIET$a8lmq-1mE04^&L7Cv@Mjv~ zKNbGMqDMLK1N^C0;~13n9(C0Z@JAjM-NY~}X8NJ<7ihUF>WykQR7^A497h#j04V z^WQGVjDUG$(to*1)@uC}WkJ=>!+}{INpgRJs#&Y|Q0KQ|9(68_ddk1Y6^o5b2IzXUFp zXj%9RXc}wt{8IQ>qNns1(nQu~`XzC)G*$U8sHv>Y^-JSrxd0dc!kWz5Y`;WqX0-W9 zR)IRTAT5g%+b=6%YMO4X>HD5I!{ZJuK0yFskK>u4O}fvyXsfa zwASYRweYnx@tR*r6I+}4*TmV<)a!mlO>J%NUmI^rldu1kHMzCfe~sKNO<(&fYx0_VCb4ay&4O!|wo-A|kAw5% zto3|K)_cAtfw(GC8+R9}i|<3~T1A`E7Dc z%5ZXAN((tYWgj`gN63l3h2&)4Iph@Id*syAG31QYspQPmBgi?a&ysV~(#d&g>&W?O z*OLp=z9tu?&n6eAA4e`tf0;m0=prg{4pt~P*3G#T*Jpj5Sxew?b1YM%s3c80tmm)6*-NT?umd^#< zBcMx_4+q_&p!3OZf$lNTrOS_i?s3qixdwyo3DEU*c|i9h==!*dK=%~r`n$40_cZAG zxsC_jGoTyb+6=m9L8rN11Ko3=8{~QbbkBospzAx(y#Tr)uHS?1MbHgaib3}h=!Pjd zpnDl~LzS~Z_X_BSD~EyZRnTQ9?}P3&&}AymfbMnBjZm?^Z-8!;iuHXHbR*TRpnD5+ zW7GiX-Ui)hbsy;d4|LH_5XMbRU2&JN_cjeF(bT_+vo#JJ99Ce+0UZKsP!51<-vAx;$?d=zb5nsouVz z`vi1TyxpMt6m-+QHK6+pbkn@pzn_C{rWgD73((C-@Ph6SpquUe26TS}-K>Nv(0vKI zISGe=?kmt8l5h#={sg*t3CDr%0O;l>HiPcZpvzCJ0^Qf3^C#{B-Csagn0N{3z5!i9 zBKF5$K{r1U`{Qq*D@rN^-QPjCAZa4#z6D)z(y5^P2j~_iZ3W#wL06LWCg{EcU1`$8 zp!*(li;{%2{5|Mg zpsP;)1au1Ms#4~IP6gevlu4j-gKlZc8KCokZbixt(8YmndCEJWiwE7Rl*d8m1>H(t zCg>7Cx5k$QItsegzBbS$f^MB}1?ZAMx7N2GbjhGw@4FIoDWI!Kl|knNU9Inrpi2c^ zAayb5(m+?AIums1psP!TIPmlVT|+9wfu}F%f~g;at{>={QeOmJf6z6iO$40=x(#Xl zK{o(&&1u^}HxP6!X|0-X24zl2UgJ##@(4vQi`2E}hx=v$EeVOzcd>Ogfc{L^%uU(Gjl`MPetT5Rfy zJ-NgMo_=+{XCCa*I25XLIc~8i;jWAlZsf@KP$cu@Hwf{g$VX9tq7X$9iuovtQ7k}F zf?^?xMJP&9l%Xg`QGsGHiX|v2QB;ibfPoD4J1hK(P@;3yM}0Z78P5wS=@|ZWD^lC^}GdqUb`=jbaOm ztthsk*p6ZcibGNCL~$63T__GmaRiDZQ5=WjC=^GdI0nVBD2_*Q0*Vt+oP^?J6sMp# z6~$>NPDgPDiZfB1h2m@!=b$(j#d#>sM{xm)3sGEz;$jq+ptuypWhgF3u^Yt|D6T|t z6^g4-T!Z3T6xX4+9>onPZbWetiknf~g5p*bx1qQl#T_X2ptuvoT`2aV*oWe76#G%! zgW_Hk_o28S#RDiFMDY-chfzF&;!zZjp?Dm{6DXcU@f3=uQ9Og+LM zC|*SI5{j2myn^CY6tAIp9mN|c-bC>hinmcr2O+PP*ARKGJdenwav703xHm4rt$F38@-ial$hm~=5zMx(mA{q$LFDgX7h)wF#UvCtC~{Hc zp_q(f3W}*HrlFXQVg`ztC}yFUjp7g#b5P7hF%N|wMLvoG6on{?P|QbBjA8+b5)=zj zEJ9I=q6|ejiV75qQ7l1GiJ}TcHHxJumZ4aVVg-toC|03ZjbaUowJ6r1s6nwFMF2%D ziaHeaD1s;&P&A^zKRT@7p9xm*5Bn0xfivZF6lb6~6UA95&PH(#igQt%hvIw`7ofNh#YHGCMsW#> zOHo{g;&K$bQCxxIN)%V2xEjSZD6U0u9SZ!TCkpC{9Fi8j4gDXQDU<#rY^MLUAdID^XmB;${?gpxB3^ABy`>JdENA z6wjh~3B~IuSUuju+(#%rLoo=&mngnQ@ply8gODW@ZWIY9Qc(0kF#v>=fw`e5GVyQ} zit#8Wp{_`tPvjGE2>L?)gM_dKu_*l$c tfVoTM%ZPlMd^(X|kYT98@lXDp{E>uvWJ~fpXg6J+K|FqV@NlVw{68VodDZ{` literal 86835 zcmd^o2VfM(_4n-F?wxcRm6JqSxoIwj8`Zb@yamt;?h7dUV$n|KyLf5ZB z{Sc<#lA^O#hhG)3-D= zbWM@`UR5gIQKhPK#>|<%+!3Ax*VuJUzAU%fHQ|uNpp-VNJy6w^Ib2GXQ%pGM+Bwmn~Dp3!O$X)Jbk23YVgSEBm2^olLpRea8;CTY}Lj!H1^Hz@0W*eS~n_t zW5NO{Co3`N$|{mlT#2RICN7XBk4%)Nl*q0;kF;Ziqzvs`JfN&`;_B%Q>wss_KegTO z_XX7o)wQ|B7xXWk-By~HSt)r-y>qset((<7FE1xOD>czo-n1wySefGL zqYmu9WNlvc;)^`FyFvOIB1f+~-eM)`bA9$6hfsuS&s zxZMajb!KzF)|FG+nwBR*_sOG^NBOp(ojP|{NlKxz$izcC#2Y>{*PC1`d0ksFgYvZQ z!Xdl*rVLOM1{S0z`-V%EuED|Slh#kJ3k}Ih4<@S#S*E_UaRSp9ZSnWfSUioBl&<2# zGe)<8|5(#5YsJJ>=nr;%nVo;El+e<+eAlQ6>t}5!$y>WEXTXfa)SxRH<1f*@#aFR< z_J-o+gSIzo)0^k@?ef&h6M4H;NvW*eR?Y63mr_5yb!C2=Z*b6ElIvGxUs6zBJ-v3G zH)lrM%Dk2phmUWB`UZ@4$yi#pV&Z^V8>(kzC)CQh23}(0+$kk(*j~eDW+m(GkX4kw zqiIxEN!#FA_45|x^n>;d88}(Koart7XSZxV+y!wwrG8zNqSVS$3_M?H-$C2xkm+0J z737SrT%Fg}w4h*%G|;GbVrX&7t_7)UXKx7h&D_|c&FBtg&CE(+Nk~21p{Z-RvtcLM$4Kcc^$^@TGbV7^(_thrni?&g!Ub5 zl%sBLa?jaD*H7>A4bDo?+sE)R1p&KpikQr1uIT)Y7I4Ac4e z6I+8&?+F9)wpJdVv9fY4I}hWAWVBoQnu0-aJ>+*SuG%$f(vTS&LVan1T@kn`iCn+p=m}qEDSF z>GjWYtYZv6_tU8Yr%T zKQmyo-?UvN6IM^|YI0|k5UGfw)R8`>j5A2heI5XR?Y+9F6 zzan*YzBf^ANnh%bY11M)9e8Y6Q3dhpQsw!6HXanaMrt!AXfrmfnVY?0f?sZ3JS}H< zR#v(%Q5~G&OG;2(8Q!LmiY%9n_4$0Is_Gi*T{TitIySop^)Fus$D_St7cjpXe^xM4 zE>p9X!nm2`ngHX(n#tQkZY5#TfLVQ2wcF(?@K1Iv-jtP=7c<=ay3 z&s8JsWzC1pQO!_lkofipWKJXb7v#e zbE4l}A6S&5kIM?&tMiQ8bMf}}=BB!)uEMsK_NL}gWqVgsTWe=_RXzOr#WC)28WX@DzH%M+B!lKNhsq5g2s!QKu2d+pcx+5%wodNabS~N z1kwO@jg*!?=1#V!ccdW=xKZRA(JJhi9S-p zcnkc?%4#5LS*-aB3yZ6(S=&q&=%7_&?D7P=%;DJm>14;1(-76%GSYpP)c? z?W&J_nYuI6@#eJ_ZS4ZDZVKHNuAtFn>H5jYPScef7wbrMO<6^tdUd#2ST6!mXsJ}) z0##5w>{ne=Sy2YHHR@GeSWy%xgZ2*_@Bz(WQeES(fsu+=-SEPZSg*O!Y^VxX+~_#e zVnZ060#ugx3l}p*Wb8wg33!sEJ(3t`DdV7#Quwk9ZAP<>4In)1#bOTcVsp z@wVX3X2dg7J>q$uMZC9k!7_+%J)VsNJ)Vt27SF!Y3W(>ZaXeaw<4&{=$DL?hzCefL zPP844JJC8EccOJTj$3u%aXeOw<9MtV$MIM#@Dyl)sX&Y4cq{^rM3 z)Z02dbuHe9*lDE zAON{=+!zOX+!%)}Zc^|FW3-|G5%HNcLSc^bsIGUp_*H=*);PH+r4xqqd zNoipquW(gi85|_zL4hCG;-eirm$74p#!kUd99U6VRRp63^D{0DX2*vIW>-^L<1fR3 z8+r~Q%wwY!QmTsKfv*Oxc>OUc5ozn!P?DbKP2ts#cuUljmKRqA%8E+>zZh;q>G-*n zzyD2CvL9RwMl(J&n8v?{A&>Ep}2zcWYNu zOK4JcS4Vdpe3T6~7Y3V~tKk*SL*9qGU~OAlS7#S|IF`tnRt9n2(yT850Nd2sXw^hG z*6e5x#Xo7Kue%xqXH)Va`K_0HKz^6%CLh7aWca+@yh9?{Q0ar!4xE2aK1qj9cILMdO6za)~+ z$pL6f0BsGx3rHw|d)2#SW zu5nSnBj0<;=kR7nT*3N!iIiA@cttHW|34s0vgCr+kra4LfVSM&R$myb+Zck#A0FK= zF#!%2iHG}u`GB6w$1yLe<-xUoSQW|FBPEG0VHlp>UHJOlnjob_vV~JR5y-_}{4j_o zZR&!zW5Yco(jCt0?vRUhhwL2L_dfg3jv2JinNZ_TS@8C#ZIH~(WF4h-r z9j>mH&IAcQlvuk3^tv15V%^~Gq8Ew2@X^HT3nz77$i@23z#{9L5~Q3+H_+>Dkc)Mj zX%>mT5C_&G;iT>hxeV-OexVtIGTfOH*jE+!%#a{Km6EL?h-dZif~>$DO7pN5ZmLg^ zAfh6?;iTaWS%Ei%N`wO(8xD{aIAEA`)CcN=UBLtipT@0Z;iTaWS%EjiNcam9gfP6K zMF7Bg0|2rD00@-C`r1bR1u8)*kMhTG(_0I&0)J@Uq>fM{eD>0-P!)v$1_lCT1qcu~ z1_BI19SPEkCpg85PGo#e|b%i8X`f^MhC%cEQve}D}Ghiw5cXkJAI~o(DL!-RI;gu&0uRI7D zPg8^LePon(IJD4CP&R~%yR()TeO#1tII8l5QI!Yb;;C;5a_^I)yu)FIc7mcISR&df z97lP=ILe2>usYze-V>OOEg>I5A;KXXC3s5U01*)35Dt!fVQ}O}1qU7*l!U>N4-w$O zd+F9tU4nFZRB_=*K|29IjFeWml3?mXf^>H!J!;yk^g0dk5 zQknvF?cH!4H+R8xyd^=pEea$YG5NxX$%jZt<{;NY^Z-e3M3q!Xf7ZFVVA-N6AQ>IQ6S+c zog$3VDG+@rc*Cr$65)M{07chY!gqsG8Ef$b>qd>wjJ4G0?Qy>Tv@g=c?Uojs< z`G><5Ed?Yn7CYM-y14ttQSRYLog$3XDG-6lq3vC8wRU#Y@o4`n3L_k^XdO#oDg+;9LHb)1NH|QV3d3|NhN%UlvkN9d z!L#nyQ8?i+MGpZPh`VHtgQ3p2{3i+{9Hmo*Q92dFu1&v!@vStVvytT}q;RM*pO^>X zsStb7qXANqJyAg6a77nEwIKeYMgxXJqj16zJ5?C5Qy~u1`Os9`vAMm=teGzgC>*-z zA|M12nN}aF3v@Mi2Vm-4LtSgvrW*P)$ zG)!KCJS-9ht@KF7tN;c=Ga4p8K^_?e6OQF+koB}|X0!d^H*EO2V*E%Q@#}GdZUP@g za>tk^G4loCvz5S|%H!pnB$6OcfX^{qFgFo6>OWo^zjVVZQW6XTdGJZ9ITUOKyD_C> z;RgY!7A|hf2`E2#jPdjCY%rnn6nSbAamx@aiQR@J%p?f2TvpoJWg%7oML=<0(-<&E zhcV3xh}@_=OP-CT&4B?U(h{B$gPqN7t&N=fB4}2A98GxI?Hyc7$o0=Cd~N<(u~JA8a$MK!h7HFwvCCIz>{ zv(3g}Yip>v6FNaf8$ccri7d3H@(Ot+;;(|XM~Y!?a3ze1B?KSUBF&(nLE(a89jLrc zUXLXNp!0C1M4`V7Le>1@Xik+_9i{qVCrjuh16wW3*7)kFbD(m)973w_mPl*6pugZ7 z(#Bxt#(0shhmzc02Un5R35v3D1u%CiZ};1(Fptr&rZw&r>mnqzd?RBq=kTl8Y_ z4P7Ujg68Hin09f~ZoOKK8x6~xs0;ca*NYn)qX|OY1rU0<1{hR#YPe-1fg+E>*N9&E zL*-pq`NN>19a}?NL#+Y$(%aOv1HMbv!5g;+zretw5R64!&+-|urcl$PIn*%_VG-xq z1?r1dfy42dz4O?qFpw&W9Gk04<1AH%l3*1zK?I|4mRQ71p0aLF+I>TXON@K_CjZ?rfo0jxjtX`&^hC$jFdyiNvEiOL2s0|5 zE1!q0e?Du0=1#o@TpgWo6NBpO8mRuoy!w~GNYSyiCD^$crkb?`yXxTbm=!mUA}bTs z{V=8>79`ls(DZnO!zoNuvK9ihDh$`kgk&Mq!x3xAsN$%6wR{cM_gd@CM!$Wf*0r@Z zG&RDHI`H*A(6~(^o5K|=Y;LRDJlibFawj)+g072qE{YmlR`3D^5?<8dQiynh58wnY zP_~4c8n@MTbu!*m*Nw_|$aiA1-vu3O zwh1qmT~498I(T)ggQsd}fO@>xA*RDh2)}*&O1;N4hsR82zA)TJ@uER+E^7Rj$k9I# zRQPHZlxkLAa1O6@8Kd8gb;oA#bcWy?bg15J5MFKQ$fbgg6hOu+E~){j{IL88_7Z$e zfXgr3{DEokN`oV+*-M~-K6!%o$&;ozC&$cfjtPu$%$1;*Wx_#q|F2iS2$;&x%Fkg1 z;R^*+Fg#|$^Ar2U*m%$uv}0*RW8s*-IBv8=*~bkD>~^Sf1Rtm}{CucS;S7&EHkeWQ z75P=H< z3VF^&NfFPfloa!vhmr+6mqp1X>Yb9n9=O3vlE>nJ&o=Wd|ne4e|B zk_&k57D_JUx!WkYi0AI04al#B(oGax>4p zO35ue_c|rF^4y!0+{SZnQ*t}c{fd%1c<$Gf+{tslq2w-}`+$<&Joj5l?&i6VDA~hv zzo%p`&wWbCKA!uGl6!dWPn7KExz8!Nm*@UM$$dQcS4!^ZxxZ2J0MGrMk_UP2pOier zbN`~`VV?Vjl1F&%Ka@PmbKg_)7|SUVC6Du*i;^dJPNn2Yp7T)h6wf76@-)vSQSuDW zB~$V&&!tlG9MAbEd7kGoD0zYB`cU#B&-J6^C7#nLd70-1Qt}GV4W{H(o*PQZYdn`l z$?H5ff|56QZX_jd^4w@j-r~8jl)TMz<0*NE=iq}PyKk}SR^dAruFlZcdhokMT%)o| zZZrySH6o<&0uF9CvIoQPf)Q>vB90wSKIB$Id$0;y2-)Mx626>;!^Aa;TSY{Qt|EI9 zh;9ooG?%XMLgSi+D==PEML>&Q=n@~4O@qeuFSg8#D)&T@q2X#78)&$Q#)cWLt+8ch zpb5Jk+9lj_!cdD?pu-Ey616b5gLOOHW^_CoeK}7&%g9we+;WTnlRYXq*^7*M?6n%azCG_@JOXsWlXXx!rKz>Gy= zyitdV;vByj}5Y+?LBe=rmCA*IJo2rr!DSfbl4Un8flr{iX#`<1bjuC$2Th#sE| z8(eC^t%RKvUX;g;CJMr=hqZd#K~xQW*;yW2!pF@-ov)jjEBm;mDCVq|#*@Rr?2JbT z(ZFTJ_Tkv;k=ViRa^~_^-bFnY6^={cAYm?+{m@EL6y=ixKjG|t0kv}v4&&uG&)51-MdabBLRrU!j_iZzb& z@)T5Z?7fo%(FPhqnUo?%=t}!dK`M5Ad@GJt$sBytIHxLbJxXzldUFJ5TAhXchMeOl8S#O6u6&AkL^~5^7@}2dkXjl>~kmt-q zogcYwp4*A;#O88(ZX)V&%PRYxTOz#pzGqI6Yx22WI{bWY%&5@k!%~t%Ccv-f%Cj(= z2~J0C)kVozG7(R|z<+#?-l&U`Nn|pfe;KAAfV;k17bUqQ57nhvunZ4M96|~$J%HI-|FO{#LucCoAUwq;(iCP%U|;;(OBCfBn7Rl<_9XVxibsKU9qw%GJea?d!soBB zGtA|Cl_V+OsS;JbSAGL?SyWfV`aR-Q+|zNv1tUz+l~3wCMnppYQU`9##}P)Ad+xoIa0Qgsmg#21bfeVd4~U`uU% zusqZiYzWqMwRP<9s6&7uth%%4ByzlUD}sp4DI)hCv~E*jXIBgBz6<)k8`donV)n97 zhpAa!b*MTVDm{Xa7QCtpx?Afo+$Td5{aziJP9${{%%0;Xmvn?+1{AdE7-(pH-i@wf zEjlhy9jlI)$S9)|VD$sv?zywAyQ41D)Y{NCshVZWnp#61bwUDxe(z^(6uq{kIEhAi zPo3;lC#rB^dz)JLR+G5p#we?Upt`z>s`=^^FHnNzKQ<_p0y~ciD|7l9^dqktkBUoX z>e~YP#vd>jG`h{qIP1CMSW0+8T4V{9U=MAF1wgP0uC)s`%Pt6ZhIr)8rs`~Uju!&= z5UPBtyo7-}5BhL^n(|UQW!q?o)_B!4 zbr~hU!VOPkbp;@X&3IRNR9Hgc=20qHZ?f#cvQei%&u#L1vTtB1SXIg9&BJTk9ynn%cJr*z{;39oWmXYV8G`fQ}sCYc;n|N+FmD+f24?MB) zo6o-R16_Hj#d=}xhesauUbvOu!(RBDN4+1qqQ0)Kg)JOz+ZyVC)l?y>K8OWBpgx3+ z_z+xbO)(aaa*M~%;xX7-2IdK~6^Hm-6u?Q!^-Z04r=#kV-0~^3dG*~w5s@s{}*bxfC{eY^kV4T0KzKRRTaEn-~ zz79{8fB?^(u%ry8ds6i+Stc{k4R2wV)eyct->bI zoE+uP>gR~^1)_X`4XrOILnk!xsDJgUU#c*t%*#c06uYxQ4P!oLCBxB!gpk3H(QP&sqVG1TlX{9U5@AN70KuRa=GS}5p=}oR{pwb&$w~@n;NoGnGEzI=E%N&+Xc&^fA|UQ0XJC z>!Q+UydGPr^arln4sXG1IC1Z!(&t>a%Mz64s{TNi$9;I@^=mmdn@V4}kHjE?yXco3 z<`^pdjZ-*|O8?|KxMzONb#Tx8mh0f2`5&%3jlyM#k4^3~s4R2cSyXm&-8oeDaNT)S zPU5-?s7$%;A}XhG-6d4^aouH9?!$FgP`NMHT}9;qTz3tX2XftYR36H8H&A&P*WET}e6`nGi!B5K5^N>ogsDkMsm8R%~<1Q|IOisnaIiA0ZdqfruX=7u->ZA0ZdqA&4I#7u@oPA0Zdq!iOIr7u=tRA0Zdqe1{!j zM#i0W_z`l!ZFBe$a>4C!_z`l!J#P3Ba=|@o_z`l+H@IL%#?55-Ipl)d!tf*Hg4?|C zBjkd6wXh@1z~2lpj*tuPo5If_7u*1aA0Zdq$%G#v7u=GBA0ZdqTZA7W7u+d?A0Zdq z_=6uI7u>>wA0Zdqje{LwM#gP5_z`l!%`x~9a=~pb_z`l!tt$8ta>4y3_z`l!T_gAr za>1=1_z`l!9US-(a>0!l_z`l!{S?>{W@OwJfgeF8BfB1+lK4l75dZW5_n7I{_a^<7 z-}rP9s^@0#iW&X#1=r(H{vr#zd$8>}xoJ_j2#+U6BIgL;;p4`}=)arb zYw(d5KWo5;iHh!)TG%L)YtqZ$3t;ndSTBmlx-yMde2KBCW+%K^l)@eY9qhFi_t*6D z?;H!@&tkwrvMS!P%bVEVmj2e(HrR^=|5gS(+rbMb-}IDYf-1EdxAiP-Z3Zs*y#QWj znFi>SEFu#H{<%p4tU^e~FT(JxDjh%lvJ^h?vJ}4QvJ}4PvJ{q+5y>+Z@-mqY_A|&# z$QR&xF_yv-FP6gkEJ)LF{Sr(4dRm~Tg?d_~r^R}@Ku=5bbfKP>>gggqU96{NdRnfh z6?$5!r%Uv7sh(EpX|-+~^|VD#TlKU}Puul$i=KAq zX{Vlc>1nr~Zq?Imdb(XtVKot}53D6(DXb)7DXb%6DXb!5DXbx4DXbu3>5+PRl%5`~ zr^o2&v3h!(o*u8KC+O*kdU}$co~);*=;^6?dYYb|uBT_{>6v-6+`J-tCsZ`9M9^z>#uy+u!N)zjPb^maYHLr?G2)4TL^x1Qdur+f5tub%GH(|h!E zzn;Qs9#$V%%fnJw$-`1u$HP)s#luoq!^2Wo!Nbx=^z>0ZeN0au*V8BT^hrH^N>88G z(`WSbSv`GDPoLM*7xeT+J$*?}U)IxC^z>CdeN9ha*V8xj^i4f|OHbd{(|0hHt|W>0 z-I2(iX;7;}VdTUw`#JZKKM+zje%wCtr}CVqh?;ZfZt~Z0>3C zXP>05$hi~jU7qP6lZf;mlI|fNcqHnX0SY&fKo)qg!G-~_3V(XXEx{i=1k)@jL4se> z;7ktrwd94L6lOsl-l~61(%_pne9+T5?b10-5Od0qQhP(H&_ZgAl%|s!F8Op)6GWuo z+oD}kna)Y|F-i4}M+&}h+9jp+hE!2ROARnd4U9($zO33MHN-iop(d$e@kqf(Uc015 z^oCS%L`!9xq(;Ug1z(r#k{aWj)L4_$xOk-CL$_U06M92xK}1VUG)Ya0M+&~V+a;Cf zoK(I^YDzp(@cG{^sp-8TRT9xsGfYx5CsbZ7Vf_S9hcOAQ=N_#`9EP~V`lhopPq~NC{yQC_dld3dH zEr~}8e!H?us=7C%$|G8;#w4{Y9x3>t%r2>wy&+W*L28vrYIQtP@Z+3aQtNs{sxpGq zdXrQj9x3=W&@QRk-jG@nL8{IqRUeNO{2XbQRAX;QEsY?x(InLrj}-heYL`@VZ%9=| zkZLhWwZ@-nl=(omzNZkv{mOMe3^mYT^W|BHQ9x3=e&@QQ?dPAxyg4EF_sbk`i zg5M$Sk~+ROq&7v6I>97$Vmwmt^QT=>r}T!@<_J=!nxsyPM+$z4wM(j3-PamH>I{?A znej-$kHU6I^(xTYB1oNWk~$|IDfoTbE~#F{RC@%e^Gs6b$0G$lmD?rNtC-pnLFz)2 z)J5?~!LRmqN%d;*+z~T#3Q6Y)sF^dY;Xp6(5)<0D8tW0HC{9x0f=WS7(ny&-jC1gRHIQZL0L z1rw<3l6ti_q)v(;^_ofQ^?0OU2A5q@Z}o=M$q}U9Hc7n`k5u^QqJ#c4^XuM_IwgYC zdnT#h#3KcB*zC5{hrJQ5%AKgS~l(+KU7`b%#}ofARofJy4F@kqg>M7yNE>J6#$BS`(-B=wJYq+nL0 zT~hz*4XFzvNd4O+^-VldFfG$AsqcD2>cR+8-y5W45{DGd3$;l~cJ+qTMOIR>VvOvQZO~wE~)h1kh&~_RE9|^ zGaf0J8*GVVc{Q?S8jXix zQ*Iznl5rNJgbQZ$8qI>qG&r5cJ#OHBdHStF@4nnZ_Xb-zA7%kb9zOL34$=T}hCDL{ za{PYz5HTSEq&znoa-KXt1`=2n-PU`S#qt6jvKVF-u{Fu#2IlOS7mI1)^dp#KWY*ln zYtD2fKv-sNkSJpt$R(^D%H;Cc5(e#;tL>Ihfo;o5sFZ8MB~(BOm8^ti@^WDbtADT( z*2ru15+cH5gSdd$zC_|?cyQ7|xmJg?hHIl3F(O>~%WIQ0 z#x}9WY!gFvIDqUFLvD2dxlP_4)8*qKY!4S>#)j<tc2sl&2pl+fY{Ds1sG!vz(PEn)C1|$#F(+o!UBRd%gI*K5E}By ztc26$Ghmt`jtFoN9|hZGwCb6z0<7 z`b<`(WEU8wfk~Qt4lDS=9;$Y!xZK#PU1au0MAa@bt9F@uxgJyDs*TTqs$C~8BDQK* z=tU&RS7Ph2s$C^t4^_iE161h>DC|o3cNMGB4f2h8fnCG{|0g7692BT2nyR_?%e%$J zF65SGi>Amo$#=6BO_6VgN%&Z7ihK(e%W}6u4*MxZz729J%iRt+HzTFF<(q)e&G7FQ z_;)M(yAA%`&Is-iN9cYrvDgURi|t`V=w1eSuY8{#KWl*tvhngd@0TAF!%pE=W_`W# z19~%iWh?;e>y;mb9M;z>KLj~NkEQ!r;XXxv0O|w;!$iIJ@c*fl$e}-8k!zXyVh?LaB6KR?r=92tJ`A-7C z&pF@$0Q~&_2>4g|O99|l9Ppn2_|^Xr@N4;Bdh~@KipKAiKe!7j8vDc@(~mGi-CQXo z|63m=*tB&?{zm>*zmmex1NX|mwGSPB9OsZ^zOZ+{v(>xAFLHLl-%t_NG$Otr6bgjS zFx1*{E)+T|_MD4^&Tf0o#X{!Lv&v~KHImMoHsn9vip7SE1bGkj} z#X{#yd(LG-=f3uw%Z1MU?KxKnod?)+t`s^Cvgf=+=sd)p^HQPnFni8bLg(T3oU4V- z+4h`agO8Zo?jF}Dd(O**&SUI3FBdwGv*)}*=$vEEd8N>KqCMwTLg&f$oL38-^XxgV z5jsz?=e$<}2ZYXZ>^W}`I?uJ|927dwx940dbS|*xTqkrc zvgcecbY5W3IV5ymXwSJp=)B0DbED9?%%1Z`p>u^j=O&@^5_`^@gw9p=oHq-dYwS5U z3!RtSb8Znjue9gfDs*0L&$&(Lyw;v`yU=;PJ?AY#=MDCpJA}@)_MAI~&h_@3yM)dS z_ME$g&KvDHZxuRkvgf=_=-h12dArcL)t>VXp>w-E=bb|54tvgr3Z1*`IqwoWZ?)%q zn9zB&-ogm^Aq-*uN68!WzYFK zq4P8LoUa!;KWESR2BGr{_MC4NI=^Jk`6i+BEB2gk7COIX&-oUi^BeY@ZxuSfWzYFG zq4PWToNpI8ziZF=4x#gV_MGn&I=^qv`7WXJhxVLz3!Q&w&-rel^T+m__XwRovFE&3 z===wJ&ijPUf3)X(kI?zg_MG<%oxiZ>e6P^?fIa8?gw9{ubG~2b{FOcD2ZYZ5u;=`s z(D`e7&JPKl|839tVWIQ4_M9IPI)7)+`B9OxLhLy|CUlnVIX^CRR_r-HA#`@zbAD3j zoM6xSDWS91p7YZ}XKK&+8KHBEJ?CeI&T00XpA$N#+jD+i=$vWK`30eKUwh6k3Z47g zbACzaJiwmw%R=Wt_MBf4IuEhu{HoA-m_6s$gwDh5IlnG+&bH_LhR}JGJ?A%t&SUI3 zza?}YXV3X

vKs=XZq86Ky#wlf?6wzU%!wCS|e^(nTCV=87R@2atJUNW}qUz8KQ& z0CI{LGQk1lR57I20pv6>By|8eT@0Dx0CI*HGR*;2v&E2o9YD?z zL-uz7d59QtfCI?6V#q-bAm@o8hd6+oFNPfE0Majp9PR+JKn$7f0J2aFIm!WKkr;A} z1IS`Ay zJAiByL$*4A+$e@@cL3QWhU{uv$YwF*b_b9xV#u8iAX~+dyBt8a zi6IYn0NE~vJkkN=7BS?}4j?=Z*D?*Ot(40)mh$Zj#@$qpd5iXl&R0J%*J zdAbA0?PAC?9YF37L!Rvba;F&bTnCVciXqQ;0J%#Hd7%Ty!^DsmJAgb~40)*o$Ros% zmpgzwQVe;e1IVMqkXJi^JX#EStpmto#E{oJfILq$P>hn zw>yA5Q4D#f1IUxakh>i~o-Bsk;{fs$G2}i6kf(|v_d9?*O$>RT1IW|GkPkS3JVOlm zkORmw#gLCUfILeK`IrO9v&E24IDkAy4EdA;$aBSz&p3cQPYn5-1IY8mkS{oZyg&^3 zk^{&K#gMN!fV@Zy`I-aBi^Y&{IDouF4EdG=$VKOkavh7 zzjFY2rw~#h4j}ImL&^>ycZ(qv2atD*A>9rj_lO}A96;_BLwX%R?h`{&2axxOAyXVc z?iWL*Ie@%Z44Li#@;)(SrUS_P#gKg+Kt3Rb?C${bK{4b22apemAqP2td{_)Q!~x_Z zV#r|*ARiS&4tD_gm>4qK0p#Oi$Waa;pAbWiaRB+G7;>Bg$fv}RISwG77DG<#JtWCd zo{8N{QF$(U%isjjpNk-4mFES{FGf4h6FN^)UJ^LJ674)+=$xy(DsYb3@7XVO&KLZN zj6KSm(IuZ9>zwA7$0~2dl)O)QC)!!?_chY|(AvKeIRDy)Gf9^}kw4X)L$H%M?)N=x z+^Vw2`2NbNvIaq%Y zZS5zL@}5!oC8Z>h97;%^yTV4|^8%Sb#&OWvF;YZZ^N7M$RA_ZxE0NCKa2{4-XsVx-~m~-0%(>ZCDqA6i_EMblPv;>Z@6^OEu617BTw_QuL*m*T? z*v=@aD6Oxkq$DkgA?(zWEC^Ji9ATGHQnHrJ><-tGEp{ndN^G5q#U-U`sSM#rE!BdM zrlm!dBV3TBd}>p3&82AN0}s zFqD(EJ{FX|THh$X{j`3}?o_Rx#jd~BKWt}|v@mUes1GzvV+f~fngwBiHXw`ufw73i z@Yx1dsTgaZHjrVRs|~bZ4bld2tn-cj9IOpyb{A@cEp|h+Az?eCq_VWZQLH(YOMnz! z6tjkELmAd(+E5GDFl|_vzkyXA5$~6q)w;^S%F?nJ)-_s|1#7rAJQk}Wt-pm=80&fi zYlJp}Vcn>WuwZ3t*|Aua5s`$K`y$rdw-{I>wUG?#Hf^K@Ym_!B7HdgF9m8067+9mV z(G2S@ZL|ezj5a0~YiUF;0~QP~W3{o&{cdfn#eJLx@Wv=+lr&!BqupLDJlrMC%F*-z z53g>cXR6XtEv<=H!9Dxb`}V01Lv9gki$@I8Wod&frdUC4`nYNOgkico;@S$EK5d#l zW0|SJyBjJAkEd!dQO=7+Fkv7TFYm>Ff90)H=187~uy$5M8 zVjb|Q$?Xq@>G}xre=<$~VwxT>Oal>(@wahc@%Me|KQEGRH@&{u?Ix~$Zurk_(S`5s zb!pkqRN}k4+xv){8fDd4Yv4{cz}#uE1%NJGK)u}p>U$_4Lr_45rGSv#0zy3$&{t4E zUrPZE@e5GXj3#P`D4?I&L<3p0H%mB1DdK$WkBP!sTQDV+O$}pO+5fjU_jHg=?rL+Hr)a=Lz@u` zv^f&!1{sIrMeJJmhGEUrW-_c?ZKeflmIe=-(aqEvfn^Cv1~gln&4BW?*%qKV+MHOR zwjO{o7|^k#+G@9e zt>OYyKKT1JKkLkyn%~ly1zG{`OzYsk!wRIDgTH$=i;6<6kO3W{6EK;fQq#e3(!JsVJxFv z5kO%^B@C!kD`h~CT7VX5aJ?IkHAXxh5&cxe2L<+|fmIycNJqKoV~6 z6%1*qwv-{Q(w16~s+$B69Lj+8EM0Z5>0}qOG$at=HBIkWPyj2f}^V$&dnC zfFX5j0SnRwZG!;mbnAUa4I^!1NI@;gkalQ63sS9C%aJT2ijSNTakX4N&bS-958bQ4 zvp2k()M<4L?J%v*f>y89Gc@-R@Z4fL9j#x^K5|aPwFB=SfE3a~4Cz=cWI<}s8p1U+ zk&ZW!&W~s{j?}0%GNco=MhntLZKD9`WE1Ivh__3Q)TA{rq*Jvf3(_WSlK|;-6Y0W; z_UA~OwapCaOl`9Tsab>fX(Kw#+8M9>K5|h+baA8>t%V_-tF>5=TD4XI()lK*OCoxb zBeiL54Cz9x&4SdfwF{6gHjyqBw9^)C3q!h8+hRfL&^iQ2mzzkJ2{?6Xoeb$ptRqXOApK+N zH>uw#2hygb6{jtP^zgJZ($0qTnY3S}y{8=TrTa$sMnSsP*Wzo3^m^YtzWX3OkS?Vw z%7OH`>6PhKke--+Q9AHSe=Yr^^iPxn8G|w=WK4#%A!A#{PDt;}cr@b)NdKLgl$oL& z$SlfSmbntr(=)Hgyc*JXGC#}wvvQ!%@ILu{ra{`==deCUDhK#)DtRZ8UEh;0;SV*! ze=7X>VUKd)d-!9m#xW@CJ?iT3;mmZH-R0%^b+6w+i1a$H2lS zaf)L$PazrRkdl?w4}k^LcCnG6kPQC;s9EX#Px!6O1G?PsHFIL4` zo&R<@W(3S9lmE+AvR3QIC=04~J`T+CNRsy>RLxqwAFDjs;~vWHJ@d(wAE}DgYW|pI zTB^AxKyLc!NyAkJ#p- z!RDtb-*^}!^GVT9)CAVB`zbj-T@iH$!KUwlKYcgxI{T#Vj zqOIy@*mTzB`?>P7G-1upv8{|oH`qZ|0_2|sE01=l0GE*pR0b&0OervHKZMAxbLf22;)^=kbe zs#kQ~+W*Ju7G1xN|H1l2*Rkt=w2smB-1ivYYB~2pjN!!Vm zq(@079ZtIFF{GP*OtvN$lO4&Ylby+LlS5O6kzFZG4Zr}@q&r~5u6XQYoKXQ$5~=cFG^&QE`VT#(V1T$r(e zT$FJ$xg_H&a%tvVa#`ky)PUx%Yxjl`aC^KF}pd$AIo0(0Qas zLAM`tUg;Ll-3z)z*#)}$Ku4v|L3cmslH~EAdjNDPav#t=2)bms1#}OAE=^tmx`#oR zDxU|sM?jY@9|5{YLFbd-2Hj(z%ak7l-Q%Fka193C6QJws@__D1(DiW@gYGHN^>cp!*zjha_DJx-URCKk0bT{RMRMlAAzx0CWY()u8(;=={mMLH8x-ijpq{ z-QPf0n2i1L73dZuV}JY|bj2w}p!)~t7N$%D-9JHBl5!g8z6RZ*lx?8<7wAe;-U8jf zL06XY2TwhMF~(5*;&4|EBjTb=e4 z=n_G<$~OvhUeK-erGYL9bZdO=prfE$?^_MJWYDei-3Pi9&~5Nt3%XR$1=1DJrGc*2 z_XX&DpbMr~fi4|%_33j!mjSxEbZC1|Cg>W{q3u0=Ko?5?1ay5tw=w+{(DegdW5#6A z^#|Rii~*q2K-ZM96LbSW*PKxgx`CkEobd$c27#_M<95&u23<>L3h0J_u07*x&@7CT=nW9EU-g1?dP#vmqTt#=uP`k&I_J zKF=ITWs>MQ1kxlp?}dL!orHSkf}#QzMScv5->BJ8)Nj=Ourc2Nb)Y&J{%N|-uNIiP z0$sO2EirW^o?PMrPrtgrGY|G@917LB0ykNda9>6Vw{qmWD3bZ|n}qmL6rdEk9MX?CQViaX4%28CHs6?>@#ZnYiD5_D^pjd`tIf@l1R-#yiVl|32DAuA_ zhhja70E!JLf+%WH)S;+H5kk>`q7lVL6ip~Lq1cR~8AS_T(T9E;*O6eplK5yeR; zPDXJGic?XXhT?P-XP`I}#aSrMMsW^`b5Wd!;(QbrptumlMJO&taS4h`QCx=Nauipf zxDv%xD6U3v4T@_~T!-R%6gQx_5yed?Zboqnid#|KhT?V_c%6iv1|=MR6aB`%yfA;z1M-p?Da@BPbq4@feE7Q9Oa-Nfb|^cpAksD4s>}90)mx z9r`>TzJTII6fdE88O19oUPbX5iq}!Rf#OXRZ=rY_#XBfwfRNY7Yl%Eho=@a5xtz$I zauboa$=iv%5p!)QZjf&z1b5XXxH~Sv&3WZz@^T{Q%6WwC63jNQmA{t%MdWW_A7W(^ zipeN)QRJb>M==G(R20)tOh+*T#Y_~lP|QX#2gM;M=AxK~Vm=B#iUJgcD2h-Nqga5V z1jRxWr6?AmSd5|!MLCKJ6qP8Jpje8c3Pm-F8WhV=EJv{d#Yz;bP^?C=2E|$w>rkvm z5kRp4MG!?TiaHeaC_*S2P&A^zKRc}89|~6RPx~tP$9NU|^SKKC!CM9YM6J?>q8&vy ziY+KQP;{c`La`OaHWb@Y>_D*-#i1y6p*Rf1;V6zkaU_bPP#lfo7!=2%I1a_}C{93u zf3{A+KQyP{pN3QLkGU!M=hqbcgJ}x>i8JL46lbD13&q(e&Ovc5it|vMkKzIp7oxZb z#l_%}niajXyqS%Mx9u)gg+>7Eq6!)We0L6nS9zyXjibqg9 zisCU8kE3`3#gizWLh&>Rw)3?-7OoVwA2j(Dd6!62QOrUy4@Cir5)@@9mZDgWVhxH7 zD3VcxP;5fchN26_HWWKi9D(9k6epoL9Ys2dvrwFi;sO*Gqqq#k)hKR2aVv_uQ0zm| z55@f`9zpRWisw+gjN%OxtRC-U?jsa`Krsl#=P15J@lO=rf{-N?ZWKu<(opn4F#v>= zg}I?9vhi>fit#8Wqpnz9K;)Bf2>PS^CkgkNmgK+6UrI7;|18P(!kel5wEPT__u$y{ zIEo|C_&Cg6h`Gz;%ZYrtdvaWJ~h9Xg5QiNj&r6!Na8z^8Wxu CCv*1z