diff --git a/EL2_IC_DATA.anno.json b/EL2_IC_DATA.anno.json new file mode 100644 index 00000000..16430c21 --- /dev/null +++ b/EL2_IC_DATA.anno.json @@ -0,0 +1,18 @@ +[ + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"EL2_IC_DATA" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/EL2_IC_DATA.fir b/EL2_IC_DATA.fir new file mode 100644 index 00000000..8d944f25 --- /dev/null +++ b/EL2_IC_DATA.fir @@ -0,0 +1,26 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit EL2_IC_DATA : + module EL2_IC_DATA : + input clock : Clock + input reset : UInt<1> + output io : {flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<15>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, flip mask : UInt<1>[2][2]} + + smem ic_memory : UInt<26>[2][2][512], undefined @[el2_ifu_ic_mem.scala 209:30] + wire data : UInt<71>[2][2] @[el2_ifu_ic_mem.scala 210:48] + data[0][0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 210:48] + data[0][1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 210:48] + data[1][0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 210:48] + data[1][1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 210:48] + wire mem_mask : UInt<1>[2] @[el2_ifu_ic_mem.scala 211:51] + mem_mask[0] <= UInt<1>("h01") @[el2_ifu_ic_mem.scala 211:51] + mem_mask[1] <= UInt<1>("h01") @[el2_ifu_ic_mem.scala 211:51] + wire mem_mask2 : UInt<1>[2][2] @[el2_ifu_ic_mem.scala 212:52] + mem_mask2[0][0] <= mem_mask[0] @[el2_ifu_ic_mem.scala 212:52] + mem_mask2[0][1] <= mem_mask[1] @[el2_ifu_ic_mem.scala 212:52] + mem_mask2[1][0] <= mem_mask[0] @[el2_ifu_ic_mem.scala 212:52] + mem_mask2[1][1] <= mem_mask[1] @[el2_ifu_ic_mem.scala 212:52] + io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 214:23] + io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 215:17] + io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 216:16] + io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 217:16] + diff --git a/EL2_IC_DATA.v b/EL2_IC_DATA.v new file mode 100644 index 00000000..0bde4d62 --- /dev/null +++ b/EL2_IC_DATA.v @@ -0,0 +1,34 @@ +module EL2_IC_DATA( + input clock, + input reset, + input io_rst_l, + input io_clk_override, + input [11:0] io_ic_rw_addr, + input [1:0] io_ic_wr_en, + input io_ic_rd_en, + input [70:0] io_ic_wr_data_0, + input [70:0] io_ic_wr_data_1, + output [63:0] io_ic_rd_data, + input [70:0] io_ic_debug_wr_data, + output [70:0] io_ic_debug_rd_data, + output [1:0] io_ic_parerr, + output [1:0] io_ic_eccerr, + input [14:0] io_ic_debug_addr, + input io_ic_debug_rd_en, + input io_ic_debug_wr_en, + input io_ic_debug_tag_array, + input [1:0] io_ic_debug_way, + input [63:0] io_ic_premux_data, + input io_ic_sel_premux_data, + input [1:0] io_ic_rd_hit, + input io_scan_mode, + input io_mask_0_0, + input io_mask_0_1, + input io_mask_1_0, + input io_mask_1_1 +); + assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 215:17] + assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 214:23] + assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 217:16] + assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 216:16] +endmodule diff --git a/src/main/scala/ifu/el2_ifu_ic_mem.scala b/src/main/scala/ifu/el2_ifu_ic_mem.scala index 8e1948f3..a4a12ea3 100644 --- a/src/main/scala/ifu/el2_ifu_ic_mem.scala +++ b/src/main/scala/ifu/el2_ifu_ic_mem.scala @@ -179,6 +179,48 @@ class EL2_IC_TAG extends Module with el2_lib with param { io.ic_rd_hit := VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(w_tout_Vec(i)(31,ICACHE_TAG_LO)===ic_rw_addr_ff(31,ICACHE_TAG_LO)).asUInt() & io.ic_tag_valid).reduce(Cat(_,_)) } + + +class EL2_IC_DATA extends Module with param{ + val io = IO (new Bundle{ + val rst_l = Input(UInt(1.W)) + val clk_override = Input(UInt(1.W)) + val ic_rw_addr = Input(UInt(ICACHE_INDEX_HI.W)) + val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_rd_en = Input(UInt(1.W)) + val ic_wr_data = Input(Vec(ICACHE_NUM_WAYS, UInt(71.W))) + val ic_rd_data = Output(UInt(64.W)) + val ic_debug_wr_data = Input(UInt(71.W)) + val ic_debug_rd_data = Output(UInt(71.W)) + val ic_parerr = Output(UInt(ICACHE_NUM_WAYS.W)) + val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W)) + val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI+3).W)) + val ic_debug_rd_en = Input(UInt(1.W)) + val ic_debug_wr_en = Input(UInt(1.W)) + val ic_debug_tag_array = Input(UInt(1.W)) + val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_premux_data = Input(UInt(64.W)) + val ic_sel_premux_data = Input(UInt(1.W)) + val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W)) + val scan_mode = Input(UInt(1.W)) + val mask = Input(Vec(2,Vec(2,Bool()))) + }) + + + // val data_memory = VecInit.tabulate(ICACHE_BANKS_WAY)(i => SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W)))) + // SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(22.W))) + val mask = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>1.U) + val data_mem = (SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W))), SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W)))) + data_mem(0).write(io.ic_rw_addr,io.ic_wr_data,mask) +// ic_memory.write(io.ic_rw_addr, io.ic_wr_data, io.mask) + io.ic_debug_rd_data := 0.U + io.ic_rd_data := 0.U + io.ic_eccerr := 0.U + io.ic_parerr := 0.U + + +} + object ifu_ic extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_TAG())) + println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_DATA())) } \ No newline at end of file diff --git a/src/main/scala/lib/beh_lib.scala b/src/main/scala/lib/beh_lib.scala index ec4a1131..33c1e879 100644 --- a/src/main/scala/lib/beh_lib.scala +++ b/src/main/scala/lib/beh_lib.scala @@ -149,17 +149,17 @@ class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{ - +// DONE class rveven_paritygen(WIDTH:Int= 16) extends Module{ //Done for verification and testing val io = IO(new Bundle{ val data_in = Input (UInt(WIDTH.W)) val parity_out = Output(UInt(1.W)) }) io.parity_out := io.data_in.xorR.asUInt -} - +} // DONE +// DONE class rveven_paritycheck(WIDTH:Int= 16) extends Module{ //Done for verification and testing val io = IO(new Bundle{ val data_in = Input (UInt(WIDTH.W)) @@ -167,7 +167,7 @@ class rveven_paritycheck(WIDTH:Int= 16) extends Module{ //Done for verificati val parity_err = Output(UInt(1.W)) }) io.parity_err := (io.data_in.xorR.asUInt) ^ io.parity_in -} +} // DONE diff --git a/src/main/scala/lib/el2_lib.scala b/src/main/scala/lib/el2_lib.scala index 0db68481..b63a701f 100644 --- a/src/main/scala/lib/el2_lib.scala +++ b/src/main/scala/lib/el2_lib.scala @@ -182,6 +182,15 @@ trait el2_lib extends param{ def rveven_paritygen(data_in : UInt) = data_in.xorR.asUInt + def memory_cal = + (ICACHE_WAYPACK, ICACHE_ECC) match{ + case(false,false) => 68 + case(false,true) => 71 + case(true,false) => 68*ICACHE_NUM_WAYS + case(true,true) => 71*ICACHE_NUM_WAYS + } + + val data_mem_size : Int = memory_cal // Move rvecc_encode to a proper trait def rvecc_encode(din:UInt) = { //Done for verification and testing val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1) @@ -213,4 +222,58 @@ trait el2_lib extends param{ } + class rvecc_decode extends Module{ //Done for verification and testing + val io = IO(new Bundle{ + val en = Input(UInt(1.W)) + val din = Input(UInt(32.W)) + val ecc_in = Input(UInt(7.W)) + val sed_ded = Input(UInt(1.W)) + val ecc_out = Output(UInt(7.W)) + val dout = Output(UInt(32.W)) + val single_ecc_error = Output(UInt(1.W)) + val double_ecc_error = Output(UInt(1.W)) + }) + val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0) + val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1) + val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1) + val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0) + val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0) + val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1) + + val w0 = Wire(Vec(18,UInt(1.W))) + val w1 = Wire(Vec(18,UInt(1.W))) + val w2 = Wire(Vec(18,UInt(1.W))) + val w3 = Wire(Vec(15,UInt(1.W))) + val w4 = Wire(Vec(15,UInt(1.W))) + val w5 = Wire(Vec(6,UInt(1.W))) + + var j = 0;var k = 0;var m = 0; var n =0; + var x = 0;var y = 0; + + for(i <- 0 to 31) + { + if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 } + if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 } + if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 } + if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 } + if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 } + if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 } + } + + val ecc_check = Cat((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR)) + io.ecc_out := ecc_check + + io.single_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded) + io.double_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded) + val error_mask = Wire(Vec(39,UInt(1.W))) + + for(i <- 1 until 40){ + error_mask(i-1) := ecc_check(5,0) === i.asUInt + } + val din_plus_parity = Cat(io.ecc_in(6), io.din(31,26), io.ecc_in(5), io.din(25,11), io.ecc_in(4), io.din(10,4), io.ecc_in(3), io.din(3,1), io.ecc_in(2), io.din(0), io.ecc_in(1,0)) + val dout_plus_parity = Mux(io.single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity) + + io.dout := Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2)) + io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0)) + } } diff --git a/target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class b/target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class new file mode 100644 index 00000000..3c2c0914 Binary files /dev/null and b/target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class differ diff --git a/target/scala-2.12/classes/ifu/EL2_IC_DATA.class b/target/scala-2.12/classes/ifu/EL2_IC_DATA.class new file mode 100644 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