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Bus-buffer testing start

This commit is contained in:
waleed-lm 2020-11-09 12:10:16 +05:00
parent 9a64685dfc
commit f3e4572e1c
6 changed files with 5345 additions and 5343 deletions
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7321
el2_lsu_bus_buffer.fir
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el2_lsu_bus_buffer.v
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11
src/main/scala/lsu/el2_lsu_bus_buffer.scala
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@ -421,12 +421,13 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)} obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)}
val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
WrPtr0_m := MuxCase(0.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | WrPtr0_m := MuxCase(0.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) &
(io.lsu_busreq_r & ((WrPtr0_r === i.U) | !((ibuf_valid & (ibuf_tag===i.U)) | (io.lsu_busreq_r &
(io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U)) ((WrPtr0_r === i.U) | (io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U))
io.buf_state := buf_state.reduce(Cat(_,_)) io.buf_state := buf_state.reverse.reduce(Cat(_,_))
val WrPtr1_m = MuxCase(0.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | val WrPtr1_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
WrPtr1_m := MuxCase(WrPtr1_r, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
(io.lsu_busreq_m & (WrPtr0_m===i.U)) | (io.lsu_busreq_m & (WrPtr0_m===i.U)) |
(io.lsu_busreq_r & (((WrPtr0_r === i.U)) | (io.lsu_busreq_r & (((WrPtr0_r === i.U)) |
(io.ldst_dual_r & (WrPtr1_r===i.U)))))) -> i.U)) (io.ldst_dual_r & (WrPtr1_r===i.U)))))) -> i.U))

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target/scala-2.12/classes/lsu/BusBufmain$.class
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target/scala-2.12/classes/lsu/BusBufmain$delayedInit$body.class
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target/scala-2.12/classes/lsu/el2_lsu_bus_buffer.class
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