From f60e035eeb2d343b50423dd38347a830fd89197d Mon Sep 17 00:00:00 2001 From: Jahanzaib-Rasheed Date: Thu, 10 Sep 2020 14:45:14 +0500 Subject: [PATCH] LSU clock domain skeleton --- src/main/scala/lsu/el2_lsu_bus_intf.scala | 17 ++--- src/main/scala/lsu/el2_lsu_clkdomain.scala | 74 ++++++++++++++-------- 2 files changed, 55 insertions(+), 36 deletions(-) diff --git a/src/main/scala/lsu/el2_lsu_bus_intf.scala b/src/main/scala/lsu/el2_lsu_bus_intf.scala index 6c76afa6..af781af0 100644 --- a/src/main/scala/lsu/el2_lsu_bus_intf.scala +++ b/src/main/scala/lsu/el2_lsu_bus_intf.scala @@ -1,7 +1,11 @@ + +package lsu import chisel3._ import chisel3.util._ - -class el2_lsu_bus_intf extends Module +import lib._ +import include._ +import snapshot._ +class el2_lsu_lsc_ctl extends Module { val io = IO (new Bundle { //val clk = Input(Clock()) //implicit @@ -108,10 +112,10 @@ class el2_lsu_bus_intf extends Module val lsu_axi_rready = Output(UInt(1.W)) val lsu_axi_rid = Input(UInt(pt1.LSU_BUS_TAG.W)) val lsu_axi_rdata = Input(UInt(64.W)) - val lsu_axi_rresp = Input(UInt(2.W)) - val lsu_axi_rlast = Input(UInt(1.W)) + val lsu_axi_rresp = Intput(UInt(2.W)) + val lsu_axi_rlast = Intput(UInt(1.W)) - val lsu_bus_clk_en = Input(UInt(1.W)) + val lsu_bus_clk_en = Intput(UInt(1.W)) }) val lsu_pkt_m = new el2_lsu_pkt_t() @@ -178,6 +182,3 @@ class el2_lsu_bus_intf extends Module } -object busIntfMain extends App { - println(chisel3.Driver.emitVerilog(new el2_lsu_bus_intf)) -} diff --git a/src/main/scala/lsu/el2_lsu_clkdomain.scala b/src/main/scala/lsu/el2_lsu_clkdomain.scala index e9745702..9ee29685 100644 --- a/src/main/scala/lsu/el2_lsu_clkdomain.scala +++ b/src/main/scala/lsu/el2_lsu_clkdomain.scala @@ -1,3 +1,5 @@ + +package lsu import chisel3._ import chisel3.util._ import lib._ @@ -77,7 +79,7 @@ class el2_lsu_clkdomain extends Module { // Clock Enable Logic //------------------------------------------------------------------------------------------- - lsu_c1_d_clken := lsu_p.valid | io.dma_dccm_req | io.clk_override + lsu_c1_d_clken := lsu_p.valid | io.dma_dccm_req | io.clk_override lsu_c1_m_clken := lsu_pkt_d.valid | lsu_c1_d_clken_q | io.clk_override lsu_c1_r_clken := lsu_pkt_m.valid | lsu_c1_m_clken_q | io.clk_override @@ -86,42 +88,58 @@ class el2_lsu_clkdomain extends Module { lsu_store_c1_m_clken := ((lsu_c1_m_clken & lsu_pkt_d.store) | io.clk_override) lsu_store_c1_r_clken := ((lsu_c1_r_clken & lsu_pkt_m.store) | io.clk_override) - - lsu_stbuf_c1_clken := io.ldst_stbuf_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override - lsu_bus_ibuf_c1_clken := io.lsu_busreq_r | io.clk_override - lsu_bus_obuf_c1_clken := (io.lsu_bus_buffer_pend_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en - lsu_bus_buf_c1_clken := ~io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override + lsu_stbuf_c1_clken := st_stbu_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override + lsu_bus_ibuf_c1_clken := io.lsu_busreq_r | io.clk_override + lsu_bus_obuf_c1_clken := (io.lsu_bus_buffer_pend_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en + lsu_bus_buf_c1_clken := ~io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override lsu_free_c1_clken := (lsu_p.valid | lsu_pkt_d.valid | lsu_pkt_m.valid | lsu_pkt_r.valid) | ~io.lsu_bus_buffer_empty_any | ~io.lsu_stbuf_empty_any | io.clk_override - lsu_free_c2_clken := lsu_free_c1_clken | lsu_free_c1_clken_q | io.clk_override -/* - // Flops - rvdff #(1) lsu_free_c1_clkenff (.din(lsu_free_c1_clken), dout(lsu_free_c1_clken_q), clk(free_clk), *) + lsu_free_c2_clken := lsu_free_c1_clken | lsu_free_c1_clken_q | io.clk_override - rvdff #(1) lsu_c1_d_clkenff (.din(lsu_c1_d_clken), dout(lsu_c1_d_clken_q), clk(lsu_free_c2_clk), *) - rvdff #(1) lsu_c1_m_clkenff (.din(lsu_c1_m_clken), dout(lsu_c1_m_clken_q), clk(lsu_free_c2_clk), *) - rvdff #(1) lsu_c1_r_clkenff (.din(lsu_c1_r_clken), dout(lsu_c1_r_clken_q), clk(lsu_free_c2_clk), *) + io.lsu_c1_m_clk := 0.U // m pipe single pulse clock + io.lsu_c1_r_clk := 0.U // r pipe single pulse clock - // Clock Headers - rvoclkhdr lsu_c1m_cgc ( .en(lsu_c1_m_clken), l1clk(lsu_c1_m_clk), * ) - rvoclkhdr lsu_c1r_cgc ( .en(lsu_c1_r_clken), l1clk(lsu_c1_r_clk), * ) + io.lsu_c2_m_clk := 0.U // m pipe double pulse clock + io.lsu_c2_r_clk := 0.U // r pipe double pulse clock - rvoclkhdr lsu_c2m_cgc ( .en(lsu_c2_m_clken), l1clk(lsu_c2_m_clk), * ) - rvoclkhdr lsu_c2r_cgc ( .en(lsu_c2_r_clken), l1clk(lsu_c2_r_clk), * ) + io.lsu_store_c1_m_clk := 0.U // store in m + io.lsu_store_c1_r_clk := 0.U // store in r - rvoclkhdr lsu_store_c1m_cgc (.en(lsu_store_c1_m_clken), l1clk(lsu_store_c1_m_clk), *) - rvoclkhdr lsu_store_c1r_cgc (.en(lsu_store_c1_r_clken), l1clk(lsu_store_c1_r_clk), *) + io.lsu_stbuf_c1_clk := 0.U + io.lsu_bus_obuf_c1_clk := 0.U // ibuf clock + io.lsu_bus_ibuf_c1_clk := 0.U // ibuf clock + io.lsu_bus_buf_c1_clk := 0.U // ibuf clock + io.lsu_busm_clk := 0.U // bus clock - rvoclkhdr lsu_stbuf_c1_cgc ( .en(lsu_stbuf_c1_clken), l1clk(lsu_stbuf_c1_clk), * ) - rvoclkhdr lsu_bus_ibuf_c1_cgc ( .en(lsu_bus_ibuf_c1_clken), l1clk(lsu_bus_ibuf_c1_clk), * ) - rvclkhdr lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), l1clk(lsu_bus_obuf_c1_clk), * ) - rvoclkhdr lsu_bus_buf_c1_cgc ( .en(lsu_bus_buf_c1_clken) = - val .l1clk(lsu_bus_buf_c1_clk), * ) + io.lsu_free_c2_clk := 0.U - rvclkhdr lsu_busm_cgc (.en(lsu_bus_clk_en), l1clk(lsu_busm_clk), *) + /*0.U // Flops + rvdff #(1) lsu_free_c1_clkenff (.din(lsu_free_c1_clken), dout(lsu_free_c1_clken_q), clk(free_clk), *) - rvoclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), l1clk(lsu_free_c2_clk), *) + rvdff #(1) lsu_c1_d_clkenff (.din(lsu_c1_d_clken), dout(lsu_c1_d_clken_q), clk(lsu_free_c2_clk), *) + rvdff #(1) lsu_c1_m_clkenff (.din(lsu_c1_m_clken), dout(lsu_c1_m_clken_q), clk(lsu_free_c2_clk), *) + rvdff #(1) lsu_c1_r_clkenff (.din(lsu_c1_r_clken), dout(lsu_c1_r_clken_q), clk(lsu_free_c2_clk), *) -*/ + // Clock Headers + rvoclkhdr lsu_c1m_cgc ( .en(lsu_c1_m_clken), l1clk(lsu_c1_m_clk), * ) + rvoclkhdr lsu_c1r_cgc ( .en(lsu_c1_r_clken), l1clk(lsu_c1_r_clk), * ) + + rvoclkhdr lsu_c2m_cgc ( .en(lsu_c2_m_clken), l1clk(lsu_c2_m_clk), * ) + rvoclkhdr lsu_c2r_cgc ( .en(lsu_c2_r_clken), l1clk(lsu_c2_r_clk), * ) + + rvoclkhdr lsu_store_c1m_cgc (.en(lsu_store_c1_m_clken), l1clk(lsu_store_c1_m_clk), *) + rvoclkhdr lsu_store_c1r_cgc (.en(lsu_store_c1_r_clken), l1clk(lsu_store_c1_r_clk), *) + + rvoclkhdr lsu_stbuf_c1_cgc ( .en(lsu_stbuf_c1_clken), l1clk(lsu_stbuf_c1_clk), * ) + rvoclkhdr lsu_bus_ibuf_c1_cgc ( .en(lsu_bus_ibuf_c1_clken), l1clk(lsu_bus_ibuf_c1_clk), * ) + rvclkhdr lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), l1clk(lsu_bus_obuf_c1_clk), * ) + rvoclkhdr lsu_bus_buf_c1_cgc ( .en(lsu_bus_buf_c1_clken) = + val .l1clk(lsu_bus_buf_c1_clk), * ) + + rvclkhdr lsu_busm_cgc (.en(lsu_bus_clk_en), l1clk(lsu_busm_clk), *) + + rvoclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), l1clk(lsu_free_c2_clk), *) + + */ }