shiftq_ff corrected

src/main/scala/exu/exu_div_ctl.scala

@@ -583,69 +583,25 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
     val data_out              = Output(UInt(32.W))
     val valid_out             = Output(UInt(1.W))
   })
-
- // val valid_ff_in          = WireInit(Bool(),init=false.B)
   val valid_ff             = WireInit(Bool(),init=false.B)
- // val finish_raw           = WireInit(Bool(),init=false.B)
-  //val finish               = WireInit(Bool(),init=false.B)
   val finish_ff            = WireInit(Bool(),init=false.B)
-//  val running_state        = WireInit(Bool(),init=false.B)
-//  val misc_enable          = WireInit(Bool(),init=false.B)
-//  val control_in           = WireInit(0.U(3.W))
   val control_ff           = WireInit(0.U(3.W))
-//   val dividend_sign_ff     = WireInit(Bool(),init=false.B)
-//    val divisor_sign_ff      = WireInit(Bool(),init=false.B)
-//    val count_enable         = WireInit(Bool(),init=false.B)
-//    val count_in             = WireInit(0.U(7.W))
   val count_ff             = WireInit(0.U(7.W))
   val smallnum             = WireInit(0.U(4.W))
- //  val smallnum_case        = WireInit(Bool(),init=false.B)
-//  val a_enable             = WireInit(Bool(),init=false.B)
-//  val a_shift              = WireInit(Bool(),init=false.B)
-//  val b_enable             = WireInit(Bool(),init=false.B)
-//  val b_twos_comp          = WireInit(Bool(),init=false.B)
-//  val a_in                 = WireInit(0.U(33.W))
   val a_ff                 = WireInit(0.U(33.W))
-  //  val b_in                 = WireInit(0.U(33.W))
   val b_ff1                = WireInit(0.U(33.W))
   val b_ff                 = WireInit(0.U(37.W))
- //   val q_in                 = WireInit(0.U(32.W))
   val q_ff                 = WireInit(0.U(32.W))
- //  val r_in                 = WireInit(0.U(33.W))
   val r_ff                 = WireInit(0.U(33.W))
-  //  val rq_enable            = WireInit(Bool(),init=false.B)
- //  val r_sign_sel           = WireInit(Bool(),init=false.B)
- //  val r_restore_sel        = WireInit(Bool(),init=false.B)
-   // val r_adder1_sel         = WireInit(Bool(),init=false.B)
-  //  val r_adder2_sel         = WireInit(Bool(),init=false.B)
- //  val r_adder3_sel         = WireInit(Bool(),init=false.B)
-  //  val r_adder4_sel         = WireInit(Bool(),init=false.B)
-  //  val r_adder5_sel         = WireInit(Bool(),init=false.B)
-  // val r_adder6_sel         = WireInit(Bool(),init=false.B)
- //  val r_adder7_sel         = WireInit(Bool(),init=false.B)
-//    val twos_comp_q_sel      = WireInit(Bool(),init=false.B)
-//    val twos_comp_b_sel      = WireInit(Bool(),init=false.B)
   val quotient_raw         = WireInit(0.U(8.W))
   val quotient_new         = WireInit(0.U(3.W))
   val shortq_enable        = WireInit(Bool(),init=false.B)
   val shortq_enable_ff     = WireInit(Bool(),init=false.B)
- //   val by_zero_case         = WireInit(Bool(),init=false.B)
   val by_zero_case_ff      = WireInit(Bool(),init=false.B)
- //  val twos_comp_in         = WireInit(0.U(32.W))
- //   val twos_comp_out        = WireInit(0.U(32.W))
- //  val adder1_out            = WireInit(0.U(34.W))
-//   val adder2_out            = WireInit(0.U(35.W))
- //   val adder3_out            = WireInit(0.U(36.W))
-//   val adder4_out            = WireInit(0.U(37.W))
- //  val adder5_out            = WireInit(0.U(37.W))
- //   val adder6_out            = WireInit(0.U(37.W))
-//    val adder7_out            = WireInit(0.U(37.W))
   val ar_shifted           = WireInit(0.U(66.W))
-//  val shortq               = WireInit(0.U(6.W))
- //  val shortq_shift         = WireInit(0.U(5.W))
+  val shortq_shift        = WireInit(0.U(5.W))
   val shortq_decode        = WireInit(0.U(5.W))
   val shortq_shift_ff      = WireInit(0.U(5.W))
-//   val shortq_dividend      = WireInit(0.U(33.W))
   val valid_ff_in = io.valid_in & !io.cancel
   val control_in           = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in  & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in  &  io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in))
   val dividend_sign_ff     = control_ff(2)
@@ -663,7 +619,7 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
   val count_in             = Fill(7,count_enable) & (count_ff + Cat(0.U(5.W),3.U(2.W)) + Cat(0.U(2.W),shortq_shift_ff))
   val a_enable             =  io.valid_in | running_state
   val a_shift              =  running_state & !shortq_enable_ff
-  ar_shifted               := Cat (Fill(33,dividend_sign_ff),a_ff) << shortq_shift_ff
+  ar_shifted               := Cat (Fill(33,dividend_sign_ff),a_ff) << shortq_shift_ff(4,0)
   val b_twos_comp          =  valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
   val twos_comp_b_sel      =  valid_ff  & !(dividend_sign_ff ^ divisor_sign_ff)
   val twos_comp_q_sel      = !valid_ff & !rem_ff &  (dividend_sign_ff ^ divisor_sign_ff) & !by_zero_case_ff
@@ -773,13 +729,13 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
   shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) ===  "b111".U) & !io.cancel
   val list = Array(27,27,27,27,27,27,24,24,24,21,21,21,18,18,18,15,15,15,12,12,12,9,9,9,6,6,6,3,0,0,0,0)
   shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U))
-  val shortq_shift = Mux(!shortq_enable,0.U,shortq_decode)
+  shortq_shift := Mux(!shortq_enable,0.U,shortq_decode)
   b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1)
   valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode)
   control_ff   := rvdffe(control_in, misc_enable,clock,io.scan_mode)
   by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode)
   shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode)
-  shortq_shift_ff := Cat(rvdffe(shortq_shift, misc_enable,clock,io.scan_mode),0.U)
+  shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode)
   finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode)
   count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode)