BP corrected
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ed92fad092
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52177
ifu_bp_ctl.fir
52177
ifu_bp_ctl.fir
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15966
ifu_bp_ctl.v
15966
ifu_bp_ctl.v
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@ -255,7 +255,6 @@ if(!BTB_FULLYA) {
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//io.test := btb_lru_b0_ns
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// Checking if the end of line is near
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val eoc_near = io.ifc_fetch_addr_f(ICACHE_BEAT_ADDR_HI-1, 2).andR
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// Mask according to eoc-near and make the hit-final
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eoc_mask := !eoc_near | (~io.ifc_fetch_addr_f(1,0)).orR()
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@ -357,7 +356,6 @@ if(!BTB_FULLYA) {
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val btb_fg_crossing_f = fetch_start_f(0) & btb_sel_f(0) & btb_rd_pc4_f
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val bp_total_branch_offset_f = bloc_f(1)^btb_rd_pc4_f
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val ifc_fetch_adder_prior = rvdfflie_UInt(io.ifc_fetch_addr_f(30,1), clock,reset.asAsyncReset,(io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f).asBool,io.scan_mode,WIDTH =30, LEFT =19 )
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io.ifu_bp_poffset_f := btb_rd_tgt_f
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@ -407,7 +405,6 @@ if(!BTB_FULLYA) {
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// vwayhit_f := Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool -> wayhit_f,
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// io.ifc_fetch_addr_f(0).asBool -> Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
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// }
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// Making the data to write into the BTB according the structure discribed above
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val btb_wr_data = Cat(btb_wr_tag, exu_mp_tgt, exu_mp_pc4, exu_mp_boffset, exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid)
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val exu_mp_valid_write = exu_mp_valid & exu_mp_ataken & !io.exu_bp.exu_mp_pkt.valid
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@ -439,8 +436,10 @@ if(!BTB_FULLYA) {
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// Writing is always done from dec or exu check if the dec have a valid data
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val btb_wr_addr = Mux(dec_tlu_error_wb.asBool, btb_error_addr_wb, exu_mp_addr)
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vwayhit_f := Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool -> wayhit_f,
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io.ifc_fetch_addr_f(0).asBool -> Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
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vwayhit_f := Mux1H(Seq(
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io.ifc_fetch_addr_f(0).asBool -> wayhit_f,
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io.ifc_fetch_addr_f(1).asBool -> Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
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val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode))
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val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode))
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