Hist0-1 shut-down

el2_ifu_bp_ctl.anno.json

@@ -25,13 +25,6 @@
       "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
     ]
   },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hist0_f",
-    "sources":[
-      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f"
-    ]
-  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_way_f",
@@ -48,19 +41,6 @@
       "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
     ]
   },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hist1_f",
-    "sources":[
-      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
-      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
-      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
-      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_error",
-      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
-    ]
-  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_poffset_f",

src/main/scala/ifu/el2_ifu_bp_ctl.scala

@@ -40,17 +40,6 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
     val ifu_bp_poffset_f = Output(UInt(12.W))
   })
 
-  io.ifu_bp_hit_taken_f := 0.U
-  io.ifu_bp_btb_target_f := 0.U
-  io.ifu_bp_inst_mask_f := 0.U
-  io.ifu_bp_fghr_f := 0.U
-  io.ifu_bp_way_f := 0.U
-  io.ifu_bp_ret_f := 0.U
-  io.ifu_bp_hist1_f := 0.U
-  io.ifu_bp_hist0_f := 0.U
-  io.ifu_bp_pc4_f := 0.U
-  io.ifu_bp_valid_f := 0.U
-  io.ifu_bp_poffset_f := 0.U
   val TAG_START = 16+BTB_BTAG_SIZE
   val PC4 = 4
   val BOFF = 3
@@ -295,8 +284,8 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
   io.ifu_bp_fghr_f := fghr
 
   io.ifu_bp_way_f := way_raw
-  io.ifu_bp_hist1_f := hist1_raw
-  io.ifu_bp_hist0_f := hist0_raw
+  io.ifu_bp_hist1_f := 1.U//hist1_raw
+  io.ifu_bp_hist0_f := 2.U//hist0_raw
   io.ifu_bp_pc4_f := pc4_raw
 
   io.ifu_bp_valid_f := vwayhit_f & ~Fill(2, io.dec_tlu_bpred_disable)
@@ -399,15 +388,16 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
       (bht_wr_en2(i) & (bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt) & ((bht_wr_addr2(BHT_ADDR_HI-BHT_ADDR_LO, NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt) | BHT_NO_ADDR_MATCH.B))
   }
 
-// Blah blah
   val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W))))
   for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
-    bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j))//&bht_bank_clken(i)(k))
+    bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j) & bht_bank_clken(i)(k))
   }
 
   bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i)))
   bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
   bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
+
+
 }
 
 object ifu_bp extends App {

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -230,6 +230,10 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   io.ic_dma_active := iccm_correct_ecc | (perr_state === dma_sb_err_C) | (err_stop_state === err_stop_fetch_C) | err_stop_fetch | io.dec_tlu_flush_err_wb
   val scnd_miss_req_in = ifu_bus_rsp_valid & bus_ifu_bus_clk_en & ifu_bus_rsp_ready & bus_new_data_beat_count.andR &
     !uncacheable_miss_ff ((miss_state === scnd_miss_C)|(miss_nxtstate === scnd_miss_C)) & !io.exu_flush_final
+
+  val ifu_bp_hit_taken_q_f = io.ifu_bp_hit_taken_f & io.ic_hit_f
+
+
 }
 object ifu_mem extends App {
   println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl()))