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Bus-buffer testing start

This commit is contained in:
waleed-lm 2020-11-07 00:54:52 +05:00
parent 63b7686462
commit fa8b783fce
4 changed files with 5134 additions and 5087 deletions
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6948
el2_lsu_bus_buffer.fir
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3269
el2_lsu_bus_buffer.v
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4
src/main/scala/lsu/el2_lsu_bus_buffer.scala
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@ -389,8 +389,8 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, io.lsu_busm_clk, io.scan_mode) val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, io.lsu_busm_clk, io.scan_mode)
obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)} obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)}
val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
val found_array1 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | val found_array1 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((Fill(DEPTH_LOG2,ibuf_valid) & (ibuf_tag===i.U)) |
(io.lsu_busreq_m & (WrPtr0_r===i.U)) | (io.ldst_dual_r & (WrPtr1_r === i.U))))->i.U) (Fill(DEPTH_LOG2, io.lsu_busreq_m) & (WrPtr0_r===i.U)) | (Fill(DEPTH_LOG2, io.ldst_dual_r) & (WrPtr1_r === i.U))))->i.U)
WrPtr0_m := MuxCase(0.U, found_array1) WrPtr0_m := MuxCase(0.U, found_array1)
val found_array2 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | val found_array2 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
(io.lsu_busreq_m & (WrPtr0_m===i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U)) | (io.ldst_dual_r & (WrPtr1_r===i.U))))->i.U) (io.lsu_busreq_m & (WrPtr0_m===i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U)) | (io.ldst_dual_r & (WrPtr1_r===i.U))))->i.U)

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target/scala-2.12/classes/lsu/el2_lsu_bus_buffer.class
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