diff --git a/soc/ahb_sif.sv b/soc/ahb_sif.sv
index 56b3c696..b0971689 100644
--- a/soc/ahb_sif.sv
+++ b/soc/ahb_sif.sv
@@ -53,58 +53,76 @@ module axi_slv #(
     output reg [TAGW-1:0] bid
 );
 
-  parameter MEM_DEPTH = 12;  // memory size = 0x8000 = 32k WIDTH=15
+  parameter MEM_DEPTH = 15;  // memory size = 0x8000 = 32k WIDTH=15
+  parameter MEM_DEPTH_EACH = MEM_DEPTH - 3;  // memory size = 0x8000 = 32k WIDTH=15
 
-  bit [7:0] mem[(1<<MEM_DEPTH)-1:0];
+  bit [7:0] mem0[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem1[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem2[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem3[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem4[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem5[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem6[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem7[(1<<MEM_DEPTH_EACH)-1:0];
 
   bit [63:0] memdata;
 
-  wire [MEM_DEPTH-1:0] saraddr = araddr[MEM_DEPTH-1:0];
-  wire [MEM_DEPTH-1:0] sawaddr = awaddr[MEM_DEPTH-1:0];
+  wire [MEM_DEPTH-1:0] saraddr = araddr[MEM_DEPTH - 1:0];
+  wire [MEM_DEPTH-1:0] sawaddr = awaddr[MEM_DEPTH - 1:0];
 
+  initial begin
+    mem0[0]= 8'h0;
+    mem0[1]= 8'h0;
+    mem0[2]= 8'h0;
+    mem0[3]= 8'h63;
+    mem0[5]= 8'h0;
+    mem0[6]= 8'h0;
+    mem0[7]= 8'h0;
+    mem0[8]= 8'h0;
+  end
   always @(posedge aclk or negedge rst_l) begin
     if (!rst_l) begin
       rvalid <= 0;
       bvalid <= 0;
     end else begin
-      bid    <= awid;
-      rid    <= arid;
+      bid <= awid;
+      rid <= arid;
       rvalid <= arvalid;
       bvalid <= awvalid;
-      rdata  <= memdata;
+      rdata <= memdata;
     end
   end
 
   always @(negedge aclk) begin
     if (arvalid)
       memdata <= {
-        mem[saraddr+7],
-        mem[saraddr+6],
-        mem[saraddr+5],
-        mem[saraddr+4],
-        mem[saraddr+3],
-        mem[saraddr+2],
-        mem[saraddr+1],
-        mem[saraddr]
+        mem7[saraddr + 7],
+        mem6[saraddr + 6],
+        mem5[saraddr + 5],
+        mem4[saraddr + 4],
+        mem3[saraddr + 3],
+        mem2[saraddr + 2],
+        mem1[saraddr + 1],
+        mem0[saraddr]
       };
     if (awvalid) begin
-      if (wstrb[7]) mem[sawaddr+7] = wdata[63:56];
-      if (wstrb[6]) mem[sawaddr+6] = wdata[55:48];
-      if (wstrb[5]) mem[sawaddr+5] = wdata[47:40];
-      if (wstrb[4]) mem[sawaddr+4] = wdata[39:32];
-      if (wstrb[3]) mem[sawaddr+3] = wdata[31:24];
-      if (wstrb[2]) mem[sawaddr+2] = wdata[23:16];
-      if (wstrb[1]) mem[sawaddr+1] = wdata[15:08];
-      if (wstrb[0]) mem[sawaddr+0] = wdata[07:00];
+      if (wstrb[7]) mem7[sawaddr + 7] = wdata[63:56];
+      if (wstrb[6]) mem6[sawaddr + 6] = wdata[55:48];
+      if (wstrb[5]) mem5[sawaddr + 5] = wdata[47:40];
+      if (wstrb[4]) mem4[sawaddr + 4] = wdata[39:32];
+      if (wstrb[3]) mem3[sawaddr + 3] = wdata[31:24];
+      if (wstrb[2]) mem2[sawaddr + 2] = wdata[23:16];
+      if (wstrb[1]) mem1[sawaddr + 1] = wdata[15:08];
+      if (wstrb[0]) mem0[sawaddr + 0] = wdata[07:00];
     end
   end
 
 
   assign arready = 1'b1;
   assign awready = 1'b1;
-  assign wready  = 1'b1;
-  assign rresp   = 2'b0;
-  assign bresp   = 2'b0;
-  assign rlast   = 1'b1;
+  assign wready = 1'b1;
+  assign rresp = 2'b0;
+  assign bresp = 2'b0;
+  assign rlast = 1'b1;
 
 endmodule