diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 1a72b2b1..13df2aaa 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -109073,5728 +109073,723 @@ circuit quasar_wrapper : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_849 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_849 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_849 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_850 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_850 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_850 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_851 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_851 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_851 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_852 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_852 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_852 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_853 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_853 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_853 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_854 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_854 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_854 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_855 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_855 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_855 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_856 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_856 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_856 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_857 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_857 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_857 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_858 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_858 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_858 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 55:11] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 57:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 58:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 59:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 63:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 63:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 63:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 63:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 63:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 63:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 63:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<1> - slave_tag <= UInt<1>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<1> - wrbuf_tag <= UInt<1>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 83:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 84:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<1> - master_tag <= UInt<1>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<1> - buf_tag <= UInt<1>("h00") - wire buf_tag_in : UInt<1> - buf_tag_in <= UInt<1>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<1> - slvbuf_tag <= UInt<1>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 151:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 172:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 172:14] - node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 173:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 173:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 174:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 174:51] - node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 174:76] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 174:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 174:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 175:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 175:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 175:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 176:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 176:53] - node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 176:75] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 176:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 176:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 177:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 177:53] - node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 177:74] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 177:21] - master_size <= _T_22 @[axi4_to_ahb.scala 177:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 178:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 178:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 179:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 179:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 182:32] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 182:57] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 182:46] - io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 182:17] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 183:32] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 183:59] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 183:49] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 183:22] - io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 183:16] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 184:26] - io.axi_bid <= _T_32 @[axi4_to_ahb.scala 184:14] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 186:32] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 186:58] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 186:65] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 186:46] - io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 186:17] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 187:32] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 187:59] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 187:49] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 187:22] - io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 187:16] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 188:26] - io.axi_rid <= _T_41 @[axi4_to_ahb.scala 188:14] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 189:30] - io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 189:16] - node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 190:32] - slave_ready <= _T_43 @[axi4_to_ahb.scala 190:15] - node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 193:56] - node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 193:91] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20] - inst rvclkhdr of rvclkhdr_849 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59] - inst rvclkhdr_1 of rvclkhdr_850 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 196:17] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 199:21] - master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 200:16] - buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 201:16] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 202:18] - buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 204:18] - slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 205:21] - slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 206:21] - buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 207:18] - cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 208:18] - trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 209:18] - buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:23] - buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] - slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 213:19] - bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 214:20] - rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 219:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 220:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 220:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 220:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 221:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 221:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 221:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 222:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 222:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 223:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 224:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 224:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 224:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 227:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 168:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 169:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 169:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 169:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 169:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 169:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 169:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 169:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 169:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 227:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 227:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 227:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 228:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 229:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 229:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 229:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 230:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 230:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 234:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 234:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 234:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 234:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 234:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 234:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 235:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 235:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 235:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 235:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 235:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 235:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 236:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 236:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 236:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 237:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 238:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 238:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 238:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 238:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 238:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 238:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 238:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 238:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 238:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 238:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 238:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 238:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 238:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 239:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 240:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 240:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 241:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 241:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 241:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 241:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 241:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 242:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 242:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 242:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 242:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 246:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 246:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 246:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 246:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 246:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 246:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 246:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 246:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 247:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 247:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 247:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 247:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 247:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 248:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 248:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 248:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 248:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 248:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 248:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 248:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 248:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 248:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 249:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 249:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 250:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 251:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 252:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 253:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 253:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 253:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 254:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 254:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 254:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 255:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 255:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 255:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 255:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 255:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 256:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 256:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 256:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 256:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 256:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 257:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 257:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 257:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 257:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 257:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 258:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 262:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 263:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 263:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 263:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 263:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 264:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 265:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 266:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 266:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 267:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 267:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 267:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 271:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 272:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 272:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 273:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 274:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 275:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 276:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 280:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 281:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 281:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 281:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 281:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 281:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 282:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 283:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 284:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 285:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 285:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 285:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 168:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 168:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 169:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 169:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 169:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 169:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 169:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 169:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 169:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 169:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 285:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 285:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 286:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 286:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 286:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 286:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 168:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 168:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 169:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 169:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 169:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 169:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 169:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 169:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 169:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 169:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 286:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 286:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 286:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 286:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 286:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 286:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 287:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 287:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 287:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 287:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 291:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 291:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 291:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 292:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 292:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 292:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 292:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 293:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 293:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 293:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 293:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 293:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 293:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 293:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 293:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 293:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 294:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 295:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 296:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 296:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 296:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 297:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 297:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 297:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 297:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 297:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 298:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 299:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 299:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 299:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 300:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 300:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 300:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 168:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 168:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 169:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 169:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 169:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 169:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 169:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 169:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 169:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 169:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 300:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 300:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 300:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 300:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 299:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 299:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 299:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 301:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 301:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 301:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 301:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 302:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 302:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 302:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 302:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 302:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 303:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 303:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 303:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 304:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 304:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 304:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 304:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 304:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 305:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 305:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 306:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 168:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 169:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 169:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 169:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 169:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 169:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 169:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 169:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 169:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 168:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 168:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 169:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 169:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 169:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 169:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 169:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 169:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 169:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 169:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 306:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 306:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 306:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 328:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 329:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 330:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 331:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 335:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 336:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 336:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 336:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 336:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 336:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 336:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 160:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 160:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 160:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 160:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 160:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 161:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 161:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 161:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 160:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 162:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 162:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 162:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 162:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 161:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 163:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 163:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 163:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 162:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 164:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 164:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 164:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 336:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 336:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 336:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 337:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 337:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 338:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 338:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 339:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 339:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 339:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 339:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 339:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 340:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 340:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 340:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 340:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 340:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 340:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 340:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 154:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 154:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 154:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 155:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 155:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 155:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 155:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 154:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 156:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 156:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 156:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 156:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 156:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 156:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 156:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 156:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 155:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 340:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 340:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 341:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 341:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 342:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 341:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 342:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 342:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 342:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 342:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 343:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 343:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 343:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 343:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 343:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 343:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 343:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 343:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 344:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 343:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 344:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 344:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 344:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 344:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 343:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 342:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 341:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 346:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 346:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 346:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 346:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 346:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 347:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 347:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 347:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 347:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 347:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 347:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 347:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 349:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 350:24] - node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 351:51] - node _T_588 = not(_T_587) @[axi4_to_ahb.scala 351:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 351:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 352:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 352:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 352:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 352:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 353:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 353:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 355:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 356:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 356:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 356:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 356:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 357:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 357:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 357:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 357:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 357:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 357:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 357:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 357:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 358:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 358:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 360:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 360:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 360:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 360:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 360:16] - node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 362:30] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 362:47] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 362:12] - node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 363:34] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 363:50] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 363:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 364:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 364:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 364:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 364:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 364:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 365:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 365:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 365:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 367:35] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 367:33] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 367:21] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 367:52] - io.axi_awready <= _T_627 @[axi4_to_ahb.scala 367:18] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 368:39] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 368:37] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 368:20] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 368:56] - io.axi_wready <= _T_631 @[axi4_to_ahb.scala 368:17] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 369:33] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 369:21] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 369:51] - io.axi_arready <= _T_634 @[axi4_to_ahb.scala 369:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 370:16] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 372:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 372:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 372:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 372:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 372:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 372:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 372:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 373:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 373:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 373:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 373:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 373:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 373:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 373:21] - node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 374:65] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 374:99] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 374:21] - node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 375:67] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 375:95] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55] - inst rvclkhdr_2 of rvclkhdr_851 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi_awaddr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59] - inst rvclkhdr_3 of rvclkhdr_852 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi_wdata @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 377:21] - node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 378:66] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 378:99] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 378:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 379:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 379:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 379:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 380:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 380:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 381:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 381:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 381:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78] - inst rvclkhdr_4 of rvclkhdr_853 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 382:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 383:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 383:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 383:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 384:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 384:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 385:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 385:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89] - inst rvclkhdr_5 of rvclkhdr_854 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 386:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 387:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 388:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 388:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 389:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 389:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 390:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 390:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 390:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 390:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 390:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 390:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 390:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 391:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 391:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 391:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 392:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 392:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 392:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 393:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 393:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 393:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 393:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 394:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 394:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 394:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 395:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 395:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 395:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 396:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 396:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 396:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 398:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 398:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 398:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 398:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 399:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 399:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 399:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 399:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 399:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 400:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19] - inst rvclkhdr_6 of rvclkhdr_855 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12] - inst rvclkhdr_7 of rvclkhdr_856 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12] - inst rvclkhdr_8 of rvclkhdr_857 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17] - inst rvclkhdr_9 of rvclkhdr_858 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17] - - extmodule gated_latch_859 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_859 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_859 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_860 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_860 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_860 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_861 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_861 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_861 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_862 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_862 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_862 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_863 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_863 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_863 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_864 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_864 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_864 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_865 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_865 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_865 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_866 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_866 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_866 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_867 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_867 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_867 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_868 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_868 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_868 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb_1 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 55:11] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 57:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 58:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 59:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 63:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 63:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 63:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 63:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 63:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 63:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 63:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<1> - slave_tag <= UInt<1>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<1> - wrbuf_tag <= UInt<1>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 83:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 84:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<1> - master_tag <= UInt<1>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<1> - buf_tag <= UInt<1>("h00") - wire buf_tag_in : UInt<1> - buf_tag_in <= UInt<1>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<1> - slvbuf_tag <= UInt<1>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 151:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 172:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 172:14] - node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 173:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 173:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 174:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 174:51] - node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 174:76] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 174:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 174:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 175:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 175:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 175:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 176:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 176:53] - node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 176:75] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 176:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 176:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 177:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 177:53] - node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 177:74] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 177:21] - master_size <= _T_22 @[axi4_to_ahb.scala 177:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 178:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 178:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 179:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 179:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 182:32] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 182:57] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 182:46] - io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 182:17] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 183:32] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 183:59] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 183:49] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 183:22] - io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 183:16] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 184:26] - io.axi_bid <= _T_32 @[axi4_to_ahb.scala 184:14] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 186:32] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 186:58] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 186:65] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 186:46] - io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 186:17] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 187:32] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 187:59] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 187:49] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 187:22] - io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 187:16] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 188:26] - io.axi_rid <= _T_41 @[axi4_to_ahb.scala 188:14] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 189:30] - io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 189:16] - node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 190:32] - slave_ready <= _T_43 @[axi4_to_ahb.scala 190:15] - node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 193:56] - node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 193:91] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20] - inst rvclkhdr of rvclkhdr_859 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59] - inst rvclkhdr_1 of rvclkhdr_860 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 196:17] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 199:21] - master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 200:16] - buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 201:16] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 202:18] - buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 204:18] - slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 205:21] - slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 206:21] - buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 207:18] - cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 208:18] - trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 209:18] - buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:23] - buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] - slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 213:19] - bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 214:20] - rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 219:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 220:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 220:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 220:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 221:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 221:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 221:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 222:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 222:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 223:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 224:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 224:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 224:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 227:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 168:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 169:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 169:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 169:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 169:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 169:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 169:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 169:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 169:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 227:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 227:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 227:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 228:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 229:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 229:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 229:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 230:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 230:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 234:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 234:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 234:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 234:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 234:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 234:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 235:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 235:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 235:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 235:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 235:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 235:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 236:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 236:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 236:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 237:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 238:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 238:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 238:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 238:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 238:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 238:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 238:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 238:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 238:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 238:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 238:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 238:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 238:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 239:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 240:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 240:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 241:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 241:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 241:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 241:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 241:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 242:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 242:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 242:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 242:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 246:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 246:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 246:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 246:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 246:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 246:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 246:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 246:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 247:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 247:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 247:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 247:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 247:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 248:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 248:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 248:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 248:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 248:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 248:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 248:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 248:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 248:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 249:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 249:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 250:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 251:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 252:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 253:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 253:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 253:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 254:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 254:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 254:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 255:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 255:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 255:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 255:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 255:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 256:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 256:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 256:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 256:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 256:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 257:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 257:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 257:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 257:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 257:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 258:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 262:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 263:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 263:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 263:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 263:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 264:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 265:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 266:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 266:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 267:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 267:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 267:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 271:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 272:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 272:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 273:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 274:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 275:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 276:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 280:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 281:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 281:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 281:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 281:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 281:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 282:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 283:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 284:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 285:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 285:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 285:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 168:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 168:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 169:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 169:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 169:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 169:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 169:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 169:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 169:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 169:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 285:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 285:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 286:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 286:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 286:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 286:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 168:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 168:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 169:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 169:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 169:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 169:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 169:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 169:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 169:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 169:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 286:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 286:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 286:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 286:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 286:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 286:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 287:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 287:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 287:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 287:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 291:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 291:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 291:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 292:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 292:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 292:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 292:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 293:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 293:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 293:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 293:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 293:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 293:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 293:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 293:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 293:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 294:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 295:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 296:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 296:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 296:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 297:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 297:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 297:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 297:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 297:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 298:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 299:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 299:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 299:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 300:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 300:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 300:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 168:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 168:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 169:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 169:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 169:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 169:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 169:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 169:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 169:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 169:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 300:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 300:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 300:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 300:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 299:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 299:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 299:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 301:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 301:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 301:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 301:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 302:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 302:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 302:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 302:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 302:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 303:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 303:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 303:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 304:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 304:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 304:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 304:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 304:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 305:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 305:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 306:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 168:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 169:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 169:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 169:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 169:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 169:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 169:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 169:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 169:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 168:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 168:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 169:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 169:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 169:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 169:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 169:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 169:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 169:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 169:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 306:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 306:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 306:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 328:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 329:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 330:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 331:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 335:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 336:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 336:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 336:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 336:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 336:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 336:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 160:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 160:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 160:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 160:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 160:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 161:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 161:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 161:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 160:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 162:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 162:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 162:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 162:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 161:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 163:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 163:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 163:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 162:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 164:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 164:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 164:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 336:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 336:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 336:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 337:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 337:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 338:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 338:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 339:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 339:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 339:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 339:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 339:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 340:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 340:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 340:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 340:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 340:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 340:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 340:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 154:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 154:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 154:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 155:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 155:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 155:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 155:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 154:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 156:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 156:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 156:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 156:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 156:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 156:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 156:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 156:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 155:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 340:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 340:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 341:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 341:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 342:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 341:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 342:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 342:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 342:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 342:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 343:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 343:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 343:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 343:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 343:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 343:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 343:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 343:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 344:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 343:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 344:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 344:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 344:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 344:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 343:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 342:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 341:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 346:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 346:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 346:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 346:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 346:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 347:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 347:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 347:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 347:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 347:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 347:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 347:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 349:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 350:24] - node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 351:51] - node _T_588 = not(_T_587) @[axi4_to_ahb.scala 351:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 351:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 352:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 352:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 352:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 352:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 353:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 353:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 355:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 356:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 356:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 356:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 356:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 357:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 357:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 357:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 357:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 357:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 357:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 357:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 357:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 358:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 358:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 360:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 360:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 360:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 360:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 360:16] - node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 362:30] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 362:47] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 362:12] - node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 363:34] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 363:50] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 363:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 364:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 364:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 364:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 364:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 364:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 365:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 365:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 365:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 367:35] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 367:33] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 367:21] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 367:52] - io.axi_awready <= _T_627 @[axi4_to_ahb.scala 367:18] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 368:39] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 368:37] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 368:20] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 368:56] - io.axi_wready <= _T_631 @[axi4_to_ahb.scala 368:17] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 369:33] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 369:21] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 369:51] - io.axi_arready <= _T_634 @[axi4_to_ahb.scala 369:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 370:16] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 372:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 372:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 372:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 372:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 372:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 372:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 372:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 373:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 373:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 373:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 373:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 373:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 373:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 373:21] - node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 374:65] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 374:99] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 374:21] - node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 375:67] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 375:95] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55] - inst rvclkhdr_2 of rvclkhdr_861 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi_awaddr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59] - inst rvclkhdr_3 of rvclkhdr_862 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi_wdata @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 377:21] - node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 378:66] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 378:99] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 378:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 379:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 379:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 379:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 380:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 380:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 381:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 381:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 381:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78] - inst rvclkhdr_4 of rvclkhdr_863 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 382:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 383:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 383:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 383:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 384:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 384:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 385:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 385:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89] - inst rvclkhdr_5 of rvclkhdr_864 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 386:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 387:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 388:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 388:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 389:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 389:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 390:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 390:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 390:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 390:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 390:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 390:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 390:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 391:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 391:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 391:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 392:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 392:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 392:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 393:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 393:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 393:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 393:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 394:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 394:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 394:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 395:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 395:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 395:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 396:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 396:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 396:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 398:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 398:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 398:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 398:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 399:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 399:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 399:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 399:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 399:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 400:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19] - inst rvclkhdr_6 of rvclkhdr_865 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12] - inst rvclkhdr_7 of rvclkhdr_866 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12] - inst rvclkhdr_8 of rvclkhdr_867 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17] - inst rvclkhdr_9 of rvclkhdr_868 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17] - - extmodule gated_latch_869 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_869 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_869 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_870 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_870 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_870 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_871 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_871 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_871 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_872 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_872 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_872 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_873 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_873 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_873 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_874 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_874 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_874 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_875 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_875 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_875 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_876 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_876 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_876 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_877 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_877 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_877 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_878 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_878 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_878 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb_2 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 55:11] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 57:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 58:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 59:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 63:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 63:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 63:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 63:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 63:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 63:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 63:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<1> - slave_tag <= UInt<1>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<1> - wrbuf_tag <= UInt<1>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 83:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 84:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<1> - master_tag <= UInt<1>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<1> - buf_tag <= UInt<1>("h00") - wire buf_tag_in : UInt<1> - buf_tag_in <= UInt<1>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<1> - slvbuf_tag <= UInt<1>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 151:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 172:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 172:14] - node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 173:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 173:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 174:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 174:51] - node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 174:76] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 174:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 174:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 175:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 175:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 175:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 176:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 176:53] - node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 176:75] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 176:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 176:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 177:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 177:53] - node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 177:74] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 177:21] - master_size <= _T_22 @[axi4_to_ahb.scala 177:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 178:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 178:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 179:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 179:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 182:32] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 182:57] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 182:46] - io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 182:17] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 183:32] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 183:59] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 183:49] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 183:22] - io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 183:16] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 184:26] - io.axi_bid <= _T_32 @[axi4_to_ahb.scala 184:14] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 186:32] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 186:58] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 186:65] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 186:46] - io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 186:17] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 187:32] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 187:59] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 187:49] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 187:22] - io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 187:16] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 188:26] - io.axi_rid <= _T_41 @[axi4_to_ahb.scala 188:14] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 189:30] - io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 189:16] - node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 190:32] - slave_ready <= _T_43 @[axi4_to_ahb.scala 190:15] - node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 193:56] - node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 193:91] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20] - inst rvclkhdr of rvclkhdr_869 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59] - inst rvclkhdr_1 of rvclkhdr_870 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 196:17] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 199:21] - master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 200:16] - buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 201:16] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 202:18] - buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 204:18] - slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 205:21] - slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 206:21] - buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 207:18] - cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 208:18] - trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 209:18] - buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:23] - buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] - slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 213:19] - bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 214:20] - rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 219:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 220:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 220:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 220:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 221:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 221:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 221:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 222:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 222:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 223:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 224:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 224:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 224:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 227:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 168:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 169:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 169:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 169:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 169:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 169:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 169:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 169:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 169:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 169:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 227:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 227:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 227:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 228:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 229:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 229:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 229:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 230:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 230:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 234:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 234:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 234:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 234:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 234:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 234:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 235:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 235:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 235:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 235:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 235:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 235:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 236:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 236:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 236:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 237:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 238:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 238:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 238:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 238:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 238:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 238:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 238:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 238:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 238:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 238:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 238:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 238:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 238:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 239:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 240:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 240:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 241:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 241:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 241:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 241:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 241:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 242:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 242:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 242:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 242:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 246:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 246:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 246:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 246:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 246:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 246:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 246:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 246:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 247:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 247:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 247:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 247:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 247:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 248:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 248:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 248:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 248:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 248:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 248:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 248:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 248:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 248:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 249:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 249:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 250:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 251:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 252:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 253:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 253:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 253:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 254:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 254:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 254:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 255:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 255:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 255:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 255:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 255:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 256:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 256:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 256:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 256:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 256:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 257:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 257:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 257:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 257:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 257:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 258:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 262:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 263:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 263:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 263:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 263:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 264:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 265:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 266:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 266:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 267:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 267:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 267:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 271:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 272:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 272:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 273:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 274:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 275:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 276:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 280:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 281:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 281:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 281:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 281:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 281:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 282:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 283:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 284:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 285:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 285:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 285:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 168:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 168:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 169:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 169:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 169:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 169:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 169:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 169:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 169:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 169:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 169:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 285:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 285:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 286:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 286:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 286:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 286:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 168:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 168:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 169:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 169:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 169:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 169:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 169:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 169:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 169:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 169:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 169:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 286:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 286:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 286:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 286:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 286:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 286:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 287:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 287:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 287:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 287:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 291:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 291:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 291:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 292:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 292:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 292:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 292:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 293:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 293:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 293:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 293:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 293:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 293:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 293:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 293:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 293:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 294:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 295:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 296:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 296:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 296:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 297:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 297:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 297:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 297:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 297:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 298:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 299:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 299:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 299:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 300:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 300:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 300:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 168:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 168:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 169:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 169:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 169:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 169:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 169:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 169:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 169:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 169:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 169:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 300:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 300:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 300:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 300:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 299:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 299:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 299:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 301:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 301:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 301:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 301:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 302:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 302:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 302:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 302:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 302:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 303:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 303:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 303:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 304:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 304:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 304:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 304:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 304:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 305:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 305:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 306:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 168:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 169:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 169:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 169:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 169:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 169:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 169:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 169:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 169:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 169:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 168:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 168:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 169:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 169:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 169:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 169:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 169:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 169:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 169:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 169:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 169:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 169:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 169:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 169:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 169:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 169:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 169:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 169:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 169:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 306:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 306:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 306:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 328:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 329:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 330:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 331:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 335:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 336:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 336:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 336:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 336:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 336:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 336:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 160:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 160:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 160:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 160:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 160:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 161:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 161:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 161:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 160:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 162:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 162:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 162:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 162:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 161:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 163:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 163:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 163:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 162:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 164:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 164:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 164:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 336:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 336:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 336:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 337:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 337:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 338:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 338:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 339:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 339:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 339:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 339:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 339:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 340:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 340:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 340:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 340:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 340:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 340:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 340:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 154:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 154:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 154:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 155:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 155:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 155:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 155:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 154:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 156:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 156:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 156:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 156:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 156:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 156:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 156:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 156:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 155:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 340:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 340:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 341:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 341:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 342:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 341:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 342:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 342:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 342:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 342:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 343:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 343:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 343:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 343:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 343:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 343:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 343:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 343:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 344:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 343:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 344:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 344:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 344:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 344:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 343:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 342:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 341:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 346:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 346:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 346:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 346:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 346:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 347:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 347:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 347:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 347:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 347:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 347:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 347:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 349:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 350:24] - node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 351:51] - node _T_588 = not(_T_587) @[axi4_to_ahb.scala 351:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 351:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 352:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 352:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 352:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 352:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 353:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 353:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 355:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 356:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 356:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 356:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 356:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 357:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 357:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 357:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 357:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 357:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 357:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 357:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 357:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 358:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 358:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 360:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 360:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 360:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 360:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 360:16] - node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 362:30] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 362:47] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 362:12] - node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 363:34] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 363:50] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 363:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 364:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 364:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 364:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 364:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 364:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 365:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 365:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 365:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 367:35] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 367:33] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 367:21] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 367:52] - io.axi_awready <= _T_627 @[axi4_to_ahb.scala 367:18] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 368:39] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 368:37] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 368:20] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 368:56] - io.axi_wready <= _T_631 @[axi4_to_ahb.scala 368:17] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 369:33] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 369:21] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 369:51] - io.axi_arready <= _T_634 @[axi4_to_ahb.scala 369:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 370:16] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 372:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 372:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 372:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 372:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 372:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 372:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 372:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 373:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 373:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 373:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 373:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 373:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 373:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 373:21] - node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 374:65] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 374:99] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 374:21] - node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 375:67] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 375:95] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55] - inst rvclkhdr_2 of rvclkhdr_871 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi_awaddr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59] - inst rvclkhdr_3 of rvclkhdr_872 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi_wdata @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 377:21] - node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 378:66] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 378:99] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 378:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 379:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 379:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 379:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 380:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 380:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 381:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 381:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 381:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78] - inst rvclkhdr_4 of rvclkhdr_873 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 382:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 383:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 383:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 383:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 384:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 384:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 385:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 385:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89] - inst rvclkhdr_5 of rvclkhdr_874 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 386:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 387:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 388:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 388:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 389:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 389:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 390:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 390:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 390:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 390:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 390:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 390:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 390:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 391:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 391:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 391:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 392:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 392:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 392:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 393:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 393:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 393:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 393:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 394:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 394:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 394:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 395:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 395:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 395:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 396:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 396:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 396:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 398:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 398:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 398:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 398:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 399:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 399:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 399:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 399:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 399:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 400:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19] - inst rvclkhdr_6 of rvclkhdr_875 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12] - inst rvclkhdr_7 of rvclkhdr_876 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12] - inst rvclkhdr_8 of rvclkhdr_877 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17] - inst rvclkhdr_9 of rvclkhdr_878 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17] - - extmodule gated_latch_879 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_879 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_879 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_880 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_880 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_880 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_881 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_881 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_881 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_882 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_882 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_882 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_883 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_883 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_883 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_884 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_884 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_884 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module ahb_to_axi4 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awready : UInt<1>, flip axi_wready : UInt<1>, flip axi_bvalid : UInt<1>, flip axi_bresp : UInt<2>, flip axi_bid : UInt<0>, flip axi_arready : UInt<1>, flip axi_rvalid : UInt<1>, flip axi_rid : UInt<0>, flip axi_rdata : UInt<64>, flip axi_rresp : UInt<2>, axi_awvalid : UInt<1>, axi_awid : UInt<0>, axi_awaddr : UInt<32>, axi_awsize : UInt<3>, axi_awprot : UInt<3>, axi_awlen : UInt<8>, axi_awburst : UInt<2>, axi_wvalid : UInt<1>, axi_wdata : UInt<64>, axi_wstrb : UInt<8>, axi_wlast : UInt<1>, axi_bready : UInt<1>, axi_arvalid : UInt<1>, axi_arid : UInt<0>, axi_araddr : UInt<32>, axi_arsize : UInt<3>, axi_arprot : UInt<3>, axi_arlen : UInt<8>, axi_arburst : UInt<2>, axi_rready : UInt<1>, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}} - - wire master_wstrb : UInt<8> - master_wstrb <= UInt<8>("h00") - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire buf_read_error_in : UInt<1> - buf_read_error_in <= UInt<1>("h00") - wire buf_read_error : UInt<1> - buf_read_error <= UInt<1>("h00") - wire buf_rdata : UInt<64> - buf_rdata <= UInt<64>("h00") - wire ahb_hready : UInt<1> - ahb_hready <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_htrans_in : UInt<2> - ahb_htrans_in <= UInt<2>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hsize_q : UInt<3> - ahb_hsize_q <= UInt<3>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_haddr_q : UInt<32> - ahb_haddr_q <= UInt<32>("h00") - wire ahb_hwdata_q : UInt<64> - ahb_hwdata_q <= UInt<64>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire buf_rdata_en : UInt<1> - buf_rdata_en <= UInt<1>("h00") - wire ahb_bus_addr_clk_en : UInt<1> - ahb_bus_addr_clk_en <= UInt<1>("h00") - wire buf_rdata_clk_en : UInt<1> - buf_rdata_clk_en <= UInt<1>("h00") - wire ahb_clk : Clock @[ahb_to_axi4.scala 89:33] - wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 90:33] - wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 91:33] - wire cmdbuf_wr_en : UInt<1> - cmdbuf_wr_en <= UInt<1>("h00") - wire cmdbuf_rst : UInt<1> - cmdbuf_rst <= UInt<1>("h00") - wire cmdbuf_full : UInt<1> - cmdbuf_full <= UInt<1>("h00") - wire cmdbuf_vld : UInt<1> - cmdbuf_vld <= UInt<1>("h00") - wire cmdbuf_write : UInt<1> - cmdbuf_write <= UInt<1>("h00") - wire cmdbuf_size : UInt<2> - cmdbuf_size <= UInt<2>("h00") - wire cmdbuf_wstrb : UInt<8> - cmdbuf_wstrb <= UInt<8>("h00") - wire cmdbuf_addr : UInt<32> - cmdbuf_addr <= UInt<32>("h00") - wire cmdbuf_wdata : UInt<64> - cmdbuf_wdata <= UInt<64>("h00") - wire bus_clk : Clock @[ahb_to_axi4.scala 103:33] - node _T = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_dccm_region_nc = eq(_T, UInt<4>("h0f")) @[lib.scala 84:47] - node _T_1 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] - node ahb_addr_in_dccm = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 87:29] - node _T_2 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_iccm_region_nc = eq(_T_2, UInt<4>("h0e")) @[lib.scala 84:47] - node _T_3 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] - node ahb_addr_in_iccm = eq(_T_3, UInt<16>("h0ee00")) @[lib.scala 87:29] - node _T_4 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_pic_region_nc = eq(_T_4, UInt<4>("h0f")) @[lib.scala 84:47] - node _T_5 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14] - node ahb_addr_in_pic = eq(_T_5, UInt<17>("h01e018")) @[lib.scala 87:29] - wire buf_state : UInt<2> - buf_state <= UInt<2>("h00") - wire buf_nxtstate : UInt<2> - buf_nxtstate <= UInt<2>("h00") - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 113:31] - buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 114:31] - buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 115:31] - buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 116:31] - cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 117:31] - node _T_6 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_6 : @[Conditional.scala 40:58] - node _T_7 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 121:26] - buf_nxtstate <= _T_7 @[ahb_to_axi4.scala 121:20] - node _T_8 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 122:57] - node _T_9 = and(ahb_hready, _T_8) @[ahb_to_axi4.scala 122:34] - node _T_10 = and(_T_9, io.ahb.hsel) @[ahb_to_axi4.scala 122:61] - buf_state_en <= _T_10 @[ahb_to_axi4.scala 122:20] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_11 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_11 : @[Conditional.scala 39:67] - node _T_12 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 125:72] - node _T_13 = eq(_T_12, UInt<1>("h00")) @[ahb_to_axi4.scala 125:79] - node _T_14 = or(io.ahb.sig.in.hresp, _T_13) @[ahb_to_axi4.scala 125:48] - node _T_15 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 125:93] - node _T_16 = or(_T_14, _T_15) @[ahb_to_axi4.scala 125:91] - node _T_17 = bits(_T_16, 0, 0) @[ahb_to_axi4.scala 125:107] - node _T_18 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 125:124] - node _T_19 = mux(_T_17, UInt<2>("h00"), _T_18) @[ahb_to_axi4.scala 125:26] - buf_nxtstate <= _T_19 @[ahb_to_axi4.scala 125:20] - node _T_20 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 126:24] - node _T_21 = or(_T_20, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 126:37] - buf_state_en <= _T_21 @[ahb_to_axi4.scala 126:20] - node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 127:23] - node _T_23 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 127:85] - node _T_24 = eq(_T_23, UInt<2>("h01")) @[ahb_to_axi4.scala 127:92] - node _T_25 = and(_T_24, io.ahb.hsel) @[ahb_to_axi4.scala 127:110] - node _T_26 = or(io.ahb.sig.in.hresp, _T_25) @[ahb_to_axi4.scala 127:60] - node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 127:38] - node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 127:36] - cmdbuf_wr_en <= _T_28 @[ahb_to_axi4.scala 127:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_29 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_29 : @[Conditional.scala 39:67] - node _T_30 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 130:26] - buf_nxtstate <= _T_30 @[ahb_to_axi4.scala 130:20] - node _T_31 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 131:24] - node _T_32 = or(_T_31, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 131:37] - buf_state_en <= _T_32 @[ahb_to_axi4.scala 131:20] - node _T_33 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 132:23] - node _T_34 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 132:46] - node _T_35 = and(_T_33, _T_34) @[ahb_to_axi4.scala 132:44] - cmdbuf_wr_en <= _T_35 @[ahb_to_axi4.scala 132:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_36 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_36 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 135:20] - node _T_37 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 136:39] - node _T_38 = and(io.axi_rvalid, _T_37) @[ahb_to_axi4.scala 136:37] - buf_state_en <= _T_38 @[ahb_to_axi4.scala 136:20] - buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 137:20] - node _T_39 = bits(io.axi_rresp, 1, 0) @[ahb_to_axi4.scala 138:55] - node _T_40 = orr(_T_39) @[ahb_to_axi4.scala 138:62] - node _T_41 = and(buf_state_en, _T_40) @[ahb_to_axi4.scala 138:41] - buf_read_error_in <= _T_41 @[ahb_to_axi4.scala 138:25] - skip @[Conditional.scala 39:67] - node _T_42 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 141:99] - reg _T_43 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_42 : @[Reg.scala 28:19] - _T_43 <= buf_nxtstate @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_state <= _T_43 @[ahb_to_axi4.scala 141:31] - node _T_44 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 143:54] - node _T_45 = eq(_T_44, UInt<1>("h00")) @[ahb_to_axi4.scala 143:60] - node _T_46 = bits(_T_45, 0, 0) @[Bitwise.scala 72:15] - node _T_47 = mux(_T_46, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_48 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 143:92] - node _T_49 = dshl(UInt<1>("h01"), _T_48) @[ahb_to_axi4.scala 143:78] - node _T_50 = and(_T_47, _T_49) @[ahb_to_axi4.scala 143:70] - node _T_51 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 144:24] - node _T_52 = eq(_T_51, UInt<1>("h01")) @[ahb_to_axi4.scala 144:30] - node _T_53 = bits(_T_52, 0, 0) @[Bitwise.scala 72:15] - node _T_54 = mux(_T_53, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_55 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 144:62] - node _T_56 = dshl(UInt<2>("h03"), _T_55) @[ahb_to_axi4.scala 144:48] - node _T_57 = and(_T_54, _T_56) @[ahb_to_axi4.scala 144:40] - node _T_58 = or(_T_50, _T_57) @[ahb_to_axi4.scala 143:109] - node _T_59 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 145:24] - node _T_60 = eq(_T_59, UInt<2>("h02")) @[ahb_to_axi4.scala 145:30] - node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15] - node _T_62 = mux(_T_61, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_63 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 145:62] - node _T_64 = dshl(UInt<4>("h0f"), _T_63) @[ahb_to_axi4.scala 145:48] - node _T_65 = and(_T_62, _T_64) @[ahb_to_axi4.scala 145:40] - node _T_66 = or(_T_58, _T_65) @[ahb_to_axi4.scala 144:79] - node _T_67 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 146:24] - node _T_68 = eq(_T_67, UInt<2>("h03")) @[ahb_to_axi4.scala 146:30] - node _T_69 = bits(_T_68, 0, 0) @[Bitwise.scala 72:15] - node _T_70 = mux(_T_69, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_71 = and(_T_70, UInt<8>("h0ff")) @[ahb_to_axi4.scala 146:40] - node _T_72 = or(_T_66, _T_71) @[ahb_to_axi4.scala 145:79] - master_wstrb <= _T_72 @[ahb_to_axi4.scala 143:31] - node _T_73 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 149:80] - node _T_74 = and(ahb_hresp_q, _T_73) @[ahb_to_axi4.scala 149:78] - node _T_75 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 149:98] - node _T_76 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 149:124] - node _T_77 = or(_T_75, _T_76) @[ahb_to_axi4.scala 149:111] - node _T_78 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 149:149] - node _T_79 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 149:168] - node _T_80 = or(_T_78, _T_79) @[ahb_to_axi4.scala 149:156] - node _T_81 = eq(_T_80, UInt<1>("h00")) @[ahb_to_axi4.scala 149:137] - node _T_82 = and(_T_77, _T_81) @[ahb_to_axi4.scala 149:135] - node _T_83 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 149:181] - node _T_84 = and(_T_82, _T_83) @[ahb_to_axi4.scala 149:179] - node _T_85 = mux(io.ahb.sig.in.hresp, _T_74, _T_84) @[ahb_to_axi4.scala 149:44] - io.ahb.sig.in.hready <= _T_85 @[ahb_to_axi4.scala 149:38] - node _T_86 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 150:55] - ahb_hready <= _T_86 @[ahb_to_axi4.scala 150:31] - node _T_87 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15] - node _T_88 = mux(_T_87, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_89 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 151:77] - node _T_90 = and(_T_88, _T_89) @[ahb_to_axi4.scala 151:54] - ahb_htrans_in <= _T_90 @[ahb_to_axi4.scala 151:31] - node _T_91 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 152:50] - io.ahb.sig.in.hrdata <= _T_91 @[ahb_to_axi4.scala 152:38] - node _T_92 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 153:55] - node _T_93 = neq(_T_92, UInt<1>("h00")) @[ahb_to_axi4.scala 153:61] - node _T_94 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 153:83] - node _T_95 = and(_T_93, _T_94) @[ahb_to_axi4.scala 153:70] - node _T_96 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 154:26] - node _T_97 = eq(_T_96, UInt<1>("h00")) @[ahb_to_axi4.scala 154:7] - node _T_98 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 155:46] - node _T_99 = or(ahb_addr_in_iccm, _T_98) @[ahb_to_axi4.scala 155:26] - node _T_100 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 155:80] - node _T_101 = eq(_T_100, UInt<2>("h02")) @[ahb_to_axi4.scala 155:86] - node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 155:109] - node _T_103 = eq(_T_102, UInt<2>("h03")) @[ahb_to_axi4.scala 155:115] - node _T_104 = or(_T_101, _T_103) @[ahb_to_axi4.scala 155:95] - node _T_105 = eq(_T_104, UInt<1>("h00")) @[ahb_to_axi4.scala 155:66] - node _T_106 = and(_T_99, _T_105) @[ahb_to_axi4.scala 155:64] - node _T_107 = or(_T_97, _T_106) @[ahb_to_axi4.scala 154:47] - node _T_108 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 156:20] - node _T_109 = eq(_T_108, UInt<1>("h01")) @[ahb_to_axi4.scala 156:26] - node _T_110 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 156:48] - node _T_111 = and(_T_109, _T_110) @[ahb_to_axi4.scala 156:35] - node _T_112 = or(_T_107, _T_111) @[ahb_to_axi4.scala 155:126] - node _T_113 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 157:20] - node _T_114 = eq(_T_113, UInt<2>("h02")) @[ahb_to_axi4.scala 157:26] - node _T_115 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 157:49] - node _T_116 = orr(_T_115) @[ahb_to_axi4.scala 157:56] - node _T_117 = and(_T_114, _T_116) @[ahb_to_axi4.scala 157:35] - node _T_118 = or(_T_112, _T_117) @[ahb_to_axi4.scala 156:55] - node _T_119 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 158:20] - node _T_120 = eq(_T_119, UInt<2>("h03")) @[ahb_to_axi4.scala 158:26] - node _T_121 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 158:49] - node _T_122 = orr(_T_121) @[ahb_to_axi4.scala 158:56] - node _T_123 = and(_T_120, _T_122) @[ahb_to_axi4.scala 158:35] - node _T_124 = or(_T_118, _T_123) @[ahb_to_axi4.scala 157:61] - node _T_125 = and(_T_95, _T_124) @[ahb_to_axi4.scala 153:94] - node _T_126 = or(_T_125, buf_read_error) @[ahb_to_axi4.scala 158:63] - node _T_127 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 160:20] - node _T_128 = and(ahb_hresp_q, _T_127) @[ahb_to_axi4.scala 160:18] - node _T_129 = or(_T_126, _T_128) @[ahb_to_axi4.scala 159:20] - io.ahb.sig.in.hresp <= _T_129 @[ahb_to_axi4.scala 153:38] - reg _T_130 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 163:66] - _T_130 <= io.axi_rdata @[ahb_to_axi4.scala 163:66] - buf_rdata <= _T_130 @[ahb_to_axi4.scala 163:31] - reg _T_131 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 164:60] - _T_131 <= buf_read_error_in @[ahb_to_axi4.scala 164:60] - buf_read_error <= _T_131 @[ahb_to_axi4.scala 164:31] - reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 167:60] - _T_132 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 167:60] - ahb_hresp_q <= _T_132 @[ahb_to_axi4.scala 167:31] - reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 168:60] - _T_133 <= ahb_hready @[ahb_to_axi4.scala 168:60] - ahb_hready_q <= _T_133 @[ahb_to_axi4.scala 168:31] - reg _T_134 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 169:60] - _T_134 <= ahb_htrans_in @[ahb_to_axi4.scala 169:60] - ahb_htrans_q <= _T_134 @[ahb_to_axi4.scala 169:31] - reg _T_135 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 170:65] - _T_135 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 170:65] - ahb_hsize_q <= _T_135 @[ahb_to_axi4.scala 170:31] - reg _T_136 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 171:65] - _T_136 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 171:65] - ahb_hwrite_q <= _T_136 @[ahb_to_axi4.scala 171:31] - reg _T_137 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 172:65] - _T_137 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 172:65] - ahb_haddr_q <= _T_137 @[ahb_to_axi4.scala 172:31] - node _T_138 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 175:85] - node _T_139 = and(ahb_hready, _T_138) @[ahb_to_axi4.scala 175:62] - node _T_140 = and(io.bus_clk_en, _T_139) @[ahb_to_axi4.scala 175:48] - ahb_bus_addr_clk_en <= _T_140 @[ahb_to_axi4.scala 175:31] - node _T_141 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 176:48] - buf_rdata_clk_en <= _T_141 @[ahb_to_axi4.scala 176:31] - inst rvclkhdr of rvclkhdr_879 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 178:31] - inst rvclkhdr_1 of rvclkhdr_880 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 179:31] - inst rvclkhdr_2 of rvclkhdr_881 @[lib.scala 343:22] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 345:16] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 180:31] - node _T_142 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 182:52] - node _T_143 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 182:88] - node _T_144 = or(_T_142, _T_143) @[ahb_to_axi4.scala 182:70] - node _T_145 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 182:109] - node _T_146 = and(_T_144, _T_145) @[ahb_to_axi4.scala 182:107] - node _T_147 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 182:149] - node _T_148 = and(io.ahb.sig.in.hresp, _T_147) @[ahb_to_axi4.scala 182:147] - node _T_149 = or(_T_146, _T_148) @[ahb_to_axi4.scala 182:124] - cmdbuf_rst <= _T_149 @[ahb_to_axi4.scala 182:31] - node _T_150 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 183:66] - node _T_151 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 183:102] - node _T_152 = or(_T_150, _T_151) @[ahb_to_axi4.scala 183:84] - node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 183:48] - node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 183:46] - cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 183:31] - node _T_155 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 185:86] - node _T_156 = mux(_T_155, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 185:66] - node _T_157 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 185:110] - node _T_158 = and(_T_156, _T_157) @[ahb_to_axi4.scala 185:108] - reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 185:61] - _T_159 <= _T_158 @[ahb_to_axi4.scala 185:61] - cmdbuf_vld <= _T_159 @[ahb_to_axi4.scala 185:31] - node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 189:53] - reg _T_161 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_160 : @[Reg.scala 28:19] - _T_161 <= ahb_hwrite_q @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_write <= _T_161 @[ahb_to_axi4.scala 188:31] - node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 192:52] - reg _T_163 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_162 : @[Reg.scala 28:19] - _T_163 <= ahb_hsize_q @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_size <= _T_163 @[ahb_to_axi4.scala 191:31] - node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 195:53] - reg _T_165 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_164 : @[Reg.scala 28:19] - _T_165 <= master_wstrb @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_wstrb <= _T_165 @[ahb_to_axi4.scala 194:31] - node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 198:57] - inst rvclkhdr_3 of rvclkhdr_882 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_166 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_167 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_167 <= ahb_haddr_q @[lib.scala 374:16] - cmdbuf_addr <= _T_167 @[ahb_to_axi4.scala 198:15] - node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 199:68] - inst rvclkhdr_4 of rvclkhdr_883 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_168 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_169 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_169 <= io.ahb.sig.out.hwdata @[lib.scala 374:16] - cmdbuf_wdata <= _T_169 @[ahb_to_axi4.scala 199:16] - node _T_170 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 202:41] - io.axi_awvalid <= _T_170 @[ahb_to_axi4.scala 202:27] - io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 203:27] - io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 204:27] - node _T_171 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 205:53] - node _T_172 = cat(UInt<1>("h00"), _T_171) @[Cat.scala 29:58] - io.axi_awsize <= _T_172 @[ahb_to_axi4.scala 205:27] - node _T_173 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi_awprot <= _T_173 @[ahb_to_axi4.scala 206:27] - node _T_174 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi_awlen <= _T_174 @[ahb_to_axi4.scala 207:27] - io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 208:27] - node _T_175 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 210:41] - io.axi_wvalid <= _T_175 @[ahb_to_axi4.scala 210:27] - io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 211:27] - io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 212:27] - io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 213:27] - io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 215:27] - node _T_176 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 217:43] - node _T_177 = and(cmdbuf_vld, _T_176) @[ahb_to_axi4.scala 217:41] - io.axi_arvalid <= _T_177 @[ahb_to_axi4.scala 217:27] - io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 218:27] - io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 219:27] - node _T_178 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 220:53] - node _T_179 = cat(UInt<1>("h00"), _T_178) @[Cat.scala 29:58] - io.axi_arsize <= _T_179 @[ahb_to_axi4.scala 220:27] - node _T_180 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi_arprot <= _T_180 @[ahb_to_axi4.scala 221:27] - node _T_181 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi_arlen <= _T_181 @[ahb_to_axi4.scala 222:27] - io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 223:27] - io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 225:27] - inst rvclkhdr_5 of rvclkhdr_884 @[lib.scala 343:22] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 228:27] - module quasar : input clock : Clock input reset : AsyncReset output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, lsu_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, dma : {flip ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} - inst ifu of ifu @[quasar.scala 125:19] + inst ifu of ifu @[quasar.scala 72:19] ifu.clock <= clock ifu.reset <= reset - inst dec of dec @[quasar.scala 126:19] + inst dec of dec @[quasar.scala 73:19] dec.clock <= clock dec.reset <= reset - inst dbg of dbg @[quasar.scala 127:19] + inst dbg of dbg @[quasar.scala 74:19] dbg.clock <= clock dbg.reset <= reset - inst exu of exu @[quasar.scala 128:19] + inst exu of exu @[quasar.scala 75:19] exu.clock <= clock exu.reset <= reset - inst lsu of lsu @[quasar.scala 129:19] + inst lsu of lsu @[quasar.scala 76:19] lsu.clock <= clock lsu.reset <= reset - inst pic_ctrl_inst of pic_ctrl @[quasar.scala 130:29] + inst pic_ctrl_inst of pic_ctrl @[quasar.scala 77:29] pic_ctrl_inst.clock <= clock pic_ctrl_inst.reset <= reset - inst dma_ctrl of dma_ctrl @[quasar.scala 131:24] + inst dma_ctrl of dma_ctrl @[quasar.scala 78:24] dma_ctrl.clock <= clock dma_ctrl.reset <= reset - node _T = asUInt(reset) @[quasar.scala 133:33] - node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 133:67] - node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 133:70] - node _T_3 = and(_T, _T_2) @[quasar.scala 133:36] - node _T_4 = asAsyncReset(_T_3) @[quasar.scala 133:99] - io.core_rst_l <= _T_4 @[quasar.scala 133:17] - node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 134:23] - node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 134:50] - node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 134:98] + node _T = asUInt(reset) @[quasar.scala 80:33] + node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 80:67] + node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 80:70] + node _T_3 = and(_T, _T_2) @[quasar.scala 80:36] + node _T_4 = asAsyncReset(_T_3) @[quasar.scala 80:99] + io.core_rst_l <= _T_4 @[quasar.scala 80:17] + node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 81:23] + node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 81:50] + node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 81:98] inst rvclkhdr of rvclkhdr_847 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= UInt<1>("h01") @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_7 = bits(active_state, 0, 0) @[quasar.scala 136:49] + node _T_7 = bits(active_state, 0, 0) @[quasar.scala 83:49] inst rvclkhdr_1 of rvclkhdr_848 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= _T_7 @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 137:56] - node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 138:56] - node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 139:28] - ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 142:18] - dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 142:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 142:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 142:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 142:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 142:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 142:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 142:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 142:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 142:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 142:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 142:18] - dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 142:18] - ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 142:18] - ifu.reset <= io.core_rst_l @[quasar.scala 144:13] - ifu.io.scan_mode <= io.scan_mode @[quasar.scala 145:20] - ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 146:19] - ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 147:21] - ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 149:26] - ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 150:31] - ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 152:25] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 153:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 153:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 153:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 153:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 153:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 153:18] - ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 153:18] - io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 154:13] - io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 154:13] - io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 154:13] - io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 154:13] - io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 154:13] - io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 154:13] - ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 154:13] - ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 154:13] - ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 154:13] - ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 154:13] - ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 154:13] - ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 154:13] - ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 154:13] - io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 154:13] - io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 154:13] - io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 154:13] - io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 154:13] - io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 154:13] - io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 154:13] - io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 154:13] - io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 154:13] - ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 155:15] - ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 155:15] - io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 155:15] - io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 155:15] - io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 155:15] - io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 155:15] - io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 155:15] - io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 155:15] - io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 155:15] - ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 156:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 157:42] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 158:43] - ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 159:33] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 160:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 160:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 160:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 160:51] - dec.reset <= io.core_rst_l @[quasar.scala 163:13] - dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 164:19] - dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 165:21] - dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 166:32] - dec.io.rst_vec <= io.rst_vec @[quasar.scala 167:18] - dec.io.nmi_int <= io.nmi_int @[quasar.scala 168:18] - dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 169:18] - dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 170:25] - dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 171:24] - dec.io.core_id <= io.core_id @[quasar.scala 172:18] - dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 173:29] - dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 174:28] - dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 175:28] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 176:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 176:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 176:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 176:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 176:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 176:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 176:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 176:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 176:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 176:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 176:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 176:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 176:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 176:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 176:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 176:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 176:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 176:18] - dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 177:18] - dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 177:18] - dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 178:31] - dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 179:18] - dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 179:18] - dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 179:18] - dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 179:18] - dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 179:18] - dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 179:18] - dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 179:18] - dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 179:18] - dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 181:23] - dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 182:24] - dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 183:30] - dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 184:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 184:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 184:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 184:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 184:18] - dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 185:23] - dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 186:26] - dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 186:26] - dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 186:26] - dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 186:26] - dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 186:26] - dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 186:26] - dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 187:36] - dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 188:25] - dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 189:23] - dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 190:23] - dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 191:28] - dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 192:29] - dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 193:30] - dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 194:28] - dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 195:26] - dec.io.soft_int <= io.soft_int @[quasar.scala 197:19] - dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 198:23] - dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 199:25] - dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 200:26] - dec.io.timer_int <= io.timer_int @[quasar.scala 201:20] - dec.io.scan_mode <= io.scan_mode @[quasar.scala 202:20] - exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 205:18] - exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 205:18] - exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 205:18] - exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 205:18] - dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 205:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 205:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 205:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 205:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 205:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 205:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 205:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 205:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 205:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 205:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 205:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 205:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 205:18] - exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 205:18] - dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 205:18] - dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 205:18] - exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 205:18] - exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 205:18] - exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 205:18] - exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 205:18] - exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 205:18] - dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 205:18] - exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 205:18] - exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 205:18] - exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 205:18] - exu.reset <= io.core_rst_l @[quasar.scala 206:13] - exu.io.scan_mode <= io.scan_mode @[quasar.scala 207:20] - exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 208:25] - lsu.reset <= io.core_rst_l @[quasar.scala 211:13] - lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 212:23] - lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 213:32] - lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 214:35] - lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 215:29] - lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 216:35] - lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 217:18] - lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 217:18] - lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 218:27] - lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 219:16] - lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 219:16] - lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 219:16] - lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 219:16] - lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 219:16] - lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 219:16] - lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 219:16] - lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 219:16] - lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 219:16] - lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 219:16] - lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 219:16] - lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 219:16] - lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 219:16] - lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 220:30] - lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 221:26] - lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 222:26] - lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 222:26] - lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 224:25] - lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 225:18] - dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 225:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 225:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 225:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 225:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 225:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 225:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 225:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 225:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 225:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 225:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 225:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 225:18] - lsu.io.scan_mode <= io.scan_mode @[quasar.scala 226:20] - lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 227:19] - dbg.reset <= io.core_rst_l @[quasar.scala 230:13] - node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 231:32] - dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 231:26] - node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 232:60] - dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 232:28] - node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 233:60] - dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 233:28] - dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 234:29] - dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 235:29] - dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 236:34] - dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 237:29] - dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 238:21] - dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 239:23] - dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 240:24] - dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 241:24] - dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 242:17] - dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 242:17] - dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 242:17] - dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 242:17] - dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 242:17] - io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 242:17] - io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 242:17] - io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 242:17] - io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 242:17] - io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 242:17] - io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 242:17] - io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 242:17] - io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 242:17] - io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 242:17] - io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 242:17] - io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 242:17] - io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 242:17] - dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 242:17] - dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 242:17] - dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 242:17] - dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 242:17] - io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 242:17] - io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 242:17] - io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 242:17] - io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 242:17] - io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 242:17] - dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 242:17] - io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 242:17] - io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 242:17] - io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 242:17] - io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 242:17] - io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 242:17] - io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 242:17] - io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 242:17] - io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 242:17] - io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 242:17] - io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 242:17] - io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 242:17] - dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 242:17] - dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 243:25] - node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 244:42] - dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 244:20] - dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 245:23] - dbg.io.scan_mode <= io.scan_mode @[quasar.scala 246:20] - dma_ctrl.reset <= io.core_rst_l @[quasar.scala 250:18] - dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 251:24] - dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 252:30] - dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 253:28] - dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 254:25] - dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 255:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 255:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 255:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 255:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 255:23] - dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 256:26] - dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 256:26] - dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 257:28] - dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 258:31] - dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 259:29] - dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 260:30] - dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 261:26] - dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 262:34] - pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 265:30] - pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 266:23] - pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 267:29] - pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 268:31] - pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 269:33] - pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 270:34] - lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 271:28] - pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 271:28] - pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 271:28] - pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 271:28] - pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 271:28] - pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 271:28] - pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 271:28] - dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 272:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 272:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 272:28] - dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 272:28] - dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 272:28] - dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 272:28] - io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 274:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 274:19] - io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 274:19] - io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 274:19] - io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 274:19] - io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 274:19] - io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 274:19] - io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 277:24] - io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 278:23] - io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 279:31] - io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 280:21] - io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 281:24] - io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 282:20] - io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 283:26] - io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 284:25] - io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 285:24] - io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 286:25] - io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 287:23] - io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 288:23] - io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 289:23] - io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 290:23] - lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 292:11] - lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 292:11] - io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 292:11] - io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 292:11] - io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 292:11] - io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 292:11] - io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 292:11] - io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 292:11] - io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 292:11] - io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 292:11] - lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 295:14] - lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 295:14] - lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 295:14] - lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 295:14] - lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 295:14] - io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 295:14] - io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 295:14] - io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 295:14] - io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 295:14] - io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 295:14] - io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 295:14] - io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 295:14] - io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 295:14] - io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 295:14] - io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 295:14] - io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 295:14] - io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 295:14] - lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 295:14] - lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 295:14] - lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 295:14] - lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 295:14] - io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 295:14] - io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 295:14] - io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 295:14] - io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 295:14] - io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 295:14] - lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 295:14] - io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 295:14] - io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 295:14] - io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 295:14] - io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 295:14] - io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 295:14] - io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 295:14] - io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 295:14] - io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 295:14] - io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 295:14] - io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 295:14] - io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 295:14] - lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 295:14] - ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 298:14] - ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 298:14] - ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 298:14] - ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 298:14] - ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 298:14] - io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 298:14] - io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 298:14] - io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 298:14] - io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 298:14] - io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 298:14] - io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 298:14] - io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 298:14] - io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 298:14] - io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 298:14] - io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 298:14] - io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 298:14] - io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 298:14] - ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 298:14] - ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 298:14] - ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 298:14] - ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 298:14] - io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 298:14] - io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 298:14] - io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 298:14] - io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 298:14] - io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 298:14] - ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 298:14] - io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 298:14] - io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 298:14] - io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 298:14] - io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 298:14] - io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 298:14] - io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 298:14] - io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 298:14] - io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 298:14] - io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 298:14] - io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 298:14] - io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 298:14] - ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 298:14] - io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 299:14] - io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 299:14] - io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 299:14] - io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 299:14] - io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 299:14] - io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 299:14] - io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 299:14] - io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 299:14] - io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 299:14] - io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 299:14] - dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 299:14] - io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 299:14] - when UInt<1>("h00") : @[quasar.scala 305:26] - inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 306:33] - axi4_to_ahb.clock <= clock - axi4_to_ahb.reset <= reset - axi4_to_ahb.io.axi_awvalid <= io.lsu_axi.aw.valid @[quasar.scala 307:36] - axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 308:34] - axi4_to_ahb.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 309:35] - axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 310:37] - axi4_to_ahb.io.axi_awid <= io.lsu_axi.aw.bits.id @[quasar.scala 311:33] - axi4_to_ahb.io.axi_awaddr <= io.lsu_axi.aw.bits.addr @[quasar.scala 312:35] - axi4_to_ahb.io.axi_awsize <= io.lsu_axi.aw.bits.size @[quasar.scala 313:35] - axi4_to_ahb.io.axi_awprot <= io.lsu_axi.aw.bits.prot @[quasar.scala 314:35] - axi4_to_ahb.io.axi_wvalid <= io.lsu_axi.w.valid @[quasar.scala 316:35] - axi4_to_ahb.io.axi_wdata <= io.lsu_axi.w.bits.data @[quasar.scala 317:34] - axi4_to_ahb.io.axi_wstrb <= io.lsu_axi.w.bits.strb @[quasar.scala 318:34] - axi4_to_ahb.io.axi_wlast <= io.lsu_axi.w.bits.last @[quasar.scala 319:34] - axi4_to_ahb.io.axi_bready <= io.lsu_axi.b.ready @[quasar.scala 320:35] - axi4_to_ahb.io.axi_arvalid <= io.lsu_axi.ar.valid @[quasar.scala 322:36] - axi4_to_ahb.io.axi_arid <= io.lsu_axi.ar.bits.id @[quasar.scala 323:33] - axi4_to_ahb.io.axi_araddr <= io.lsu_axi.ar.bits.addr @[quasar.scala 324:35] - axi4_to_ahb.io.axi_arsize <= io.lsu_axi.ar.bits.size @[quasar.scala 325:35] - axi4_to_ahb.io.axi_arprot <= io.lsu_axi.ar.bits.prot @[quasar.scala 326:35] - axi4_to_ahb.io.axi_rready <= io.lsu_axi.r.ready @[quasar.scala 328:35] - inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 333:33] - axi4_to_ahb_1.clock <= clock - axi4_to_ahb_1.reset <= reset - axi4_to_ahb_1.io.axi_awvalid <= io.ifu_axi.aw.valid @[quasar.scala 334:36] - axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 335:34] - axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 336:35] - axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 337:37] - axi4_to_ahb_1.io.axi_awid <= io.ifu_axi.aw.bits.id @[quasar.scala 338:33] - axi4_to_ahb_1.io.axi_awaddr <= io.ifu_axi.aw.bits.addr @[quasar.scala 339:35] - axi4_to_ahb_1.io.axi_awsize <= io.ifu_axi.aw.bits.size @[quasar.scala 340:35] - axi4_to_ahb_1.io.axi_awprot <= io.ifu_axi.aw.bits.prot @[quasar.scala 341:35] - axi4_to_ahb_1.io.axi_wvalid <= io.ifu_axi.w.valid @[quasar.scala 343:35] - axi4_to_ahb_1.io.axi_wdata <= io.ifu_axi.w.bits.data @[quasar.scala 344:34] - axi4_to_ahb_1.io.axi_wstrb <= io.ifu_axi.w.bits.strb @[quasar.scala 345:34] - axi4_to_ahb_1.io.axi_wlast <= io.ifu_axi.w.bits.last @[quasar.scala 346:34] - axi4_to_ahb_1.io.axi_bready <= io.ifu_axi.b.ready @[quasar.scala 347:35] - axi4_to_ahb_1.io.axi_arvalid <= io.ifu_axi.ar.valid @[quasar.scala 349:36] - axi4_to_ahb_1.io.axi_arid <= io.ifu_axi.ar.bits.id @[quasar.scala 350:33] - axi4_to_ahb_1.io.axi_araddr <= io.ifu_axi.ar.bits.addr @[quasar.scala 351:35] - axi4_to_ahb_1.io.axi_arsize <= io.ifu_axi.ar.bits.size @[quasar.scala 352:35] - axi4_to_ahb_1.io.axi_arprot <= io.ifu_axi.ar.bits.prot @[quasar.scala 353:35] - axi4_to_ahb_1.io.axi_rready <= io.ifu_axi.r.ready @[quasar.scala 355:35] - inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 361:32] - axi4_to_ahb_2.clock <= clock - axi4_to_ahb_2.reset <= reset - axi4_to_ahb_2.io.axi_awvalid <= io.sb_axi.aw.valid @[quasar.scala 362:35] - axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 363:33] - axi4_to_ahb_2.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 364:34] - axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 365:36] - axi4_to_ahb_2.io.axi_awid <= io.sb_axi.aw.bits.id @[quasar.scala 366:32] - axi4_to_ahb_2.io.axi_awaddr <= io.sb_axi.aw.bits.addr @[quasar.scala 367:34] - axi4_to_ahb_2.io.axi_awsize <= io.sb_axi.aw.bits.size @[quasar.scala 368:34] - axi4_to_ahb_2.io.axi_awprot <= io.sb_axi.aw.bits.prot @[quasar.scala 369:34] - axi4_to_ahb_2.io.axi_wvalid <= io.sb_axi.w.valid @[quasar.scala 371:34] - axi4_to_ahb_2.io.axi_wdata <= io.sb_axi.w.bits.data @[quasar.scala 372:33] - axi4_to_ahb_2.io.axi_wstrb <= io.sb_axi.w.bits.strb @[quasar.scala 373:33] - axi4_to_ahb_2.io.axi_wlast <= io.sb_axi.w.bits.last @[quasar.scala 374:33] - axi4_to_ahb_2.io.axi_bready <= io.sb_axi.b.ready @[quasar.scala 375:34] - axi4_to_ahb_2.io.axi_arvalid <= io.sb_axi.ar.valid @[quasar.scala 377:35] - axi4_to_ahb_2.io.axi_arid <= io.sb_axi.ar.bits.id @[quasar.scala 378:32] - axi4_to_ahb_2.io.axi_araddr <= io.sb_axi.ar.bits.addr @[quasar.scala 379:34] - axi4_to_ahb_2.io.axi_arsize <= io.sb_axi.ar.bits.size @[quasar.scala 380:34] - axi4_to_ahb_2.io.axi_arprot <= io.sb_axi.ar.bits.prot @[quasar.scala 381:34] - axi4_to_ahb_2.io.axi_rready <= io.sb_axi.r.ready @[quasar.scala 383:34] - inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 388:33] - ahb_to_axi4.clock <= clock - ahb_to_axi4.reset <= reset - ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 389:34] - ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 390:35] - ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 391:37] - ahb_to_axi4.io.axi_awready <= io.dma_axi.aw.ready @[quasar.scala 392:36] - ahb_to_axi4.io.axi_wready <= io.dma_axi.w.ready @[quasar.scala 393:35] - ahb_to_axi4.io.axi_bvalid <= io.dma_axi.b.valid @[quasar.scala 394:35] - ahb_to_axi4.io.axi_bresp <= io.dma_axi.b.bits.resp @[quasar.scala 395:34] - ahb_to_axi4.io.axi_bid <= io.dma_axi.b.bits.id @[quasar.scala 396:32] - ahb_to_axi4.io.axi_arready <= io.dma_axi.ar.ready @[quasar.scala 399:36] - ahb_to_axi4.io.axi_rvalid <= io.dma_axi.ar.valid @[quasar.scala 400:35] - ahb_to_axi4.io.axi_rid <= io.dma_axi.r.bits.id @[quasar.scala 401:32] - ahb_to_axi4.io.axi_rdata <= io.dma_axi.r.bits.data @[quasar.scala 402:34] - ahb_to_axi4.io.axi_rresp <= io.dma_axi.r.bits.resp @[quasar.scala 403:34] - ahb_to_axi4.io.ahb.hsel <= io.dma.hsel @[quasar.scala 414:33] - ahb_to_axi4.io.ahb.hreadyin <= io.dma.hreadyin @[quasar.scala 415:37] - node _T_12 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) @[quasar.scala 416:31] - lsu.io.axi.aw.ready <= _T_12 @[quasar.scala 416:25] - node _T_13 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) @[quasar.scala 417:30] - lsu.io.axi.w.ready <= _T_13 @[quasar.scala 417:24] - node _T_14 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) @[quasar.scala 418:30] - lsu.io.axi.b.valid <= _T_14 @[quasar.scala 418:24] - node _T_15 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp) @[quasar.scala 419:34] - lsu.io.axi.b.bits.resp <= _T_15 @[quasar.scala 419:28] - node _T_16 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id) @[quasar.scala 420:32] - lsu.io.axi.b.bits.id <= _T_16 @[quasar.scala 420:26] - node _T_17 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready) @[quasar.scala 421:31] - lsu.io.axi.ar.ready <= _T_17 @[quasar.scala 421:25] - node _T_18 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid) @[quasar.scala 422:30] - lsu.io.axi.r.valid <= _T_18 @[quasar.scala 422:24] - node _T_19 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id) @[quasar.scala 423:32] - lsu.io.axi.r.bits.id <= _T_19 @[quasar.scala 423:26] - node _T_20 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data) @[quasar.scala 424:34] - lsu.io.axi.r.bits.data <= _T_20 @[quasar.scala 424:28] - node _T_21 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp) @[quasar.scala 425:34] - lsu.io.axi.r.bits.resp <= _T_21 @[quasar.scala 425:28] - node _T_22 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last) @[quasar.scala 426:34] - lsu.io.axi.r.bits.last <= _T_22 @[quasar.scala 426:28] - node _T_23 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_awready, io.ifu_axi.aw.ready) @[quasar.scala 428:31] - ifu.io.ifu.aw.ready <= _T_23 @[quasar.scala 428:25] - node _T_24 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_wready, io.ifu_axi.w.ready) @[quasar.scala 429:30] - ifu.io.ifu.w.ready <= _T_24 @[quasar.scala 429:24] - node _T_25 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_arready, io.ifu_axi.ar.ready) @[quasar.scala 430:31] - ifu.io.ifu.ar.ready <= _T_25 @[quasar.scala 430:25] - node _T_26 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rvalid, io.ifu_axi.r.valid) @[quasar.scala 431:30] - ifu.io.ifu.r.valid <= _T_26 @[quasar.scala 431:24] - node _T_27 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rid, io.ifu_axi.r.bits.id) @[quasar.scala 432:32] - ifu.io.ifu.r.bits.id <= _T_27 @[quasar.scala 432:26] - node _T_28 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rdata, io.ifu_axi.r.bits.data) @[quasar.scala 433:34] - ifu.io.ifu.r.bits.data <= _T_28 @[quasar.scala 433:28] - node _T_29 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rresp, io.ifu_axi.r.bits.resp) @[quasar.scala 434:34] - ifu.io.ifu.r.bits.resp <= _T_29 @[quasar.scala 434:28] - node _T_30 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rlast, io.ifu_axi.r.bits.last) @[quasar.scala 435:34] - ifu.io.ifu.r.bits.last <= _T_30 @[quasar.scala 435:28] - node _T_31 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_awready, io.sb_axi.aw.ready) @[quasar.scala 437:34] - dbg.io.sb_axi.aw.ready <= _T_31 @[quasar.scala 437:28] - node _T_32 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_wready, io.sb_axi.w.ready) @[quasar.scala 438:33] - dbg.io.sb_axi.w.ready <= _T_32 @[quasar.scala 438:27] - node _T_33 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bvalid, io.sb_axi.b.valid) @[quasar.scala 439:33] - dbg.io.sb_axi.b.valid <= _T_33 @[quasar.scala 439:27] - node _T_34 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bresp, io.sb_axi.b.bits.resp) @[quasar.scala 440:37] - dbg.io.sb_axi.b.bits.resp <= _T_34 @[quasar.scala 440:31] - node _T_35 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_arready, io.sb_axi.ar.ready) @[quasar.scala 441:34] - dbg.io.sb_axi.ar.ready <= _T_35 @[quasar.scala 441:28] - node _T_36 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rvalid, io.sb_axi.r.valid) @[quasar.scala 442:33] - dbg.io.sb_axi.r.valid <= _T_36 @[quasar.scala 442:27] - node _T_37 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rid, io.sb_axi.r.bits.id) @[quasar.scala 443:35] - dbg.io.sb_axi.r.bits.id <= _T_37 @[quasar.scala 443:29] - node _T_38 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rdata, io.sb_axi.r.bits.data) @[quasar.scala 444:37] - dbg.io.sb_axi.r.bits.data <= _T_38 @[quasar.scala 444:31] - node _T_39 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rresp, io.sb_axi.r.bits.resp) @[quasar.scala 445:37] - dbg.io.sb_axi.r.bits.resp <= _T_39 @[quasar.scala 445:31] - node _T_40 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid) @[quasar.scala 447:40] - dma_ctrl.io.dma_axi.aw.valid <= _T_40 @[quasar.scala 447:34] - node _T_41 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id) @[quasar.scala 448:42] - dma_ctrl.io.dma_axi.aw.bits.id <= _T_41 @[quasar.scala 448:36] - node _T_42 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr) @[quasar.scala 449:44] - dma_ctrl.io.dma_axi.aw.bits.addr <= _T_42 @[quasar.scala 449:38] - node _T_43 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size) @[quasar.scala 450:44] - dma_ctrl.io.dma_axi.aw.bits.size <= _T_43 @[quasar.scala 450:38] - node _T_44 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid) @[quasar.scala 451:39] - dma_ctrl.io.dma_axi.w.valid <= _T_44 @[quasar.scala 451:33] - node _T_45 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data) @[quasar.scala 452:43] - dma_ctrl.io.dma_axi.w.bits.data <= _T_45 @[quasar.scala 452:37] - node _T_46 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb) @[quasar.scala 453:43] - dma_ctrl.io.dma_axi.w.bits.strb <= _T_46 @[quasar.scala 453:37] - node _T_47 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready) @[quasar.scala 454:39] - dma_ctrl.io.dma_axi.b.ready <= _T_47 @[quasar.scala 454:33] - node _T_48 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid) @[quasar.scala 455:40] - dma_ctrl.io.dma_axi.ar.valid <= _T_48 @[quasar.scala 455:34] - node _T_49 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id) @[quasar.scala 456:42] - dma_ctrl.io.dma_axi.ar.bits.id <= _T_49 @[quasar.scala 456:36] - node _T_50 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) @[quasar.scala 457:44] - dma_ctrl.io.dma_axi.ar.bits.addr <= _T_50 @[quasar.scala 457:38] - node _T_51 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) @[quasar.scala 458:44] - dma_ctrl.io.dma_axi.ar.bits.size <= _T_51 @[quasar.scala 458:38] - node _T_52 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) @[quasar.scala 459:39] - dma_ctrl.io.dma_axi.r.ready <= _T_52 @[quasar.scala 459:33] - io.ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 461:12] - io.ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 461:12] - io.ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 461:12] - io.ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 461:12] - io.ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 461:12] - io.ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 461:12] - io.ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 461:12] - io.ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 461:12] - axi4_to_ahb_1.io.ahb.in.hresp <= io.ahb.in.hresp @[quasar.scala 461:12] - axi4_to_ahb_1.io.ahb.in.hready <= io.ahb.in.hready @[quasar.scala 461:12] - axi4_to_ahb_1.io.ahb.in.hrdata <= io.ahb.in.hrdata @[quasar.scala 461:12] - io.lsu_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 470:16] - io.lsu_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 470:16] - io.lsu_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 470:16] - io.lsu_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 470:16] - io.lsu_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 470:16] - io.lsu_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 470:16] - io.lsu_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 470:16] - io.lsu_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 470:16] - axi4_to_ahb.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 470:16] - axi4_to_ahb.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 470:16] - axi4_to_ahb.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 470:16] - io.sb_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 480:15] - io.sb_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 480:15] - io.sb_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 480:15] - io.sb_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 480:15] - io.sb_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 480:15] - io.sb_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 480:15] - io.sb_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 480:15] - io.sb_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 480:15] - axi4_to_ahb_2.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 480:15] - axi4_to_ahb_2.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 480:15] - axi4_to_ahb_2.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 480:15] - ahb_to_axi4.io.ahb.sig.out.hwdata <= io.dma.ahb.out.hwdata @[quasar.scala 490:16] - ahb_to_axi4.io.ahb.sig.out.hwrite <= io.dma.ahb.out.hwrite @[quasar.scala 490:16] - ahb_to_axi4.io.ahb.sig.out.htrans <= io.dma.ahb.out.htrans @[quasar.scala 490:16] - ahb_to_axi4.io.ahb.sig.out.hsize <= io.dma.ahb.out.hsize @[quasar.scala 490:16] - ahb_to_axi4.io.ahb.sig.out.hprot <= io.dma.ahb.out.hprot @[quasar.scala 490:16] - ahb_to_axi4.io.ahb.sig.out.hmastlock <= io.dma.ahb.out.hmastlock @[quasar.scala 490:16] - ahb_to_axi4.io.ahb.sig.out.hburst <= io.dma.ahb.out.hburst @[quasar.scala 490:16] - ahb_to_axi4.io.ahb.sig.out.haddr <= io.dma.ahb.out.haddr @[quasar.scala 490:16] - io.dma.ahb.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 490:16] - io.dma.ahb.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 490:16] - io.dma.ahb.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 490:16] - skip @[quasar.scala 305:26] - else : @[quasar.scala 497:15] - wire _T_53 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 499:33] - _T_53.hwdata <= UInt<64>("h00") @[quasar.scala 499:33] - _T_53.hwrite <= UInt<1>("h00") @[quasar.scala 499:33] - _T_53.htrans <= UInt<2>("h00") @[quasar.scala 499:33] - _T_53.hsize <= UInt<3>("h00") @[quasar.scala 499:33] - _T_53.hprot <= UInt<4>("h00") @[quasar.scala 499:33] - _T_53.hmastlock <= UInt<1>("h00") @[quasar.scala 499:33] - _T_53.hburst <= UInt<3>("h00") @[quasar.scala 499:33] - _T_53.haddr <= UInt<32>("h00") @[quasar.scala 499:33] - io.ahb.out.hwdata <= _T_53.hwdata @[quasar.scala 499:18] - io.ahb.out.hwrite <= _T_53.hwrite @[quasar.scala 499:18] - io.ahb.out.htrans <= _T_53.htrans @[quasar.scala 499:18] - io.ahb.out.hsize <= _T_53.hsize @[quasar.scala 499:18] - io.ahb.out.hprot <= _T_53.hprot @[quasar.scala 499:18] - io.ahb.out.hmastlock <= _T_53.hmastlock @[quasar.scala 499:18] - io.ahb.out.hburst <= _T_53.hburst @[quasar.scala 499:18] - io.ahb.out.haddr <= _T_53.haddr @[quasar.scala 499:18] - wire _T_54 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 508:37] - _T_54.hwdata <= UInt<64>("h00") @[quasar.scala 508:37] - _T_54.hwrite <= UInt<1>("h00") @[quasar.scala 508:37] - _T_54.htrans <= UInt<2>("h00") @[quasar.scala 508:37] - _T_54.hsize <= UInt<3>("h00") @[quasar.scala 508:37] - _T_54.hprot <= UInt<4>("h00") @[quasar.scala 508:37] - _T_54.hmastlock <= UInt<1>("h00") @[quasar.scala 508:37] - _T_54.hburst <= UInt<3>("h00") @[quasar.scala 508:37] - _T_54.haddr <= UInt<32>("h00") @[quasar.scala 508:37] - io.lsu_ahb.out.hwdata <= _T_54.hwdata @[quasar.scala 508:22] - io.lsu_ahb.out.hwrite <= _T_54.hwrite @[quasar.scala 508:22] - io.lsu_ahb.out.htrans <= _T_54.htrans @[quasar.scala 508:22] - io.lsu_ahb.out.hsize <= _T_54.hsize @[quasar.scala 508:22] - io.lsu_ahb.out.hprot <= _T_54.hprot @[quasar.scala 508:22] - io.lsu_ahb.out.hmastlock <= _T_54.hmastlock @[quasar.scala 508:22] - io.lsu_ahb.out.hburst <= _T_54.hburst @[quasar.scala 508:22] - io.lsu_ahb.out.haddr <= _T_54.haddr @[quasar.scala 508:22] - wire _T_55 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 518:36] - _T_55.hwdata <= UInt<64>("h00") @[quasar.scala 518:36] - _T_55.hwrite <= UInt<1>("h00") @[quasar.scala 518:36] - _T_55.htrans <= UInt<2>("h00") @[quasar.scala 518:36] - _T_55.hsize <= UInt<3>("h00") @[quasar.scala 518:36] - _T_55.hprot <= UInt<4>("h00") @[quasar.scala 518:36] - _T_55.hmastlock <= UInt<1>("h00") @[quasar.scala 518:36] - _T_55.hburst <= UInt<3>("h00") @[quasar.scala 518:36] - _T_55.haddr <= UInt<32>("h00") @[quasar.scala 518:36] - io.sb_ahb.out.hwdata <= _T_55.hwdata @[quasar.scala 518:21] - io.sb_ahb.out.hwrite <= _T_55.hwrite @[quasar.scala 518:21] - io.sb_ahb.out.htrans <= _T_55.htrans @[quasar.scala 518:21] - io.sb_ahb.out.hsize <= _T_55.hsize @[quasar.scala 518:21] - io.sb_ahb.out.hprot <= _T_55.hprot @[quasar.scala 518:21] - io.sb_ahb.out.hmastlock <= _T_55.hmastlock @[quasar.scala 518:21] - io.sb_ahb.out.hburst <= _T_55.hburst @[quasar.scala 518:21] - io.sb_ahb.out.haddr <= _T_55.haddr @[quasar.scala 518:21] - wire _T_56 : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar.scala 528:36] - _T_56.hresp <= UInt<1>("h00") @[quasar.scala 528:36] - _T_56.hready <= UInt<1>("h00") @[quasar.scala 528:36] - _T_56.hrdata <= UInt<64>("h00") @[quasar.scala 528:36] - io.dma.ahb.in.hresp <= _T_56.hresp @[quasar.scala 528:21] - io.dma.ahb.in.hready <= _T_56.hready @[quasar.scala 528:21] - io.dma.ahb.in.hrdata <= _T_56.hrdata @[quasar.scala 528:21] - skip @[quasar.scala 497:15] - io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 533:20] + node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 84:56] + node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 85:56] + node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 86:28] + ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 89:18] + dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 89:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 89:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 89:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 89:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 89:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 89:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 89:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 89:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 89:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 89:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 89:18] + dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 89:18] + ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 89:18] + ifu.reset <= io.core_rst_l @[quasar.scala 91:13] + ifu.io.scan_mode <= io.scan_mode @[quasar.scala 92:20] + ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 93:19] + ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 94:21] + ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 96:26] + ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 97:31] + ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 99:25] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 100:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 100:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 100:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 100:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 100:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 100:18] + ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 100:18] + io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 101:13] + io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 101:13] + io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 101:13] + io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 101:13] + io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 101:13] + io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 101:13] + ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 101:13] + ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 101:13] + ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 101:13] + ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 101:13] + ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 101:13] + ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 101:13] + ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 101:13] + io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 101:13] + io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 101:13] + io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 101:13] + io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 101:13] + io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 101:13] + io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 101:13] + io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 101:13] + io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 101:13] + ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 102:15] + ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 102:15] + io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 102:15] + io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 102:15] + io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 102:15] + io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 102:15] + io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 102:15] + io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 102:15] + io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 102:15] + ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 103:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 104:42] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 105:43] + ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 106:33] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 107:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 107:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 107:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 107:51] + dec.reset <= io.core_rst_l @[quasar.scala 110:13] + dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 111:19] + dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 112:21] + dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 113:32] + dec.io.rst_vec <= io.rst_vec @[quasar.scala 114:18] + dec.io.nmi_int <= io.nmi_int @[quasar.scala 115:18] + dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 116:18] + dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 117:25] + dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 118:24] + dec.io.core_id <= io.core_id @[quasar.scala 119:18] + dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 120:29] + dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 121:28] + dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 122:28] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 123:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 123:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 123:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 123:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 123:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 123:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 123:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 123:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 123:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 123:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 123:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 123:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 123:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 123:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 123:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 123:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 123:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 123:18] + dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 124:18] + dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 124:18] + dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 125:31] + dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 126:18] + dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 126:18] + dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 126:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 126:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 126:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 126:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 126:18] + dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 126:18] + dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 128:23] + dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 129:24] + dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 130:30] + dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 131:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 131:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 131:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 131:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 131:18] + dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 132:23] + dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 133:26] + dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 133:26] + dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 133:26] + dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 133:26] + dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 133:26] + dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 133:26] + dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 134:36] + dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 135:25] + dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 136:23] + dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 137:23] + dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 138:28] + dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 139:29] + dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 140:30] + dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 141:28] + dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 142:26] + dec.io.soft_int <= io.soft_int @[quasar.scala 144:19] + dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 145:23] + dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 146:25] + dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 147:26] + dec.io.timer_int <= io.timer_int @[quasar.scala 148:20] + dec.io.scan_mode <= io.scan_mode @[quasar.scala 149:20] + exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 152:18] + exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 152:18] + exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 152:18] + exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 152:18] + dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 152:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 152:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 152:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 152:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 152:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 152:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 152:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 152:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 152:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 152:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 152:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 152:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 152:18] + exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 152:18] + dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 152:18] + dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 152:18] + exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 152:18] + exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 152:18] + exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 152:18] + exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 152:18] + exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 152:18] + dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 152:18] + exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 152:18] + exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 152:18] + exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 152:18] + exu.reset <= io.core_rst_l @[quasar.scala 153:13] + exu.io.scan_mode <= io.scan_mode @[quasar.scala 154:20] + exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 155:25] + lsu.reset <= io.core_rst_l @[quasar.scala 158:13] + lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 159:23] + lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 160:32] + lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 161:35] + lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 162:29] + lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 163:35] + lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 164:18] + lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 164:18] + lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 165:27] + lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 166:16] + lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 166:16] + lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 166:16] + lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 166:16] + lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 166:16] + lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 166:16] + lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 166:16] + lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 166:16] + lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 166:16] + lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 166:16] + lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 166:16] + lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 166:16] + lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 166:16] + lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 167:30] + lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 169:26] + lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 169:26] + lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 171:25] + lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 172:18] + dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 172:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 172:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 172:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 172:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 172:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 172:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 172:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 172:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 172:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 172:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 172:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 172:18] + lsu.io.scan_mode <= io.scan_mode @[quasar.scala 173:20] + lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 174:19] + dbg.reset <= io.core_rst_l @[quasar.scala 177:13] + node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 178:32] + dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 178:26] + node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 179:60] + dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 179:28] + node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 180:60] + dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 180:28] + dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 181:29] + dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 182:29] + dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 183:34] + dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 184:29] + dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 185:21] + dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 186:23] + dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 187:24] + dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 188:24] + dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 189:17] + dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 189:17] + dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 189:17] + dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 189:17] + dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 189:17] + io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 189:17] + io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 189:17] + io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 189:17] + io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 189:17] + io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 189:17] + io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 189:17] + io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 189:17] + io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 189:17] + io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 189:17] + io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 189:17] + io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 189:17] + io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 189:17] + dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 189:17] + dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 189:17] + dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 189:17] + dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 189:17] + io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 189:17] + io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 189:17] + io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 189:17] + io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 189:17] + io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 189:17] + dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 189:17] + io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 189:17] + io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 189:17] + io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 189:17] + io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 189:17] + io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 189:17] + io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 189:17] + io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 189:17] + io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 189:17] + io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 189:17] + io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 189:17] + io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 189:17] + dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 189:17] + dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 190:25] + node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 191:42] + dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 191:20] + dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 192:23] + dbg.io.scan_mode <= io.scan_mode @[quasar.scala 193:20] + dma_ctrl.reset <= io.core_rst_l @[quasar.scala 197:18] + dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 198:24] + dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 199:30] + dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 200:28] + dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 201:25] + dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 202:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 202:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 202:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 202:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 202:23] + dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 203:26] + dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 203:26] + dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 204:28] + dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 205:31] + dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 206:29] + dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 207:30] + dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 208:26] + dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 209:34] + pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 212:30] + pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 213:23] + pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 214:29] + pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 215:31] + pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 216:33] + pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 217:34] + lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 218:28] + pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 218:28] + pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 218:28] + pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 218:28] + pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 218:28] + pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 218:28] + pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 218:28] + dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 219:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 219:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 219:28] + dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 219:28] + dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 219:28] + dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 219:28] + io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 221:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 221:19] + io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 221:19] + io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 221:19] + io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 221:19] + io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 221:19] + io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 221:19] + io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 224:24] + io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 225:23] + io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 226:31] + io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 227:21] + io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 228:24] + io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 229:20] + io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 230:26] + io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 231:25] + io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 232:24] + io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 233:25] + io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 234:23] + io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 235:23] + io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 236:23] + io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 237:23] + lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 239:11] + lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 239:11] + io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 239:11] + io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 239:11] + io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 239:11] + io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 239:11] + io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 239:11] + io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 239:11] + io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 239:11] + io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 239:11] + lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 242:14] + lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 242:14] + lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 242:14] + lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 242:14] + lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 242:14] + io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 242:14] + io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 242:14] + io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 242:14] + io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 242:14] + io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 242:14] + io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 242:14] + io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 242:14] + io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 242:14] + io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 242:14] + io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 242:14] + io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 242:14] + io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 242:14] + lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 242:14] + lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 242:14] + lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 242:14] + lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 242:14] + io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 242:14] + io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 242:14] + io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 242:14] + io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 242:14] + io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 242:14] + lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 242:14] + io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 242:14] + io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 242:14] + io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 242:14] + io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 242:14] + io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 242:14] + io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 242:14] + io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 242:14] + io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 242:14] + io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 242:14] + io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 242:14] + io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 242:14] + lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 242:14] + ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 245:14] + ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 245:14] + ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 245:14] + ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 245:14] + ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 245:14] + io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 245:14] + io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 245:14] + io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 245:14] + io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 245:14] + io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 245:14] + io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 245:14] + io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 245:14] + io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 245:14] + io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 245:14] + io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 245:14] + io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 245:14] + io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 245:14] + ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 245:14] + ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 245:14] + ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 245:14] + ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 245:14] + io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 245:14] + io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 245:14] + io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 245:14] + io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 245:14] + io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 245:14] + ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 245:14] + io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 245:14] + io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 245:14] + io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 245:14] + io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 245:14] + io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 245:14] + io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 245:14] + io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 245:14] + io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 245:14] + io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 245:14] + io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 245:14] + io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 245:14] + ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 245:14] + io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 246:14] + io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 246:14] + io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 246:14] + io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 246:14] + io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 246:14] + io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 246:14] + io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 246:14] + io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 246:14] + io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 246:14] + io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 246:14] + dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 246:14] + io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 246:14] + wire _T_12 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 424:29] + _T_12.hwdata <= UInt<64>("h00") @[quasar.scala 424:29] + _T_12.hwrite <= UInt<1>("h00") @[quasar.scala 424:29] + _T_12.htrans <= UInt<2>("h00") @[quasar.scala 424:29] + _T_12.hsize <= UInt<3>("h00") @[quasar.scala 424:29] + _T_12.hprot <= UInt<4>("h00") @[quasar.scala 424:29] + _T_12.hmastlock <= UInt<1>("h00") @[quasar.scala 424:29] + _T_12.hburst <= UInt<3>("h00") @[quasar.scala 424:29] + _T_12.haddr <= UInt<32>("h00") @[quasar.scala 424:29] + io.ahb.out.hwdata <= _T_12.hwdata @[quasar.scala 424:14] + io.ahb.out.hwrite <= _T_12.hwrite @[quasar.scala 424:14] + io.ahb.out.htrans <= _T_12.htrans @[quasar.scala 424:14] + io.ahb.out.hsize <= _T_12.hsize @[quasar.scala 424:14] + io.ahb.out.hprot <= _T_12.hprot @[quasar.scala 424:14] + io.ahb.out.hmastlock <= _T_12.hmastlock @[quasar.scala 424:14] + io.ahb.out.hburst <= _T_12.hburst @[quasar.scala 424:14] + io.ahb.out.haddr <= _T_12.haddr @[quasar.scala 424:14] + wire _T_13 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 425:33] + _T_13.hwdata <= UInt<64>("h00") @[quasar.scala 425:33] + _T_13.hwrite <= UInt<1>("h00") @[quasar.scala 425:33] + _T_13.htrans <= UInt<2>("h00") @[quasar.scala 425:33] + _T_13.hsize <= UInt<3>("h00") @[quasar.scala 425:33] + _T_13.hprot <= UInt<4>("h00") @[quasar.scala 425:33] + _T_13.hmastlock <= UInt<1>("h00") @[quasar.scala 425:33] + _T_13.hburst <= UInt<3>("h00") @[quasar.scala 425:33] + _T_13.haddr <= UInt<32>("h00") @[quasar.scala 425:33] + io.lsu_ahb.out.hwdata <= _T_13.hwdata @[quasar.scala 425:18] + io.lsu_ahb.out.hwrite <= _T_13.hwrite @[quasar.scala 425:18] + io.lsu_ahb.out.htrans <= _T_13.htrans @[quasar.scala 425:18] + io.lsu_ahb.out.hsize <= _T_13.hsize @[quasar.scala 425:18] + io.lsu_ahb.out.hprot <= _T_13.hprot @[quasar.scala 425:18] + io.lsu_ahb.out.hmastlock <= _T_13.hmastlock @[quasar.scala 425:18] + io.lsu_ahb.out.hburst <= _T_13.hburst @[quasar.scala 425:18] + io.lsu_ahb.out.haddr <= _T_13.haddr @[quasar.scala 425:18] + wire _T_14 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 426:32] + _T_14.hwdata <= UInt<64>("h00") @[quasar.scala 426:32] + _T_14.hwrite <= UInt<1>("h00") @[quasar.scala 426:32] + _T_14.htrans <= UInt<2>("h00") @[quasar.scala 426:32] + _T_14.hsize <= UInt<3>("h00") @[quasar.scala 426:32] + _T_14.hprot <= UInt<4>("h00") @[quasar.scala 426:32] + _T_14.hmastlock <= UInt<1>("h00") @[quasar.scala 426:32] + _T_14.hburst <= UInt<3>("h00") @[quasar.scala 426:32] + _T_14.haddr <= UInt<32>("h00") @[quasar.scala 426:32] + io.sb_ahb.out.hwdata <= _T_14.hwdata @[quasar.scala 426:17] + io.sb_ahb.out.hwrite <= _T_14.hwrite @[quasar.scala 426:17] + io.sb_ahb.out.htrans <= _T_14.htrans @[quasar.scala 426:17] + io.sb_ahb.out.hsize <= _T_14.hsize @[quasar.scala 426:17] + io.sb_ahb.out.hprot <= _T_14.hprot @[quasar.scala 426:17] + io.sb_ahb.out.hmastlock <= _T_14.hmastlock @[quasar.scala 426:17] + io.sb_ahb.out.hburst <= _T_14.hburst @[quasar.scala 426:17] + io.sb_ahb.out.haddr <= _T_14.haddr @[quasar.scala 426:17] + wire _T_15 : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar.scala 427:32] + _T_15.hresp <= UInt<1>("h00") @[quasar.scala 427:32] + _T_15.hready <= UInt<1>("h00") @[quasar.scala 427:32] + _T_15.hrdata <= UInt<64>("h00") @[quasar.scala 427:32] + io.dma.ahb.in.hresp <= _T_15.hresp @[quasar.scala 427:17] + io.dma.ahb.in.hready <= _T_15.hready @[quasar.scala 427:17] + io.dma.ahb.in.hrdata <= _T_15.hrdata @[quasar.scala 427:17] + io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 428:20] module quasar_wrapper : input clock : Clock diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 5ba94ad1..a5ef518c 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -50524,7 +50524,6 @@ module csr_tlu( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -52651,7 +52650,6 @@ module csr_tlu( assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1718:31] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1719:31] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1721:31] - assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1722:31] assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1723:31] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1724:31] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1725:31] @@ -54380,7 +54378,6 @@ module dec_tlu_ctl( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -54633,7 +54630,6 @@ module dec_tlu_ctl( wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 818:15] @@ -55722,7 +55718,6 @@ module dec_tlu_ctl( .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(csr_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override), @@ -56047,7 +56042,6 @@ module dec_tlu_ctl( assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 890:40] assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 891:40] assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 893:40] - assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 894:40] assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 895:40] assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 896:40] assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 897:40] @@ -57946,7 +57940,6 @@ module dec( output [31:0] io_rv_trace_pkt_rv_i_tval_ip, output io_dec_tlu_misc_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -58492,7 +58485,6 @@ module dec( wire tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 120:19] - wire tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 120:19] @@ -58949,7 +58941,6 @@ module dec( .io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(tlu_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override), @@ -59089,7 +59080,6 @@ module dec( assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 300:32] assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 284:35] assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 286:36] - assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 287:36] assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 288:36] assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 289:36] assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 290:36] @@ -80519,627 +80509,6 @@ end // initial end end endmodule -module axi4_to_ahb( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_clk_override, - input io_axi_awvalid, - input io_axi_wvalid, - input io_axi_bready, - input io_axi_arvalid, - input io_axi_rready, - output io_axi_awready, - output io_axi_wready -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_en; // @[lib.scala 368:23] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_en; // @[lib.scala 368:23] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_en; // @[lib.scala 343:22] - wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_en; // @[lib.scala 343:22] - wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_en; // @[lib.scala 343:22] - wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_en; // @[lib.scala 343:22] - wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 57:22 axi4_to_ahb.scala 404:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 63:45] - wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 83:21 axi4_to_ahb.scala 195:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 372:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 373:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 172:27] - wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 173:30] - wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 190:32] - wire _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_281 ? 1'h0 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_188 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_186 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_175 ? 1'h0 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_136 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_101 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] - wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 175:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 175:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 220:41] - wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 221:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 234:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 234:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 234:26] - wire _T_286 = buf_state_en & slave_ready; // @[axi4_to_ahb.scala 292:51] - wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_136 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_101 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67] - wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 248:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 248:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 248:67] - wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 293:42] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 293:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 293:65] - wire [2:0] _T_295 = _T_287 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 293:26] - wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] - wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] - wire [2:0] _GEN_68 = _T_136 ? _T_154 : _GEN_50; // @[Conditional.scala 39:67] - wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] - wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 193:56] - wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 193:91] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 193:74] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 224:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 224:38] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 229:51] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 297:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 297:33] - wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] - wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 362:47] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 363:50] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 364:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 365:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 365:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 367:35] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 367:33] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 367:21] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 368:37] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 368:20] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 372:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 372:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 373:55] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 398:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 398:58] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 400:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 400:60] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_6_io_l1clk), - .io_clk(rvclkhdr_6_io_clk), - .io_en(rvclkhdr_6_io_en), - .io_scan_mode(rvclkhdr_6_io_scan_mode) - ); - rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_7_io_l1clk), - .io_clk(rvclkhdr_7_io_clk), - .io_en(rvclkhdr_7_io_en), - .io_scan_mode(rvclkhdr_7_io_scan_mode) - ); - rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_8_io_l1clk), - .io_clk(rvclkhdr_8_io_clk), - .io_en(rvclkhdr_8_io_en), - .io_scan_mode(rvclkhdr_8_io_scan_mode) - ); - rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_9_io_l1clk), - .io_clk(rvclkhdr_9_io_clk), - .io_en(rvclkhdr_9_io_en), - .io_scan_mode(rvclkhdr_9_io_scan_mode) - ); - assign io_axi_awready = _T_626 & master_ready; // @[axi4_to_ahb.scala 367:18] - assign io_axi_wready = _T_630 & master_ready; // @[axi4_to_ahb.scala 368:17] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & io_clk_override; // @[lib.scala 345:16] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - buf_state = _RAND_0[2:0]; - _RAND_1 = {1{`RANDOM}}; - wrbuf_vld = _RAND_1[0:0]; - _RAND_2 = {1{`RANDOM}}; - wrbuf_data_vld = _RAND_2[0:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - buf_state = 3'h0; - end - if (reset) begin - wrbuf_vld = 1'h0; - end - if (reset) begin - wrbuf_data_vld = 1'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_state <= 3'h0; - end else if (buf_state_en) begin - if (_T_49) begin - if (buf_write_in) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else if (_T_101) begin - if (_T_104) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_136) begin - if (_T_152) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_175) begin - buf_state <= 3'h3; - end else if (_T_186) begin - buf_state <= 3'h5; - end else if (_T_188) begin - buf_state <= 3'h4; - end else if (_T_281) begin - if (_T_287) begin - buf_state <= 3'h5; - end else if (master_valid) begin - if (_T_51) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else begin - buf_state <= 3'h0; - end - end else begin - buf_state <= 3'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_vld <= 1'h0; - end else begin - wrbuf_vld <= _T_636 & _T_637; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_data_vld <= 1'h0; - end else begin - wrbuf_data_vld <= _T_641 & _T_637; - end - end -endmodule -module ahb_to_axi4( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_axi_awready, - input io_axi_arready, - input io_axi_rvalid, - input [1:0] io_axi_rresp, - output io_axi_awvalid, - output io_axi_arvalid, - output io_ahb_sig_in_hresp -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_2_io_en; // @[lib.scala 343:22] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_5_io_en; // @[lib.scala 343:22] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] - wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 89:33 ahb_to_axi4.scala 178:31] - reg [1:0] buf_state; // @[Reg.scala 27:20] - wire _T_6 = 2'h0 == buf_state; // @[Conditional.scala 37:30] - wire _T_11 = 2'h1 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 103:33 ahb_to_axi4.scala 228:27] - reg cmdbuf_vld; // @[ahb_to_axi4.scala 185:61] - wire _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 183:66] - wire _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 183:102] - wire _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 183:84] - wire _T_153 = ~_T_152; // @[ahb_to_axi4.scala 183:48] - wire cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 183:46] - wire _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 126:24] - wire _T_21 = _T_20 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 126:37] - wire _T_27 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 127:38] - wire _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 127:36] - wire _T_29 = 2'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_35 = _T_27 & _T_20; // @[ahb_to_axi4.scala 132:44] - wire _T_36 = 2'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 138:62] - wire _GEN_1 = _T_36 & io_axi_rvalid; // @[Conditional.scala 39:67] - wire _GEN_5 = _T_29 ? _T_21 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_10 = _T_11 ? _T_21 : _GEN_5; // @[Conditional.scala 39:67] - wire buf_state_en = _T_6 ? 1'h0 : _GEN_10; // @[Conditional.scala 40:58] - wire _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 138:41] - wire _GEN_2 = _T_36 & buf_state_en; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_36 & _T_41; // @[Conditional.scala 39:67] - wire _GEN_6 = _T_29 & _T_35; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_29 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67] - wire _GEN_11 = _T_11 ? _T_28 : _GEN_6; // @[Conditional.scala 39:67] - wire _GEN_12 = _T_11 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire cmdbuf_wr_en = _T_6 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] - wire buf_rdata_en = _T_6 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] - reg ahb_hresp_q; // @[ahb_to_axi4.scala 167:60] - reg buf_read_error; // @[ahb_to_axi4.scala 164:60] - wire _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 182:109] - wire _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 182:107] - wire cmdbuf_rst = _T_146 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 182:124] - wire _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 185:66] - wire _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 185:110] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - assign io_axi_awvalid = 1'h0; // @[ahb_to_axi4.scala 202:27] - assign io_axi_arvalid = cmdbuf_vld; // @[ahb_to_axi4.scala 217:27] - assign io_ahb_sig_in_hresp = buf_read_error | ahb_hresp_q; // @[ahb_to_axi4.scala 153:38] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = 1'h0; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_3_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_6 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = _T_6 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_5_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - buf_state = _RAND_0[1:0]; - _RAND_1 = {1{`RANDOM}}; - cmdbuf_vld = _RAND_1[0:0]; - _RAND_2 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - buf_read_error = _RAND_3[0:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - buf_state = 2'h0; - end - if (reset) begin - cmdbuf_vld = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - buf_read_error = 1'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - buf_state <= 2'h0; - end else if (buf_state_en) begin - if (_T_6) begin - buf_state <= 2'h2; - end else if (_T_11) begin - buf_state <= 2'h0; - end else if (_T_29) begin - if (io_ahb_sig_in_hresp) begin - buf_state <= 2'h0; - end else begin - buf_state <= 2'h3; - end - end else begin - buf_state <= 2'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_vld <= 1'h0; - end else begin - cmdbuf_vld <= _T_156 & _T_157; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_sig_in_hresp; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - buf_read_error <= 1'h0; - end else if (_T_6) begin - buf_read_error <= 1'h0; - end else if (_T_11) begin - buf_read_error <= 1'h0; - end else if (_T_29) begin - buf_read_error <= 1'h0; - end else begin - buf_read_error <= _GEN_3; - end - end -endmodule module quasar( input clock, input reset, @@ -81154,7 +80523,6 @@ module quasar( output io_lsu_axi_w_valid, output [63:0] io_lsu_axi_w_bits_data, output [7:0] io_lsu_axi_w_bits_strb, - output io_lsu_axi_b_ready, input io_lsu_axi_b_valid, input [1:0] io_lsu_axi_b_bits_resp, input [2:0] io_lsu_axi_b_bits_id, @@ -81165,20 +80533,15 @@ module quasar( output [3:0] io_lsu_axi_ar_bits_region, output [2:0] io_lsu_axi_ar_bits_size, output [3:0] io_lsu_axi_ar_bits_cache, - output io_lsu_axi_r_ready, input io_lsu_axi_r_valid, input [2:0] io_lsu_axi_r_bits_id, input [63:0] io_lsu_axi_r_bits_data, input [1:0] io_lsu_axi_r_bits_resp, - output io_ifu_axi_aw_valid, - output io_ifu_axi_w_valid, - output io_ifu_axi_b_ready, input io_ifu_axi_ar_ready, output io_ifu_axi_ar_valid, output [2:0] io_ifu_axi_ar_bits_id, output [31:0] io_ifu_axi_ar_bits_addr, output [3:0] io_ifu_axi_ar_bits_region, - output io_ifu_axi_r_ready, input io_ifu_axi_r_valid, input [2:0] io_ifu_axi_r_bits_id, input [63:0] io_ifu_axi_r_bits_data, @@ -81192,7 +80555,6 @@ module quasar( output io_sb_axi_w_valid, output [63:0] io_sb_axi_w_bits_data, output [7:0] io_sb_axi_w_bits_strb, - output io_sb_axi_b_ready, input io_sb_axi_b_valid, input [1:0] io_sb_axi_b_bits_resp, input io_sb_axi_ar_ready, @@ -81200,7 +80562,6 @@ module quasar( output [31:0] io_sb_axi_ar_bits_addr, output [3:0] io_sb_axi_ar_bits_region, output [2:0] io_sb_axi_ar_bits_size, - output io_sb_axi_r_ready, input io_sb_axi_r_valid, input [63:0] io_sb_axi_r_bits_data, input [1:0] io_sb_axi_r_bits_resp, @@ -81311,793 +80672,792 @@ module quasar( input io_soft_int, input io_scan_mode ); - wire ifu_clock; // @[quasar.scala 125:19] - wire ifu_reset; // @[quasar.scala 125:19] - wire ifu_io_exu_flush_final; // @[quasar.scala 125:19] - wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 125:19] - wire ifu_io_free_clk; // @[quasar.scala 125:19] - wire ifu_io_active_clk; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 125:19] - wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 125:19] - wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 125:19] - wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 125:19] - wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 125:19] - wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 125:19] - wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 125:19] - wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 125:19] - wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 125:19] - wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 125:19] - wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 125:19] - wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 125:19] - wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 125:19] - wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 125:19] - wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 125:19] - wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 125:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 125:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 125:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 125:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 125:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 125:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 125:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 125:19] - wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 125:19] - wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 125:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 125:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 125:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 125:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 125:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 125:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 125:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 125:19] - wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 125:19] - wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 125:19] - wire ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 125:19] - wire ifu_io_iccm_correction_state; // @[quasar.scala 125:19] - wire ifu_io_iccm_wren; // @[quasar.scala 125:19] - wire ifu_io_iccm_rden; // @[quasar.scala 125:19] - wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 125:19] - wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 125:19] - wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 125:19] - wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 125:19] - wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 125:19] - wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 125:19] - wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 125:19] - wire ifu_io_ic_rd_en; // @[quasar.scala 125:19] - wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 125:19] - wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 125:19] - wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 125:19] - wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 125:19] - wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 125:19] - wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 125:19] - wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 125:19] - wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 125:19] - wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 125:19] - wire ifu_io_ic_tag_perr; // @[quasar.scala 125:19] - wire ifu_io_ic_debug_rd_en; // @[quasar.scala 125:19] - wire ifu_io_ic_debug_wr_en; // @[quasar.scala 125:19] - wire ifu_io_ic_debug_tag_array; // @[quasar.scala 125:19] - wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 125:19] - wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 125:19] - wire ifu_io_ic_sel_premux_data; // @[quasar.scala 125:19] - wire ifu_io_ifu_ar_ready; // @[quasar.scala 125:19] - wire ifu_io_ifu_ar_valid; // @[quasar.scala 125:19] - wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 125:19] - wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 125:19] - wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 125:19] - wire ifu_io_ifu_r_valid; // @[quasar.scala 125:19] - wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 125:19] - wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 125:19] - wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 125:19] - wire ifu_io_ifu_bus_clk_en; // @[quasar.scala 125:19] - wire ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 125:19] - wire ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 125:19] - wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 125:19] - wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 125:19] - wire ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 125:19] - wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 125:19] - wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 125:19] - wire ifu_io_iccm_dma_ecc_error; // @[quasar.scala 125:19] - wire ifu_io_iccm_dma_rvalid; // @[quasar.scala 125:19] - wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 125:19] - wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 125:19] - wire ifu_io_iccm_ready; // @[quasar.scala 125:19] - wire ifu_io_iccm_dma_sb_error; // @[quasar.scala 125:19] - wire ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 125:19] - wire ifu_io_scan_mode; // @[quasar.scala 125:19] - wire dec_clock; // @[quasar.scala 126:19] - wire dec_reset; // @[quasar.scala 126:19] - wire dec_io_free_clk; // @[quasar.scala 126:19] - wire dec_io_active_clk; // @[quasar.scala 126:19] - wire dec_io_lsu_fastint_stall_any; // @[quasar.scala 126:19] - wire dec_io_dec_pause_state_cg; // @[quasar.scala 126:19] - wire [30:0] dec_io_rst_vec; // @[quasar.scala 126:19] - wire dec_io_nmi_int; // @[quasar.scala 126:19] - wire [30:0] dec_io_nmi_vec; // @[quasar.scala 126:19] - wire dec_io_i_cpu_halt_req; // @[quasar.scala 126:19] - wire dec_io_i_cpu_run_req; // @[quasar.scala 126:19] - wire dec_io_o_cpu_halt_status; // @[quasar.scala 126:19] - wire dec_io_o_cpu_halt_ack; // @[quasar.scala 126:19] - wire dec_io_o_cpu_run_ack; // @[quasar.scala 126:19] - wire dec_io_o_debug_mode_status; // @[quasar.scala 126:19] - wire [27:0] dec_io_core_id; // @[quasar.scala 126:19] - wire dec_io_mpc_debug_halt_req; // @[quasar.scala 126:19] - wire dec_io_mpc_debug_run_req; // @[quasar.scala 126:19] - wire dec_io_mpc_reset_run_req; // @[quasar.scala 126:19] - wire dec_io_mpc_debug_halt_ack; // @[quasar.scala 126:19] - wire dec_io_mpc_debug_run_ack; // @[quasar.scala 126:19] - wire dec_io_debug_brkpt_status; // @[quasar.scala 126:19] - wire dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 126:19] - wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 126:19] - wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 126:19] - wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 126:19] - wire dec_io_lsu_idle_any; // @[quasar.scala 126:19] - wire dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 126:19] - wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 126:19] - wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 126:19] - wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 126:19] - wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 126:19] - wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 126:19] - wire dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 126:19] - wire [31:0] dec_io_exu_div_result; // @[quasar.scala 126:19] - wire dec_io_exu_div_wren; // @[quasar.scala 126:19] - wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 126:19] - wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 126:19] - wire dec_io_lsu_load_stall_any; // @[quasar.scala 126:19] - wire dec_io_lsu_store_stall_any; // @[quasar.scala 126:19] - wire dec_io_iccm_dma_sb_error; // @[quasar.scala 126:19] - wire dec_io_exu_flush_final; // @[quasar.scala 126:19] - wire dec_io_timer_int; // @[quasar.scala 126:19] - wire dec_io_soft_int; // @[quasar.scala 126:19] - wire dec_io_dbg_halt_req; // @[quasar.scala 126:19] - wire dec_io_dbg_resume_req; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 126:19] - wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 126:19] - wire dec_io_dec_dbg_cmd_done; // @[quasar.scala 126:19] - wire dec_io_dec_dbg_cmd_fail; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_0_select; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_0_store; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_0_load; // @[quasar.scala 126:19] - wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_1_select; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_1_store; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_1_load; // @[quasar.scala 126:19] - wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_2_select; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_2_store; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_2_load; // @[quasar.scala 126:19] - wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_3_select; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_3_store; // @[quasar.scala 126:19] - wire dec_io_trigger_pkt_any_3_load; // @[quasar.scala 126:19] - wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 126:19] - wire dec_io_exu_i0_br_way_r; // @[quasar.scala 126:19] - wire dec_io_lsu_p_valid; // @[quasar.scala 126:19] - wire dec_io_lsu_p_bits_fast_int; // @[quasar.scala 126:19] - wire dec_io_lsu_p_bits_by; // @[quasar.scala 126:19] - wire dec_io_lsu_p_bits_half; // @[quasar.scala 126:19] - wire dec_io_lsu_p_bits_word; // @[quasar.scala 126:19] - wire dec_io_lsu_p_bits_load; // @[quasar.scala 126:19] - wire dec_io_lsu_p_bits_store; // @[quasar.scala 126:19] - wire dec_io_lsu_p_bits_unsign; // @[quasar.scala 126:19] - wire dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 126:19] - wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 126:19] - wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_perfcnt0; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_perfcnt1; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_perfcnt2; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_perfcnt3; // @[quasar.scala 126:19] - wire dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 126:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 126:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 126:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 126:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 126:19] - wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 126:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 126:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 126:19] - wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 126:19] - wire dec_io_scan_mode; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 126:19] - wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 126:19] - wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 126:19] - wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 126:19] - wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 126:19] - wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 126:19] - wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 126:19] - wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 126:19] - wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 126:19] - wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 126:19] - wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 126:19] - wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 126:19] - wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 126:19] - wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 126:19] - wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 126:19] - wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 126:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 126:19] - wire dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 126:19] - wire dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 126:19] - wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 126:19] - wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 126:19] - wire dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 126:19] - wire dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 126:19] - wire dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 126:19] - wire dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 126:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 126:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 126:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 126:19] - wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 126:19] - wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 126:19] - wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 126:19] - wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 126:19] - wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 126:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 126:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 126:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 126:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 126:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 126:19] - wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 126:19] - wire dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 126:19] - wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 126:19] - wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 126:19] - wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 126:19] - wire dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 126:19] - wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 126:19] - wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 126:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 126:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 126:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 126:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 126:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 126:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 126:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 126:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 126:19] - wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 126:19] - wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 126:19] - wire dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 126:19] - wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 126:19] - wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 126:19] - wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 126:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 126:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 126:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 126:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 126:19] - wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 126:19] - wire dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 126:19] - wire dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 126:19] - wire dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 126:19] - wire dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 126:19] - wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 126:19] - wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 126:19] - wire [31:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 126:19] - wire dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 126:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 126:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 126:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 126:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 126:19] - wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 126:19] - wire dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 126:19] - wire dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 126:19] - wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 126:19] - wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 126:19] - wire dec_io_dec_pic_mhwakeup; // @[quasar.scala 126:19] - wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 126:19] - wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 126:19] - wire dec_io_dec_pic_mexintpend; // @[quasar.scala 126:19] - wire dbg_clock; // @[quasar.scala 127:19] - wire dbg_reset; // @[quasar.scala 127:19] - wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 127:19] - wire dbg_io_dbg_core_rst_l; // @[quasar.scala 127:19] - wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 127:19] - wire dbg_io_core_dbg_cmd_done; // @[quasar.scala 127:19] - wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 127:19] - wire dbg_io_dbg_halt_req; // @[quasar.scala 127:19] - wire dbg_io_dbg_resume_req; // @[quasar.scala 127:19] - wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 127:19] - wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 127:19] - wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 127:19] - wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 127:19] - wire dbg_io_dmi_reg_en; // @[quasar.scala 127:19] - wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 127:19] - wire dbg_io_dmi_reg_wr_en; // @[quasar.scala 127:19] - wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 127:19] - wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 127:19] - wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 127:19] - wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 127:19] - wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 127:19] - wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 127:19] - wire dbg_io_sb_axi_w_ready; // @[quasar.scala 127:19] - wire dbg_io_sb_axi_w_valid; // @[quasar.scala 127:19] - wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 127:19] - wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 127:19] - wire dbg_io_sb_axi_b_ready; // @[quasar.scala 127:19] - wire dbg_io_sb_axi_b_valid; // @[quasar.scala 127:19] - wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 127:19] - wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 127:19] - wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 127:19] - wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 127:19] - wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 127:19] - wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 127:19] - wire dbg_io_sb_axi_r_ready; // @[quasar.scala 127:19] - wire dbg_io_sb_axi_r_valid; // @[quasar.scala 127:19] - wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 127:19] - wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 127:19] - wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 127:19] - wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 127:19] - wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 127:19] - wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 127:19] - wire [31:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 127:19] - wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 127:19] - wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 127:19] - wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 127:19] - wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 127:19] - wire [31:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 127:19] - wire dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 127:19] - wire dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 127:19] - wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 127:19] - wire dbg_io_dbg_rst_l; // @[quasar.scala 127:19] - wire dbg_io_clk_override; // @[quasar.scala 127:19] - wire dbg_io_scan_mode; // @[quasar.scala 127:19] - wire exu_clock; // @[quasar.scala 128:19] - wire exu_reset; // @[quasar.scala 128:19] - wire exu_io_scan_mode; // @[quasar.scala 128:19] - wire exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 128:19] - wire exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 128:19] - wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 128:19] - wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 128:19] - wire exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 128:19] - wire exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 128:19] - wire exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 128:19] - wire exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 128:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 128:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 128:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 128:19] - wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 128:19] - wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 128:19] - wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 128:19] - wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 128:19] - wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 128:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 128:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 128:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 128:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 128:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 128:19] - wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 128:19] - wire exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 128:19] - wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 128:19] - wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 128:19] - wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 128:19] - wire exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 128:19] - wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 128:19] - wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 128:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 128:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 128:19] - wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 128:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 128:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 128:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 128:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 128:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 128:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 128:19] - wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 128:19] - wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 128:19] - wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 128:19] - wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 128:19] - wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 128:19] - wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 128:19] - wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 128:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 128:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 128:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 128:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 128:19] - wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 128:19] - wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 128:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 128:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 128:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 128:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 128:19] - wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 128:19] - wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 128:19] - wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 128:19] - wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 128:19] - wire exu_io_exu_flush_final; // @[quasar.scala 128:19] - wire [31:0] exu_io_exu_div_result; // @[quasar.scala 128:19] - wire exu_io_exu_div_wren; // @[quasar.scala 128:19] - wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 128:19] - wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 128:19] - wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 128:19] - wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 128:19] - wire lsu_clock; // @[quasar.scala 129:19] - wire lsu_reset; // @[quasar.scala 129:19] - wire lsu_io_clk_override; // @[quasar.scala 129:19] - wire lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 129:19] - wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 129:19] - wire lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 129:19] - wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 129:19] - wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 129:19] - wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 129:19] - wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 129:19] - wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 129:19] - wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 129:19] - wire lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 129:19] - wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 129:19] - wire lsu_io_lsu_pic_picm_wren; // @[quasar.scala 129:19] - wire lsu_io_lsu_pic_picm_rden; // @[quasar.scala 129:19] - wire lsu_io_lsu_pic_picm_mken; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 129:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 129:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 129:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 129:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 129:19] - wire lsu_io_dccm_wren; // @[quasar.scala 129:19] - wire lsu_io_dccm_rden; // @[quasar.scala 129:19] - wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 129:19] - wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 129:19] - wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 129:19] - wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 129:19] - wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 129:19] - wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 129:19] - wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 129:19] - wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 129:19] - wire lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 129:19] - wire lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 129:19] - wire lsu_io_axi_aw_ready; // @[quasar.scala 129:19] - wire lsu_io_axi_aw_valid; // @[quasar.scala 129:19] - wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 129:19] - wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 129:19] - wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 129:19] - wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 129:19] - wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 129:19] - wire lsu_io_axi_w_ready; // @[quasar.scala 129:19] - wire lsu_io_axi_w_valid; // @[quasar.scala 129:19] - wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 129:19] - wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 129:19] - wire lsu_io_axi_b_valid; // @[quasar.scala 129:19] - wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 129:19] - wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 129:19] - wire lsu_io_axi_ar_ready; // @[quasar.scala 129:19] - wire lsu_io_axi_ar_valid; // @[quasar.scala 129:19] - wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 129:19] - wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 129:19] - wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 129:19] - wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 129:19] - wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 129:19] - wire lsu_io_axi_r_valid; // @[quasar.scala 129:19] - wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 129:19] - wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 129:19] - wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 129:19] - wire lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 129:19] - wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 129:19] - wire lsu_io_dec_tlu_force_halt; // @[quasar.scala 129:19] - wire lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 129:19] - wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 129:19] - wire lsu_io_lsu_p_valid; // @[quasar.scala 129:19] - wire lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 129:19] - wire lsu_io_lsu_p_bits_by; // @[quasar.scala 129:19] - wire lsu_io_lsu_p_bits_half; // @[quasar.scala 129:19] - wire lsu_io_lsu_p_bits_word; // @[quasar.scala 129:19] - wire lsu_io_lsu_p_bits_load; // @[quasar.scala 129:19] - wire lsu_io_lsu_p_bits_store; // @[quasar.scala 129:19] - wire lsu_io_lsu_p_bits_unsign; // @[quasar.scala 129:19] - wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 129:19] - wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 129:19] - wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 129:19] - wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 129:19] - wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 129:19] - wire lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 129:19] - wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 129:19] - wire lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 129:19] - wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 129:19] - wire lsu_io_lsu_load_stall_any; // @[quasar.scala 129:19] - wire lsu_io_lsu_store_stall_any; // @[quasar.scala 129:19] - wire lsu_io_lsu_fastint_stall_any; // @[quasar.scala 129:19] - wire lsu_io_lsu_idle_any; // @[quasar.scala 129:19] - wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 129:19] - wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 129:19] - wire lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 129:19] - wire lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 129:19] - wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 129:19] - wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 129:19] - wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 129:19] - wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 129:19] - wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 129:19] - wire lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 129:19] - wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 129:19] - wire lsu_io_lsu_bus_clk_en; // @[quasar.scala 129:19] - wire lsu_io_scan_mode; // @[quasar.scala 129:19] - wire lsu_io_free_clk; // @[quasar.scala 129:19] - wire pic_ctrl_inst_clock; // @[quasar.scala 130:29] - wire pic_ctrl_inst_reset; // @[quasar.scala 130:29] - wire pic_ctrl_inst_io_scan_mode; // @[quasar.scala 130:29] - wire pic_ctrl_inst_io_free_clk; // @[quasar.scala 130:29] - wire pic_ctrl_inst_io_active_clk; // @[quasar.scala 130:29] - wire pic_ctrl_inst_io_clk_override; // @[quasar.scala 130:29] - wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 130:29] - wire pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 130:29] - wire pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 130:29] - wire pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 130:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 130:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 130:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 130:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 130:29] - wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 130:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 130:29] - wire pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 130:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 130:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 130:29] - wire pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 130:29] - wire dma_ctrl_clock; // @[quasar.scala 131:24] - wire dma_ctrl_reset; // @[quasar.scala 131:24] - wire dma_ctrl_io_free_clk; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 131:24] - wire dma_ctrl_io_clk_override; // @[quasar.scala 131:24] - wire dma_ctrl_io_scan_mode; // @[quasar.scala 131:24] - wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 131:24] - wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 131:24] - wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 131:24] - wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 131:24] - wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 131:24] - wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 131:24] - wire [31:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 131:24] - wire dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 131:24] - wire dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 131:24] - wire dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 131:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 131:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 131:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 131:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 131:24] - wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 131:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 131:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 131:24] - wire dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 131:24] - wire dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 131:24] - wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 131:24] - wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 131:24] - wire dma_ctrl_io_iccm_ready; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 131:24] - wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 131:24] - wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 131:24] - wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 131:24] - wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 131:24] - wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 131:24] - wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 131:24] - wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 131:24] - wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 131:24] - wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 131:24] - wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 131:24] - wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 131:24] - wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 131:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 131:24] - wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 131:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 131:24] - wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 131:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 131:24] - wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 131:24] - wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 131:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 131:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 131:24] - wire dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 131:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 131:24] - wire dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 131:24] - wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 131:24] - wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 131:24] - wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 131:24] - wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 131:24] - wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 131:24] - wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 131:24] + wire ifu_clock; // @[quasar.scala 72:19] + wire ifu_reset; // @[quasar.scala 72:19] + wire ifu_io_exu_flush_final; // @[quasar.scala 72:19] + wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 72:19] + wire ifu_io_free_clk; // @[quasar.scala 72:19] + wire ifu_io_active_clk; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 72:19] + wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 72:19] + wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 72:19] + wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 72:19] + wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 72:19] + wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 72:19] + wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 72:19] + wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 72:19] + wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 72:19] + wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 72:19] + wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 72:19] + wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 72:19] + wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 72:19] + wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 72:19] + wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 72:19] + wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 72:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 72:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 72:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 72:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 72:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 72:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 72:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 72:19] + wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 72:19] + wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 72:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 72:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 72:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 72:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 72:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 72:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 72:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 72:19] + wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 72:19] + wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 72:19] + wire ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 72:19] + wire ifu_io_iccm_correction_state; // @[quasar.scala 72:19] + wire ifu_io_iccm_wren; // @[quasar.scala 72:19] + wire ifu_io_iccm_rden; // @[quasar.scala 72:19] + wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 72:19] + wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 72:19] + wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 72:19] + wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 72:19] + wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 72:19] + wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 72:19] + wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 72:19] + wire ifu_io_ic_rd_en; // @[quasar.scala 72:19] + wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 72:19] + wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 72:19] + wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 72:19] + wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 72:19] + wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 72:19] + wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 72:19] + wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 72:19] + wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 72:19] + wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 72:19] + wire ifu_io_ic_tag_perr; // @[quasar.scala 72:19] + wire ifu_io_ic_debug_rd_en; // @[quasar.scala 72:19] + wire ifu_io_ic_debug_wr_en; // @[quasar.scala 72:19] + wire ifu_io_ic_debug_tag_array; // @[quasar.scala 72:19] + wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 72:19] + wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 72:19] + wire ifu_io_ic_sel_premux_data; // @[quasar.scala 72:19] + wire ifu_io_ifu_ar_ready; // @[quasar.scala 72:19] + wire ifu_io_ifu_ar_valid; // @[quasar.scala 72:19] + wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 72:19] + wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 72:19] + wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 72:19] + wire ifu_io_ifu_r_valid; // @[quasar.scala 72:19] + wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 72:19] + wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 72:19] + wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 72:19] + wire ifu_io_ifu_bus_clk_en; // @[quasar.scala 72:19] + wire ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 72:19] + wire ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 72:19] + wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 72:19] + wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 72:19] + wire ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 72:19] + wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 72:19] + wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 72:19] + wire ifu_io_iccm_dma_ecc_error; // @[quasar.scala 72:19] + wire ifu_io_iccm_dma_rvalid; // @[quasar.scala 72:19] + wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 72:19] + wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 72:19] + wire ifu_io_iccm_ready; // @[quasar.scala 72:19] + wire ifu_io_iccm_dma_sb_error; // @[quasar.scala 72:19] + wire ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 72:19] + wire ifu_io_scan_mode; // @[quasar.scala 72:19] + wire dec_clock; // @[quasar.scala 73:19] + wire dec_reset; // @[quasar.scala 73:19] + wire dec_io_free_clk; // @[quasar.scala 73:19] + wire dec_io_active_clk; // @[quasar.scala 73:19] + wire dec_io_lsu_fastint_stall_any; // @[quasar.scala 73:19] + wire dec_io_dec_pause_state_cg; // @[quasar.scala 73:19] + wire [30:0] dec_io_rst_vec; // @[quasar.scala 73:19] + wire dec_io_nmi_int; // @[quasar.scala 73:19] + wire [30:0] dec_io_nmi_vec; // @[quasar.scala 73:19] + wire dec_io_i_cpu_halt_req; // @[quasar.scala 73:19] + wire dec_io_i_cpu_run_req; // @[quasar.scala 73:19] + wire dec_io_o_cpu_halt_status; // @[quasar.scala 73:19] + wire dec_io_o_cpu_halt_ack; // @[quasar.scala 73:19] + wire dec_io_o_cpu_run_ack; // @[quasar.scala 73:19] + wire dec_io_o_debug_mode_status; // @[quasar.scala 73:19] + wire [27:0] dec_io_core_id; // @[quasar.scala 73:19] + wire dec_io_mpc_debug_halt_req; // @[quasar.scala 73:19] + wire dec_io_mpc_debug_run_req; // @[quasar.scala 73:19] + wire dec_io_mpc_reset_run_req; // @[quasar.scala 73:19] + wire dec_io_mpc_debug_halt_ack; // @[quasar.scala 73:19] + wire dec_io_mpc_debug_run_ack; // @[quasar.scala 73:19] + wire dec_io_debug_brkpt_status; // @[quasar.scala 73:19] + wire dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 73:19] + wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 73:19] + wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 73:19] + wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 73:19] + wire dec_io_lsu_idle_any; // @[quasar.scala 73:19] + wire dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 73:19] + wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 73:19] + wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 73:19] + wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 73:19] + wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 73:19] + wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 73:19] + wire dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 73:19] + wire [31:0] dec_io_exu_div_result; // @[quasar.scala 73:19] + wire dec_io_exu_div_wren; // @[quasar.scala 73:19] + wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 73:19] + wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 73:19] + wire dec_io_lsu_load_stall_any; // @[quasar.scala 73:19] + wire dec_io_lsu_store_stall_any; // @[quasar.scala 73:19] + wire dec_io_iccm_dma_sb_error; // @[quasar.scala 73:19] + wire dec_io_exu_flush_final; // @[quasar.scala 73:19] + wire dec_io_timer_int; // @[quasar.scala 73:19] + wire dec_io_soft_int; // @[quasar.scala 73:19] + wire dec_io_dbg_halt_req; // @[quasar.scala 73:19] + wire dec_io_dbg_resume_req; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 73:19] + wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 73:19] + wire dec_io_dec_dbg_cmd_done; // @[quasar.scala 73:19] + wire dec_io_dec_dbg_cmd_fail; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_0_select; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_0_store; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_0_load; // @[quasar.scala 73:19] + wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_1_select; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_1_store; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_1_load; // @[quasar.scala 73:19] + wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_2_select; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_2_store; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_2_load; // @[quasar.scala 73:19] + wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_3_select; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_3_store; // @[quasar.scala 73:19] + wire dec_io_trigger_pkt_any_3_load; // @[quasar.scala 73:19] + wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 73:19] + wire dec_io_exu_i0_br_way_r; // @[quasar.scala 73:19] + wire dec_io_lsu_p_valid; // @[quasar.scala 73:19] + wire dec_io_lsu_p_bits_fast_int; // @[quasar.scala 73:19] + wire dec_io_lsu_p_bits_by; // @[quasar.scala 73:19] + wire dec_io_lsu_p_bits_half; // @[quasar.scala 73:19] + wire dec_io_lsu_p_bits_word; // @[quasar.scala 73:19] + wire dec_io_lsu_p_bits_load; // @[quasar.scala 73:19] + wire dec_io_lsu_p_bits_store; // @[quasar.scala 73:19] + wire dec_io_lsu_p_bits_unsign; // @[quasar.scala 73:19] + wire dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 73:19] + wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 73:19] + wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_perfcnt0; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_perfcnt1; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_perfcnt2; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_perfcnt3; // @[quasar.scala 73:19] + wire dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 73:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 73:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 73:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 73:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 73:19] + wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 73:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 73:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 73:19] + wire dec_io_scan_mode; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 73:19] + wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 73:19] + wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 73:19] + wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 73:19] + wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 73:19] + wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 73:19] + wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 73:19] + wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 73:19] + wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 73:19] + wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 73:19] + wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 73:19] + wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 73:19] + wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 73:19] + wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 73:19] + wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 73:19] + wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 73:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 73:19] + wire dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 73:19] + wire dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 73:19] + wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 73:19] + wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 73:19] + wire dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 73:19] + wire dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 73:19] + wire dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 73:19] + wire dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 73:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 73:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 73:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 73:19] + wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 73:19] + wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 73:19] + wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 73:19] + wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 73:19] + wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 73:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 73:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 73:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 73:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 73:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 73:19] + wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 73:19] + wire dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 73:19] + wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 73:19] + wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 73:19] + wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 73:19] + wire dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 73:19] + wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 73:19] + wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 73:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 73:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 73:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 73:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 73:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 73:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 73:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 73:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 73:19] + wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 73:19] + wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 73:19] + wire dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 73:19] + wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 73:19] + wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 73:19] + wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 73:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 73:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 73:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 73:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 73:19] + wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 73:19] + wire dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 73:19] + wire dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 73:19] + wire dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 73:19] + wire dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 73:19] + wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 73:19] + wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 73:19] + wire [31:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 73:19] + wire dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 73:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 73:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 73:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 73:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 73:19] + wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 73:19] + wire dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 73:19] + wire dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 73:19] + wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 73:19] + wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 73:19] + wire dec_io_dec_pic_mhwakeup; // @[quasar.scala 73:19] + wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 73:19] + wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 73:19] + wire dec_io_dec_pic_mexintpend; // @[quasar.scala 73:19] + wire dbg_clock; // @[quasar.scala 74:19] + wire dbg_reset; // @[quasar.scala 74:19] + wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 74:19] + wire dbg_io_dbg_core_rst_l; // @[quasar.scala 74:19] + wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 74:19] + wire dbg_io_core_dbg_cmd_done; // @[quasar.scala 74:19] + wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 74:19] + wire dbg_io_dbg_halt_req; // @[quasar.scala 74:19] + wire dbg_io_dbg_resume_req; // @[quasar.scala 74:19] + wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 74:19] + wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 74:19] + wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 74:19] + wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 74:19] + wire dbg_io_dmi_reg_en; // @[quasar.scala 74:19] + wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 74:19] + wire dbg_io_dmi_reg_wr_en; // @[quasar.scala 74:19] + wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 74:19] + wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 74:19] + wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 74:19] + wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 74:19] + wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 74:19] + wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 74:19] + wire dbg_io_sb_axi_w_ready; // @[quasar.scala 74:19] + wire dbg_io_sb_axi_w_valid; // @[quasar.scala 74:19] + wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 74:19] + wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 74:19] + wire dbg_io_sb_axi_b_ready; // @[quasar.scala 74:19] + wire dbg_io_sb_axi_b_valid; // @[quasar.scala 74:19] + wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 74:19] + wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 74:19] + wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 74:19] + wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 74:19] + wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 74:19] + wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 74:19] + wire dbg_io_sb_axi_r_ready; // @[quasar.scala 74:19] + wire dbg_io_sb_axi_r_valid; // @[quasar.scala 74:19] + wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 74:19] + wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 74:19] + wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 74:19] + wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 74:19] + wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 74:19] + wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 74:19] + wire [31:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 74:19] + wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 74:19] + wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 74:19] + wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 74:19] + wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 74:19] + wire [31:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 74:19] + wire dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 74:19] + wire dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 74:19] + wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 74:19] + wire dbg_io_dbg_rst_l; // @[quasar.scala 74:19] + wire dbg_io_clk_override; // @[quasar.scala 74:19] + wire dbg_io_scan_mode; // @[quasar.scala 74:19] + wire exu_clock; // @[quasar.scala 75:19] + wire exu_reset; // @[quasar.scala 75:19] + wire exu_io_scan_mode; // @[quasar.scala 75:19] + wire exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 75:19] + wire exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 75:19] + wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 75:19] + wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 75:19] + wire exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 75:19] + wire exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 75:19] + wire exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 75:19] + wire exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 75:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 75:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 75:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 75:19] + wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 75:19] + wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 75:19] + wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 75:19] + wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 75:19] + wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 75:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 75:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 75:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 75:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 75:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 75:19] + wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 75:19] + wire exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 75:19] + wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 75:19] + wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 75:19] + wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 75:19] + wire exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 75:19] + wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 75:19] + wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 75:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 75:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 75:19] + wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 75:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 75:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 75:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 75:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 75:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 75:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 75:19] + wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 75:19] + wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 75:19] + wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 75:19] + wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 75:19] + wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 75:19] + wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 75:19] + wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 75:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 75:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 75:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 75:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 75:19] + wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 75:19] + wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 75:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 75:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 75:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 75:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 75:19] + wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 75:19] + wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 75:19] + wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 75:19] + wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 75:19] + wire exu_io_exu_flush_final; // @[quasar.scala 75:19] + wire [31:0] exu_io_exu_div_result; // @[quasar.scala 75:19] + wire exu_io_exu_div_wren; // @[quasar.scala 75:19] + wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 75:19] + wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 75:19] + wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 75:19] + wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 75:19] + wire lsu_clock; // @[quasar.scala 76:19] + wire lsu_reset; // @[quasar.scala 76:19] + wire lsu_io_clk_override; // @[quasar.scala 76:19] + wire lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 76:19] + wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 76:19] + wire lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 76:19] + wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 76:19] + wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 76:19] + wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 76:19] + wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 76:19] + wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 76:19] + wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 76:19] + wire lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 76:19] + wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 76:19] + wire lsu_io_lsu_pic_picm_wren; // @[quasar.scala 76:19] + wire lsu_io_lsu_pic_picm_rden; // @[quasar.scala 76:19] + wire lsu_io_lsu_pic_picm_mken; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 76:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 76:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 76:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 76:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 76:19] + wire lsu_io_dccm_wren; // @[quasar.scala 76:19] + wire lsu_io_dccm_rden; // @[quasar.scala 76:19] + wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 76:19] + wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 76:19] + wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 76:19] + wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 76:19] + wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 76:19] + wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 76:19] + wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 76:19] + wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 76:19] + wire lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 76:19] + wire lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 76:19] + wire lsu_io_axi_aw_ready; // @[quasar.scala 76:19] + wire lsu_io_axi_aw_valid; // @[quasar.scala 76:19] + wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 76:19] + wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 76:19] + wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 76:19] + wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 76:19] + wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 76:19] + wire lsu_io_axi_w_ready; // @[quasar.scala 76:19] + wire lsu_io_axi_w_valid; // @[quasar.scala 76:19] + wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 76:19] + wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 76:19] + wire lsu_io_axi_b_valid; // @[quasar.scala 76:19] + wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 76:19] + wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 76:19] + wire lsu_io_axi_ar_ready; // @[quasar.scala 76:19] + wire lsu_io_axi_ar_valid; // @[quasar.scala 76:19] + wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 76:19] + wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 76:19] + wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 76:19] + wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 76:19] + wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 76:19] + wire lsu_io_axi_r_valid; // @[quasar.scala 76:19] + wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 76:19] + wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 76:19] + wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 76:19] + wire lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 76:19] + wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 76:19] + wire lsu_io_dec_tlu_force_halt; // @[quasar.scala 76:19] + wire lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 76:19] + wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 76:19] + wire lsu_io_lsu_p_valid; // @[quasar.scala 76:19] + wire lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 76:19] + wire lsu_io_lsu_p_bits_by; // @[quasar.scala 76:19] + wire lsu_io_lsu_p_bits_half; // @[quasar.scala 76:19] + wire lsu_io_lsu_p_bits_word; // @[quasar.scala 76:19] + wire lsu_io_lsu_p_bits_load; // @[quasar.scala 76:19] + wire lsu_io_lsu_p_bits_store; // @[quasar.scala 76:19] + wire lsu_io_lsu_p_bits_unsign; // @[quasar.scala 76:19] + wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 76:19] + wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 76:19] + wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 76:19] + wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 76:19] + wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 76:19] + wire lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 76:19] + wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 76:19] + wire lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 76:19] + wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 76:19] + wire lsu_io_lsu_load_stall_any; // @[quasar.scala 76:19] + wire lsu_io_lsu_store_stall_any; // @[quasar.scala 76:19] + wire lsu_io_lsu_fastint_stall_any; // @[quasar.scala 76:19] + wire lsu_io_lsu_idle_any; // @[quasar.scala 76:19] + wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 76:19] + wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 76:19] + wire lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 76:19] + wire lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 76:19] + wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 76:19] + wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 76:19] + wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 76:19] + wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 76:19] + wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 76:19] + wire lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 76:19] + wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 76:19] + wire lsu_io_lsu_bus_clk_en; // @[quasar.scala 76:19] + wire lsu_io_scan_mode; // @[quasar.scala 76:19] + wire lsu_io_free_clk; // @[quasar.scala 76:19] + wire pic_ctrl_inst_clock; // @[quasar.scala 77:29] + wire pic_ctrl_inst_reset; // @[quasar.scala 77:29] + wire pic_ctrl_inst_io_scan_mode; // @[quasar.scala 77:29] + wire pic_ctrl_inst_io_free_clk; // @[quasar.scala 77:29] + wire pic_ctrl_inst_io_active_clk; // @[quasar.scala 77:29] + wire pic_ctrl_inst_io_clk_override; // @[quasar.scala 77:29] + wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 77:29] + wire pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 77:29] + wire pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 77:29] + wire pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 77:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 77:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 77:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 77:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 77:29] + wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 77:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 77:29] + wire pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 77:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 77:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 77:29] + wire pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 77:29] + wire dma_ctrl_clock; // @[quasar.scala 78:24] + wire dma_ctrl_reset; // @[quasar.scala 78:24] + wire dma_ctrl_io_free_clk; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 78:24] + wire dma_ctrl_io_clk_override; // @[quasar.scala 78:24] + wire dma_ctrl_io_scan_mode; // @[quasar.scala 78:24] + wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 78:24] + wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 78:24] + wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 78:24] + wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 78:24] + wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 78:24] + wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 78:24] + wire [31:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 78:24] + wire dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 78:24] + wire dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 78:24] + wire dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 78:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 78:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 78:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 78:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 78:24] + wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 78:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 78:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 78:24] + wire dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 78:24] + wire dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 78:24] + wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 78:24] + wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 78:24] + wire dma_ctrl_io_iccm_ready; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 78:24] + wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 78:24] + wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 78:24] + wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 78:24] + wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 78:24] + wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 78:24] + wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 78:24] + wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 78:24] + wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 78:24] + wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 78:24] + wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 78:24] + wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 78:24] + wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 78:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 78:24] + wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 78:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 78:24] + wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 78:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 78:24] + wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 78:24] + wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 78:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 78:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 78:24] + wire dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 78:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 78:24] + wire dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 78:24] + wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 78:24] + wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 78:24] + wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 78:24] + wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 78:24] + wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 78:24] + wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 78:24] wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] wire rvclkhdr_io_clk; // @[lib.scala 343:22] wire rvclkhdr_io_en; // @[lib.scala 343:22] @@ -82106,58 +81466,11 @@ module quasar( wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] wire rvclkhdr_1_io_en; // @[lib.scala 343:22] wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire axi4_to_ahb_clock; // @[quasar.scala 306:33] - wire axi4_to_ahb_reset; // @[quasar.scala 306:33] - wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 306:33] - wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 306:33] - wire axi4_to_ahb_io_clk_override; // @[quasar.scala 306:33] - wire axi4_to_ahb_io_axi_awvalid; // @[quasar.scala 306:33] - wire axi4_to_ahb_io_axi_wvalid; // @[quasar.scala 306:33] - wire axi4_to_ahb_io_axi_bready; // @[quasar.scala 306:33] - wire axi4_to_ahb_io_axi_arvalid; // @[quasar.scala 306:33] - wire axi4_to_ahb_io_axi_rready; // @[quasar.scala 306:33] - wire axi4_to_ahb_io_axi_awready; // @[quasar.scala 306:33] - wire axi4_to_ahb_io_axi_wready; // @[quasar.scala 306:33] - wire axi4_to_ahb_1_clock; // @[quasar.scala 333:33] - wire axi4_to_ahb_1_reset; // @[quasar.scala 333:33] - wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 333:33] - wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 333:33] - wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 333:33] - wire axi4_to_ahb_1_io_axi_awvalid; // @[quasar.scala 333:33] - wire axi4_to_ahb_1_io_axi_wvalid; // @[quasar.scala 333:33] - wire axi4_to_ahb_1_io_axi_bready; // @[quasar.scala 333:33] - wire axi4_to_ahb_1_io_axi_arvalid; // @[quasar.scala 333:33] - wire axi4_to_ahb_1_io_axi_rready; // @[quasar.scala 333:33] - wire axi4_to_ahb_1_io_axi_awready; // @[quasar.scala 333:33] - wire axi4_to_ahb_1_io_axi_wready; // @[quasar.scala 333:33] - wire axi4_to_ahb_2_clock; // @[quasar.scala 361:32] - wire axi4_to_ahb_2_reset; // @[quasar.scala 361:32] - wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 361:32] - wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 361:32] - wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 361:32] - wire axi4_to_ahb_2_io_axi_awvalid; // @[quasar.scala 361:32] - wire axi4_to_ahb_2_io_axi_wvalid; // @[quasar.scala 361:32] - wire axi4_to_ahb_2_io_axi_bready; // @[quasar.scala 361:32] - wire axi4_to_ahb_2_io_axi_arvalid; // @[quasar.scala 361:32] - wire axi4_to_ahb_2_io_axi_rready; // @[quasar.scala 361:32] - wire axi4_to_ahb_2_io_axi_awready; // @[quasar.scala 361:32] - wire axi4_to_ahb_2_io_axi_wready; // @[quasar.scala 361:32] - wire ahb_to_axi4_clock; // @[quasar.scala 388:33] - wire ahb_to_axi4_reset; // @[quasar.scala 388:33] - wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 388:33] - wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 388:33] - wire ahb_to_axi4_io_axi_awready; // @[quasar.scala 388:33] - wire ahb_to_axi4_io_axi_arready; // @[quasar.scala 388:33] - wire ahb_to_axi4_io_axi_rvalid; // @[quasar.scala 388:33] - wire [1:0] ahb_to_axi4_io_axi_rresp; // @[quasar.scala 388:33] - wire ahb_to_axi4_io_axi_awvalid; // @[quasar.scala 388:33] - wire ahb_to_axi4_io_axi_arvalid; // @[quasar.scala 388:33] - wire ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 388:33] - wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 133:67] - wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 133:70] - wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 134:23] - wire _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 134:50] - ifu ifu ( // @[quasar.scala 125:19] + wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 80:67] + wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 80:70] + wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 81:23] + wire _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 81:50] + ifu ifu ( // @[quasar.scala 72:19] .clock(ifu_clock), .reset(ifu_reset), .io_exu_flush_final(ifu_io_exu_flush_final), @@ -82287,7 +81600,7 @@ module quasar( .io_dec_tlu_flush_lower_wb(ifu_io_dec_tlu_flush_lower_wb), .io_scan_mode(ifu_io_scan_mode) ); - dec dec ( // @[quasar.scala 126:19] + dec dec ( // @[quasar.scala 73:19] .clock(dec_clock), .reset(dec_reset), .io_free_clk(dec_io_free_clk), @@ -82388,7 +81701,6 @@ module quasar( .io_rv_trace_pkt_rv_i_tval_ip(dec_io_rv_trace_pkt_rv_i_tval_ip), .io_dec_tlu_misc_clk_override(dec_io_dec_tlu_misc_clk_override), .io_dec_tlu_lsu_clk_override(dec_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(dec_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(dec_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(dec_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(dec_io_dec_tlu_icm_clk_override), @@ -82561,7 +81873,7 @@ module quasar( .io_dec_pic_dec_tlu_meipt(dec_io_dec_pic_dec_tlu_meipt), .io_dec_pic_mexintpend(dec_io_dec_pic_mexintpend) ); - dbg dbg ( // @[quasar.scala 127:19] + dbg dbg ( // @[quasar.scala 74:19] .clock(dbg_clock), .reset(dbg_reset), .io_dbg_cmd_size(dbg_io_dbg_cmd_size), @@ -82617,7 +81929,7 @@ module quasar( .io_clk_override(dbg_io_clk_override), .io_scan_mode(dbg_io_scan_mode) ); - exu exu ( // @[quasar.scala 128:19] + exu exu ( // @[quasar.scala 75:19] .clock(exu_clock), .reset(exu_reset), .io_scan_mode(exu_io_scan_mode), @@ -82722,7 +82034,7 @@ module quasar( .io_lsu_exu_exu_lsu_rs2_d(exu_io_lsu_exu_exu_lsu_rs2_d), .io_exu_flush_path_final(exu_io_exu_flush_path_final) ); - lsu lsu ( // @[quasar.scala 129:19] + lsu lsu ( // @[quasar.scala 76:19] .clock(lsu_clock), .reset(lsu_reset), .io_clk_override(lsu_io_clk_override), @@ -82861,7 +82173,7 @@ module quasar( .io_scan_mode(lsu_io_scan_mode), .io_free_clk(lsu_io_free_clk) ); - pic_ctrl pic_ctrl_inst ( // @[quasar.scala 130:29] + pic_ctrl pic_ctrl_inst ( // @[quasar.scala 77:29] .clock(pic_ctrl_inst_clock), .reset(pic_ctrl_inst_reset), .io_scan_mode(pic_ctrl_inst_io_scan_mode), @@ -82883,7 +82195,7 @@ module quasar( .io_dec_pic_dec_tlu_meipt(pic_ctrl_inst_io_dec_pic_dec_tlu_meipt), .io_dec_pic_mexintpend(pic_ctrl_inst_io_dec_pic_mexintpend) ); - dma_ctrl dma_ctrl ( // @[quasar.scala 131:24] + dma_ctrl dma_ctrl ( // @[quasar.scala 78:24] .clock(dma_ctrl_clock), .reset(dma_ctrl_reset), .io_free_clk(dma_ctrl_io_free_clk), @@ -82970,601 +82282,500 @@ module quasar( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 306:33] - .clock(axi4_to_ahb_clock), - .reset(axi4_to_ahb_reset), - .io_scan_mode(axi4_to_ahb_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_io_clk_override), - .io_axi_awvalid(axi4_to_ahb_io_axi_awvalid), - .io_axi_wvalid(axi4_to_ahb_io_axi_wvalid), - .io_axi_bready(axi4_to_ahb_io_axi_bready), - .io_axi_arvalid(axi4_to_ahb_io_axi_arvalid), - .io_axi_rready(axi4_to_ahb_io_axi_rready), - .io_axi_awready(axi4_to_ahb_io_axi_awready), - .io_axi_wready(axi4_to_ahb_io_axi_wready) - ); - axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 333:33] - .clock(axi4_to_ahb_1_clock), - .reset(axi4_to_ahb_1_reset), - .io_scan_mode(axi4_to_ahb_1_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_1_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_1_io_clk_override), - .io_axi_awvalid(axi4_to_ahb_1_io_axi_awvalid), - .io_axi_wvalid(axi4_to_ahb_1_io_axi_wvalid), - .io_axi_bready(axi4_to_ahb_1_io_axi_bready), - .io_axi_arvalid(axi4_to_ahb_1_io_axi_arvalid), - .io_axi_rready(axi4_to_ahb_1_io_axi_rready), - .io_axi_awready(axi4_to_ahb_1_io_axi_awready), - .io_axi_wready(axi4_to_ahb_1_io_axi_wready) - ); - axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 361:32] - .clock(axi4_to_ahb_2_clock), - .reset(axi4_to_ahb_2_reset), - .io_scan_mode(axi4_to_ahb_2_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_2_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_2_io_clk_override), - .io_axi_awvalid(axi4_to_ahb_2_io_axi_awvalid), - .io_axi_wvalid(axi4_to_ahb_2_io_axi_wvalid), - .io_axi_bready(axi4_to_ahb_2_io_axi_bready), - .io_axi_arvalid(axi4_to_ahb_2_io_axi_arvalid), - .io_axi_rready(axi4_to_ahb_2_io_axi_rready), - .io_axi_awready(axi4_to_ahb_2_io_axi_awready), - .io_axi_wready(axi4_to_ahb_2_io_axi_wready) - ); - ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 388:33] - .clock(ahb_to_axi4_clock), - .reset(ahb_to_axi4_reset), - .io_scan_mode(ahb_to_axi4_io_scan_mode), - .io_bus_clk_en(ahb_to_axi4_io_bus_clk_en), - .io_axi_awready(ahb_to_axi4_io_axi_awready), - .io_axi_arready(ahb_to_axi4_io_axi_arready), - .io_axi_rvalid(ahb_to_axi4_io_axi_rvalid), - .io_axi_rresp(ahb_to_axi4_io_axi_rresp), - .io_axi_awvalid(ahb_to_axi4_io_axi_awvalid), - .io_axi_arvalid(ahb_to_axi4_io_axi_arvalid), - .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp) - ); - assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 295:14] - assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 295:14] - assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 295:14] - assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 295:14] - assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 295:14] - assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 295:14] - assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 295:14] - assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 295:14] - assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 295:14] - assign io_lsu_axi_b_ready = 1'h1; // @[quasar.scala 295:14] - assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 295:14] - assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 295:14] - assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 295:14] - assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 295:14] - assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 295:14] - assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 295:14] - assign io_lsu_axi_r_ready = 1'h1; // @[quasar.scala 295:14] - assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 298:14] - assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 298:14] - assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 298:14] - assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 298:14] - assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 298:14] - assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 298:14] - assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 298:14] - assign io_ifu_axi_r_ready = 1'h1; // @[quasar.scala 298:14] - assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 242:17] - assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 242:17] - assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 242:17] - assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 242:17] - assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 242:17] - assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 242:17] - assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 242:17] - assign io_sb_axi_b_ready = 1'h1; // @[quasar.scala 242:17] - assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 242:17] - assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 242:17] - assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 242:17] - assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 242:17] - assign io_sb_axi_r_ready = 1'h1; // @[quasar.scala 242:17] - assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 299:14] - assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 299:14] - assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 299:14] - assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 299:14] - assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 299:14] - assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 299:14] - assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 299:14] - assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 299:14] - assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 299:14] - assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 299:14] - assign io_core_rst_l = reset & _T_2; // @[quasar.scala 133:17] - assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 274:19] - assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 274:19] - assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 274:19] - assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 274:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 274:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 274:19] - assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 274:19] - assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 277:24] - assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 278:23] - assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 279:31] - assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 280:21] - assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 281:24] - assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 282:20] - assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 283:26] - assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 284:25] - assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 285:24] - assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 286:25] - assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 287:23] - assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 288:23] - assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 289:23] - assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 290:23] - assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 292:11] - assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 292:11] - assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 292:11] - assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 292:11] - assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 292:11] - assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 292:11] - assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 292:11] - assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 292:11] - assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 154:13] - assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 154:13] - assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 154:13] - assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 154:13] - assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 154:13] - assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 154:13] - assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 154:13] - assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 154:13] - assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 154:13] - assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 154:13] - assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 154:13] - assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 154:13] - assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 154:13] - assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 154:13] - assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 155:15] - assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 155:15] - assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 155:15] - assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 155:15] - assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 155:15] - assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 155:15] - assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 155:15] + assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 242:14] + assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 242:14] + assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 242:14] + assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 242:14] + assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 242:14] + assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 242:14] + assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 242:14] + assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 242:14] + assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 242:14] + assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 242:14] + assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 242:14] + assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 242:14] + assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 242:14] + assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 242:14] + assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 242:14] + assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 245:14] + assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 245:14] + assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 245:14] + assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 245:14] + assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 189:17] + assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 189:17] + assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 189:17] + assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 189:17] + assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 189:17] + assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 189:17] + assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 189:17] + assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 189:17] + assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 189:17] + assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 189:17] + assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 189:17] + assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 246:14] + assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 246:14] + assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 246:14] + assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 246:14] + assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 246:14] + assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 246:14] + assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 246:14] + assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 246:14] + assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 246:14] + assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 246:14] + assign io_core_rst_l = reset & _T_2; // @[quasar.scala 80:17] + assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 221:19] + assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 221:19] + assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 221:19] + assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 221:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 221:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 221:19] + assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 221:19] + assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 224:24] + assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 225:23] + assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 226:31] + assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 227:21] + assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 228:24] + assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 229:20] + assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 230:26] + assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 231:25] + assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 232:24] + assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 233:25] + assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 234:23] + assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 235:23] + assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 236:23] + assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 237:23] + assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 239:11] + assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 239:11] + assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 239:11] + assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 239:11] + assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 239:11] + assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 239:11] + assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 239:11] + assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 239:11] + assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 101:13] + assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 101:13] + assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 101:13] + assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 101:13] + assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 101:13] + assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 101:13] + assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 101:13] + assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 101:13] + assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 101:13] + assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 101:13] + assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 101:13] + assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 101:13] + assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 101:13] + assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 101:13] + assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 102:15] + assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 102:15] + assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 102:15] + assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 102:15] + assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 102:15] + assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 102:15] + assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 102:15] assign ifu_clock = clock; - assign ifu_reset = io_core_rst_l; // @[quasar.scala 144:13] - assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 149:26] - assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 150:31] - assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 146:19] - assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 147:21] - assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 142:18 quasar.scala 160:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 142:18 quasar.scala 160:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 142:18 quasar.scala 160:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 142:18 quasar.scala 160:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 142:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 142:18] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 156:25 quasar.scala 158:43] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 156:25 quasar.scala 157:42] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 156:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 156:25] - assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 155:15] - assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 155:15] - assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 154:13] - assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 154:13] - assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 154:13] - assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 154:13] - assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 154:13] - assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 154:13] - assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 298:14 quasar.scala 430:25] - assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 298:14 quasar.scala 431:24] - assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 298:14 quasar.scala 432:26] - assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 298:14 quasar.scala 433:28] - assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 298:14 quasar.scala 434:28] - assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 152:25] - assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 153:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 153:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 153:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 153:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 153:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 153:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 153:18] - assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 159:33] - assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 145:20] + assign ifu_reset = io_core_rst_l; // @[quasar.scala 91:13] + assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 96:26] + assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 97:31] + assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 93:19] + assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 94:21] + assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 89:18 quasar.scala 107:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 89:18 quasar.scala 107:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 89:18 quasar.scala 107:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 89:18 quasar.scala 107:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 89:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 89:18] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 103:25 quasar.scala 105:43] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 103:25 quasar.scala 104:42] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 103:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 103:25] + assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 102:15] + assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 102:15] + assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 101:13] + assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 101:13] + assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 101:13] + assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 101:13] + assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 101:13] + assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 101:13] + assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 245:14] + assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 245:14] + assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 245:14] + assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 245:14] + assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 245:14] + assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 99:25] + assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 100:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 100:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 100:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 100:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 100:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 100:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 100:18] + assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 106:33] + assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 92:20] assign dec_clock = clock; - assign dec_reset = io_core_rst_l; // @[quasar.scala 163:13] - assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 164:19] - assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 165:21] - assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 166:32] - assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 167:18] - assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 168:18] - assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 169:18] - assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 170:25] - assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 171:24] - assign dec_io_core_id = io_core_id; // @[quasar.scala 172:18] - assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 173:29] - assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 174:28] - assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 175:28] - assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 178:31] - assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 181:23] - assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 182:24] - assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 183:30] - assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 185:23] - assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 186:26] - assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 186:26] - assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 186:26] - assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 186:26] - assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 186:26] - assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 186:26] - assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 187:36] - assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 188:25] - assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 189:23] - assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 190:23] - assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 191:28] - assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 192:29] - assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 193:30] - assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 194:28] - assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 195:26] - assign dec_io_timer_int = io_timer_int; // @[quasar.scala 201:20] - assign dec_io_soft_int = io_soft_int; // @[quasar.scala 197:19] - assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 198:23] - assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 199:25] - assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 200:26] - assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 202:20] - assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 142:18] - assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 142:18] - assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 205:18] - assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 205:18] - assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 205:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 205:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 205:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 205:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 205:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 205:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 205:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 205:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 205:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 205:18] - assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 205:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 176:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 176:18] - assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 177:18] - assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 177:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 184:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 184:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 184:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 184:18] - assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 184:18] - assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 179:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 179:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 179:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 179:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 179:18] - assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 179:18] - assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 179:18] - assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 272:28] - assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 272:28] - assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 272:28] - assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 272:28] + assign dec_reset = io_core_rst_l; // @[quasar.scala 110:13] + assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 111:19] + assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 112:21] + assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 113:32] + assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 114:18] + assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 115:18] + assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 116:18] + assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 117:25] + assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 118:24] + assign dec_io_core_id = io_core_id; // @[quasar.scala 119:18] + assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 120:29] + assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 121:28] + assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 122:28] + assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 125:31] + assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 128:23] + assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 129:24] + assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 130:30] + assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 132:23] + assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 133:26] + assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 133:26] + assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 133:26] + assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 133:26] + assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 133:26] + assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 133:26] + assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 134:36] + assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 135:25] + assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 136:23] + assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 137:23] + assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 138:28] + assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 139:29] + assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 140:30] + assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 141:28] + assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 142:26] + assign dec_io_timer_int = io_timer_int; // @[quasar.scala 148:20] + assign dec_io_soft_int = io_soft_int; // @[quasar.scala 144:19] + assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 145:23] + assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 146:25] + assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 147:26] + assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 149:20] + assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 89:18] + assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 89:18] + assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 152:18] + assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 152:18] + assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 152:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 152:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 152:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 152:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 152:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 152:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 152:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 152:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 152:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 152:18] + assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 152:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 123:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 123:18] + assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 124:18] + assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 124:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 131:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 131:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 131:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 131:18] + assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 131:18] + assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 126:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 126:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 126:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 126:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 126:18] + assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 126:18] + assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 126:18] + assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 219:28] + assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 219:28] + assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 219:28] + assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 219:28] assign dbg_clock = clock; - assign dbg_reset = io_core_rst_l; // @[quasar.scala 230:13] - assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 231:26] - assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 232:28] - assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 233:28] - assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 234:29] - assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 235:29] - assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 236:34] - assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 237:29] - assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 238:21] - assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 239:23] - assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 240:24] - assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 241:24] - assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 242:17 quasar.scala 437:28] - assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 242:17 quasar.scala 438:27] - assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 242:17 quasar.scala 439:27] - assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 242:17 quasar.scala 440:31] - assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 242:17 quasar.scala 441:28] - assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 242:17 quasar.scala 442:27] - assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 242:17 quasar.scala 444:31] - assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 242:17 quasar.scala 445:31] - assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 256:26] - assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 243:25] - assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 244:20] - assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 245:23] - assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 246:20] + assign dbg_reset = io_core_rst_l; // @[quasar.scala 177:13] + assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 178:26] + assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 179:28] + assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 180:28] + assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 181:29] + assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 182:29] + assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 183:34] + assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 184:29] + assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 185:21] + assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 186:23] + assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 187:24] + assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 188:24] + assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 189:17] + assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 189:17] + assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 189:17] + assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 189:17] + assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 189:17] + assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 189:17] + assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 189:17] + assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 189:17] + assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 203:26] + assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 190:25] + assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 191:20] + assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 192:23] + assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 193:20] assign exu_clock = clock; - assign exu_reset = io_core_rst_l; // @[quasar.scala 206:13] - assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 207:20] - assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 205:18] - assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 205:18] - assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 205:18] - assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 205:18] - assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 205:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 205:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 205:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 205:18] - assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 205:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 205:18] - assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 208:25] + assign exu_reset = io_core_rst_l; // @[quasar.scala 153:13] + assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 154:20] + assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 152:18] + assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 152:18] + assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 152:18] + assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 152:18] + assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 152:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 152:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 152:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 152:18] + assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 152:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 152:18] + assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 155:25] assign lsu_clock = clock; - assign lsu_reset = io_core_rst_l; // @[quasar.scala 211:13] - assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 212:23] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 225:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 225:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 225:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 225:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 225:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 225:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 225:18] - assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 225:18] - assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 271:28] - assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 217:18] - assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 217:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 176:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 176:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 176:18] - assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 292:11] - assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 292:11] - assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 295:14 quasar.scala 416:25] - assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 295:14 quasar.scala 417:24] - assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 295:14 quasar.scala 418:24] - assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 295:14 quasar.scala 419:28] - assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 295:14 quasar.scala 420:26] - assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 295:14 quasar.scala 421:25] - assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 295:14 quasar.scala 422:24] - assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 295:14 quasar.scala 423:26] - assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 295:14 quasar.scala 424:28] - assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 295:14 quasar.scala 425:28] - assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 213:32] - assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 214:35] - assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 215:29] - assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 216:35] - assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 218:27] - assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 219:16] - assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 219:16] - assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 219:16] - assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 219:16] - assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 219:16] - assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 219:16] - assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 219:16] - assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 219:16] - assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 219:16] - assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 219:16] - assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 222:26] - assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 222:26] - assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 220:30] - assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 221:26] - assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 224:25] - assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 226:20] - assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 227:19] + assign lsu_reset = io_core_rst_l; // @[quasar.scala 158:13] + assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 159:23] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 172:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 172:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 172:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 172:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 172:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 172:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 172:18] + assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 172:18] + assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 218:28] + assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 164:18] + assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 164:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 123:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 123:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 123:18] + assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 239:11] + assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 239:11] + assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 242:14] + assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 242:14] + assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 242:14] + assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 242:14] + assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 242:14] + assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 242:14] + assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 242:14] + assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 242:14] + assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 242:14] + assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 242:14] + assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 160:32] + assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 161:35] + assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 162:29] + assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 163:35] + assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 165:27] + assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 166:16] + assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 166:16] + assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 166:16] + assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 166:16] + assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 166:16] + assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 166:16] + assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 166:16] + assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 166:16] + assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 166:16] + assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 166:16] + assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 169:26] + assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 169:26] + assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 167:30] + assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 168:26] + assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 171:25] + assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 173:20] + assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 174:19] assign pic_ctrl_inst_clock = clock; - assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 266:23] - assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 265:30] - assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 267:29] - assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 268:31] - assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 269:33] - assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 270:34] - assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 271:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 271:28] - assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 271:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 271:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 271:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 271:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 272:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 272:28] + assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 213:23] + assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 212:30] + assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 214:29] + assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 215:31] + assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 216:33] + assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 217:34] + assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 218:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 218:28] + assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 218:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 218:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 218:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 218:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 219:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 219:28] assign dma_ctrl_clock = clock; - assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 250:18] - assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 251:24] - assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 252:30] - assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 253:28] - assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 254:25] - assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 257:28] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 255:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 255:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 255:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 255:23] - assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 255:23] - assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 256:26] - assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 179:18] - assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 258:31] - assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 262:34] - assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 259:29] - assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 260:30] - assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 261:26] - assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 299:14 quasar.scala 447:34] - assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 299:14 quasar.scala 448:36] - assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 299:14 quasar.scala 449:38] - assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 299:14 quasar.scala 450:38] - assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 299:14 quasar.scala 451:33] - assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 299:14 quasar.scala 452:37] - assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 299:14 quasar.scala 453:37] - assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 299:14 quasar.scala 454:33] - assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 299:14 quasar.scala 455:34] - assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 299:14 quasar.scala 456:36] - assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 299:14 quasar.scala 457:38] - assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 299:14 quasar.scala 458:38] - assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 299:14 quasar.scala 459:33] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 225:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 225:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 225:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 225:18] - assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 225:18] + assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 197:18] + assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 198:24] + assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 199:30] + assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 200:28] + assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 201:25] + assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 204:28] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 202:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 202:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 202:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 202:23] + assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 202:23] + assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 203:26] + assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 126:18] + assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 205:31] + assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 209:34] + assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 206:29] + assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 207:30] + assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 208:26] + assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 246:14] + assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 246:14] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 172:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 172:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 172:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 172:18] + assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 172:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = 1'h1; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_1_io_en = _T_6 | dec_io_dec_tlu_misc_clk_override; // @[lib.scala 345:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign axi4_to_ahb_clock = clock; - assign axi4_to_ahb_reset = reset; - assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 308:34] - assign axi4_to_ahb_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 309:35] - assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 310:37] - assign axi4_to_ahb_io_axi_awvalid = io_lsu_axi_aw_valid; // @[quasar.scala 307:36] - assign axi4_to_ahb_io_axi_wvalid = io_lsu_axi_w_valid; // @[quasar.scala 316:35] - assign axi4_to_ahb_io_axi_bready = io_lsu_axi_b_ready; // @[quasar.scala 320:35] - assign axi4_to_ahb_io_axi_arvalid = io_lsu_axi_ar_valid; // @[quasar.scala 322:36] - assign axi4_to_ahb_io_axi_rready = io_lsu_axi_r_ready; // @[quasar.scala 328:35] - assign axi4_to_ahb_1_clock = clock; - assign axi4_to_ahb_1_reset = reset; - assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 335:34] - assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 336:35] - assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 337:37] - assign axi4_to_ahb_1_io_axi_awvalid = io_ifu_axi_aw_valid; // @[quasar.scala 334:36] - assign axi4_to_ahb_1_io_axi_wvalid = io_ifu_axi_w_valid; // @[quasar.scala 343:35] - assign axi4_to_ahb_1_io_axi_bready = io_ifu_axi_b_ready; // @[quasar.scala 347:35] - assign axi4_to_ahb_1_io_axi_arvalid = io_ifu_axi_ar_valid; // @[quasar.scala 349:36] - assign axi4_to_ahb_1_io_axi_rready = io_ifu_axi_r_ready; // @[quasar.scala 355:35] - assign axi4_to_ahb_2_clock = clock; - assign axi4_to_ahb_2_reset = reset; - assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 363:33] - assign axi4_to_ahb_2_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 364:34] - assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 365:36] - assign axi4_to_ahb_2_io_axi_awvalid = io_sb_axi_aw_valid; // @[quasar.scala 362:35] - assign axi4_to_ahb_2_io_axi_wvalid = io_sb_axi_w_valid; // @[quasar.scala 371:34] - assign axi4_to_ahb_2_io_axi_bready = io_sb_axi_b_ready; // @[quasar.scala 375:34] - assign axi4_to_ahb_2_io_axi_arvalid = io_sb_axi_ar_valid; // @[quasar.scala 377:35] - assign axi4_to_ahb_2_io_axi_rready = io_sb_axi_r_ready; // @[quasar.scala 383:34] - assign ahb_to_axi4_clock = clock; - assign ahb_to_axi4_reset = reset; - assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 389:34] - assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 390:35] - assign ahb_to_axi4_io_axi_awready = io_dma_axi_aw_ready; // @[quasar.scala 392:36] - assign ahb_to_axi4_io_axi_arready = io_dma_axi_ar_ready; // @[quasar.scala 399:36] - assign ahb_to_axi4_io_axi_rvalid = io_dma_axi_ar_valid; // @[quasar.scala 400:35] - assign ahb_to_axi4_io_axi_rresp = io_dma_axi_r_bits_resp; // @[quasar.scala 403:34] endmodule module quasar_wrapper( input clock, @@ -83843,7 +83054,6 @@ module quasar_wrapper( wire core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 65:20] wire [63:0] core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] wire [7:0] core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 65:20] wire core_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 65:20] wire [1:0] core_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] wire [2:0] core_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 65:20] @@ -83854,20 +83064,15 @@ module quasar_wrapper( wire [3:0] core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] wire [2:0] core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] wire [3:0] core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 65:20] wire core_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 65:20] wire [2:0] core_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] wire [63:0] core_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] wire [1:0] core_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 65:20] wire core_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 65:20] wire core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 65:20] wire [2:0] core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] wire [31:0] core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] wire [3:0] core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 65:20] wire core_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 65:20] wire [2:0] core_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] wire [63:0] core_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] @@ -83881,7 +83086,6 @@ module quasar_wrapper( wire core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 65:20] wire [63:0] core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] wire [7:0] core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_b_ready; // @[quasar_wrapper.scala 65:20] wire core_io_sb_axi_b_valid; // @[quasar_wrapper.scala 65:20] wire [1:0] core_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] wire core_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 65:20] @@ -83889,7 +83093,6 @@ module quasar_wrapper( wire [31:0] core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] wire [3:0] core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] wire [2:0] core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_r_ready; // @[quasar_wrapper.scala 65:20] wire core_io_sb_axi_r_valid; // @[quasar_wrapper.scala 65:20] wire [63:0] core_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] wire [1:0] core_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] @@ -84078,7 +83281,6 @@ module quasar_wrapper( .io_lsu_axi_w_valid(core_io_lsu_axi_w_valid), .io_lsu_axi_w_bits_data(core_io_lsu_axi_w_bits_data), .io_lsu_axi_w_bits_strb(core_io_lsu_axi_w_bits_strb), - .io_lsu_axi_b_ready(core_io_lsu_axi_b_ready), .io_lsu_axi_b_valid(core_io_lsu_axi_b_valid), .io_lsu_axi_b_bits_resp(core_io_lsu_axi_b_bits_resp), .io_lsu_axi_b_bits_id(core_io_lsu_axi_b_bits_id), @@ -84089,20 +83291,15 @@ module quasar_wrapper( .io_lsu_axi_ar_bits_region(core_io_lsu_axi_ar_bits_region), .io_lsu_axi_ar_bits_size(core_io_lsu_axi_ar_bits_size), .io_lsu_axi_ar_bits_cache(core_io_lsu_axi_ar_bits_cache), - .io_lsu_axi_r_ready(core_io_lsu_axi_r_ready), .io_lsu_axi_r_valid(core_io_lsu_axi_r_valid), .io_lsu_axi_r_bits_id(core_io_lsu_axi_r_bits_id), .io_lsu_axi_r_bits_data(core_io_lsu_axi_r_bits_data), .io_lsu_axi_r_bits_resp(core_io_lsu_axi_r_bits_resp), - .io_ifu_axi_aw_valid(core_io_ifu_axi_aw_valid), - .io_ifu_axi_w_valid(core_io_ifu_axi_w_valid), - .io_ifu_axi_b_ready(core_io_ifu_axi_b_ready), .io_ifu_axi_ar_ready(core_io_ifu_axi_ar_ready), .io_ifu_axi_ar_valid(core_io_ifu_axi_ar_valid), .io_ifu_axi_ar_bits_id(core_io_ifu_axi_ar_bits_id), .io_ifu_axi_ar_bits_addr(core_io_ifu_axi_ar_bits_addr), .io_ifu_axi_ar_bits_region(core_io_ifu_axi_ar_bits_region), - .io_ifu_axi_r_ready(core_io_ifu_axi_r_ready), .io_ifu_axi_r_valid(core_io_ifu_axi_r_valid), .io_ifu_axi_r_bits_id(core_io_ifu_axi_r_bits_id), .io_ifu_axi_r_bits_data(core_io_ifu_axi_r_bits_data), @@ -84116,7 +83313,6 @@ module quasar_wrapper( .io_sb_axi_w_valid(core_io_sb_axi_w_valid), .io_sb_axi_w_bits_data(core_io_sb_axi_w_bits_data), .io_sb_axi_w_bits_strb(core_io_sb_axi_w_bits_strb), - .io_sb_axi_b_ready(core_io_sb_axi_b_ready), .io_sb_axi_b_valid(core_io_sb_axi_b_valid), .io_sb_axi_b_bits_resp(core_io_sb_axi_b_bits_resp), .io_sb_axi_ar_ready(core_io_sb_axi_ar_ready), @@ -84124,7 +83320,6 @@ module quasar_wrapper( .io_sb_axi_ar_bits_addr(core_io_sb_axi_ar_bits_addr), .io_sb_axi_ar_bits_region(core_io_sb_axi_ar_bits_region), .io_sb_axi_ar_bits_size(core_io_sb_axi_ar_bits_size), - .io_sb_axi_r_ready(core_io_sb_axi_r_ready), .io_sb_axi_r_valid(core_io_sb_axi_r_valid), .io_sb_axi_r_bits_data(core_io_sb_axi_r_bits_data), .io_sb_axi_r_bits_resp(core_io_sb_axi_r_bits_resp), diff --git a/src/main/scala/quasar.scala b/src/main/scala/quasar.scala index 30caa25a..6bb39976 100644 --- a/src/main/scala/quasar.scala +++ b/src/main/scala/quasar.scala @@ -52,59 +52,6 @@ class quasar_bundle extends Bundle with lib{ val ic = new ic_mem() val iccm = new iccm_mem() - // // AHB Lite Bus - // val haddr = Output(UInt(32.W)) - // val hburst = Output(UInt(3.W)) - // val hmastlock = Output(Bool()) - // val hprot = Output(UInt(4.W)) - // val hsize = Output(UInt(3.W)) - // val htrans = Output(UInt(2.W)) - // val hwrite = Output(Bool()) - // val hrdata = Input(UInt(64.W)) - // val hready = Input(Bool()) - // val hresp = Input(Bool()) - // - // // AHB Master - // val lsu_haddr = Output(UInt(32.W)) - // val lsu_hburst = Output(UInt(3.W)) - // val lsu_hmastlock = Output(Bool()) - // val lsu_hprot = Output(UInt(4.W)) - // val lsu_hsize = Output(UInt(3.W)) - // val lsu_htrans = Output(UInt(2.W)) - // val lsu_hwrite = Output(Bool()) - // val lsu_hwdata = Output(UInt(64.W)) - // val lsu_hrdata = Input(UInt(64.W)) - // val lsu_hready = Input(Bool()) - // val lsu_hresp = Input(Bool()) - // - // // System Bus Debug Master - // val sb_haddr = Output(UInt(32.W)) - // val sb_hburst = Output(UInt(3.W)) - // val sb_hmastlock = Output(Bool()) - // val sb_hprot = Output(UInt(4.W)) - // val sb_hsize = Output(UInt(3.W)) - // val sb_htrans = Output(UInt(2.W)) - // val sb_hwrite = Output(Bool()) - // val sb_hwdata = Output(UInt(64.W)) - // val sb_hrdata = Input(UInt(64.W)) - // val sb_hready = Input(Bool()) - // val sb_hresp = Input(Bool()) - // - // // DMA slave -// dma_hsel = Input(Bool()) - // val dma_haddr = Input(UInt(32.W)) - // val dma_hburst = Input(UInt(3.W)) - // val dma_hmastlock = Input(Bool()) - // val dma_hprot = Input(UInt(4.W)) - // val dma_hsize = Input(UInt(3.W)) - // val dma_htrans = Input(UInt(2.W)) - // val dma_hwrite = Input(Bool()) - // val dma_hwdata = Input(UInt(64.W)) -// val dma_hreadyin = Input(Bool()) - // val dma_hrdata = Output(UInt(64.W)) - // val dma_hreadyout = Output(Bool()) - // val dma_hresp = Output(Bool()) - val lsu_bus_clk_en = Input(Bool()) val ifu_bus_clk_en = Input(Bool()) val dbg_bus_clk_en = Input(Bool()) @@ -301,7 +248,7 @@ class quasar extends Module with RequireAsyncReset with lib { - +/* when(BUILD_AHB_LITE.B) { val lsu_axi4_to_ahb = Module(new axi4_to_ahb()) lsu_axi4_to_ahb.io.axi_awvalid := io.lsu_axi.aw.valid @@ -326,9 +273,6 @@ class quasar extends Module with RequireAsyncReset with lib { lsu_axi4_to_ahb.io.axi_arprot := io.lsu_axi.ar.bits.prot lsu_axi4_to_ahb.io.axi_rready := io.lsu_axi.r.ready - // lsu_axi4_to_ahb.io.ahb_hrdata := io.lsu_hrdata - // lsu_axi4_to_ahb.io.ahb_hready := io.lsu_hready - // lsu_axi4_to_ahb.io.ahb_hresp := io.lsu_hresp val ifu_axi4_to_ahb = Module(new axi4_to_ahb()) ifu_axi4_to_ahb.io.axi_awvalid := io.ifu_axi.aw.valid @@ -459,77 +403,28 @@ class quasar extends Module with RequireAsyncReset with lib { dma_ctrl.io.dma_axi.r.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) // AHB Signals io.ahb <> ifu_axi4_to_ahb.io.ahb - // io.haddr := ifu_axi4_to_ahb.io.ahb_haddr - // io.hburst := ifu_axi4_to_ahb.io.ahb_hburst - // io.hmastlock := ifu_axi4_to_ahb.io.ahb_hmastlock - // io.hprot := ifu_axi4_to_ahb.io.ahb_hprot - // io.hsize := ifu_axi4_to_ahb.io.ahb_hsize - // io.htrans := ifu_axi4_to_ahb.io.ahb_htrans - // io.hwrite := ifu_axi4_to_ahb.io.ahb_hwrite io.lsu_ahb <> lsu_axi4_to_ahb.io.ahb - // io.lsu_haddr := lsu_axi4_to_ahb.io.ahb_haddr - // io.lsu_hburst := lsu_axi4_to_ahb.io.ahb_hburst - // io.lsu_hmastlock := lsu_axi4_to_ahb.io.ahb_hmastlock - // io.lsu_hprot := lsu_axi4_to_ahb.io.ahb_hprot - // io.lsu_hsize := lsu_axi4_to_ahb.io.ahb_hsize - // io.lsu_htrans := lsu_axi4_to_ahb.io.ahb_htrans - // io.lsu_hwrite := lsu_axi4_to_ahb.io.ahb_hwrite - // io.lsu_hwdata := lsu_axi4_to_ahb.io.ahb_hwdata io.sb_ahb <> sb_axi4_to_ahb.io.ahb - // io.sb_haddr := sb_axi4_to_ahb.io.ahb_haddr - // io.sb_hburst := sb_axi4_to_ahb.io.ahb_hburst - // io.sb_hmastlock := sb_axi4_to_ahb.io.ahb_hmastlock - // io.sb_hprot := sb_axi4_to_ahb.io.ahb_hprot - // io.sb_hsize := sb_axi4_to_ahb.io.ahb_hsize - // io.sb_htrans := sb_axi4_to_ahb.io.ahb_htrans - // io.sb_hwrite := sb_axi4_to_ahb.io.ahb_hwrite - // io.sb_hwdata := sb_axi4_to_ahb.io.ahb_hwdata io.dma.ahb <> dma_ahb_to_axi4.io.ahb.sig - // io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata - // io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout - // io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp - // io.dma_hresp := 0.U//dma_ahb_to_axi4.io.ahb_hrdata - // io.dmi_reg_rdata := 0.U//dma_ahb_to_axi4.io.ahb_rdata } .otherwise{ // AHB Signals io.ahb.out <> 0.U.asTypeOf(io.ahb.out) - // io.haddr := 0.U - // io.hburst := 0.U - // io.hmastlock := 0.U - // io.hprot := 0.U - // io.hsize := 0.U - // io.htrans := 0.U - // io.hwrite := 0.U io.lsu_ahb.out <> 0.U.asTypeOf(io.lsu_ahb.out) - // io.lsu_haddr := 0.U - // io.lsu_hburst := 0.U - // io.lsu_hmastlock := 0.U - // io.lsu_hprot := 0.U - // io.lsu_hsize := 0.U - // io.lsu_htrans := 0.U - // io.lsu_hwrite := 0.U - // io.lsu_hwdata := 0.U io.sb_ahb.out <> 0.U.asTypeOf(io.sb_ahb.out) - // io.sb_haddr := 0.U - // io.sb_hburst := 0.U - // io.sb_hmastlock := 0.U - // io.sb_hprot := 0.U - // io.sb_hsize := 0.U - // io.sb_htrans := 0.U - // io.sb_hwrite := 0.U - // io.sb_hwdata := 0.U io.dma.ahb.in <> 0.U.asTypeOf(io.dma.ahb.in) - // io.dma_hrdata := 0.U - // io.dma_hreadyout := 0.U - // io.dma_hresp := 0.U } + */ + io.ahb.out <> 0.U.asTypeOf(io.ahb.out) + io.lsu_ahb.out <> 0.U.asTypeOf(io.lsu_ahb.out) + io.sb_ahb.out <> 0.U.asTypeOf(io.sb_ahb.out) + io.dma.ahb.in <> 0.U.asTypeOf(io.dma.ahb.in) io.dmi_reg_rdata := 0.U } diff --git a/target/scala-2.12/classes/QUASAR_Wrp$.class b/target/scala-2.12/classes/QUASAR_Wrp$.class index 804b4d29..941c84a5 100644 Binary files a/target/scala-2.12/classes/QUASAR_Wrp$.class and b/target/scala-2.12/classes/QUASAR_Wrp$.class differ diff --git a/target/scala-2.12/classes/quasar.class b/target/scala-2.12/classes/quasar.class index a57aeb44..90f7419d 100644 Binary files a/target/scala-2.12/classes/quasar.class and b/target/scala-2.12/classes/quasar.class differ diff --git a/target/scala-2.12/classes/quasar_bundle.class b/target/scala-2.12/classes/quasar_bundle.class index e5d21a63..74bb4e66 100644 Binary files a/target/scala-2.12/classes/quasar_bundle.class and b/target/scala-2.12/classes/quasar_bundle.class differ