Predictor hash check

src/main/scala/ifu/el2_ifu_bp_ctl.scala

@@ -174,7 +174,6 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
   // Making virtual banks, made bit 1 of the pc to check
   val btb_vbank0_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(1)->btb_bank0e_rd_data_f,
                                         io.ifc_fetch_addr_f(1)->btb_bank0o_rd_data_f))
-  io.test:=btb_vbank0_rd_data_f
   val btb_vbank1_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(1)->btb_bank0o_rd_data_f,
                                         io.ifc_fetch_addr_f(1)->btb_bank0e_rd_data_p1_f))
 
@@ -186,10 +185,9 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
   val fetch_wrindex_p1_dec = 1.U(LRU_SIZE) << btb_rd_addr_p1_f
 
   val mp_wrlru_b0 = mp_wrindex_dec & Fill(LRU_SIZE, exu_mp_valid)
-
   val vwayhit_f = Mux1H(Seq(~io.ifc_fetch_addr_f(0).asBool->wayhit_f,
     io.ifc_fetch_addr_f(0).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
-
+  io.test := vwayhit_f
   val lru_update_valid_f = (vwayhit_f(0) | vwayhit_f(1)) & io.ifc_fetch_req_f & !leak_one_f
 
   val fetch_wrlru_b0 = fetch_wrindex_dec & Fill(fetch_wrindex_dec.getWidth, lru_update_valid_f)

src/main/scala/ifu/el2_ifu_ic_mem.scala

@@ -253,7 +253,7 @@ class EL2_IC_DATA extends Module with el2_lib {
   })
 
   val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & !io.ic_debug_tag_array) & io.ic_debug_way
-  val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & !io.ic_debug_tag_array) & io.ic_debug_way
+  val ic_debug_wr_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & !io.ic_debug_tag_array) & io.ic_debug_way
 
   val ic_bank_wr_data = Wire(Vec(ICACHE_BANKS_WAY,UInt(71.W)))
   val ic_rd_en_with_debug = WireInit(Bool(), 0.U)

src/main/scala/lib/el2_lib.scala

@@ -169,24 +169,25 @@ trait el2_lib extends param{
   val DATA_MEM_LINE = MEM_CAL
   val Tag_Word = MEM_CAL._4
 
+  ///////////////////////////////////////////////////////////////////
   def el2_btb_tag_hash(pc : UInt) =
     VecInit.tabulate(3)(i => pc(BTB_ADDR_HI-1+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE))).reduce(_^_)
 
+  ///////////////////////////////////////////////////////////////////
   def el2_btb_tag_hash_fold(pc : UInt) =
     pc(BTB_ADDR_HI+(2*BTB_BTAG_SIZE),BTB_ADDR_HI+BTB_BTAG_SIZE+1)^pc(BTB_ADDR_HI+BTB_BTAG_SIZE,BTB_ADDR_HI+1)
 
+  ///////////////////////////////////////////////////////////////////
   def el2_btb_addr_hash(pc : UInt) =
     if(BTB_FOLD2_INDEX_HASH) pc(BTB_INDEX1_HI-1,BTB_INDEX1_LO-1) ^ pc(BTB_INDEX3_HI-1,BTB_INDEX3_LO-1)
     else pc(BTB_INDEX1_HI-1,BTB_INDEX1_LO-1) ^ pc(BTB_INDEX2_HI-1,BTB_INDEX2_LO-1) ^ pc(BTB_INDEX3_HI-1,BTB_INDEX3_LO-1)
 
+  ///////////////////////////////////////////////////////////////////
   def el2_btb_ghr_hash(hashin : UInt, ghr :UInt) =
     if(BHT_GHR_HASH_1) Cat(ghr(BHT_GHR_SIZE-1,BTB_INDEX1_HI-1), hashin(BTB_INDEX1_HI,2) ^ ghr(BTB_INDEX1_HI-2,0))
     else hashin(BHT_GHR_SIZE+1,2) ^ ghr(BHT_GHR_SIZE-1,0)
 
-  def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
+  ///////////////////////////////////////////////////////////////////
-
-  def Mux1H_LM(a:Seq[Bool], b:Seq[UInt]) = (0 until b.size).map(i=> repl(b(i).getWidth,a(i)) & b(i)).reduce(_|_)
-
   def rveven_paritycheck(data_in:UInt, parity_in:UInt) : UInt =
     (data_in.xorR.asUInt) ^ parity_in