colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

DECODE added

This commit is contained in:
​Laraib Khan 2020-12-17 10:54:07 +05:00
parent 4328532fdb
commit ff87a1341a
11 changed files with 194148 additions and 278 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
firrtl_black_box_resource_files.f
View File

@ -1,3 +1 @@
/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.sv /home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.sv
/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
/home/laraibkhan/Desktop/SweRV-Chislified/mem.sv

1252
quasar.anno.json Normal file
View File

File diff suppressed because it is too large Load Diff

109692
quasar.fir Normal file
View File

File diff suppressed because one or more lines are too long

82929
quasar.v Normal file
View File

File diff suppressed because it is too large Load Diff

6
src/main/scala/dec/dec.scala
View File

@ -162,7 +162,7 @@ class dec extends Module with param with RequireAsyncReset{
decode.io.lsu_store_stall_any := io.lsu_store_stall_any decode.io.lsu_store_stall_any := io.lsu_store_stall_any
decode.io.exu_div_wren := io.exu_div_wren decode.io.exu_div_wren := io.exu_div_wren
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
decode.io.dec_tlu_flush_lower_wb := tlu.io.tlu_bp.dec_tlu_flush_lower_wb decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
@ -303,3 +303,7 @@ class dec extends Module with param with RequireAsyncReset{
// debug command read data // debug command read data
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
} }
object dec_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new dec()))
}

32
src/main/scala/dec/dec_decode_ctl.scala
View File

@ -10,11 +10,13 @@ import lsu._
class dec_decode_ctl extends Module with lib with RequireAsyncReset{ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
val io = IO(new Bundle{ val io = IO(new Bundle{
val decode_exu = Flipped(new decode_exu) val decode_exu = Flipped(new decode_exu) //connection with exu top
val dec_alu = Flipped(new dec_alu) val dec_alu = Flipped(new dec_alu) //connection with alu
val dec_div = Flipped(new dec_div) val dec_div = Flipped(new dec_div) //connection with divider
val dctl_busbuff = Flipped(new dctl_busbuff()) val dctl_busbuff = Flipped(new dctl_busbuff()) //connection with bus buffer
val dctl_dma = new dctl_dma val dctl_dma = new dctl_dma //connection with dma
val dec_aln = Flipped(new aln_dec) //connection with aligner
val dbg_dctl = new dbg_dctl() //connection with dbg
val dec_tlu_flush_extint = Input(Bool()) val dec_tlu_flush_extint = Input(Bool())
val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event
val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder
@ -88,12 +90,8 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating
val dec_div_active = Output(Bool()) // non-block divide is active val dec_div_active = Output(Bool()) // non-block divide is active
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val dec_aln = Flipped(new aln_dec)
val dbg_dctl = new dbg_dctl()
}) })
///////////////////////////////////////////////////////////////////////////////////////// //packets zero initialization
// //packets zero initialization
io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p) io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p)
// Vals defined // Vals defined
val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U) val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U)
@ -122,7 +120,6 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
val nonblock_load_write = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) val nonblock_load_write = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
val cam_raw = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) val cam_raw = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
val cam_in = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) val cam_in = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
//val i0_temp = Wire(new inst_pkt_t)
val i0_dp = Wire(new dec_pkt_t) val i0_dp = Wire(new dec_pkt_t)
val i0_dp_raw = Wire(new dec_pkt_t) val i0_dp_raw = Wire(new dec_pkt_t)
val i0_rs1bypass = WireInit(UInt(3.W), 0.U) val i0_rs1bypass = WireInit(UInt(3.W), 0.U)
@ -190,8 +187,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
val data_gate_clk = rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode) val data_gate_clk = rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode)
// End - Data gating
// End - Data gating }}
val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode
io.decode_exu.dec_i0_predict_p_d.bits.misp := 0.U io.decode_exu.dec_i0_predict_p_d.bits.misp := 0.U
@ -224,7 +220,6 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
// on i0 instruction fetch access fault turn anything into a nop // on i0 instruction fetch access fault turn anything into a nop
// nop => alu rs1 imm12 rd lor // nop => alu rs1 imm12 rd lor
val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d
val i0_instr_error = i0_icaf_d; val i0_instr_error = i0_icaf_d;
i0_dp := i0_dp_raw i0_dp := i0_dp_raw
when((i0_br_error_all | i0_instr_error).asBool){ when((i0_br_error_all | i0_instr_error).asBool){
@ -242,7 +237,6 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
// branches that can be predicted // branches that can be predicted
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret; val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
val i0_ap_pc2 = !io.dec_i0_pc4_d val i0_ap_pc2 = !io.dec_i0_pc4_d
@ -617,8 +611,8 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
i0_d_c.load := i0_dp.load & i0_legal_decode_d i0_d_c.load := i0_dp.load & i0_legal_decode_d
i0_d_c.alu := i0_dp.alu & i0_legal_decode_d i0_d_c.alu := i0_dp.alu & i0_legal_decode_d
val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c, i0_x_ctl_en.asBool)} val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c,0.U.asTypeOf(i0_d_c), i0_x_ctl_en.asBool)}
val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c, i0_r_ctl_en.asBool)} val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c,0.U.asTypeOf(i0_x_c), i0_r_ctl_en.asBool)}
i0_pipe_en := Cat(io.dec_aln.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)}) i0_pipe_en := Cat(io.dec_aln.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override) i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override)
@ -667,7 +661,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
io.dec_i0_wdata_r := i0_result_corr_r io.dec_i0_wdata_r := i0_result_corr_r
val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode) val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode)
if ( LOAD_TO_USE_PLUS1 == 1 ) { if ( LOAD_TO_USE_PLUS1) {
i0_result_x := io.decode_exu.exu_i0_result_x i0_result_x := io.decode_exu.exu_i0_result_x
i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw) i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw)
} }
@ -747,7 +741,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U)) i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U))
// stores will bypass load data in the lsu pipe // stores will bypass load data in the lsu pipe
if (LOAD_TO_USE_PLUS1 == 1) { if (LOAD_TO_USE_PLUS1) {
i0_load_block_d := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store) i0_load_block_d := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store)
load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load
store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load) store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load)

25
src/main/scala/dec/dec_tlu_ctl.scala
View File

@ -141,6 +141,7 @@ class dec_tlu_ctl_IO extends Bundle with lib {
val dec_tlu_pic_clk_override = Output(UInt(1.W)) // override PIC clock domain gating val dec_tlu_pic_clk_override = Output(UInt(1.W)) // override PIC clock domain gating
val dec_tlu_dccm_clk_override = Output(UInt(1.W)) // override DCCM clock domain gating val dec_tlu_dccm_clk_override = Output(UInt(1.W)) // override DCCM clock domain gating
val dec_tlu_icm_clk_override = Output(UInt(1.W)) // override ICCM clock domain gating val dec_tlu_icm_clk_override = Output(UInt(1.W)) // override ICCM clock domain gating
val dec_tlu_flush_lower_wb = Output(Bool())
val ifu_pmu_instr_aligned = Input(UInt(1.W)) val ifu_pmu_instr_aligned = Input(UInt(1.W))
val tlu_bp = Flipped(new dec_bp) val tlu_bp = Flipped(new dec_bp)
val tlu_ifc = Flipped(new dec_ifc) val tlu_ifc = Flipped(new dec_ifc)
@ -329,8 +330,6 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val internal_dbg_halt_mode_f2 =withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)} val internal_dbg_halt_mode_f2 =withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)}
io.tlu_mem.dec_tlu_force_halt :=withClock(io.free_clk){RegNext(force_halt,0.U)} io.tlu_mem.dec_tlu_force_halt :=withClock(io.free_clk){RegNext(force_halt,0.U)}
io.dec_tlu_i0_kill_writeb_r :=tlu_i0_kill_writeb_r io.dec_tlu_i0_kill_writeb_r :=tlu_i0_kill_writeb_r
val reset_detect =withClock(io.free_clk){RegNext(1.U(1.W),0.U)} val reset_detect =withClock(io.free_clk){RegNext(1.U(1.W),0.U)}
val reset_detected =withClock(io.free_clk){RegNext(reset_detect,0.U)} val reset_detected =withClock(io.free_clk){RegNext(reset_detect,0.U)}
@ -440,7 +439,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val dbg_cmd_done_ns = io.dec_tlu_i0_valid_r & io.dec_tlu_dbg_halted val dbg_cmd_done_ns = io.dec_tlu_i0_valid_r & io.dec_tlu_dbg_halted
// used to hold off commits after an in-pipe debug mode request (triggers, DCSR) // used to hold off commits after an in-pipe debug mode request (triggers, DCSR)
val request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~io.tlu_bp.dec_tlu_flush_lower_wb) val request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~io.dec_tlu_flush_lower_wb)
val request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f val request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f
@ -516,7 +515,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val i0trigger_qual_r = Fill(4,i0_trigger_eval_r) & io.dec_tlu_packet_r.i0trigger(3,0) & i0_iside_trigger_has_pri_r & i0_lsu_trigger_has_pri_r & trigger_enabled val i0trigger_qual_r = Fill(4,i0_trigger_eval_r) & io.dec_tlu_packet_r.i0trigger(3,0) & i0_iside_trigger_has_pri_r & i0_lsu_trigger_has_pri_r & trigger_enabled
// Qual trigger hits // Qual trigger hits
val i0_trigger_r = ~(Fill(4,io.tlu_bp.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r val i0_trigger_r = ~(Fill(4,io.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r
// chaining can mask raw trigger info // chaining can mask raw trigger info
val i0_trigger_chain_masked_r = Cat(i0_trigger_r(3) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(2)), i0_trigger_r(2) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(3)), i0_trigger_r(1) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(0)), i0_trigger_r(0) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(1))) val i0_trigger_chain_masked_r = Cat(i0_trigger_r(3) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(2)), i0_trigger_r(2) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(3)), i0_trigger_r(1) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(0)), i0_trigger_r(0) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(1)))
@ -605,7 +604,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
mdseac_locked_f :=withClock(io.free_clk){RegNext(mdseac_locked_ns,0.U)} mdseac_locked_f :=withClock(io.free_clk){RegNext(mdseac_locked_ns,0.U)}
val lsu_single_ecc_error_r_d1 =withClock(io.free_clk){RegNext(lsu_single_ecc_error_r,0.U)} val lsu_single_ecc_error_r_d1 =withClock(io.free_clk){RegNext(lsu_single_ecc_error_r,0.U)}
val lsu_error_pkt_addr_r =io.lsu_error_pkt_r.bits.addr val lsu_error_pkt_addr_r =io.lsu_error_pkt_r.bits.addr
val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.valid & ~io.tlu_bp.dec_tlu_flush_lower_wb val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.valid & ~io.dec_tlu_flush_lower_wb
lsu_i0_exc_r_raw := io.lsu_error_pkt_r.valid lsu_i0_exc_r_raw := io.lsu_error_pkt_r.valid
val lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r val lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r
val lsu_exc_valid_r = lsu_i0_exc_r val lsu_exc_valid_r = lsu_i0_exc_r
@ -739,7 +738,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val block_interrupts = ((internal_dbg_halt_mode & (~dcsr_single_step_running | io.dec_tlu_i0_valid_r)) | internal_pmu_fw_halt_mode | i_cpu_halt_req_d1 | take_nmi | ebreak_to_debug_mode_r | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r | ext_int_freeze_d1) val block_interrupts = ((internal_dbg_halt_mode & (~dcsr_single_step_running | io.dec_tlu_i0_valid_r)) | internal_pmu_fw_halt_mode | i_cpu_halt_req_d1 | take_nmi | ebreak_to_debug_mode_r | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r | ext_int_freeze_d1)
if(FAST_INTERRUPT_REDIRECT==1) { if(FAST_INTERRUPT_REDIRECT) {
take_ext_int_start_d1:=withClock(io.free_clk){RegNext(take_ext_int_start,0.U)} take_ext_int_start_d1:=withClock(io.free_clk){RegNext(take_ext_int_start,0.U)}
take_ext_int_start_d2:=withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)} take_ext_int_start_d2:=withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)}
take_ext_int_start_d3:=withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)} take_ext_int_start_d3:=withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)}
@ -797,8 +796,8 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this
io.tlu_bp.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1 io.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1
io.tlu_mem.dec_tlu_flush_lower_wb := io.tlu_bp.dec_tlu_flush_lower_wb // io.tlu_mem.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
io.tlu_exu.dec_tlu_flush_lower_r := tlu_flush_lower_r io.tlu_exu.dec_tlu_flush_lower_r := tlu_flush_lower_r
io.tlu_exu.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this io.tlu_exu.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this
@ -1747,7 +1746,7 @@ val wr_mcycleh_r = WireInit(UInt(1.W), 0.U)
mfdc_int := rvdffe(mfdc_ns,wr_mfdc_r.asBool,clock,io.scan_mode) mfdc_int := rvdffe(mfdc_ns,wr_mfdc_r.asBool,clock,io.scan_mode)
// rvdffe #(15) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[14:0]}), .dout(mfdc_int[14:0])); // rvdffe #(15) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[14:0]}), .dout(mfdc_int[14:0]));
if(BUILD_AXI4 == 1){ if(BUILD_AXI4){
// flip poweron value of bit 6 for AXI build // flip poweron value of bit 6 for AXI build
mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,7), ~io.dec_csr_wrdata_r(6), io.dec_csr_wrdata_r(5,0)) mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,7), ~io.dec_csr_wrdata_r(6), io.dec_csr_wrdata_r(5,0))
mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,7), ~mfdc_int(6), mfdc_int(5,0)) mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,7), ~mfdc_int(6), mfdc_int(5,0))
@ -2118,7 +2117,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm
val dicad0h = rvdffe(dicad0h_ns,(wr_dicad0h_r | io.ifu_ic_debug_rd_data_valid).asBool,clock,io.scan_mode) val dicad0h = rvdffe(dicad0h_ns,(wr_dicad0h_r | io.ifu_ic_debug_rd_data_valid).asBool,clock,io.scan_mode)
if (ICACHE_ECC == 1) { if (ICACHE_ECC) {
// ---------------------------------------------------------------------- // ----------------------------------------------------------------------
// DICAD1 (R/W) (Only accessible in debug mode) // DICAD1 (R/W) (Only accessible in debug mode)
// [6:0] : ECC // [6:0] : ECC
@ -2126,7 +2125,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm
val dicad1_raw = WireInit(UInt(7.W),0.U) val dicad1_raw = WireInit(UInt(7.W),0.U)
val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1)
val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(70,64)) val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r(6,0), io.ifu_ic_debug_rd_data(70,64))
dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)}
dicad1 := Cat(0.U(25.W), dicad1_raw) dicad1 := Cat(0.U(25.W), dicad1_raw)
@ -2151,7 +2150,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm
// DICAGO (R/W) (Only accessible in debug mode) // DICAGO (R/W) (Only accessible in debug mode)
// [0] : Go // [0] : Go
if (ICACHE_ECC == 1) io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0)) if (ICACHE_ECC) io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0))
else io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(0.U(2.W),dicad1(3,0), dicad0h(31,0), dicad0(31,0)) else io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(0.U(2.W),dicad1(3,0), dicad0h(31,0), dicad0(31,0))
io.dec_tlu_ic_diag_pkt.icache_dicawics := dicawics io.dec_tlu_ic_diag_pkt.icache_dicawics := dicawics
@ -2498,7 +2497,7 @@ for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)}
io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W), io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W),
io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W), io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W),
io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W), io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W),
io.csr_pkt.csr_mimpid.asBool -> 0x2.U(32.W), io.csr_pkt.csr_mimpid.asBool -> 0x1.U(32.W),
io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)), io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)),
io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)), io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)),
io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)), io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)),

4
src/main/scala/quasar.scala
View File

@ -419,7 +419,9 @@ class quasar extends Module with RequireAsyncReset with lib {
io.dmi_reg_rdata := 0.U io.dmi_reg_rdata := 0.U
} }
object QUASAR extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
}

BIN
target/scala-2.12/classes/QUASAR$.class Normal file
View File

Binary file not shown.

BIN
target/scala-2.12/classes/QUASAR$delayedInit$body.class Normal file
View File

Binary file not shown.

BIN
target/scala-2.12/classes/QUASAR.class Normal file
View File

Binary file not shown.