Laraib Khan
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91635292c6
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ifu_bp_btb_target_f corrected
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2021-01-25 10:44:37 +05:00 |
Laraib Khan
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a5be674839
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btb_vbank0_rd_data_f := Mux1H(Seq(!io.ifc_fetch_addr_f(0) -> btb_bank0e_rd_data_f,
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2021-01-22 16:41:53 +05:00 |
Laraib Khan
|
a25ee3cf0e
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vwayhit corrected
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2021-01-22 15:59:15 +05:00 |
Laraib Khan
|
ef2f0bbbb2
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vwayhit corrected
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2021-01-22 14:59:02 +05:00 |
Laraib Khan
|
5ec570e847
|
vwayhit corrected
|
2021-01-22 12:38:12 +05:00 |
Laraib Khan
|
f2bbfb2e20
|
vwayhit corrected
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2021-01-22 11:44:00 +05:00 |
Laraib Khan
|
f8874723a6
|
BP corrected
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2021-01-21 16:12:12 +05:00 |
Laraib Khan
|
ed92fad092
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BP added
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2021-01-20 15:46:13 +05:00 |
Laraib Khan
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5ac08982de
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IFC updated
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2021-01-18 11:10:24 +05:00 |
Laraib Khan
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d9dc8848f9
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AHB/AXI added
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2021-01-13 10:07:59 +05:00 |
Laraib Khan
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65d5369d1e
|
2 bit divider
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2021-01-06 09:32:46 +05:00 |
Laraib Khan
|
309087b854
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bus buffer added
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2020-12-24 15:53:17 +05:00 |
Laraib Khan
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e1ce51fdd4
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clk domain with rvoclkhdr
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2020-12-22 16:44:36 +05:00 |
Laraib Khan
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15483fd532
|
Master updated with vsrc
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2020-12-17 18:21:54 +05:00 |
Laraib Khan
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3ab9b841d7
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PIC,param,lib,mem.scala added
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2020-12-17 09:32:59 +05:00 |
Laraib Khan
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4cf7b083e5
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IFU added
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2020-12-16 18:06:34 +05:00 |
Laraib Khan
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b9c70b1fb5
|
Core with Bundles
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2020-12-09 09:34:03 +05:00 |