Laraib Khan
|
bb89af4b68
|
fpga registers updated
|
2020-12-28 14:17:13 +05:00 |
|
Laraib Khan
|
57f1b66c15
|
bus buffer with buf_nextstate in resp updated
|
2020-12-28 12:49:43 +05:00 |
|
Laraib Khan
|
17fe416e15
|
bus buffer with reg_fpga updated
|
2020-12-28 10:41:40 +05:00 |
|
Laraib Khan
|
c438fae14a
|
bus buffer added
|
2020-12-24 16:51:11 +05:00 |
|
Laraib Khan
|
46ffb7c24f
|
bus buffer added
|
2020-12-24 16:34:10 +05:00 |
|
Laraib Khan
|
309087b854
|
bus buffer added
|
2020-12-24 15:53:17 +05:00 |
|
Laraib Khan
|
248ab0784b
|
stbuf with rvdffe
|
2020-12-23 09:39:18 +05:00 |
|
Laraib Khan
|
b1a6c0bf30
|
rvclkhdr with scan mode=0
|
2020-12-22 16:51:17 +05:00 |
|
Laraib Khan
|
e1ce51fdd4
|
clk domain with rvoclkhdr
|
2020-12-22 16:44:36 +05:00 |
|
Laraib Khan
|
1c41a85c25
|
Master updated
|
2020-12-18 10:14:48 +05:00 |
|
Laraib Khan
|
15483fd532
|
Master updated with vsrc
|
2020-12-17 18:21:54 +05:00 |
|
Laraib Khan
|
4328532fdb
|
vsrc replaced
|
2020-12-17 10:16:07 +05:00 |
|
Laraib Khan
|
3ab9b841d7
|
PIC,param,lib,mem.scala added
|
2020-12-17 09:32:59 +05:00 |