.metals/
.vscode/

# design/project/target/
# design/project/project/
design/project/
design/.idea/

design/target/

generated_rtl/*.sv
verif/sim/*.log 
verif/sim/*.s 
verif/sim/*.hex 
verif/sim/*.dis 
verif/sim/*.tbl 
verif/sim/vcs* 
verif/sim/simv* 
verif/sim/quasar*
verif/sim/*.exe 
verif/sim/obj* 
verif/sim/*.o 
verif/sim/ucli.key 
verif/sim/vc_hdrs.h 
verif/sim/csrc 
verif/sim/*.csv 
verif/sim/work
verif/sim/*.dump
verif/sim/*.fsdb
FM_WORK
tracer_logs/*.log
verif/LEC/formality_work/formality_log/*.log
verif/LEC/*.fss

design/snapshots/
design/src/main/scala/lib/param.scala

design/*.v
design/*.sv
design/*.f
design/*.json
design/*.fir


# soc/
# demo/