[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_write_stall",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wren",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_write",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_type_f",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_dma_active",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_flush_err_wb",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_i0_commit_cmt",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_fetch_val",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rw_addr",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_addr",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_addr_bf",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_f",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_en",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_iccm_access_bf",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_req_bf",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_uncacheable_bf",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_force_halt",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wr_data",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_wdata",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wr_size",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_sz",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_ecc_error",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_perr",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rden",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_iccm_access_bf",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_req_bf",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_write",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wrdata"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_async_error_start",
    "sources":[
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_perr",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid",
      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
    ]
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.transforms.BlackBoxResourceAnno",
    "target":"el2_ifu_mem_ctl.TEC_RV_ICG",
    "resourceId":"/vsrc/TEC_RV_ICG.v"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"el2_ifu_mem_ctl"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]