;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit el2_ifu_iccm_mem : module el2_ifu_iccm_mem : input clock : Clock input reset : UInt<1> output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>, iccm_bank_addr : UInt[4]} io.iccm_rd_data <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 22:19] io.iccm_rd_data_ecc <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 23:23] node _T = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 24:38] node _T_1 = eq(_T, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 24:43] node _T_2 = bits(_T_1, 0, 0) @[el2_ifu_iccm_mem.scala 24:51] node addr_inc = mux(_T_2, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_iccm_mem.scala 24:21] node _T_3 = bits(io.iccm_rw_addr, 14, 0) @[el2_ifu_iccm_mem.scala 25:38] node _T_4 = add(_T_3, addr_inc) @[el2_ifu_iccm_mem.scala 25:54] node addr_bank_inc = tail(_T_4, 1) @[el2_ifu_iccm_mem.scala 25:54] wire iccm_bank_wr_data : UInt<39>[4] @[el2_ifu_iccm_mem.scala 27:35] node _T_5 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50] iccm_bank_wr_data[0] <= _T_5 @[el2_ifu_iccm_mem.scala 29:32] node _T_6 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54] iccm_bank_wr_data[1] <= _T_6 @[el2_ifu_iccm_mem.scala 30:36] node _T_7 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50] iccm_bank_wr_data[2] <= _T_7 @[el2_ifu_iccm_mem.scala 29:32] node _T_8 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54] iccm_bank_wr_data[3] <= _T_8 @[el2_ifu_iccm_mem.scala 30:36] node _T_9 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82] node _T_10 = eq(_T_9, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:100] node _T_11 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122] node _T_12 = eq(_T_11, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:140] node _T_13 = or(_T_10, _T_12) @[el2_ifu_iccm_mem.scala 33:107] node wren_bank_0 = and(io.iccm_wren, _T_13) @[el2_ifu_iccm_mem.scala 33:64] node _T_14 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82] node _T_15 = eq(_T_14, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:100] node _T_16 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122] node _T_17 = eq(_T_16, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:140] node _T_18 = or(_T_15, _T_17) @[el2_ifu_iccm_mem.scala 33:107] node wren_bank_1 = and(io.iccm_wren, _T_18) @[el2_ifu_iccm_mem.scala 33:64] node _T_19 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82] node _T_20 = eq(_T_19, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:100] node _T_21 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122] node _T_22 = eq(_T_21, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:140] node _T_23 = or(_T_20, _T_22) @[el2_ifu_iccm_mem.scala 33:107] node wren_bank_2 = and(io.iccm_wren, _T_23) @[el2_ifu_iccm_mem.scala 33:64] node _T_24 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82] node _T_25 = eq(_T_24, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:100] node _T_26 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122] node _T_27 = eq(_T_26, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:140] node _T_28 = or(_T_25, _T_27) @[el2_ifu_iccm_mem.scala 33:107] node wren_bank_3 = and(io.iccm_wren, _T_28) @[el2_ifu_iccm_mem.scala 33:64] node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:99] node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 35:64] node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:139] node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 35:106] node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:99] node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 35:64] node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:139] node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 35:106] node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:99] node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 35:64] node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:139] node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 35:106] node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:99] node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 35:64] node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:139] node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 35:106] node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 36:72] node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 36:72] node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 36:72] node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 36:72] node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] node _T_53 = bits(wren_bank_0, 0, 0) @[el2_ifu_iccm_mem.scala 38:69] node _T_54 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92] node _T_55 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23] node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 39:41] node _T_57 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62] node _T_58 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112] node _T_59 = mux(_T_56, _T_57, _T_58) @[el2_ifu_iccm_mem.scala 39:8] node addr_bank_0 = mux(_T_53, _T_54, _T_59) @[el2_ifu_iccm_mem.scala 38:55] node _T_60 = bits(wren_bank_1, 0, 0) @[el2_ifu_iccm_mem.scala 38:69] node _T_61 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92] node _T_62 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23] node _T_63 = eq(_T_62, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 39:41] node _T_64 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62] node _T_65 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112] node _T_66 = mux(_T_63, _T_64, _T_65) @[el2_ifu_iccm_mem.scala 39:8] node addr_bank_1 = mux(_T_60, _T_61, _T_66) @[el2_ifu_iccm_mem.scala 38:55] node _T_67 = bits(wren_bank_2, 0, 0) @[el2_ifu_iccm_mem.scala 38:69] node _T_68 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92] node _T_69 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23] node _T_70 = eq(_T_69, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 39:41] node _T_71 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62] node _T_72 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112] node _T_73 = mux(_T_70, _T_71, _T_72) @[el2_ifu_iccm_mem.scala 39:8] node addr_bank_2 = mux(_T_67, _T_68, _T_73) @[el2_ifu_iccm_mem.scala 38:55] node _T_74 = bits(wren_bank_3, 0, 0) @[el2_ifu_iccm_mem.scala 38:69] node _T_75 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92] node _T_76 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23] node _T_77 = eq(_T_76, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 39:41] node _T_78 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62] node _T_79 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112] node _T_80 = mux(_T_77, _T_78, _T_79) @[el2_ifu_iccm_mem.scala 39:8] node addr_bank_3 = mux(_T_74, _T_75, _T_80) @[el2_ifu_iccm_mem.scala 38:55] cmem iccm_mem : UInt<39>[4][4096] @[el2_ifu_iccm_mem.scala 41:21] node _T_81 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 43:68] node _T_82 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 43:68] node _T_83 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 43:68] node _T_84 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 43:68] wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 43:51] write_vec[0] <= _T_81 @[el2_ifu_iccm_mem.scala 43:51] write_vec[1] <= _T_82 @[el2_ifu_iccm_mem.scala 43:51] write_vec[2] <= _T_83 @[el2_ifu_iccm_mem.scala 43:51] write_vec[3] <= _T_84 @[el2_ifu_iccm_mem.scala 43:51] node _T_85 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72] node _T_86 = and(iccm_clken_0, _T_85) @[el2_ifu_iccm_mem.scala 44:70] node _T_87 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72] node _T_88 = and(iccm_clken_1, _T_87) @[el2_ifu_iccm_mem.scala 44:70] node _T_89 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72] node _T_90 = and(iccm_clken_2, _T_89) @[el2_ifu_iccm_mem.scala 44:70] node _T_91 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72] node _T_92 = and(iccm_clken_3, _T_91) @[el2_ifu_iccm_mem.scala 44:70] wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 44:53] read_enable[0] <= _T_86 @[el2_ifu_iccm_mem.scala 44:53] read_enable[1] <= _T_88 @[el2_ifu_iccm_mem.scala 44:53] read_enable[2] <= _T_90 @[el2_ifu_iccm_mem.scala 44:53] read_enable[3] <= _T_92 @[el2_ifu_iccm_mem.scala 44:53] wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 46:28] node _T_93 = bits(write_vec[0], 0, 0) @[el2_ifu_iccm_mem.scala 49:53] when _T_93 : @[el2_ifu_iccm_mem.scala 49:60] infer mport _T_94 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 49:69] _T_94[0] <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 49:87] skip @[el2_ifu_iccm_mem.scala 49:60] node _T_95 = bits(write_vec[1], 0, 0) @[el2_ifu_iccm_mem.scala 49:53] when _T_95 : @[el2_ifu_iccm_mem.scala 49:60] infer mport _T_96 = iccm_mem[addr_bank_1], clock @[el2_ifu_iccm_mem.scala 49:69] _T_96[1] <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 49:87] skip @[el2_ifu_iccm_mem.scala 49:60] node _T_97 = bits(write_vec[2], 0, 0) @[el2_ifu_iccm_mem.scala 49:53] when _T_97 : @[el2_ifu_iccm_mem.scala 49:60] infer mport _T_98 = iccm_mem[addr_bank_2], clock @[el2_ifu_iccm_mem.scala 49:69] _T_98[2] <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 49:87] skip @[el2_ifu_iccm_mem.scala 49:60] node _T_99 = bits(write_vec[3], 0, 0) @[el2_ifu_iccm_mem.scala 49:53] when _T_99 : @[el2_ifu_iccm_mem.scala 49:60] infer mport _T_100 = iccm_mem[addr_bank_3], clock @[el2_ifu_iccm_mem.scala 49:69] _T_100[3] <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 49:87] skip @[el2_ifu_iccm_mem.scala 49:60] infer mport _T_101 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 51:68] wire _T_102 : UInt<1>[4] @[el2_ifu_iccm_mem.scala 51:115] _T_102[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_102[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_102[2] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_102[3] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] reg _T_103 : UInt<39>[4], clock with : (reset => (reset, _T_102)) @[el2_ifu_iccm_mem.scala 51:59] _T_103[0] <= _T_101[0] @[el2_ifu_iccm_mem.scala 51:59] _T_103[1] <= _T_101[1] @[el2_ifu_iccm_mem.scala 51:59] _T_103[2] <= _T_101[2] @[el2_ifu_iccm_mem.scala 51:59] _T_103[3] <= _T_101[3] @[el2_ifu_iccm_mem.scala 51:59] iccm_bank_dout[0] <= _T_103[0] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[1] <= _T_103[1] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[2] <= _T_103[2] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[3] <= _T_103[3] @[el2_ifu_iccm_mem.scala 51:49] infer mport _T_104 = iccm_mem[addr_bank_1], clock @[el2_ifu_iccm_mem.scala 51:68] wire _T_105 : UInt<1>[4] @[el2_ifu_iccm_mem.scala 51:115] _T_105[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_105[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_105[2] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_105[3] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] reg _T_106 : UInt<39>[4], clock with : (reset => (reset, _T_105)) @[el2_ifu_iccm_mem.scala 51:59] _T_106[0] <= _T_104[0] @[el2_ifu_iccm_mem.scala 51:59] _T_106[1] <= _T_104[1] @[el2_ifu_iccm_mem.scala 51:59] _T_106[2] <= _T_104[2] @[el2_ifu_iccm_mem.scala 51:59] _T_106[3] <= _T_104[3] @[el2_ifu_iccm_mem.scala 51:59] iccm_bank_dout[0] <= _T_106[0] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[1] <= _T_106[1] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[2] <= _T_106[2] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[3] <= _T_106[3] @[el2_ifu_iccm_mem.scala 51:49] infer mport _T_107 = iccm_mem[addr_bank_2], clock @[el2_ifu_iccm_mem.scala 51:68] wire _T_108 : UInt<1>[4] @[el2_ifu_iccm_mem.scala 51:115] _T_108[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_108[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_108[2] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_108[3] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] reg _T_109 : UInt<39>[4], clock with : (reset => (reset, _T_108)) @[el2_ifu_iccm_mem.scala 51:59] _T_109[0] <= _T_107[0] @[el2_ifu_iccm_mem.scala 51:59] _T_109[1] <= _T_107[1] @[el2_ifu_iccm_mem.scala 51:59] _T_109[2] <= _T_107[2] @[el2_ifu_iccm_mem.scala 51:59] _T_109[3] <= _T_107[3] @[el2_ifu_iccm_mem.scala 51:59] iccm_bank_dout[0] <= _T_109[0] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[1] <= _T_109[1] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[2] <= _T_109[2] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[3] <= _T_109[3] @[el2_ifu_iccm_mem.scala 51:49] infer mport _T_110 = iccm_mem[addr_bank_3], clock @[el2_ifu_iccm_mem.scala 51:68] wire _T_111 : UInt<1>[4] @[el2_ifu_iccm_mem.scala 51:115] _T_111[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_111[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_111[2] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] _T_111[3] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115] reg _T_112 : UInt<39>[4], clock with : (reset => (reset, _T_111)) @[el2_ifu_iccm_mem.scala 51:59] _T_112[0] <= _T_110[0] @[el2_ifu_iccm_mem.scala 51:59] _T_112[1] <= _T_110[1] @[el2_ifu_iccm_mem.scala 51:59] _T_112[2] <= _T_110[2] @[el2_ifu_iccm_mem.scala 51:59] _T_112[3] <= _T_110[3] @[el2_ifu_iccm_mem.scala 51:59] iccm_bank_dout[0] <= _T_112[0] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[1] <= _T_112[1] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[2] <= _T_112[2] @[el2_ifu_iccm_mem.scala 51:49] iccm_bank_dout[3] <= _T_112[3] @[el2_ifu_iccm_mem.scala 51:49] io.iccm_bank_addr[0] <= addr_bank_0 @[el2_ifu_iccm_mem.scala 56:21] io.iccm_bank_addr[1] <= addr_bank_1 @[el2_ifu_iccm_mem.scala 56:21] io.iccm_bank_addr[2] <= addr_bank_2 @[el2_ifu_iccm_mem.scala 56:21] io.iccm_bank_addr[3] <= addr_bank_3 @[el2_ifu_iccm_mem.scala 56:21] wire redundant_valid : UInt<2> redundant_valid <= UInt<1>("h00") wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 62:31] redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 63:21] redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 63:21] node _T_113 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67] node _T_114 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90] node _T_115 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128] node _T_116 = eq(_T_114, _T_115) @[el2_ifu_iccm_mem.scala 65:105] node _T_117 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163] node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 65:169] node _T_119 = and(_T_116, _T_118) @[el2_ifu_iccm_mem.scala 65:145] node _T_120 = and(_T_113, _T_119) @[el2_ifu_iccm_mem.scala 65:71] node _T_121 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22] node _T_122 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60] node _T_123 = eq(_T_121, _T_122) @[el2_ifu_iccm_mem.scala 66:37] node _T_124 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93] node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 66:99] node _T_126 = and(_T_123, _T_125) @[el2_ifu_iccm_mem.scala 66:77] node _T_127 = or(_T_120, _T_126) @[el2_ifu_iccm_mem.scala 65:179] node _T_128 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67] node _T_129 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90] node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128] node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 65:105] node _T_132 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163] node _T_133 = eq(_T_132, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 65:169] node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 65:145] node _T_135 = and(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 65:71] node _T_136 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22] node _T_137 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60] node _T_138 = eq(_T_136, _T_137) @[el2_ifu_iccm_mem.scala 66:37] node _T_139 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93] node _T_140 = eq(_T_139, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 66:99] node _T_141 = and(_T_138, _T_140) @[el2_ifu_iccm_mem.scala 66:77] node _T_142 = or(_T_135, _T_141) @[el2_ifu_iccm_mem.scala 65:179] node _T_143 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67] node _T_144 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90] node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128] node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 65:105] node _T_147 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163] node _T_148 = eq(_T_147, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 65:169] node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 65:145] node _T_150 = and(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 65:71] node _T_151 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22] node _T_152 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60] node _T_153 = eq(_T_151, _T_152) @[el2_ifu_iccm_mem.scala 66:37] node _T_154 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93] node _T_155 = eq(_T_154, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 66:99] node _T_156 = and(_T_153, _T_155) @[el2_ifu_iccm_mem.scala 66:77] node _T_157 = or(_T_150, _T_156) @[el2_ifu_iccm_mem.scala 65:179] node _T_158 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67] node _T_159 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90] node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128] node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 65:105] node _T_162 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163] node _T_163 = eq(_T_162, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 65:169] node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 65:145] node _T_165 = and(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 65:71] node _T_166 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22] node _T_167 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60] node _T_168 = eq(_T_166, _T_167) @[el2_ifu_iccm_mem.scala 66:37] node _T_169 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93] node _T_170 = eq(_T_169, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 66:99] node _T_171 = and(_T_168, _T_170) @[el2_ifu_iccm_mem.scala 66:77] node _T_172 = or(_T_165, _T_171) @[el2_ifu_iccm_mem.scala 65:179] node _T_173 = cat(_T_172, _T_157) @[Cat.scala 29:58] node _T_174 = cat(_T_173, _T_142) @[Cat.scala 29:58] node sel_red1 = cat(_T_174, _T_127) @[Cat.scala 29:58] node _T_175 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67] node _T_176 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90] node _T_177 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128] node _T_178 = eq(_T_176, _T_177) @[el2_ifu_iccm_mem.scala 67:105] node _T_179 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163] node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 67:169] node _T_181 = and(_T_178, _T_180) @[el2_ifu_iccm_mem.scala 67:145] node _T_182 = and(_T_175, _T_181) @[el2_ifu_iccm_mem.scala 67:71] node _T_183 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22] node _T_184 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60] node _T_185 = eq(_T_183, _T_184) @[el2_ifu_iccm_mem.scala 68:37] node _T_186 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93] node _T_187 = eq(_T_186, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 68:99] node _T_188 = and(_T_185, _T_187) @[el2_ifu_iccm_mem.scala 68:77] node _T_189 = or(_T_182, _T_188) @[el2_ifu_iccm_mem.scala 67:179] node _T_190 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67] node _T_191 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90] node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128] node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 67:105] node _T_194 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163] node _T_195 = eq(_T_194, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 67:169] node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 67:145] node _T_197 = and(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 67:71] node _T_198 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22] node _T_199 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60] node _T_200 = eq(_T_198, _T_199) @[el2_ifu_iccm_mem.scala 68:37] node _T_201 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93] node _T_202 = eq(_T_201, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 68:99] node _T_203 = and(_T_200, _T_202) @[el2_ifu_iccm_mem.scala 68:77] node _T_204 = or(_T_197, _T_203) @[el2_ifu_iccm_mem.scala 67:179] node _T_205 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67] node _T_206 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90] node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128] node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 67:105] node _T_209 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163] node _T_210 = eq(_T_209, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 67:169] node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 67:145] node _T_212 = and(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 67:71] node _T_213 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22] node _T_214 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60] node _T_215 = eq(_T_213, _T_214) @[el2_ifu_iccm_mem.scala 68:37] node _T_216 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93] node _T_217 = eq(_T_216, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 68:99] node _T_218 = and(_T_215, _T_217) @[el2_ifu_iccm_mem.scala 68:77] node _T_219 = or(_T_212, _T_218) @[el2_ifu_iccm_mem.scala 67:179] node _T_220 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67] node _T_221 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90] node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128] node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 67:105] node _T_224 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163] node _T_225 = eq(_T_224, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 67:169] node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 67:145] node _T_227 = and(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 67:71] node _T_228 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22] node _T_229 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60] node _T_230 = eq(_T_228, _T_229) @[el2_ifu_iccm_mem.scala 68:37] node _T_231 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93] node _T_232 = eq(_T_231, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 68:99] node _T_233 = and(_T_230, _T_232) @[el2_ifu_iccm_mem.scala 68:77] node _T_234 = or(_T_227, _T_233) @[el2_ifu_iccm_mem.scala 67:179] node _T_235 = cat(_T_234, _T_219) @[Cat.scala 29:58] node _T_236 = cat(_T_235, _T_204) @[Cat.scala 29:58] node sel_red0 = cat(_T_236, _T_189) @[Cat.scala 29:58] reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 70:27] sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 70:27] reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 71:27] sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 71:27] wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 72:28] redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 73:18] redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 73:18] node _T_237 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 75:47] node _T_238 = bits(_T_237, 0, 0) @[el2_ifu_iccm_mem.scala 75:51] node _T_239 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 76:47] node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_iccm_mem.scala 76:51] node _T_241 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 77:47] node _T_242 = not(_T_241) @[el2_ifu_iccm_mem.scala 77:36] node _T_243 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 77:64] node _T_244 = not(_T_243) @[el2_ifu_iccm_mem.scala 77:53] node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 77:51] node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 77:69] node _T_247 = mux(_T_238, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_248 = mux(_T_240, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_249 = mux(_T_246, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_250 = or(_T_247, _T_248) @[Mux.scala 27:72] node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72] wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72] iccm_bank_dout_fn_0 <= _T_251 @[Mux.scala 27:72] node _T_252 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 75:47] node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_iccm_mem.scala 75:51] node _T_254 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 76:47] node _T_255 = bits(_T_254, 0, 0) @[el2_ifu_iccm_mem.scala 76:51] node _T_256 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 77:47] node _T_257 = not(_T_256) @[el2_ifu_iccm_mem.scala 77:36] node _T_258 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 77:64] node _T_259 = not(_T_258) @[el2_ifu_iccm_mem.scala 77:53] node _T_260 = and(_T_257, _T_259) @[el2_ifu_iccm_mem.scala 77:51] node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 77:69] node _T_262 = mux(_T_253, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_263 = mux(_T_255, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_264 = mux(_T_261, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_265 = or(_T_262, _T_263) @[Mux.scala 27:72] node _T_266 = or(_T_265, _T_264) @[Mux.scala 27:72] wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72] iccm_bank_dout_fn_1 <= _T_266 @[Mux.scala 27:72] node _T_267 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 75:47] node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_iccm_mem.scala 75:51] node _T_269 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 76:47] node _T_270 = bits(_T_269, 0, 0) @[el2_ifu_iccm_mem.scala 76:51] node _T_271 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 77:47] node _T_272 = not(_T_271) @[el2_ifu_iccm_mem.scala 77:36] node _T_273 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 77:64] node _T_274 = not(_T_273) @[el2_ifu_iccm_mem.scala 77:53] node _T_275 = and(_T_272, _T_274) @[el2_ifu_iccm_mem.scala 77:51] node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 77:69] node _T_277 = mux(_T_268, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_278 = mux(_T_270, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_279 = mux(_T_276, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_280 = or(_T_277, _T_278) @[Mux.scala 27:72] node _T_281 = or(_T_280, _T_279) @[Mux.scala 27:72] wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72] iccm_bank_dout_fn_2 <= _T_281 @[Mux.scala 27:72] node _T_282 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 75:47] node _T_283 = bits(_T_282, 0, 0) @[el2_ifu_iccm_mem.scala 75:51] node _T_284 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 76:47] node _T_285 = bits(_T_284, 0, 0) @[el2_ifu_iccm_mem.scala 76:51] node _T_286 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 77:47] node _T_287 = not(_T_286) @[el2_ifu_iccm_mem.scala 77:36] node _T_288 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 77:64] node _T_289 = not(_T_288) @[el2_ifu_iccm_mem.scala 77:53] node _T_290 = and(_T_287, _T_289) @[el2_ifu_iccm_mem.scala 77:51] node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 77:69] node _T_292 = mux(_T_283, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_293 = mux(_T_285, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_294 = mux(_T_291, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72] node _T_295 = or(_T_292, _T_293) @[Mux.scala 27:72] node _T_296 = or(_T_295, _T_294) @[Mux.scala 27:72] wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72] iccm_bank_dout_fn_3 <= _T_296 @[Mux.scala 27:72] wire redundant_lru : UInt<1> redundant_lru <= UInt<1>("h00") node _T_297 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 79:20] node r0_addr_en = and(_T_297, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 79:35] node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 80:35] node _T_298 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 81:63] node _T_299 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 81:78] node _T_300 = or(_T_298, _T_299) @[el2_ifu_iccm_mem.scala 81:67] node _T_301 = and(_T_300, io.iccm_rden) @[el2_ifu_iccm_mem.scala 81:83] node _T_302 = and(_T_301, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 81:98] node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_302) @[el2_ifu_iccm_mem.scala 81:50] node _T_303 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 82:55] node _T_304 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 82:84] node _T_305 = mux(_T_304, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 82:74] node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_303, _T_305) @[el2_ifu_iccm_mem.scala 82:29] reg _T_306 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when redundant_lru_en : @[Reg.scala 28:19] _T_306 <= redundant_lru_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] redundant_lru <= _T_306 @[el2_ifu_iccm_mem.scala 83:17] node _T_307 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 84:52] reg _T_308 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when r0_addr_en : @[Reg.scala 28:19] _T_308 <= _T_307 @[Reg.scala 28:23] skip @[Reg.scala 28:19] redundant_address[0] <= _T_308 @[el2_ifu_iccm_mem.scala 84:24] node _T_309 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 85:52] node _T_310 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 85:85] reg _T_311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_310 : @[Reg.scala 28:19] _T_311 <= _T_309 @[Reg.scala 28:23] skip @[Reg.scala 28:19] redundant_address[1] <= _T_311 @[el2_ifu_iccm_mem.scala 85:24] node _T_312 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 86:57] reg _T_313 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_312 : @[Reg.scala 28:19] _T_313 <= UInt<1>("h01") @[Reg.scala 28:23] skip @[Reg.scala 28:19] reg _T_314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when r0_addr_en : @[Reg.scala 28:19] _T_314 <= UInt<1>("h01") @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_315 = cat(_T_313, _T_314) @[Cat.scala 29:58] redundant_valid <= _T_315 @[el2_ifu_iccm_mem.scala 86:19] node _T_316 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 88:45] node _T_317 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 88:85] node _T_318 = eq(_T_316, _T_317) @[el2_ifu_iccm_mem.scala 88:61] node _T_319 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:22] node _T_320 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 89:48] node _T_321 = and(_T_319, _T_320) @[el2_ifu_iccm_mem.scala 89:26] node _T_322 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:70] node _T_323 = eq(_T_322, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:75] node _T_324 = or(_T_321, _T_323) @[el2_ifu_iccm_mem.scala 89:52] node _T_325 = and(_T_318, _T_324) @[el2_ifu_iccm_mem.scala 88:102] node _T_326 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 89:101] node _T_327 = and(_T_325, _T_326) @[el2_ifu_iccm_mem.scala 89:84] node _T_328 = and(_T_327, io.iccm_wren) @[el2_ifu_iccm_mem.scala 89:105] node _T_329 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 90:6] node _T_330 = and(_T_329, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 90:21] node redundant_data0_en = or(_T_328, _T_330) @[el2_ifu_iccm_mem.scala 89:121] node _T_331 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 91:49] node _T_332 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 91:73] node _T_333 = and(_T_331, _T_332) @[el2_ifu_iccm_mem.scala 91:52] node _T_334 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 91:100] node _T_335 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 91:122] node _T_336 = eq(_T_335, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 91:127] node _T_337 = and(_T_334, _T_336) @[el2_ifu_iccm_mem.scala 91:104] node _T_338 = or(_T_333, _T_337) @[el2_ifu_iccm_mem.scala 91:78] node _T_339 = bits(_T_338, 0, 0) @[el2_ifu_iccm_mem.scala 91:137] node _T_340 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 92:20] node _T_341 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 92:44] node redundant_data0_in = mux(_T_339, _T_340, _T_341) @[el2_ifu_iccm_mem.scala 91:31] node _T_342 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 93:78] reg _T_343 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_342 : @[Reg.scala 28:19] _T_343 <= redundant_data0_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] redundant_data[0] <= _T_343 @[el2_ifu_iccm_mem.scala 93:21] node _T_344 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 95:45] node _T_345 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 95:85] node _T_346 = eq(_T_344, _T_345) @[el2_ifu_iccm_mem.scala 95:61] node _T_347 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:22] node _T_348 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 96:48] node _T_349 = and(_T_347, _T_348) @[el2_ifu_iccm_mem.scala 96:26] node _T_350 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:70] node _T_351 = eq(_T_350, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:75] node _T_352 = or(_T_349, _T_351) @[el2_ifu_iccm_mem.scala 96:52] node _T_353 = and(_T_346, _T_352) @[el2_ifu_iccm_mem.scala 95:102] node _T_354 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 96:101] node _T_355 = and(_T_353, _T_354) @[el2_ifu_iccm_mem.scala 96:84] node _T_356 = and(_T_355, io.iccm_wren) @[el2_ifu_iccm_mem.scala 96:105] node _T_357 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:6] node _T_358 = and(_T_357, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 97:21] node redundant_data1_en = or(_T_356, _T_358) @[el2_ifu_iccm_mem.scala 96:121] node _T_359 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 98:49] node _T_360 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 98:73] node _T_361 = and(_T_359, _T_360) @[el2_ifu_iccm_mem.scala 98:52] node _T_362 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 98:100] node _T_363 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 98:122] node _T_364 = eq(_T_363, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 98:127] node _T_365 = and(_T_362, _T_364) @[el2_ifu_iccm_mem.scala 98:104] node _T_366 = or(_T_361, _T_365) @[el2_ifu_iccm_mem.scala 98:78] node _T_367 = bits(_T_366, 0, 0) @[el2_ifu_iccm_mem.scala 98:137] node _T_368 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 99:20] node _T_369 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 99:44] node redundant_data1_in = mux(_T_367, _T_368, _T_369) @[el2_ifu_iccm_mem.scala 98:31] node _T_370 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 100:78] reg _T_371 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_370 : @[Reg.scala 28:19] _T_371 <= redundant_data1_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 100:21] node _T_372 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 102:50] reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 102:34] iccm_rd_addr_lo_q <= _T_372 @[el2_ifu_iccm_mem.scala 102:34] node _T_373 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48] reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 103:34] iccm_rd_addr_hi_q <= _T_373 @[el2_ifu_iccm_mem.scala 103:34] node _T_374 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 105:86] node _T_375 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 105:115] node _T_376 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 105:86] node _T_377 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 105:115] node _T_378 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 105:86] node _T_379 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 105:115] node _T_380 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 105:86] node _T_381 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 105:115] node _T_382 = mux(_T_374, _T_375, UInt<1>("h00")) @[Mux.scala 27:72] node _T_383 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72] node _T_384 = mux(_T_378, _T_379, UInt<1>("h00")) @[Mux.scala 27:72] node _T_385 = mux(_T_380, _T_381, UInt<1>("h00")) @[Mux.scala 27:72] node _T_386 = or(_T_382, _T_383) @[Mux.scala 27:72] node _T_387 = or(_T_386, _T_384) @[Mux.scala 27:72] node _T_388 = or(_T_387, _T_385) @[Mux.scala 27:72] wire _T_389 : UInt<32> @[Mux.scala 27:72] _T_389 <= _T_388 @[Mux.scala 27:72] node _T_390 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59] node _T_391 = eq(_T_390, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:77] node _T_392 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 106:106] node _T_393 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59] node _T_394 = eq(_T_393, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:77] node _T_395 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 106:106] node _T_396 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59] node _T_397 = eq(_T_396, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:77] node _T_398 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 106:106] node _T_399 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59] node _T_400 = eq(_T_399, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:77] node _T_401 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 106:106] node _T_402 = mux(_T_391, _T_392, UInt<1>("h00")) @[Mux.scala 27:72] node _T_403 = mux(_T_394, _T_395, UInt<1>("h00")) @[Mux.scala 27:72] node _T_404 = mux(_T_397, _T_398, UInt<1>("h00")) @[Mux.scala 27:72] node _T_405 = mux(_T_400, _T_401, UInt<1>("h00")) @[Mux.scala 27:72] node _T_406 = or(_T_402, _T_403) @[Mux.scala 27:72] node _T_407 = or(_T_406, _T_404) @[Mux.scala 27:72] node _T_408 = or(_T_407, _T_405) @[Mux.scala 27:72] wire _T_409 : UInt<32> @[Mux.scala 27:72] _T_409 <= _T_408 @[Mux.scala 27:72] node iccm_rd_data_pre = cat(_T_389, _T_409) @[Cat.scala 29:58] node _T_410 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 107:43] node _T_411 = bits(_T_410, 0, 0) @[el2_ifu_iccm_mem.scala 107:53] node _T_412 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] node _T_413 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 107:89] node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58] node _T_415 = mux(_T_411, _T_414, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 107:25] io.iccm_rd_data <= _T_415 @[el2_ifu_iccm_mem.scala 107:19] node _T_416 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 108:85] node _T_417 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 108:85] node _T_418 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 108:85] node _T_419 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 108:85] node _T_420 = mux(_T_416, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_421 = mux(_T_417, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_422 = mux(_T_418, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] node _T_423 = mux(_T_419, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] node _T_424 = or(_T_420, _T_421) @[Mux.scala 27:72] node _T_425 = or(_T_424, _T_422) @[Mux.scala 27:72] node _T_426 = or(_T_425, _T_423) @[Mux.scala 27:72] wire _T_427 : UInt<39> @[Mux.scala 27:72] _T_427 <= _T_426 @[Mux.scala 27:72] node _T_428 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61] node _T_429 = eq(_T_428, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 109:79] node _T_430 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61] node _T_431 = eq(_T_430, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 109:79] node _T_432 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61] node _T_433 = eq(_T_432, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 109:79] node _T_434 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61] node _T_435 = eq(_T_434, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 109:79] node _T_436 = mux(_T_429, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_437 = mux(_T_431, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_438 = mux(_T_433, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] node _T_439 = mux(_T_435, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] node _T_440 = or(_T_436, _T_437) @[Mux.scala 27:72] node _T_441 = or(_T_440, _T_438) @[Mux.scala 27:72] node _T_442 = or(_T_441, _T_439) @[Mux.scala 27:72] wire _T_443 : UInt<39> @[Mux.scala 27:72] _T_443 <= _T_442 @[Mux.scala 27:72] node _T_444 = cat(_T_427, _T_443) @[Cat.scala 29:58] io.iccm_rd_data_ecc <= _T_444 @[el2_ifu_iccm_mem.scala 108:23]