[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~dbg|dbg>io_dbg_resume_req",
    "sources":[
      "~dbg|dbg>io_dec_tlu_mpc_halted_only",
      "~dbg|dbg>io_core_dbg_cmd_done",
      "~dbg|dbg>io_dbg_dec_dma_dbg_ib_dbg_cmd_valid",
      "~dbg|dbg>io_dbg_dma_dma_dbg_ready",
      "~dbg|dbg>io_dbg_bus_clk_en",
      "~dbg|dbg>io_sb_axi_r_valid",
      "~dbg|dbg>io_sb_axi_r_ready",
      "~dbg|dbg>io_sb_axi_b_valid",
      "~dbg|dbg>io_sb_axi_b_ready",
      "~dbg|dbg>reset",
      "~dbg|dbg>io_sb_axi_ar_valid",
      "~dbg|dbg>io_sb_axi_ar_ready",
      "~dbg|dbg>io_sb_axi_aw_valid",
      "~dbg|dbg>io_sb_axi_aw_ready",
      "~dbg|dbg>io_sb_axi_w_valid",
      "~dbg|dbg>io_sb_axi_w_ready"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~dbg|dbg>io_dbg_core_rst_l",
    "sources":[
      "~dbg|dbg>io_scan_mode"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~dbg|dbg>io_dbg_dec_dma_dbg_ib_dbg_cmd_valid",
    "sources":[
      "~dbg|dbg>io_dbg_dma_dma_dbg_ready"
    ]
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.transforms.BlackBoxResourceAnno",
    "target":"dbg.gated_latch",
    "resourceId":"/vsrc/gated_latch.sv"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"dbg"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]