[
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      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_way_f",
    "sources":[
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_index",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_btag",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_pkt_misp"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
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    "sources":[
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
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    "sources":[
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb"
    ]
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  {
    "class":"firrtl.transforms.CombinationalPath",
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    "sources":[
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_valid_f",
    "sources":[
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_bpred_disable",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb"
    ]
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
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  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]