[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test",
    "sources":[
      "~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
      "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
      "~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
      "~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
      "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
      "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
      "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
      "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
      "~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
    ]
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"EL2_IC_DATA"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]