[ { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_1", "sources":[ "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_0", "sources":[ "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_2", "sources":[ "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_3", "sources":[ "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data" ] }, { "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" }, { "class":"firrtl.options.TargetDirAnnotation", "directory":"." }, { "class":"firrtl.options.OutputAnnotationFileAnnotation", "file":"el2_ifu_iccm_mem" }, { "class":"firrtl.transforms.BlackBoxTargetDirAnno", "targetDir":"." } ]