[ { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall", "sources":[ "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "~el2_ifu|el2_ifu>io_ic_rd_data", "~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_iccm_wren", "sources":[ "~el2_ifu|el2_ifu>io_dma_mem_write", "~el2_ifu|el2_ifu>io_dma_iccm_req", "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", "~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "~el2_ifu|el2_ifu>io_ic_rd_data" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ic_debug_addr", "sources":[ "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ic_debug_way", "sources":[ "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ic_debug_rd_en", "sources":[ "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_rd_valid" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_iccm_wr_data", "sources":[ "~el2_ifu|el2_ifu>io_dma_iccm_req", "~el2_ifu|el2_ifu>io_dma_mem_wdata", "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", "~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "~el2_ifu|el2_ifu>io_ic_rd_data" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_iccm_wr_size", "sources":[ "~el2_ifu|el2_ifu>io_dma_mem_sz", "~el2_ifu|el2_ifu>io_dma_iccm_req" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_en", "sources":[ "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wr_valid" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ifu_ic_error_start", "sources":[ "~el2_ifu|el2_ifu>io_ic_eccerr", "~el2_ifu|el2_ifu>io_ic_tag_perr", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_ifu_axi_rid", "~el2_ifu|el2_ifu>io_ifu_axi_rvalid", "~el2_ifu|el2_ifu>io_ifu_bus_clk_en", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_iccm_dma_ecc_error", "sources":[ "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_iccm_rden", "sources":[ "~el2_ifu|el2_ifu>io_dma_iccm_req", "~el2_ifu|el2_ifu>io_dma_mem_write", "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "~el2_ifu|el2_ifu>io_ic_rd_data", "~el2_ifu|el2_ifu>io_dec_i0_decode_d" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ifu_pmu_instr_aligned", "sources":[ "~el2_ifu|el2_ifu>io_dec_i0_decode_d" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error", "sources":[ "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array", "sources":[ "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ic_rw_addr", "sources":[ "~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ifu_iccm_rd_ecc_single_err", "sources":[ "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ic_tag_valid", "sources":[ "~el2_ifu|el2_ifu>io_exu_flush_final" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ic_rd_en", "sources":[ "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_dec_tlu_force_halt", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", "~el2_ifu|el2_ifu>io_dec_tlu_mrac_ff", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "~el2_ifu|el2_ifu>io_ic_rd_data", "~el2_ifu|el2_ifu>io_dec_i0_decode_d" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_iccm_rw_addr", "sources":[ "~el2_ifu|el2_ifu>io_dma_mem_addr", "~el2_ifu|el2_ifu>io_dma_iccm_req", "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "~el2_ifu|el2_ifu>io_ic_rd_data" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_data", "sources":[ "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wrdata" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_iccm_ready", "sources":[ "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", "~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "~el2_ifu|el2_ifu>io_ic_rd_data" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data", "sources":[ "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_ifu_axi_rid", "~el2_ifu|el2_ifu>io_ifu_axi_rvalid", "~el2_ifu|el2_ifu>io_ifu_bus_clk_en", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" ] }, { "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" }, { "class":"firrtl.options.TargetDirAnnotation", "directory":"." }, { "class":"firrtl.options.OutputAnnotationFileAnnotation", "file":"el2_ifu" }, { "class":"firrtl.transforms.BlackBoxTargetDirAnno", "targetDir":"." } ]