;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit rvdffs : module rvdffs : input clock : Clock input reset : UInt<1> output io : {flip din : UInt<32>, flip en : UInt<1>, flip clear : UInt<1>, out : UInt} wire _T : UInt<1>[32] @[el2_lib.scala 40:24] _T[0] <= io.clear @[el2_lib.scala 40:24] _T[1] <= io.clear @[el2_lib.scala 40:24] _T[2] <= io.clear @[el2_lib.scala 40:24] _T[3] <= io.clear @[el2_lib.scala 40:24] _T[4] <= io.clear @[el2_lib.scala 40:24] _T[5] <= io.clear @[el2_lib.scala 40:24] _T[6] <= io.clear @[el2_lib.scala 40:24] _T[7] <= io.clear @[el2_lib.scala 40:24] _T[8] <= io.clear @[el2_lib.scala 40:24] _T[9] <= io.clear @[el2_lib.scala 40:24] _T[10] <= io.clear @[el2_lib.scala 40:24] _T[11] <= io.clear @[el2_lib.scala 40:24] _T[12] <= io.clear @[el2_lib.scala 40:24] _T[13] <= io.clear @[el2_lib.scala 40:24] _T[14] <= io.clear @[el2_lib.scala 40:24] _T[15] <= io.clear @[el2_lib.scala 40:24] _T[16] <= io.clear @[el2_lib.scala 40:24] _T[17] <= io.clear @[el2_lib.scala 40:24] _T[18] <= io.clear @[el2_lib.scala 40:24] _T[19] <= io.clear @[el2_lib.scala 40:24] _T[20] <= io.clear @[el2_lib.scala 40:24] _T[21] <= io.clear @[el2_lib.scala 40:24] _T[22] <= io.clear @[el2_lib.scala 40:24] _T[23] <= io.clear @[el2_lib.scala 40:24] _T[24] <= io.clear @[el2_lib.scala 40:24] _T[25] <= io.clear @[el2_lib.scala 40:24] _T[26] <= io.clear @[el2_lib.scala 40:24] _T[27] <= io.clear @[el2_lib.scala 40:24] _T[28] <= io.clear @[el2_lib.scala 40:24] _T[29] <= io.clear @[el2_lib.scala 40:24] _T[30] <= io.clear @[el2_lib.scala 40:24] _T[31] <= io.clear @[el2_lib.scala 40:24] node _T_1 = cat(_T[0], _T[1]) @[Cat.scala 29:58] node _T_2 = cat(_T_1, _T[2]) @[Cat.scala 29:58] node _T_3 = cat(_T_2, _T[3]) @[Cat.scala 29:58] node _T_4 = cat(_T_3, _T[4]) @[Cat.scala 29:58] node _T_5 = cat(_T_4, _T[5]) @[Cat.scala 29:58] node _T_6 = cat(_T_5, _T[6]) @[Cat.scala 29:58] node _T_7 = cat(_T_6, _T[7]) @[Cat.scala 29:58] node _T_8 = cat(_T_7, _T[8]) @[Cat.scala 29:58] node _T_9 = cat(_T_8, _T[9]) @[Cat.scala 29:58] node _T_10 = cat(_T_9, _T[10]) @[Cat.scala 29:58] node _T_11 = cat(_T_10, _T[11]) @[Cat.scala 29:58] node _T_12 = cat(_T_11, _T[12]) @[Cat.scala 29:58] node _T_13 = cat(_T_12, _T[13]) @[Cat.scala 29:58] node _T_14 = cat(_T_13, _T[14]) @[Cat.scala 29:58] node _T_15 = cat(_T_14, _T[15]) @[Cat.scala 29:58] node _T_16 = cat(_T_15, _T[16]) @[Cat.scala 29:58] node _T_17 = cat(_T_16, _T[17]) @[Cat.scala 29:58] node _T_18 = cat(_T_17, _T[18]) @[Cat.scala 29:58] node _T_19 = cat(_T_18, _T[19]) @[Cat.scala 29:58] node _T_20 = cat(_T_19, _T[20]) @[Cat.scala 29:58] node _T_21 = cat(_T_20, _T[21]) @[Cat.scala 29:58] node _T_22 = cat(_T_21, _T[22]) @[Cat.scala 29:58] node _T_23 = cat(_T_22, _T[23]) @[Cat.scala 29:58] node _T_24 = cat(_T_23, _T[24]) @[Cat.scala 29:58] node _T_25 = cat(_T_24, _T[25]) @[Cat.scala 29:58] node _T_26 = cat(_T_25, _T[26]) @[Cat.scala 29:58] node _T_27 = cat(_T_26, _T[27]) @[Cat.scala 29:58] node _T_28 = cat(_T_27, _T[28]) @[Cat.scala 29:58] node _T_29 = cat(_T_28, _T[29]) @[Cat.scala 29:58] node _T_30 = cat(_T_29, _T[30]) @[Cat.scala 29:58] node _T_31 = cat(_T_30, _T[31]) @[Cat.scala 29:58] node _T_32 = and(io.din, _T_31) @[el2_ifu_ic_mem.scala 93:30] reg _T_33 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.en : @[Reg.scala 28:19] _T_33 <= _T_32 @[Reg.scala 28:23] skip @[Reg.scala 28:19] io.out <= _T_33 @[el2_ifu_ic_mem.scala 93:10]