;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit axi4_to_ahb : extmodule gated_latch : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> defname = gated_latch module rvclkhdr : input clock : Clock input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} inst clkhdr of gated_latch @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid io.l1clk <= clkhdr.Q @[lib.scala 335:14] clkhdr.CK <= io.clk @[lib.scala 336:18] clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_1 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> defname = gated_latch module rvclkhdr_1 : input clock : Clock input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} inst clkhdr of gated_latch_1 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid io.l1clk <= clkhdr.Q @[lib.scala 335:14] clkhdr.CK <= io.clk @[lib.scala 336:18] clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_2 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> defname = gated_latch module rvclkhdr_2 : input clock : Clock input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} inst clkhdr of gated_latch_2 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid io.l1clk <= clkhdr.Q @[lib.scala 335:14] clkhdr.CK <= io.clk @[lib.scala 336:18] clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_3 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> defname = gated_latch module rvclkhdr_3 : input clock : Clock input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} inst clkhdr of gated_latch_3 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid io.l1clk <= clkhdr.Q @[lib.scala 335:14] clkhdr.CK <= io.clk @[lib.scala 336:18] clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module axi4_to_ahb : input clock : Clock input reset : AsyncReset output io : {flip free_clk : Clock, flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire dec_tlu_force_halt_bus_q : UInt<1> dec_tlu_force_halt_bus_q <= UInt<1>("h00") node dec_tlu_force_halt_bus = or(io.dec_tlu_force_halt, dec_tlu_force_halt_bus_q) @[axi4_to_ahb.scala 24:54] node _T = eq(io.bus_clk_en, UInt<1>("h00")) @[axi4_to_ahb.scala 25:35] node dec_tlu_force_halt_bus_ns = and(_T, dec_tlu_force_halt_bus) @[axi4_to_ahb.scala 25:50] reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 26:62] _T_1 <= dec_tlu_force_halt_bus_ns @[axi4_to_ahb.scala 26:62] dec_tlu_force_halt_bus_q <= _T_1 @[axi4_to_ahb.scala 26:28] wire buf_rst : UInt<1> buf_rst <= UInt<1>("h00") buf_rst <= dec_tlu_force_halt_bus @[axi4_to_ahb.scala 28:11] io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 29:21] wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") wire bus_clk : Clock @[axi4_to_ahb.scala 31:21] wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 32:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") node _T_2 = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 36:62] wire _T_3 : UInt @[lib.scala 389:21] node _T_4 = eq(buf_rst, UInt<1>("h00")) @[lib.scala 391:73] node _T_5 = bits(_T_4, 0, 0) @[Bitwise.scala 72:15] node _T_6 = mux(_T_5, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_7 = and(buf_nxtstate, _T_6) @[lib.scala 391:53] node _T_8 = or(_T_2, buf_rst) @[lib.scala 391:92] node _T_9 = and(_T_8, io.bus_clk_en) @[lib.scala 391:99] node _T_10 = bits(_T_9, 0, 0) @[lib.scala 8:44] reg _T_11 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_10 : @[Reg.scala 28:19] _T_11 <= _T_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_3 <= _T_11 @[lib.scala 391:14] buf_state <= _T_3 @[axi4_to_ahb.scala 36:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> slave_ready <= UInt<1>("h00") wire slave_tag : UInt<1> slave_tag <= UInt<1>("h00") wire slave_rdata : UInt<64> slave_rdata <= UInt<64>("h00") wire slave_opc : UInt<4> slave_opc <= UInt<4>("h00") wire wrbuf_en : UInt<1> wrbuf_en <= UInt<1>("h00") wire wrbuf_data_en : UInt<1> wrbuf_data_en <= UInt<1>("h00") wire wrbuf_cmd_sent : UInt<1> wrbuf_cmd_sent <= UInt<1>("h00") wire wrbuf_rst : UInt<1> wrbuf_rst <= UInt<1>("h00") wire wrbuf_vld : UInt<1> wrbuf_vld <= UInt<1>("h00") wire wrbuf_data_vld : UInt<1> wrbuf_data_vld <= UInt<1>("h00") wire wrbuf_tag : UInt<1> wrbuf_tag <= UInt<1>("h00") wire wrbuf_size : UInt<3> wrbuf_size <= UInt<3>("h00") wire wrbuf_addr : UInt<32> wrbuf_addr <= UInt<32>("h00") wire wrbuf_data : UInt<64> wrbuf_data <= UInt<64>("h00") wire wrbuf_byteen : UInt<8> wrbuf_byteen <= UInt<8>("h00") wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> master_ready <= UInt<1>("h00") wire master_tag : UInt<1> master_tag <= UInt<1>("h00") wire master_addr : UInt<32> master_addr <= UInt<32>("h00") wire master_wdata : UInt<64> master_wdata <= UInt<64>("h00") wire master_size : UInt<3> master_size <= UInt<3>("h00") wire master_opc : UInt<3> master_opc <= UInt<3>("h00") wire master_byteen : UInt<8> master_byteen <= UInt<8>("h00") wire buf_addr : UInt<32> buf_addr <= UInt<32>("h00") wire buf_size : UInt<2> buf_size <= UInt<2>("h00") wire buf_write : UInt<1> buf_write <= UInt<1>("h00") wire buf_byteen : UInt<8> buf_byteen <= UInt<8>("h00") wire buf_aligned : UInt<1> buf_aligned <= UInt<1>("h00") wire buf_data : UInt<64> buf_data <= UInt<64>("h00") wire buf_tag : UInt<1> buf_tag <= UInt<1>("h00") wire buf_tag_in : UInt<1> buf_tag_in <= UInt<1>("h00") wire buf_addr_in : UInt<32> buf_addr_in <= UInt<32>("h00") wire buf_byteen_in : UInt<8> buf_byteen_in <= UInt<8>("h00") wire buf_data_in : UInt<64> buf_data_in <= UInt<64>("h00") wire buf_write_in : UInt<1> buf_write_in <= UInt<1>("h00") wire buf_aligned_in : UInt<1> buf_aligned_in <= UInt<1>("h00") wire buf_size_in : UInt<3> buf_size_in <= UInt<3>("h00") wire buf_wr_en : UInt<1> buf_wr_en <= UInt<1>("h00") wire buf_data_wr_en : UInt<1> buf_data_wr_en <= UInt<1>("h00") wire slvbuf_error_en : UInt<1> slvbuf_error_en <= UInt<1>("h00") wire wr_cmd_vld : UInt<1> wr_cmd_vld <= UInt<1>("h00") wire cmd_done_rst : UInt<1> cmd_done_rst <= UInt<1>("h00") wire cmd_done : UInt<1> cmd_done <= UInt<1>("h00") wire cmd_doneQ : UInt<1> cmd_doneQ <= UInt<1>("h00") wire trxn_done : UInt<1> trxn_done <= UInt<1>("h00") wire buf_cmd_byte_ptr : UInt<3> buf_cmd_byte_ptr <= UInt<3>("h00") wire buf_cmd_byte_ptrQ : UInt<3> buf_cmd_byte_ptrQ <= UInt<3>("h00") wire buf_cmd_nxtbyte_ptr : UInt<3> buf_cmd_nxtbyte_ptr <= UInt<3>("h00") wire buf_cmd_byte_ptr_en : UInt<1> buf_cmd_byte_ptr_en <= UInt<1>("h00") wire found : UInt<1> found <= UInt<1>("h00") wire slave_valid_pre : UInt<1> slave_valid_pre <= UInt<1>("h00") wire ahb_hready_q : UInt<1> ahb_hready_q <= UInt<1>("h00") wire ahb_hresp_q : UInt<1> ahb_hresp_q <= UInt<1>("h00") wire ahb_htrans_q : UInt<2> ahb_htrans_q <= UInt<2>("h00") wire ahb_hwrite_q : UInt<1> ahb_hwrite_q <= UInt<1>("h00") wire ahb_hrdata_q : UInt<64> ahb_hrdata_q <= UInt<64>("h00") wire slvbuf_write : UInt<1> slvbuf_write <= UInt<1>("h00") wire slvbuf_error : UInt<1> slvbuf_error <= UInt<1>("h00") wire slvbuf_tag : UInt<1> slvbuf_tag <= UInt<1>("h00") wire slvbuf_error_in : UInt<1> slvbuf_error_in <= UInt<1>("h00") wire slvbuf_wr_en : UInt<1> slvbuf_wr_en <= UInt<1>("h00") wire bypass_en : UInt<1> bypass_en <= UInt<1>("h00") wire rd_bypass_idle : UInt<1> rd_bypass_idle <= UInt<1>("h00") wire last_addr_en : UInt<1> last_addr_en <= UInt<1>("h00") wire last_bus_addr : UInt<32> last_bus_addr <= UInt<32>("h00") wire buf_clken : UInt<1> buf_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] node _T_12 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 140:27] wr_cmd_vld <= _T_12 @[axi4_to_ahb.scala 140:14] node _T_13 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 141:30] master_valid <= _T_13 @[axi4_to_ahb.scala 141:16] node _T_14 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] node _T_15 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 142:51] node _T_16 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 142:82] node _T_17 = mux(_T_14, _T_15, _T_16) @[axi4_to_ahb.scala 142:20] master_tag <= _T_17 @[axi4_to_ahb.scala 142:14] node _T_18 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:38] node _T_19 = mux(_T_18, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 143:20] master_opc <= _T_19 @[axi4_to_ahb.scala 143:14] node _T_20 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] node _T_21 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 144:53] node _T_22 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 144:81] node _T_23 = mux(_T_20, _T_21, _T_22) @[axi4_to_ahb.scala 144:21] master_addr <= _T_23 @[axi4_to_ahb.scala 144:15] node _T_24 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 145:39] node _T_25 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 145:53] node _T_26 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 145:80] node _T_27 = mux(_T_24, _T_25, _T_26) @[axi4_to_ahb.scala 145:21] master_size <= _T_27 @[axi4_to_ahb.scala 145:15] node _T_28 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 146:32] master_byteen <= _T_28 @[axi4_to_ahb.scala 146:17] node _T_29 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 147:29] master_wdata <= _T_29 @[axi4_to_ahb.scala 147:16] node _T_30 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 150:33] node _T_31 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 150:58] node _T_32 = and(_T_30, _T_31) @[axi4_to_ahb.scala 150:47] io.axi.b.valid <= _T_32 @[axi4_to_ahb.scala 150:18] node _T_33 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 151:38] node _T_34 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 151:65] node _T_35 = mux(_T_34, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 151:55] node _T_36 = mux(_T_33, UInt<2>("h02"), _T_35) @[axi4_to_ahb.scala 151:28] io.axi.b.bits.resp <= _T_36 @[axi4_to_ahb.scala 151:22] node _T_37 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 152:32] io.axi.b.bits.id <= _T_37 @[axi4_to_ahb.scala 152:20] node _T_38 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 154:33] node _T_39 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 154:59] node _T_40 = eq(_T_39, UInt<1>("h00")) @[axi4_to_ahb.scala 154:66] node _T_41 = and(_T_38, _T_40) @[axi4_to_ahb.scala 154:47] io.axi.r.valid <= _T_41 @[axi4_to_ahb.scala 154:18] node _T_42 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 155:38] node _T_43 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 155:65] node _T_44 = mux(_T_43, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 155:55] node _T_45 = mux(_T_42, UInt<2>("h02"), _T_44) @[axi4_to_ahb.scala 155:28] io.axi.r.bits.resp <= _T_45 @[axi4_to_ahb.scala 155:22] node _T_46 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 156:32] io.axi.r.bits.id <= _T_46 @[axi4_to_ahb.scala 156:20] node _T_47 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 157:36] io.axi.r.bits.data <= _T_47 @[axi4_to_ahb.scala 157:22] node _T_48 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 158:33] slave_ready <= _T_48 @[axi4_to_ahb.scala 158:15] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 162:20] node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 163:34] node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 163:41] buf_write_in <= _T_51 @[axi4_to_ahb.scala 163:20] node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 164:46] node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 164:26] buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 164:20] node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 165:36] buf_state_en <= _T_54 @[axi4_to_ahb.scala 165:20] buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 166:17] node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 167:54] node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 167:38] buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 167:22] buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 168:27] node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:50] node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 169:94] node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 136:52] node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 136:24] node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 137:44] node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 137:62] node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 137:48] node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 137:44] node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 137:62] node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 137:48] node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 137:44] node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 137:62] node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 137:48] node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 137:44] node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 137:62] node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 137:48] node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 137:44] node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 137:62] node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 137:48] node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 137:44] node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 137:62] node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 137:48] node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 137:44] node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 137:62] node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 137:48] node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 137:44] node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 137:62] node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 137:48] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 169:124] node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 169:30] buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 169:24] bypass_en <= buf_state_en @[axi4_to_ahb.scala 170:17] node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 171:51] node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 171:35] rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 171:22] node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 172:49] io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 172:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_101 : @[Conditional.scala 39:67] node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 176:54] node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 176:61] node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 176:41] node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 176:82] node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 176:26] buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 176:20] node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 177:51] node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 177:58] node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 177:36] node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 177:72] node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 177:70] buf_state_en <= _T_111 @[axi4_to_ahb.scala 177:20] node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 178:34] node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 178:32] cmd_done <= _T_113 @[axi4_to_ahb.scala 178:16] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 179:20] node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 180:52] node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 180:59] node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 180:37] node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 180:73] node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 180:71] node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 180:122] node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 180:129] node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 180:109] node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 180:150] node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 180:94] node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 180:174] node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 180:88] master_ready <= _T_125 @[axi4_to_ahb.scala 180:20] buf_wr_en <= master_ready @[axi4_to_ahb.scala 181:17] node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 182:33] bypass_en <= _T_126 @[axi4_to_ahb.scala 182:17] node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 183:47] node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 183:62] node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 183:78] node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 183:30] buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 183:24] node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 184:48] node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 184:62] node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 184:36] io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 184:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_136 : @[Conditional.scala 39:67] node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 188:39] node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 188:37] node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 188:82] node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 188:89] node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 188:70] node _T_142 = not(_T_141) @[axi4_to_ahb.scala 188:55] node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 188:53] master_ready <= _T_143 @[axi4_to_ahb.scala 188:20] node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 189:34] node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:62] node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 189:69] node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 189:49] buf_wr_en <= _T_147 @[axi4_to_ahb.scala 189:17] node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 190:45] node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 190:82] node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 190:110] node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 190:117] node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 190:97] node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 190:138] node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 190:67] node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 190:26] buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 190:20] node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 191:37] buf_state_en <= _T_156 @[axi4_to_ahb.scala 191:20] buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:22] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 193:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 194:23] node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 195:41] node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 195:39] slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 195:23] node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 196:34] node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 196:32] cmd_done <= _T_160 @[axi4_to_ahb.scala 196:16] node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 197:33] node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 197:64] node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 197:48] node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 197:79] bypass_en <= _T_164 @[axi4_to_ahb.scala 197:17] node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 198:47] node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 198:62] node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 198:78] node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 198:30] buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 198:24] node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 199:63] node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 199:78] node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 199:47] node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 199:36] io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 199:25] slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 200:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_175 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 204:20] node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 205:51] node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 205:58] node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 205:36] node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 205:72] node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 205:70] buf_state_en <= _T_180 @[axi4_to_ahb.scala 205:20] slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 206:23] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 207:20] node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 208:35] buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 208:24] node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 209:51] node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 209:41] io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 209:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 213:20] node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 214:37] buf_state_en <= _T_187 @[axi4_to_ahb.scala 214:20] buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 215:22] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 216:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 217:23] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 218:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_188 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 222:20] node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 223:33] node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 223:63] node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 223:70] node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 223:48] trxn_done <= _T_192 @[axi4_to_ahb.scala 223:17] buf_state_en <= trxn_done @[axi4_to_ahb.scala 224:20] buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 226:20] node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 227:47] node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 227:85] node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 227:103] node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 136:52] node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 136:24] node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 137:44] node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 137:62] node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 137:48] node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 137:44] node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 137:62] node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 137:48] node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 137:44] node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 137:62] node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 137:48] node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 137:44] node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 137:62] node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 137:48] node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 137:44] node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 137:62] node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 137:48] node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 137:44] node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 137:62] node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 137:48] node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 137:44] node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 137:62] node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 137:48] node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 137:44] node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 137:62] node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 137:48] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 227:30] buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 227:24] node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 228:65] node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 228:44] node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 228:127] node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 228:145] node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 136:52] node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 136:24] node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 137:44] node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 137:62] node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 137:48] node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 137:44] node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 137:62] node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 137:48] node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 137:44] node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 137:62] node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 137:48] node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 137:44] node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 137:62] node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 137:48] node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 137:44] node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 137:62] node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 137:48] node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 137:44] node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 137:62] node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 137:48] node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 137:44] node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 137:62] node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 137:48] node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 137:44] node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 137:62] node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 137:48] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 228:92] node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 228:92] node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 228:163] node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 228:79] node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 228:29] cmd_done <= _T_275 @[axi4_to_ahb.scala 228:16] node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 229:47] node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 229:36] node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 229:61] io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 229:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_281 : @[Conditional.scala 39:67] node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 233:34] node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 233:50] buf_state_en <= _T_283 @[axi4_to_ahb.scala 233:20] node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 234:38] node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 234:36] node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 234:51] master_ready <= _T_286 @[axi4_to_ahb.scala 234:20] node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 235:42] node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 235:40] node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 235:81] node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 235:113] node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 235:120] node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 235:135] node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 235:101] node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 235:66] node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 235:26] buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 235:20] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 236:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 237:23] node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 238:33] node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 238:40] buf_write_in <= _T_297 @[axi4_to_ahb.scala 238:20] node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 239:50] node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 239:78] node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 239:62] node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 239:33] buf_wr_en <= _T_301 @[axi4_to_ahb.scala 239:17] buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 240:22] node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:63] node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 241:70] node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 241:48] node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 242:29] node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 242:85] node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 242:103] node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 136:52] node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 136:24] node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 137:44] node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 137:62] node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 137:48] node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 137:44] node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 137:62] node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 137:48] node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 137:44] node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 137:62] node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 137:48] node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 137:44] node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 137:62] node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 137:48] node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 137:44] node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 137:62] node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 137:48] node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 137:44] node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 137:62] node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 137:48] node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 137:44] node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 137:62] node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 137:48] node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 137:44] node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 137:62] node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 137:48] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 242:51] node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 242:51] node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 242:120] node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 242:38] node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 241:79] node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 241:32] cmd_done <= _T_348 @[axi4_to_ahb.scala 241:16] node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 243:33] node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 243:64] node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 243:48] bypass_en <= _T_351 @[axi4_to_ahb.scala 243:17] node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 244:48] node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 244:37] node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 244:61] node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 244:75] io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 244:25] node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 245:55] node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 245:39] slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 245:23] node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 246:33] node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 246:63] node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 246:70] node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 246:48] trxn_done <= _T_363 @[axi4_to_ahb.scala 246:17] node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 247:40] buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 247:27] node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 248:81] node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 136:52] node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 136:24] node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 137:44] node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 137:62] node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 137:48] node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 137:44] node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 137:62] node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 137:48] node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 137:44] node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 137:62] node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 137:48] node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 137:44] node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 137:62] node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 137:48] node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 137:44] node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 137:62] node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 137:48] node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 137:44] node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 137:62] node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 137:48] node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 137:44] node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 137:62] node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 137:48] node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 137:44] node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 137:62] node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 137:48] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:147] node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:165] node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 136:52] node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 136:24] node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 137:44] node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 137:62] node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 137:48] node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 137:44] node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 137:62] node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 137:48] node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 137:44] node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 137:62] node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 137:48] node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 137:44] node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 137:62] node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 137:48] node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 137:44] node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 137:62] node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 137:48] node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 137:44] node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 137:62] node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 137:48] node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 137:44] node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 137:62] node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 137:48] node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 137:44] node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 137:62] node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 137:48] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 248:102] node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 248:30] buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 248:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_440 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 251:20] buf_state_en <= slave_ready @[axi4_to_ahb.scala 252:20] slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 253:23] slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 254:23] skip @[Conditional.scala 39:67] cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 258:16] node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 259:33] node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 259:75] node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 259:82] node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 259:62] node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 259:102] node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 259:134] node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 259:154] node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 259:45] node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] buf_addr_in <= _T_486 @[axi4_to_ahb.scala 259:15] node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 260:27] buf_tag_in <= _T_487 @[axi4_to_ahb.scala 260:14] node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 261:32] buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 261:17] node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 262:33] node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 262:59] node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 262:80] node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 262:21] buf_data_in <= _T_492 @[axi4_to_ahb.scala 262:15] node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 263:52] node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 263:59] node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 263:38] node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 263:85] node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 263:92] node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 263:72] node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 263:112] node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 263:144] node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 120:42] node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 120:49] node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 120:25] node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:35] node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 121:42] node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:64] node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 121:71] node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 121:55] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 121:16] node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 120:64] node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:40] node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 122:47] node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:69] node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 122:76] node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 122:60] node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:98] node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 122:105] node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 122:89] node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:132] node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 122:139] node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 122:123] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 122:21] node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 121:93] node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 263:164] node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 263:21] buf_size_in <= _T_531 @[axi4_to_ahb.scala 263:15] node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 264:32] node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 264:39] node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:17] node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 265:24] node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 264:48] node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:47] node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 265:54] node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 265:33] node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:86] node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 265:93] node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 265:72] node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 266:18] node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 266:25] node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:55] node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 266:62] node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:90] node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 266:97] node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 266:74] node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:125] node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 266:132] node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 266:109] node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:161] node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 266:168] node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 266:145] node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:21] node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 267:28] node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 266:181] node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:56] node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 267:63] node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 267:40] node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:92] node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 267:99] node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 267:76] node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 266:38] node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 265:106] buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 264:18] node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 269:47] node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 269:62] node _T_569 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 269:79] node _T_570 = mux(_T_567, _T_568, _T_569) @[axi4_to_ahb.scala 269:30] node _T_571 = eq(io.ahb.out.htrans, UInt<2>("h02")) @[axi4_to_ahb.scala 269:115] node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] node _T_573 = mux(_T_572, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_574 = and(_T_573, buf_cmd_byte_ptr) @[axi4_to_ahb.scala 269:124] node _T_575 = cat(_T_570, _T_574) @[Cat.scala 29:58] io.ahb.out.haddr <= _T_575 @[axi4_to_ahb.scala 269:20] node _T_576 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 270:43] node _T_577 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_578 = mux(_T_577, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_579 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 270:94] node _T_580 = and(_T_578, _T_579) @[axi4_to_ahb.scala 270:81] node _T_581 = cat(UInt<1>("h00"), _T_580) @[Cat.scala 29:58] node _T_582 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_583 = mux(_T_582, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_584 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 270:148] node _T_585 = and(_T_583, _T_584) @[axi4_to_ahb.scala 270:138] node _T_586 = cat(UInt<1>("h00"), _T_585) @[Cat.scala 29:58] node _T_587 = mux(_T_576, _T_581, _T_586) @[axi4_to_ahb.scala 270:26] io.ahb.out.hsize <= _T_587 @[axi4_to_ahb.scala 270:20] io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 272:21] io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 273:24] node _T_588 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 274:57] node _T_589 = eq(_T_588, UInt<1>("h00")) @[axi4_to_ahb.scala 274:37] node _T_590 = cat(UInt<1>("h01"), _T_589) @[Cat.scala 29:58] io.ahb.out.hprot <= _T_590 @[axi4_to_ahb.scala 274:20] node _T_591 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:44] node _T_592 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 275:59] node _T_593 = eq(_T_592, UInt<1>("h01")) @[axi4_to_ahb.scala 275:66] node _T_594 = mux(_T_591, _T_593, buf_write) @[axi4_to_ahb.scala 275:27] io.ahb.out.hwrite <= _T_594 @[axi4_to_ahb.scala 275:21] node _T_595 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 276:32] io.ahb.out.hwdata <= _T_595 @[axi4_to_ahb.scala 276:21] slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 278:15] node _T_596 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 279:43] node _T_597 = mux(_T_596, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 279:23] node _T_598 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_599 = mux(_T_598, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_600 = and(_T_599, UInt<2>("h02")) @[axi4_to_ahb.scala 279:88] node _T_601 = cat(_T_597, _T_600) @[Cat.scala 29:58] slave_opc <= _T_601 @[axi4_to_ahb.scala 279:13] node _T_602 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 280:41] node _T_603 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 280:66] node _T_604 = cat(_T_603, _T_603) @[Cat.scala 29:58] node _T_605 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 280:91] node _T_606 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 280:110] node _T_607 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 280:131] node _T_608 = mux(_T_605, _T_606, _T_607) @[axi4_to_ahb.scala 280:79] node _T_609 = mux(_T_602, _T_604, _T_608) @[axi4_to_ahb.scala 280:21] slave_rdata <= _T_609 @[axi4_to_ahb.scala 280:15] node _T_610 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 281:26] slave_tag <= _T_610 @[axi4_to_ahb.scala 281:13] node _T_611 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 283:37] node _T_612 = neq(_T_611, UInt<1>("h00")) @[axi4_to_ahb.scala 283:44] node _T_613 = and(_T_612, io.ahb.in.hready) @[axi4_to_ahb.scala 283:56] node _T_614 = and(_T_613, io.ahb.out.hwrite) @[axi4_to_ahb.scala 283:75] last_addr_en <= _T_614 @[axi4_to_ahb.scala 283:16] node _T_615 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 285:31] node _T_616 = and(_T_615, master_ready) @[axi4_to_ahb.scala 285:49] wrbuf_en <= _T_616 @[axi4_to_ahb.scala 285:12] node _T_617 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 286:35] node _T_618 = and(_T_617, master_ready) @[axi4_to_ahb.scala 286:52] wrbuf_data_en <= _T_618 @[axi4_to_ahb.scala 286:17] node _T_619 = and(master_valid, master_ready) @[axi4_to_ahb.scala 287:34] node _T_620 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 287:62] node _T_621 = eq(_T_620, UInt<1>("h01")) @[axi4_to_ahb.scala 287:69] node _T_622 = and(_T_619, _T_621) @[axi4_to_ahb.scala 287:49] wrbuf_cmd_sent <= _T_622 @[axi4_to_ahb.scala 287:18] node _T_623 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 288:34] node _T_624 = and(wrbuf_cmd_sent, _T_623) @[axi4_to_ahb.scala 288:32] node _T_625 = or(_T_624, dec_tlu_force_halt_bus) @[axi4_to_ahb.scala 288:45] wrbuf_rst <= _T_625 @[axi4_to_ahb.scala 288:13] node _T_626 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 290:36] node _T_627 = and(wrbuf_vld, _T_626) @[axi4_to_ahb.scala 290:34] node _T_628 = eq(_T_627, UInt<1>("h00")) @[axi4_to_ahb.scala 290:22] node _T_629 = and(_T_628, master_ready) @[axi4_to_ahb.scala 290:53] io.axi.aw.ready <= _T_629 @[axi4_to_ahb.scala 290:19] node _T_630 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 291:40] node _T_631 = and(wrbuf_data_vld, _T_630) @[axi4_to_ahb.scala 291:38] node _T_632 = eq(_T_631, UInt<1>("h00")) @[axi4_to_ahb.scala 291:21] node _T_633 = and(_T_632, master_ready) @[axi4_to_ahb.scala 291:57] io.axi.w.ready <= _T_633 @[axi4_to_ahb.scala 291:18] node _T_634 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 292:34] node _T_635 = eq(_T_634, UInt<1>("h00")) @[axi4_to_ahb.scala 292:22] node _T_636 = and(_T_635, master_ready) @[axi4_to_ahb.scala 292:52] io.axi.ar.ready <= _T_636 @[axi4_to_ahb.scala 292:19] io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 293:22] node _T_637 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 295:49] wire _T_638 : UInt @[lib.scala 389:21] node _T_639 = eq(wrbuf_rst, UInt<1>("h00")) @[lib.scala 391:73] node _T_640 = and(UInt<1>("h01"), _T_639) @[lib.scala 391:53] node _T_641 = or(_T_637, wrbuf_rst) @[lib.scala 391:92] node _T_642 = and(_T_641, io.bus_clk_en) @[lib.scala 391:99] node _T_643 = bits(_T_642, 0, 0) @[lib.scala 8:44] reg _T_644 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_643 : @[Reg.scala 28:19] _T_644 <= _T_640 @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_638 <= _T_644 @[lib.scala 391:14] wrbuf_vld <= _T_638 @[axi4_to_ahb.scala 295:13] node _T_645 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 296:59] wire _T_646 : UInt @[lib.scala 389:21] node _T_647 = eq(wrbuf_rst, UInt<1>("h00")) @[lib.scala 391:73] node _T_648 = and(UInt<1>("h01"), _T_647) @[lib.scala 391:53] node _T_649 = or(_T_645, wrbuf_rst) @[lib.scala 391:92] node _T_650 = and(_T_649, io.bus_clk_en) @[lib.scala 391:99] node _T_651 = bits(_T_650, 0, 0) @[lib.scala 8:44] reg _T_652 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_651 : @[Reg.scala 28:19] _T_652 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_646 <= _T_652 @[lib.scala 391:14] wrbuf_data_vld <= _T_646 @[axi4_to_ahb.scala 296:18] node _T_653 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 297:45] node _T_654 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 297:74] node _T_655 = and(io.bus_clk_en, _T_654) @[lib.scala 383:57] reg _T_656 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_655 : @[Reg.scala 28:19] _T_656 <= _T_653 @[Reg.scala 28:23] skip @[Reg.scala 28:19] wrbuf_tag <= _T_656 @[axi4_to_ahb.scala 297:13] node _T_657 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 298:48] node _T_658 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 298:71] node _T_659 = and(io.bus_clk_en, _T_658) @[lib.scala 383:57] reg _T_660 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_657 @[Reg.scala 28:23] skip @[Reg.scala 28:19] wrbuf_size <= _T_660 @[axi4_to_ahb.scala 298:14] node _T_661 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 299:54] node _T_662 = and(_T_661, io.bus_clk_en) @[axi4_to_ahb.scala 299:61] inst rvclkhdr of rvclkhdr @[lib.scala 399:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 401:18] rvclkhdr.io.en <= _T_662 @[lib.scala 402:17] rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg _T_663 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_662 : @[Reg.scala 28:19] _T_663 <= io.axi.aw.bits.addr @[Reg.scala 28:23] skip @[Reg.scala 28:19] wrbuf_addr <= _T_663 @[axi4_to_ahb.scala 299:14] node _T_664 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 300:58] node _T_665 = and(_T_664, io.bus_clk_en) @[axi4_to_ahb.scala 300:65] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 401:18] rvclkhdr_1.io.en <= _T_665 @[lib.scala 402:17] rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg _T_666 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_665 : @[Reg.scala 28:19] _T_666 <= io.axi.w.bits.data @[Reg.scala 28:23] skip @[Reg.scala 28:19] wrbuf_data <= _T_666 @[axi4_to_ahb.scala 300:14] node _T_667 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 301:49] node _T_668 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 301:77] node _T_669 = and(io.bus_clk_en, _T_668) @[lib.scala 383:57] reg _T_670 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_669 : @[Reg.scala 28:19] _T_670 <= _T_667 @[Reg.scala 28:23] skip @[Reg.scala 28:19] wrbuf_byteen <= _T_670 @[axi4_to_ahb.scala 301:16] node _T_671 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 302:48] node _T_672 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 302:76] node _T_673 = and(io.bus_clk_en, _T_672) @[lib.scala 383:57] reg _T_674 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_673 : @[Reg.scala 28:19] _T_674 <= _T_671 @[Reg.scala 28:23] skip @[Reg.scala 28:19] last_bus_addr <= _T_674 @[axi4_to_ahb.scala 302:17] node _T_675 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 303:66] node _T_676 = and(buf_clken, _T_675) @[lib.scala 383:57] reg _T_677 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] buf_write <= _T_677 @[axi4_to_ahb.scala 303:21] node _T_678 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 304:46] node _T_679 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 304:76] node _T_680 = and(buf_clken, _T_679) @[lib.scala 383:57] reg _T_681 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_680 : @[Reg.scala 28:19] _T_681 <= _T_678 @[Reg.scala 28:23] skip @[Reg.scala 28:19] buf_tag <= _T_681 @[axi4_to_ahb.scala 304:21] node _T_682 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 305:42] node _T_683 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 305:62] node _T_684 = bits(_T_683, 0, 0) @[axi4_to_ahb.scala 305:79] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 399:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 401:18] rvclkhdr_2.io.en <= _T_684 @[lib.scala 402:17] rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg _T_685 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_684 : @[Reg.scala 28:19] _T_685 <= _T_682 @[Reg.scala 28:23] skip @[Reg.scala 28:19] buf_addr <= _T_685 @[axi4_to_ahb.scala 305:21] node _T_686 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 306:47] node _T_687 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 306:70] node _T_688 = and(buf_clken, _T_687) @[lib.scala 383:57] reg _T_689 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_688 : @[Reg.scala 28:19] _T_689 <= _T_686 @[Reg.scala 28:23] skip @[Reg.scala 28:19] buf_size <= _T_689 @[axi4_to_ahb.scala 306:21] node _T_690 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 307:68] node _T_691 = and(buf_clken, _T_690) @[lib.scala 383:57] reg _T_692 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_691 : @[Reg.scala 28:19] _T_692 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] buf_aligned <= _T_692 @[axi4_to_ahb.scala 307:21] node _T_693 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 308:49] node _T_694 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 308:73] node _T_695 = and(buf_clken, _T_694) @[lib.scala 383:57] reg _T_696 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_695 : @[Reg.scala 28:19] _T_696 <= _T_693 @[Reg.scala 28:23] skip @[Reg.scala 28:19] buf_byteen <= _T_696 @[axi4_to_ahb.scala 308:21] node _T_697 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 309:42] node _T_698 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 309:67] node _T_699 = bits(_T_698, 0, 0) @[axi4_to_ahb.scala 309:90] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 399:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 401:18] rvclkhdr_3.io.en <= _T_699 @[lib.scala 402:17] rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg _T_700 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_699 : @[Reg.scala 28:19] _T_700 <= _T_697 @[Reg.scala 28:23] skip @[Reg.scala 28:19] buf_data <= _T_700 @[axi4_to_ahb.scala 309:21] node _T_701 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:66] node _T_702 = and(buf_clken, _T_701) @[lib.scala 383:57] reg _T_703 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_702 : @[Reg.scala 28:19] _T_703 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] slvbuf_write <= _T_703 @[axi4_to_ahb.scala 310:21] node _T_704 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 311:43] node _T_705 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 311:76] node _T_706 = and(buf_clken, _T_705) @[lib.scala 383:57] reg _T_707 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_706 : @[Reg.scala 28:19] _T_707 <= _T_704 @[Reg.scala 28:23] skip @[Reg.scala 28:19] slvbuf_tag <= _T_707 @[axi4_to_ahb.scala 311:21] node _T_708 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 312:75] node _T_709 = and(io.bus_clk_en, _T_708) @[lib.scala 383:57] reg _T_710 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_709 : @[Reg.scala 28:19] _T_710 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] slvbuf_error <= _T_710 @[axi4_to_ahb.scala 312:21] node _T_711 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 313:57] wire _T_712 : UInt @[lib.scala 389:21] node _T_713 = eq(cmd_done_rst, UInt<1>("h00")) @[lib.scala 391:73] node _T_714 = and(UInt<1>("h01"), _T_713) @[lib.scala 391:53] node _T_715 = or(_T_711, cmd_done_rst) @[lib.scala 391:92] node _T_716 = and(_T_715, io.bus_clk_en) @[lib.scala 391:99] node _T_717 = bits(_T_716, 0, 0) @[lib.scala 8:44] reg _T_718 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_717 : @[Reg.scala 28:19] _T_718 <= _T_714 @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_712 <= _T_718 @[lib.scala 391:14] cmd_doneQ <= _T_712 @[axi4_to_ahb.scala 313:21] node _T_719 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 314:52] node _T_720 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 314:86] node _T_721 = and(io.bus_clk_en, _T_720) @[lib.scala 383:57] reg _T_722 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_721 : @[Reg.scala 28:19] _T_722 <= _T_719 @[Reg.scala 28:23] skip @[Reg.scala 28:19] buf_cmd_byte_ptrQ <= _T_722 @[axi4_to_ahb.scala 314:21] reg _T_723 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.bus_clk_en : @[Reg.scala 28:19] _T_723 <= io.ahb.in.hready @[Reg.scala 28:23] skip @[Reg.scala 28:19] ahb_hready_q <= _T_723 @[axi4_to_ahb.scala 315:21] node _T_724 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 316:52] reg _T_725 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.bus_clk_en : @[Reg.scala 28:19] _T_725 <= _T_724 @[Reg.scala 28:23] skip @[Reg.scala 28:19] ahb_htrans_q <= _T_725 @[axi4_to_ahb.scala 316:21] reg _T_726 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.bus_clk_en : @[Reg.scala 28:19] _T_726 <= io.ahb.out.hwrite @[Reg.scala 28:23] skip @[Reg.scala 28:19] ahb_hwrite_q <= _T_726 @[axi4_to_ahb.scala 317:21] reg _T_727 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.bus_clk_en : @[Reg.scala 28:19] _T_727 <= io.ahb.in.hresp @[Reg.scala 28:23] skip @[Reg.scala 28:19] ahb_hresp_q <= _T_727 @[axi4_to_ahb.scala 318:21] node _T_728 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 319:51] reg _T_729 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ahbm_data_clken : @[Reg.scala 28:19] _T_729 <= _T_728 @[Reg.scala 28:23] skip @[Reg.scala 28:19] ahb_hrdata_q <= _T_729 @[axi4_to_ahb.scala 319:21] node _T_730 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 320:51] node _T_731 = or(_T_730, io.clk_override) @[axi4_to_ahb.scala 320:66] node _T_732 = and(io.bus_clk_en, _T_731) @[axi4_to_ahb.scala 320:38] buf_clken <= _T_732 @[axi4_to_ahb.scala 320:21] node _T_733 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 321:52] node _T_734 = or(_T_733, io.clk_override) @[axi4_to_ahb.scala 321:62] node _T_735 = and(io.bus_clk_en, _T_734) @[axi4_to_ahb.scala 321:38] ahbm_data_clken <= _T_735 @[axi4_to_ahb.scala 321:21] node _T_736 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 323:27] bus_clk <= _T_736 @[axi4_to_ahb.scala 323:13] node _T_737 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 324:27] buf_clk <= _T_737 @[axi4_to_ahb.scala 324:13] node _T_738 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 325:33] ahbm_data_clk <= _T_738 @[axi4_to_ahb.scala 325:19]