[ { "class":"firrtl.transforms.CombinationalPath", "sink":"~sbox|sbox>io_s_box_out_valid", "sources":[ "~sbox|sbox>io_op" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~sbox|sbox>io_inv_s_box_out_bits", "sources":[ "~sbox|sbox>io_in" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~sbox|sbox>io_s_box_out_bits", "sources":[ "~sbox|sbox>io_in" ] }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~sbox|sbox>io_inv_s_box_out_valid", "sources":[ "~sbox|sbox>io_op" ] }, { "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" }, { "class":"firrtl.options.TargetDirAnnotation", "directory":"." }, { "class":"firrtl.options.OutputAnnotationFileAnnotation", "file":"sbox" }, { "class":"firrtl.transforms.BlackBoxTargetDirAnno", "targetDir":"." } ]