;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit el2_ifu_aln_ctl : module el2_ifu_aln_ctl : input clock : Clock input reset : UInt<1> output io : {flip scan_mode : UInt<1>, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<32>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<32>, way : UInt<1>, ret : UInt<1>}} wire error_stall_in : UInt<1> error_stall_in <= UInt<1>("h00") wire alignval : UInt<2> alignval <= UInt<1>("h00") wire q0final : UInt<16> q0final <= UInt<1>("h00") wire q1final : UInt<16> q1final <= UInt<1>("h00") wire wrptr_in : UInt<2> wrptr_in <= UInt<1>("h00") wire rdptr_in : UInt<2> rdptr_in <= UInt<1>("h00") wire f2val_in : UInt<2> f2val_in <= UInt<1>("h00") wire f1val_in : UInt<2> f1val_in <= UInt<1>("h00") wire f0val_in : UInt<2> f0val_in <= UInt<1>("h00") wire q2off_in : UInt<1> q2off_in <= UInt<1>("h00") wire q1off_in : UInt<1> q1off_in <= UInt<1>("h00") wire q0off_in : UInt<1> q0off_in <= UInt<1>("h00") wire sf0_valid : UInt<1> sf0_valid <= UInt<1>("h00") wire sf1_valid : UInt<1> sf1_valid <= UInt<1>("h00") wire f2_valid : UInt<1> f2_valid <= UInt<1>("h00") wire ifvalid : UInt<1> ifvalid <= UInt<1>("h00") wire shift_f2_f1 : UInt<1> shift_f2_f1 <= UInt<1>("h00") wire shift_f2_f0 : UInt<1> shift_f2_f0 <= UInt<1>("h00") wire shift_f1_f0 : UInt<1> shift_f1_f0 <= UInt<1>("h00") wire f0icaf : UInt<1> f0icaf <= UInt<1>("h00") wire f1icaf : UInt<1> f1icaf <= UInt<1>("h00") wire sf0val : UInt<2> sf0val <= UInt<1>("h00") wire sf1val : UInt<2> sf1val <= UInt<1>("h00") wire misc0 : UInt<54> misc0 <= UInt<1>("h00") wire misc1 : UInt<54> misc1 <= UInt<1>("h00") wire misc2 : UInt<54> misc2 <= UInt<1>("h00") wire brdata1 : UInt<12> brdata1 <= UInt<1>("h00") wire brdata0 : UInt<12> brdata0 <= UInt<1>("h00") wire brdata2 : UInt<12> brdata2 <= UInt<1>("h00") reg error_stall : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 88:28] error_stall <= error_stall_in @[el2_ifu_aln_ctl.scala 88:28] reg f0val : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 89:22] f0val <= f0val_in @[el2_ifu_aln_ctl.scala 89:22] node _T = or(error_stall, io.ifu_async_error_start) @[el2_ifu_aln_ctl.scala 90:34] node _T_1 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 90:64] node _T_2 = and(_T, _T_1) @[el2_ifu_aln_ctl.scala 90:62] error_stall_in <= _T_2 @[el2_ifu_aln_ctl.scala 90:18] node _T_3 = not(error_stall) @[el2_ifu_aln_ctl.scala 92:39] node i0_shift = and(io.dec_i0_decode_d, _T_3) @[el2_ifu_aln_ctl.scala 92:37] io.ifu_pmu_instr_aligned <= i0_shift @[el2_ifu_aln_ctl.scala 94:28] node _T_4 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 96:34] node _T_5 = bits(_T_4, 0, 0) @[el2_ifu_aln_ctl.scala 96:38] node _T_6 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 96:64] node _T_7 = not(_T_6) @[el2_ifu_aln_ctl.scala 96:58] node _T_8 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 96:75] node _T_9 = and(_T_7, _T_8) @[el2_ifu_aln_ctl.scala 96:68] node _T_10 = bits(_T_9, 0, 0) @[el2_ifu_aln_ctl.scala 96:80] node _T_11 = cat(q1final, q0final) @[Cat.scala 29:58] node _T_12 = mux(_T_5, q0final, UInt<1>("h00")) @[Mux.scala 27:72] node _T_13 = mux(_T_10, _T_11, UInt<1>("h00")) @[Mux.scala 27:72] node _T_14 = or(_T_12, _T_13) @[Mux.scala 27:72] wire aligndata : UInt<32> @[Mux.scala 27:72] aligndata <= _T_14 @[Mux.scala 27:72] io.ifu_i0_instr <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 104:19] node _T_15 = bits(aligndata, 15, 0) @[el2_ifu_aln_ctl.scala 107:31] io.ifu_i0_cinst <= _T_15 @[el2_ifu_aln_ctl.scala 107:19] wire first4B : UInt<1> first4B <= UInt<1>("h00") node first2B = not(first4B) @[el2_ifu_aln_ctl.scala 112:17] node _T_16 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 113:34] node _T_17 = bits(_T_16, 0, 0) @[el2_ifu_aln_ctl.scala 113:38] node _T_18 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 113:63] node _T_19 = not(_T_18) @[el2_ifu_aln_ctl.scala 113:57] node _T_20 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 113:74] node _T_21 = and(_T_19, _T_20) @[el2_ifu_aln_ctl.scala 113:67] node _T_22 = bits(_T_21, 0, 0) @[el2_ifu_aln_ctl.scala 113:79] node _T_23 = cat(f1icaf, f0icaf) @[Cat.scala 29:58] node _T_24 = mux(_T_17, f0icaf, UInt<1>("h00")) @[Mux.scala 27:72] node _T_25 = mux(_T_22, _T_23, UInt<1>("h00")) @[Mux.scala 27:72] node _T_26 = or(_T_24, _T_25) @[Mux.scala 27:72] wire alignicaf : UInt<2> @[Mux.scala 27:72] alignicaf <= _T_26 @[Mux.scala 27:72] node _T_27 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 115:39] node _T_28 = orr(alignicaf) @[el2_ifu_aln_ctl.scala 115:59] node _T_29 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 115:72] node _T_30 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 115:91] node _T_31 = mux(_T_27, _T_28, UInt<1>("h00")) @[Mux.scala 27:72] node _T_32 = mux(_T_29, _T_30, UInt<1>("h00")) @[Mux.scala 27:72] node _T_33 = or(_T_31, _T_32) @[Mux.scala 27:72] wire _T_34 : UInt<1> @[Mux.scala 27:72] _T_34 <= _T_33 @[Mux.scala 27:72] io.ifu_i0_icaf <= _T_34 @[el2_ifu_aln_ctl.scala 115:18] node _T_35 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 116:40] node _T_36 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 116:58] node _T_37 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 116:71] node _T_38 = bits(alignval, 0, 0) @[el2_ifu_aln_ctl.scala 116:89] node _T_39 = mux(_T_35, _T_36, UInt<1>("h00")) @[Mux.scala 27:72] node _T_40 = mux(_T_37, _T_38, UInt<1>("h00")) @[Mux.scala 27:72] node _T_41 = or(_T_39, _T_40) @[Mux.scala 27:72] wire _T_42 : UInt<1> @[Mux.scala 27:72] _T_42 <= _T_41 @[Mux.scala 27:72] io.ifu_i0_valid <= _T_42 @[el2_ifu_aln_ctl.scala 116:19] io.ifu_i0_pc4 <= first4B @[el2_ifu_aln_ctl.scala 117:17] node shift_2B = and(i0_shift, first2B) @[el2_ifu_aln_ctl.scala 119:27] node shift_4B = and(i0_shift, first4B) @[el2_ifu_aln_ctl.scala 120:27] node _T_43 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 121:40] node _T_44 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 121:55] node _T_45 = bits(shift_4B, 0, 0) @[el2_ifu_aln_ctl.scala 121:69] node _T_46 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 121:86] node _T_47 = not(_T_46) @[el2_ifu_aln_ctl.scala 121:80] node _T_48 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 121:97] node _T_49 = and(_T_47, _T_48) @[el2_ifu_aln_ctl.scala 121:90] node _T_50 = mux(_T_43, _T_44, UInt<1>("h00")) @[Mux.scala 27:72] node _T_51 = mux(_T_45, _T_49, UInt<1>("h00")) @[Mux.scala 27:72] node _T_52 = or(_T_50, _T_51) @[Mux.scala 27:72] wire f0_shift_2B : UInt<1> @[Mux.scala 27:72] f0_shift_2B <= _T_52 @[Mux.scala 27:72] node _T_53 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 122:27] node _T_54 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 122:39] node _T_55 = not(_T_54) @[el2_ifu_aln_ctl.scala 122:33] node _T_56 = and(_T_53, _T_55) @[el2_ifu_aln_ctl.scala 122:31] node f1_shift_2B = and(_T_56, shift_4B) @[el2_ifu_aln_ctl.scala 122:43] reg wrptr : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 124:22] wrptr <= wrptr_in @[el2_ifu_aln_ctl.scala 124:22] reg rdptr : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 125:22] rdptr <= wrptr_in @[el2_ifu_aln_ctl.scala 125:22] reg f2val : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 127:22] f2val <= f2val_in @[el2_ifu_aln_ctl.scala 127:22] reg f1val : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 128:22] f1val <= f1val_in @[el2_ifu_aln_ctl.scala 128:22] reg q2off : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 131:22] q2off <= q2off_in @[el2_ifu_aln_ctl.scala 131:22] reg q1off : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 132:22] q1off <= q1off_in @[el2_ifu_aln_ctl.scala 132:22] reg q0off : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 133:22] q0off <= q0off_in @[el2_ifu_aln_ctl.scala 133:22] node _T_57 = not(sf0_valid) @[el2_ifu_aln_ctl.scala 135:29] node _T_58 = not(sf1_valid) @[el2_ifu_aln_ctl.scala 135:42] node _T_59 = and(_T_57, _T_58) @[el2_ifu_aln_ctl.scala 135:40] node _T_60 = not(f2_valid) @[el2_ifu_aln_ctl.scala 135:55] node _T_61 = and(_T_59, _T_60) @[el2_ifu_aln_ctl.scala 135:53] node fetch_to_f0 = and(_T_61, ifvalid) @[el2_ifu_aln_ctl.scala 135:65] node _T_62 = not(sf0_valid) @[el2_ifu_aln_ctl.scala 136:29] node _T_63 = not(sf1_valid) @[el2_ifu_aln_ctl.scala 136:42] node _T_64 = and(_T_62, _T_63) @[el2_ifu_aln_ctl.scala 136:40] node _T_65 = and(_T_64, f2_valid) @[el2_ifu_aln_ctl.scala 136:53] node _T_66 = and(_T_65, ifvalid) @[el2_ifu_aln_ctl.scala 136:65] node _T_67 = not(sf0_valid) @[el2_ifu_aln_ctl.scala 137:6] node _T_68 = and(_T_67, sf1_valid) @[el2_ifu_aln_ctl.scala 137:17] node _T_69 = not(f2_valid) @[el2_ifu_aln_ctl.scala 137:32] node _T_70 = and(_T_68, _T_69) @[el2_ifu_aln_ctl.scala 137:30] node _T_71 = and(_T_70, ifvalid) @[el2_ifu_aln_ctl.scala 137:42] node _T_72 = or(_T_66, _T_71) @[el2_ifu_aln_ctl.scala 136:77] node _T_73 = not(sf1_valid) @[el2_ifu_aln_ctl.scala 138:19] node _T_74 = and(sf0_valid, _T_73) @[el2_ifu_aln_ctl.scala 138:17] node _T_75 = not(f2_valid) @[el2_ifu_aln_ctl.scala 138:32] node _T_76 = and(_T_74, _T_75) @[el2_ifu_aln_ctl.scala 138:30] node _T_77 = and(_T_76, ifvalid) @[el2_ifu_aln_ctl.scala 138:42] node fetch_to_f1 = or(_T_72, _T_77) @[el2_ifu_aln_ctl.scala 137:54] node _T_78 = not(sf0_valid) @[el2_ifu_aln_ctl.scala 139:29] node _T_79 = and(_T_78, sf1_valid) @[el2_ifu_aln_ctl.scala 139:40] node _T_80 = and(_T_79, f2_valid) @[el2_ifu_aln_ctl.scala 139:53] node _T_81 = and(_T_80, ifvalid) @[el2_ifu_aln_ctl.scala 139:65] node _T_82 = and(sf0_valid, sf1_valid) @[el2_ifu_aln_ctl.scala 140:17] node _T_83 = not(f2_valid) @[el2_ifu_aln_ctl.scala 140:32] node _T_84 = and(_T_82, _T_83) @[el2_ifu_aln_ctl.scala 140:30] node _T_85 = and(_T_84, ifvalid) @[el2_ifu_aln_ctl.scala 140:42] node f2_wr_en = or(_T_81, _T_85) @[el2_ifu_aln_ctl.scala 139:77] node _T_86 = or(fetch_to_f1, shift_f2_f1) @[el2_ifu_aln_ctl.scala 143:36] node f1_shift_wr_en = or(_T_86, f1_shift_2B) @[el2_ifu_aln_ctl.scala 143:50] node _T_87 = or(fetch_to_f0, shift_f2_f0) @[el2_ifu_aln_ctl.scala 144:36] node _T_88 = or(_T_87, shift_f1_f0) @[el2_ifu_aln_ctl.scala 144:50] node _T_89 = or(_T_88, shift_2B) @[el2_ifu_aln_ctl.scala 144:64] node f0_shift_wr_en = or(_T_89, shift_4B) @[el2_ifu_aln_ctl.scala 144:75] node _T_90 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 146:24] node _T_91 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 146:39] node _T_92 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 146:54] node _T_93 = cat(_T_90, _T_91) @[Cat.scala 29:58] node qren = cat(_T_93, _T_92) @[Cat.scala 29:58] node _T_94 = eq(wrptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 147:24] node _T_95 = and(_T_94, ifvalid) @[el2_ifu_aln_ctl.scala 147:32] node _T_96 = eq(wrptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 147:49] node _T_97 = and(_T_96, ifvalid) @[el2_ifu_aln_ctl.scala 147:57] node _T_98 = eq(wrptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 147:74] node _T_99 = and(_T_98, ifvalid) @[el2_ifu_aln_ctl.scala 147:82] node _T_100 = cat(_T_95, _T_97) @[Cat.scala 29:58] node qwen = cat(_T_100, _T_99) @[Cat.scala 29:58] node _T_101 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 149:30] node _T_102 = and(_T_101, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 149:34] node _T_103 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 149:57] node _T_104 = and(_T_102, _T_103) @[el2_ifu_aln_ctl.scala 149:55] node _T_105 = bits(_T_104, 0, 0) @[el2_ifu_aln_ctl.scala 149:78] node _T_106 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 150:30] node _T_107 = and(_T_106, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 150:34] node _T_108 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 150:57] node _T_109 = and(_T_107, _T_108) @[el2_ifu_aln_ctl.scala 150:55] node _T_110 = bits(_T_109, 0, 0) @[el2_ifu_aln_ctl.scala 150:78] node _T_111 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 151:30] node _T_112 = and(_T_111, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 151:34] node _T_113 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 151:57] node _T_114 = and(_T_112, _T_113) @[el2_ifu_aln_ctl.scala 151:55] node _T_115 = bits(_T_114, 0, 0) @[el2_ifu_aln_ctl.scala 151:78] node _T_116 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 152:30] node _T_117 = and(_T_116, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 152:34] node _T_118 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 152:57] node _T_119 = and(_T_117, _T_118) @[el2_ifu_aln_ctl.scala 152:55] node _T_120 = bits(_T_119, 0, 0) @[el2_ifu_aln_ctl.scala 152:78] node _T_121 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 153:30] node _T_122 = and(_T_121, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 153:34] node _T_123 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 153:57] node _T_124 = and(_T_122, _T_123) @[el2_ifu_aln_ctl.scala 153:55] node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_aln_ctl.scala 153:78] node _T_126 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 154:30] node _T_127 = and(_T_126, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 154:34] node _T_128 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 154:57] node _T_129 = and(_T_127, _T_128) @[el2_ifu_aln_ctl.scala 154:55] node _T_130 = bits(_T_129, 0, 0) @[el2_ifu_aln_ctl.scala 154:78] node _T_131 = not(io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 155:12] node _T_132 = not(io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 155:34] node _T_133 = and(_T_131, _T_132) @[el2_ifu_aln_ctl.scala 155:32] node _T_134 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 155:56] node _T_135 = and(_T_133, _T_134) @[el2_ifu_aln_ctl.scala 155:54] node _T_136 = bits(_T_135, 0, 0) @[el2_ifu_aln_ctl.scala 155:77] node _T_137 = mux(_T_105, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_138 = mux(_T_110, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_139 = mux(_T_115, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_140 = mux(_T_120, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_141 = mux(_T_125, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_142 = mux(_T_130, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_143 = mux(_T_136, rdptr, UInt<1>("h00")) @[Mux.scala 27:72] node _T_144 = or(_T_137, _T_138) @[Mux.scala 27:72] node _T_145 = or(_T_144, _T_139) @[Mux.scala 27:72] node _T_146 = or(_T_145, _T_140) @[Mux.scala 27:72] node _T_147 = or(_T_146, _T_141) @[Mux.scala 27:72] node _T_148 = or(_T_147, _T_142) @[Mux.scala 27:72] node _T_149 = or(_T_148, _T_143) @[Mux.scala 27:72] wire _T_150 : UInt @[Mux.scala 27:72] _T_150 <= _T_149 @[Mux.scala 27:72] rdptr_in <= _T_150 @[el2_ifu_aln_ctl.scala 149:12] node _T_151 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 157:30] node _T_152 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 157:36] node _T_153 = and(_T_151, _T_152) @[el2_ifu_aln_ctl.scala 157:34] node _T_154 = bits(_T_153, 0, 0) @[el2_ifu_aln_ctl.scala 157:57] node _T_155 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 158:30] node _T_156 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 158:36] node _T_157 = and(_T_155, _T_156) @[el2_ifu_aln_ctl.scala 158:34] node _T_158 = bits(_T_157, 0, 0) @[el2_ifu_aln_ctl.scala 158:57] node _T_159 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 159:30] node _T_160 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 159:36] node _T_161 = and(_T_159, _T_160) @[el2_ifu_aln_ctl.scala 159:34] node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_aln_ctl.scala 159:57] node _T_163 = not(ifvalid) @[el2_ifu_aln_ctl.scala 160:26] node _T_164 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 160:37] node _T_165 = and(_T_163, _T_164) @[el2_ifu_aln_ctl.scala 160:35] node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_aln_ctl.scala 160:58] node _T_167 = mux(_T_154, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_168 = mux(_T_158, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_169 = mux(_T_162, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_170 = mux(_T_166, wrptr, UInt<1>("h00")) @[Mux.scala 27:72] node _T_171 = or(_T_167, _T_168) @[Mux.scala 27:72] node _T_172 = or(_T_171, _T_169) @[Mux.scala 27:72] node _T_173 = or(_T_172, _T_170) @[Mux.scala 27:72] wire _T_174 : UInt @[Mux.scala 27:72] _T_174 <= _T_173 @[Mux.scala 27:72] wrptr_in <= _T_174 @[el2_ifu_aln_ctl.scala 157:12] node _T_175 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 162:31] node _T_176 = not(_T_175) @[el2_ifu_aln_ctl.scala 162:26] node _T_177 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 162:43] node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 162:35] node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 162:52] node _T_180 = or(q2off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 162:74] node _T_181 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 163:31] node _T_182 = not(_T_181) @[el2_ifu_aln_ctl.scala 163:26] node _T_183 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 163:43] node _T_184 = and(_T_182, _T_183) @[el2_ifu_aln_ctl.scala 163:35] node _T_185 = bits(_T_184, 0, 0) @[el2_ifu_aln_ctl.scala 163:52] node _T_186 = or(q2off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 163:74] node _T_187 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 164:31] node _T_188 = not(_T_187) @[el2_ifu_aln_ctl.scala 164:26] node _T_189 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 164:43] node _T_190 = and(_T_188, _T_189) @[el2_ifu_aln_ctl.scala 164:35] node _T_191 = bits(_T_190, 0, 0) @[el2_ifu_aln_ctl.scala 164:52] node _T_192 = mux(_T_179, _T_180, UInt<1>("h00")) @[Mux.scala 27:72] node _T_193 = mux(_T_185, _T_186, UInt<1>("h00")) @[Mux.scala 27:72] node _T_194 = mux(_T_191, q2off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_195 = or(_T_192, _T_193) @[Mux.scala 27:72] node _T_196 = or(_T_195, _T_194) @[Mux.scala 27:72] wire _T_197 : UInt @[Mux.scala 27:72] _T_197 <= _T_196 @[Mux.scala 27:72] q2off_in <= _T_197 @[el2_ifu_aln_ctl.scala 162:12] node _T_198 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 166:31] node _T_199 = not(_T_198) @[el2_ifu_aln_ctl.scala 166:26] node _T_200 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 166:43] node _T_201 = and(_T_199, _T_200) @[el2_ifu_aln_ctl.scala 166:35] node _T_202 = bits(_T_201, 0, 0) @[el2_ifu_aln_ctl.scala 166:52] node _T_203 = or(q1off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 166:74] node _T_204 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 167:31] node _T_205 = not(_T_204) @[el2_ifu_aln_ctl.scala 167:26] node _T_206 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 167:43] node _T_207 = and(_T_205, _T_206) @[el2_ifu_aln_ctl.scala 167:35] node _T_208 = bits(_T_207, 0, 0) @[el2_ifu_aln_ctl.scala 167:52] node _T_209 = or(q1off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 167:74] node _T_210 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 168:31] node _T_211 = not(_T_210) @[el2_ifu_aln_ctl.scala 168:26] node _T_212 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 168:43] node _T_213 = and(_T_211, _T_212) @[el2_ifu_aln_ctl.scala 168:35] node _T_214 = bits(_T_213, 0, 0) @[el2_ifu_aln_ctl.scala 168:52] node _T_215 = mux(_T_202, _T_203, UInt<1>("h00")) @[Mux.scala 27:72] node _T_216 = mux(_T_208, _T_209, UInt<1>("h00")) @[Mux.scala 27:72] node _T_217 = mux(_T_214, q1off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_218 = or(_T_215, _T_216) @[Mux.scala 27:72] node _T_219 = or(_T_218, _T_217) @[Mux.scala 27:72] wire _T_220 : UInt @[Mux.scala 27:72] _T_220 <= _T_219 @[Mux.scala 27:72] q1off_in <= _T_220 @[el2_ifu_aln_ctl.scala 166:12] node _T_221 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 170:31] node _T_222 = not(_T_221) @[el2_ifu_aln_ctl.scala 170:26] node _T_223 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 170:43] node _T_224 = and(_T_222, _T_223) @[el2_ifu_aln_ctl.scala 170:35] node _T_225 = bits(_T_224, 0, 0) @[el2_ifu_aln_ctl.scala 170:52] node _T_226 = or(q0off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 170:76] node _T_227 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 171:31] node _T_228 = not(_T_227) @[el2_ifu_aln_ctl.scala 171:26] node _T_229 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 171:43] node _T_230 = and(_T_228, _T_229) @[el2_ifu_aln_ctl.scala 171:35] node _T_231 = bits(_T_230, 0, 0) @[el2_ifu_aln_ctl.scala 171:52] node _T_232 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 171:76] node _T_233 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 172:31] node _T_234 = not(_T_233) @[el2_ifu_aln_ctl.scala 172:26] node _T_235 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 172:43] node _T_236 = and(_T_234, _T_235) @[el2_ifu_aln_ctl.scala 172:35] node _T_237 = bits(_T_236, 0, 0) @[el2_ifu_aln_ctl.scala 172:52] node _T_238 = mux(_T_225, _T_226, UInt<1>("h00")) @[Mux.scala 27:72] node _T_239 = mux(_T_231, _T_232, UInt<1>("h00")) @[Mux.scala 27:72] node _T_240 = mux(_T_237, q0off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_241 = or(_T_238, _T_239) @[Mux.scala 27:72] node _T_242 = or(_T_241, _T_240) @[Mux.scala 27:72] wire _T_243 : UInt @[Mux.scala 27:72] _T_243 <= _T_242 @[Mux.scala 27:72] q0off_in <= _T_243 @[el2_ifu_aln_ctl.scala 170:12] node _T_244 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 174:31] node _T_245 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 175:31] node _T_246 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 176:31] node _T_247 = mux(_T_244, q0off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_248 = mux(_T_245, q1off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_249 = mux(_T_246, q2off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_250 = or(_T_247, _T_248) @[Mux.scala 27:72] node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72] wire q0ptr : UInt @[Mux.scala 27:72] q0ptr <= _T_251 @[Mux.scala 27:72] node _T_252 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 178:32] node _T_253 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 178:57] node _T_254 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 178:83] node _T_255 = mux(_T_252, q1off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_256 = mux(_T_253, q2off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_257 = mux(_T_254, q0off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_258 = or(_T_255, _T_256) @[Mux.scala 27:72] node _T_259 = or(_T_258, _T_257) @[Mux.scala 27:72] wire q1ptr : UInt @[Mux.scala 27:72] q1ptr <= _T_259 @[Mux.scala 27:72] node _T_260 = not(q0ptr) @[el2_ifu_aln_ctl.scala 180:26] node q0sel = cat(q0ptr, _T_260) @[Cat.scala 29:58] node _T_261 = not(q1ptr) @[el2_ifu_aln_ctl.scala 182:26] node q1sel = cat(q1ptr, _T_261) @[Cat.scala 29:58] node _T_262 = bits(io.ifu_bp_btb_target_f, 31, 1) @[el2_ifu_aln_ctl.scala 185:25] node _T_263 = cat(_T_262, io.ifu_bp_poffset_f) @[Cat.scala 29:58] node _T_264 = cat(_T_263, io.ifu_bp_fghr_f) @[Cat.scala 29:58] node _T_265 = cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f) @[Cat.scala 29:58] node _T_266 = cat(_T_265, io.ic_access_fault_type_f) @[Cat.scala 29:58] node misc_data_in = cat(_T_266, _T_264) @[Cat.scala 29:58] node _T_267 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 187:31] node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_aln_ctl.scala 187:41] node _T_269 = cat(misc1, misc0) @[Cat.scala 29:58] node _T_270 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 188:27] node _T_271 = bits(_T_270, 0, 0) @[el2_ifu_aln_ctl.scala 188:37] node _T_272 = cat(misc2, misc1) @[Cat.scala 29:58] node _T_273 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 189:27] node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_aln_ctl.scala 189:37] node _T_275 = cat(misc0, misc2) @[Cat.scala 29:58] node _T_276 = mux(_T_268, _T_269, UInt<1>("h00")) @[Mux.scala 27:72] node _T_277 = mux(_T_271, _T_272, UInt<1>("h00")) @[Mux.scala 27:72] node _T_278 = mux(_T_274, _T_275, UInt<1>("h00")) @[Mux.scala 27:72] node _T_279 = or(_T_276, _T_277) @[Mux.scala 27:72] node _T_280 = or(_T_279, _T_278) @[Mux.scala 27:72] wire misceff : UInt<108> @[Mux.scala 27:72] misceff <= _T_280 @[Mux.scala 27:72] node misc1eff = bits(misceff, 107, 55) @[el2_ifu_aln_ctl.scala 191:25] node misc0eff = bits(misceff, 54, 0) @[el2_ifu_aln_ctl.scala 192:25] node f1dbecc = bits(misc1eff, 52, 52) @[el2_ifu_aln_ctl.scala 194:25] node _T_281 = bits(misc1eff, 51, 51) @[el2_ifu_aln_ctl.scala 195:21] f1icaf <= _T_281 @[el2_ifu_aln_ctl.scala 195:10] node f1ictype = bits(misc1eff, 50, 49) @[el2_ifu_aln_ctl.scala 196:26] node f1prett = bits(misc1eff, 48, 18) @[el2_ifu_aln_ctl.scala 197:25] node f1poffset = bits(misc1eff, 19, 8) @[el2_ifu_aln_ctl.scala 198:27] node f1fghr = bits(misc1eff, 7, 0) @[el2_ifu_aln_ctl.scala 199:24] node f0dbecc = bits(misc0eff, 54, 54) @[el2_ifu_aln_ctl.scala 201:25] node _T_282 = bits(misc0eff, 53, 53) @[el2_ifu_aln_ctl.scala 202:21] f0icaf <= _T_282 @[el2_ifu_aln_ctl.scala 202:10] node f0ictype = bits(misc0eff, 52, 51) @[el2_ifu_aln_ctl.scala 203:26] node f0prett = bits(misc0eff, 50, 20) @[el2_ifu_aln_ctl.scala 204:25] node f0poffset = bits(misc0eff, 19, 8) @[el2_ifu_aln_ctl.scala 205:27] node f0fghr = bits(misc0eff, 7, 0) @[el2_ifu_aln_ctl.scala 206:24] node _T_283 = bits(io.ifu_bp_hist1_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:40] node _T_284 = bits(io.ifu_bp_hist0_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:61] node _T_285 = bits(io.ifu_bp_pc4_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:80] node _T_286 = bits(io.ifu_bp_way_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:99] node _T_287 = bits(io.ifu_bp_valid_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:120] node _T_288 = bits(io.ifu_bp_ret_f, 1, 1) @[el2_ifu_aln_ctl.scala 209:20] node _T_289 = bits(io.ifu_bp_hist1_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:42] node _T_290 = bits(io.ifu_bp_hist0_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:63] node _T_291 = bits(io.ifu_bp_pc4_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:82] node _T_292 = bits(io.ifu_bp_way_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:101] node _T_293 = bits(io.ifu_bp_valid_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:22] node _T_294 = bits(io.ifu_bp_ret_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:41] node _T_295 = cat(_T_292, _T_293) @[Cat.scala 29:58] node _T_296 = cat(_T_295, _T_294) @[Cat.scala 29:58] node _T_297 = cat(_T_289, _T_290) @[Cat.scala 29:58] node _T_298 = cat(_T_297, _T_291) @[Cat.scala 29:58] node _T_299 = cat(_T_298, _T_296) @[Cat.scala 29:58] node _T_300 = cat(_T_286, _T_287) @[Cat.scala 29:58] node _T_301 = cat(_T_300, _T_288) @[Cat.scala 29:58] node _T_302 = cat(_T_283, _T_284) @[Cat.scala 29:58] node _T_303 = cat(_T_302, _T_285) @[Cat.scala 29:58] node _T_304 = cat(_T_303, _T_301) @[Cat.scala 29:58] node brdata_in = cat(_T_304, _T_299) @[Cat.scala 29:58] node _T_305 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 212:33] node _T_306 = bits(_T_305, 0, 0) @[el2_ifu_aln_ctl.scala 212:37] node _T_307 = cat(brdata1, brdata0) @[Cat.scala 29:58] node _T_308 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 213:33] node _T_309 = bits(_T_308, 0, 0) @[el2_ifu_aln_ctl.scala 213:37] node _T_310 = cat(brdata2, brdata1) @[Cat.scala 29:58] node _T_311 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 214:33] node _T_312 = bits(_T_311, 0, 0) @[el2_ifu_aln_ctl.scala 214:37] node _T_313 = cat(brdata0, brdata2) @[Cat.scala 29:58] node _T_314 = mux(_T_306, _T_307, UInt<1>("h00")) @[Mux.scala 27:72] node _T_315 = mux(_T_309, _T_310, UInt<1>("h00")) @[Mux.scala 27:72] node _T_316 = mux(_T_312, _T_313, UInt<1>("h00")) @[Mux.scala 27:72] node _T_317 = or(_T_314, _T_315) @[Mux.scala 27:72] node _T_318 = or(_T_317, _T_316) @[Mux.scala 27:72] wire brdataeff : UInt<24> @[Mux.scala 27:72] brdataeff <= _T_318 @[Mux.scala 27:72] node brdata0eff = bits(brdataeff, 11, 0) @[el2_ifu_aln_ctl.scala 216:43] node brdata1eff = bits(brdataeff, 23, 12) @[el2_ifu_aln_ctl.scala 216:61] wire q0 : UInt<32> q0 <= UInt<1>("h00") wire q1 : UInt<32> q1 <= UInt<1>("h00") wire q2 : UInt<32> q2 <= UInt<1>("h00") node _T_319 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 222:28] node _T_320 = bits(_T_319, 0, 0) @[el2_ifu_aln_ctl.scala 222:32] node _T_321 = cat(q1, q0) @[Cat.scala 29:58] node _T_322 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 223:27] node _T_323 = bits(_T_322, 0, 0) @[el2_ifu_aln_ctl.scala 223:31] node _T_324 = cat(q2, q1) @[Cat.scala 29:58] node _T_325 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 224:27] node _T_326 = bits(_T_325, 0, 0) @[el2_ifu_aln_ctl.scala 224:31] node _T_327 = cat(q0, q2) @[Cat.scala 29:58] node _T_328 = mux(_T_320, _T_321, UInt<1>("h00")) @[Mux.scala 27:72] node _T_329 = mux(_T_323, _T_324, UInt<1>("h00")) @[Mux.scala 27:72] node _T_330 = mux(_T_326, _T_327, UInt<1>("h00")) @[Mux.scala 27:72] node _T_331 = or(_T_328, _T_329) @[Mux.scala 27:72] node _T_332 = or(_T_331, _T_330) @[Mux.scala 27:72] wire qeff : UInt<64> @[Mux.scala 27:72] qeff <= _T_332 @[Mux.scala 27:72] node q1eff = bits(qeff, 63, 32) @[el2_ifu_aln_ctl.scala 225:29] node q0eff = bits(qeff, 31, 0) @[el2_ifu_aln_ctl.scala 225:42] node _T_333 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 226:37] node _T_334 = bits(_T_333, 0, 0) @[el2_ifu_aln_ctl.scala 226:41] node _T_335 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 226:68] node _T_336 = bits(_T_335, 0, 0) @[el2_ifu_aln_ctl.scala 226:72] node _T_337 = bits(brdata0eff, 11, 6) @[el2_ifu_aln_ctl.scala 226:92] node _T_338 = mux(_T_334, brdata0eff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_339 = mux(_T_336, _T_337, UInt<1>("h00")) @[Mux.scala 27:72] node _T_340 = or(_T_338, _T_339) @[Mux.scala 27:72] wire brdata0final : UInt<12> @[Mux.scala 27:72] brdata0final <= _T_340 @[Mux.scala 27:72] node _T_341 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 228:37] node _T_342 = bits(_T_341, 0, 0) @[el2_ifu_aln_ctl.scala 228:41] node _T_343 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 228:68] node _T_344 = bits(_T_343, 0, 0) @[el2_ifu_aln_ctl.scala 228:72] node _T_345 = bits(brdata1eff, 11, 6) @[el2_ifu_aln_ctl.scala 228:92] node _T_346 = mux(_T_342, brdata1eff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_347 = mux(_T_344, _T_345, UInt<1>("h00")) @[Mux.scala 27:72] node _T_348 = or(_T_346, _T_347) @[Mux.scala 27:72] wire brdata1final : UInt<12> @[Mux.scala 27:72] brdata1final <= _T_348 @[Mux.scala 27:72] node _T_349 = bits(brdata0final, 6, 6) @[el2_ifu_aln_ctl.scala 230:31] node _T_350 = bits(brdata0final, 0, 0) @[el2_ifu_aln_ctl.scala 230:47] node f0ret = cat(_T_349, _T_350) @[Cat.scala 29:58] node _T_351 = bits(brdata0final, 7, 7) @[el2_ifu_aln_ctl.scala 231:33] node _T_352 = bits(brdata0final, 1, 1) @[el2_ifu_aln_ctl.scala 231:49] node f0brend = cat(_T_351, _T_352) @[Cat.scala 29:58] node _T_353 = bits(brdata0final, 8, 8) @[el2_ifu_aln_ctl.scala 232:31] node _T_354 = bits(brdata0final, 2, 2) @[el2_ifu_aln_ctl.scala 232:47] node f0way = cat(_T_353, _T_354) @[Cat.scala 29:58] node _T_355 = bits(brdata0final, 9, 9) @[el2_ifu_aln_ctl.scala 233:31] node _T_356 = bits(brdata0final, 3, 3) @[el2_ifu_aln_ctl.scala 233:47] node f0pc4 = cat(_T_355, _T_356) @[Cat.scala 29:58] node _T_357 = bits(brdata0final, 10, 10) @[el2_ifu_aln_ctl.scala 234:33] node _T_358 = bits(brdata0final, 4, 4) @[el2_ifu_aln_ctl.scala 234:50] node f0hist0 = cat(_T_357, _T_358) @[Cat.scala 29:58] node _T_359 = bits(brdata0final, 11, 11) @[el2_ifu_aln_ctl.scala 235:33] node _T_360 = bits(brdata0final, 5, 5) @[el2_ifu_aln_ctl.scala 235:50] node f0hist1 = cat(_T_359, _T_360) @[Cat.scala 29:58] node _T_361 = bits(brdata1final, 6, 6) @[el2_ifu_aln_ctl.scala 237:31] node _T_362 = bits(brdata1final, 0, 0) @[el2_ifu_aln_ctl.scala 237:47] node f1ret = cat(_T_361, _T_362) @[Cat.scala 29:58] node _T_363 = bits(brdata1final, 7, 7) @[el2_ifu_aln_ctl.scala 238:33] node _T_364 = bits(brdata1final, 1, 1) @[el2_ifu_aln_ctl.scala 238:49] node f1brend = cat(_T_363, _T_364) @[Cat.scala 29:58] node _T_365 = bits(brdata1final, 8, 8) @[el2_ifu_aln_ctl.scala 239:31] node _T_366 = bits(brdata1final, 2, 2) @[el2_ifu_aln_ctl.scala 239:47] node f1way = cat(_T_365, _T_366) @[Cat.scala 29:58] node _T_367 = bits(brdata1final, 9, 9) @[el2_ifu_aln_ctl.scala 240:31] node _T_368 = bits(brdata1final, 3, 3) @[el2_ifu_aln_ctl.scala 240:47] node f1pc4 = cat(_T_367, _T_368) @[Cat.scala 29:58] node _T_369 = bits(brdata1final, 10, 10) @[el2_ifu_aln_ctl.scala 241:33] node _T_370 = bits(brdata1final, 4, 4) @[el2_ifu_aln_ctl.scala 241:50] node f1hist0 = cat(_T_369, _T_370) @[Cat.scala 29:58] node _T_371 = bits(brdata1final, 11, 11) @[el2_ifu_aln_ctl.scala 242:33] node _T_372 = bits(brdata1final, 5, 5) @[el2_ifu_aln_ctl.scala 242:50] node f1hist1 = cat(_T_371, _T_372) @[Cat.scala 29:58] node _T_373 = bits(f2val, 0, 0) @[el2_ifu_aln_ctl.scala 246:20] f2_valid <= _T_373 @[el2_ifu_aln_ctl.scala 246:12] node _T_374 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 247:22] sf1_valid <= _T_374 @[el2_ifu_aln_ctl.scala 247:13] node _T_375 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 248:22] sf0_valid <= _T_375 @[el2_ifu_aln_ctl.scala 248:13] node _T_376 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 250:28] node _T_377 = not(_T_376) @[el2_ifu_aln_ctl.scala 250:21] node _T_378 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 250:39] node consume_fb0 = and(_T_377, _T_378) @[el2_ifu_aln_ctl.scala 250:32] node _T_379 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 251:28] node _T_380 = not(_T_379) @[el2_ifu_aln_ctl.scala 251:21] node _T_381 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 251:39] node consume_fb1 = and(_T_380, _T_381) @[el2_ifu_aln_ctl.scala 251:32] node _T_382 = not(consume_fb1) @[el2_ifu_aln_ctl.scala 253:39] node _T_383 = and(consume_fb0, _T_382) @[el2_ifu_aln_ctl.scala 253:37] node _T_384 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 253:54] node _T_385 = and(_T_383, _T_384) @[el2_ifu_aln_ctl.scala 253:52] io.ifu_fb_consume1 <= _T_385 @[el2_ifu_aln_ctl.scala 253:22] node _T_386 = and(consume_fb0, consume_fb1) @[el2_ifu_aln_ctl.scala 254:37] node _T_387 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 254:54] node _T_388 = and(_T_386, _T_387) @[el2_ifu_aln_ctl.scala 254:52] io.ifu_fb_consume2 <= _T_388 @[el2_ifu_aln_ctl.scala 254:22] node _T_389 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_aln_ctl.scala 256:30] ifvalid <= _T_389 @[el2_ifu_aln_ctl.scala 256:11] node _T_390 = not(sf0_valid) @[el2_ifu_aln_ctl.scala 258:18] node _T_391 = and(_T_390, sf1_valid) @[el2_ifu_aln_ctl.scala 258:29] shift_f1_f0 <= _T_391 @[el2_ifu_aln_ctl.scala 258:15] node _T_392 = not(sf0_valid) @[el2_ifu_aln_ctl.scala 259:18] node _T_393 = not(sf1_valid) @[el2_ifu_aln_ctl.scala 259:31] node _T_394 = and(_T_392, _T_393) @[el2_ifu_aln_ctl.scala 259:29] node _T_395 = and(_T_394, f2_valid) @[el2_ifu_aln_ctl.scala 259:42] shift_f2_f0 <= _T_395 @[el2_ifu_aln_ctl.scala 259:15] node _T_396 = not(sf0_valid) @[el2_ifu_aln_ctl.scala 260:18] node _T_397 = and(_T_396, sf1_valid) @[el2_ifu_aln_ctl.scala 260:29] node _T_398 = and(_T_397, f2_valid) @[el2_ifu_aln_ctl.scala 260:42] shift_f2_f1 <= _T_398 @[el2_ifu_aln_ctl.scala 260:15] wire f0pc : UInt<31> f0pc <= UInt<1>("h00") wire f2pc : UInt<31> f2pc <= UInt<1>("h00") node _T_399 = add(f0pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 265:25] node f0pc_plus1 = tail(_T_399, 1) @[el2_ifu_aln_ctl.scala 265:25] node _T_400 = bits(f1_shift_2B, 0, 0) @[Bitwise.scala 72:15] node _T_401 = mux(_T_400, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] node _T_402 = and(_T_401, f0pc_plus1) @[el2_ifu_aln_ctl.scala 267:38] node _T_403 = not(f1_shift_2B) @[el2_ifu_aln_ctl.scala 267:64] node _T_404 = bits(_T_403, 0, 0) @[Bitwise.scala 72:15] node _T_405 = mux(_T_404, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] node _T_406 = and(_T_405, f0pc) @[el2_ifu_aln_ctl.scala 267:78] node sf1pc = or(_T_402, _T_406) @[el2_ifu_aln_ctl.scala 267:52] node _T_407 = bits(fetch_to_f1, 0, 0) @[el2_ifu_aln_ctl.scala 269:39] node _T_408 = bits(shift_f2_f1, 0, 0) @[el2_ifu_aln_ctl.scala 270:39] node _T_409 = not(fetch_to_f1) @[el2_ifu_aln_ctl.scala 271:28] node _T_410 = not(shift_f2_f1) @[el2_ifu_aln_ctl.scala 271:43] node _T_411 = and(_T_409, _T_410) @[el2_ifu_aln_ctl.scala 271:41] node _T_412 = bits(_T_411, 0, 0) @[el2_ifu_aln_ctl.scala 271:57] node _T_413 = mux(_T_407, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_414 = mux(_T_408, f2pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_415 = mux(_T_412, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_416 = or(_T_413, _T_414) @[Mux.scala 27:72] node _T_417 = or(_T_416, _T_415) @[Mux.scala 27:72] wire f1pc_in : UInt<32> @[Mux.scala 27:72] f1pc_in <= _T_417 @[Mux.scala 27:72] node _T_418 = bits(fetch_to_f0, 0, 0) @[el2_ifu_aln_ctl.scala 273:39] node _T_419 = bits(shift_f2_f0, 0, 0) @[el2_ifu_aln_ctl.scala 274:39] node _T_420 = bits(shift_f1_f0, 0, 0) @[el2_ifu_aln_ctl.scala 275:39] node _T_421 = not(fetch_to_f0) @[el2_ifu_aln_ctl.scala 276:28] node _T_422 = not(shift_f2_f0) @[el2_ifu_aln_ctl.scala 276:43] node _T_423 = and(_T_421, _T_422) @[el2_ifu_aln_ctl.scala 276:41] node _T_424 = not(shift_f1_f0) @[el2_ifu_aln_ctl.scala 276:58] node _T_425 = and(_T_423, _T_424) @[el2_ifu_aln_ctl.scala 276:56] node _T_426 = bits(_T_425, 0, 0) @[el2_ifu_aln_ctl.scala 276:72] node _T_427 = mux(_T_418, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_428 = mux(_T_419, f2pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_429 = mux(_T_420, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_430 = mux(_T_426, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_431 = or(_T_427, _T_428) @[Mux.scala 27:72] node _T_432 = or(_T_431, _T_429) @[Mux.scala 27:72] node _T_433 = or(_T_432, _T_430) @[Mux.scala 27:72] wire f0pc_in : UInt<32> @[Mux.scala 27:72] f0pc_in <= _T_433 @[Mux.scala 27:72] node _T_434 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 278:40] node _T_435 = and(f2_wr_en, _T_434) @[el2_ifu_aln_ctl.scala 278:38] node _T_436 = bits(_T_435, 0, 0) @[el2_ifu_aln_ctl.scala 278:61] node _T_437 = not(f2_wr_en) @[el2_ifu_aln_ctl.scala 279:6] node _T_438 = not(shift_f2_f1) @[el2_ifu_aln_ctl.scala 279:21] node _T_439 = and(_T_437, _T_438) @[el2_ifu_aln_ctl.scala 279:19] node _T_440 = not(shift_f2_f0) @[el2_ifu_aln_ctl.scala 279:36] node _T_441 = and(_T_439, _T_440) @[el2_ifu_aln_ctl.scala 279:34] node _T_442 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 279:51] node _T_443 = and(_T_441, _T_442) @[el2_ifu_aln_ctl.scala 279:49] node _T_444 = bits(_T_443, 0, 0) @[el2_ifu_aln_ctl.scala 279:72] node _T_445 = mux(_T_436, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_446 = mux(_T_444, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_447 = or(_T_445, _T_446) @[Mux.scala 27:72] wire _T_448 : UInt @[Mux.scala 27:72] _T_448 <= _T_447 @[Mux.scala 27:72] f2val_in <= _T_448 @[el2_ifu_aln_ctl.scala 278:12] node _T_449 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 281:35] node _T_450 = bits(f1val, 1, 1) @[el2_ifu_aln_ctl.scala 281:48] node _T_451 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 281:66] node _T_452 = not(_T_451) @[el2_ifu_aln_ctl.scala 281:53] node _T_453 = mux(_T_449, _T_450, UInt<1>("h00")) @[Mux.scala 27:72] node _T_454 = mux(_T_452, f1val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_455 = or(_T_453, _T_454) @[Mux.scala 27:72] wire _T_456 : UInt @[Mux.scala 27:72] _T_456 <= _T_455 @[Mux.scala 27:72] sf1val <= _T_456 @[el2_ifu_aln_ctl.scala 281:10] node _T_457 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 283:40] node _T_458 = and(fetch_to_f1, _T_457) @[el2_ifu_aln_ctl.scala 283:38] node _T_459 = bits(_T_458, 0, 0) @[el2_ifu_aln_ctl.scala 283:61] node _T_460 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 284:40] node _T_461 = and(shift_f2_f1, _T_460) @[el2_ifu_aln_ctl.scala 284:38] node _T_462 = bits(_T_461, 0, 0) @[el2_ifu_aln_ctl.scala 284:61] node _T_463 = not(fetch_to_f1) @[el2_ifu_aln_ctl.scala 285:26] node _T_464 = not(shift_f2_f1) @[el2_ifu_aln_ctl.scala 285:41] node _T_465 = and(_T_463, _T_464) @[el2_ifu_aln_ctl.scala 285:39] node _T_466 = not(shift_f1_f0) @[el2_ifu_aln_ctl.scala 285:56] node _T_467 = and(_T_465, _T_466) @[el2_ifu_aln_ctl.scala 285:54] node _T_468 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 285:71] node _T_469 = and(_T_467, _T_468) @[el2_ifu_aln_ctl.scala 285:69] node _T_470 = bits(_T_469, 0, 0) @[el2_ifu_aln_ctl.scala 285:92] node _T_471 = mux(_T_459, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_472 = mux(_T_462, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_473 = mux(_T_470, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_474 = or(_T_471, _T_472) @[Mux.scala 27:72] node _T_475 = or(_T_474, _T_473) @[Mux.scala 27:72] wire _T_476 : UInt @[Mux.scala 27:72] _T_476 <= _T_475 @[Mux.scala 27:72] f1val_in <= _T_476 @[el2_ifu_aln_ctl.scala 283:12] node _T_477 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 287:31] node _T_478 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 287:46] node _T_479 = not(shift_2B) @[el2_ifu_aln_ctl.scala 287:52] node _T_480 = not(shift_4B) @[el2_ifu_aln_ctl.scala 287:64] node _T_481 = and(_T_479, _T_480) @[el2_ifu_aln_ctl.scala 287:62] node _T_482 = bits(_T_481, 0, 0) @[el2_ifu_aln_ctl.scala 287:75] node _T_483 = mux(_T_477, _T_478, UInt<1>("h00")) @[Mux.scala 27:72] node _T_484 = mux(_T_482, f0val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_485 = or(_T_483, _T_484) @[Mux.scala 27:72] wire _T_486 : UInt @[Mux.scala 27:72] _T_486 <= _T_485 @[Mux.scala 27:72] f0val <= _T_486 @[el2_ifu_aln_ctl.scala 287:9] node _T_487 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 289:40] node _T_488 = and(fetch_to_f0, _T_487) @[el2_ifu_aln_ctl.scala 289:38] node _T_489 = bits(_T_488, 0, 0) @[el2_ifu_aln_ctl.scala 289:61] node _T_490 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 290:40] node _T_491 = and(shift_f2_f0, _T_490) @[el2_ifu_aln_ctl.scala 290:38] node _T_492 = bits(_T_491, 0, 0) @[el2_ifu_aln_ctl.scala 290:61] node _T_493 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 291:40] node _T_494 = and(shift_f1_f0, _T_493) @[el2_ifu_aln_ctl.scala 291:38] node _T_495 = bits(_T_494, 0, 0) @[el2_ifu_aln_ctl.scala 291:67] node _T_496 = not(fetch_to_f0) @[el2_ifu_aln_ctl.scala 292:26] node _T_497 = not(shift_f2_f0) @[el2_ifu_aln_ctl.scala 292:41] node _T_498 = and(_T_496, _T_497) @[el2_ifu_aln_ctl.scala 292:39] node _T_499 = not(shift_f1_f0) @[el2_ifu_aln_ctl.scala 292:56] node _T_500 = and(_T_498, _T_499) @[el2_ifu_aln_ctl.scala 292:54] node _T_501 = not(io.exu_flush_final) @[el2_ifu_aln_ctl.scala 292:71] node _T_502 = and(_T_500, _T_501) @[el2_ifu_aln_ctl.scala 292:69] node _T_503 = bits(_T_502, 0, 0) @[el2_ifu_aln_ctl.scala 292:92] node _T_504 = mux(_T_489, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_505 = mux(_T_492, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_506 = mux(_T_495, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_507 = mux(_T_503, sf0val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_508 = or(_T_504, _T_505) @[Mux.scala 27:72] node _T_509 = or(_T_508, _T_506) @[Mux.scala 27:72] node _T_510 = or(_T_509, _T_507) @[Mux.scala 27:72] wire _T_511 : UInt @[Mux.scala 27:72] _T_511 <= _T_510 @[Mux.scala 27:72] f0val_in <= _T_511 @[el2_ifu_aln_ctl.scala 289:12] node _T_512 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 294:29] node _T_513 = bits(_T_512, 0, 0) @[el2_ifu_aln_ctl.scala 294:33] node _T_514 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 294:53] node _T_515 = bits(_T_514, 0, 0) @[el2_ifu_aln_ctl.scala 294:57] node _T_516 = bits(q0eff, 31, 16) @[el2_ifu_aln_ctl.scala 294:70] node _T_517 = mux(_T_513, q0eff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_518 = mux(_T_515, _T_516, UInt<1>("h00")) @[Mux.scala 27:72] node _T_519 = or(_T_517, _T_518) @[Mux.scala 27:72] wire _T_520 : UInt<32> @[Mux.scala 27:72] _T_520 <= _T_519 @[Mux.scala 27:72] q0final <= _T_520 @[el2_ifu_aln_ctl.scala 294:11] node _T_521 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 296:29] node _T_522 = bits(_T_521, 0, 0) @[el2_ifu_aln_ctl.scala 296:33] node _T_523 = bits(q1eff, 15, 0) @[el2_ifu_aln_ctl.scala 296:46] node _T_524 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 296:59] node _T_525 = bits(_T_524, 0, 0) @[el2_ifu_aln_ctl.scala 296:63] node _T_526 = bits(q1eff, 31, 16) @[el2_ifu_aln_ctl.scala 296:76] node _T_527 = mux(_T_522, _T_523, UInt<1>("h00")) @[Mux.scala 27:72] node _T_528 = mux(_T_525, _T_526, UInt<1>("h00")) @[Mux.scala 27:72] node _T_529 = or(_T_527, _T_528) @[Mux.scala 27:72] wire _T_530 : UInt<16> @[Mux.scala 27:72] _T_530 <= _T_529 @[Mux.scala 27:72] q1final <= _T_530 @[el2_ifu_aln_ctl.scala 296:11] node _T_531 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 298:30] node _T_532 = bits(_T_531, 0, 0) @[el2_ifu_aln_ctl.scala 298:34] node _T_533 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 298:54] node _T_534 = not(_T_533) @[el2_ifu_aln_ctl.scala 298:48] node _T_535 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 298:65] node _T_536 = and(_T_534, _T_535) @[el2_ifu_aln_ctl.scala 298:58] node _T_537 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 298:82] node _T_538 = cat(_T_537, UInt<1>("h01")) @[Cat.scala 29:58] node _T_539 = mux(_T_532, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_540 = mux(_T_536, _T_538, UInt<1>("h00")) @[Mux.scala 27:72] node _T_541 = or(_T_539, _T_540) @[Mux.scala 27:72] wire _T_542 : UInt<2> @[Mux.scala 27:72] _T_542 <= _T_541 @[Mux.scala 27:72] alignval <= _T_542 @[el2_ifu_aln_ctl.scala 298:12] node _T_543 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 300:35] node _T_544 = bits(_T_543, 0, 0) @[el2_ifu_aln_ctl.scala 300:39] node _T_545 = bits(f0dbecc, 0, 0) @[Bitwise.scala 72:15] node _T_546 = mux(_T_545, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_547 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 300:73] node _T_548 = not(_T_547) @[el2_ifu_aln_ctl.scala 300:67] node _T_549 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 300:84] node _T_550 = and(_T_548, _T_549) @[el2_ifu_aln_ctl.scala 300:77] node _T_551 = bits(_T_550, 0, 0) @[el2_ifu_aln_ctl.scala 300:89] node _T_552 = cat(f1dbecc, f0dbecc) @[Cat.scala 29:58] node _T_553 = mux(_T_544, _T_546, UInt<1>("h00")) @[Mux.scala 27:72] node _T_554 = mux(_T_551, _T_552, UInt<1>("h00")) @[Mux.scala 27:72] node _T_555 = or(_T_553, _T_554) @[Mux.scala 27:72] wire aligndbecc : UInt<2> @[Mux.scala 27:72] aligndbecc <= _T_555 @[Mux.scala 27:72] node _T_556 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:35] node _T_557 = bits(_T_556, 0, 0) @[el2_ifu_aln_ctl.scala 302:45] node _T_558 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:65] node _T_559 = not(_T_558) @[el2_ifu_aln_ctl.scala 302:59] node _T_560 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 302:76] node _T_561 = and(_T_559, _T_560) @[el2_ifu_aln_ctl.scala 302:69] node _T_562 = bits(_T_561, 0, 0) @[el2_ifu_aln_ctl.scala 302:81] node _T_563 = bits(f1brend, 0, 0) @[el2_ifu_aln_ctl.scala 302:100] node _T_564 = bits(f0brend, 0, 0) @[el2_ifu_aln_ctl.scala 302:111] node _T_565 = cat(_T_563, _T_564) @[Cat.scala 29:58] node _T_566 = mux(_T_557, f0brend, UInt<1>("h00")) @[Mux.scala 27:72] node _T_567 = mux(_T_562, _T_565, UInt<1>("h00")) @[Mux.scala 27:72] node _T_568 = or(_T_566, _T_567) @[Mux.scala 27:72] wire alignbrend : UInt<2> @[Mux.scala 27:72] alignbrend <= _T_568 @[Mux.scala 27:72] node _T_569 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:33] node _T_570 = bits(_T_569, 0, 0) @[el2_ifu_aln_ctl.scala 304:43] node _T_571 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:61] node _T_572 = not(_T_571) @[el2_ifu_aln_ctl.scala 304:55] node _T_573 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 304:72] node _T_574 = and(_T_572, _T_573) @[el2_ifu_aln_ctl.scala 304:65] node _T_575 = bits(_T_574, 0, 0) @[el2_ifu_aln_ctl.scala 304:77] node _T_576 = bits(f1pc4, 0, 0) @[el2_ifu_aln_ctl.scala 304:94] node _T_577 = bits(f0pc4, 0, 0) @[el2_ifu_aln_ctl.scala 304:103] node _T_578 = cat(_T_576, _T_577) @[Cat.scala 29:58] node _T_579 = mux(_T_570, f0pc4, UInt<1>("h00")) @[Mux.scala 27:72] node _T_580 = mux(_T_575, _T_578, UInt<1>("h00")) @[Mux.scala 27:72] node _T_581 = or(_T_579, _T_580) @[Mux.scala 27:72] wire alignpc4 : UInt<2> @[Mux.scala 27:72] alignpc4 <= _T_581 @[Mux.scala 27:72] node _T_582 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:33] node _T_583 = bits(_T_582, 0, 0) @[el2_ifu_aln_ctl.scala 306:43] node _T_584 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:61] node _T_585 = not(_T_584) @[el2_ifu_aln_ctl.scala 306:55] node _T_586 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 306:72] node _T_587 = and(_T_585, _T_586) @[el2_ifu_aln_ctl.scala 306:65] node _T_588 = bits(_T_587, 0, 0) @[el2_ifu_aln_ctl.scala 306:77] node _T_589 = bits(f1ret, 0, 0) @[el2_ifu_aln_ctl.scala 306:94] node _T_590 = bits(f0ret, 0, 0) @[el2_ifu_aln_ctl.scala 306:103] node _T_591 = cat(_T_589, _T_590) @[Cat.scala 29:58] node _T_592 = mux(_T_583, f0ret, UInt<1>("h00")) @[Mux.scala 27:72] node _T_593 = mux(_T_588, _T_591, UInt<1>("h00")) @[Mux.scala 27:72] node _T_594 = or(_T_592, _T_593) @[Mux.scala 27:72] wire alignret : UInt<2> @[Mux.scala 27:72] alignret <= _T_594 @[Mux.scala 27:72] node _T_595 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:33] node _T_596 = bits(_T_595, 0, 0) @[el2_ifu_aln_ctl.scala 308:43] node _T_597 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:61] node _T_598 = not(_T_597) @[el2_ifu_aln_ctl.scala 308:55] node _T_599 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 308:72] node _T_600 = and(_T_598, _T_599) @[el2_ifu_aln_ctl.scala 308:65] node _T_601 = bits(_T_600, 0, 0) @[el2_ifu_aln_ctl.scala 308:77] node _T_602 = bits(f1way, 0, 0) @[el2_ifu_aln_ctl.scala 308:94] node _T_603 = bits(f0way, 0, 0) @[el2_ifu_aln_ctl.scala 308:103] node _T_604 = cat(_T_602, _T_603) @[Cat.scala 29:58] node _T_605 = mux(_T_596, f0way, UInt<1>("h00")) @[Mux.scala 27:72] node _T_606 = mux(_T_601, _T_604, UInt<1>("h00")) @[Mux.scala 27:72] node _T_607 = or(_T_605, _T_606) @[Mux.scala 27:72] wire alignway : UInt<2> @[Mux.scala 27:72] alignway <= _T_607 @[Mux.scala 27:72] node _T_608 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:35] node _T_609 = bits(_T_608, 0, 0) @[el2_ifu_aln_ctl.scala 310:45] node _T_610 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:65] node _T_611 = not(_T_610) @[el2_ifu_aln_ctl.scala 310:59] node _T_612 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 310:76] node _T_613 = and(_T_611, _T_612) @[el2_ifu_aln_ctl.scala 310:69] node _T_614 = bits(_T_613, 0, 0) @[el2_ifu_aln_ctl.scala 310:81] node _T_615 = bits(f1hist1, 0, 0) @[el2_ifu_aln_ctl.scala 310:100] node _T_616 = bits(f0hist1, 0, 0) @[el2_ifu_aln_ctl.scala 310:111] node _T_617 = cat(_T_615, _T_616) @[Cat.scala 29:58] node _T_618 = mux(_T_609, f0hist1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_619 = mux(_T_614, _T_617, UInt<1>("h00")) @[Mux.scala 27:72] node _T_620 = or(_T_618, _T_619) @[Mux.scala 27:72] wire alignhist1 : UInt<2> @[Mux.scala 27:72] alignhist1 <= _T_620 @[Mux.scala 27:72] node _T_621 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:35] node _T_622 = bits(_T_621, 0, 0) @[el2_ifu_aln_ctl.scala 312:45] node _T_623 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:65] node _T_624 = not(_T_623) @[el2_ifu_aln_ctl.scala 312:59] node _T_625 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 312:76] node _T_626 = and(_T_624, _T_625) @[el2_ifu_aln_ctl.scala 312:69] node _T_627 = bits(_T_626, 0, 0) @[el2_ifu_aln_ctl.scala 312:81] node _T_628 = bits(f1hist0, 0, 0) @[el2_ifu_aln_ctl.scala 312:100] node _T_629 = bits(f0hist0, 0, 0) @[el2_ifu_aln_ctl.scala 312:111] node _T_630 = cat(_T_628, _T_629) @[Cat.scala 29:58] node _T_631 = mux(_T_622, f0hist0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_632 = mux(_T_627, _T_630, UInt<1>("h00")) @[Mux.scala 27:72] node _T_633 = or(_T_631, _T_632) @[Mux.scala 27:72] wire alignhist0 : UInt<2> @[Mux.scala 27:72] alignhist0 <= _T_633 @[Mux.scala 27:72] node _T_634 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 314:27] node _T_635 = not(_T_634) @[el2_ifu_aln_ctl.scala 314:21] node _T_636 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 314:38] node alignfromf1 = and(_T_635, _T_636) @[el2_ifu_aln_ctl.scala 314:31] wire f1pc : UInt<31> f1pc <= UInt<1>("h00") node _T_637 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:33] node _T_638 = bits(_T_637, 0, 0) @[el2_ifu_aln_ctl.scala 318:43] node _T_639 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:67] node _T_640 = not(_T_639) @[el2_ifu_aln_ctl.scala 318:61] node _T_641 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 318:78] node _T_642 = and(_T_640, _T_641) @[el2_ifu_aln_ctl.scala 318:71] node _T_643 = bits(_T_642, 0, 0) @[el2_ifu_aln_ctl.scala 318:83] node _T_644 = mux(_T_638, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_645 = mux(_T_643, f1pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_646 = or(_T_644, _T_645) @[Mux.scala 27:72] wire secondpc : UInt<31> @[Mux.scala 27:72] secondpc <= _T_646 @[Mux.scala 27:72] io.ifu_i0_pc <= f0pc @[el2_ifu_aln_ctl.scala 320:16] node _T_647 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 324:47] node _T_648 = not(_T_647) @[el2_ifu_aln_ctl.scala 324:41] node _T_649 = and(first4B, _T_648) @[el2_ifu_aln_ctl.scala 324:39] node _T_650 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 324:58] node _T_651 = and(_T_649, _T_650) @[el2_ifu_aln_ctl.scala 324:51] node _T_652 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 324:74] node _T_653 = not(_T_652) @[el2_ifu_aln_ctl.scala 324:64] node _T_654 = and(_T_651, _T_653) @[el2_ifu_aln_ctl.scala 324:62] node _T_655 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 324:91] node _T_656 = not(_T_655) @[el2_ifu_aln_ctl.scala 324:80] node _T_657 = and(_T_654, _T_656) @[el2_ifu_aln_ctl.scala 324:78] node _T_658 = bits(_T_657, 0, 0) @[el2_ifu_aln_ctl.scala 324:96] node _T_659 = mux(_T_658, f1ictype, f0ictype) @[el2_ifu_aln_ctl.scala 324:29] io.ifu_i0_icaf_type <= _T_659 @[el2_ifu_aln_ctl.scala 324:23] node _T_660 = bits(alignicaf, 1, 1) @[el2_ifu_aln_ctl.scala 326:27] node _T_661 = bits(aligndbecc, 1, 1) @[el2_ifu_aln_ctl.scala 326:43] node icaf_eff = or(_T_660, _T_661) @[el2_ifu_aln_ctl.scala 326:31] node _T_662 = and(first4B, icaf_eff) @[el2_ifu_aln_ctl.scala 328:32] node _T_663 = and(_T_662, alignfromf1) @[el2_ifu_aln_ctl.scala 328:43] io.ifu_i0_icaf_f1 <= _T_663 @[el2_ifu_aln_ctl.scala 328:21] node _T_664 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 330:40] node _T_665 = orr(aligndbecc) @[el2_ifu_aln_ctl.scala 330:59] node _T_666 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 330:72] node _T_667 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 330:90] node _T_668 = mux(_T_664, _T_665, UInt<1>("h00")) @[Mux.scala 27:72] node _T_669 = mux(_T_666, _T_667, UInt<1>("h00")) @[Mux.scala 27:72] node _T_670 = or(_T_668, _T_669) @[Mux.scala 27:72] wire _T_671 : UInt<1> @[Mux.scala 27:72] _T_671 <= _T_670 @[Mux.scala 27:72] io.ifu_i0_dbecc <= _T_671 @[el2_ifu_aln_ctl.scala 330:19] node _T_672 = bits(f0pc, 9, 2) @[el2_lib.scala 182:12] node _T_673 = bits(f0pc, 17, 10) @[el2_lib.scala 182:46] node _T_674 = xor(_T_672, _T_673) @[el2_lib.scala 182:42] node _T_675 = bits(f0pc, 25, 18) @[el2_lib.scala 182:80] node firstpc_hash = xor(_T_674, _T_675) @[el2_lib.scala 182:76] node _T_676 = bits(secondpc, 9, 2) @[el2_lib.scala 182:12] node _T_677 = bits(secondpc, 17, 10) @[el2_lib.scala 182:46] node _T_678 = xor(_T_676, _T_677) @[el2_lib.scala 182:42] node _T_679 = bits(secondpc, 25, 18) @[el2_lib.scala 182:80] node secondpc_hash = xor(_T_678, _T_679) @[el2_lib.scala 182:76] node _T_680 = bits(f0pc, 14, 10) @[el2_lib.scala 175:32] node _T_681 = bits(f0pc, 19, 15) @[el2_lib.scala 175:32] node _T_682 = bits(f0pc, 24, 20) @[el2_lib.scala 175:32] wire _T_683 : UInt<5>[3] @[el2_lib.scala 175:24] _T_683[0] <= _T_680 @[el2_lib.scala 175:24] _T_683[1] <= _T_681 @[el2_lib.scala 175:24] _T_683[2] <= _T_682 @[el2_lib.scala 175:24] node _T_684 = xor(_T_683[0], _T_683[1]) @[el2_lib.scala 175:111] node firstbrtag_hash = xor(_T_684, _T_683[2]) @[el2_lib.scala 175:111] node _T_685 = bits(secondpc, 14, 10) @[el2_lib.scala 175:32] node _T_686 = bits(secondpc, 19, 15) @[el2_lib.scala 175:32] node _T_687 = bits(secondpc, 24, 20) @[el2_lib.scala 175:32] wire _T_688 : UInt<5>[3] @[el2_lib.scala 175:24] _T_688[0] <= _T_685 @[el2_lib.scala 175:24] _T_688[1] <= _T_686 @[el2_lib.scala 175:24] _T_688[2] <= _T_687 @[el2_lib.scala 175:24] node _T_689 = xor(_T_688[0], _T_688[1]) @[el2_lib.scala 175:111] node secondbrtag_hash = xor(_T_689, _T_688[2]) @[el2_lib.scala 175:111] node _T_690 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 340:42] node _T_691 = and(first2B, _T_690) @[el2_ifu_aln_ctl.scala 340:30] node _T_692 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 340:70] node _T_693 = and(first4B, _T_692) @[el2_ifu_aln_ctl.scala 340:58] node _T_694 = or(_T_691, _T_693) @[el2_ifu_aln_ctl.scala 340:47] node _T_695 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 340:96] node _T_696 = and(first4B, _T_695) @[el2_ifu_aln_ctl.scala 340:86] node _T_697 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 340:112] node _T_698 = and(_T_696, _T_697) @[el2_ifu_aln_ctl.scala 340:100] node _T_699 = or(_T_694, _T_698) @[el2_ifu_aln_ctl.scala 340:75] io.i0_brp.valid <= _T_699 @[el2_ifu_aln_ctl.scala 340:19] node _T_700 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 342:39] node _T_701 = and(first2B, _T_700) @[el2_ifu_aln_ctl.scala 342:29] node _T_702 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 342:65] node _T_703 = and(first4B, _T_702) @[el2_ifu_aln_ctl.scala 342:55] node _T_704 = or(_T_701, _T_703) @[el2_ifu_aln_ctl.scala 342:44] io.i0_brp.ret <= _T_704 @[el2_ifu_aln_ctl.scala 342:17] node _T_705 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 344:45] node _T_706 = or(first2B, _T_705) @[el2_ifu_aln_ctl.scala 344:33] node _T_707 = bits(_T_706, 0, 0) @[el2_ifu_aln_ctl.scala 344:50] node _T_708 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 344:66] node _T_709 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 344:80] node _T_710 = mux(_T_707, _T_708, _T_709) @[el2_ifu_aln_ctl.scala 344:23] io.i0_brp.way <= _T_710 @[el2_ifu_aln_ctl.scala 344:17] node _T_711 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 345:46] node _T_712 = and(first2B, _T_711) @[el2_ifu_aln_ctl.scala 345:34] node _T_713 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 345:74] node _T_714 = and(first4B, _T_713) @[el2_ifu_aln_ctl.scala 345:62] node _T_715 = or(_T_712, _T_714) @[el2_ifu_aln_ctl.scala 345:51] node _T_716 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 346:26] node _T_717 = and(first2B, _T_716) @[el2_ifu_aln_ctl.scala 346:14] node _T_718 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 346:54] node _T_719 = and(first4B, _T_718) @[el2_ifu_aln_ctl.scala 346:42] node _T_720 = or(_T_717, _T_719) @[el2_ifu_aln_ctl.scala 346:31] node _T_721 = cat(_T_715, _T_720) @[Cat.scala 29:58] io.i0_brp.hist <= _T_721 @[el2_ifu_aln_ctl.scala 345:18] node _T_722 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 348:37] node _T_723 = bits(_T_722, 0, 0) @[el2_ifu_aln_ctl.scala 348:52] node _T_724 = mux(_T_723, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 348:27] io.i0_brp.toffset <= _T_724 @[el2_ifu_aln_ctl.scala 348:21] node _T_725 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 350:35] node _T_726 = bits(_T_725, 0, 0) @[el2_ifu_aln_ctl.scala 350:50] node _T_727 = mux(_T_726, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 350:25] io.i0_brp.prett <= _T_727 @[el2_ifu_aln_ctl.scala 350:19] node _T_728 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 352:51] node _T_729 = and(first4B, _T_728) @[el2_ifu_aln_ctl.scala 352:41] node _T_730 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 352:67] node _T_731 = and(_T_729, _T_730) @[el2_ifu_aln_ctl.scala 352:55] io.i0_brp.br_start_error <= _T_731 @[el2_ifu_aln_ctl.scala 352:29] node _T_732 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 354:57] node _T_733 = or(first2B, _T_732) @[el2_ifu_aln_ctl.scala 354:45] node _T_734 = bits(_T_733, 0, 0) @[el2_ifu_aln_ctl.scala 354:62] node _T_735 = bits(f0pc, 1, 1) @[el2_ifu_aln_ctl.scala 354:77] node _T_736 = bits(secondpc, 1, 1) @[el2_ifu_aln_ctl.scala 354:90] node _T_737 = mux(_T_734, _T_735, _T_736) @[el2_ifu_aln_ctl.scala 354:35] io.i0_brp.bank <= _T_737 @[el2_ifu_aln_ctl.scala 354:29] node _T_738 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 356:39] node _T_739 = and(first2B, _T_738) @[el2_ifu_aln_ctl.scala 356:29] node _T_740 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 356:65] node _T_741 = and(first4B, _T_740) @[el2_ifu_aln_ctl.scala 356:55] node i0_brp_pc4 = or(_T_739, _T_741) @[el2_ifu_aln_ctl.scala 356:44] node _T_742 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 358:42] node _T_743 = and(_T_742, first2B) @[el2_ifu_aln_ctl.scala 358:56] node _T_744 = not(i0_brp_pc4) @[el2_ifu_aln_ctl.scala 358:89] node _T_745 = and(io.i0_brp.valid, _T_744) @[el2_ifu_aln_ctl.scala 358:87] node _T_746 = and(_T_745, first4B) @[el2_ifu_aln_ctl.scala 358:101] node _T_747 = or(_T_743, _T_746) @[el2_ifu_aln_ctl.scala 358:68] io.i0_brp.br_error <= _T_747 @[el2_ifu_aln_ctl.scala 358:22] node _T_748 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 361:50] node _T_749 = or(first2B, _T_748) @[el2_ifu_aln_ctl.scala 361:38] node _T_750 = bits(_T_749, 0, 0) @[el2_ifu_aln_ctl.scala 361:55] node _T_751 = mux(_T_750, firstpc_hash, secondpc_hash) @[el2_ifu_aln_ctl.scala 361:28] io.ifu_i0_bp_index <= _T_751 @[el2_ifu_aln_ctl.scala 361:22] node _T_752 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 363:37] node _T_753 = bits(_T_752, 0, 0) @[el2_ifu_aln_ctl.scala 363:52] node _T_754 = mux(_T_753, f1fghr, f0fghr) @[el2_ifu_aln_ctl.scala 363:27] io.ifu_i0_bp_fghr <= _T_754 @[el2_ifu_aln_ctl.scala 363:21] node _T_755 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 365:49] node _T_756 = or(first2B, _T_755) @[el2_ifu_aln_ctl.scala 365:37] node _T_757 = bits(_T_756, 0, 0) @[el2_ifu_aln_ctl.scala 365:54] node _T_758 = mux(_T_757, firstbrtag_hash, secondbrtag_hash) @[el2_ifu_aln_ctl.scala 365:27] io.ifu_i0_bp_btag <= _T_758 @[el2_ifu_aln_ctl.scala 365:21] node _T_759 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 367:44] reg _T_760 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_759 : @[Reg.scala 28:19] _T_760 <= brdata_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] brdata2 <= _T_760 @[el2_ifu_aln_ctl.scala 367:11] node _T_761 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 368:44] reg _T_762 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_761 : @[Reg.scala 28:19] _T_762 <= brdata_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] brdata1 <= _T_762 @[el2_ifu_aln_ctl.scala 368:11] node _T_763 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 369:44] reg _T_764 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_763 : @[Reg.scala 28:19] _T_764 <= brdata_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] brdata0 <= _T_764 @[el2_ifu_aln_ctl.scala 369:11] node _T_765 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 371:45] reg _T_766 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_765 : @[Reg.scala 28:19] _T_766 <= misc_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] misc2 <= _T_766 @[el2_ifu_aln_ctl.scala 371:9] node _T_767 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 372:45] reg _T_768 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_767 : @[Reg.scala 28:19] _T_768 <= misc_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] misc1 <= _T_768 @[el2_ifu_aln_ctl.scala 372:9] node _T_769 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 373:45] reg _T_770 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_769 : @[Reg.scala 28:19] _T_770 <= misc_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] misc0 <= _T_770 @[el2_ifu_aln_ctl.scala 373:9] node _T_771 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 375:49] reg _T_772 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_771 : @[Reg.scala 28:19] _T_772 <= io.ifu_fetch_data_f @[Reg.scala 28:23] skip @[Reg.scala 28:19] q2 <= _T_772 @[el2_ifu_aln_ctl.scala 375:6] node _T_773 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 376:49] reg _T_774 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_773 : @[Reg.scala 28:19] _T_774 <= io.ifu_fetch_data_f @[Reg.scala 28:23] skip @[Reg.scala 28:19] q1 <= _T_774 @[el2_ifu_aln_ctl.scala 376:6] node _T_775 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 377:49] reg _T_776 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_775 : @[Reg.scala 28:19] _T_776 <= io.ifu_fetch_data_f @[Reg.scala 28:23] skip @[Reg.scala 28:19] q0 <= _T_776 @[el2_ifu_aln_ctl.scala 377:6] node _T_777 = bits(f2_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 379:52] reg _T_778 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_777 : @[Reg.scala 28:19] _T_778 <= io.ifu_fetch_pc @[Reg.scala 28:23] skip @[Reg.scala 28:19] f2pc <= _T_778 @[el2_ifu_aln_ctl.scala 379:8] node _T_779 = bits(f1_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 380:50] reg _T_780 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_779 : @[Reg.scala 28:19] _T_780 <= f1pc_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] f2pc <= _T_780 @[el2_ifu_aln_ctl.scala 380:8] node _T_781 = bits(f0_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 381:50] reg _T_782 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_781 : @[Reg.scala 28:19] _T_782 <= f0pc_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] f2pc <= _T_782 @[el2_ifu_aln_ctl.scala 381:8]