[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~test|test>io_in_region",
    "sources":[
      "~test|test>io_addr"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~test|test>io_in_range",
    "sources":[
      "~test|test>io_addr"
    ]
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"test"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]