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    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data",
    "sources":[
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    ]
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    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
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    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"el2_ifu_mem_ctl"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]