[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~lsu_clkdomain|lsu_clkdomain>io_lsu_busm_clken",
    "sources":[
      "~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_clk_en",
      "~lsu_clkdomain|lsu_clkdomain>io_clk_override",
      "~lsu_clkdomain|lsu_clkdomain>io_lsu_busreq_r",
      "~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_buffer_empty_any"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_obuf_c1_clken",
    "sources":[
      "~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_clk_en",
      "~lsu_clkdomain|lsu_clkdomain>io_clk_override",
      "~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_buffer_pend_any",
      "~lsu_clkdomain|lsu_clkdomain>io_lsu_busreq_r"
    ]
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.transforms.BlackBoxResourceAnno",
    "target":"lsu_clkdomain.gated_latch",
    "resourceId":"/vsrc/gated_latch.sv"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"lsu_clkdomain"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]