;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit dmi_wrapper : module rvjtag_tap : input clock : Clock input reset : AsyncReset output io : {flip trst : AsyncReset, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>, flip rd_status : UInt<2>, flip dmi_stat : UInt<2>, flip idle : UInt<3>, flip version : UInt<4>, flip jtag_id : UInt<31>, flip rd_data : UInt<32>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_en : UInt<1>, rd_en : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<0>} wire nsr : UInt<41> nsr <= UInt<41>("h00") reg sr : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 32:55] sr <= nsr @[rvjtag_tap.scala 32:55] wire dr : UInt<41> dr <= UInt<41>("h00") wire nstate : UInt<4> nstate <= UInt<4>("h00") reg state : UInt, io.tck with : (reset => (io.trst, UInt<4>("h00"))) @[rvjtag_tap.scala 39:57] state <= nstate @[rvjtag_tap.scala 39:57] wire ir : UInt<5> ir <= UInt<5>("h00") wire jtag_reset : UInt<1> jtag_reset <= UInt<1>("h00") wire shift_dr : UInt<1> shift_dr <= UInt<1>("h00") wire pause_dr : UInt<1> pause_dr <= UInt<1>("h00") wire update_dr : UInt<1> update_dr <= UInt<1>("h00") wire capture_dr : UInt<1> capture_dr <= UInt<1>("h00") wire shift_ir : UInt<1> shift_ir <= UInt<1>("h00") wire pause_ir : UInt<1> pause_ir <= UInt<1>("h00") wire update_ir : UInt<1> update_ir <= UInt<1>("h00") wire capture_ir : UInt<1> capture_ir <= UInt<1>("h00") wire dr_en : UInt<2> dr_en <= UInt<1>("h00") wire devid_sel : UInt<1> devid_sel <= UInt<1>("h00") node _T = eq(UInt<4>("h00"), state) @[Conditional.scala 37:30] when _T : @[Conditional.scala 40:58] node _T_1 = mux(io.tms, UInt<4>("h00"), UInt<4>("h01")) @[rvjtag_tap.scala 55:46] nstate <= _T_1 @[rvjtag_tap.scala 55:40] jtag_reset <= UInt<1>("h01") @[rvjtag_tap.scala 56:18] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_2 = eq(UInt<4>("h01"), state) @[Conditional.scala 37:30] when _T_2 : @[Conditional.scala 39:67] node _T_3 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 57:47] nstate <= _T_3 @[rvjtag_tap.scala 57:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4 = eq(UInt<4>("h02"), state) @[Conditional.scala 37:30] when _T_4 : @[Conditional.scala 39:67] node _T_5 = mux(io.tms, UInt<4>("h09"), UInt<4>("h03")) @[rvjtag_tap.scala 58:47] nstate <= _T_5 @[rvjtag_tap.scala 58:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_6 = eq(UInt<4>("h03"), state) @[Conditional.scala 37:30] when _T_6 : @[Conditional.scala 39:67] node _T_7 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 59:47] nstate <= _T_7 @[rvjtag_tap.scala 59:41] capture_dr <= UInt<1>("h01") @[rvjtag_tap.scala 60:18] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_8 = eq(UInt<4>("h04"), state) @[Conditional.scala 37:30] when _T_8 : @[Conditional.scala 39:67] node _T_9 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 61:47] nstate <= _T_9 @[rvjtag_tap.scala 61:41] shift_dr <= UInt<1>("h01") @[rvjtag_tap.scala 62:16] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_10 = eq(UInt<4>("h05"), state) @[Conditional.scala 37:30] when _T_10 : @[Conditional.scala 39:67] node _T_11 = mux(io.tms, UInt<4>("h08"), UInt<4>("h06")) @[rvjtag_tap.scala 63:47] nstate <= _T_11 @[rvjtag_tap.scala 63:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_12 = eq(UInt<4>("h06"), state) @[Conditional.scala 37:30] when _T_12 : @[Conditional.scala 39:67] node _T_13 = mux(io.tms, UInt<4>("h07"), UInt<4>("h06")) @[rvjtag_tap.scala 64:47] nstate <= _T_13 @[rvjtag_tap.scala 64:41] pause_dr <= UInt<1>("h01") @[rvjtag_tap.scala 65:16] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_14 = eq(UInt<4>("h07"), state) @[Conditional.scala 37:30] when _T_14 : @[Conditional.scala 39:67] node _T_15 = mux(io.tms, UInt<4>("h08"), UInt<4>("h04")) @[rvjtag_tap.scala 66:47] nstate <= _T_15 @[rvjtag_tap.scala 66:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_16 = eq(UInt<4>("h08"), state) @[Conditional.scala 37:30] when _T_16 : @[Conditional.scala 39:67] node _T_17 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 67:47] nstate <= _T_17 @[rvjtag_tap.scala 67:41] update_dr <= UInt<1>("h01") @[rvjtag_tap.scala 68:17] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_18 = eq(UInt<4>("h09"), state) @[Conditional.scala 37:30] when _T_18 : @[Conditional.scala 39:67] node _T_19 = mux(io.tms, UInt<4>("h00"), UInt<4>("h0a")) @[rvjtag_tap.scala 69:47] nstate <= _T_19 @[rvjtag_tap.scala 69:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_20 = eq(UInt<4>("h0a"), state) @[Conditional.scala 37:30] when _T_20 : @[Conditional.scala 39:67] node _T_21 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 70:47] nstate <= _T_21 @[rvjtag_tap.scala 70:41] capture_ir <= UInt<1>("h01") @[rvjtag_tap.scala 71:18] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_22 = eq(UInt<4>("h0b"), state) @[Conditional.scala 37:30] when _T_22 : @[Conditional.scala 39:67] node _T_23 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 72:47] nstate <= _T_23 @[rvjtag_tap.scala 72:41] shift_ir <= UInt<1>("h01") @[rvjtag_tap.scala 73:16] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_24 = eq(UInt<4>("h0c"), state) @[Conditional.scala 37:30] when _T_24 : @[Conditional.scala 39:67] node _T_25 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0d")) @[rvjtag_tap.scala 74:47] nstate <= _T_25 @[rvjtag_tap.scala 74:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_26 = eq(UInt<4>("h0d"), state) @[Conditional.scala 37:30] when _T_26 : @[Conditional.scala 39:67] node _T_27 = mux(io.tms, UInt<4>("h0e"), UInt<4>("h0d")) @[rvjtag_tap.scala 75:47] nstate <= _T_27 @[rvjtag_tap.scala 75:41] pause_ir <= UInt<1>("h01") @[rvjtag_tap.scala 76:16] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_28 = eq(UInt<4>("h0e"), state) @[Conditional.scala 37:30] when _T_28 : @[Conditional.scala 39:67] node _T_29 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0b")) @[rvjtag_tap.scala 77:47] nstate <= _T_29 @[rvjtag_tap.scala 77:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_30 = eq(UInt<4>("h0f"), state) @[Conditional.scala 37:30] when _T_30 : @[Conditional.scala 39:67] node _T_31 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 78:47] nstate <= _T_31 @[rvjtag_tap.scala 78:41] update_ir <= UInt<1>("h01") @[rvjtag_tap.scala 79:17] skip @[Conditional.scala 39:67] node _T_32 = or(shift_dr, shift_ir) @[rvjtag_tap.scala 81:28] io.tdoEnable <= _T_32 @[rvjtag_tap.scala 81:16] node _T_33 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:93] node _T_34 = eq(_T_33, UInt<1>("h00")) @[rvjtag_tap.scala 85:98] node _T_35 = bits(_T_34, 0, 0) @[rvjtag_tap.scala 85:106] node _T_36 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:123] node _T_37 = mux(_T_35, UInt<5>("h01f"), _T_36) @[rvjtag_tap.scala 85:89] node _T_38 = mux(update_ir, _T_37, UInt<1>("h00")) @[rvjtag_tap.scala 85:75] node _T_39 = mux(jtag_reset, UInt<1>("h01"), _T_38) @[rvjtag_tap.scala 85:56] reg _T_40 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h01"))) @[rvjtag_tap.scala 85:52] _T_40 <= _T_39 @[rvjtag_tap.scala 85:52] ir <= _T_40 @[rvjtag_tap.scala 85:6] node _T_41 = eq(ir, UInt<5>("h01")) @[rvjtag_tap.scala 86:18] devid_sel <= _T_41 @[rvjtag_tap.scala 86:13] node _T_42 = eq(ir, UInt<5>("h011")) @[rvjtag_tap.scala 87:22] node _T_43 = eq(ir, UInt<5>("h010")) @[rvjtag_tap.scala 87:32] node _T_44 = cat(_T_42, _T_43) @[Cat.scala 29:58] dr_en <= _T_44 @[rvjtag_tap.scala 87:13] node _T_45 = eq(shift_dr, UInt<1>("h01")) @[rvjtag_tap.scala 92:16] when _T_45 : @[rvjtag_tap.scala 92:23] node _T_46 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 93:15] node _T_47 = eq(_T_46, UInt<1>("h01")) @[rvjtag_tap.scala 93:18] when _T_47 : @[rvjtag_tap.scala 93:28] node _T_48 = bits(sr, 40, 1) @[rvjtag_tap.scala 93:49] node _T_49 = cat(io.tdi, _T_48) @[Cat.scala 29:58] nsr <= _T_49 @[rvjtag_tap.scala 93:33] skip @[rvjtag_tap.scala 93:28] else : @[rvjtag_tap.scala 94:54] node _T_50 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 94:22] node _T_51 = eq(_T_50, UInt<1>("h01")) @[rvjtag_tap.scala 94:25] node _T_52 = eq(devid_sel, UInt<1>("h01")) @[rvjtag_tap.scala 94:44] node _T_53 = or(_T_51, _T_52) @[rvjtag_tap.scala 94:32] when _T_53 : @[rvjtag_tap.scala 94:54] node _T_54 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] node _T_55 = bits(sr, 31, 1) @[rvjtag_tap.scala 94:106] node _T_56 = cat(_T_54, io.tdi) @[Cat.scala 29:58] node _T_57 = cat(_T_56, _T_55) @[Cat.scala 29:58] nsr <= _T_57 @[rvjtag_tap.scala 94:59] skip @[rvjtag_tap.scala 94:54] else : @[rvjtag_tap.scala 95:17] node _T_58 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12] node _T_59 = cat(_T_58, io.tdi) @[Cat.scala 29:58] nsr <= _T_59 @[rvjtag_tap.scala 95:22] skip @[rvjtag_tap.scala 95:17] skip @[rvjtag_tap.scala 92:23] else : @[rvjtag_tap.scala 97:33] node _T_60 = eq(capture_dr, UInt<1>("h01")) @[rvjtag_tap.scala 97:26] when _T_60 : @[rvjtag_tap.scala 97:33] node _T_61 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 98:17] when _T_61 : @[rvjtag_tap.scala 98:21] node _T_62 = mux(UInt<1>("h00"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12] node _T_63 = cat(UInt<6>("h07"), io.version) @[Cat.scala 29:58] node _T_64 = cat(_T_62, io.idle) @[Cat.scala 29:58] node _T_65 = cat(_T_64, io.dmi_stat) @[Cat.scala 29:58] node _T_66 = cat(_T_65, _T_63) @[Cat.scala 29:58] nsr <= _T_66 @[rvjtag_tap.scala 98:26] skip @[rvjtag_tap.scala 98:21] else : @[rvjtag_tap.scala 99:28] node _T_67 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 99:24] when _T_67 : @[rvjtag_tap.scala 99:28] node _T_68 = mux(UInt<1>("h00"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] node _T_69 = cat(_T_68, io.rd_data) @[Cat.scala 29:58] node _T_70 = cat(_T_69, io.rd_status) @[Cat.scala 29:58] nsr <= _T_70 @[rvjtag_tap.scala 99:33] skip @[rvjtag_tap.scala 99:28] else : @[rvjtag_tap.scala 100:29] when devid_sel : @[rvjtag_tap.scala 100:29] node _T_71 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] node _T_72 = cat(_T_71, io.jtag_id) @[Cat.scala 29:58] node _T_73 = cat(_T_72, UInt<1>("h01")) @[Cat.scala 29:58] nsr <= _T_73 @[rvjtag_tap.scala 100:34] skip @[rvjtag_tap.scala 100:29] skip @[rvjtag_tap.scala 97:33] else : @[rvjtag_tap.scala 102:30] node _T_74 = eq(shift_ir, UInt<1>("h01")) @[rvjtag_tap.scala 102:23] when _T_74 : @[rvjtag_tap.scala 102:30] node _T_75 = mux(UInt<1>("h00"), UInt<36>("h0fffffffff"), UInt<36>("h00")) @[Bitwise.scala 72:12] node _T_76 = bits(sr, 4, 1) @[rvjtag_tap.scala 102:78] node _T_77 = cat(_T_75, io.tdi) @[Cat.scala 29:58] node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58] nsr <= _T_78 @[rvjtag_tap.scala 102:35] skip @[rvjtag_tap.scala 102:30] else : @[rvjtag_tap.scala 103:32] node _T_79 = eq(capture_ir, UInt<1>("h01")) @[rvjtag_tap.scala 103:25] when _T_79 : @[rvjtag_tap.scala 103:32] node _T_80 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12] node _T_81 = cat(_T_80, UInt<1>("h01")) @[Cat.scala 29:58] nsr <= _T_81 @[rvjtag_tap.scala 103:37] skip @[rvjtag_tap.scala 103:32] node _T_82 = bits(sr, 0, 0) @[rvjtag_tap.scala 106:40] reg _T_83 : UInt<1>, io.tck with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 106:37] _T_83 <= _T_82 @[rvjtag_tap.scala 106:37] io.tdo <= _T_83 @[rvjtag_tap.scala 106:28] node _T_84 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 108:89] node _T_85 = bits(_T_84, 0, 0) @[rvjtag_tap.scala 108:99] node _T_86 = and(update_dr, _T_85) @[rvjtag_tap.scala 108:82] node _T_87 = bits(sr, 17, 17) @[rvjtag_tap.scala 108:104] node _T_88 = mux(_T_86, _T_87, UInt<1>("h00")) @[rvjtag_tap.scala 108:71] reg _T_89 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 108:67] _T_89 <= _T_88 @[rvjtag_tap.scala 108:67] io.dmi_hard_reset <= _T_89 @[rvjtag_tap.scala 108:57] node _T_90 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 109:84] node _T_91 = bits(_T_90, 0, 0) @[rvjtag_tap.scala 109:94] node _T_92 = and(update_dr, _T_91) @[rvjtag_tap.scala 109:77] node _T_93 = bits(sr, 16, 16) @[rvjtag_tap.scala 109:99] node _T_94 = mux(_T_92, _T_93, UInt<1>("h00")) @[rvjtag_tap.scala 109:66] reg _T_95 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 109:62] _T_95 <= _T_94 @[rvjtag_tap.scala 109:62] io.dmi_reset <= _T_95 @[rvjtag_tap.scala 109:52] node _T_96 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 111:74] node _T_97 = bits(_T_96, 0, 0) @[rvjtag_tap.scala 111:84] node _T_98 = and(update_dr, _T_97) @[rvjtag_tap.scala 111:67] node _T_99 = bits(dr, 40, 2) @[rvjtag_tap.scala 111:96] node _T_100 = cat(_T_99, UInt<2>("h00")) @[Cat.scala 29:58] node _T_101 = mux(_T_98, sr, _T_100) @[rvjtag_tap.scala 111:56] reg _T_102 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 111:52] _T_102 <= _T_101 @[rvjtag_tap.scala 111:52] dr <= _T_102 @[rvjtag_tap.scala 111:42] node _T_103 = bits(dr, 0, 0) @[rvjtag_tap.scala 113:19] io.rd_en <= _T_103 @[rvjtag_tap.scala 113:14] node _T_104 = bits(dr, 1, 1) @[rvjtag_tap.scala 114:19] io.wr_en <= _T_104 @[rvjtag_tap.scala 114:14] node _T_105 = bits(dr, 33, 2) @[rvjtag_tap.scala 115:19] io.wr_data <= _T_105 @[rvjtag_tap.scala 115:14] node _T_106 = bits(dr, 40, 34) @[rvjtag_tap.scala 116:19] io.wr_addr <= _T_106 @[rvjtag_tap.scala 116:14] module dmi_jtag_to_core_sync : input clock : Clock input reset : AsyncReset output io : {flip rd_en : UInt<1>, flip wr_en : UInt<1>, reg_en : UInt<1>, reg_wr_en : UInt<1>} wire c_rd_en : UInt<1> c_rd_en <= UInt<1>("h00") wire c_wr_en : UInt<1> c_wr_en <= UInt<1>("h00") wire rden : UInt<3> rden <= UInt<3>("h00") wire wren : UInt<3> wren <= UInt<3>("h00") node _T = bits(rden, 1, 0) @[dmi_jtag_to_core_sync.scala 26:27] node _T_1 = cat(_T, io.rd_en) @[Cat.scala 29:58] reg _T_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 26:18] _T_2 <= _T_1 @[dmi_jtag_to_core_sync.scala 26:18] rden <= _T_2 @[dmi_jtag_to_core_sync.scala 26:8] node _T_3 = bits(wren, 1, 0) @[dmi_jtag_to_core_sync.scala 27:27] node _T_4 = cat(_T_3, io.wr_en) @[Cat.scala 29:58] reg _T_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 27:18] _T_5 <= _T_4 @[dmi_jtag_to_core_sync.scala 27:18] wren <= _T_5 @[dmi_jtag_to_core_sync.scala 27:8] node _T_6 = bits(rden, 1, 1) @[dmi_jtag_to_core_sync.scala 28:18] node _T_7 = bits(rden, 2, 2) @[dmi_jtag_to_core_sync.scala 28:29] node _T_8 = eq(_T_7, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 28:24] node _T_9 = and(_T_6, _T_8) @[dmi_jtag_to_core_sync.scala 28:22] c_rd_en <= _T_9 @[dmi_jtag_to_core_sync.scala 28:11] node _T_10 = bits(wren, 1, 1) @[dmi_jtag_to_core_sync.scala 29:18] node _T_11 = bits(wren, 2, 2) @[dmi_jtag_to_core_sync.scala 29:29] node _T_12 = eq(_T_11, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 29:24] node _T_13 = and(_T_10, _T_12) @[dmi_jtag_to_core_sync.scala 29:22] c_wr_en <= _T_13 @[dmi_jtag_to_core_sync.scala 29:11] node _T_14 = or(c_wr_en, c_rd_en) @[dmi_jtag_to_core_sync.scala 31:28] io.reg_en <= _T_14 @[dmi_jtag_to_core_sync.scala 31:17] io.reg_wr_en <= c_wr_en @[dmi_jtag_to_core_sync.scala 32:17] module dmi_wrapper : input clock : Clock input reset : AsyncReset output io : {flip trst_n : AsyncReset, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, tdo : UInt<1>, tdoEnable : UInt<1>, flip jtag_id : UInt<32>, flip rd_data : UInt<32>, reg_wr_data : UInt<32>, reg_wr_addr : UInt<7>, reg_en : UInt<1>, reg_wr_en : UInt<1>, dmi_hard_reset : UInt<1>} wire rd_en : UInt<1> rd_en <= UInt<1>("h00") wire wr_en : UInt<1> wr_en <= UInt<1>("h00") wire dmireset : UInt<1> dmireset <= UInt<1>("h00") inst i_jtag_tap of rvjtag_tap @[dmi_wrapper.scala 35:27] i_jtag_tap.clock <= clock i_jtag_tap.reset <= reset i_jtag_tap.io.trst <= io.trst_n @[dmi_wrapper.scala 36:27] i_jtag_tap.io.tck <= io.tck @[dmi_wrapper.scala 37:27] i_jtag_tap.io.tms <= io.tms @[dmi_wrapper.scala 38:27] i_jtag_tap.io.tdi <= io.tdi @[dmi_wrapper.scala 39:27] io.tdo <= i_jtag_tap.io.tdo @[dmi_wrapper.scala 40:27] io.tdoEnable <= i_jtag_tap.io.tdoEnable @[dmi_wrapper.scala 41:27] io.reg_wr_data <= i_jtag_tap.io.wr_data @[dmi_wrapper.scala 42:27] io.reg_wr_addr <= i_jtag_tap.io.wr_addr @[dmi_wrapper.scala 43:27] rd_en <= i_jtag_tap.io.rd_en @[dmi_wrapper.scala 44:27] wr_en <= i_jtag_tap.io.wr_en @[dmi_wrapper.scala 45:27] i_jtag_tap.io.rd_data <= io.rd_data @[dmi_wrapper.scala 46:27] i_jtag_tap.io.rd_status <= UInt<2>("h00") @[dmi_wrapper.scala 47:27] i_jtag_tap.io.idle <= UInt<3>("h00") @[dmi_wrapper.scala 48:27] i_jtag_tap.io.dmi_stat <= UInt<2>("h00") @[dmi_wrapper.scala 49:27] i_jtag_tap.io.version <= UInt<4>("h01") @[dmi_wrapper.scala 50:27] i_jtag_tap.io.jtag_id <= io.jtag_id @[dmi_wrapper.scala 51:27] io.dmi_hard_reset <= i_jtag_tap.io.dmi_hard_reset @[dmi_wrapper.scala 52:27] dmireset <= i_jtag_tap.io.dmi_reset @[dmi_wrapper.scala 53:26] inst i_dmi_jtag_to_core_sync of dmi_jtag_to_core_sync @[dmi_wrapper.scala 56:39] i_dmi_jtag_to_core_sync.clock <= clock i_dmi_jtag_to_core_sync.reset <= reset i_dmi_jtag_to_core_sync.io.wr_en <= wr_en @[dmi_wrapper.scala 57:36] i_dmi_jtag_to_core_sync.io.rd_en <= rd_en @[dmi_wrapper.scala 58:36] io.reg_en <= i_dmi_jtag_to_core_sync.io.reg_en @[dmi_wrapper.scala 59:16] io.reg_wr_en <= i_dmi_jtag_to_core_sync.io.reg_wr_en @[dmi_wrapper.scala 60:16]