// SPDX-License-Identifier: Apache-2.0 // Copyright 2020 Western Digital Corporation or it's affiliates. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. `define LOCAL_RAM_TEST_IO \ input logic WE, \ input logic ME, \ input logic CLK, \ input logic TEST1, \ input logic RME, \ input logic [3:0] RM, \ input logic LS, \ input logic DS, \ input logic SD, \ input logic TEST_RNM, \ input logic BC1, \ input logic BC2, \ output logic ROP `define RAM(depth, width) \ module ram_``depth``x``width( \ input logic [$clog2(depth)-1:0] ADR, \ input logic [(width-1):0] D, \ output logic [(width-1):0] Q, \ `LOCAL_RAM_TEST_IO \ ); \ reg [(width-1):0] ram_core [(depth-1):0]; \ `ifdef GTLSIM \ integer i; \ initial begin \ for (i=0; i