[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
    "sources":[
      "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist1_f",
    "sources":[
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f",
    "sources":[
      "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_inst_mask_f",
    "sources":[
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
      "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist0_f",
    "sources":[
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f",
    "sources":[
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_btb_target_f",
    "sources":[
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
      "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_way_f",
    "sources":[
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
      "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
      "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_mp_index",
      "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
      "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_mp_btag",
      "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_mp_pkt_bits_misp",
      "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
    ]
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.transforms.BlackBoxResourceAnno",
    "target":"ifu_bp_ctl.gated_latch",
    "resourceId":"/vsrc/gated_latch.sv"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"ifu_bp_ctl"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]