[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~RVCExpander|RVCExpander>io_out_rs2",
    "sources":[
      "~RVCExpander|RVCExpander>io_in"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~RVCExpander|RVCExpander>io_out_rd",
    "sources":[
      "~RVCExpander|RVCExpander>io_in"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~RVCExpander|RVCExpander>io_out_rs1",
    "sources":[
      "~RVCExpander|RVCExpander>io_in"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~RVCExpander|RVCExpander>io_out_bits",
    "sources":[
      "~RVCExpander|RVCExpander>io_in"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~RVCExpander|RVCExpander>io_rvc",
    "sources":[
      "~RVCExpander|RVCExpander>io_in"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~RVCExpander|RVCExpander>io_out_rs3",
    "sources":[
      "~RVCExpander|RVCExpander>io_in"
    ]
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"RVCExpander"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]