174 lines
6.0 KiB
Makefile
Executable File
174 lines
6.0 KiB
Makefile
Executable File
# SPDX-License-Identifier: Apache-2.0
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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TEST_CFLAGS = -g -O3 -funroll-all-loops
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ABI = -mabi=ilp32 -march=rv32imc
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# Allow snapshot override
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target = default
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snapshot = $(target)
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# Allow tool override
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QUASAR_CONFIG = ${RV_ROOT}/configs/quasar.config
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VCS = vcs
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VERILATOR = verilator
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GCC_PREFIX = riscv64-unknown-elf
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GCC_PREFIX_cpp = /home/users/cores/chipyard/riscv-tools-install/bin/riscv64-unknown-elf#riscv toolchain path
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BUILD_DIR = ${RV_ROOT}/design/snapshots/${snapshot}
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TBDIR = ${RV_ROOT}/testbench
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# Define test name
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TEST = hello_world
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# Define test name
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TEST_DIR = ${TBDIR}/asm
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HEX_DIR = ${TBDIR}/hex
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# provide specific link file
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ifeq (,$(wildcard $(TEST_DIR)/$(TEST).ld))
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LINK = $(TBDIR)/link.ld
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else
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LINK = $(TEST_DIR)/$(TEST).ld
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endif
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ifdef debug
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DEBUG_PLUS = +dumpon
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endif
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VPATH = $(TEST_DIR) $(BUILD_DIR) $(TBDIR)
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TBFILES = $(TBDIR)/tb_top.sv
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defines = $(BUILD_DIR)/common_defines.vh
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defines += $(BUILD_DIR)/pdef.vh
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includes = -I${BUILD_DIR}
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# CFLAGS for verilator generated Makefiles. Without -std=c++11 it
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# complains for `auto` variables
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CFLAGS += "-std=c++11"
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# Optimization for better performance; alternative is nothing for
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# slower runtime (faster compiles) -O2 for faster runtime (slower
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# compiles), or -O for balance.
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VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
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#############Targets#######################################
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all: clean conf sbt_ verilator
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vcs_all: clean conf sbt_ vcs
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############ Model Builds ###############################
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conf:
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BUILD_PATH=${BUILD_DIR} ${RV_ROOT}/configs/quasar.config -target=$(target) $(CONF_PARAMS)
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sbt_:
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cd ${RV_ROOT}/design/ && exec sbt "run"
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python3 ${RV_ROOT}/design/reset_script.py
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rm -rf ${RV_ROOT}/design/quasar_wrapper.v
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mv ${RV_ROOT}/design/quasar_wrapper.sv ${RV_ROOT}/generated_rtl/quasar_wrapper.sv
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vcs-build: ${TBFILES} conf
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$(VCS) -full64 -LDFLAGS '-Wl,--no-as-needed' -assert svaext -sverilog +define+RV_OPENSOURCE \
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+error+500 -debug_access \
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${BUILD_DIR}/common_defines.vh \
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+incdir+$(BUILD_DIR) +libext+.v $(defines) \
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-f ${RV_ROOT}/testbench/flist ${TBFILES} -l ${RV_ROOT}/verif/sim/vcs.log
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verilator-build: ${TBFILES} conf test_tb_top.cpp
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echo '`undef RV_ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
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$(VERILATOR) --cc -CFLAGS ${CFLAGS} $(defines) \
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$(includes) -I${RV_ROOT}/testbench -f ${RV_ROOT}/testbench/flist \
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-Wno-WIDTH -Wno-UNOPTFLAT ${TBFILES} --top-module tb_top \
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-exe test_tb_top.cpp --autoflush $(VERILATOR_DEBUG)
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cp ${RV_ROOT}/testbench/test_tb_top.cpp obj_dir/
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$(MAKE) -j -e -C obj_dir/ -f Vtb_top.mk $(VERILATOR_MAKE_FLAGS)
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############ TEST Simulation ###############################
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vcs: program.hex vcs-build
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./simv $(DEBUG_PLUS) +vcs+lic+wait -l ${RV_ROOT}/verif/sim/vcs.log
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rm -rf program.hex data.hex
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mv csrc simv* vc_hdrs.h ucli.key console.log *.csv ${RV_ROOT}/verif/sim
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mv *.log ${RV_ROOT}/tracer_logs
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lec: sbt_
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rm -rf ${RV_ROOT}/verif/LEC/LEC_RTL
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git clone https://github.com/Lampro-Mellon/LEC-RTL.git -b quasar-1.0 LEC_RTL
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mv LEC_RTL ${RV_ROOT}/verif/LEC
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python3 ${RV_ROOT}/verif/LEC/config.py
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fm_shell -f ${RV_ROOT}/verif/LEC/formality_work/run_me.fms
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@mv *.log ${RV_ROOT}/verif/LEC/formality_work/formality_log
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verilator: program.hex verilator-build
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./obj_dir/Vtb_top
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rm -rf program.hex data.hex
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mv console.log *.csv obj_dir ${RV_ROOT}/verif/sim
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mv *.log ${RV_ROOT}/tracer_logs
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program.hex: $(TEST).o $(LINK)
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@echo Building $(TEST)
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$(GCC_PREFIX_cpp)-ld -m elf32lriscv --discard-none -T$(LINK) -o ${RV_ROOT}/verif/sim/$(TEST).exe ${RV_ROOT}/verif/sim/$(TEST).o
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$(GCC_PREFIX_cpp)-objcopy -O verilog --only-section ".data*" --change-section-lma .data*-0x10000 ${RV_ROOT}/verif/sim/$(TEST).exe ${RV_ROOT}/data.hex
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$(GCC_PREFIX_cpp)-objcopy -O verilog --only-section ".text*" ${RV_ROOT}/verif/sim/$(TEST).exe ${RV_ROOT}/program.hex
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$(GCC_PREFIX_cpp)-objdump -S ${RV_ROOT}/verif/sim/$(TEST).exe > ${RV_ROOT}/verif/sim/$(TEST).dis
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$(GCC_PREFIX_cpp)-nm -f posix -C ${RV_ROOT}/verif/sim/$(TEST).exe > ${RV_ROOT}/verif/sim/$(TEST).tbl
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@echo Completed building $(TEST)
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%.o : %.s conf
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$(GCC_PREFIX_cpp)-cpp -I${BUILD_DIR} $< > ${RV_ROOT}/verif/sim/$(TEST).cpp.s
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$(GCC_PREFIX_cpp)-as -march=rv32gc ${RV_ROOT}/verif/sim/$(TEST).cpp.s -o ${RV_ROOT}/verif/sim/$(TEST).o
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%.o : %.c conf
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$(GCC_PREFIX_cpp)-gcc -I${BUILD_DIR} ${TEST_CFLAGS} ${ABI} -nostdlib -c $< -o ${RV_ROOT}/verif/sim/$(TEST).o
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help:
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@echo Make sure the environment variable RV_ROOT is set.
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@echo Possible targets: vcs verilator help clean conf sbt_ vcs-build verilator-build program.hex
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clean:
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rm -rf ${RV_ROOT}/design/*.v
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rm -rf ${RV_ROOT}/design/*.sv
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rm -rf ${RV_ROOT}/design/*.f
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rm -rf ${RV_ROOT}/design/*.json
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rm -rf ${RV_ROOT}/design/*.fir
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rm -rf ${RV_ROOT}/generated_rtl/*.sv
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rm -rf ${RV_ROOT}/verif/sim/*.log
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rm -rf ${RV_ROOT}/verif/sim/*.s
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rm -rf ${RV_ROOT}/verif/sim/*.hex
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rm -rf ${RV_ROOT}/verif/sim/*.dis
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rm -rf ${RV_ROOT}/verif/sim/*.tbl
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rm -rf ${RV_ROOT}/verif/sim/vcs*
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rm -rf ${RV_ROOT}/verif/sim/simv*
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rm -rf ${RV_ROOT}/design/src/main/scala/lib/param.scala
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rm -rf ${RV_ROOT}/design/snapshots
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rm -rf ${RV_ROOT}/verif/sim/quasar*
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rm -rf ${RV_ROOT}/verif/sim/*.exe
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rm -rf ${RV_ROOT}/verif/sim/obj*
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rm -rf ${RV_ROOT}/verif/sim/*.o
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rm -rf ${RV_ROOT}/verif/sim/ucli.key
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rm -rf ${RV_ROOT}/verif/sim/vc_hdrs.h
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rm -rf ${RV_ROOT}/verif/sim/csrc
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rm -rf ${RV_ROOT}/verif/sim/*.csv
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rm -rf ${RV_ROOT}/verif/sim/work
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rm -rf ${RV_ROOT}/verif/sim/*.dump
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rm -rf ${RV_ROOT}/verif/sim/*.fsdb
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rm -rf *.log *.s *.hex *.dis *.tbl vcs* simv* quasar* *.exe obj* *.o ucli.key vc_hdrs.h csrc *.csv work *.dump *.fsdb
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