67 lines
2.0 KiB
Verilog
67 lines
2.0 KiB
Verilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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// Function: Basic RAM model with separate read/write ports and byte-wise write enable
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// Comments:
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//
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//********************************************************************************
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module dpram64
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#(parameter SIZE=0,
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parameter mem_clear = 0,
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parameter memfile = "")
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(input wire clk,
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input wire [7:0] we,
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input wire [63:0] din,
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input wire [$clog2(SIZE)-1:0] waddr,
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input wire [$clog2(SIZE)-1:0] raddr,
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output reg [63:0] dout);
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localparam AW = $clog2(SIZE);
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reg [63:0] mem [0:SIZE/8-1] /* verilator public */;
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integer i;
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wire [AW-4:0] wadd = waddr[AW-1:3];
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always @(posedge clk) begin
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if (we[0]) mem[wadd][ 7: 0] <= din[ 7: 0];
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if (we[1]) mem[wadd][15: 8] <= din[15: 8];
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if (we[2]) mem[wadd][23:16] <= din[23:16];
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if (we[3]) mem[wadd][31:24] <= din[31:24];
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if (we[4]) mem[wadd][39:32] <= din[39:32];
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if (we[5]) mem[wadd][47:40] <= din[47:40];
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if (we[6]) mem[wadd][55:48] <= din[55:48];
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if (we[7]) mem[wadd][63:56] <= din[63:56];
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dout <= mem[raddr[AW-1:3]];
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end
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generate
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initial begin
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if (mem_clear)
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for (i=0;i<SIZE;i=i+1)
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mem[i] = 64'd0;
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if(|memfile) begin
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$display("Preloading %m from %s", memfile);
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$readmemh(memfile, mem);
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end
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end
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endgenerate
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endmodule
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