14 lines
481 B
Verilog
14 lines
481 B
Verilog
module aes(
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input clock,
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input reset,
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input [7:0] io_byteIn,
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output [7:0] io_byteOut
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);
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wire [10:0] _T = {io_byteIn, 3'h0}; // @[cipher.scala 16:16]
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wire [3:0] _T_2 = 4'h8 - 4'h3; // @[cipher.scala 16:39]
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wire [7:0] _T_3 = io_byteIn >> _T_2; // @[cipher.scala 16:31]
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wire [10:0] _GEN_0 = {{3'd0}, _T_3}; // @[cipher.scala 16:26]
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wire [10:0] z = _T | _GEN_0; // @[cipher.scala 16:26]
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assign io_byteOut = z[7:0]; // @[cipher.scala 21:14]
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endmodule
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