13454 lines
951 KiB
Plaintext
13454 lines
951 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_mem_ctl :
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module el2_ifu_mem_ctl :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, flip ifu_axi_arready : UInt<1>, flip ifu_axi_rvalid : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, flip ifu_fetch_val : UInt<2>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_miss_state_idle : UInt<1>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, ifu_axi_rready : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, iccm_rd_ecc_single_err : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, ic_error_start : UInt<1>, ifu_async_error_start : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>}
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io.ifu_axi_wvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 129:21]
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io.ifu_axi_wdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 130:20]
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io.ifu_axi_awqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 131:20]
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io.ifu_axi_awaddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 132:21]
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io.ifu_axi_awprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 133:21]
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io.ifu_axi_awlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 134:20]
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io.ifu_axi_arlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 135:21]
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io.ifu_axi_awregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 136:23]
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io.ifu_axi_awid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 137:19]
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io.ifu_axi_awvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 138:22]
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io.ifu_axi_wstrb <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 139:20]
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io.ifu_axi_awcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 140:22]
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io.ifu_axi_arqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 141:20]
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io.ifu_axi_awlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 142:21]
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io.ifu_axi_bready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 143:21]
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io.ifu_axi_arlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 144:20]
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io.ifu_axi_awsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 145:21]
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io.ifu_axi_arprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 146:21]
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io.ifu_axi_awburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 147:22]
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io.ifu_axi_wlast <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 148:20]
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wire iccm_single_ecc_error : UInt<2>
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iccm_single_ecc_error <= UInt<1>("h00")
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wire ifc_fetch_req_f : UInt<1>
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ifc_fetch_req_f <= UInt<1>("h00")
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wire miss_pending : UInt<1>
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miss_pending <= UInt<1>("h00")
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wire scnd_miss_req : UInt<1>
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scnd_miss_req <= UInt<1>("h00")
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wire dma_iccm_req_f : UInt<1>
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dma_iccm_req_f <= UInt<1>("h00")
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wire iccm_correct_ecc : UInt<1>
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iccm_correct_ecc <= UInt<1>("h00")
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wire perr_state : UInt<3>
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perr_state <= UInt<1>("h00")
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wire err_stop_state : UInt<2>
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err_stop_state <= UInt<1>("h00")
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wire err_stop_fetch : UInt<1>
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err_stop_fetch <= UInt<1>("h00")
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wire miss_state : UInt<3>
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miss_state <= UInt<1>("h00")
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wire miss_nxtstate : UInt<3>
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miss_nxtstate <= UInt<1>("h00")
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wire miss_state_en : UInt<1>
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miss_state_en <= UInt<1>("h00")
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wire ifu_bus_rsp_valid : UInt<1>
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ifu_bus_rsp_valid <= UInt<1>("h00")
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wire bus_ifu_bus_clk_en : UInt<1>
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bus_ifu_bus_clk_en <= UInt<1>("h00")
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wire ifu_bus_rsp_ready : UInt<1>
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ifu_bus_rsp_ready <= UInt<1>("h00")
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wire uncacheable_miss_ff : UInt<1>
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uncacheable_miss_ff <= UInt<1>("h00")
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wire ic_act_miss_f : UInt<1>
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ic_act_miss_f <= UInt<1>("h00")
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wire ic_byp_hit_f : UInt<1>
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ic_byp_hit_f <= UInt<1>("h00")
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wire bus_new_data_beat_count : UInt<3>
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bus_new_data_beat_count <= UInt<1>("h00")
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wire bus_ifu_wr_en_ff : UInt<1>
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bus_ifu_wr_en_ff <= UInt<1>("h00")
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wire last_beat : UInt<1>
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last_beat <= UInt<1>("h00")
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wire last_data_recieved_ff : UInt<1>
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last_data_recieved_ff <= UInt<1>("h00")
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wire stream_eol_f : UInt<1>
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stream_eol_f <= UInt<1>("h00")
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wire ic_miss_under_miss_f : UInt<1>
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ic_miss_under_miss_f <= UInt<1>("h00")
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wire ic_ignore_2nd_miss_f : UInt<1>
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ic_ignore_2nd_miss_f <= UInt<1>("h00")
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reg flush_final_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 180:30]
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flush_final_f <= io.exu_flush_final @[el2_ifu_mem_ctl.scala 180:30]
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node _T = or(io.ifc_fetch_req_bf_raw, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 181:53]
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node _T_1 = or(_T, miss_pending) @[el2_ifu_mem_ctl.scala 181:71]
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node _T_2 = or(_T_1, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 181:86]
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node fetch_bf_f_c1_clken = or(_T_2, scnd_miss_req) @[el2_ifu_mem_ctl.scala 181:107]
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node debug_c1_clken = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 182:42]
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node _T_3 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 185:52]
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node _T_4 = bits(dma_iccm_req_f, 0, 0) @[el2_ifu_mem_ctl.scala 185:78]
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node _T_5 = and(_T_3, _T_4) @[el2_ifu_mem_ctl.scala 185:55]
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io.iccm_dma_sb_error <= _T_5 @[el2_ifu_mem_ctl.scala 185:24]
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node _T_6 = or(io.iccm_rd_ecc_single_err, io.ic_error_start) @[el2_ifu_mem_ctl.scala 186:57]
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io.ifu_async_error_start <= _T_6 @[el2_ifu_mem_ctl.scala 186:28]
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node _T_7 = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 187:54]
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node _T_8 = or(iccm_correct_ecc, _T_7) @[el2_ifu_mem_ctl.scala 187:40]
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node _T_9 = eq(err_stop_state, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 187:90]
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node _T_10 = or(_T_8, _T_9) @[el2_ifu_mem_ctl.scala 187:72]
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node _T_11 = or(_T_10, err_stop_fetch) @[el2_ifu_mem_ctl.scala 187:112]
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node _T_12 = or(_T_11, io.dec_tlu_flush_err_wb) @[el2_ifu_mem_ctl.scala 187:129]
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io.ic_dma_active <= _T_12 @[el2_ifu_mem_ctl.scala 187:20]
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node _T_13 = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 188:44]
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node _T_14 = and(_T_13, ifu_bus_rsp_ready) @[el2_ifu_mem_ctl.scala 188:65]
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node _T_15 = andr(bus_new_data_beat_count) @[el2_ifu_mem_ctl.scala 188:111]
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node _T_16 = and(_T_14, _T_15) @[el2_ifu_mem_ctl.scala 188:85]
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node _T_17 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 189:39]
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node _T_18 = eq(miss_nxtstate, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 189:71]
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node _T_19 = or(_T_17, _T_18) @[el2_ifu_mem_ctl.scala 189:55]
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node _T_20 = dshr(uncacheable_miss_ff, _T_19) @[el2_ifu_mem_ctl.scala 189:26]
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node _T_21 = bits(_T_20, 0, 0) @[el2_ifu_mem_ctl.scala 189:26]
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node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 189:5]
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node _T_23 = and(_T_16, _T_22) @[el2_ifu_mem_ctl.scala 188:116]
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node _T_24 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 189:91]
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node scnd_miss_req_in = and(_T_23, _T_24) @[el2_ifu_mem_ctl.scala 189:89]
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node ifu_bp_hit_taken_q_f = and(io.ifu_bp_hit_taken_f, io.ic_hit_f) @[el2_ifu_mem_ctl.scala 191:52]
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node _T_25 = eq(UInt<3>("h00"), miss_state) @[Conditional.scala 37:30]
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when _T_25 : @[Conditional.scala 40:58]
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node _T_26 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 195:45]
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node _T_27 = and(ic_act_miss_f, _T_26) @[el2_ifu_mem_ctl.scala 195:43]
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node _T_28 = bits(_T_27, 0, 0) @[el2_ifu_mem_ctl.scala 195:66]
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node _T_29 = mux(_T_28, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 195:27]
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miss_nxtstate <= _T_29 @[el2_ifu_mem_ctl.scala 195:21]
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node _T_30 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 196:40]
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node _T_31 = and(ic_act_miss_f, _T_30) @[el2_ifu_mem_ctl.scala 196:38]
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miss_state_en <= _T_31 @[el2_ifu_mem_ctl.scala 196:21]
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skip @[Conditional.scala 40:58]
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else : @[Conditional.scala 39:67]
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node _T_32 = eq(UInt<3>("h01"), miss_state) @[Conditional.scala 37:30]
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when _T_32 : @[Conditional.scala 39:67]
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node _T_33 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 199:113]
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node _T_34 = or(last_data_recieved_ff, _T_33) @[el2_ifu_mem_ctl.scala 199:93]
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node _T_35 = and(ic_byp_hit_f, _T_34) @[el2_ifu_mem_ctl.scala 199:67]
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node _T_36 = and(_T_35, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 199:127]
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node _T_37 = or(io.dec_tlu_force_halt, _T_36) @[el2_ifu_mem_ctl.scala 199:51]
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node _T_38 = bits(_T_37, 0, 0) @[el2_ifu_mem_ctl.scala 199:152]
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node _T_39 = eq(last_data_recieved_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 200:30]
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node _T_40 = and(ic_byp_hit_f, _T_39) @[el2_ifu_mem_ctl.scala 200:27]
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node _T_41 = and(_T_40, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 200:53]
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node _T_42 = bits(_T_41, 0, 0) @[el2_ifu_mem_ctl.scala 200:77]
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node _T_43 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 201:16]
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node _T_44 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 201:32]
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node _T_45 = and(_T_43, _T_44) @[el2_ifu_mem_ctl.scala 201:30]
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node _T_46 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 201:72]
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node _T_47 = and(_T_45, _T_46) @[el2_ifu_mem_ctl.scala 201:52]
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node _T_48 = and(_T_47, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 201:85]
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node _T_49 = bits(_T_48, 0, 0) @[el2_ifu_mem_ctl.scala 201:109]
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node _T_50 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 202:36]
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node _T_51 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 202:51]
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node _T_52 = and(_T_50, _T_51) @[el2_ifu_mem_ctl.scala 202:49]
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node _T_53 = bits(_T_52, 0, 0) @[el2_ifu_mem_ctl.scala 202:73]
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node _T_54 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 203:35]
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node _T_55 = and(ic_byp_hit_f, _T_54) @[el2_ifu_mem_ctl.scala 203:33]
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node _T_56 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 203:76]
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node _T_57 = eq(_T_56, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 203:57]
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node _T_58 = and(_T_55, _T_57) @[el2_ifu_mem_ctl.scala 203:55]
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node _T_59 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 203:91]
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node _T_60 = and(_T_58, _T_59) @[el2_ifu_mem_ctl.scala 203:89]
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node _T_61 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 203:115]
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node _T_62 = and(_T_60, _T_61) @[el2_ifu_mem_ctl.scala 203:113]
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node _T_63 = bits(_T_62, 0, 0) @[el2_ifu_mem_ctl.scala 203:137]
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node _T_64 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:41]
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node _T_65 = and(bus_ifu_wr_en_ff, _T_64) @[el2_ifu_mem_ctl.scala 204:39]
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node _T_66 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 204:82]
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node _T_67 = eq(_T_66, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:63]
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node _T_68 = and(_T_65, _T_67) @[el2_ifu_mem_ctl.scala 204:61]
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node _T_69 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:97]
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node _T_70 = and(_T_68, _T_69) @[el2_ifu_mem_ctl.scala 204:95]
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node _T_71 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:121]
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node _T_72 = and(_T_70, _T_71) @[el2_ifu_mem_ctl.scala 204:119]
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node _T_73 = bits(_T_72, 0, 0) @[el2_ifu_mem_ctl.scala 204:143]
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node _T_74 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 205:22]
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node _T_75 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 205:40]
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node _T_76 = and(_T_74, _T_75) @[el2_ifu_mem_ctl.scala 205:37]
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node _T_77 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 205:81]
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node _T_78 = and(_T_76, _T_77) @[el2_ifu_mem_ctl.scala 205:60]
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node _T_79 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 205:102]
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node _T_80 = and(_T_78, _T_79) @[el2_ifu_mem_ctl.scala 205:100]
|
|
node _T_81 = bits(_T_80, 0, 0) @[el2_ifu_mem_ctl.scala 205:124]
|
|
node _T_82 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 206:44]
|
|
node _T_83 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 206:89]
|
|
node _T_84 = eq(_T_83, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 206:70]
|
|
node _T_85 = and(_T_82, _T_84) @[el2_ifu_mem_ctl.scala 206:68]
|
|
node _T_86 = bits(_T_85, 0, 0) @[el2_ifu_mem_ctl.scala 206:103]
|
|
node _T_87 = mux(_T_86, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 206:22]
|
|
node _T_88 = mux(_T_81, UInt<3>("h00"), _T_87) @[el2_ifu_mem_ctl.scala 205:20]
|
|
node _T_89 = mux(_T_73, UInt<3>("h06"), _T_88) @[el2_ifu_mem_ctl.scala 204:20]
|
|
node _T_90 = mux(_T_63, UInt<3>("h06"), _T_89) @[el2_ifu_mem_ctl.scala 203:18]
|
|
node _T_91 = mux(_T_53, UInt<3>("h00"), _T_90) @[el2_ifu_mem_ctl.scala 202:16]
|
|
node _T_92 = mux(_T_49, UInt<3>("h04"), _T_91) @[el2_ifu_mem_ctl.scala 201:14]
|
|
node _T_93 = mux(_T_42, UInt<3>("h03"), _T_92) @[el2_ifu_mem_ctl.scala 200:12]
|
|
node _T_94 = mux(_T_38, UInt<3>("h00"), _T_93) @[el2_ifu_mem_ctl.scala 199:27]
|
|
miss_nxtstate <= _T_94 @[el2_ifu_mem_ctl.scala 199:21]
|
|
node _T_95 = or(io.dec_tlu_force_halt, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 207:46]
|
|
node _T_96 = or(_T_95, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 207:67]
|
|
node _T_97 = or(_T_96, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 207:82]
|
|
node _T_98 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 207:125]
|
|
node _T_99 = or(_T_97, _T_98) @[el2_ifu_mem_ctl.scala 207:105]
|
|
node _T_100 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 207:160]
|
|
node _T_101 = and(bus_ifu_wr_en_ff, _T_100) @[el2_ifu_mem_ctl.scala 207:158]
|
|
node _T_102 = or(_T_99, _T_101) @[el2_ifu_mem_ctl.scala 207:138]
|
|
miss_state_en <= _T_102 @[el2_ifu_mem_ctl.scala 207:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_103 = eq(UInt<3>("h04"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_103 : @[Conditional.scala 39:67]
|
|
miss_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 210:21]
|
|
node _T_104 = or(io.exu_flush_final, flush_final_f) @[el2_ifu_mem_ctl.scala 211:43]
|
|
node _T_105 = or(_T_104, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 211:59]
|
|
node _T_106 = or(_T_105, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 211:74]
|
|
miss_state_en <= _T_106 @[el2_ifu_mem_ctl.scala 211:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_107 = eq(UInt<3>("h06"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_107 : @[Conditional.scala 39:67]
|
|
node _T_108 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 214:49]
|
|
node _T_109 = or(_T_108, stream_eol_f) @[el2_ifu_mem_ctl.scala 214:72]
|
|
node _T_110 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 214:108]
|
|
node _T_111 = eq(_T_110, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 214:89]
|
|
node _T_112 = and(_T_109, _T_111) @[el2_ifu_mem_ctl.scala 214:87]
|
|
node _T_113 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 214:124]
|
|
node _T_114 = and(_T_112, _T_113) @[el2_ifu_mem_ctl.scala 214:122]
|
|
node _T_115 = bits(_T_114, 0, 0) @[el2_ifu_mem_ctl.scala 214:148]
|
|
node _T_116 = mux(_T_115, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 214:27]
|
|
miss_nxtstate <= _T_116 @[el2_ifu_mem_ctl.scala 214:21]
|
|
node _T_117 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 215:43]
|
|
node _T_118 = or(_T_117, stream_eol_f) @[el2_ifu_mem_ctl.scala 215:67]
|
|
node _T_119 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 215:105]
|
|
node _T_120 = or(_T_118, _T_119) @[el2_ifu_mem_ctl.scala 215:84]
|
|
node _T_121 = or(_T_120, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 215:118]
|
|
miss_state_en <= _T_121 @[el2_ifu_mem_ctl.scala 215:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_122 = eq(UInt<3>("h03"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_122 : @[Conditional.scala 39:67]
|
|
node _T_123 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 218:69]
|
|
node _T_124 = eq(_T_123, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 218:50]
|
|
node _T_125 = and(io.exu_flush_final, _T_124) @[el2_ifu_mem_ctl.scala 218:48]
|
|
node _T_126 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 218:84]
|
|
node _T_127 = and(_T_125, _T_126) @[el2_ifu_mem_ctl.scala 218:82]
|
|
node _T_128 = bits(_T_127, 0, 0) @[el2_ifu_mem_ctl.scala 218:108]
|
|
node _T_129 = mux(_T_128, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 218:27]
|
|
miss_nxtstate <= _T_129 @[el2_ifu_mem_ctl.scala 218:21]
|
|
node _T_130 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 219:63]
|
|
node _T_131 = or(io.exu_flush_final, _T_130) @[el2_ifu_mem_ctl.scala 219:43]
|
|
node _T_132 = or(_T_131, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 219:76]
|
|
miss_state_en <= _T_132 @[el2_ifu_mem_ctl.scala 219:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_133 = eq(UInt<3>("h02"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_133 : @[Conditional.scala 39:67]
|
|
node _T_134 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 222:71]
|
|
node _T_135 = eq(_T_134, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 222:52]
|
|
node _T_136 = and(ic_miss_under_miss_f, _T_135) @[el2_ifu_mem_ctl.scala 222:50]
|
|
node _T_137 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 222:86]
|
|
node _T_138 = and(_T_136, _T_137) @[el2_ifu_mem_ctl.scala 222:84]
|
|
node _T_139 = bits(_T_138, 0, 0) @[el2_ifu_mem_ctl.scala 222:110]
|
|
node _T_140 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 223:56]
|
|
node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 223:37]
|
|
node _T_142 = and(ic_ignore_2nd_miss_f, _T_141) @[el2_ifu_mem_ctl.scala 223:35]
|
|
node _T_143 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 223:71]
|
|
node _T_144 = and(_T_142, _T_143) @[el2_ifu_mem_ctl.scala 223:69]
|
|
node _T_145 = bits(_T_144, 0, 0) @[el2_ifu_mem_ctl.scala 223:95]
|
|
node _T_146 = mux(_T_145, UInt<3>("h07"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 223:12]
|
|
node _T_147 = mux(_T_139, UInt<3>("h05"), _T_146) @[el2_ifu_mem_ctl.scala 222:27]
|
|
miss_nxtstate <= _T_147 @[el2_ifu_mem_ctl.scala 222:21]
|
|
node _T_148 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 224:42]
|
|
node _T_149 = or(_T_148, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 224:55]
|
|
node _T_150 = or(_T_149, ic_ignore_2nd_miss_f) @[el2_ifu_mem_ctl.scala 224:78]
|
|
node _T_151 = or(_T_150, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 224:101]
|
|
miss_state_en <= _T_151 @[el2_ifu_mem_ctl.scala 224:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_152 = eq(UInt<3>("h05"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_152 : @[Conditional.scala 39:67]
|
|
node _T_153 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 228:31]
|
|
node _T_154 = bits(_T_153, 0, 0) @[el2_ifu_mem_ctl.scala 228:44]
|
|
node _T_155 = mux(_T_154, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 228:12]
|
|
node _T_156 = mux(io.exu_flush_final, _T_155, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 227:62]
|
|
node _T_157 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_156) @[el2_ifu_mem_ctl.scala 227:27]
|
|
miss_nxtstate <= _T_157 @[el2_ifu_mem_ctl.scala 227:21]
|
|
node _T_158 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 229:42]
|
|
node _T_159 = or(_T_158, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 229:55]
|
|
node _T_160 = or(_T_159, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 229:76]
|
|
miss_state_en <= _T_160 @[el2_ifu_mem_ctl.scala 229:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_161 = eq(UInt<3>("h07"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_161 : @[Conditional.scala 39:67]
|
|
node _T_162 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 233:31]
|
|
node _T_163 = bits(_T_162, 0, 0) @[el2_ifu_mem_ctl.scala 233:44]
|
|
node _T_164 = mux(_T_163, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 233:12]
|
|
node _T_165 = mux(io.exu_flush_final, _T_164, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 232:62]
|
|
node _T_166 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_165) @[el2_ifu_mem_ctl.scala 232:27]
|
|
miss_nxtstate <= _T_166 @[el2_ifu_mem_ctl.scala 232:21]
|
|
node _T_167 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 234:42]
|
|
node _T_168 = or(_T_167, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 234:55]
|
|
node _T_169 = or(_T_168, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 234:76]
|
|
miss_state_en <= _T_169 @[el2_ifu_mem_ctl.scala 234:21]
|
|
skip @[Conditional.scala 39:67]
|
|
node _T_170 = bits(miss_state_en, 0, 0) @[el2_ifu_mem_ctl.scala 237:61]
|
|
reg _T_171 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_170 : @[Reg.scala 28:19]
|
|
_T_171 <= miss_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
miss_state <= _T_171 @[el2_ifu_mem_ctl.scala 237:14]
|
|
wire crit_byp_hit_f : UInt<1>
|
|
crit_byp_hit_f <= UInt<1>("h00")
|
|
wire way_status_mb_scnd_ff : UInt<1>
|
|
way_status_mb_scnd_ff <= UInt<1>("h00")
|
|
wire way_status : UInt<1>
|
|
way_status <= UInt<1>("h00")
|
|
wire tagv_mb_scnd_ff : UInt<2>
|
|
tagv_mb_scnd_ff <= UInt<1>("h00")
|
|
wire ic_tag_valid : UInt<2>
|
|
ic_tag_valid <= UInt<1>("h00")
|
|
wire uncacheable_miss_scnd_ff : UInt<1>
|
|
uncacheable_miss_scnd_ff <= UInt<1>("h00")
|
|
wire imb_scnd_ff : UInt<31>
|
|
imb_scnd_ff <= UInt<1>("h00")
|
|
wire reset_all_tags : UInt<1>
|
|
reset_all_tags <= UInt<1>("h00")
|
|
wire bus_rd_addr_count : UInt<3>
|
|
bus_rd_addr_count <= UInt<1>("h00")
|
|
wire ifu_bus_rid_ff : UInt<3>
|
|
ifu_bus_rid_ff <= UInt<1>("h00")
|
|
node _T_172 = neq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 248:30]
|
|
miss_pending <= _T_172 @[el2_ifu_mem_ctl.scala 248:16]
|
|
node _T_173 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 249:39]
|
|
node _T_174 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 249:73]
|
|
node _T_175 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 249:95]
|
|
node _T_176 = and(_T_174, _T_175) @[el2_ifu_mem_ctl.scala 249:93]
|
|
node crit_wd_byp_ok_ff = or(_T_173, _T_176) @[el2_ifu_mem_ctl.scala 249:58]
|
|
node _T_177 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 250:57]
|
|
node _T_178 = eq(_T_177, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 250:38]
|
|
node _T_179 = and(miss_pending, _T_178) @[el2_ifu_mem_ctl.scala 250:36]
|
|
node _T_180 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 250:86]
|
|
node _T_181 = and(_T_180, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 250:106]
|
|
node _T_182 = eq(_T_181, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 250:72]
|
|
node _T_183 = and(_T_179, _T_182) @[el2_ifu_mem_ctl.scala 250:70]
|
|
node _T_184 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 251:37]
|
|
node _T_185 = and(_T_184, crit_byp_hit_f) @[el2_ifu_mem_ctl.scala 251:57]
|
|
node _T_186 = eq(_T_185, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 251:23]
|
|
node _T_187 = and(_T_183, _T_186) @[el2_ifu_mem_ctl.scala 250:128]
|
|
node _T_188 = or(_T_187, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 251:77]
|
|
node _T_189 = eq(miss_nxtstate, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 252:36]
|
|
node _T_190 = and(miss_pending, _T_189) @[el2_ifu_mem_ctl.scala 252:19]
|
|
node sel_hold_imb = or(_T_188, _T_190) @[el2_ifu_mem_ctl.scala 251:93]
|
|
node _T_191 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 254:40]
|
|
node _T_192 = or(_T_191, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 254:57]
|
|
node _T_193 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 254:83]
|
|
node sel_hold_imb_scnd = and(_T_192, _T_193) @[el2_ifu_mem_ctl.scala 254:81]
|
|
node _T_194 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 255:46]
|
|
node way_status_mb_scnd_in = mux(_T_194, way_status_mb_scnd_ff, way_status) @[el2_ifu_mem_ctl.scala 255:34]
|
|
node _T_195 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 257:40]
|
|
node _T_196 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:96]
|
|
node _T_197 = bits(_T_196, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_198 = mux(_T_197, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_199 = and(_T_198, ic_tag_valid) @[el2_ifu_mem_ctl.scala 257:113]
|
|
node tagv_mb_scnd_in = mux(_T_195, tagv_mb_scnd_ff, _T_199) @[el2_ifu_mem_ctl.scala 257:28]
|
|
node _T_200 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 258:56]
|
|
node uncacheable_miss_scnd_in = mux(_T_200, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 258:37]
|
|
reg _T_201 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 259:38]
|
|
_T_201 <= uncacheable_miss_scnd_in @[el2_ifu_mem_ctl.scala 259:38]
|
|
uncacheable_miss_scnd_ff <= _T_201 @[el2_ifu_mem_ctl.scala 259:28]
|
|
node _T_202 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 260:43]
|
|
node imb_scnd_in = mux(_T_202, imb_scnd_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 260:24]
|
|
reg _T_203 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 261:25]
|
|
_T_203 <= imb_scnd_in @[el2_ifu_mem_ctl.scala 261:25]
|
|
imb_scnd_ff <= _T_203 @[el2_ifu_mem_ctl.scala 261:15]
|
|
reg _T_204 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 262:35]
|
|
_T_204 <= way_status_mb_scnd_in @[el2_ifu_mem_ctl.scala 262:35]
|
|
way_status_mb_scnd_ff <= _T_204 @[el2_ifu_mem_ctl.scala 262:25]
|
|
reg _T_205 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 263:29]
|
|
_T_205 <= tagv_mb_scnd_in @[el2_ifu_mem_ctl.scala 263:29]
|
|
tagv_mb_scnd_ff <= _T_205 @[el2_ifu_mem_ctl.scala 263:19]
|
|
node _T_206 = bits(bus_ifu_wr_en_ff, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_207 = mux(_T_206, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node ic_wr_addr_bits_hi_3 = and(ifu_bus_rid_ff, _T_207) @[el2_ifu_mem_ctl.scala 266:45]
|
|
wire ifc_iccm_access_f : UInt<1>
|
|
ifc_iccm_access_f <= UInt<1>("h00")
|
|
wire ifc_region_acc_fault_final_f : UInt<1>
|
|
ifc_region_acc_fault_final_f <= UInt<1>("h00")
|
|
node _T_208 = eq(ifc_iccm_access_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 269:48]
|
|
node _T_209 = and(ifc_fetch_req_f, _T_208) @[el2_ifu_mem_ctl.scala 269:46]
|
|
node _T_210 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 269:69]
|
|
node fetch_req_icache_f = and(_T_209, _T_210) @[el2_ifu_mem_ctl.scala 269:67]
|
|
node fetch_req_iccm_f = and(ifc_fetch_req_f, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 270:46]
|
|
node _T_211 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 271:45]
|
|
node _T_212 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 271:73]
|
|
node _T_213 = or(_T_211, _T_212) @[el2_ifu_mem_ctl.scala 271:59]
|
|
node _T_214 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 271:105]
|
|
node _T_215 = or(_T_213, _T_214) @[el2_ifu_mem_ctl.scala 271:91]
|
|
node ic_iccm_hit_f = and(fetch_req_iccm_f, _T_215) @[el2_ifu_mem_ctl.scala 271:41]
|
|
wire stream_hit_f : UInt<1>
|
|
stream_hit_f <= UInt<1>("h00")
|
|
node _T_216 = or(crit_byp_hit_f, stream_hit_f) @[el2_ifu_mem_ctl.scala 273:35]
|
|
node _T_217 = and(_T_216, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 273:52]
|
|
node _T_218 = and(_T_217, miss_pending) @[el2_ifu_mem_ctl.scala 273:73]
|
|
ic_byp_hit_f <= _T_218 @[el2_ifu_mem_ctl.scala 273:16]
|
|
wire sel_mb_addr_ff : UInt<1>
|
|
sel_mb_addr_ff <= UInt<1>("h00")
|
|
wire imb_ff : UInt<31>
|
|
imb_ff <= UInt<1>("h00")
|
|
wire ifu_fetch_addr_int_f : UInt<31>
|
|
ifu_fetch_addr_int_f <= UInt<1>("h00")
|
|
node _T_219 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 277:35]
|
|
node _T_220 = and(_T_219, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 277:39]
|
|
node _T_221 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 277:62]
|
|
node _T_222 = and(_T_220, _T_221) @[el2_ifu_mem_ctl.scala 277:60]
|
|
node _T_223 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 277:81]
|
|
node _T_224 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 277:108]
|
|
node _T_225 = or(_T_223, _T_224) @[el2_ifu_mem_ctl.scala 277:95]
|
|
node _T_226 = and(_T_222, _T_225) @[el2_ifu_mem_ctl.scala 277:78]
|
|
node _T_227 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 277:128]
|
|
node ic_act_hit_f = and(_T_226, _T_227) @[el2_ifu_mem_ctl.scala 277:126]
|
|
node _T_228 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 278:37]
|
|
node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 278:23]
|
|
node _T_230 = or(_T_229, reset_all_tags) @[el2_ifu_mem_ctl.scala 278:41]
|
|
node _T_231 = and(_T_230, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 278:59]
|
|
node _T_232 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 278:82]
|
|
node _T_233 = and(_T_231, _T_232) @[el2_ifu_mem_ctl.scala 278:80]
|
|
node _T_234 = or(_T_233, scnd_miss_req) @[el2_ifu_mem_ctl.scala 278:97]
|
|
node _T_235 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 278:116]
|
|
node _T_236 = and(_T_234, _T_235) @[el2_ifu_mem_ctl.scala 278:114]
|
|
ic_act_miss_f <= _T_236 @[el2_ifu_mem_ctl.scala 278:17]
|
|
node _T_237 = eq(io.ic_rd_hit, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 279:28]
|
|
node _T_238 = or(_T_237, reset_all_tags) @[el2_ifu_mem_ctl.scala 279:42]
|
|
node _T_239 = and(_T_238, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 279:60]
|
|
node _T_240 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 279:94]
|
|
node _T_241 = and(_T_239, _T_240) @[el2_ifu_mem_ctl.scala 279:81]
|
|
node _T_242 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 280:12]
|
|
node _T_243 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 280:63]
|
|
node _T_244 = neq(_T_242, _T_243) @[el2_ifu_mem_ctl.scala 280:39]
|
|
node _T_245 = and(_T_241, _T_244) @[el2_ifu_mem_ctl.scala 279:111]
|
|
node _T_246 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 280:93]
|
|
node _T_247 = and(_T_245, _T_246) @[el2_ifu_mem_ctl.scala 280:91]
|
|
node _T_248 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 280:116]
|
|
node _T_249 = and(_T_247, _T_248) @[el2_ifu_mem_ctl.scala 280:114]
|
|
node _T_250 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 280:134]
|
|
node _T_251 = and(_T_249, _T_250) @[el2_ifu_mem_ctl.scala 280:132]
|
|
ic_miss_under_miss_f <= _T_251 @[el2_ifu_mem_ctl.scala 279:24]
|
|
node _T_252 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 281:42]
|
|
node _T_253 = eq(_T_252, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 281:28]
|
|
node _T_254 = or(_T_253, reset_all_tags) @[el2_ifu_mem_ctl.scala 281:46]
|
|
node _T_255 = and(_T_254, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 281:64]
|
|
node _T_256 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 281:99]
|
|
node _T_257 = and(_T_255, _T_256) @[el2_ifu_mem_ctl.scala 281:85]
|
|
node _T_258 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 282:13]
|
|
node _T_259 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 282:62]
|
|
node _T_260 = eq(_T_258, _T_259) @[el2_ifu_mem_ctl.scala 282:39]
|
|
node _T_261 = or(_T_260, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 282:91]
|
|
node _T_262 = and(_T_257, _T_261) @[el2_ifu_mem_ctl.scala 281:117]
|
|
ic_ignore_2nd_miss_f <= _T_262 @[el2_ifu_mem_ctl.scala 281:24]
|
|
node _T_263 = or(ic_act_hit_f, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 284:31]
|
|
node _T_264 = or(_T_263, ic_iccm_hit_f) @[el2_ifu_mem_ctl.scala 284:46]
|
|
node _T_265 = and(ifc_region_acc_fault_final_f, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 284:94]
|
|
node _T_266 = or(_T_264, _T_265) @[el2_ifu_mem_ctl.scala 284:62]
|
|
io.ic_hit_f <= _T_266 @[el2_ifu_mem_ctl.scala 284:15]
|
|
node _T_267 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 285:47]
|
|
node _T_268 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 285:98]
|
|
node _T_269 = mux(_T_268, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 285:84]
|
|
node uncacheable_miss_in = mux(_T_267, uncacheable_miss_scnd_ff, _T_269) @[el2_ifu_mem_ctl.scala 285:32]
|
|
node _T_270 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 286:34]
|
|
node _T_271 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 286:72]
|
|
node _T_272 = mux(_T_271, imb_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 286:58]
|
|
node imb_in = mux(_T_270, imb_scnd_ff, _T_272) @[el2_ifu_mem_ctl.scala 286:19]
|
|
wire ifu_wr_cumulative_err_data : UInt<1>
|
|
ifu_wr_cumulative_err_data <= UInt<1>("h00")
|
|
node _T_273 = bits(imb_ff, 12, 6) @[el2_ifu_mem_ctl.scala 288:38]
|
|
node _T_274 = bits(imb_scnd_ff, 12, 6) @[el2_ifu_mem_ctl.scala 288:89]
|
|
node _T_275 = eq(_T_273, _T_274) @[el2_ifu_mem_ctl.scala 288:75]
|
|
node _T_276 = and(_T_275, scnd_miss_req) @[el2_ifu_mem_ctl.scala 288:127]
|
|
node _T_277 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 288:145]
|
|
node scnd_miss_index_match = and(_T_276, _T_277) @[el2_ifu_mem_ctl.scala 288:143]
|
|
wire way_status_mb_ff : UInt<1>
|
|
way_status_mb_ff <= UInt<1>("h00")
|
|
wire way_status_rep_new : UInt<1>
|
|
way_status_rep_new <= UInt<1>("h00")
|
|
node _T_278 = eq(scnd_miss_index_match, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 291:47]
|
|
node _T_279 = and(scnd_miss_req, _T_278) @[el2_ifu_mem_ctl.scala 291:45]
|
|
node _T_280 = bits(_T_279, 0, 0) @[el2_ifu_mem_ctl.scala 291:71]
|
|
node _T_281 = and(scnd_miss_req, scnd_miss_index_match) @[el2_ifu_mem_ctl.scala 292:26]
|
|
node _T_282 = bits(_T_281, 0, 0) @[el2_ifu_mem_ctl.scala 292:52]
|
|
node _T_283 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 293:26]
|
|
node _T_284 = mux(_T_283, way_status_mb_ff, way_status) @[el2_ifu_mem_ctl.scala 293:12]
|
|
node _T_285 = mux(_T_282, way_status_rep_new, _T_284) @[el2_ifu_mem_ctl.scala 292:10]
|
|
node way_status_mb_in = mux(_T_280, way_status_mb_scnd_ff, _T_285) @[el2_ifu_mem_ctl.scala 291:29]
|
|
wire replace_way_mb_any : UInt<1>[2] @[el2_ifu_mem_ctl.scala 294:32]
|
|
wire tagv_mb_ff : UInt<2>
|
|
tagv_mb_ff <= UInt<1>("h00")
|
|
node _T_286 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 296:38]
|
|
node _T_287 = bits(scnd_miss_index_match, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_288 = mux(_T_287, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_289 = cat(replace_way_mb_any[1], replace_way_mb_any[0]) @[Cat.scala 29:58]
|
|
node _T_290 = and(_T_288, _T_289) @[el2_ifu_mem_ctl.scala 296:110]
|
|
node _T_291 = or(tagv_mb_scnd_ff, _T_290) @[el2_ifu_mem_ctl.scala 296:62]
|
|
node _T_292 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 297:20]
|
|
node _T_293 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 297:77]
|
|
node _T_294 = bits(_T_293, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_295 = mux(_T_294, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_296 = and(ic_tag_valid, _T_295) @[el2_ifu_mem_ctl.scala 297:53]
|
|
node _T_297 = mux(_T_292, tagv_mb_ff, _T_296) @[el2_ifu_mem_ctl.scala 297:6]
|
|
node tagv_mb_in = mux(_T_286, _T_291, _T_297) @[el2_ifu_mem_ctl.scala 296:23]
|
|
wire scnd_miss_req_q : UInt<1>
|
|
scnd_miss_req_q <= UInt<1>("h00")
|
|
wire reset_ic_ff : UInt<1>
|
|
reset_ic_ff <= UInt<1>("h00")
|
|
node _T_298 = eq(scnd_miss_req_q, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 300:36]
|
|
node _T_299 = and(miss_pending, _T_298) @[el2_ifu_mem_ctl.scala 300:34]
|
|
node _T_300 = or(reset_all_tags, reset_ic_ff) @[el2_ifu_mem_ctl.scala 300:72]
|
|
node reset_ic_in = and(_T_299, _T_300) @[el2_ifu_mem_ctl.scala 300:53]
|
|
reg _T_301 : UInt, clock @[el2_ifu_mem_ctl.scala 301:25]
|
|
_T_301 <= reset_ic_in @[el2_ifu_mem_ctl.scala 301:25]
|
|
reset_ic_ff <= _T_301 @[el2_ifu_mem_ctl.scala 301:15]
|
|
reg fetch_uncacheable_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 302:37]
|
|
fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[el2_ifu_mem_ctl.scala 302:37]
|
|
reg _T_302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 303:34]
|
|
_T_302 <= io.ifc_fetch_addr_bf @[el2_ifu_mem_ctl.scala 303:34]
|
|
ifu_fetch_addr_int_f <= _T_302 @[el2_ifu_mem_ctl.scala 303:24]
|
|
reg _T_303 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 305:33]
|
|
_T_303 <= uncacheable_miss_in @[el2_ifu_mem_ctl.scala 305:33]
|
|
uncacheable_miss_ff <= _T_303 @[el2_ifu_mem_ctl.scala 305:23]
|
|
reg _T_304 : UInt, clock @[el2_ifu_mem_ctl.scala 306:20]
|
|
_T_304 <= imb_in @[el2_ifu_mem_ctl.scala 306:20]
|
|
imb_ff <= _T_304 @[el2_ifu_mem_ctl.scala 306:10]
|
|
wire miss_addr : UInt<26>
|
|
miss_addr <= UInt<1>("h00")
|
|
node _T_305 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 308:26]
|
|
node _T_306 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 308:47]
|
|
node _T_307 = bits(scnd_miss_req_q, 0, 0) @[el2_ifu_mem_ctl.scala 309:25]
|
|
node _T_308 = bits(imb_scnd_ff, 30, 5) @[el2_ifu_mem_ctl.scala 309:44]
|
|
node _T_309 = mux(_T_307, _T_308, miss_addr) @[el2_ifu_mem_ctl.scala 309:8]
|
|
node miss_addr_in = mux(_T_305, _T_306, _T_309) @[el2_ifu_mem_ctl.scala 308:25]
|
|
reg _T_310 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 310:23]
|
|
_T_310 <= miss_addr_in @[el2_ifu_mem_ctl.scala 310:23]
|
|
miss_addr <= _T_310 @[el2_ifu_mem_ctl.scala 310:13]
|
|
reg _T_311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 311:30]
|
|
_T_311 <= way_status_mb_in @[el2_ifu_mem_ctl.scala 311:30]
|
|
way_status_mb_ff <= _T_311 @[el2_ifu_mem_ctl.scala 311:20]
|
|
reg _T_312 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 312:24]
|
|
_T_312 <= tagv_mb_in @[el2_ifu_mem_ctl.scala 312:24]
|
|
tagv_mb_ff <= _T_312 @[el2_ifu_mem_ctl.scala 312:14]
|
|
wire stream_miss_f : UInt<1>
|
|
stream_miss_f <= UInt<1>("h00")
|
|
node _T_313 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 314:68]
|
|
node _T_314 = and(_T_313, flush_final_f) @[el2_ifu_mem_ctl.scala 314:87]
|
|
node _T_315 = eq(_T_314, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 314:55]
|
|
node _T_316 = and(io.ifc_fetch_req_bf, _T_315) @[el2_ifu_mem_ctl.scala 314:53]
|
|
node _T_317 = eq(stream_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 314:106]
|
|
node ifc_fetch_req_qual_bf = and(_T_316, _T_317) @[el2_ifu_mem_ctl.scala 314:104]
|
|
reg ifc_fetch_req_f_raw : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 315:36]
|
|
ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf @[el2_ifu_mem_ctl.scala 315:36]
|
|
node _T_318 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 316:44]
|
|
node _T_319 = and(ifc_fetch_req_f_raw, _T_318) @[el2_ifu_mem_ctl.scala 316:42]
|
|
ifc_fetch_req_f <= _T_319 @[el2_ifu_mem_ctl.scala 316:19]
|
|
reg _T_320 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 317:31]
|
|
_T_320 <= io.ifc_iccm_access_bf @[el2_ifu_mem_ctl.scala 317:31]
|
|
ifc_iccm_access_f <= _T_320 @[el2_ifu_mem_ctl.scala 317:21]
|
|
wire ifc_region_acc_fault_final_bf : UInt<1>
|
|
ifc_region_acc_fault_final_bf <= UInt<1>("h00")
|
|
reg _T_321 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 319:42]
|
|
_T_321 <= ifc_region_acc_fault_final_bf @[el2_ifu_mem_ctl.scala 319:42]
|
|
ifc_region_acc_fault_final_f <= _T_321 @[el2_ifu_mem_ctl.scala 319:32]
|
|
reg ifc_region_acc_fault_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 320:39]
|
|
ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[el2_ifu_mem_ctl.scala 320:39]
|
|
node ifu_ic_req_addr_f = cat(miss_addr, bus_rd_addr_count) @[Cat.scala 29:58]
|
|
node _T_322 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 322:38]
|
|
node _T_323 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 322:68]
|
|
node _T_324 = or(_T_322, _T_323) @[el2_ifu_mem_ctl.scala 322:55]
|
|
node _T_325 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 322:103]
|
|
node _T_326 = eq(_T_325, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 322:84]
|
|
node _T_327 = and(_T_324, _T_326) @[el2_ifu_mem_ctl.scala 322:82]
|
|
node _T_328 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 322:119]
|
|
node _T_329 = or(_T_327, _T_328) @[el2_ifu_mem_ctl.scala 322:117]
|
|
io.ifu_ic_mb_empty <= _T_329 @[el2_ifu_mem_ctl.scala 322:22]
|
|
node _T_330 = eq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 323:40]
|
|
io.ifu_miss_state_idle <= _T_330 @[el2_ifu_mem_ctl.scala 323:26]
|
|
wire write_ic_16_bytes : UInt<1>
|
|
write_ic_16_bytes <= UInt<1>("h00")
|
|
wire reset_tag_valid_for_miss : UInt<1>
|
|
reset_tag_valid_for_miss <= UInt<1>("h00")
|
|
node _T_331 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 326:35]
|
|
node _T_332 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 326:57]
|
|
node _T_333 = and(_T_331, _T_332) @[el2_ifu_mem_ctl.scala 326:55]
|
|
node sel_mb_addr = or(_T_333, reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 326:79]
|
|
node _T_334 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 327:50]
|
|
node _T_335 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 327:68]
|
|
node _T_336 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 327:124]
|
|
node _T_337 = cat(_T_335, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58]
|
|
node _T_338 = cat(_T_337, _T_336) @[Cat.scala 29:58]
|
|
node _T_339 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 328:50]
|
|
node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 328:37]
|
|
node _T_341 = mux(_T_334, _T_338, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_342 = mux(_T_340, ifu_fetch_addr_int_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_343 = or(_T_341, _T_342) @[Mux.scala 27:72]
|
|
wire ifu_ic_rw_int_addr : UInt<31> @[Mux.scala 27:72]
|
|
ifu_ic_rw_int_addr <= _T_343 @[Mux.scala 27:72]
|
|
wire bus_ifu_wr_en_ff_q : UInt<1>
|
|
bus_ifu_wr_en_ff_q <= UInt<1>("h00")
|
|
node _T_344 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 330:41]
|
|
node _T_345 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 330:63]
|
|
node _T_346 = and(_T_344, _T_345) @[el2_ifu_mem_ctl.scala 330:61]
|
|
node _T_347 = and(_T_346, last_beat) @[el2_ifu_mem_ctl.scala 330:84]
|
|
node sel_mb_status_addr = and(_T_347, bus_ifu_wr_en_ff_q) @[el2_ifu_mem_ctl.scala 330:96]
|
|
node _T_348 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 331:62]
|
|
node _T_349 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 331:116]
|
|
node _T_350 = cat(_T_348, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58]
|
|
node _T_351 = cat(_T_350, _T_349) @[Cat.scala 29:58]
|
|
node ifu_status_wr_addr = mux(sel_mb_status_addr, _T_351, ifu_fetch_addr_int_f) @[el2_ifu_mem_ctl.scala 331:31]
|
|
io.ic_rw_addr <= ifu_ic_rw_int_addr @[el2_ifu_mem_ctl.scala 332:17]
|
|
reg _T_352 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 333:51]
|
|
_T_352 <= sel_mb_addr @[el2_ifu_mem_ctl.scala 333:51]
|
|
sel_mb_addr_ff <= _T_352 @[el2_ifu_mem_ctl.scala 333:18]
|
|
wire ifu_bus_rdata_ff : UInt<64>
|
|
ifu_bus_rdata_ff <= UInt<1>("h00")
|
|
wire ic_miss_buff_half : UInt<64>
|
|
ic_miss_buff_half <= UInt<1>("h00")
|
|
wire _T_353 : UInt<1>[35] @[el2_lib.scala 327:18]
|
|
wire _T_354 : UInt<1>[35] @[el2_lib.scala 328:18]
|
|
wire _T_355 : UInt<1>[35] @[el2_lib.scala 329:18]
|
|
wire _T_356 : UInt<1>[31] @[el2_lib.scala 330:18]
|
|
wire _T_357 : UInt<1>[31] @[el2_lib.scala 331:18]
|
|
wire _T_358 : UInt<1>[31] @[el2_lib.scala 332:18]
|
|
wire _T_359 : UInt<1>[7] @[el2_lib.scala 333:18]
|
|
node _T_360 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 340:36]
|
|
_T_353[0] <= _T_360 @[el2_lib.scala 340:30]
|
|
node _T_361 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 341:36]
|
|
_T_354[0] <= _T_361 @[el2_lib.scala 341:30]
|
|
node _T_362 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 340:36]
|
|
_T_353[1] <= _T_362 @[el2_lib.scala 340:30]
|
|
node _T_363 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 342:36]
|
|
_T_355[0] <= _T_363 @[el2_lib.scala 342:30]
|
|
node _T_364 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 341:36]
|
|
_T_354[1] <= _T_364 @[el2_lib.scala 341:30]
|
|
node _T_365 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 342:36]
|
|
_T_355[1] <= _T_365 @[el2_lib.scala 342:30]
|
|
node _T_366 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 340:36]
|
|
_T_353[2] <= _T_366 @[el2_lib.scala 340:30]
|
|
node _T_367 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 341:36]
|
|
_T_354[2] <= _T_367 @[el2_lib.scala 341:30]
|
|
node _T_368 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 342:36]
|
|
_T_355[2] <= _T_368 @[el2_lib.scala 342:30]
|
|
node _T_369 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 340:36]
|
|
_T_353[3] <= _T_369 @[el2_lib.scala 340:30]
|
|
node _T_370 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 343:36]
|
|
_T_356[0] <= _T_370 @[el2_lib.scala 343:30]
|
|
node _T_371 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 341:36]
|
|
_T_354[3] <= _T_371 @[el2_lib.scala 341:30]
|
|
node _T_372 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 343:36]
|
|
_T_356[1] <= _T_372 @[el2_lib.scala 343:30]
|
|
node _T_373 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 340:36]
|
|
_T_353[4] <= _T_373 @[el2_lib.scala 340:30]
|
|
node _T_374 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 341:36]
|
|
_T_354[4] <= _T_374 @[el2_lib.scala 341:30]
|
|
node _T_375 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 343:36]
|
|
_T_356[2] <= _T_375 @[el2_lib.scala 343:30]
|
|
node _T_376 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 342:36]
|
|
_T_355[3] <= _T_376 @[el2_lib.scala 342:30]
|
|
node _T_377 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 343:36]
|
|
_T_356[3] <= _T_377 @[el2_lib.scala 343:30]
|
|
node _T_378 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 340:36]
|
|
_T_353[5] <= _T_378 @[el2_lib.scala 340:30]
|
|
node _T_379 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 342:36]
|
|
_T_355[4] <= _T_379 @[el2_lib.scala 342:30]
|
|
node _T_380 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 343:36]
|
|
_T_356[4] <= _T_380 @[el2_lib.scala 343:30]
|
|
node _T_381 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 341:36]
|
|
_T_354[5] <= _T_381 @[el2_lib.scala 341:30]
|
|
node _T_382 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 342:36]
|
|
_T_355[5] <= _T_382 @[el2_lib.scala 342:30]
|
|
node _T_383 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 343:36]
|
|
_T_356[5] <= _T_383 @[el2_lib.scala 343:30]
|
|
node _T_384 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 340:36]
|
|
_T_353[6] <= _T_384 @[el2_lib.scala 340:30]
|
|
node _T_385 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 341:36]
|
|
_T_354[6] <= _T_385 @[el2_lib.scala 341:30]
|
|
node _T_386 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 342:36]
|
|
_T_355[6] <= _T_386 @[el2_lib.scala 342:30]
|
|
node _T_387 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 343:36]
|
|
_T_356[6] <= _T_387 @[el2_lib.scala 343:30]
|
|
node _T_388 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 340:36]
|
|
_T_353[7] <= _T_388 @[el2_lib.scala 340:30]
|
|
node _T_389 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 344:36]
|
|
_T_357[0] <= _T_389 @[el2_lib.scala 344:30]
|
|
node _T_390 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 341:36]
|
|
_T_354[7] <= _T_390 @[el2_lib.scala 341:30]
|
|
node _T_391 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 344:36]
|
|
_T_357[1] <= _T_391 @[el2_lib.scala 344:30]
|
|
node _T_392 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 340:36]
|
|
_T_353[8] <= _T_392 @[el2_lib.scala 340:30]
|
|
node _T_393 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 341:36]
|
|
_T_354[8] <= _T_393 @[el2_lib.scala 341:30]
|
|
node _T_394 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 344:36]
|
|
_T_357[2] <= _T_394 @[el2_lib.scala 344:30]
|
|
node _T_395 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 342:36]
|
|
_T_355[7] <= _T_395 @[el2_lib.scala 342:30]
|
|
node _T_396 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 344:36]
|
|
_T_357[3] <= _T_396 @[el2_lib.scala 344:30]
|
|
node _T_397 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 340:36]
|
|
_T_353[9] <= _T_397 @[el2_lib.scala 340:30]
|
|
node _T_398 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 342:36]
|
|
_T_355[8] <= _T_398 @[el2_lib.scala 342:30]
|
|
node _T_399 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 344:36]
|
|
_T_357[4] <= _T_399 @[el2_lib.scala 344:30]
|
|
node _T_400 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 341:36]
|
|
_T_354[9] <= _T_400 @[el2_lib.scala 341:30]
|
|
node _T_401 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 342:36]
|
|
_T_355[9] <= _T_401 @[el2_lib.scala 342:30]
|
|
node _T_402 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 344:36]
|
|
_T_357[5] <= _T_402 @[el2_lib.scala 344:30]
|
|
node _T_403 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 340:36]
|
|
_T_353[10] <= _T_403 @[el2_lib.scala 340:30]
|
|
node _T_404 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 341:36]
|
|
_T_354[10] <= _T_404 @[el2_lib.scala 341:30]
|
|
node _T_405 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 342:36]
|
|
_T_355[10] <= _T_405 @[el2_lib.scala 342:30]
|
|
node _T_406 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 344:36]
|
|
_T_357[6] <= _T_406 @[el2_lib.scala 344:30]
|
|
node _T_407 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 343:36]
|
|
_T_356[7] <= _T_407 @[el2_lib.scala 343:30]
|
|
node _T_408 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 344:36]
|
|
_T_357[7] <= _T_408 @[el2_lib.scala 344:30]
|
|
node _T_409 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 340:36]
|
|
_T_353[11] <= _T_409 @[el2_lib.scala 340:30]
|
|
node _T_410 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 343:36]
|
|
_T_356[8] <= _T_410 @[el2_lib.scala 343:30]
|
|
node _T_411 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 344:36]
|
|
_T_357[8] <= _T_411 @[el2_lib.scala 344:30]
|
|
node _T_412 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 341:36]
|
|
_T_354[11] <= _T_412 @[el2_lib.scala 341:30]
|
|
node _T_413 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 343:36]
|
|
_T_356[9] <= _T_413 @[el2_lib.scala 343:30]
|
|
node _T_414 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 344:36]
|
|
_T_357[9] <= _T_414 @[el2_lib.scala 344:30]
|
|
node _T_415 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 340:36]
|
|
_T_353[12] <= _T_415 @[el2_lib.scala 340:30]
|
|
node _T_416 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 341:36]
|
|
_T_354[12] <= _T_416 @[el2_lib.scala 341:30]
|
|
node _T_417 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 343:36]
|
|
_T_356[10] <= _T_417 @[el2_lib.scala 343:30]
|
|
node _T_418 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 344:36]
|
|
_T_357[10] <= _T_418 @[el2_lib.scala 344:30]
|
|
node _T_419 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 342:36]
|
|
_T_355[11] <= _T_419 @[el2_lib.scala 342:30]
|
|
node _T_420 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 343:36]
|
|
_T_356[11] <= _T_420 @[el2_lib.scala 343:30]
|
|
node _T_421 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 344:36]
|
|
_T_357[11] <= _T_421 @[el2_lib.scala 344:30]
|
|
node _T_422 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 340:36]
|
|
_T_353[13] <= _T_422 @[el2_lib.scala 340:30]
|
|
node _T_423 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 342:36]
|
|
_T_355[12] <= _T_423 @[el2_lib.scala 342:30]
|
|
node _T_424 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 343:36]
|
|
_T_356[12] <= _T_424 @[el2_lib.scala 343:30]
|
|
node _T_425 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 344:36]
|
|
_T_357[12] <= _T_425 @[el2_lib.scala 344:30]
|
|
node _T_426 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 341:36]
|
|
_T_354[13] <= _T_426 @[el2_lib.scala 341:30]
|
|
node _T_427 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 342:36]
|
|
_T_355[13] <= _T_427 @[el2_lib.scala 342:30]
|
|
node _T_428 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 343:36]
|
|
_T_356[13] <= _T_428 @[el2_lib.scala 343:30]
|
|
node _T_429 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 344:36]
|
|
_T_357[13] <= _T_429 @[el2_lib.scala 344:30]
|
|
node _T_430 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 340:36]
|
|
_T_353[14] <= _T_430 @[el2_lib.scala 340:30]
|
|
node _T_431 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 341:36]
|
|
_T_354[14] <= _T_431 @[el2_lib.scala 341:30]
|
|
node _T_432 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 342:36]
|
|
_T_355[14] <= _T_432 @[el2_lib.scala 342:30]
|
|
node _T_433 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 343:36]
|
|
_T_356[14] <= _T_433 @[el2_lib.scala 343:30]
|
|
node _T_434 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 344:36]
|
|
_T_357[14] <= _T_434 @[el2_lib.scala 344:30]
|
|
node _T_435 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 340:36]
|
|
_T_353[15] <= _T_435 @[el2_lib.scala 340:30]
|
|
node _T_436 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 345:36]
|
|
_T_358[0] <= _T_436 @[el2_lib.scala 345:30]
|
|
node _T_437 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 341:36]
|
|
_T_354[15] <= _T_437 @[el2_lib.scala 341:30]
|
|
node _T_438 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 345:36]
|
|
_T_358[1] <= _T_438 @[el2_lib.scala 345:30]
|
|
node _T_439 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 340:36]
|
|
_T_353[16] <= _T_439 @[el2_lib.scala 340:30]
|
|
node _T_440 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 341:36]
|
|
_T_354[16] <= _T_440 @[el2_lib.scala 341:30]
|
|
node _T_441 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 345:36]
|
|
_T_358[2] <= _T_441 @[el2_lib.scala 345:30]
|
|
node _T_442 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 342:36]
|
|
_T_355[15] <= _T_442 @[el2_lib.scala 342:30]
|
|
node _T_443 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 345:36]
|
|
_T_358[3] <= _T_443 @[el2_lib.scala 345:30]
|
|
node _T_444 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 340:36]
|
|
_T_353[17] <= _T_444 @[el2_lib.scala 340:30]
|
|
node _T_445 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 342:36]
|
|
_T_355[16] <= _T_445 @[el2_lib.scala 342:30]
|
|
node _T_446 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 345:36]
|
|
_T_358[4] <= _T_446 @[el2_lib.scala 345:30]
|
|
node _T_447 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 341:36]
|
|
_T_354[17] <= _T_447 @[el2_lib.scala 341:30]
|
|
node _T_448 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 342:36]
|
|
_T_355[17] <= _T_448 @[el2_lib.scala 342:30]
|
|
node _T_449 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 345:36]
|
|
_T_358[5] <= _T_449 @[el2_lib.scala 345:30]
|
|
node _T_450 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 340:36]
|
|
_T_353[18] <= _T_450 @[el2_lib.scala 340:30]
|
|
node _T_451 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 341:36]
|
|
_T_354[18] <= _T_451 @[el2_lib.scala 341:30]
|
|
node _T_452 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 342:36]
|
|
_T_355[18] <= _T_452 @[el2_lib.scala 342:30]
|
|
node _T_453 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 345:36]
|
|
_T_358[6] <= _T_453 @[el2_lib.scala 345:30]
|
|
node _T_454 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 343:36]
|
|
_T_356[15] <= _T_454 @[el2_lib.scala 343:30]
|
|
node _T_455 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 345:36]
|
|
_T_358[7] <= _T_455 @[el2_lib.scala 345:30]
|
|
node _T_456 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 340:36]
|
|
_T_353[19] <= _T_456 @[el2_lib.scala 340:30]
|
|
node _T_457 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 343:36]
|
|
_T_356[16] <= _T_457 @[el2_lib.scala 343:30]
|
|
node _T_458 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 345:36]
|
|
_T_358[8] <= _T_458 @[el2_lib.scala 345:30]
|
|
node _T_459 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 341:36]
|
|
_T_354[19] <= _T_459 @[el2_lib.scala 341:30]
|
|
node _T_460 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 343:36]
|
|
_T_356[17] <= _T_460 @[el2_lib.scala 343:30]
|
|
node _T_461 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 345:36]
|
|
_T_358[9] <= _T_461 @[el2_lib.scala 345:30]
|
|
node _T_462 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 340:36]
|
|
_T_353[20] <= _T_462 @[el2_lib.scala 340:30]
|
|
node _T_463 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 341:36]
|
|
_T_354[20] <= _T_463 @[el2_lib.scala 341:30]
|
|
node _T_464 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 343:36]
|
|
_T_356[18] <= _T_464 @[el2_lib.scala 343:30]
|
|
node _T_465 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 345:36]
|
|
_T_358[10] <= _T_465 @[el2_lib.scala 345:30]
|
|
node _T_466 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 342:36]
|
|
_T_355[19] <= _T_466 @[el2_lib.scala 342:30]
|
|
node _T_467 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 343:36]
|
|
_T_356[19] <= _T_467 @[el2_lib.scala 343:30]
|
|
node _T_468 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 345:36]
|
|
_T_358[11] <= _T_468 @[el2_lib.scala 345:30]
|
|
node _T_469 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 340:36]
|
|
_T_353[21] <= _T_469 @[el2_lib.scala 340:30]
|
|
node _T_470 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 342:36]
|
|
_T_355[20] <= _T_470 @[el2_lib.scala 342:30]
|
|
node _T_471 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 343:36]
|
|
_T_356[20] <= _T_471 @[el2_lib.scala 343:30]
|
|
node _T_472 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 345:36]
|
|
_T_358[12] <= _T_472 @[el2_lib.scala 345:30]
|
|
node _T_473 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 341:36]
|
|
_T_354[21] <= _T_473 @[el2_lib.scala 341:30]
|
|
node _T_474 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 342:36]
|
|
_T_355[21] <= _T_474 @[el2_lib.scala 342:30]
|
|
node _T_475 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 343:36]
|
|
_T_356[21] <= _T_475 @[el2_lib.scala 343:30]
|
|
node _T_476 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 345:36]
|
|
_T_358[13] <= _T_476 @[el2_lib.scala 345:30]
|
|
node _T_477 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 340:36]
|
|
_T_353[22] <= _T_477 @[el2_lib.scala 340:30]
|
|
node _T_478 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 341:36]
|
|
_T_354[22] <= _T_478 @[el2_lib.scala 341:30]
|
|
node _T_479 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 342:36]
|
|
_T_355[22] <= _T_479 @[el2_lib.scala 342:30]
|
|
node _T_480 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 343:36]
|
|
_T_356[22] <= _T_480 @[el2_lib.scala 343:30]
|
|
node _T_481 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 345:36]
|
|
_T_358[14] <= _T_481 @[el2_lib.scala 345:30]
|
|
node _T_482 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 344:36]
|
|
_T_357[15] <= _T_482 @[el2_lib.scala 344:30]
|
|
node _T_483 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 345:36]
|
|
_T_358[15] <= _T_483 @[el2_lib.scala 345:30]
|
|
node _T_484 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 340:36]
|
|
_T_353[23] <= _T_484 @[el2_lib.scala 340:30]
|
|
node _T_485 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 344:36]
|
|
_T_357[16] <= _T_485 @[el2_lib.scala 344:30]
|
|
node _T_486 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 345:36]
|
|
_T_358[16] <= _T_486 @[el2_lib.scala 345:30]
|
|
node _T_487 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 341:36]
|
|
_T_354[23] <= _T_487 @[el2_lib.scala 341:30]
|
|
node _T_488 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 344:36]
|
|
_T_357[17] <= _T_488 @[el2_lib.scala 344:30]
|
|
node _T_489 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 345:36]
|
|
_T_358[17] <= _T_489 @[el2_lib.scala 345:30]
|
|
node _T_490 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 340:36]
|
|
_T_353[24] <= _T_490 @[el2_lib.scala 340:30]
|
|
node _T_491 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 341:36]
|
|
_T_354[24] <= _T_491 @[el2_lib.scala 341:30]
|
|
node _T_492 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 344:36]
|
|
_T_357[18] <= _T_492 @[el2_lib.scala 344:30]
|
|
node _T_493 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 345:36]
|
|
_T_358[18] <= _T_493 @[el2_lib.scala 345:30]
|
|
node _T_494 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 342:36]
|
|
_T_355[23] <= _T_494 @[el2_lib.scala 342:30]
|
|
node _T_495 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 344:36]
|
|
_T_357[19] <= _T_495 @[el2_lib.scala 344:30]
|
|
node _T_496 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 345:36]
|
|
_T_358[19] <= _T_496 @[el2_lib.scala 345:30]
|
|
node _T_497 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 340:36]
|
|
_T_353[25] <= _T_497 @[el2_lib.scala 340:30]
|
|
node _T_498 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 342:36]
|
|
_T_355[24] <= _T_498 @[el2_lib.scala 342:30]
|
|
node _T_499 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 344:36]
|
|
_T_357[20] <= _T_499 @[el2_lib.scala 344:30]
|
|
node _T_500 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 345:36]
|
|
_T_358[20] <= _T_500 @[el2_lib.scala 345:30]
|
|
node _T_501 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 341:36]
|
|
_T_354[25] <= _T_501 @[el2_lib.scala 341:30]
|
|
node _T_502 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 342:36]
|
|
_T_355[25] <= _T_502 @[el2_lib.scala 342:30]
|
|
node _T_503 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 344:36]
|
|
_T_357[21] <= _T_503 @[el2_lib.scala 344:30]
|
|
node _T_504 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 345:36]
|
|
_T_358[21] <= _T_504 @[el2_lib.scala 345:30]
|
|
node _T_505 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 340:36]
|
|
_T_353[26] <= _T_505 @[el2_lib.scala 340:30]
|
|
node _T_506 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 341:36]
|
|
_T_354[26] <= _T_506 @[el2_lib.scala 341:30]
|
|
node _T_507 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 342:36]
|
|
_T_355[26] <= _T_507 @[el2_lib.scala 342:30]
|
|
node _T_508 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 344:36]
|
|
_T_357[22] <= _T_508 @[el2_lib.scala 344:30]
|
|
node _T_509 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 345:36]
|
|
_T_358[22] <= _T_509 @[el2_lib.scala 345:30]
|
|
node _T_510 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 343:36]
|
|
_T_356[23] <= _T_510 @[el2_lib.scala 343:30]
|
|
node _T_511 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 344:36]
|
|
_T_357[23] <= _T_511 @[el2_lib.scala 344:30]
|
|
node _T_512 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 345:36]
|
|
_T_358[23] <= _T_512 @[el2_lib.scala 345:30]
|
|
node _T_513 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 340:36]
|
|
_T_353[27] <= _T_513 @[el2_lib.scala 340:30]
|
|
node _T_514 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 343:36]
|
|
_T_356[24] <= _T_514 @[el2_lib.scala 343:30]
|
|
node _T_515 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 344:36]
|
|
_T_357[24] <= _T_515 @[el2_lib.scala 344:30]
|
|
node _T_516 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 345:36]
|
|
_T_358[24] <= _T_516 @[el2_lib.scala 345:30]
|
|
node _T_517 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 341:36]
|
|
_T_354[27] <= _T_517 @[el2_lib.scala 341:30]
|
|
node _T_518 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 343:36]
|
|
_T_356[25] <= _T_518 @[el2_lib.scala 343:30]
|
|
node _T_519 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 344:36]
|
|
_T_357[25] <= _T_519 @[el2_lib.scala 344:30]
|
|
node _T_520 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 345:36]
|
|
_T_358[25] <= _T_520 @[el2_lib.scala 345:30]
|
|
node _T_521 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 340:36]
|
|
_T_353[28] <= _T_521 @[el2_lib.scala 340:30]
|
|
node _T_522 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 341:36]
|
|
_T_354[28] <= _T_522 @[el2_lib.scala 341:30]
|
|
node _T_523 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 343:36]
|
|
_T_356[26] <= _T_523 @[el2_lib.scala 343:30]
|
|
node _T_524 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 344:36]
|
|
_T_357[26] <= _T_524 @[el2_lib.scala 344:30]
|
|
node _T_525 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 345:36]
|
|
_T_358[26] <= _T_525 @[el2_lib.scala 345:30]
|
|
node _T_526 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 342:36]
|
|
_T_355[27] <= _T_526 @[el2_lib.scala 342:30]
|
|
node _T_527 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 343:36]
|
|
_T_356[27] <= _T_527 @[el2_lib.scala 343:30]
|
|
node _T_528 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 344:36]
|
|
_T_357[27] <= _T_528 @[el2_lib.scala 344:30]
|
|
node _T_529 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 345:36]
|
|
_T_358[27] <= _T_529 @[el2_lib.scala 345:30]
|
|
node _T_530 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 340:36]
|
|
_T_353[29] <= _T_530 @[el2_lib.scala 340:30]
|
|
node _T_531 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 342:36]
|
|
_T_355[28] <= _T_531 @[el2_lib.scala 342:30]
|
|
node _T_532 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 343:36]
|
|
_T_356[28] <= _T_532 @[el2_lib.scala 343:30]
|
|
node _T_533 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 344:36]
|
|
_T_357[28] <= _T_533 @[el2_lib.scala 344:30]
|
|
node _T_534 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 345:36]
|
|
_T_358[28] <= _T_534 @[el2_lib.scala 345:30]
|
|
node _T_535 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 341:36]
|
|
_T_354[29] <= _T_535 @[el2_lib.scala 341:30]
|
|
node _T_536 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 342:36]
|
|
_T_355[29] <= _T_536 @[el2_lib.scala 342:30]
|
|
node _T_537 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 343:36]
|
|
_T_356[29] <= _T_537 @[el2_lib.scala 343:30]
|
|
node _T_538 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 344:36]
|
|
_T_357[29] <= _T_538 @[el2_lib.scala 344:30]
|
|
node _T_539 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 345:36]
|
|
_T_358[29] <= _T_539 @[el2_lib.scala 345:30]
|
|
node _T_540 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 340:36]
|
|
_T_353[30] <= _T_540 @[el2_lib.scala 340:30]
|
|
node _T_541 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 341:36]
|
|
_T_354[30] <= _T_541 @[el2_lib.scala 341:30]
|
|
node _T_542 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 342:36]
|
|
_T_355[30] <= _T_542 @[el2_lib.scala 342:30]
|
|
node _T_543 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 343:36]
|
|
_T_356[30] <= _T_543 @[el2_lib.scala 343:30]
|
|
node _T_544 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 344:36]
|
|
_T_357[30] <= _T_544 @[el2_lib.scala 344:30]
|
|
node _T_545 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 345:36]
|
|
_T_358[30] <= _T_545 @[el2_lib.scala 345:30]
|
|
node _T_546 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 340:36]
|
|
_T_353[31] <= _T_546 @[el2_lib.scala 340:30]
|
|
node _T_547 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 346:36]
|
|
_T_359[0] <= _T_547 @[el2_lib.scala 346:30]
|
|
node _T_548 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 341:36]
|
|
_T_354[31] <= _T_548 @[el2_lib.scala 341:30]
|
|
node _T_549 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 346:36]
|
|
_T_359[1] <= _T_549 @[el2_lib.scala 346:30]
|
|
node _T_550 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 340:36]
|
|
_T_353[32] <= _T_550 @[el2_lib.scala 340:30]
|
|
node _T_551 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 341:36]
|
|
_T_354[32] <= _T_551 @[el2_lib.scala 341:30]
|
|
node _T_552 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 346:36]
|
|
_T_359[2] <= _T_552 @[el2_lib.scala 346:30]
|
|
node _T_553 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 342:36]
|
|
_T_355[31] <= _T_553 @[el2_lib.scala 342:30]
|
|
node _T_554 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 346:36]
|
|
_T_359[3] <= _T_554 @[el2_lib.scala 346:30]
|
|
node _T_555 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 340:36]
|
|
_T_353[33] <= _T_555 @[el2_lib.scala 340:30]
|
|
node _T_556 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 342:36]
|
|
_T_355[32] <= _T_556 @[el2_lib.scala 342:30]
|
|
node _T_557 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 346:36]
|
|
_T_359[4] <= _T_557 @[el2_lib.scala 346:30]
|
|
node _T_558 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 341:36]
|
|
_T_354[33] <= _T_558 @[el2_lib.scala 341:30]
|
|
node _T_559 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 342:36]
|
|
_T_355[33] <= _T_559 @[el2_lib.scala 342:30]
|
|
node _T_560 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 346:36]
|
|
_T_359[5] <= _T_560 @[el2_lib.scala 346:30]
|
|
node _T_561 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 340:36]
|
|
_T_353[34] <= _T_561 @[el2_lib.scala 340:30]
|
|
node _T_562 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 341:36]
|
|
_T_354[34] <= _T_562 @[el2_lib.scala 341:30]
|
|
node _T_563 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 342:36]
|
|
_T_355[34] <= _T_563 @[el2_lib.scala 342:30]
|
|
node _T_564 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 346:36]
|
|
_T_359[6] <= _T_564 @[el2_lib.scala 346:30]
|
|
node _T_565 = cat(_T_353[1], _T_353[0]) @[el2_lib.scala 348:27]
|
|
node _T_566 = cat(_T_353[3], _T_353[2]) @[el2_lib.scala 348:27]
|
|
node _T_567 = cat(_T_566, _T_565) @[el2_lib.scala 348:27]
|
|
node _T_568 = cat(_T_353[5], _T_353[4]) @[el2_lib.scala 348:27]
|
|
node _T_569 = cat(_T_353[7], _T_353[6]) @[el2_lib.scala 348:27]
|
|
node _T_570 = cat(_T_569, _T_568) @[el2_lib.scala 348:27]
|
|
node _T_571 = cat(_T_570, _T_567) @[el2_lib.scala 348:27]
|
|
node _T_572 = cat(_T_353[9], _T_353[8]) @[el2_lib.scala 348:27]
|
|
node _T_573 = cat(_T_353[11], _T_353[10]) @[el2_lib.scala 348:27]
|
|
node _T_574 = cat(_T_573, _T_572) @[el2_lib.scala 348:27]
|
|
node _T_575 = cat(_T_353[13], _T_353[12]) @[el2_lib.scala 348:27]
|
|
node _T_576 = cat(_T_353[16], _T_353[15]) @[el2_lib.scala 348:27]
|
|
node _T_577 = cat(_T_576, _T_353[14]) @[el2_lib.scala 348:27]
|
|
node _T_578 = cat(_T_577, _T_575) @[el2_lib.scala 348:27]
|
|
node _T_579 = cat(_T_578, _T_574) @[el2_lib.scala 348:27]
|
|
node _T_580 = cat(_T_579, _T_571) @[el2_lib.scala 348:27]
|
|
node _T_581 = cat(_T_353[18], _T_353[17]) @[el2_lib.scala 348:27]
|
|
node _T_582 = cat(_T_353[20], _T_353[19]) @[el2_lib.scala 348:27]
|
|
node _T_583 = cat(_T_582, _T_581) @[el2_lib.scala 348:27]
|
|
node _T_584 = cat(_T_353[22], _T_353[21]) @[el2_lib.scala 348:27]
|
|
node _T_585 = cat(_T_353[25], _T_353[24]) @[el2_lib.scala 348:27]
|
|
node _T_586 = cat(_T_585, _T_353[23]) @[el2_lib.scala 348:27]
|
|
node _T_587 = cat(_T_586, _T_584) @[el2_lib.scala 348:27]
|
|
node _T_588 = cat(_T_587, _T_583) @[el2_lib.scala 348:27]
|
|
node _T_589 = cat(_T_353[27], _T_353[26]) @[el2_lib.scala 348:27]
|
|
node _T_590 = cat(_T_353[29], _T_353[28]) @[el2_lib.scala 348:27]
|
|
node _T_591 = cat(_T_590, _T_589) @[el2_lib.scala 348:27]
|
|
node _T_592 = cat(_T_353[31], _T_353[30]) @[el2_lib.scala 348:27]
|
|
node _T_593 = cat(_T_353[34], _T_353[33]) @[el2_lib.scala 348:27]
|
|
node _T_594 = cat(_T_593, _T_353[32]) @[el2_lib.scala 348:27]
|
|
node _T_595 = cat(_T_594, _T_592) @[el2_lib.scala 348:27]
|
|
node _T_596 = cat(_T_595, _T_591) @[el2_lib.scala 348:27]
|
|
node _T_597 = cat(_T_596, _T_588) @[el2_lib.scala 348:27]
|
|
node _T_598 = cat(_T_597, _T_580) @[el2_lib.scala 348:27]
|
|
node _T_599 = xorr(_T_598) @[el2_lib.scala 348:34]
|
|
node _T_600 = cat(_T_354[1], _T_354[0]) @[el2_lib.scala 348:44]
|
|
node _T_601 = cat(_T_354[3], _T_354[2]) @[el2_lib.scala 348:44]
|
|
node _T_602 = cat(_T_601, _T_600) @[el2_lib.scala 348:44]
|
|
node _T_603 = cat(_T_354[5], _T_354[4]) @[el2_lib.scala 348:44]
|
|
node _T_604 = cat(_T_354[7], _T_354[6]) @[el2_lib.scala 348:44]
|
|
node _T_605 = cat(_T_604, _T_603) @[el2_lib.scala 348:44]
|
|
node _T_606 = cat(_T_605, _T_602) @[el2_lib.scala 348:44]
|
|
node _T_607 = cat(_T_354[9], _T_354[8]) @[el2_lib.scala 348:44]
|
|
node _T_608 = cat(_T_354[11], _T_354[10]) @[el2_lib.scala 348:44]
|
|
node _T_609 = cat(_T_608, _T_607) @[el2_lib.scala 348:44]
|
|
node _T_610 = cat(_T_354[13], _T_354[12]) @[el2_lib.scala 348:44]
|
|
node _T_611 = cat(_T_354[16], _T_354[15]) @[el2_lib.scala 348:44]
|
|
node _T_612 = cat(_T_611, _T_354[14]) @[el2_lib.scala 348:44]
|
|
node _T_613 = cat(_T_612, _T_610) @[el2_lib.scala 348:44]
|
|
node _T_614 = cat(_T_613, _T_609) @[el2_lib.scala 348:44]
|
|
node _T_615 = cat(_T_614, _T_606) @[el2_lib.scala 348:44]
|
|
node _T_616 = cat(_T_354[18], _T_354[17]) @[el2_lib.scala 348:44]
|
|
node _T_617 = cat(_T_354[20], _T_354[19]) @[el2_lib.scala 348:44]
|
|
node _T_618 = cat(_T_617, _T_616) @[el2_lib.scala 348:44]
|
|
node _T_619 = cat(_T_354[22], _T_354[21]) @[el2_lib.scala 348:44]
|
|
node _T_620 = cat(_T_354[25], _T_354[24]) @[el2_lib.scala 348:44]
|
|
node _T_621 = cat(_T_620, _T_354[23]) @[el2_lib.scala 348:44]
|
|
node _T_622 = cat(_T_621, _T_619) @[el2_lib.scala 348:44]
|
|
node _T_623 = cat(_T_622, _T_618) @[el2_lib.scala 348:44]
|
|
node _T_624 = cat(_T_354[27], _T_354[26]) @[el2_lib.scala 348:44]
|
|
node _T_625 = cat(_T_354[29], _T_354[28]) @[el2_lib.scala 348:44]
|
|
node _T_626 = cat(_T_625, _T_624) @[el2_lib.scala 348:44]
|
|
node _T_627 = cat(_T_354[31], _T_354[30]) @[el2_lib.scala 348:44]
|
|
node _T_628 = cat(_T_354[34], _T_354[33]) @[el2_lib.scala 348:44]
|
|
node _T_629 = cat(_T_628, _T_354[32]) @[el2_lib.scala 348:44]
|
|
node _T_630 = cat(_T_629, _T_627) @[el2_lib.scala 348:44]
|
|
node _T_631 = cat(_T_630, _T_626) @[el2_lib.scala 348:44]
|
|
node _T_632 = cat(_T_631, _T_623) @[el2_lib.scala 348:44]
|
|
node _T_633 = cat(_T_632, _T_615) @[el2_lib.scala 348:44]
|
|
node _T_634 = xorr(_T_633) @[el2_lib.scala 348:51]
|
|
node _T_635 = cat(_T_355[1], _T_355[0]) @[el2_lib.scala 348:61]
|
|
node _T_636 = cat(_T_355[3], _T_355[2]) @[el2_lib.scala 348:61]
|
|
node _T_637 = cat(_T_636, _T_635) @[el2_lib.scala 348:61]
|
|
node _T_638 = cat(_T_355[5], _T_355[4]) @[el2_lib.scala 348:61]
|
|
node _T_639 = cat(_T_355[7], _T_355[6]) @[el2_lib.scala 348:61]
|
|
node _T_640 = cat(_T_639, _T_638) @[el2_lib.scala 348:61]
|
|
node _T_641 = cat(_T_640, _T_637) @[el2_lib.scala 348:61]
|
|
node _T_642 = cat(_T_355[9], _T_355[8]) @[el2_lib.scala 348:61]
|
|
node _T_643 = cat(_T_355[11], _T_355[10]) @[el2_lib.scala 348:61]
|
|
node _T_644 = cat(_T_643, _T_642) @[el2_lib.scala 348:61]
|
|
node _T_645 = cat(_T_355[13], _T_355[12]) @[el2_lib.scala 348:61]
|
|
node _T_646 = cat(_T_355[16], _T_355[15]) @[el2_lib.scala 348:61]
|
|
node _T_647 = cat(_T_646, _T_355[14]) @[el2_lib.scala 348:61]
|
|
node _T_648 = cat(_T_647, _T_645) @[el2_lib.scala 348:61]
|
|
node _T_649 = cat(_T_648, _T_644) @[el2_lib.scala 348:61]
|
|
node _T_650 = cat(_T_649, _T_641) @[el2_lib.scala 348:61]
|
|
node _T_651 = cat(_T_355[18], _T_355[17]) @[el2_lib.scala 348:61]
|
|
node _T_652 = cat(_T_355[20], _T_355[19]) @[el2_lib.scala 348:61]
|
|
node _T_653 = cat(_T_652, _T_651) @[el2_lib.scala 348:61]
|
|
node _T_654 = cat(_T_355[22], _T_355[21]) @[el2_lib.scala 348:61]
|
|
node _T_655 = cat(_T_355[25], _T_355[24]) @[el2_lib.scala 348:61]
|
|
node _T_656 = cat(_T_655, _T_355[23]) @[el2_lib.scala 348:61]
|
|
node _T_657 = cat(_T_656, _T_654) @[el2_lib.scala 348:61]
|
|
node _T_658 = cat(_T_657, _T_653) @[el2_lib.scala 348:61]
|
|
node _T_659 = cat(_T_355[27], _T_355[26]) @[el2_lib.scala 348:61]
|
|
node _T_660 = cat(_T_355[29], _T_355[28]) @[el2_lib.scala 348:61]
|
|
node _T_661 = cat(_T_660, _T_659) @[el2_lib.scala 348:61]
|
|
node _T_662 = cat(_T_355[31], _T_355[30]) @[el2_lib.scala 348:61]
|
|
node _T_663 = cat(_T_355[34], _T_355[33]) @[el2_lib.scala 348:61]
|
|
node _T_664 = cat(_T_663, _T_355[32]) @[el2_lib.scala 348:61]
|
|
node _T_665 = cat(_T_664, _T_662) @[el2_lib.scala 348:61]
|
|
node _T_666 = cat(_T_665, _T_661) @[el2_lib.scala 348:61]
|
|
node _T_667 = cat(_T_666, _T_658) @[el2_lib.scala 348:61]
|
|
node _T_668 = cat(_T_667, _T_650) @[el2_lib.scala 348:61]
|
|
node _T_669 = xorr(_T_668) @[el2_lib.scala 348:68]
|
|
node _T_670 = cat(_T_356[2], _T_356[1]) @[el2_lib.scala 348:78]
|
|
node _T_671 = cat(_T_670, _T_356[0]) @[el2_lib.scala 348:78]
|
|
node _T_672 = cat(_T_356[4], _T_356[3]) @[el2_lib.scala 348:78]
|
|
node _T_673 = cat(_T_356[6], _T_356[5]) @[el2_lib.scala 348:78]
|
|
node _T_674 = cat(_T_673, _T_672) @[el2_lib.scala 348:78]
|
|
node _T_675 = cat(_T_674, _T_671) @[el2_lib.scala 348:78]
|
|
node _T_676 = cat(_T_356[8], _T_356[7]) @[el2_lib.scala 348:78]
|
|
node _T_677 = cat(_T_356[10], _T_356[9]) @[el2_lib.scala 348:78]
|
|
node _T_678 = cat(_T_677, _T_676) @[el2_lib.scala 348:78]
|
|
node _T_679 = cat(_T_356[12], _T_356[11]) @[el2_lib.scala 348:78]
|
|
node _T_680 = cat(_T_356[14], _T_356[13]) @[el2_lib.scala 348:78]
|
|
node _T_681 = cat(_T_680, _T_679) @[el2_lib.scala 348:78]
|
|
node _T_682 = cat(_T_681, _T_678) @[el2_lib.scala 348:78]
|
|
node _T_683 = cat(_T_682, _T_675) @[el2_lib.scala 348:78]
|
|
node _T_684 = cat(_T_356[16], _T_356[15]) @[el2_lib.scala 348:78]
|
|
node _T_685 = cat(_T_356[18], _T_356[17]) @[el2_lib.scala 348:78]
|
|
node _T_686 = cat(_T_685, _T_684) @[el2_lib.scala 348:78]
|
|
node _T_687 = cat(_T_356[20], _T_356[19]) @[el2_lib.scala 348:78]
|
|
node _T_688 = cat(_T_356[22], _T_356[21]) @[el2_lib.scala 348:78]
|
|
node _T_689 = cat(_T_688, _T_687) @[el2_lib.scala 348:78]
|
|
node _T_690 = cat(_T_689, _T_686) @[el2_lib.scala 348:78]
|
|
node _T_691 = cat(_T_356[24], _T_356[23]) @[el2_lib.scala 348:78]
|
|
node _T_692 = cat(_T_356[26], _T_356[25]) @[el2_lib.scala 348:78]
|
|
node _T_693 = cat(_T_692, _T_691) @[el2_lib.scala 348:78]
|
|
node _T_694 = cat(_T_356[28], _T_356[27]) @[el2_lib.scala 348:78]
|
|
node _T_695 = cat(_T_356[30], _T_356[29]) @[el2_lib.scala 348:78]
|
|
node _T_696 = cat(_T_695, _T_694) @[el2_lib.scala 348:78]
|
|
node _T_697 = cat(_T_696, _T_693) @[el2_lib.scala 348:78]
|
|
node _T_698 = cat(_T_697, _T_690) @[el2_lib.scala 348:78]
|
|
node _T_699 = cat(_T_698, _T_683) @[el2_lib.scala 348:78]
|
|
node _T_700 = xorr(_T_699) @[el2_lib.scala 348:85]
|
|
node _T_701 = cat(_T_357[2], _T_357[1]) @[el2_lib.scala 348:95]
|
|
node _T_702 = cat(_T_701, _T_357[0]) @[el2_lib.scala 348:95]
|
|
node _T_703 = cat(_T_357[4], _T_357[3]) @[el2_lib.scala 348:95]
|
|
node _T_704 = cat(_T_357[6], _T_357[5]) @[el2_lib.scala 348:95]
|
|
node _T_705 = cat(_T_704, _T_703) @[el2_lib.scala 348:95]
|
|
node _T_706 = cat(_T_705, _T_702) @[el2_lib.scala 348:95]
|
|
node _T_707 = cat(_T_357[8], _T_357[7]) @[el2_lib.scala 348:95]
|
|
node _T_708 = cat(_T_357[10], _T_357[9]) @[el2_lib.scala 348:95]
|
|
node _T_709 = cat(_T_708, _T_707) @[el2_lib.scala 348:95]
|
|
node _T_710 = cat(_T_357[12], _T_357[11]) @[el2_lib.scala 348:95]
|
|
node _T_711 = cat(_T_357[14], _T_357[13]) @[el2_lib.scala 348:95]
|
|
node _T_712 = cat(_T_711, _T_710) @[el2_lib.scala 348:95]
|
|
node _T_713 = cat(_T_712, _T_709) @[el2_lib.scala 348:95]
|
|
node _T_714 = cat(_T_713, _T_706) @[el2_lib.scala 348:95]
|
|
node _T_715 = cat(_T_357[16], _T_357[15]) @[el2_lib.scala 348:95]
|
|
node _T_716 = cat(_T_357[18], _T_357[17]) @[el2_lib.scala 348:95]
|
|
node _T_717 = cat(_T_716, _T_715) @[el2_lib.scala 348:95]
|
|
node _T_718 = cat(_T_357[20], _T_357[19]) @[el2_lib.scala 348:95]
|
|
node _T_719 = cat(_T_357[22], _T_357[21]) @[el2_lib.scala 348:95]
|
|
node _T_720 = cat(_T_719, _T_718) @[el2_lib.scala 348:95]
|
|
node _T_721 = cat(_T_720, _T_717) @[el2_lib.scala 348:95]
|
|
node _T_722 = cat(_T_357[24], _T_357[23]) @[el2_lib.scala 348:95]
|
|
node _T_723 = cat(_T_357[26], _T_357[25]) @[el2_lib.scala 348:95]
|
|
node _T_724 = cat(_T_723, _T_722) @[el2_lib.scala 348:95]
|
|
node _T_725 = cat(_T_357[28], _T_357[27]) @[el2_lib.scala 348:95]
|
|
node _T_726 = cat(_T_357[30], _T_357[29]) @[el2_lib.scala 348:95]
|
|
node _T_727 = cat(_T_726, _T_725) @[el2_lib.scala 348:95]
|
|
node _T_728 = cat(_T_727, _T_724) @[el2_lib.scala 348:95]
|
|
node _T_729 = cat(_T_728, _T_721) @[el2_lib.scala 348:95]
|
|
node _T_730 = cat(_T_729, _T_714) @[el2_lib.scala 348:95]
|
|
node _T_731 = xorr(_T_730) @[el2_lib.scala 348:102]
|
|
node _T_732 = cat(_T_358[2], _T_358[1]) @[el2_lib.scala 348:112]
|
|
node _T_733 = cat(_T_732, _T_358[0]) @[el2_lib.scala 348:112]
|
|
node _T_734 = cat(_T_358[4], _T_358[3]) @[el2_lib.scala 348:112]
|
|
node _T_735 = cat(_T_358[6], _T_358[5]) @[el2_lib.scala 348:112]
|
|
node _T_736 = cat(_T_735, _T_734) @[el2_lib.scala 348:112]
|
|
node _T_737 = cat(_T_736, _T_733) @[el2_lib.scala 348:112]
|
|
node _T_738 = cat(_T_358[8], _T_358[7]) @[el2_lib.scala 348:112]
|
|
node _T_739 = cat(_T_358[10], _T_358[9]) @[el2_lib.scala 348:112]
|
|
node _T_740 = cat(_T_739, _T_738) @[el2_lib.scala 348:112]
|
|
node _T_741 = cat(_T_358[12], _T_358[11]) @[el2_lib.scala 348:112]
|
|
node _T_742 = cat(_T_358[14], _T_358[13]) @[el2_lib.scala 348:112]
|
|
node _T_743 = cat(_T_742, _T_741) @[el2_lib.scala 348:112]
|
|
node _T_744 = cat(_T_743, _T_740) @[el2_lib.scala 348:112]
|
|
node _T_745 = cat(_T_744, _T_737) @[el2_lib.scala 348:112]
|
|
node _T_746 = cat(_T_358[16], _T_358[15]) @[el2_lib.scala 348:112]
|
|
node _T_747 = cat(_T_358[18], _T_358[17]) @[el2_lib.scala 348:112]
|
|
node _T_748 = cat(_T_747, _T_746) @[el2_lib.scala 348:112]
|
|
node _T_749 = cat(_T_358[20], _T_358[19]) @[el2_lib.scala 348:112]
|
|
node _T_750 = cat(_T_358[22], _T_358[21]) @[el2_lib.scala 348:112]
|
|
node _T_751 = cat(_T_750, _T_749) @[el2_lib.scala 348:112]
|
|
node _T_752 = cat(_T_751, _T_748) @[el2_lib.scala 348:112]
|
|
node _T_753 = cat(_T_358[24], _T_358[23]) @[el2_lib.scala 348:112]
|
|
node _T_754 = cat(_T_358[26], _T_358[25]) @[el2_lib.scala 348:112]
|
|
node _T_755 = cat(_T_754, _T_753) @[el2_lib.scala 348:112]
|
|
node _T_756 = cat(_T_358[28], _T_358[27]) @[el2_lib.scala 348:112]
|
|
node _T_757 = cat(_T_358[30], _T_358[29]) @[el2_lib.scala 348:112]
|
|
node _T_758 = cat(_T_757, _T_756) @[el2_lib.scala 348:112]
|
|
node _T_759 = cat(_T_758, _T_755) @[el2_lib.scala 348:112]
|
|
node _T_760 = cat(_T_759, _T_752) @[el2_lib.scala 348:112]
|
|
node _T_761 = cat(_T_760, _T_745) @[el2_lib.scala 348:112]
|
|
node _T_762 = xorr(_T_761) @[el2_lib.scala 348:119]
|
|
node _T_763 = cat(_T_359[2], _T_359[1]) @[el2_lib.scala 348:129]
|
|
node _T_764 = cat(_T_763, _T_359[0]) @[el2_lib.scala 348:129]
|
|
node _T_765 = cat(_T_359[4], _T_359[3]) @[el2_lib.scala 348:129]
|
|
node _T_766 = cat(_T_359[6], _T_359[5]) @[el2_lib.scala 348:129]
|
|
node _T_767 = cat(_T_766, _T_765) @[el2_lib.scala 348:129]
|
|
node _T_768 = cat(_T_767, _T_764) @[el2_lib.scala 348:129]
|
|
node _T_769 = xorr(_T_768) @[el2_lib.scala 348:136]
|
|
node _T_770 = cat(_T_731, _T_762) @[Cat.scala 29:58]
|
|
node _T_771 = cat(_T_770, _T_769) @[Cat.scala 29:58]
|
|
node _T_772 = cat(_T_669, _T_700) @[Cat.scala 29:58]
|
|
node _T_773 = cat(_T_599, _T_634) @[Cat.scala 29:58]
|
|
node _T_774 = cat(_T_773, _T_772) @[Cat.scala 29:58]
|
|
node ic_wr_ecc = cat(_T_774, _T_771) @[Cat.scala 29:58]
|
|
wire _T_775 : UInt<1>[35] @[el2_lib.scala 327:18]
|
|
wire _T_776 : UInt<1>[35] @[el2_lib.scala 328:18]
|
|
wire _T_777 : UInt<1>[35] @[el2_lib.scala 329:18]
|
|
wire _T_778 : UInt<1>[31] @[el2_lib.scala 330:18]
|
|
wire _T_779 : UInt<1>[31] @[el2_lib.scala 331:18]
|
|
wire _T_780 : UInt<1>[31] @[el2_lib.scala 332:18]
|
|
wire _T_781 : UInt<1>[7] @[el2_lib.scala 333:18]
|
|
node _T_782 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 340:36]
|
|
_T_775[0] <= _T_782 @[el2_lib.scala 340:30]
|
|
node _T_783 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 341:36]
|
|
_T_776[0] <= _T_783 @[el2_lib.scala 341:30]
|
|
node _T_784 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 340:36]
|
|
_T_775[1] <= _T_784 @[el2_lib.scala 340:30]
|
|
node _T_785 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 342:36]
|
|
_T_777[0] <= _T_785 @[el2_lib.scala 342:30]
|
|
node _T_786 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 341:36]
|
|
_T_776[1] <= _T_786 @[el2_lib.scala 341:30]
|
|
node _T_787 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 342:36]
|
|
_T_777[1] <= _T_787 @[el2_lib.scala 342:30]
|
|
node _T_788 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 340:36]
|
|
_T_775[2] <= _T_788 @[el2_lib.scala 340:30]
|
|
node _T_789 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 341:36]
|
|
_T_776[2] <= _T_789 @[el2_lib.scala 341:30]
|
|
node _T_790 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 342:36]
|
|
_T_777[2] <= _T_790 @[el2_lib.scala 342:30]
|
|
node _T_791 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 340:36]
|
|
_T_775[3] <= _T_791 @[el2_lib.scala 340:30]
|
|
node _T_792 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 343:36]
|
|
_T_778[0] <= _T_792 @[el2_lib.scala 343:30]
|
|
node _T_793 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 341:36]
|
|
_T_776[3] <= _T_793 @[el2_lib.scala 341:30]
|
|
node _T_794 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 343:36]
|
|
_T_778[1] <= _T_794 @[el2_lib.scala 343:30]
|
|
node _T_795 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 340:36]
|
|
_T_775[4] <= _T_795 @[el2_lib.scala 340:30]
|
|
node _T_796 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 341:36]
|
|
_T_776[4] <= _T_796 @[el2_lib.scala 341:30]
|
|
node _T_797 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 343:36]
|
|
_T_778[2] <= _T_797 @[el2_lib.scala 343:30]
|
|
node _T_798 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 342:36]
|
|
_T_777[3] <= _T_798 @[el2_lib.scala 342:30]
|
|
node _T_799 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 343:36]
|
|
_T_778[3] <= _T_799 @[el2_lib.scala 343:30]
|
|
node _T_800 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 340:36]
|
|
_T_775[5] <= _T_800 @[el2_lib.scala 340:30]
|
|
node _T_801 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 342:36]
|
|
_T_777[4] <= _T_801 @[el2_lib.scala 342:30]
|
|
node _T_802 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 343:36]
|
|
_T_778[4] <= _T_802 @[el2_lib.scala 343:30]
|
|
node _T_803 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 341:36]
|
|
_T_776[5] <= _T_803 @[el2_lib.scala 341:30]
|
|
node _T_804 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 342:36]
|
|
_T_777[5] <= _T_804 @[el2_lib.scala 342:30]
|
|
node _T_805 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 343:36]
|
|
_T_778[5] <= _T_805 @[el2_lib.scala 343:30]
|
|
node _T_806 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 340:36]
|
|
_T_775[6] <= _T_806 @[el2_lib.scala 340:30]
|
|
node _T_807 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 341:36]
|
|
_T_776[6] <= _T_807 @[el2_lib.scala 341:30]
|
|
node _T_808 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 342:36]
|
|
_T_777[6] <= _T_808 @[el2_lib.scala 342:30]
|
|
node _T_809 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 343:36]
|
|
_T_778[6] <= _T_809 @[el2_lib.scala 343:30]
|
|
node _T_810 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 340:36]
|
|
_T_775[7] <= _T_810 @[el2_lib.scala 340:30]
|
|
node _T_811 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 344:36]
|
|
_T_779[0] <= _T_811 @[el2_lib.scala 344:30]
|
|
node _T_812 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 341:36]
|
|
_T_776[7] <= _T_812 @[el2_lib.scala 341:30]
|
|
node _T_813 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 344:36]
|
|
_T_779[1] <= _T_813 @[el2_lib.scala 344:30]
|
|
node _T_814 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 340:36]
|
|
_T_775[8] <= _T_814 @[el2_lib.scala 340:30]
|
|
node _T_815 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 341:36]
|
|
_T_776[8] <= _T_815 @[el2_lib.scala 341:30]
|
|
node _T_816 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 344:36]
|
|
_T_779[2] <= _T_816 @[el2_lib.scala 344:30]
|
|
node _T_817 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 342:36]
|
|
_T_777[7] <= _T_817 @[el2_lib.scala 342:30]
|
|
node _T_818 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 344:36]
|
|
_T_779[3] <= _T_818 @[el2_lib.scala 344:30]
|
|
node _T_819 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 340:36]
|
|
_T_775[9] <= _T_819 @[el2_lib.scala 340:30]
|
|
node _T_820 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 342:36]
|
|
_T_777[8] <= _T_820 @[el2_lib.scala 342:30]
|
|
node _T_821 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 344:36]
|
|
_T_779[4] <= _T_821 @[el2_lib.scala 344:30]
|
|
node _T_822 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 341:36]
|
|
_T_776[9] <= _T_822 @[el2_lib.scala 341:30]
|
|
node _T_823 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 342:36]
|
|
_T_777[9] <= _T_823 @[el2_lib.scala 342:30]
|
|
node _T_824 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 344:36]
|
|
_T_779[5] <= _T_824 @[el2_lib.scala 344:30]
|
|
node _T_825 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 340:36]
|
|
_T_775[10] <= _T_825 @[el2_lib.scala 340:30]
|
|
node _T_826 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 341:36]
|
|
_T_776[10] <= _T_826 @[el2_lib.scala 341:30]
|
|
node _T_827 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 342:36]
|
|
_T_777[10] <= _T_827 @[el2_lib.scala 342:30]
|
|
node _T_828 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 344:36]
|
|
_T_779[6] <= _T_828 @[el2_lib.scala 344:30]
|
|
node _T_829 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 343:36]
|
|
_T_778[7] <= _T_829 @[el2_lib.scala 343:30]
|
|
node _T_830 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 344:36]
|
|
_T_779[7] <= _T_830 @[el2_lib.scala 344:30]
|
|
node _T_831 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 340:36]
|
|
_T_775[11] <= _T_831 @[el2_lib.scala 340:30]
|
|
node _T_832 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 343:36]
|
|
_T_778[8] <= _T_832 @[el2_lib.scala 343:30]
|
|
node _T_833 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 344:36]
|
|
_T_779[8] <= _T_833 @[el2_lib.scala 344:30]
|
|
node _T_834 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 341:36]
|
|
_T_776[11] <= _T_834 @[el2_lib.scala 341:30]
|
|
node _T_835 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 343:36]
|
|
_T_778[9] <= _T_835 @[el2_lib.scala 343:30]
|
|
node _T_836 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 344:36]
|
|
_T_779[9] <= _T_836 @[el2_lib.scala 344:30]
|
|
node _T_837 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 340:36]
|
|
_T_775[12] <= _T_837 @[el2_lib.scala 340:30]
|
|
node _T_838 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 341:36]
|
|
_T_776[12] <= _T_838 @[el2_lib.scala 341:30]
|
|
node _T_839 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 343:36]
|
|
_T_778[10] <= _T_839 @[el2_lib.scala 343:30]
|
|
node _T_840 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 344:36]
|
|
_T_779[10] <= _T_840 @[el2_lib.scala 344:30]
|
|
node _T_841 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 342:36]
|
|
_T_777[11] <= _T_841 @[el2_lib.scala 342:30]
|
|
node _T_842 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 343:36]
|
|
_T_778[11] <= _T_842 @[el2_lib.scala 343:30]
|
|
node _T_843 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 344:36]
|
|
_T_779[11] <= _T_843 @[el2_lib.scala 344:30]
|
|
node _T_844 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 340:36]
|
|
_T_775[13] <= _T_844 @[el2_lib.scala 340:30]
|
|
node _T_845 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 342:36]
|
|
_T_777[12] <= _T_845 @[el2_lib.scala 342:30]
|
|
node _T_846 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 343:36]
|
|
_T_778[12] <= _T_846 @[el2_lib.scala 343:30]
|
|
node _T_847 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 344:36]
|
|
_T_779[12] <= _T_847 @[el2_lib.scala 344:30]
|
|
node _T_848 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 341:36]
|
|
_T_776[13] <= _T_848 @[el2_lib.scala 341:30]
|
|
node _T_849 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 342:36]
|
|
_T_777[13] <= _T_849 @[el2_lib.scala 342:30]
|
|
node _T_850 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 343:36]
|
|
_T_778[13] <= _T_850 @[el2_lib.scala 343:30]
|
|
node _T_851 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 344:36]
|
|
_T_779[13] <= _T_851 @[el2_lib.scala 344:30]
|
|
node _T_852 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 340:36]
|
|
_T_775[14] <= _T_852 @[el2_lib.scala 340:30]
|
|
node _T_853 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 341:36]
|
|
_T_776[14] <= _T_853 @[el2_lib.scala 341:30]
|
|
node _T_854 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 342:36]
|
|
_T_777[14] <= _T_854 @[el2_lib.scala 342:30]
|
|
node _T_855 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 343:36]
|
|
_T_778[14] <= _T_855 @[el2_lib.scala 343:30]
|
|
node _T_856 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 344:36]
|
|
_T_779[14] <= _T_856 @[el2_lib.scala 344:30]
|
|
node _T_857 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 340:36]
|
|
_T_775[15] <= _T_857 @[el2_lib.scala 340:30]
|
|
node _T_858 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 345:36]
|
|
_T_780[0] <= _T_858 @[el2_lib.scala 345:30]
|
|
node _T_859 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 341:36]
|
|
_T_776[15] <= _T_859 @[el2_lib.scala 341:30]
|
|
node _T_860 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 345:36]
|
|
_T_780[1] <= _T_860 @[el2_lib.scala 345:30]
|
|
node _T_861 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 340:36]
|
|
_T_775[16] <= _T_861 @[el2_lib.scala 340:30]
|
|
node _T_862 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 341:36]
|
|
_T_776[16] <= _T_862 @[el2_lib.scala 341:30]
|
|
node _T_863 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 345:36]
|
|
_T_780[2] <= _T_863 @[el2_lib.scala 345:30]
|
|
node _T_864 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 342:36]
|
|
_T_777[15] <= _T_864 @[el2_lib.scala 342:30]
|
|
node _T_865 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 345:36]
|
|
_T_780[3] <= _T_865 @[el2_lib.scala 345:30]
|
|
node _T_866 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 340:36]
|
|
_T_775[17] <= _T_866 @[el2_lib.scala 340:30]
|
|
node _T_867 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 342:36]
|
|
_T_777[16] <= _T_867 @[el2_lib.scala 342:30]
|
|
node _T_868 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 345:36]
|
|
_T_780[4] <= _T_868 @[el2_lib.scala 345:30]
|
|
node _T_869 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 341:36]
|
|
_T_776[17] <= _T_869 @[el2_lib.scala 341:30]
|
|
node _T_870 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 342:36]
|
|
_T_777[17] <= _T_870 @[el2_lib.scala 342:30]
|
|
node _T_871 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 345:36]
|
|
_T_780[5] <= _T_871 @[el2_lib.scala 345:30]
|
|
node _T_872 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 340:36]
|
|
_T_775[18] <= _T_872 @[el2_lib.scala 340:30]
|
|
node _T_873 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 341:36]
|
|
_T_776[18] <= _T_873 @[el2_lib.scala 341:30]
|
|
node _T_874 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 342:36]
|
|
_T_777[18] <= _T_874 @[el2_lib.scala 342:30]
|
|
node _T_875 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 345:36]
|
|
_T_780[6] <= _T_875 @[el2_lib.scala 345:30]
|
|
node _T_876 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 343:36]
|
|
_T_778[15] <= _T_876 @[el2_lib.scala 343:30]
|
|
node _T_877 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 345:36]
|
|
_T_780[7] <= _T_877 @[el2_lib.scala 345:30]
|
|
node _T_878 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 340:36]
|
|
_T_775[19] <= _T_878 @[el2_lib.scala 340:30]
|
|
node _T_879 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 343:36]
|
|
_T_778[16] <= _T_879 @[el2_lib.scala 343:30]
|
|
node _T_880 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 345:36]
|
|
_T_780[8] <= _T_880 @[el2_lib.scala 345:30]
|
|
node _T_881 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 341:36]
|
|
_T_776[19] <= _T_881 @[el2_lib.scala 341:30]
|
|
node _T_882 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 343:36]
|
|
_T_778[17] <= _T_882 @[el2_lib.scala 343:30]
|
|
node _T_883 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 345:36]
|
|
_T_780[9] <= _T_883 @[el2_lib.scala 345:30]
|
|
node _T_884 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 340:36]
|
|
_T_775[20] <= _T_884 @[el2_lib.scala 340:30]
|
|
node _T_885 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 341:36]
|
|
_T_776[20] <= _T_885 @[el2_lib.scala 341:30]
|
|
node _T_886 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 343:36]
|
|
_T_778[18] <= _T_886 @[el2_lib.scala 343:30]
|
|
node _T_887 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 345:36]
|
|
_T_780[10] <= _T_887 @[el2_lib.scala 345:30]
|
|
node _T_888 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 342:36]
|
|
_T_777[19] <= _T_888 @[el2_lib.scala 342:30]
|
|
node _T_889 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 343:36]
|
|
_T_778[19] <= _T_889 @[el2_lib.scala 343:30]
|
|
node _T_890 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 345:36]
|
|
_T_780[11] <= _T_890 @[el2_lib.scala 345:30]
|
|
node _T_891 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 340:36]
|
|
_T_775[21] <= _T_891 @[el2_lib.scala 340:30]
|
|
node _T_892 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 342:36]
|
|
_T_777[20] <= _T_892 @[el2_lib.scala 342:30]
|
|
node _T_893 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 343:36]
|
|
_T_778[20] <= _T_893 @[el2_lib.scala 343:30]
|
|
node _T_894 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 345:36]
|
|
_T_780[12] <= _T_894 @[el2_lib.scala 345:30]
|
|
node _T_895 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 341:36]
|
|
_T_776[21] <= _T_895 @[el2_lib.scala 341:30]
|
|
node _T_896 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 342:36]
|
|
_T_777[21] <= _T_896 @[el2_lib.scala 342:30]
|
|
node _T_897 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 343:36]
|
|
_T_778[21] <= _T_897 @[el2_lib.scala 343:30]
|
|
node _T_898 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 345:36]
|
|
_T_780[13] <= _T_898 @[el2_lib.scala 345:30]
|
|
node _T_899 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 340:36]
|
|
_T_775[22] <= _T_899 @[el2_lib.scala 340:30]
|
|
node _T_900 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 341:36]
|
|
_T_776[22] <= _T_900 @[el2_lib.scala 341:30]
|
|
node _T_901 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 342:36]
|
|
_T_777[22] <= _T_901 @[el2_lib.scala 342:30]
|
|
node _T_902 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 343:36]
|
|
_T_778[22] <= _T_902 @[el2_lib.scala 343:30]
|
|
node _T_903 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 345:36]
|
|
_T_780[14] <= _T_903 @[el2_lib.scala 345:30]
|
|
node _T_904 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 344:36]
|
|
_T_779[15] <= _T_904 @[el2_lib.scala 344:30]
|
|
node _T_905 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 345:36]
|
|
_T_780[15] <= _T_905 @[el2_lib.scala 345:30]
|
|
node _T_906 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 340:36]
|
|
_T_775[23] <= _T_906 @[el2_lib.scala 340:30]
|
|
node _T_907 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 344:36]
|
|
_T_779[16] <= _T_907 @[el2_lib.scala 344:30]
|
|
node _T_908 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 345:36]
|
|
_T_780[16] <= _T_908 @[el2_lib.scala 345:30]
|
|
node _T_909 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 341:36]
|
|
_T_776[23] <= _T_909 @[el2_lib.scala 341:30]
|
|
node _T_910 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 344:36]
|
|
_T_779[17] <= _T_910 @[el2_lib.scala 344:30]
|
|
node _T_911 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 345:36]
|
|
_T_780[17] <= _T_911 @[el2_lib.scala 345:30]
|
|
node _T_912 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 340:36]
|
|
_T_775[24] <= _T_912 @[el2_lib.scala 340:30]
|
|
node _T_913 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 341:36]
|
|
_T_776[24] <= _T_913 @[el2_lib.scala 341:30]
|
|
node _T_914 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 344:36]
|
|
_T_779[18] <= _T_914 @[el2_lib.scala 344:30]
|
|
node _T_915 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 345:36]
|
|
_T_780[18] <= _T_915 @[el2_lib.scala 345:30]
|
|
node _T_916 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 342:36]
|
|
_T_777[23] <= _T_916 @[el2_lib.scala 342:30]
|
|
node _T_917 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 344:36]
|
|
_T_779[19] <= _T_917 @[el2_lib.scala 344:30]
|
|
node _T_918 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 345:36]
|
|
_T_780[19] <= _T_918 @[el2_lib.scala 345:30]
|
|
node _T_919 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 340:36]
|
|
_T_775[25] <= _T_919 @[el2_lib.scala 340:30]
|
|
node _T_920 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 342:36]
|
|
_T_777[24] <= _T_920 @[el2_lib.scala 342:30]
|
|
node _T_921 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 344:36]
|
|
_T_779[20] <= _T_921 @[el2_lib.scala 344:30]
|
|
node _T_922 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 345:36]
|
|
_T_780[20] <= _T_922 @[el2_lib.scala 345:30]
|
|
node _T_923 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 341:36]
|
|
_T_776[25] <= _T_923 @[el2_lib.scala 341:30]
|
|
node _T_924 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 342:36]
|
|
_T_777[25] <= _T_924 @[el2_lib.scala 342:30]
|
|
node _T_925 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 344:36]
|
|
_T_779[21] <= _T_925 @[el2_lib.scala 344:30]
|
|
node _T_926 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 345:36]
|
|
_T_780[21] <= _T_926 @[el2_lib.scala 345:30]
|
|
node _T_927 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 340:36]
|
|
_T_775[26] <= _T_927 @[el2_lib.scala 340:30]
|
|
node _T_928 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 341:36]
|
|
_T_776[26] <= _T_928 @[el2_lib.scala 341:30]
|
|
node _T_929 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 342:36]
|
|
_T_777[26] <= _T_929 @[el2_lib.scala 342:30]
|
|
node _T_930 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 344:36]
|
|
_T_779[22] <= _T_930 @[el2_lib.scala 344:30]
|
|
node _T_931 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 345:36]
|
|
_T_780[22] <= _T_931 @[el2_lib.scala 345:30]
|
|
node _T_932 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 343:36]
|
|
_T_778[23] <= _T_932 @[el2_lib.scala 343:30]
|
|
node _T_933 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 344:36]
|
|
_T_779[23] <= _T_933 @[el2_lib.scala 344:30]
|
|
node _T_934 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 345:36]
|
|
_T_780[23] <= _T_934 @[el2_lib.scala 345:30]
|
|
node _T_935 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 340:36]
|
|
_T_775[27] <= _T_935 @[el2_lib.scala 340:30]
|
|
node _T_936 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 343:36]
|
|
_T_778[24] <= _T_936 @[el2_lib.scala 343:30]
|
|
node _T_937 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 344:36]
|
|
_T_779[24] <= _T_937 @[el2_lib.scala 344:30]
|
|
node _T_938 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 345:36]
|
|
_T_780[24] <= _T_938 @[el2_lib.scala 345:30]
|
|
node _T_939 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 341:36]
|
|
_T_776[27] <= _T_939 @[el2_lib.scala 341:30]
|
|
node _T_940 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 343:36]
|
|
_T_778[25] <= _T_940 @[el2_lib.scala 343:30]
|
|
node _T_941 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 344:36]
|
|
_T_779[25] <= _T_941 @[el2_lib.scala 344:30]
|
|
node _T_942 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 345:36]
|
|
_T_780[25] <= _T_942 @[el2_lib.scala 345:30]
|
|
node _T_943 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 340:36]
|
|
_T_775[28] <= _T_943 @[el2_lib.scala 340:30]
|
|
node _T_944 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 341:36]
|
|
_T_776[28] <= _T_944 @[el2_lib.scala 341:30]
|
|
node _T_945 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 343:36]
|
|
_T_778[26] <= _T_945 @[el2_lib.scala 343:30]
|
|
node _T_946 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 344:36]
|
|
_T_779[26] <= _T_946 @[el2_lib.scala 344:30]
|
|
node _T_947 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 345:36]
|
|
_T_780[26] <= _T_947 @[el2_lib.scala 345:30]
|
|
node _T_948 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 342:36]
|
|
_T_777[27] <= _T_948 @[el2_lib.scala 342:30]
|
|
node _T_949 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 343:36]
|
|
_T_778[27] <= _T_949 @[el2_lib.scala 343:30]
|
|
node _T_950 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 344:36]
|
|
_T_779[27] <= _T_950 @[el2_lib.scala 344:30]
|
|
node _T_951 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 345:36]
|
|
_T_780[27] <= _T_951 @[el2_lib.scala 345:30]
|
|
node _T_952 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 340:36]
|
|
_T_775[29] <= _T_952 @[el2_lib.scala 340:30]
|
|
node _T_953 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 342:36]
|
|
_T_777[28] <= _T_953 @[el2_lib.scala 342:30]
|
|
node _T_954 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 343:36]
|
|
_T_778[28] <= _T_954 @[el2_lib.scala 343:30]
|
|
node _T_955 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 344:36]
|
|
_T_779[28] <= _T_955 @[el2_lib.scala 344:30]
|
|
node _T_956 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 345:36]
|
|
_T_780[28] <= _T_956 @[el2_lib.scala 345:30]
|
|
node _T_957 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 341:36]
|
|
_T_776[29] <= _T_957 @[el2_lib.scala 341:30]
|
|
node _T_958 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 342:36]
|
|
_T_777[29] <= _T_958 @[el2_lib.scala 342:30]
|
|
node _T_959 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 343:36]
|
|
_T_778[29] <= _T_959 @[el2_lib.scala 343:30]
|
|
node _T_960 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 344:36]
|
|
_T_779[29] <= _T_960 @[el2_lib.scala 344:30]
|
|
node _T_961 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 345:36]
|
|
_T_780[29] <= _T_961 @[el2_lib.scala 345:30]
|
|
node _T_962 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 340:36]
|
|
_T_775[30] <= _T_962 @[el2_lib.scala 340:30]
|
|
node _T_963 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 341:36]
|
|
_T_776[30] <= _T_963 @[el2_lib.scala 341:30]
|
|
node _T_964 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 342:36]
|
|
_T_777[30] <= _T_964 @[el2_lib.scala 342:30]
|
|
node _T_965 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 343:36]
|
|
_T_778[30] <= _T_965 @[el2_lib.scala 343:30]
|
|
node _T_966 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 344:36]
|
|
_T_779[30] <= _T_966 @[el2_lib.scala 344:30]
|
|
node _T_967 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 345:36]
|
|
_T_780[30] <= _T_967 @[el2_lib.scala 345:30]
|
|
node _T_968 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 340:36]
|
|
_T_775[31] <= _T_968 @[el2_lib.scala 340:30]
|
|
node _T_969 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 346:36]
|
|
_T_781[0] <= _T_969 @[el2_lib.scala 346:30]
|
|
node _T_970 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 341:36]
|
|
_T_776[31] <= _T_970 @[el2_lib.scala 341:30]
|
|
node _T_971 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 346:36]
|
|
_T_781[1] <= _T_971 @[el2_lib.scala 346:30]
|
|
node _T_972 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 340:36]
|
|
_T_775[32] <= _T_972 @[el2_lib.scala 340:30]
|
|
node _T_973 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 341:36]
|
|
_T_776[32] <= _T_973 @[el2_lib.scala 341:30]
|
|
node _T_974 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 346:36]
|
|
_T_781[2] <= _T_974 @[el2_lib.scala 346:30]
|
|
node _T_975 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 342:36]
|
|
_T_777[31] <= _T_975 @[el2_lib.scala 342:30]
|
|
node _T_976 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 346:36]
|
|
_T_781[3] <= _T_976 @[el2_lib.scala 346:30]
|
|
node _T_977 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 340:36]
|
|
_T_775[33] <= _T_977 @[el2_lib.scala 340:30]
|
|
node _T_978 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 342:36]
|
|
_T_777[32] <= _T_978 @[el2_lib.scala 342:30]
|
|
node _T_979 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 346:36]
|
|
_T_781[4] <= _T_979 @[el2_lib.scala 346:30]
|
|
node _T_980 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 341:36]
|
|
_T_776[33] <= _T_980 @[el2_lib.scala 341:30]
|
|
node _T_981 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 342:36]
|
|
_T_777[33] <= _T_981 @[el2_lib.scala 342:30]
|
|
node _T_982 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 346:36]
|
|
_T_781[5] <= _T_982 @[el2_lib.scala 346:30]
|
|
node _T_983 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 340:36]
|
|
_T_775[34] <= _T_983 @[el2_lib.scala 340:30]
|
|
node _T_984 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 341:36]
|
|
_T_776[34] <= _T_984 @[el2_lib.scala 341:30]
|
|
node _T_985 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 342:36]
|
|
_T_777[34] <= _T_985 @[el2_lib.scala 342:30]
|
|
node _T_986 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 346:36]
|
|
_T_781[6] <= _T_986 @[el2_lib.scala 346:30]
|
|
node _T_987 = cat(_T_775[1], _T_775[0]) @[el2_lib.scala 348:27]
|
|
node _T_988 = cat(_T_775[3], _T_775[2]) @[el2_lib.scala 348:27]
|
|
node _T_989 = cat(_T_988, _T_987) @[el2_lib.scala 348:27]
|
|
node _T_990 = cat(_T_775[5], _T_775[4]) @[el2_lib.scala 348:27]
|
|
node _T_991 = cat(_T_775[7], _T_775[6]) @[el2_lib.scala 348:27]
|
|
node _T_992 = cat(_T_991, _T_990) @[el2_lib.scala 348:27]
|
|
node _T_993 = cat(_T_992, _T_989) @[el2_lib.scala 348:27]
|
|
node _T_994 = cat(_T_775[9], _T_775[8]) @[el2_lib.scala 348:27]
|
|
node _T_995 = cat(_T_775[11], _T_775[10]) @[el2_lib.scala 348:27]
|
|
node _T_996 = cat(_T_995, _T_994) @[el2_lib.scala 348:27]
|
|
node _T_997 = cat(_T_775[13], _T_775[12]) @[el2_lib.scala 348:27]
|
|
node _T_998 = cat(_T_775[16], _T_775[15]) @[el2_lib.scala 348:27]
|
|
node _T_999 = cat(_T_998, _T_775[14]) @[el2_lib.scala 348:27]
|
|
node _T_1000 = cat(_T_999, _T_997) @[el2_lib.scala 348:27]
|
|
node _T_1001 = cat(_T_1000, _T_996) @[el2_lib.scala 348:27]
|
|
node _T_1002 = cat(_T_1001, _T_993) @[el2_lib.scala 348:27]
|
|
node _T_1003 = cat(_T_775[18], _T_775[17]) @[el2_lib.scala 348:27]
|
|
node _T_1004 = cat(_T_775[20], _T_775[19]) @[el2_lib.scala 348:27]
|
|
node _T_1005 = cat(_T_1004, _T_1003) @[el2_lib.scala 348:27]
|
|
node _T_1006 = cat(_T_775[22], _T_775[21]) @[el2_lib.scala 348:27]
|
|
node _T_1007 = cat(_T_775[25], _T_775[24]) @[el2_lib.scala 348:27]
|
|
node _T_1008 = cat(_T_1007, _T_775[23]) @[el2_lib.scala 348:27]
|
|
node _T_1009 = cat(_T_1008, _T_1006) @[el2_lib.scala 348:27]
|
|
node _T_1010 = cat(_T_1009, _T_1005) @[el2_lib.scala 348:27]
|
|
node _T_1011 = cat(_T_775[27], _T_775[26]) @[el2_lib.scala 348:27]
|
|
node _T_1012 = cat(_T_775[29], _T_775[28]) @[el2_lib.scala 348:27]
|
|
node _T_1013 = cat(_T_1012, _T_1011) @[el2_lib.scala 348:27]
|
|
node _T_1014 = cat(_T_775[31], _T_775[30]) @[el2_lib.scala 348:27]
|
|
node _T_1015 = cat(_T_775[34], _T_775[33]) @[el2_lib.scala 348:27]
|
|
node _T_1016 = cat(_T_1015, _T_775[32]) @[el2_lib.scala 348:27]
|
|
node _T_1017 = cat(_T_1016, _T_1014) @[el2_lib.scala 348:27]
|
|
node _T_1018 = cat(_T_1017, _T_1013) @[el2_lib.scala 348:27]
|
|
node _T_1019 = cat(_T_1018, _T_1010) @[el2_lib.scala 348:27]
|
|
node _T_1020 = cat(_T_1019, _T_1002) @[el2_lib.scala 348:27]
|
|
node _T_1021 = xorr(_T_1020) @[el2_lib.scala 348:34]
|
|
node _T_1022 = cat(_T_776[1], _T_776[0]) @[el2_lib.scala 348:44]
|
|
node _T_1023 = cat(_T_776[3], _T_776[2]) @[el2_lib.scala 348:44]
|
|
node _T_1024 = cat(_T_1023, _T_1022) @[el2_lib.scala 348:44]
|
|
node _T_1025 = cat(_T_776[5], _T_776[4]) @[el2_lib.scala 348:44]
|
|
node _T_1026 = cat(_T_776[7], _T_776[6]) @[el2_lib.scala 348:44]
|
|
node _T_1027 = cat(_T_1026, _T_1025) @[el2_lib.scala 348:44]
|
|
node _T_1028 = cat(_T_1027, _T_1024) @[el2_lib.scala 348:44]
|
|
node _T_1029 = cat(_T_776[9], _T_776[8]) @[el2_lib.scala 348:44]
|
|
node _T_1030 = cat(_T_776[11], _T_776[10]) @[el2_lib.scala 348:44]
|
|
node _T_1031 = cat(_T_1030, _T_1029) @[el2_lib.scala 348:44]
|
|
node _T_1032 = cat(_T_776[13], _T_776[12]) @[el2_lib.scala 348:44]
|
|
node _T_1033 = cat(_T_776[16], _T_776[15]) @[el2_lib.scala 348:44]
|
|
node _T_1034 = cat(_T_1033, _T_776[14]) @[el2_lib.scala 348:44]
|
|
node _T_1035 = cat(_T_1034, _T_1032) @[el2_lib.scala 348:44]
|
|
node _T_1036 = cat(_T_1035, _T_1031) @[el2_lib.scala 348:44]
|
|
node _T_1037 = cat(_T_1036, _T_1028) @[el2_lib.scala 348:44]
|
|
node _T_1038 = cat(_T_776[18], _T_776[17]) @[el2_lib.scala 348:44]
|
|
node _T_1039 = cat(_T_776[20], _T_776[19]) @[el2_lib.scala 348:44]
|
|
node _T_1040 = cat(_T_1039, _T_1038) @[el2_lib.scala 348:44]
|
|
node _T_1041 = cat(_T_776[22], _T_776[21]) @[el2_lib.scala 348:44]
|
|
node _T_1042 = cat(_T_776[25], _T_776[24]) @[el2_lib.scala 348:44]
|
|
node _T_1043 = cat(_T_1042, _T_776[23]) @[el2_lib.scala 348:44]
|
|
node _T_1044 = cat(_T_1043, _T_1041) @[el2_lib.scala 348:44]
|
|
node _T_1045 = cat(_T_1044, _T_1040) @[el2_lib.scala 348:44]
|
|
node _T_1046 = cat(_T_776[27], _T_776[26]) @[el2_lib.scala 348:44]
|
|
node _T_1047 = cat(_T_776[29], _T_776[28]) @[el2_lib.scala 348:44]
|
|
node _T_1048 = cat(_T_1047, _T_1046) @[el2_lib.scala 348:44]
|
|
node _T_1049 = cat(_T_776[31], _T_776[30]) @[el2_lib.scala 348:44]
|
|
node _T_1050 = cat(_T_776[34], _T_776[33]) @[el2_lib.scala 348:44]
|
|
node _T_1051 = cat(_T_1050, _T_776[32]) @[el2_lib.scala 348:44]
|
|
node _T_1052 = cat(_T_1051, _T_1049) @[el2_lib.scala 348:44]
|
|
node _T_1053 = cat(_T_1052, _T_1048) @[el2_lib.scala 348:44]
|
|
node _T_1054 = cat(_T_1053, _T_1045) @[el2_lib.scala 348:44]
|
|
node _T_1055 = cat(_T_1054, _T_1037) @[el2_lib.scala 348:44]
|
|
node _T_1056 = xorr(_T_1055) @[el2_lib.scala 348:51]
|
|
node _T_1057 = cat(_T_777[1], _T_777[0]) @[el2_lib.scala 348:61]
|
|
node _T_1058 = cat(_T_777[3], _T_777[2]) @[el2_lib.scala 348:61]
|
|
node _T_1059 = cat(_T_1058, _T_1057) @[el2_lib.scala 348:61]
|
|
node _T_1060 = cat(_T_777[5], _T_777[4]) @[el2_lib.scala 348:61]
|
|
node _T_1061 = cat(_T_777[7], _T_777[6]) @[el2_lib.scala 348:61]
|
|
node _T_1062 = cat(_T_1061, _T_1060) @[el2_lib.scala 348:61]
|
|
node _T_1063 = cat(_T_1062, _T_1059) @[el2_lib.scala 348:61]
|
|
node _T_1064 = cat(_T_777[9], _T_777[8]) @[el2_lib.scala 348:61]
|
|
node _T_1065 = cat(_T_777[11], _T_777[10]) @[el2_lib.scala 348:61]
|
|
node _T_1066 = cat(_T_1065, _T_1064) @[el2_lib.scala 348:61]
|
|
node _T_1067 = cat(_T_777[13], _T_777[12]) @[el2_lib.scala 348:61]
|
|
node _T_1068 = cat(_T_777[16], _T_777[15]) @[el2_lib.scala 348:61]
|
|
node _T_1069 = cat(_T_1068, _T_777[14]) @[el2_lib.scala 348:61]
|
|
node _T_1070 = cat(_T_1069, _T_1067) @[el2_lib.scala 348:61]
|
|
node _T_1071 = cat(_T_1070, _T_1066) @[el2_lib.scala 348:61]
|
|
node _T_1072 = cat(_T_1071, _T_1063) @[el2_lib.scala 348:61]
|
|
node _T_1073 = cat(_T_777[18], _T_777[17]) @[el2_lib.scala 348:61]
|
|
node _T_1074 = cat(_T_777[20], _T_777[19]) @[el2_lib.scala 348:61]
|
|
node _T_1075 = cat(_T_1074, _T_1073) @[el2_lib.scala 348:61]
|
|
node _T_1076 = cat(_T_777[22], _T_777[21]) @[el2_lib.scala 348:61]
|
|
node _T_1077 = cat(_T_777[25], _T_777[24]) @[el2_lib.scala 348:61]
|
|
node _T_1078 = cat(_T_1077, _T_777[23]) @[el2_lib.scala 348:61]
|
|
node _T_1079 = cat(_T_1078, _T_1076) @[el2_lib.scala 348:61]
|
|
node _T_1080 = cat(_T_1079, _T_1075) @[el2_lib.scala 348:61]
|
|
node _T_1081 = cat(_T_777[27], _T_777[26]) @[el2_lib.scala 348:61]
|
|
node _T_1082 = cat(_T_777[29], _T_777[28]) @[el2_lib.scala 348:61]
|
|
node _T_1083 = cat(_T_1082, _T_1081) @[el2_lib.scala 348:61]
|
|
node _T_1084 = cat(_T_777[31], _T_777[30]) @[el2_lib.scala 348:61]
|
|
node _T_1085 = cat(_T_777[34], _T_777[33]) @[el2_lib.scala 348:61]
|
|
node _T_1086 = cat(_T_1085, _T_777[32]) @[el2_lib.scala 348:61]
|
|
node _T_1087 = cat(_T_1086, _T_1084) @[el2_lib.scala 348:61]
|
|
node _T_1088 = cat(_T_1087, _T_1083) @[el2_lib.scala 348:61]
|
|
node _T_1089 = cat(_T_1088, _T_1080) @[el2_lib.scala 348:61]
|
|
node _T_1090 = cat(_T_1089, _T_1072) @[el2_lib.scala 348:61]
|
|
node _T_1091 = xorr(_T_1090) @[el2_lib.scala 348:68]
|
|
node _T_1092 = cat(_T_778[2], _T_778[1]) @[el2_lib.scala 348:78]
|
|
node _T_1093 = cat(_T_1092, _T_778[0]) @[el2_lib.scala 348:78]
|
|
node _T_1094 = cat(_T_778[4], _T_778[3]) @[el2_lib.scala 348:78]
|
|
node _T_1095 = cat(_T_778[6], _T_778[5]) @[el2_lib.scala 348:78]
|
|
node _T_1096 = cat(_T_1095, _T_1094) @[el2_lib.scala 348:78]
|
|
node _T_1097 = cat(_T_1096, _T_1093) @[el2_lib.scala 348:78]
|
|
node _T_1098 = cat(_T_778[8], _T_778[7]) @[el2_lib.scala 348:78]
|
|
node _T_1099 = cat(_T_778[10], _T_778[9]) @[el2_lib.scala 348:78]
|
|
node _T_1100 = cat(_T_1099, _T_1098) @[el2_lib.scala 348:78]
|
|
node _T_1101 = cat(_T_778[12], _T_778[11]) @[el2_lib.scala 348:78]
|
|
node _T_1102 = cat(_T_778[14], _T_778[13]) @[el2_lib.scala 348:78]
|
|
node _T_1103 = cat(_T_1102, _T_1101) @[el2_lib.scala 348:78]
|
|
node _T_1104 = cat(_T_1103, _T_1100) @[el2_lib.scala 348:78]
|
|
node _T_1105 = cat(_T_1104, _T_1097) @[el2_lib.scala 348:78]
|
|
node _T_1106 = cat(_T_778[16], _T_778[15]) @[el2_lib.scala 348:78]
|
|
node _T_1107 = cat(_T_778[18], _T_778[17]) @[el2_lib.scala 348:78]
|
|
node _T_1108 = cat(_T_1107, _T_1106) @[el2_lib.scala 348:78]
|
|
node _T_1109 = cat(_T_778[20], _T_778[19]) @[el2_lib.scala 348:78]
|
|
node _T_1110 = cat(_T_778[22], _T_778[21]) @[el2_lib.scala 348:78]
|
|
node _T_1111 = cat(_T_1110, _T_1109) @[el2_lib.scala 348:78]
|
|
node _T_1112 = cat(_T_1111, _T_1108) @[el2_lib.scala 348:78]
|
|
node _T_1113 = cat(_T_778[24], _T_778[23]) @[el2_lib.scala 348:78]
|
|
node _T_1114 = cat(_T_778[26], _T_778[25]) @[el2_lib.scala 348:78]
|
|
node _T_1115 = cat(_T_1114, _T_1113) @[el2_lib.scala 348:78]
|
|
node _T_1116 = cat(_T_778[28], _T_778[27]) @[el2_lib.scala 348:78]
|
|
node _T_1117 = cat(_T_778[30], _T_778[29]) @[el2_lib.scala 348:78]
|
|
node _T_1118 = cat(_T_1117, _T_1116) @[el2_lib.scala 348:78]
|
|
node _T_1119 = cat(_T_1118, _T_1115) @[el2_lib.scala 348:78]
|
|
node _T_1120 = cat(_T_1119, _T_1112) @[el2_lib.scala 348:78]
|
|
node _T_1121 = cat(_T_1120, _T_1105) @[el2_lib.scala 348:78]
|
|
node _T_1122 = xorr(_T_1121) @[el2_lib.scala 348:85]
|
|
node _T_1123 = cat(_T_779[2], _T_779[1]) @[el2_lib.scala 348:95]
|
|
node _T_1124 = cat(_T_1123, _T_779[0]) @[el2_lib.scala 348:95]
|
|
node _T_1125 = cat(_T_779[4], _T_779[3]) @[el2_lib.scala 348:95]
|
|
node _T_1126 = cat(_T_779[6], _T_779[5]) @[el2_lib.scala 348:95]
|
|
node _T_1127 = cat(_T_1126, _T_1125) @[el2_lib.scala 348:95]
|
|
node _T_1128 = cat(_T_1127, _T_1124) @[el2_lib.scala 348:95]
|
|
node _T_1129 = cat(_T_779[8], _T_779[7]) @[el2_lib.scala 348:95]
|
|
node _T_1130 = cat(_T_779[10], _T_779[9]) @[el2_lib.scala 348:95]
|
|
node _T_1131 = cat(_T_1130, _T_1129) @[el2_lib.scala 348:95]
|
|
node _T_1132 = cat(_T_779[12], _T_779[11]) @[el2_lib.scala 348:95]
|
|
node _T_1133 = cat(_T_779[14], _T_779[13]) @[el2_lib.scala 348:95]
|
|
node _T_1134 = cat(_T_1133, _T_1132) @[el2_lib.scala 348:95]
|
|
node _T_1135 = cat(_T_1134, _T_1131) @[el2_lib.scala 348:95]
|
|
node _T_1136 = cat(_T_1135, _T_1128) @[el2_lib.scala 348:95]
|
|
node _T_1137 = cat(_T_779[16], _T_779[15]) @[el2_lib.scala 348:95]
|
|
node _T_1138 = cat(_T_779[18], _T_779[17]) @[el2_lib.scala 348:95]
|
|
node _T_1139 = cat(_T_1138, _T_1137) @[el2_lib.scala 348:95]
|
|
node _T_1140 = cat(_T_779[20], _T_779[19]) @[el2_lib.scala 348:95]
|
|
node _T_1141 = cat(_T_779[22], _T_779[21]) @[el2_lib.scala 348:95]
|
|
node _T_1142 = cat(_T_1141, _T_1140) @[el2_lib.scala 348:95]
|
|
node _T_1143 = cat(_T_1142, _T_1139) @[el2_lib.scala 348:95]
|
|
node _T_1144 = cat(_T_779[24], _T_779[23]) @[el2_lib.scala 348:95]
|
|
node _T_1145 = cat(_T_779[26], _T_779[25]) @[el2_lib.scala 348:95]
|
|
node _T_1146 = cat(_T_1145, _T_1144) @[el2_lib.scala 348:95]
|
|
node _T_1147 = cat(_T_779[28], _T_779[27]) @[el2_lib.scala 348:95]
|
|
node _T_1148 = cat(_T_779[30], _T_779[29]) @[el2_lib.scala 348:95]
|
|
node _T_1149 = cat(_T_1148, _T_1147) @[el2_lib.scala 348:95]
|
|
node _T_1150 = cat(_T_1149, _T_1146) @[el2_lib.scala 348:95]
|
|
node _T_1151 = cat(_T_1150, _T_1143) @[el2_lib.scala 348:95]
|
|
node _T_1152 = cat(_T_1151, _T_1136) @[el2_lib.scala 348:95]
|
|
node _T_1153 = xorr(_T_1152) @[el2_lib.scala 348:102]
|
|
node _T_1154 = cat(_T_780[2], _T_780[1]) @[el2_lib.scala 348:112]
|
|
node _T_1155 = cat(_T_1154, _T_780[0]) @[el2_lib.scala 348:112]
|
|
node _T_1156 = cat(_T_780[4], _T_780[3]) @[el2_lib.scala 348:112]
|
|
node _T_1157 = cat(_T_780[6], _T_780[5]) @[el2_lib.scala 348:112]
|
|
node _T_1158 = cat(_T_1157, _T_1156) @[el2_lib.scala 348:112]
|
|
node _T_1159 = cat(_T_1158, _T_1155) @[el2_lib.scala 348:112]
|
|
node _T_1160 = cat(_T_780[8], _T_780[7]) @[el2_lib.scala 348:112]
|
|
node _T_1161 = cat(_T_780[10], _T_780[9]) @[el2_lib.scala 348:112]
|
|
node _T_1162 = cat(_T_1161, _T_1160) @[el2_lib.scala 348:112]
|
|
node _T_1163 = cat(_T_780[12], _T_780[11]) @[el2_lib.scala 348:112]
|
|
node _T_1164 = cat(_T_780[14], _T_780[13]) @[el2_lib.scala 348:112]
|
|
node _T_1165 = cat(_T_1164, _T_1163) @[el2_lib.scala 348:112]
|
|
node _T_1166 = cat(_T_1165, _T_1162) @[el2_lib.scala 348:112]
|
|
node _T_1167 = cat(_T_1166, _T_1159) @[el2_lib.scala 348:112]
|
|
node _T_1168 = cat(_T_780[16], _T_780[15]) @[el2_lib.scala 348:112]
|
|
node _T_1169 = cat(_T_780[18], _T_780[17]) @[el2_lib.scala 348:112]
|
|
node _T_1170 = cat(_T_1169, _T_1168) @[el2_lib.scala 348:112]
|
|
node _T_1171 = cat(_T_780[20], _T_780[19]) @[el2_lib.scala 348:112]
|
|
node _T_1172 = cat(_T_780[22], _T_780[21]) @[el2_lib.scala 348:112]
|
|
node _T_1173 = cat(_T_1172, _T_1171) @[el2_lib.scala 348:112]
|
|
node _T_1174 = cat(_T_1173, _T_1170) @[el2_lib.scala 348:112]
|
|
node _T_1175 = cat(_T_780[24], _T_780[23]) @[el2_lib.scala 348:112]
|
|
node _T_1176 = cat(_T_780[26], _T_780[25]) @[el2_lib.scala 348:112]
|
|
node _T_1177 = cat(_T_1176, _T_1175) @[el2_lib.scala 348:112]
|
|
node _T_1178 = cat(_T_780[28], _T_780[27]) @[el2_lib.scala 348:112]
|
|
node _T_1179 = cat(_T_780[30], _T_780[29]) @[el2_lib.scala 348:112]
|
|
node _T_1180 = cat(_T_1179, _T_1178) @[el2_lib.scala 348:112]
|
|
node _T_1181 = cat(_T_1180, _T_1177) @[el2_lib.scala 348:112]
|
|
node _T_1182 = cat(_T_1181, _T_1174) @[el2_lib.scala 348:112]
|
|
node _T_1183 = cat(_T_1182, _T_1167) @[el2_lib.scala 348:112]
|
|
node _T_1184 = xorr(_T_1183) @[el2_lib.scala 348:119]
|
|
node _T_1185 = cat(_T_781[2], _T_781[1]) @[el2_lib.scala 348:129]
|
|
node _T_1186 = cat(_T_1185, _T_781[0]) @[el2_lib.scala 348:129]
|
|
node _T_1187 = cat(_T_781[4], _T_781[3]) @[el2_lib.scala 348:129]
|
|
node _T_1188 = cat(_T_781[6], _T_781[5]) @[el2_lib.scala 348:129]
|
|
node _T_1189 = cat(_T_1188, _T_1187) @[el2_lib.scala 348:129]
|
|
node _T_1190 = cat(_T_1189, _T_1186) @[el2_lib.scala 348:129]
|
|
node _T_1191 = xorr(_T_1190) @[el2_lib.scala 348:136]
|
|
node _T_1192 = cat(_T_1153, _T_1184) @[Cat.scala 29:58]
|
|
node _T_1193 = cat(_T_1192, _T_1191) @[Cat.scala 29:58]
|
|
node _T_1194 = cat(_T_1091, _T_1122) @[Cat.scala 29:58]
|
|
node _T_1195 = cat(_T_1021, _T_1056) @[Cat.scala 29:58]
|
|
node _T_1196 = cat(_T_1195, _T_1194) @[Cat.scala 29:58]
|
|
node ic_miss_buff_ecc = cat(_T_1196, _T_1193) @[Cat.scala 29:58]
|
|
wire ic_wr_16bytes_data : UInt<142>
|
|
ic_wr_16bytes_data <= UInt<1>("h00")
|
|
node _T_1197 = bits(ic_wr_16bytes_data, 70, 0) @[el2_ifu_mem_ctl.scala 339:72]
|
|
node _T_1198 = bits(ic_wr_16bytes_data, 141, 71) @[el2_ifu_mem_ctl.scala 339:72]
|
|
io.ic_wr_data[0] <= _T_1197 @[el2_ifu_mem_ctl.scala 339:17]
|
|
io.ic_wr_data[1] <= _T_1198 @[el2_ifu_mem_ctl.scala 339:17]
|
|
io.ic_debug_wr_data <= io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_ifu_mem_ctl.scala 340:23]
|
|
wire ic_rd_parity_final_err : UInt<1>
|
|
ic_rd_parity_final_err <= UInt<1>("h00")
|
|
node _T_1199 = orr(io.ic_eccerr) @[el2_ifu_mem_ctl.scala 342:56]
|
|
node _T_1200 = and(_T_1199, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 342:83]
|
|
node _T_1201 = or(_T_1200, ic_rd_parity_final_err) @[el2_ifu_mem_ctl.scala 342:99]
|
|
io.ic_error_start <= _T_1201 @[el2_ifu_mem_ctl.scala 342:21]
|
|
wire ic_debug_tag_val_rd_out : UInt<1>
|
|
ic_debug_tag_val_rd_out <= UInt<1>("h00")
|
|
wire ic_debug_ict_array_sel_ff : UInt<1>
|
|
ic_debug_ict_array_sel_ff <= UInt<1>("h00")
|
|
node _T_1202 = bits(ic_debug_ict_array_sel_ff, 0, 0) @[el2_ifu_mem_ctl.scala 345:63]
|
|
node _T_1203 = bits(io.ictag_debug_rd_data, 25, 21) @[el2_ifu_mem_ctl.scala 345:121]
|
|
node _T_1204 = bits(io.ictag_debug_rd_data, 20, 0) @[el2_ifu_mem_ctl.scala 345:161]
|
|
node _T_1205 = cat(UInt<3>("h00"), ic_debug_tag_val_rd_out) @[Cat.scala 29:58]
|
|
node _T_1206 = cat(UInt<1>("h00"), way_status) @[Cat.scala 29:58]
|
|
node _T_1207 = cat(_T_1206, _T_1205) @[Cat.scala 29:58]
|
|
node _T_1208 = cat(UInt<32>("h00"), _T_1204) @[Cat.scala 29:58]
|
|
node _T_1209 = cat(UInt<2>("h00"), _T_1203) @[Cat.scala 29:58]
|
|
node _T_1210 = cat(_T_1209, _T_1208) @[Cat.scala 29:58]
|
|
node _T_1211 = cat(_T_1210, _T_1207) @[Cat.scala 29:58]
|
|
node ifu_ic_debug_rd_data_in = mux(_T_1202, _T_1211, io.ic_debug_rd_data) @[el2_ifu_mem_ctl.scala 345:36]
|
|
reg _T_1212 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 348:37]
|
|
_T_1212 <= ifu_ic_debug_rd_data_in @[el2_ifu_mem_ctl.scala 348:37]
|
|
io.ifu_ic_debug_rd_data <= _T_1212 @[el2_ifu_mem_ctl.scala 348:27]
|
|
node _T_1213 = bits(ifu_bus_rdata_ff, 15, 0) @[el2_ifu_mem_ctl.scala 349:74]
|
|
node _T_1214 = xorr(_T_1213) @[el2_lib.scala 208:13]
|
|
node _T_1215 = bits(ifu_bus_rdata_ff, 31, 16) @[el2_ifu_mem_ctl.scala 349:74]
|
|
node _T_1216 = xorr(_T_1215) @[el2_lib.scala 208:13]
|
|
node _T_1217 = bits(ifu_bus_rdata_ff, 47, 32) @[el2_ifu_mem_ctl.scala 349:74]
|
|
node _T_1218 = xorr(_T_1217) @[el2_lib.scala 208:13]
|
|
node _T_1219 = bits(ifu_bus_rdata_ff, 63, 48) @[el2_ifu_mem_ctl.scala 349:74]
|
|
node _T_1220 = xorr(_T_1219) @[el2_lib.scala 208:13]
|
|
node _T_1221 = cat(_T_1220, _T_1218) @[Cat.scala 29:58]
|
|
node _T_1222 = cat(_T_1221, _T_1216) @[Cat.scala 29:58]
|
|
node ic_wr_parity = cat(_T_1222, _T_1214) @[Cat.scala 29:58]
|
|
node _T_1223 = bits(ic_miss_buff_half, 15, 0) @[el2_ifu_mem_ctl.scala 350:82]
|
|
node _T_1224 = xorr(_T_1223) @[el2_lib.scala 208:13]
|
|
node _T_1225 = bits(ic_miss_buff_half, 31, 16) @[el2_ifu_mem_ctl.scala 350:82]
|
|
node _T_1226 = xorr(_T_1225) @[el2_lib.scala 208:13]
|
|
node _T_1227 = bits(ic_miss_buff_half, 47, 32) @[el2_ifu_mem_ctl.scala 350:82]
|
|
node _T_1228 = xorr(_T_1227) @[el2_lib.scala 208:13]
|
|
node _T_1229 = bits(ic_miss_buff_half, 63, 48) @[el2_ifu_mem_ctl.scala 350:82]
|
|
node _T_1230 = xorr(_T_1229) @[el2_lib.scala 208:13]
|
|
node _T_1231 = cat(_T_1230, _T_1228) @[Cat.scala 29:58]
|
|
node _T_1232 = cat(_T_1231, _T_1226) @[Cat.scala 29:58]
|
|
node ic_miss_buff_parity = cat(_T_1232, _T_1224) @[Cat.scala 29:58]
|
|
node _T_1233 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 352:43]
|
|
node _T_1234 = bits(_T_1233, 0, 0) @[el2_ifu_mem_ctl.scala 352:47]
|
|
node _T_1235 = bits(ifu_bus_rdata_ff, 63, 0) @[el2_ifu_mem_ctl.scala 352:117]
|
|
node _T_1236 = bits(ic_miss_buff_half, 63, 0) @[el2_ifu_mem_ctl.scala 352:201]
|
|
node _T_1237 = cat(ic_miss_buff_ecc, _T_1236) @[Cat.scala 29:58]
|
|
node _T_1238 = cat(ic_wr_ecc, _T_1235) @[Cat.scala 29:58]
|
|
node _T_1239 = cat(_T_1238, _T_1237) @[Cat.scala 29:58]
|
|
node _T_1240 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58]
|
|
node _T_1241 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58]
|
|
node _T_1242 = cat(_T_1241, _T_1240) @[Cat.scala 29:58]
|
|
node _T_1243 = mux(_T_1234, _T_1239, _T_1242) @[el2_ifu_mem_ctl.scala 352:28]
|
|
ic_wr_16bytes_data <= _T_1243 @[el2_ifu_mem_ctl.scala 352:22]
|
|
wire bus_ifu_wr_data_error_ff : UInt<1>
|
|
bus_ifu_wr_data_error_ff <= UInt<1>("h00")
|
|
wire ifu_wr_data_comb_err_ff : UInt<1>
|
|
ifu_wr_data_comb_err_ff <= UInt<1>("h00")
|
|
wire reset_beat_cnt : UInt<1>
|
|
reset_beat_cnt <= UInt<1>("h00")
|
|
node _T_1244 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 358:53]
|
|
node _T_1245 = eq(reset_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 358:82]
|
|
node ifu_wr_cumulative_err = and(_T_1244, _T_1245) @[el2_ifu_mem_ctl.scala 358:80]
|
|
node _T_1246 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 359:55]
|
|
ifu_wr_cumulative_err_data <= _T_1246 @[el2_ifu_mem_ctl.scala 359:30]
|
|
reg _T_1247 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 360:61]
|
|
_T_1247 <= ifu_wr_cumulative_err @[el2_ifu_mem_ctl.scala 360:61]
|
|
ifu_wr_data_comb_err_ff <= _T_1247 @[el2_ifu_mem_ctl.scala 360:27]
|
|
wire ic_crit_wd_rdy : UInt<1>
|
|
ic_crit_wd_rdy <= UInt<1>("h00")
|
|
wire ifu_byp_data_err_new : UInt<1>
|
|
ifu_byp_data_err_new <= UInt<1>("h00")
|
|
node _T_1248 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 363:51]
|
|
node _T_1249 = or(ic_crit_wd_rdy, _T_1248) @[el2_ifu_mem_ctl.scala 363:38]
|
|
node _T_1250 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 363:77]
|
|
node _T_1251 = or(_T_1249, _T_1250) @[el2_ifu_mem_ctl.scala 363:64]
|
|
node _T_1252 = eq(ifu_byp_data_err_new, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 363:98]
|
|
node sel_byp_data = and(_T_1251, _T_1252) @[el2_ifu_mem_ctl.scala 363:96]
|
|
node _T_1253 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 364:51]
|
|
node _T_1254 = or(ic_crit_wd_rdy, _T_1253) @[el2_ifu_mem_ctl.scala 364:38]
|
|
node _T_1255 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 364:77]
|
|
node _T_1256 = or(_T_1254, _T_1255) @[el2_ifu_mem_ctl.scala 364:64]
|
|
node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 364:21]
|
|
node _T_1258 = eq(fetch_req_iccm_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 364:98]
|
|
node sel_ic_data = and(_T_1257, _T_1258) @[el2_ifu_mem_ctl.scala 364:96]
|
|
wire ic_byp_data_only_new : UInt<80>
|
|
ic_byp_data_only_new <= UInt<1>("h00")
|
|
node _T_1259 = or(fetch_req_iccm_f, sel_ic_data) @[el2_ifu_mem_ctl.scala 368:81]
|
|
node _T_1260 = or(sel_byp_data, _T_1259) @[el2_ifu_mem_ctl.scala 368:47]
|
|
node _T_1261 = bits(_T_1260, 0, 0) @[el2_ifu_mem_ctl.scala 368:140]
|
|
node _T_1262 = bits(fetch_req_iccm_f, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1263 = mux(_T_1262, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1264 = and(_T_1263, io.iccm_rd_data) @[el2_ifu_mem_ctl.scala 370:64]
|
|
node _T_1265 = bits(sel_byp_data, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1266 = mux(_T_1265, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1267 = and(_T_1266, ic_byp_data_only_new) @[el2_ifu_mem_ctl.scala 370:109]
|
|
node ic_premux_data = or(_T_1264, _T_1267) @[el2_ifu_mem_ctl.scala 370:83]
|
|
node ic_sel_premux_data = or(fetch_req_iccm_f, sel_byp_data) @[el2_ifu_mem_ctl.scala 372:58]
|
|
io.ic_premux_data <= ic_premux_data @[el2_ifu_mem_ctl.scala 373:21]
|
|
io.ic_sel_premux_data <= ic_sel_premux_data @[el2_ifu_mem_ctl.scala 374:25]
|
|
node ifc_bus_acc_fault_f = and(ic_byp_hit_f, ifu_byp_data_err_new) @[el2_ifu_mem_ctl.scala 375:42]
|
|
io.ic_data_f <= io.ic_rd_data @[el2_ifu_mem_ctl.scala 376:16]
|
|
node _T_1268 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 377:40]
|
|
node fetch_req_f_qual = and(io.ic_hit_f, _T_1268) @[el2_ifu_mem_ctl.scala 377:38]
|
|
wire ifc_region_acc_fault_memory_f : UInt<1>
|
|
ifc_region_acc_fault_memory_f <= UInt<1>("h00")
|
|
node _T_1269 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 379:57]
|
|
node _T_1270 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 379:82]
|
|
node _T_1271 = and(_T_1269, _T_1270) @[el2_ifu_mem_ctl.scala 379:80]
|
|
io.ic_access_fault_f <= _T_1271 @[el2_ifu_mem_ctl.scala 379:24]
|
|
node _T_1272 = bits(io.iccm_rd_ecc_double_err, 0, 0) @[el2_ifu_mem_ctl.scala 380:62]
|
|
node _T_1273 = bits(ifc_region_acc_fault_f, 0, 0) @[el2_ifu_mem_ctl.scala 381:32]
|
|
node _T_1274 = bits(ifc_region_acc_fault_memory_f, 0, 0) @[el2_ifu_mem_ctl.scala 382:47]
|
|
node _T_1275 = mux(_T_1274, UInt<2>("h03"), UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 382:10]
|
|
node _T_1276 = mux(_T_1273, UInt<2>("h02"), _T_1275) @[el2_ifu_mem_ctl.scala 381:8]
|
|
node _T_1277 = mux(_T_1272, UInt<1>("h01"), _T_1276) @[el2_ifu_mem_ctl.scala 380:35]
|
|
io.ic_access_fault_type_f <= _T_1277 @[el2_ifu_mem_ctl.scala 380:29]
|
|
wire ifu_bp_inst_mask_f : UInt<1>
|
|
ifu_bp_inst_mask_f <= UInt<1>("h00")
|
|
node _T_1278 = and(fetch_req_f_qual, ifu_bp_inst_mask_f) @[el2_ifu_mem_ctl.scala 384:45]
|
|
node _T_1279 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1280 = eq(ifu_fetch_addr_int_f, _T_1279) @[el2_ifu_mem_ctl.scala 384:77]
|
|
node _T_1281 = eq(_T_1280, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 384:68]
|
|
node _T_1282 = and(_T_1278, _T_1281) @[el2_ifu_mem_ctl.scala 384:66]
|
|
node _T_1283 = neq(err_stop_state, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 384:128]
|
|
node _T_1284 = and(_T_1282, _T_1283) @[el2_ifu_mem_ctl.scala 384:111]
|
|
node _T_1285 = cat(_T_1284, fetch_req_f_qual) @[Cat.scala 29:58]
|
|
io.ic_fetch_val_f <= _T_1285 @[el2_ifu_mem_ctl.scala 384:21]
|
|
node _T_1286 = bits(io.ic_data_f, 1, 0) @[el2_ifu_mem_ctl.scala 385:36]
|
|
node two_byte_instr = neq(_T_1286, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 385:42]
|
|
wire ic_miss_buff_data_in : UInt<64>
|
|
ic_miss_buff_data_in <= UInt<1>("h00")
|
|
wire ifu_bus_rsp_tag : UInt<3>
|
|
ifu_bus_rsp_tag <= UInt<1>("h00")
|
|
wire bus_ifu_wr_en : UInt<1>
|
|
bus_ifu_wr_en <= UInt<1>("h00")
|
|
node _T_1287 = eq(ifu_bus_rsp_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 391:91]
|
|
node write_fill_data_0 = and(bus_ifu_wr_en, _T_1287) @[el2_ifu_mem_ctl.scala 391:73]
|
|
node _T_1288 = eq(ifu_bus_rsp_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 391:91]
|
|
node write_fill_data_1 = and(bus_ifu_wr_en, _T_1288) @[el2_ifu_mem_ctl.scala 391:73]
|
|
node _T_1289 = eq(ifu_bus_rsp_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 391:91]
|
|
node write_fill_data_2 = and(bus_ifu_wr_en, _T_1289) @[el2_ifu_mem_ctl.scala 391:73]
|
|
node _T_1290 = eq(ifu_bus_rsp_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 391:91]
|
|
node write_fill_data_3 = and(bus_ifu_wr_en, _T_1290) @[el2_ifu_mem_ctl.scala 391:73]
|
|
node _T_1291 = eq(ifu_bus_rsp_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 391:91]
|
|
node write_fill_data_4 = and(bus_ifu_wr_en, _T_1291) @[el2_ifu_mem_ctl.scala 391:73]
|
|
node _T_1292 = eq(ifu_bus_rsp_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 391:91]
|
|
node write_fill_data_5 = and(bus_ifu_wr_en, _T_1292) @[el2_ifu_mem_ctl.scala 391:73]
|
|
node _T_1293 = eq(ifu_bus_rsp_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 391:91]
|
|
node write_fill_data_6 = and(bus_ifu_wr_en, _T_1293) @[el2_ifu_mem_ctl.scala 391:73]
|
|
node _T_1294 = eq(ifu_bus_rsp_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 391:91]
|
|
node write_fill_data_7 = and(bus_ifu_wr_en, _T_1294) @[el2_ifu_mem_ctl.scala 391:73]
|
|
wire ic_miss_buff_data : UInt<32>[16] @[el2_ifu_mem_ctl.scala 392:31]
|
|
node _T_1295 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 394:91]
|
|
reg _T_1296 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1295 : @[Reg.scala 28:19]
|
|
_T_1296 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[0] <= _T_1296 @[el2_ifu_mem_ctl.scala 394:26]
|
|
node _T_1297 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 395:93]
|
|
reg _T_1298 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1297 : @[Reg.scala 28:19]
|
|
_T_1298 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[1] <= _T_1298 @[el2_ifu_mem_ctl.scala 395:28]
|
|
node _T_1299 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 394:91]
|
|
reg _T_1300 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1299 : @[Reg.scala 28:19]
|
|
_T_1300 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[2] <= _T_1300 @[el2_ifu_mem_ctl.scala 394:26]
|
|
node _T_1301 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 395:93]
|
|
reg _T_1302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1301 : @[Reg.scala 28:19]
|
|
_T_1302 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[3] <= _T_1302 @[el2_ifu_mem_ctl.scala 395:28]
|
|
node _T_1303 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 394:91]
|
|
reg _T_1304 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1303 : @[Reg.scala 28:19]
|
|
_T_1304 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[4] <= _T_1304 @[el2_ifu_mem_ctl.scala 394:26]
|
|
node _T_1305 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 395:93]
|
|
reg _T_1306 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1305 : @[Reg.scala 28:19]
|
|
_T_1306 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[5] <= _T_1306 @[el2_ifu_mem_ctl.scala 395:28]
|
|
node _T_1307 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 394:91]
|
|
reg _T_1308 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1307 : @[Reg.scala 28:19]
|
|
_T_1308 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[6] <= _T_1308 @[el2_ifu_mem_ctl.scala 394:26]
|
|
node _T_1309 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 395:93]
|
|
reg _T_1310 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1309 : @[Reg.scala 28:19]
|
|
_T_1310 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[7] <= _T_1310 @[el2_ifu_mem_ctl.scala 395:28]
|
|
node _T_1311 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 394:91]
|
|
reg _T_1312 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1311 : @[Reg.scala 28:19]
|
|
_T_1312 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[8] <= _T_1312 @[el2_ifu_mem_ctl.scala 394:26]
|
|
node _T_1313 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 395:93]
|
|
reg _T_1314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1313 : @[Reg.scala 28:19]
|
|
_T_1314 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[9] <= _T_1314 @[el2_ifu_mem_ctl.scala 395:28]
|
|
node _T_1315 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 394:91]
|
|
reg _T_1316 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1315 : @[Reg.scala 28:19]
|
|
_T_1316 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[10] <= _T_1316 @[el2_ifu_mem_ctl.scala 394:26]
|
|
node _T_1317 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 395:93]
|
|
reg _T_1318 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1317 : @[Reg.scala 28:19]
|
|
_T_1318 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[11] <= _T_1318 @[el2_ifu_mem_ctl.scala 395:28]
|
|
node _T_1319 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 394:91]
|
|
reg _T_1320 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1319 : @[Reg.scala 28:19]
|
|
_T_1320 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[12] <= _T_1320 @[el2_ifu_mem_ctl.scala 394:26]
|
|
node _T_1321 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 395:93]
|
|
reg _T_1322 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1321 : @[Reg.scala 28:19]
|
|
_T_1322 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[13] <= _T_1322 @[el2_ifu_mem_ctl.scala 395:28]
|
|
node _T_1323 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 394:91]
|
|
reg _T_1324 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1323 : @[Reg.scala 28:19]
|
|
_T_1324 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[14] <= _T_1324 @[el2_ifu_mem_ctl.scala 394:26]
|
|
node _T_1325 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 395:93]
|
|
reg _T_1326 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1325 : @[Reg.scala 28:19]
|
|
_T_1326 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[15] <= _T_1326 @[el2_ifu_mem_ctl.scala 395:28]
|
|
wire ic_miss_buff_data_valid : UInt<8>
|
|
ic_miss_buff_data_valid <= UInt<1>("h00")
|
|
node _T_1327 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 397:113]
|
|
node _T_1328 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118]
|
|
node _T_1329 = and(_T_1327, _T_1328) @[el2_ifu_mem_ctl.scala 397:116]
|
|
node ic_miss_buff_data_valid_in_0 = or(write_fill_data_0, _T_1329) @[el2_ifu_mem_ctl.scala 397:88]
|
|
node _T_1330 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 397:113]
|
|
node _T_1331 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118]
|
|
node _T_1332 = and(_T_1330, _T_1331) @[el2_ifu_mem_ctl.scala 397:116]
|
|
node ic_miss_buff_data_valid_in_1 = or(write_fill_data_1, _T_1332) @[el2_ifu_mem_ctl.scala 397:88]
|
|
node _T_1333 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 397:113]
|
|
node _T_1334 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118]
|
|
node _T_1335 = and(_T_1333, _T_1334) @[el2_ifu_mem_ctl.scala 397:116]
|
|
node ic_miss_buff_data_valid_in_2 = or(write_fill_data_2, _T_1335) @[el2_ifu_mem_ctl.scala 397:88]
|
|
node _T_1336 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 397:113]
|
|
node _T_1337 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118]
|
|
node _T_1338 = and(_T_1336, _T_1337) @[el2_ifu_mem_ctl.scala 397:116]
|
|
node ic_miss_buff_data_valid_in_3 = or(write_fill_data_3, _T_1338) @[el2_ifu_mem_ctl.scala 397:88]
|
|
node _T_1339 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 397:113]
|
|
node _T_1340 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118]
|
|
node _T_1341 = and(_T_1339, _T_1340) @[el2_ifu_mem_ctl.scala 397:116]
|
|
node ic_miss_buff_data_valid_in_4 = or(write_fill_data_4, _T_1341) @[el2_ifu_mem_ctl.scala 397:88]
|
|
node _T_1342 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 397:113]
|
|
node _T_1343 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118]
|
|
node _T_1344 = and(_T_1342, _T_1343) @[el2_ifu_mem_ctl.scala 397:116]
|
|
node ic_miss_buff_data_valid_in_5 = or(write_fill_data_5, _T_1344) @[el2_ifu_mem_ctl.scala 397:88]
|
|
node _T_1345 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 397:113]
|
|
node _T_1346 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118]
|
|
node _T_1347 = and(_T_1345, _T_1346) @[el2_ifu_mem_ctl.scala 397:116]
|
|
node ic_miss_buff_data_valid_in_6 = or(write_fill_data_6, _T_1347) @[el2_ifu_mem_ctl.scala 397:88]
|
|
node _T_1348 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 397:113]
|
|
node _T_1349 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118]
|
|
node _T_1350 = and(_T_1348, _T_1349) @[el2_ifu_mem_ctl.scala 397:116]
|
|
node ic_miss_buff_data_valid_in_7 = or(write_fill_data_7, _T_1350) @[el2_ifu_mem_ctl.scala 397:88]
|
|
node _T_1351 = cat(ic_miss_buff_data_valid_in_7, ic_miss_buff_data_valid_in_6) @[Cat.scala 29:58]
|
|
node _T_1352 = cat(_T_1351, ic_miss_buff_data_valid_in_5) @[Cat.scala 29:58]
|
|
node _T_1353 = cat(_T_1352, ic_miss_buff_data_valid_in_4) @[Cat.scala 29:58]
|
|
node _T_1354 = cat(_T_1353, ic_miss_buff_data_valid_in_3) @[Cat.scala 29:58]
|
|
node _T_1355 = cat(_T_1354, ic_miss_buff_data_valid_in_2) @[Cat.scala 29:58]
|
|
node _T_1356 = cat(_T_1355, ic_miss_buff_data_valid_in_1) @[Cat.scala 29:58]
|
|
node _T_1357 = cat(_T_1356, ic_miss_buff_data_valid_in_0) @[Cat.scala 29:58]
|
|
reg _T_1358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 398:60]
|
|
_T_1358 <= _T_1357 @[el2_ifu_mem_ctl.scala 398:60]
|
|
ic_miss_buff_data_valid <= _T_1358 @[el2_ifu_mem_ctl.scala 398:27]
|
|
wire bus_ifu_wr_data_error : UInt<1>
|
|
bus_ifu_wr_data_error <= UInt<1>("h00")
|
|
wire ic_miss_buff_data_error : UInt<8>
|
|
ic_miss_buff_data_error <= UInt<1>("h00")
|
|
node _T_1359 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 401:92]
|
|
node _T_1360 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1361 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34]
|
|
node _T_1362 = and(_T_1360, _T_1361) @[el2_ifu_mem_ctl.scala 402:32]
|
|
node ic_miss_buff_data_error_in_0 = mux(_T_1359, bus_ifu_wr_data_error, _T_1362) @[el2_ifu_mem_ctl.scala 401:72]
|
|
node _T_1363 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 401:92]
|
|
node _T_1364 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1365 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34]
|
|
node _T_1366 = and(_T_1364, _T_1365) @[el2_ifu_mem_ctl.scala 402:32]
|
|
node ic_miss_buff_data_error_in_1 = mux(_T_1363, bus_ifu_wr_data_error, _T_1366) @[el2_ifu_mem_ctl.scala 401:72]
|
|
node _T_1367 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 401:92]
|
|
node _T_1368 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1369 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34]
|
|
node _T_1370 = and(_T_1368, _T_1369) @[el2_ifu_mem_ctl.scala 402:32]
|
|
node ic_miss_buff_data_error_in_2 = mux(_T_1367, bus_ifu_wr_data_error, _T_1370) @[el2_ifu_mem_ctl.scala 401:72]
|
|
node _T_1371 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 401:92]
|
|
node _T_1372 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1373 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34]
|
|
node _T_1374 = and(_T_1372, _T_1373) @[el2_ifu_mem_ctl.scala 402:32]
|
|
node ic_miss_buff_data_error_in_3 = mux(_T_1371, bus_ifu_wr_data_error, _T_1374) @[el2_ifu_mem_ctl.scala 401:72]
|
|
node _T_1375 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 401:92]
|
|
node _T_1376 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1377 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34]
|
|
node _T_1378 = and(_T_1376, _T_1377) @[el2_ifu_mem_ctl.scala 402:32]
|
|
node ic_miss_buff_data_error_in_4 = mux(_T_1375, bus_ifu_wr_data_error, _T_1378) @[el2_ifu_mem_ctl.scala 401:72]
|
|
node _T_1379 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 401:92]
|
|
node _T_1380 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1381 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34]
|
|
node _T_1382 = and(_T_1380, _T_1381) @[el2_ifu_mem_ctl.scala 402:32]
|
|
node ic_miss_buff_data_error_in_5 = mux(_T_1379, bus_ifu_wr_data_error, _T_1382) @[el2_ifu_mem_ctl.scala 401:72]
|
|
node _T_1383 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 401:92]
|
|
node _T_1384 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1385 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34]
|
|
node _T_1386 = and(_T_1384, _T_1385) @[el2_ifu_mem_ctl.scala 402:32]
|
|
node ic_miss_buff_data_error_in_6 = mux(_T_1383, bus_ifu_wr_data_error, _T_1386) @[el2_ifu_mem_ctl.scala 401:72]
|
|
node _T_1387 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 401:92]
|
|
node _T_1388 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1389 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34]
|
|
node _T_1390 = and(_T_1388, _T_1389) @[el2_ifu_mem_ctl.scala 402:32]
|
|
node ic_miss_buff_data_error_in_7 = mux(_T_1387, bus_ifu_wr_data_error, _T_1390) @[el2_ifu_mem_ctl.scala 401:72]
|
|
node _T_1391 = cat(ic_miss_buff_data_error_in_7, ic_miss_buff_data_error_in_6) @[Cat.scala 29:58]
|
|
node _T_1392 = cat(_T_1391, ic_miss_buff_data_error_in_5) @[Cat.scala 29:58]
|
|
node _T_1393 = cat(_T_1392, ic_miss_buff_data_error_in_4) @[Cat.scala 29:58]
|
|
node _T_1394 = cat(_T_1393, ic_miss_buff_data_error_in_3) @[Cat.scala 29:58]
|
|
node _T_1395 = cat(_T_1394, ic_miss_buff_data_error_in_2) @[Cat.scala 29:58]
|
|
node _T_1396 = cat(_T_1395, ic_miss_buff_data_error_in_1) @[Cat.scala 29:58]
|
|
node _T_1397 = cat(_T_1396, ic_miss_buff_data_error_in_0) @[Cat.scala 29:58]
|
|
reg _T_1398 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 403:60]
|
|
_T_1398 <= _T_1397 @[el2_ifu_mem_ctl.scala 403:60]
|
|
ic_miss_buff_data_error <= _T_1398 @[el2_ifu_mem_ctl.scala 403:27]
|
|
node bypass_index = bits(imb_ff, 4, 0) @[el2_ifu_mem_ctl.scala 406:28]
|
|
node _T_1399 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 407:42]
|
|
node _T_1400 = add(_T_1399, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 407:70]
|
|
node bypass_index_5_3_inc = tail(_T_1400, 1) @[el2_ifu_mem_ctl.scala 407:70]
|
|
node _T_1401 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87]
|
|
node _T_1402 = eq(_T_1401, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 408:114]
|
|
node _T_1403 = bits(_T_1402, 0, 0) @[el2_ifu_mem_ctl.scala 408:122]
|
|
node _T_1404 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87]
|
|
node _T_1405 = eq(_T_1404, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 408:114]
|
|
node _T_1406 = bits(_T_1405, 0, 0) @[el2_ifu_mem_ctl.scala 408:122]
|
|
node _T_1407 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87]
|
|
node _T_1408 = eq(_T_1407, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 408:114]
|
|
node _T_1409 = bits(_T_1408, 0, 0) @[el2_ifu_mem_ctl.scala 408:122]
|
|
node _T_1410 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87]
|
|
node _T_1411 = eq(_T_1410, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 408:114]
|
|
node _T_1412 = bits(_T_1411, 0, 0) @[el2_ifu_mem_ctl.scala 408:122]
|
|
node _T_1413 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87]
|
|
node _T_1414 = eq(_T_1413, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 408:114]
|
|
node _T_1415 = bits(_T_1414, 0, 0) @[el2_ifu_mem_ctl.scala 408:122]
|
|
node _T_1416 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87]
|
|
node _T_1417 = eq(_T_1416, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 408:114]
|
|
node _T_1418 = bits(_T_1417, 0, 0) @[el2_ifu_mem_ctl.scala 408:122]
|
|
node _T_1419 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87]
|
|
node _T_1420 = eq(_T_1419, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 408:114]
|
|
node _T_1421 = bits(_T_1420, 0, 0) @[el2_ifu_mem_ctl.scala 408:122]
|
|
node _T_1422 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87]
|
|
node _T_1423 = eq(_T_1422, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 408:114]
|
|
node _T_1424 = bits(_T_1423, 0, 0) @[el2_ifu_mem_ctl.scala 408:122]
|
|
node _T_1425 = mux(_T_1403, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1426 = mux(_T_1406, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1427 = mux(_T_1409, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1428 = mux(_T_1412, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1429 = mux(_T_1415, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1430 = mux(_T_1418, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1431 = mux(_T_1421, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1432 = mux(_T_1424, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1433 = or(_T_1425, _T_1426) @[Mux.scala 27:72]
|
|
node _T_1434 = or(_T_1433, _T_1427) @[Mux.scala 27:72]
|
|
node _T_1435 = or(_T_1434, _T_1428) @[Mux.scala 27:72]
|
|
node _T_1436 = or(_T_1435, _T_1429) @[Mux.scala 27:72]
|
|
node _T_1437 = or(_T_1436, _T_1430) @[Mux.scala 27:72]
|
|
node _T_1438 = or(_T_1437, _T_1431) @[Mux.scala 27:72]
|
|
node _T_1439 = or(_T_1438, _T_1432) @[Mux.scala 27:72]
|
|
wire bypass_valid_value_check : UInt<1> @[Mux.scala 27:72]
|
|
bypass_valid_value_check <= _T_1439 @[Mux.scala 27:72]
|
|
node _T_1440 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 409:71]
|
|
node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:58]
|
|
node _T_1442 = and(bypass_valid_value_check, _T_1441) @[el2_ifu_mem_ctl.scala 409:56]
|
|
node _T_1443 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 409:90]
|
|
node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:77]
|
|
node _T_1445 = and(_T_1442, _T_1444) @[el2_ifu_mem_ctl.scala 409:75]
|
|
node _T_1446 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 410:71]
|
|
node _T_1447 = eq(_T_1446, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:58]
|
|
node _T_1448 = and(bypass_valid_value_check, _T_1447) @[el2_ifu_mem_ctl.scala 410:56]
|
|
node _T_1449 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 410:89]
|
|
node _T_1450 = and(_T_1448, _T_1449) @[el2_ifu_mem_ctl.scala 410:75]
|
|
node _T_1451 = or(_T_1445, _T_1450) @[el2_ifu_mem_ctl.scala 409:95]
|
|
node _T_1452 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 411:70]
|
|
node _T_1453 = and(bypass_valid_value_check, _T_1452) @[el2_ifu_mem_ctl.scala 411:56]
|
|
node _T_1454 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 411:89]
|
|
node _T_1455 = eq(_T_1454, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 411:76]
|
|
node _T_1456 = and(_T_1453, _T_1455) @[el2_ifu_mem_ctl.scala 411:74]
|
|
node _T_1457 = or(_T_1451, _T_1456) @[el2_ifu_mem_ctl.scala 410:94]
|
|
node _T_1458 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 412:47]
|
|
node _T_1459 = and(bypass_valid_value_check, _T_1458) @[el2_ifu_mem_ctl.scala 412:33]
|
|
node _T_1460 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 412:65]
|
|
node _T_1461 = and(_T_1459, _T_1460) @[el2_ifu_mem_ctl.scala 412:51]
|
|
node _T_1462 = eq(bypass_index_5_3_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 412:132]
|
|
node _T_1463 = bits(_T_1462, 0, 0) @[el2_ifu_mem_ctl.scala 412:140]
|
|
node _T_1464 = eq(bypass_index_5_3_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 412:132]
|
|
node _T_1465 = bits(_T_1464, 0, 0) @[el2_ifu_mem_ctl.scala 412:140]
|
|
node _T_1466 = eq(bypass_index_5_3_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 412:132]
|
|
node _T_1467 = bits(_T_1466, 0, 0) @[el2_ifu_mem_ctl.scala 412:140]
|
|
node _T_1468 = eq(bypass_index_5_3_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 412:132]
|
|
node _T_1469 = bits(_T_1468, 0, 0) @[el2_ifu_mem_ctl.scala 412:140]
|
|
node _T_1470 = eq(bypass_index_5_3_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 412:132]
|
|
node _T_1471 = bits(_T_1470, 0, 0) @[el2_ifu_mem_ctl.scala 412:140]
|
|
node _T_1472 = eq(bypass_index_5_3_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 412:132]
|
|
node _T_1473 = bits(_T_1472, 0, 0) @[el2_ifu_mem_ctl.scala 412:140]
|
|
node _T_1474 = eq(bypass_index_5_3_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 412:132]
|
|
node _T_1475 = bits(_T_1474, 0, 0) @[el2_ifu_mem_ctl.scala 412:140]
|
|
node _T_1476 = eq(bypass_index_5_3_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 412:132]
|
|
node _T_1477 = bits(_T_1476, 0, 0) @[el2_ifu_mem_ctl.scala 412:140]
|
|
node _T_1478 = mux(_T_1463, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1479 = mux(_T_1465, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1480 = mux(_T_1467, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1481 = mux(_T_1469, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1482 = mux(_T_1471, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1483 = mux(_T_1473, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1484 = mux(_T_1475, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1485 = mux(_T_1477, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1486 = or(_T_1478, _T_1479) @[Mux.scala 27:72]
|
|
node _T_1487 = or(_T_1486, _T_1480) @[Mux.scala 27:72]
|
|
node _T_1488 = or(_T_1487, _T_1481) @[Mux.scala 27:72]
|
|
node _T_1489 = or(_T_1488, _T_1482) @[Mux.scala 27:72]
|
|
node _T_1490 = or(_T_1489, _T_1483) @[Mux.scala 27:72]
|
|
node _T_1491 = or(_T_1490, _T_1484) @[Mux.scala 27:72]
|
|
node _T_1492 = or(_T_1491, _T_1485) @[Mux.scala 27:72]
|
|
wire _T_1493 : UInt<1> @[Mux.scala 27:72]
|
|
_T_1493 <= _T_1492 @[Mux.scala 27:72]
|
|
node _T_1494 = and(_T_1461, _T_1493) @[el2_ifu_mem_ctl.scala 412:69]
|
|
node _T_1495 = or(_T_1457, _T_1494) @[el2_ifu_mem_ctl.scala 411:94]
|
|
node _T_1496 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 413:70]
|
|
node _T_1497 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1498 = eq(_T_1496, _T_1497) @[el2_ifu_mem_ctl.scala 413:95]
|
|
node _T_1499 = and(bypass_valid_value_check, _T_1498) @[el2_ifu_mem_ctl.scala 413:56]
|
|
node bypass_data_ready_in = or(_T_1495, _T_1499) @[el2_ifu_mem_ctl.scala 412:181]
|
|
wire ic_crit_wd_rdy_new_ff : UInt<1>
|
|
ic_crit_wd_rdy_new_ff <= UInt<1>("h00")
|
|
node _T_1500 = and(bypass_data_ready_in, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 417:53]
|
|
node _T_1501 = and(_T_1500, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 417:73]
|
|
node _T_1502 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 417:98]
|
|
node _T_1503 = and(_T_1501, _T_1502) @[el2_ifu_mem_ctl.scala 417:96]
|
|
node _T_1504 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 417:120]
|
|
node _T_1505 = and(_T_1503, _T_1504) @[el2_ifu_mem_ctl.scala 417:118]
|
|
node _T_1506 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 418:75]
|
|
node _T_1507 = and(crit_wd_byp_ok_ff, _T_1506) @[el2_ifu_mem_ctl.scala 418:73]
|
|
node _T_1508 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 418:98]
|
|
node _T_1509 = and(_T_1507, _T_1508) @[el2_ifu_mem_ctl.scala 418:96]
|
|
node _T_1510 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 418:120]
|
|
node _T_1511 = and(_T_1509, _T_1510) @[el2_ifu_mem_ctl.scala 418:118]
|
|
node _T_1512 = or(_T_1505, _T_1511) @[el2_ifu_mem_ctl.scala 417:143]
|
|
node _T_1513 = and(ic_crit_wd_rdy_new_ff, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 419:54]
|
|
node _T_1514 = eq(fetch_req_icache_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 419:76]
|
|
node _T_1515 = and(_T_1513, _T_1514) @[el2_ifu_mem_ctl.scala 419:74]
|
|
node _T_1516 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 419:98]
|
|
node _T_1517 = and(_T_1515, _T_1516) @[el2_ifu_mem_ctl.scala 419:96]
|
|
node ic_crit_wd_rdy_new_in = or(_T_1512, _T_1517) @[el2_ifu_mem_ctl.scala 418:143]
|
|
reg _T_1518 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 420:58]
|
|
_T_1518 <= ic_crit_wd_rdy_new_in @[el2_ifu_mem_ctl.scala 420:58]
|
|
ic_crit_wd_rdy_new_ff <= _T_1518 @[el2_ifu_mem_ctl.scala 420:25]
|
|
node byp_fetch_index = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 421:45]
|
|
node _T_1519 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 422:51]
|
|
node byp_fetch_index_0 = cat(_T_1519, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_1520 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 423:51]
|
|
node byp_fetch_index_1 = cat(_T_1520, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_1521 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 424:49]
|
|
node _T_1522 = add(_T_1521, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 424:75]
|
|
node byp_fetch_index_inc = tail(_T_1522, 1) @[el2_ifu_mem_ctl.scala 424:75]
|
|
node byp_fetch_index_inc_0 = cat(byp_fetch_index_inc, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node byp_fetch_index_inc_1 = cat(byp_fetch_index_inc, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_1523 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93]
|
|
node _T_1524 = eq(_T_1523, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 427:118]
|
|
node _T_1525 = bits(_T_1524, 0, 0) @[el2_ifu_mem_ctl.scala 427:126]
|
|
node _T_1526 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 427:157]
|
|
node _T_1527 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93]
|
|
node _T_1528 = eq(_T_1527, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 427:118]
|
|
node _T_1529 = bits(_T_1528, 0, 0) @[el2_ifu_mem_ctl.scala 427:126]
|
|
node _T_1530 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 427:157]
|
|
node _T_1531 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93]
|
|
node _T_1532 = eq(_T_1531, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 427:118]
|
|
node _T_1533 = bits(_T_1532, 0, 0) @[el2_ifu_mem_ctl.scala 427:126]
|
|
node _T_1534 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 427:157]
|
|
node _T_1535 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93]
|
|
node _T_1536 = eq(_T_1535, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 427:118]
|
|
node _T_1537 = bits(_T_1536, 0, 0) @[el2_ifu_mem_ctl.scala 427:126]
|
|
node _T_1538 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 427:157]
|
|
node _T_1539 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93]
|
|
node _T_1540 = eq(_T_1539, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 427:118]
|
|
node _T_1541 = bits(_T_1540, 0, 0) @[el2_ifu_mem_ctl.scala 427:126]
|
|
node _T_1542 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 427:157]
|
|
node _T_1543 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93]
|
|
node _T_1544 = eq(_T_1543, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 427:118]
|
|
node _T_1545 = bits(_T_1544, 0, 0) @[el2_ifu_mem_ctl.scala 427:126]
|
|
node _T_1546 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 427:157]
|
|
node _T_1547 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93]
|
|
node _T_1548 = eq(_T_1547, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 427:118]
|
|
node _T_1549 = bits(_T_1548, 0, 0) @[el2_ifu_mem_ctl.scala 427:126]
|
|
node _T_1550 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 427:157]
|
|
node _T_1551 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93]
|
|
node _T_1552 = eq(_T_1551, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 427:118]
|
|
node _T_1553 = bits(_T_1552, 0, 0) @[el2_ifu_mem_ctl.scala 427:126]
|
|
node _T_1554 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 427:157]
|
|
node _T_1555 = mux(_T_1525, _T_1526, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1556 = mux(_T_1529, _T_1530, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1557 = mux(_T_1533, _T_1534, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1558 = mux(_T_1537, _T_1538, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1559 = mux(_T_1541, _T_1542, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1560 = mux(_T_1545, _T_1546, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1561 = mux(_T_1549, _T_1550, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1562 = mux(_T_1553, _T_1554, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1563 = or(_T_1555, _T_1556) @[Mux.scala 27:72]
|
|
node _T_1564 = or(_T_1563, _T_1557) @[Mux.scala 27:72]
|
|
node _T_1565 = or(_T_1564, _T_1558) @[Mux.scala 27:72]
|
|
node _T_1566 = or(_T_1565, _T_1559) @[Mux.scala 27:72]
|
|
node _T_1567 = or(_T_1566, _T_1560) @[Mux.scala 27:72]
|
|
node _T_1568 = or(_T_1567, _T_1561) @[Mux.scala 27:72]
|
|
node _T_1569 = or(_T_1568, _T_1562) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_error_bypass : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_error_bypass <= _T_1569 @[Mux.scala 27:72]
|
|
node _T_1570 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 428:104]
|
|
node _T_1571 = bits(_T_1570, 0, 0) @[el2_ifu_mem_ctl.scala 428:112]
|
|
node _T_1572 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 428:143]
|
|
node _T_1573 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 428:104]
|
|
node _T_1574 = bits(_T_1573, 0, 0) @[el2_ifu_mem_ctl.scala 428:112]
|
|
node _T_1575 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 428:143]
|
|
node _T_1576 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 428:104]
|
|
node _T_1577 = bits(_T_1576, 0, 0) @[el2_ifu_mem_ctl.scala 428:112]
|
|
node _T_1578 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 428:143]
|
|
node _T_1579 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 428:104]
|
|
node _T_1580 = bits(_T_1579, 0, 0) @[el2_ifu_mem_ctl.scala 428:112]
|
|
node _T_1581 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 428:143]
|
|
node _T_1582 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 428:104]
|
|
node _T_1583 = bits(_T_1582, 0, 0) @[el2_ifu_mem_ctl.scala 428:112]
|
|
node _T_1584 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 428:143]
|
|
node _T_1585 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 428:104]
|
|
node _T_1586 = bits(_T_1585, 0, 0) @[el2_ifu_mem_ctl.scala 428:112]
|
|
node _T_1587 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 428:143]
|
|
node _T_1588 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 428:104]
|
|
node _T_1589 = bits(_T_1588, 0, 0) @[el2_ifu_mem_ctl.scala 428:112]
|
|
node _T_1590 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 428:143]
|
|
node _T_1591 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 428:104]
|
|
node _T_1592 = bits(_T_1591, 0, 0) @[el2_ifu_mem_ctl.scala 428:112]
|
|
node _T_1593 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 428:143]
|
|
node _T_1594 = mux(_T_1571, _T_1572, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1595 = mux(_T_1574, _T_1575, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1596 = mux(_T_1577, _T_1578, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1597 = mux(_T_1580, _T_1581, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1598 = mux(_T_1583, _T_1584, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1599 = mux(_T_1586, _T_1587, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1600 = mux(_T_1589, _T_1590, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1601 = mux(_T_1592, _T_1593, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1602 = or(_T_1594, _T_1595) @[Mux.scala 27:72]
|
|
node _T_1603 = or(_T_1602, _T_1596) @[Mux.scala 27:72]
|
|
node _T_1604 = or(_T_1603, _T_1597) @[Mux.scala 27:72]
|
|
node _T_1605 = or(_T_1604, _T_1598) @[Mux.scala 27:72]
|
|
node _T_1606 = or(_T_1605, _T_1599) @[Mux.scala 27:72]
|
|
node _T_1607 = or(_T_1606, _T_1600) @[Mux.scala 27:72]
|
|
node _T_1608 = or(_T_1607, _T_1601) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_error_bypass_inc : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_error_bypass_inc <= _T_1608 @[Mux.scala 27:72]
|
|
node _T_1609 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 431:28]
|
|
node _T_1610 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 431:52]
|
|
node _T_1611 = and(_T_1609, _T_1610) @[el2_ifu_mem_ctl.scala 431:31]
|
|
when _T_1611 : @[el2_ifu_mem_ctl.scala 431:56]
|
|
ifu_byp_data_err_new <= ic_miss_buff_data_error_bypass @[el2_ifu_mem_ctl.scala 432:26]
|
|
skip @[el2_ifu_mem_ctl.scala 431:56]
|
|
else : @[el2_ifu_mem_ctl.scala 433:5]
|
|
node _T_1612 = or(ic_miss_buff_data_error_bypass, ic_miss_buff_data_error_bypass_inc) @[el2_ifu_mem_ctl.scala 433:70]
|
|
ifu_byp_data_err_new <= _T_1612 @[el2_ifu_mem_ctl.scala 433:36]
|
|
skip @[el2_ifu_mem_ctl.scala 433:5]
|
|
node _T_1613 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 435:59]
|
|
node _T_1614 = bits(_T_1613, 0, 0) @[el2_ifu_mem_ctl.scala 435:63]
|
|
node _T_1615 = eq(_T_1614, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 435:38]
|
|
node _T_1616 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1617 = bits(_T_1616, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1618 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1619 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1620 = bits(_T_1619, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1621 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1622 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1623 = bits(_T_1622, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1624 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1625 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1626 = bits(_T_1625, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1627 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1628 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1629 = bits(_T_1628, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1630 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1631 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1632 = bits(_T_1631, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1633 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1634 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1635 = bits(_T_1634, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1636 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1637 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1638 = bits(_T_1637, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1639 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1640 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1641 = bits(_T_1640, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1642 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1643 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1644 = bits(_T_1643, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1645 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1646 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1647 = bits(_T_1646, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1648 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1649 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1650 = bits(_T_1649, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1651 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1652 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1653 = bits(_T_1652, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1654 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1655 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1656 = bits(_T_1655, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1657 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1658 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1659 = bits(_T_1658, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1660 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1661 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 436:73]
|
|
node _T_1662 = bits(_T_1661, 0, 0) @[el2_ifu_mem_ctl.scala 436:81]
|
|
node _T_1663 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 436:109]
|
|
node _T_1664 = mux(_T_1617, _T_1618, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1665 = mux(_T_1620, _T_1621, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1666 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1667 = mux(_T_1626, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1668 = mux(_T_1629, _T_1630, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1669 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1670 = mux(_T_1635, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1671 = mux(_T_1638, _T_1639, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1672 = mux(_T_1641, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1673 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1674 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1675 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1676 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1677 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1678 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1679 = mux(_T_1662, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1680 = or(_T_1664, _T_1665) @[Mux.scala 27:72]
|
|
node _T_1681 = or(_T_1680, _T_1666) @[Mux.scala 27:72]
|
|
node _T_1682 = or(_T_1681, _T_1667) @[Mux.scala 27:72]
|
|
node _T_1683 = or(_T_1682, _T_1668) @[Mux.scala 27:72]
|
|
node _T_1684 = or(_T_1683, _T_1669) @[Mux.scala 27:72]
|
|
node _T_1685 = or(_T_1684, _T_1670) @[Mux.scala 27:72]
|
|
node _T_1686 = or(_T_1685, _T_1671) @[Mux.scala 27:72]
|
|
node _T_1687 = or(_T_1686, _T_1672) @[Mux.scala 27:72]
|
|
node _T_1688 = or(_T_1687, _T_1673) @[Mux.scala 27:72]
|
|
node _T_1689 = or(_T_1688, _T_1674) @[Mux.scala 27:72]
|
|
node _T_1690 = or(_T_1689, _T_1675) @[Mux.scala 27:72]
|
|
node _T_1691 = or(_T_1690, _T_1676) @[Mux.scala 27:72]
|
|
node _T_1692 = or(_T_1691, _T_1677) @[Mux.scala 27:72]
|
|
node _T_1693 = or(_T_1692, _T_1678) @[Mux.scala 27:72]
|
|
node _T_1694 = or(_T_1693, _T_1679) @[Mux.scala 27:72]
|
|
wire _T_1695 : UInt<16> @[Mux.scala 27:72]
|
|
_T_1695 <= _T_1694 @[Mux.scala 27:72]
|
|
node _T_1696 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1697 = bits(_T_1696, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1698 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1699 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1700 = bits(_T_1699, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1701 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1702 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1703 = bits(_T_1702, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1704 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1705 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1706 = bits(_T_1705, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1707 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1708 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1709 = bits(_T_1708, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1710 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1711 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1712 = bits(_T_1711, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1713 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1714 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1715 = bits(_T_1714, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1716 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1717 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1718 = bits(_T_1717, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1719 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1720 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1721 = bits(_T_1720, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1722 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1723 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1724 = bits(_T_1723, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1725 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1726 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1727 = bits(_T_1726, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1728 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1729 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1730 = bits(_T_1729, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1731 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1732 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1733 = bits(_T_1732, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1734 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1735 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1736 = bits(_T_1735, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1737 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1738 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1739 = bits(_T_1738, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1740 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1741 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 436:179]
|
|
node _T_1742 = bits(_T_1741, 0, 0) @[el2_ifu_mem_ctl.scala 436:187]
|
|
node _T_1743 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 436:215]
|
|
node _T_1744 = mux(_T_1697, _T_1698, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1745 = mux(_T_1700, _T_1701, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1746 = mux(_T_1703, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1747 = mux(_T_1706, _T_1707, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1748 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1749 = mux(_T_1712, _T_1713, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1750 = mux(_T_1715, _T_1716, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1751 = mux(_T_1718, _T_1719, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1752 = mux(_T_1721, _T_1722, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1753 = mux(_T_1724, _T_1725, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1754 = mux(_T_1727, _T_1728, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1755 = mux(_T_1730, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1756 = mux(_T_1733, _T_1734, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1757 = mux(_T_1736, _T_1737, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1758 = mux(_T_1739, _T_1740, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1759 = mux(_T_1742, _T_1743, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1760 = or(_T_1744, _T_1745) @[Mux.scala 27:72]
|
|
node _T_1761 = or(_T_1760, _T_1746) @[Mux.scala 27:72]
|
|
node _T_1762 = or(_T_1761, _T_1747) @[Mux.scala 27:72]
|
|
node _T_1763 = or(_T_1762, _T_1748) @[Mux.scala 27:72]
|
|
node _T_1764 = or(_T_1763, _T_1749) @[Mux.scala 27:72]
|
|
node _T_1765 = or(_T_1764, _T_1750) @[Mux.scala 27:72]
|
|
node _T_1766 = or(_T_1765, _T_1751) @[Mux.scala 27:72]
|
|
node _T_1767 = or(_T_1766, _T_1752) @[Mux.scala 27:72]
|
|
node _T_1768 = or(_T_1767, _T_1753) @[Mux.scala 27:72]
|
|
node _T_1769 = or(_T_1768, _T_1754) @[Mux.scala 27:72]
|
|
node _T_1770 = or(_T_1769, _T_1755) @[Mux.scala 27:72]
|
|
node _T_1771 = or(_T_1770, _T_1756) @[Mux.scala 27:72]
|
|
node _T_1772 = or(_T_1771, _T_1757) @[Mux.scala 27:72]
|
|
node _T_1773 = or(_T_1772, _T_1758) @[Mux.scala 27:72]
|
|
node _T_1774 = or(_T_1773, _T_1759) @[Mux.scala 27:72]
|
|
wire _T_1775 : UInt<32> @[Mux.scala 27:72]
|
|
_T_1775 <= _T_1774 @[Mux.scala 27:72]
|
|
node _T_1776 = eq(byp_fetch_index_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1777 = bits(_T_1776, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1778 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1779 = eq(byp_fetch_index_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1780 = bits(_T_1779, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1781 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1782 = eq(byp_fetch_index_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1783 = bits(_T_1782, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1784 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1785 = eq(byp_fetch_index_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1786 = bits(_T_1785, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1787 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1788 = eq(byp_fetch_index_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1789 = bits(_T_1788, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1790 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1791 = eq(byp_fetch_index_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1792 = bits(_T_1791, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1793 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1794 = eq(byp_fetch_index_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1795 = bits(_T_1794, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1796 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1797 = eq(byp_fetch_index_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1798 = bits(_T_1797, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1799 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1800 = eq(byp_fetch_index_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1801 = bits(_T_1800, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1802 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1803 = eq(byp_fetch_index_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1804 = bits(_T_1803, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1805 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1806 = eq(byp_fetch_index_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1807 = bits(_T_1806, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1808 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1809 = eq(byp_fetch_index_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1810 = bits(_T_1809, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1811 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1812 = eq(byp_fetch_index_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1813 = bits(_T_1812, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1814 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1815 = eq(byp_fetch_index_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1816 = bits(_T_1815, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1817 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1818 = eq(byp_fetch_index_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1819 = bits(_T_1818, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1820 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1821 = eq(byp_fetch_index_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 436:285]
|
|
node _T_1822 = bits(_T_1821, 0, 0) @[el2_ifu_mem_ctl.scala 436:293]
|
|
node _T_1823 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 436:321]
|
|
node _T_1824 = mux(_T_1777, _T_1778, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1825 = mux(_T_1780, _T_1781, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1826 = mux(_T_1783, _T_1784, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1827 = mux(_T_1786, _T_1787, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1828 = mux(_T_1789, _T_1790, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1829 = mux(_T_1792, _T_1793, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1830 = mux(_T_1795, _T_1796, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1831 = mux(_T_1798, _T_1799, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1832 = mux(_T_1801, _T_1802, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1833 = mux(_T_1804, _T_1805, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1834 = mux(_T_1807, _T_1808, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1835 = mux(_T_1810, _T_1811, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1836 = mux(_T_1813, _T_1814, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1837 = mux(_T_1816, _T_1817, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1838 = mux(_T_1819, _T_1820, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1839 = mux(_T_1822, _T_1823, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1840 = or(_T_1824, _T_1825) @[Mux.scala 27:72]
|
|
node _T_1841 = or(_T_1840, _T_1826) @[Mux.scala 27:72]
|
|
node _T_1842 = or(_T_1841, _T_1827) @[Mux.scala 27:72]
|
|
node _T_1843 = or(_T_1842, _T_1828) @[Mux.scala 27:72]
|
|
node _T_1844 = or(_T_1843, _T_1829) @[Mux.scala 27:72]
|
|
node _T_1845 = or(_T_1844, _T_1830) @[Mux.scala 27:72]
|
|
node _T_1846 = or(_T_1845, _T_1831) @[Mux.scala 27:72]
|
|
node _T_1847 = or(_T_1846, _T_1832) @[Mux.scala 27:72]
|
|
node _T_1848 = or(_T_1847, _T_1833) @[Mux.scala 27:72]
|
|
node _T_1849 = or(_T_1848, _T_1834) @[Mux.scala 27:72]
|
|
node _T_1850 = or(_T_1849, _T_1835) @[Mux.scala 27:72]
|
|
node _T_1851 = or(_T_1850, _T_1836) @[Mux.scala 27:72]
|
|
node _T_1852 = or(_T_1851, _T_1837) @[Mux.scala 27:72]
|
|
node _T_1853 = or(_T_1852, _T_1838) @[Mux.scala 27:72]
|
|
node _T_1854 = or(_T_1853, _T_1839) @[Mux.scala 27:72]
|
|
wire _T_1855 : UInt<32> @[Mux.scala 27:72]
|
|
_T_1855 <= _T_1854 @[Mux.scala 27:72]
|
|
node _T_1856 = cat(_T_1695, _T_1775) @[Cat.scala 29:58]
|
|
node _T_1857 = cat(_T_1856, _T_1855) @[Cat.scala 29:58]
|
|
node _T_1858 = eq(byp_fetch_index_inc_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1859 = bits(_T_1858, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1860 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1861 = eq(byp_fetch_index_inc_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1862 = bits(_T_1861, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1863 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1864 = eq(byp_fetch_index_inc_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1865 = bits(_T_1864, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1866 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1867 = eq(byp_fetch_index_inc_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1868 = bits(_T_1867, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1869 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1870 = eq(byp_fetch_index_inc_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1871 = bits(_T_1870, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1872 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1873 = eq(byp_fetch_index_inc_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1874 = bits(_T_1873, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1875 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1876 = eq(byp_fetch_index_inc_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1877 = bits(_T_1876, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1878 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1879 = eq(byp_fetch_index_inc_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1880 = bits(_T_1879, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1881 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1882 = eq(byp_fetch_index_inc_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1883 = bits(_T_1882, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1884 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1885 = eq(byp_fetch_index_inc_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1886 = bits(_T_1885, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1887 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1888 = eq(byp_fetch_index_inc_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1889 = bits(_T_1888, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1890 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1891 = eq(byp_fetch_index_inc_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1892 = bits(_T_1891, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1893 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1894 = eq(byp_fetch_index_inc_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1895 = bits(_T_1894, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1896 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1897 = eq(byp_fetch_index_inc_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1898 = bits(_T_1897, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1899 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1900 = eq(byp_fetch_index_inc_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1901 = bits(_T_1900, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1902 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1903 = eq(byp_fetch_index_inc_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 437:73]
|
|
node _T_1904 = bits(_T_1903, 0, 0) @[el2_ifu_mem_ctl.scala 437:81]
|
|
node _T_1905 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 437:109]
|
|
node _T_1906 = mux(_T_1859, _T_1860, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1907 = mux(_T_1862, _T_1863, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1908 = mux(_T_1865, _T_1866, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1909 = mux(_T_1868, _T_1869, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1910 = mux(_T_1871, _T_1872, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1911 = mux(_T_1874, _T_1875, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1912 = mux(_T_1877, _T_1878, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1913 = mux(_T_1880, _T_1881, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1914 = mux(_T_1883, _T_1884, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1915 = mux(_T_1886, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1916 = mux(_T_1889, _T_1890, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1917 = mux(_T_1892, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1918 = mux(_T_1895, _T_1896, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1919 = mux(_T_1898, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1920 = mux(_T_1901, _T_1902, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1921 = mux(_T_1904, _T_1905, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1922 = or(_T_1906, _T_1907) @[Mux.scala 27:72]
|
|
node _T_1923 = or(_T_1922, _T_1908) @[Mux.scala 27:72]
|
|
node _T_1924 = or(_T_1923, _T_1909) @[Mux.scala 27:72]
|
|
node _T_1925 = or(_T_1924, _T_1910) @[Mux.scala 27:72]
|
|
node _T_1926 = or(_T_1925, _T_1911) @[Mux.scala 27:72]
|
|
node _T_1927 = or(_T_1926, _T_1912) @[Mux.scala 27:72]
|
|
node _T_1928 = or(_T_1927, _T_1913) @[Mux.scala 27:72]
|
|
node _T_1929 = or(_T_1928, _T_1914) @[Mux.scala 27:72]
|
|
node _T_1930 = or(_T_1929, _T_1915) @[Mux.scala 27:72]
|
|
node _T_1931 = or(_T_1930, _T_1916) @[Mux.scala 27:72]
|
|
node _T_1932 = or(_T_1931, _T_1917) @[Mux.scala 27:72]
|
|
node _T_1933 = or(_T_1932, _T_1918) @[Mux.scala 27:72]
|
|
node _T_1934 = or(_T_1933, _T_1919) @[Mux.scala 27:72]
|
|
node _T_1935 = or(_T_1934, _T_1920) @[Mux.scala 27:72]
|
|
node _T_1936 = or(_T_1935, _T_1921) @[Mux.scala 27:72]
|
|
wire _T_1937 : UInt<16> @[Mux.scala 27:72]
|
|
_T_1937 <= _T_1936 @[Mux.scala 27:72]
|
|
node _T_1938 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1939 = bits(_T_1938, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1940 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1941 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1942 = bits(_T_1941, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1943 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1944 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1945 = bits(_T_1944, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1946 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1947 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1948 = bits(_T_1947, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1949 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1950 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1951 = bits(_T_1950, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1952 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1953 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1954 = bits(_T_1953, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1955 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1956 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1957 = bits(_T_1956, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1958 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1959 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1960 = bits(_T_1959, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1961 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1962 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1963 = bits(_T_1962, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1964 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1965 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1966 = bits(_T_1965, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1967 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1968 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1969 = bits(_T_1968, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1970 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1971 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1972 = bits(_T_1971, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1973 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1974 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1975 = bits(_T_1974, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1976 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1977 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1978 = bits(_T_1977, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1979 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1980 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1981 = bits(_T_1980, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1982 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1983 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 437:183]
|
|
node _T_1984 = bits(_T_1983, 0, 0) @[el2_ifu_mem_ctl.scala 437:191]
|
|
node _T_1985 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 437:219]
|
|
node _T_1986 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1987 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1988 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1989 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1990 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1991 = mux(_T_1954, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1992 = mux(_T_1957, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1993 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1994 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1995 = mux(_T_1966, _T_1967, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1996 = mux(_T_1969, _T_1970, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1997 = mux(_T_1972, _T_1973, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1998 = mux(_T_1975, _T_1976, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1999 = mux(_T_1978, _T_1979, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2000 = mux(_T_1981, _T_1982, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2001 = mux(_T_1984, _T_1985, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2002 = or(_T_1986, _T_1987) @[Mux.scala 27:72]
|
|
node _T_2003 = or(_T_2002, _T_1988) @[Mux.scala 27:72]
|
|
node _T_2004 = or(_T_2003, _T_1989) @[Mux.scala 27:72]
|
|
node _T_2005 = or(_T_2004, _T_1990) @[Mux.scala 27:72]
|
|
node _T_2006 = or(_T_2005, _T_1991) @[Mux.scala 27:72]
|
|
node _T_2007 = or(_T_2006, _T_1992) @[Mux.scala 27:72]
|
|
node _T_2008 = or(_T_2007, _T_1993) @[Mux.scala 27:72]
|
|
node _T_2009 = or(_T_2008, _T_1994) @[Mux.scala 27:72]
|
|
node _T_2010 = or(_T_2009, _T_1995) @[Mux.scala 27:72]
|
|
node _T_2011 = or(_T_2010, _T_1996) @[Mux.scala 27:72]
|
|
node _T_2012 = or(_T_2011, _T_1997) @[Mux.scala 27:72]
|
|
node _T_2013 = or(_T_2012, _T_1998) @[Mux.scala 27:72]
|
|
node _T_2014 = or(_T_2013, _T_1999) @[Mux.scala 27:72]
|
|
node _T_2015 = or(_T_2014, _T_2000) @[Mux.scala 27:72]
|
|
node _T_2016 = or(_T_2015, _T_2001) @[Mux.scala 27:72]
|
|
wire _T_2017 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2017 <= _T_2016 @[Mux.scala 27:72]
|
|
node _T_2018 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2019 = bits(_T_2018, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2020 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2021 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2022 = bits(_T_2021, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2023 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2024 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2025 = bits(_T_2024, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2026 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2027 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2028 = bits(_T_2027, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2029 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2030 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2031 = bits(_T_2030, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2032 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2033 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2034 = bits(_T_2033, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2035 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2036 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2037 = bits(_T_2036, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2038 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2039 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2040 = bits(_T_2039, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2041 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2042 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2043 = bits(_T_2042, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2044 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2045 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2046 = bits(_T_2045, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2047 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2048 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2049 = bits(_T_2048, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2050 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2051 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2052 = bits(_T_2051, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2053 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2054 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2055 = bits(_T_2054, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2056 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2057 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2058 = bits(_T_2057, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2059 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2060 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2061 = bits(_T_2060, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2062 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2063 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 437:289]
|
|
node _T_2064 = bits(_T_2063, 0, 0) @[el2_ifu_mem_ctl.scala 437:297]
|
|
node _T_2065 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 437:325]
|
|
node _T_2066 = mux(_T_2019, _T_2020, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2067 = mux(_T_2022, _T_2023, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2068 = mux(_T_2025, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2069 = mux(_T_2028, _T_2029, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2070 = mux(_T_2031, _T_2032, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2071 = mux(_T_2034, _T_2035, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2072 = mux(_T_2037, _T_2038, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2073 = mux(_T_2040, _T_2041, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2074 = mux(_T_2043, _T_2044, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2075 = mux(_T_2046, _T_2047, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2076 = mux(_T_2049, _T_2050, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2077 = mux(_T_2052, _T_2053, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2078 = mux(_T_2055, _T_2056, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2079 = mux(_T_2058, _T_2059, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2080 = mux(_T_2061, _T_2062, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2081 = mux(_T_2064, _T_2065, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2082 = or(_T_2066, _T_2067) @[Mux.scala 27:72]
|
|
node _T_2083 = or(_T_2082, _T_2068) @[Mux.scala 27:72]
|
|
node _T_2084 = or(_T_2083, _T_2069) @[Mux.scala 27:72]
|
|
node _T_2085 = or(_T_2084, _T_2070) @[Mux.scala 27:72]
|
|
node _T_2086 = or(_T_2085, _T_2071) @[Mux.scala 27:72]
|
|
node _T_2087 = or(_T_2086, _T_2072) @[Mux.scala 27:72]
|
|
node _T_2088 = or(_T_2087, _T_2073) @[Mux.scala 27:72]
|
|
node _T_2089 = or(_T_2088, _T_2074) @[Mux.scala 27:72]
|
|
node _T_2090 = or(_T_2089, _T_2075) @[Mux.scala 27:72]
|
|
node _T_2091 = or(_T_2090, _T_2076) @[Mux.scala 27:72]
|
|
node _T_2092 = or(_T_2091, _T_2077) @[Mux.scala 27:72]
|
|
node _T_2093 = or(_T_2092, _T_2078) @[Mux.scala 27:72]
|
|
node _T_2094 = or(_T_2093, _T_2079) @[Mux.scala 27:72]
|
|
node _T_2095 = or(_T_2094, _T_2080) @[Mux.scala 27:72]
|
|
node _T_2096 = or(_T_2095, _T_2081) @[Mux.scala 27:72]
|
|
wire _T_2097 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2097 <= _T_2096 @[Mux.scala 27:72]
|
|
node _T_2098 = cat(_T_1937, _T_2017) @[Cat.scala 29:58]
|
|
node _T_2099 = cat(_T_2098, _T_2097) @[Cat.scala 29:58]
|
|
node ic_byp_data_only_pre_new = mux(_T_1615, _T_1857, _T_2099) @[el2_ifu_mem_ctl.scala 435:37]
|
|
node _T_2100 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 439:52]
|
|
node _T_2101 = bits(_T_2100, 0, 0) @[el2_ifu_mem_ctl.scala 439:62]
|
|
node _T_2102 = eq(_T_2101, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 439:31]
|
|
node _T_2103 = bits(ic_byp_data_only_pre_new, 79, 16) @[el2_ifu_mem_ctl.scala 439:128]
|
|
node _T_2104 = cat(UInt<16>("h00"), _T_2103) @[Cat.scala 29:58]
|
|
node _T_2105 = mux(_T_2102, ic_byp_data_only_pre_new, _T_2104) @[el2_ifu_mem_ctl.scala 439:30]
|
|
ic_byp_data_only_new <= _T_2105 @[el2_ifu_mem_ctl.scala 439:24]
|
|
node _T_2106 = bits(imb_ff, 5, 5) @[el2_ifu_mem_ctl.scala 441:27]
|
|
node _T_2107 = bits(ifu_fetch_addr_int_f, 6, 6) @[el2_ifu_mem_ctl.scala 441:75]
|
|
node miss_wrap_f = neq(_T_2106, _T_2107) @[el2_ifu_mem_ctl.scala 441:51]
|
|
node _T_2108 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102]
|
|
node _T_2109 = eq(_T_2108, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 442:127]
|
|
node _T_2110 = bits(_T_2109, 0, 0) @[el2_ifu_mem_ctl.scala 442:135]
|
|
node _T_2111 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 442:166]
|
|
node _T_2112 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102]
|
|
node _T_2113 = eq(_T_2112, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 442:127]
|
|
node _T_2114 = bits(_T_2113, 0, 0) @[el2_ifu_mem_ctl.scala 442:135]
|
|
node _T_2115 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 442:166]
|
|
node _T_2116 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102]
|
|
node _T_2117 = eq(_T_2116, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 442:127]
|
|
node _T_2118 = bits(_T_2117, 0, 0) @[el2_ifu_mem_ctl.scala 442:135]
|
|
node _T_2119 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 442:166]
|
|
node _T_2120 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102]
|
|
node _T_2121 = eq(_T_2120, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 442:127]
|
|
node _T_2122 = bits(_T_2121, 0, 0) @[el2_ifu_mem_ctl.scala 442:135]
|
|
node _T_2123 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 442:166]
|
|
node _T_2124 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102]
|
|
node _T_2125 = eq(_T_2124, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 442:127]
|
|
node _T_2126 = bits(_T_2125, 0, 0) @[el2_ifu_mem_ctl.scala 442:135]
|
|
node _T_2127 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 442:166]
|
|
node _T_2128 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102]
|
|
node _T_2129 = eq(_T_2128, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 442:127]
|
|
node _T_2130 = bits(_T_2129, 0, 0) @[el2_ifu_mem_ctl.scala 442:135]
|
|
node _T_2131 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 442:166]
|
|
node _T_2132 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102]
|
|
node _T_2133 = eq(_T_2132, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 442:127]
|
|
node _T_2134 = bits(_T_2133, 0, 0) @[el2_ifu_mem_ctl.scala 442:135]
|
|
node _T_2135 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 442:166]
|
|
node _T_2136 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102]
|
|
node _T_2137 = eq(_T_2136, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 442:127]
|
|
node _T_2138 = bits(_T_2137, 0, 0) @[el2_ifu_mem_ctl.scala 442:135]
|
|
node _T_2139 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 442:166]
|
|
node _T_2140 = mux(_T_2110, _T_2111, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2141 = mux(_T_2114, _T_2115, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2142 = mux(_T_2118, _T_2119, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2143 = mux(_T_2122, _T_2123, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2144 = mux(_T_2126, _T_2127, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2145 = mux(_T_2130, _T_2131, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2146 = mux(_T_2134, _T_2135, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2147 = mux(_T_2138, _T_2139, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2148 = or(_T_2140, _T_2141) @[Mux.scala 27:72]
|
|
node _T_2149 = or(_T_2148, _T_2142) @[Mux.scala 27:72]
|
|
node _T_2150 = or(_T_2149, _T_2143) @[Mux.scala 27:72]
|
|
node _T_2151 = or(_T_2150, _T_2144) @[Mux.scala 27:72]
|
|
node _T_2152 = or(_T_2151, _T_2145) @[Mux.scala 27:72]
|
|
node _T_2153 = or(_T_2152, _T_2146) @[Mux.scala 27:72]
|
|
node _T_2154 = or(_T_2153, _T_2147) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_valid_bypass_index : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_valid_bypass_index <= _T_2154 @[Mux.scala 27:72]
|
|
node _T_2155 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 443:110]
|
|
node _T_2156 = bits(_T_2155, 0, 0) @[el2_ifu_mem_ctl.scala 443:118]
|
|
node _T_2157 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 443:149]
|
|
node _T_2158 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 443:110]
|
|
node _T_2159 = bits(_T_2158, 0, 0) @[el2_ifu_mem_ctl.scala 443:118]
|
|
node _T_2160 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 443:149]
|
|
node _T_2161 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 443:110]
|
|
node _T_2162 = bits(_T_2161, 0, 0) @[el2_ifu_mem_ctl.scala 443:118]
|
|
node _T_2163 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 443:149]
|
|
node _T_2164 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 443:110]
|
|
node _T_2165 = bits(_T_2164, 0, 0) @[el2_ifu_mem_ctl.scala 443:118]
|
|
node _T_2166 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 443:149]
|
|
node _T_2167 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 443:110]
|
|
node _T_2168 = bits(_T_2167, 0, 0) @[el2_ifu_mem_ctl.scala 443:118]
|
|
node _T_2169 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 443:149]
|
|
node _T_2170 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 443:110]
|
|
node _T_2171 = bits(_T_2170, 0, 0) @[el2_ifu_mem_ctl.scala 443:118]
|
|
node _T_2172 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 443:149]
|
|
node _T_2173 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 443:110]
|
|
node _T_2174 = bits(_T_2173, 0, 0) @[el2_ifu_mem_ctl.scala 443:118]
|
|
node _T_2175 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 443:149]
|
|
node _T_2176 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 443:110]
|
|
node _T_2177 = bits(_T_2176, 0, 0) @[el2_ifu_mem_ctl.scala 443:118]
|
|
node _T_2178 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 443:149]
|
|
node _T_2179 = mux(_T_2156, _T_2157, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2180 = mux(_T_2159, _T_2160, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2181 = mux(_T_2162, _T_2163, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2182 = mux(_T_2165, _T_2166, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2183 = mux(_T_2168, _T_2169, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2184 = mux(_T_2171, _T_2172, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2185 = mux(_T_2174, _T_2175, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2186 = mux(_T_2177, _T_2178, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2187 = or(_T_2179, _T_2180) @[Mux.scala 27:72]
|
|
node _T_2188 = or(_T_2187, _T_2181) @[Mux.scala 27:72]
|
|
node _T_2189 = or(_T_2188, _T_2182) @[Mux.scala 27:72]
|
|
node _T_2190 = or(_T_2189, _T_2183) @[Mux.scala 27:72]
|
|
node _T_2191 = or(_T_2190, _T_2184) @[Mux.scala 27:72]
|
|
node _T_2192 = or(_T_2191, _T_2185) @[Mux.scala 27:72]
|
|
node _T_2193 = or(_T_2192, _T_2186) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_valid_inc_bypass_index : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_valid_inc_bypass_index <= _T_2193 @[Mux.scala 27:72]
|
|
node _T_2194 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 444:85]
|
|
node _T_2195 = eq(_T_2194, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 444:69]
|
|
node _T_2196 = and(ic_miss_buff_data_valid_bypass_index, _T_2195) @[el2_ifu_mem_ctl.scala 444:67]
|
|
node _T_2197 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 444:107]
|
|
node _T_2198 = eq(_T_2197, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 444:91]
|
|
node _T_2199 = and(_T_2196, _T_2198) @[el2_ifu_mem_ctl.scala 444:89]
|
|
node _T_2200 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 445:61]
|
|
node _T_2201 = eq(_T_2200, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 445:45]
|
|
node _T_2202 = and(ic_miss_buff_data_valid_bypass_index, _T_2201) @[el2_ifu_mem_ctl.scala 445:43]
|
|
node _T_2203 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 445:83]
|
|
node _T_2204 = and(_T_2202, _T_2203) @[el2_ifu_mem_ctl.scala 445:65]
|
|
node _T_2205 = or(_T_2199, _T_2204) @[el2_ifu_mem_ctl.scala 444:112]
|
|
node _T_2206 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 446:61]
|
|
node _T_2207 = and(ic_miss_buff_data_valid_bypass_index, _T_2206) @[el2_ifu_mem_ctl.scala 446:43]
|
|
node _T_2208 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 446:83]
|
|
node _T_2209 = eq(_T_2208, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 446:67]
|
|
node _T_2210 = and(_T_2207, _T_2209) @[el2_ifu_mem_ctl.scala 446:65]
|
|
node _T_2211 = or(_T_2205, _T_2210) @[el2_ifu_mem_ctl.scala 445:88]
|
|
node _T_2212 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 447:61]
|
|
node _T_2213 = and(ic_miss_buff_data_valid_bypass_index, _T_2212) @[el2_ifu_mem_ctl.scala 447:43]
|
|
node _T_2214 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 447:83]
|
|
node _T_2215 = and(_T_2213, _T_2214) @[el2_ifu_mem_ctl.scala 447:65]
|
|
node _T_2216 = and(_T_2215, ic_miss_buff_data_valid_inc_bypass_index) @[el2_ifu_mem_ctl.scala 447:87]
|
|
node _T_2217 = or(_T_2211, _T_2216) @[el2_ifu_mem_ctl.scala 446:88]
|
|
node _T_2218 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 448:61]
|
|
node _T_2219 = eq(_T_2218, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:45]
|
|
node _T_2220 = and(ic_miss_buff_data_valid_bypass_index, _T_2219) @[el2_ifu_mem_ctl.scala 448:43]
|
|
node _T_2221 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 448:83]
|
|
node _T_2222 = eq(_T_2221, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:67]
|
|
node _T_2223 = and(_T_2220, _T_2222) @[el2_ifu_mem_ctl.scala 448:65]
|
|
node _T_2224 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 448:105]
|
|
node _T_2225 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2226 = eq(_T_2224, _T_2225) @[el2_ifu_mem_ctl.scala 448:131]
|
|
node _T_2227 = and(_T_2223, _T_2226) @[el2_ifu_mem_ctl.scala 448:87]
|
|
node miss_buff_hit_unq_f = or(_T_2217, _T_2227) @[el2_ifu_mem_ctl.scala 447:131]
|
|
node _T_2228 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 450:30]
|
|
node _T_2229 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 450:68]
|
|
node _T_2230 = and(miss_buff_hit_unq_f, _T_2229) @[el2_ifu_mem_ctl.scala 450:66]
|
|
node _T_2231 = and(_T_2228, _T_2230) @[el2_ifu_mem_ctl.scala 450:43]
|
|
stream_hit_f <= _T_2231 @[el2_ifu_mem_ctl.scala 450:16]
|
|
node _T_2232 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 451:31]
|
|
node _T_2233 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 451:69]
|
|
node _T_2234 = and(miss_buff_hit_unq_f, _T_2233) @[el2_ifu_mem_ctl.scala 451:67]
|
|
node _T_2235 = and(_T_2232, _T_2234) @[el2_ifu_mem_ctl.scala 451:44]
|
|
node _T_2236 = and(_T_2235, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 451:83]
|
|
stream_miss_f <= _T_2236 @[el2_ifu_mem_ctl.scala 451:17]
|
|
node _T_2237 = bits(byp_fetch_index, 4, 1) @[el2_ifu_mem_ctl.scala 452:35]
|
|
node _T_2238 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2239 = eq(_T_2237, _T_2238) @[el2_ifu_mem_ctl.scala 452:60]
|
|
node _T_2240 = and(_T_2239, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 452:92]
|
|
node _T_2241 = and(_T_2240, stream_hit_f) @[el2_ifu_mem_ctl.scala 452:110]
|
|
stream_eol_f <= _T_2241 @[el2_ifu_mem_ctl.scala 452:16]
|
|
node _T_2242 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 453:55]
|
|
node _T_2243 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 453:87]
|
|
node _T_2244 = or(_T_2242, _T_2243) @[el2_ifu_mem_ctl.scala 453:74]
|
|
node _T_2245 = and(miss_buff_hit_unq_f, _T_2244) @[el2_ifu_mem_ctl.scala 453:41]
|
|
crit_byp_hit_f <= _T_2245 @[el2_ifu_mem_ctl.scala 453:18]
|
|
node _T_2246 = bits(ifu_bus_rid_ff, 2, 1) @[el2_ifu_mem_ctl.scala 456:37]
|
|
node _T_2247 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 456:70]
|
|
node _T_2248 = eq(_T_2247, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 456:55]
|
|
node other_tag = cat(_T_2246, _T_2248) @[Cat.scala 29:58]
|
|
node _T_2249 = eq(other_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 457:81]
|
|
node _T_2250 = bits(_T_2249, 0, 0) @[el2_ifu_mem_ctl.scala 457:89]
|
|
node _T_2251 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 457:120]
|
|
node _T_2252 = eq(other_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 457:81]
|
|
node _T_2253 = bits(_T_2252, 0, 0) @[el2_ifu_mem_ctl.scala 457:89]
|
|
node _T_2254 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 457:120]
|
|
node _T_2255 = eq(other_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 457:81]
|
|
node _T_2256 = bits(_T_2255, 0, 0) @[el2_ifu_mem_ctl.scala 457:89]
|
|
node _T_2257 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 457:120]
|
|
node _T_2258 = eq(other_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 457:81]
|
|
node _T_2259 = bits(_T_2258, 0, 0) @[el2_ifu_mem_ctl.scala 457:89]
|
|
node _T_2260 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 457:120]
|
|
node _T_2261 = eq(other_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 457:81]
|
|
node _T_2262 = bits(_T_2261, 0, 0) @[el2_ifu_mem_ctl.scala 457:89]
|
|
node _T_2263 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 457:120]
|
|
node _T_2264 = eq(other_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 457:81]
|
|
node _T_2265 = bits(_T_2264, 0, 0) @[el2_ifu_mem_ctl.scala 457:89]
|
|
node _T_2266 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 457:120]
|
|
node _T_2267 = eq(other_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 457:81]
|
|
node _T_2268 = bits(_T_2267, 0, 0) @[el2_ifu_mem_ctl.scala 457:89]
|
|
node _T_2269 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 457:120]
|
|
node _T_2270 = eq(other_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 457:81]
|
|
node _T_2271 = bits(_T_2270, 0, 0) @[el2_ifu_mem_ctl.scala 457:89]
|
|
node _T_2272 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 457:120]
|
|
node _T_2273 = mux(_T_2250, _T_2251, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2274 = mux(_T_2253, _T_2254, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2275 = mux(_T_2256, _T_2257, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2276 = mux(_T_2259, _T_2260, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2277 = mux(_T_2262, _T_2263, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2278 = mux(_T_2265, _T_2266, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2279 = mux(_T_2268, _T_2269, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2280 = mux(_T_2271, _T_2272, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2281 = or(_T_2273, _T_2274) @[Mux.scala 27:72]
|
|
node _T_2282 = or(_T_2281, _T_2275) @[Mux.scala 27:72]
|
|
node _T_2283 = or(_T_2282, _T_2276) @[Mux.scala 27:72]
|
|
node _T_2284 = or(_T_2283, _T_2277) @[Mux.scala 27:72]
|
|
node _T_2285 = or(_T_2284, _T_2278) @[Mux.scala 27:72]
|
|
node _T_2286 = or(_T_2285, _T_2279) @[Mux.scala 27:72]
|
|
node _T_2287 = or(_T_2286, _T_2280) @[Mux.scala 27:72]
|
|
wire second_half_available : UInt<1> @[Mux.scala 27:72]
|
|
second_half_available <= _T_2287 @[Mux.scala 27:72]
|
|
node _T_2288 = and(second_half_available, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 458:46]
|
|
write_ic_16_bytes <= _T_2288 @[el2_ifu_mem_ctl.scala 458:21]
|
|
node _T_2289 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2290 = eq(_T_2289, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2291 = bits(_T_2290, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2292 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2293 = eq(_T_2292, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2294 = bits(_T_2293, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2295 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2296 = eq(_T_2295, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2297 = bits(_T_2296, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2298 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2299 = eq(_T_2298, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2300 = bits(_T_2299, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2301 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2302 = eq(_T_2301, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2303 = bits(_T_2302, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2304 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2305 = eq(_T_2304, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2306 = bits(_T_2305, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2307 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2308 = eq(_T_2307, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2309 = bits(_T_2308, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2310 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2311 = eq(_T_2310, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2312 = bits(_T_2311, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2313 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2314 = eq(_T_2313, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2315 = bits(_T_2314, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2316 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2317 = eq(_T_2316, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2318 = bits(_T_2317, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2319 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2320 = eq(_T_2319, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2321 = bits(_T_2320, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2322 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2323 = eq(_T_2322, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2324 = bits(_T_2323, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2325 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2326 = eq(_T_2325, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2327 = bits(_T_2326, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2328 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2329 = eq(_T_2328, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2330 = bits(_T_2329, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2331 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2332 = eq(_T_2331, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2333 = bits(_T_2332, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2334 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2335 = eq(_T_2334, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 459:89]
|
|
node _T_2336 = bits(_T_2335, 0, 0) @[el2_ifu_mem_ctl.scala 459:97]
|
|
node _T_2337 = mux(_T_2291, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2338 = mux(_T_2294, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2339 = mux(_T_2297, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2340 = mux(_T_2300, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2341 = mux(_T_2303, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2342 = mux(_T_2306, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2343 = mux(_T_2309, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2344 = mux(_T_2312, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2345 = mux(_T_2315, ic_miss_buff_data[8], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2346 = mux(_T_2318, ic_miss_buff_data[9], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2347 = mux(_T_2321, ic_miss_buff_data[10], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2348 = mux(_T_2324, ic_miss_buff_data[11], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2349 = mux(_T_2327, ic_miss_buff_data[12], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2350 = mux(_T_2330, ic_miss_buff_data[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2351 = mux(_T_2333, ic_miss_buff_data[14], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2352 = mux(_T_2336, ic_miss_buff_data[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2353 = or(_T_2337, _T_2338) @[Mux.scala 27:72]
|
|
node _T_2354 = or(_T_2353, _T_2339) @[Mux.scala 27:72]
|
|
node _T_2355 = or(_T_2354, _T_2340) @[Mux.scala 27:72]
|
|
node _T_2356 = or(_T_2355, _T_2341) @[Mux.scala 27:72]
|
|
node _T_2357 = or(_T_2356, _T_2342) @[Mux.scala 27:72]
|
|
node _T_2358 = or(_T_2357, _T_2343) @[Mux.scala 27:72]
|
|
node _T_2359 = or(_T_2358, _T_2344) @[Mux.scala 27:72]
|
|
node _T_2360 = or(_T_2359, _T_2345) @[Mux.scala 27:72]
|
|
node _T_2361 = or(_T_2360, _T_2346) @[Mux.scala 27:72]
|
|
node _T_2362 = or(_T_2361, _T_2347) @[Mux.scala 27:72]
|
|
node _T_2363 = or(_T_2362, _T_2348) @[Mux.scala 27:72]
|
|
node _T_2364 = or(_T_2363, _T_2349) @[Mux.scala 27:72]
|
|
node _T_2365 = or(_T_2364, _T_2350) @[Mux.scala 27:72]
|
|
node _T_2366 = or(_T_2365, _T_2351) @[Mux.scala 27:72]
|
|
node _T_2367 = or(_T_2366, _T_2352) @[Mux.scala 27:72]
|
|
wire _T_2368 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2368 <= _T_2367 @[Mux.scala 27:72]
|
|
node _T_2369 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2370 = eq(_T_2369, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 460:64]
|
|
node _T_2371 = bits(_T_2370, 0, 0) @[el2_ifu_mem_ctl.scala 460:72]
|
|
node _T_2372 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2373 = eq(_T_2372, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 460:64]
|
|
node _T_2374 = bits(_T_2373, 0, 0) @[el2_ifu_mem_ctl.scala 460:72]
|
|
node _T_2375 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2376 = eq(_T_2375, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 460:64]
|
|
node _T_2377 = bits(_T_2376, 0, 0) @[el2_ifu_mem_ctl.scala 460:72]
|
|
node _T_2378 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2379 = eq(_T_2378, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 460:64]
|
|
node _T_2380 = bits(_T_2379, 0, 0) @[el2_ifu_mem_ctl.scala 460:72]
|
|
node _T_2381 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2382 = eq(_T_2381, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 460:64]
|
|
node _T_2383 = bits(_T_2382, 0, 0) @[el2_ifu_mem_ctl.scala 460:72]
|
|
node _T_2384 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2385 = eq(_T_2384, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 460:64]
|
|
node _T_2386 = bits(_T_2385, 0, 0) @[el2_ifu_mem_ctl.scala 460:72]
|
|
node _T_2387 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2388 = eq(_T_2387, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 460:64]
|
|
node _T_2389 = bits(_T_2388, 0, 0) @[el2_ifu_mem_ctl.scala 460:72]
|
|
node _T_2390 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2391 = eq(_T_2390, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 460:64]
|
|
node _T_2392 = bits(_T_2391, 0, 0) @[el2_ifu_mem_ctl.scala 460:72]
|
|
node _T_2393 = mux(_T_2371, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2394 = mux(_T_2374, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2395 = mux(_T_2377, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2396 = mux(_T_2380, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2397 = mux(_T_2383, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2398 = mux(_T_2386, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2399 = mux(_T_2389, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2400 = mux(_T_2392, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2401 = or(_T_2393, _T_2394) @[Mux.scala 27:72]
|
|
node _T_2402 = or(_T_2401, _T_2395) @[Mux.scala 27:72]
|
|
node _T_2403 = or(_T_2402, _T_2396) @[Mux.scala 27:72]
|
|
node _T_2404 = or(_T_2403, _T_2397) @[Mux.scala 27:72]
|
|
node _T_2405 = or(_T_2404, _T_2398) @[Mux.scala 27:72]
|
|
node _T_2406 = or(_T_2405, _T_2399) @[Mux.scala 27:72]
|
|
node _T_2407 = or(_T_2406, _T_2400) @[Mux.scala 27:72]
|
|
wire _T_2408 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2408 <= _T_2407 @[Mux.scala 27:72]
|
|
node _T_2409 = cat(_T_2368, _T_2408) @[Cat.scala 29:58]
|
|
ic_miss_buff_half <= _T_2409 @[el2_ifu_mem_ctl.scala 459:21]
|
|
node _T_2410 = and(io.ic_tag_perr, sel_ic_data) @[el2_ifu_mem_ctl.scala 462:44]
|
|
node _T_2411 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 462:91]
|
|
node _T_2412 = eq(_T_2411, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 462:60]
|
|
node _T_2413 = and(_T_2410, _T_2412) @[el2_ifu_mem_ctl.scala 462:58]
|
|
ic_rd_parity_final_err <= _T_2413 @[el2_ifu_mem_ctl.scala 462:26]
|
|
wire ifu_ic_rw_int_addr_ff : UInt<6>
|
|
ifu_ic_rw_int_addr_ff <= UInt<1>("h00")
|
|
wire perr_sb_write_status : UInt<1>
|
|
perr_sb_write_status <= UInt<1>("h00")
|
|
reg perr_ic_index_ff : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when perr_sb_write_status : @[Reg.scala 28:19]
|
|
perr_ic_index_ff <= ifu_ic_rw_int_addr_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
wire perr_sel_invalidate : UInt<1>
|
|
perr_sel_invalidate <= UInt<1>("h00")
|
|
node _T_2414 = bits(perr_sel_invalidate, 0, 0) @[Bitwise.scala 72:15]
|
|
node perr_err_inv_way = mux(_T_2414, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2415 = eq(perr_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 469:34]
|
|
iccm_correct_ecc <= _T_2415 @[el2_ifu_mem_ctl.scala 469:20]
|
|
node dma_sb_err_state = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 470:37]
|
|
wire dma_sb_err_state_ff : UInt<1> @[el2_ifu_mem_ctl.scala 471:33]
|
|
node _T_2416 = eq(dma_sb_err_state_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 472:49]
|
|
node _T_2417 = and(iccm_correct_ecc, _T_2416) @[el2_ifu_mem_ctl.scala 472:47]
|
|
io.iccm_buf_correct_ecc <= _T_2417 @[el2_ifu_mem_ctl.scala 472:27]
|
|
reg _T_2418 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 473:58]
|
|
_T_2418 <= dma_sb_err_state @[el2_ifu_mem_ctl.scala 473:58]
|
|
dma_sb_err_state_ff <= _T_2418 @[el2_ifu_mem_ctl.scala 473:23]
|
|
wire perr_nxtstate : UInt<3>
|
|
perr_nxtstate <= UInt<1>("h00")
|
|
wire perr_state_en : UInt<1>
|
|
perr_state_en <= UInt<1>("h00")
|
|
wire iccm_error_start : UInt<1>
|
|
iccm_error_start <= UInt<1>("h00")
|
|
node _T_2419 = eq(UInt<3>("h00"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2419 : @[Conditional.scala 40:58]
|
|
node _T_2420 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 481:89]
|
|
node _T_2421 = and(io.ic_error_start, _T_2420) @[el2_ifu_mem_ctl.scala 481:87]
|
|
node _T_2422 = bits(_T_2421, 0, 0) @[el2_ifu_mem_ctl.scala 481:110]
|
|
node _T_2423 = mux(_T_2422, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 481:67]
|
|
node _T_2424 = mux(io.iccm_dma_sb_error, UInt<3>("h04"), _T_2423) @[el2_ifu_mem_ctl.scala 481:27]
|
|
perr_nxtstate <= _T_2424 @[el2_ifu_mem_ctl.scala 481:21]
|
|
node _T_2425 = or(iccm_error_start, io.ic_error_start) @[el2_ifu_mem_ctl.scala 482:44]
|
|
node _T_2426 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 482:67]
|
|
node _T_2427 = and(_T_2425, _T_2426) @[el2_ifu_mem_ctl.scala 482:65]
|
|
node _T_2428 = or(_T_2427, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 482:88]
|
|
node _T_2429 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 482:114]
|
|
node _T_2430 = and(_T_2428, _T_2429) @[el2_ifu_mem_ctl.scala 482:112]
|
|
perr_state_en <= _T_2430 @[el2_ifu_mem_ctl.scala 482:21]
|
|
perr_sb_write_status <= perr_state_en @[el2_ifu_mem_ctl.scala 483:28]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2431 = eq(UInt<3>("h01"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2431 : @[Conditional.scala 39:67]
|
|
perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 486:21]
|
|
node _T_2432 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 487:50]
|
|
perr_state_en <= _T_2432 @[el2_ifu_mem_ctl.scala 487:21]
|
|
node _T_2433 = and(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 488:56]
|
|
perr_sel_invalidate <= _T_2433 @[el2_ifu_mem_ctl.scala 488:27]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2434 = eq(UInt<3>("h02"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2434 : @[Conditional.scala 39:67]
|
|
node _T_2435 = and(io.dec_tlu_flush_err_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_mem_ctl.scala 491:54]
|
|
node _T_2436 = or(_T_2435, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 491:84]
|
|
node _T_2437 = bits(_T_2436, 0, 0) @[el2_ifu_mem_ctl.scala 491:115]
|
|
node _T_2438 = mux(_T_2437, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 491:27]
|
|
perr_nxtstate <= _T_2438 @[el2_ifu_mem_ctl.scala 491:21]
|
|
node _T_2439 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 492:50]
|
|
perr_state_en <= _T_2439 @[el2_ifu_mem_ctl.scala 492:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2440 = eq(UInt<3>("h04"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2440 : @[Conditional.scala 39:67]
|
|
node _T_2441 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 495:27]
|
|
perr_nxtstate <= _T_2441 @[el2_ifu_mem_ctl.scala 495:21]
|
|
perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 496:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2442 = eq(UInt<3>("h03"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2442 : @[Conditional.scala 39:67]
|
|
perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 499:21]
|
|
perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 500:21]
|
|
skip @[Conditional.scala 39:67]
|
|
reg _T_2443 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when perr_state_en : @[Reg.scala 28:19]
|
|
_T_2443 <= perr_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
perr_state <= _T_2443 @[el2_ifu_mem_ctl.scala 503:14]
|
|
wire err_stop_nxtstate : UInt<2>
|
|
err_stop_nxtstate <= UInt<1>("h00")
|
|
wire err_stop_state_en : UInt<1>
|
|
err_stop_state_en <= UInt<1>("h00")
|
|
io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 507:28]
|
|
node _T_2444 = eq(UInt<2>("h00"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2444 : @[Conditional.scala 40:58]
|
|
err_stop_nxtstate <= UInt<2>("h01") @[el2_ifu_mem_ctl.scala 511:25]
|
|
node _T_2445 = eq(perr_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 512:66]
|
|
node _T_2446 = and(io.dec_tlu_flush_err_wb, _T_2445) @[el2_ifu_mem_ctl.scala 512:52]
|
|
node _T_2447 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 512:83]
|
|
node _T_2448 = and(_T_2446, _T_2447) @[el2_ifu_mem_ctl.scala 512:81]
|
|
err_stop_state_en <= _T_2448 @[el2_ifu_mem_ctl.scala 512:25]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2449 = eq(UInt<2>("h01"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2449 : @[Conditional.scala 39:67]
|
|
node _T_2450 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 515:59]
|
|
node _T_2451 = or(_T_2450, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 515:86]
|
|
node _T_2452 = bits(_T_2451, 0, 0) @[el2_ifu_mem_ctl.scala 515:117]
|
|
node _T_2453 = eq(io.ifu_fetch_val, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 516:31]
|
|
node _T_2454 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 516:56]
|
|
node _T_2455 = and(_T_2454, two_byte_instr) @[el2_ifu_mem_ctl.scala 516:59]
|
|
node _T_2456 = or(_T_2453, _T_2455) @[el2_ifu_mem_ctl.scala 516:38]
|
|
node _T_2457 = bits(_T_2456, 0, 0) @[el2_ifu_mem_ctl.scala 516:83]
|
|
node _T_2458 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 517:31]
|
|
node _T_2459 = bits(_T_2458, 0, 0) @[el2_ifu_mem_ctl.scala 517:41]
|
|
node _T_2460 = mux(_T_2459, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_mem_ctl.scala 517:14]
|
|
node _T_2461 = mux(_T_2457, UInt<2>("h03"), _T_2460) @[el2_ifu_mem_ctl.scala 516:12]
|
|
node _T_2462 = mux(_T_2452, UInt<2>("h00"), _T_2461) @[el2_ifu_mem_ctl.scala 515:31]
|
|
err_stop_nxtstate <= _T_2462 @[el2_ifu_mem_ctl.scala 515:25]
|
|
node _T_2463 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 518:54]
|
|
node _T_2464 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 518:99]
|
|
node _T_2465 = or(_T_2463, _T_2464) @[el2_ifu_mem_ctl.scala 518:81]
|
|
node _T_2466 = or(_T_2465, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 518:103]
|
|
node _T_2467 = or(_T_2466, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 518:126]
|
|
err_stop_state_en <= _T_2467 @[el2_ifu_mem_ctl.scala 518:25]
|
|
node _T_2468 = bits(io.ifu_fetch_val, 1, 0) @[el2_ifu_mem_ctl.scala 519:43]
|
|
node _T_2469 = eq(_T_2468, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 519:48]
|
|
node _T_2470 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 519:75]
|
|
node _T_2471 = and(_T_2470, two_byte_instr) @[el2_ifu_mem_ctl.scala 519:79]
|
|
node _T_2472 = or(_T_2469, _T_2471) @[el2_ifu_mem_ctl.scala 519:56]
|
|
node _T_2473 = or(io.exu_flush_final, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 519:122]
|
|
node _T_2474 = eq(_T_2473, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 519:101]
|
|
node _T_2475 = and(_T_2472, _T_2474) @[el2_ifu_mem_ctl.scala 519:99]
|
|
err_stop_fetch <= _T_2475 @[el2_ifu_mem_ctl.scala 519:22]
|
|
io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 520:32]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2476 = eq(UInt<2>("h02"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2476 : @[Conditional.scala 39:67]
|
|
node _T_2477 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 523:59]
|
|
node _T_2478 = or(_T_2477, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 523:86]
|
|
node _T_2479 = bits(_T_2478, 0, 0) @[el2_ifu_mem_ctl.scala 523:111]
|
|
node _T_2480 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 524:46]
|
|
node _T_2481 = bits(_T_2480, 0, 0) @[el2_ifu_mem_ctl.scala 524:50]
|
|
node _T_2482 = mux(_T_2481, UInt<2>("h03"), UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 524:29]
|
|
node _T_2483 = mux(_T_2479, UInt<2>("h00"), _T_2482) @[el2_ifu_mem_ctl.scala 523:31]
|
|
err_stop_nxtstate <= _T_2483 @[el2_ifu_mem_ctl.scala 523:25]
|
|
node _T_2484 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 525:54]
|
|
node _T_2485 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 525:99]
|
|
node _T_2486 = or(_T_2484, _T_2485) @[el2_ifu_mem_ctl.scala 525:81]
|
|
node _T_2487 = or(_T_2486, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 525:103]
|
|
err_stop_state_en <= _T_2487 @[el2_ifu_mem_ctl.scala 525:25]
|
|
node _T_2488 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 526:41]
|
|
node _T_2489 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 526:47]
|
|
node _T_2490 = and(_T_2488, _T_2489) @[el2_ifu_mem_ctl.scala 526:45]
|
|
node _T_2491 = eq(io.dec_tlu_i0_commit_cmt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 526:69]
|
|
node _T_2492 = and(_T_2490, _T_2491) @[el2_ifu_mem_ctl.scala 526:67]
|
|
err_stop_fetch <= _T_2492 @[el2_ifu_mem_ctl.scala 526:22]
|
|
io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 527:32]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2493 = eq(UInt<2>("h03"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2493 : @[Conditional.scala 39:67]
|
|
node _T_2494 = eq(io.dec_tlu_flush_err_wb, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 530:62]
|
|
node _T_2495 = and(io.dec_tlu_flush_lower_wb, _T_2494) @[el2_ifu_mem_ctl.scala 530:60]
|
|
node _T_2496 = or(_T_2495, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 530:88]
|
|
node _T_2497 = or(_T_2496, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 530:115]
|
|
node _T_2498 = bits(_T_2497, 0, 0) @[el2_ifu_mem_ctl.scala 530:140]
|
|
node _T_2499 = bits(io.dec_tlu_flush_err_wb, 0, 0) @[el2_ifu_mem_ctl.scala 531:60]
|
|
node _T_2500 = mux(_T_2499, UInt<2>("h01"), UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 531:29]
|
|
node _T_2501 = mux(_T_2498, UInt<2>("h00"), _T_2500) @[el2_ifu_mem_ctl.scala 530:31]
|
|
err_stop_nxtstate <= _T_2501 @[el2_ifu_mem_ctl.scala 530:25]
|
|
node _T_2502 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 532:54]
|
|
node _T_2503 = or(_T_2502, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 532:81]
|
|
err_stop_state_en <= _T_2503 @[el2_ifu_mem_ctl.scala 532:25]
|
|
err_stop_fetch <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 533:22]
|
|
io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 534:32]
|
|
skip @[Conditional.scala 39:67]
|
|
reg _T_2504 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when err_stop_state_en : @[Reg.scala 28:19]
|
|
_T_2504 <= err_stop_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
err_stop_state <= _T_2504 @[el2_ifu_mem_ctl.scala 537:18]
|
|
bus_ifu_bus_clk_en <= io.ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 538:22]
|
|
reg bus_ifu_bus_clk_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 539:61]
|
|
bus_ifu_bus_clk_en_ff <= bus_ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 539:61]
|
|
reg _T_2505 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 540:52]
|
|
_T_2505 <= scnd_miss_req_in @[el2_ifu_mem_ctl.scala 540:52]
|
|
scnd_miss_req_q <= _T_2505 @[el2_ifu_mem_ctl.scala 540:19]
|
|
reg scnd_miss_req_ff2 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 541:57]
|
|
scnd_miss_req_ff2 <= scnd_miss_req @[el2_ifu_mem_ctl.scala 541:57]
|
|
node _T_2506 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 542:39]
|
|
node _T_2507 = and(scnd_miss_req_q, _T_2506) @[el2_ifu_mem_ctl.scala 542:36]
|
|
scnd_miss_req <= _T_2507 @[el2_ifu_mem_ctl.scala 542:17]
|
|
wire bus_cmd_req_hold : UInt<1>
|
|
bus_cmd_req_hold <= UInt<1>("h00")
|
|
wire ifu_bus_cmd_valid : UInt<1>
|
|
ifu_bus_cmd_valid <= UInt<1>("h00")
|
|
wire bus_cmd_beat_count : UInt<3>
|
|
bus_cmd_beat_count <= UInt<1>("h00")
|
|
wire ifu_bus_cmd_ready : UInt<1>
|
|
ifu_bus_cmd_ready <= UInt<1>("h00")
|
|
node _T_2508 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 547:45]
|
|
node _T_2509 = or(_T_2508, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 547:64]
|
|
node _T_2510 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 547:87]
|
|
node _T_2511 = and(_T_2509, _T_2510) @[el2_ifu_mem_ctl.scala 547:85]
|
|
node _T_2512 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2513 = eq(bus_cmd_beat_count, _T_2512) @[el2_ifu_mem_ctl.scala 547:133]
|
|
node _T_2514 = and(_T_2513, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 547:164]
|
|
node _T_2515 = and(_T_2514, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 547:184]
|
|
node _T_2516 = and(_T_2515, miss_pending) @[el2_ifu_mem_ctl.scala 547:204]
|
|
node _T_2517 = eq(_T_2516, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 547:112]
|
|
node ifc_bus_ic_req_ff_in = and(_T_2511, _T_2517) @[el2_ifu_mem_ctl.scala 547:110]
|
|
node _T_2518 = or(bus_ifu_bus_clk_en, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 548:80]
|
|
reg _T_2519 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_2518 : @[Reg.scala 28:19]
|
|
_T_2519 <= ifc_bus_ic_req_ff_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_cmd_valid <= _T_2519 @[el2_ifu_mem_ctl.scala 548:21]
|
|
wire bus_cmd_sent : UInt<1>
|
|
bus_cmd_sent <= UInt<1>("h00")
|
|
node _T_2520 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 550:39]
|
|
node _T_2521 = eq(bus_cmd_sent, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 550:61]
|
|
node _T_2522 = and(_T_2520, _T_2521) @[el2_ifu_mem_ctl.scala 550:59]
|
|
node _T_2523 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 550:77]
|
|
node bus_cmd_req_in = and(_T_2522, _T_2523) @[el2_ifu_mem_ctl.scala 550:75]
|
|
reg _T_2524 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 551:49]
|
|
_T_2524 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 551:49]
|
|
bus_cmd_sent <= _T_2524 @[el2_ifu_mem_ctl.scala 551:16]
|
|
io.ifu_axi_arvalid <= ifu_bus_cmd_valid @[el2_ifu_mem_ctl.scala 553:22]
|
|
node _T_2525 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2526 = mux(_T_2525, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2527 = and(bus_rd_addr_count, _T_2526) @[el2_ifu_mem_ctl.scala 554:40]
|
|
io.ifu_axi_arid <= _T_2527 @[el2_ifu_mem_ctl.scala 554:19]
|
|
node _T_2528 = cat(ifu_ic_req_addr_f, UInt<3>("h00")) @[Cat.scala 29:58]
|
|
node _T_2529 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2530 = mux(_T_2529, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2531 = and(_T_2528, _T_2530) @[el2_ifu_mem_ctl.scala 555:57]
|
|
io.ifu_axi_araddr <= _T_2531 @[el2_ifu_mem_ctl.scala 555:21]
|
|
io.ifu_axi_arsize <= UInt<3>("h03") @[el2_ifu_mem_ctl.scala 556:21]
|
|
io.ifu_axi_arcache <= UInt<4>("h0f") @[el2_ifu_mem_ctl.scala 557:22]
|
|
node _T_2532 = bits(ifu_ic_req_addr_f, 28, 25) @[el2_ifu_mem_ctl.scala 558:43]
|
|
io.ifu_axi_arregion <= _T_2532 @[el2_ifu_mem_ctl.scala 558:23]
|
|
io.ifu_axi_arburst <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 559:22]
|
|
io.ifu_axi_rready <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 560:21]
|
|
reg ifu_bus_arready_unq_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_arready_unq_ff <= io.ifu_axi_arready @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_rvalid_unq_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_rvalid_unq_ff <= io.ifu_axi_rvalid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_arvalid_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_arvalid_ff <= io.ifu_axi_arvalid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_rresp_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_rresp_ff <= io.ifu_axi_rresp @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg _T_2533 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
_T_2533 <= io.ifu_axi_rdata @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_rdata_ff <= _T_2533 @[el2_ifu_mem_ctl.scala 570:20]
|
|
reg _T_2534 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
_T_2534 <= io.ifu_axi_rid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_rid_ff <= _T_2534 @[el2_ifu_mem_ctl.scala 571:18]
|
|
ifu_bus_cmd_ready <= io.ifu_axi_arready @[el2_ifu_mem_ctl.scala 572:21]
|
|
ifu_bus_rsp_valid <= io.ifu_axi_rvalid @[el2_ifu_mem_ctl.scala 573:21]
|
|
ifu_bus_rsp_ready <= io.ifu_axi_rready @[el2_ifu_mem_ctl.scala 574:21]
|
|
ifu_bus_rsp_tag <= io.ifu_axi_rid @[el2_ifu_mem_ctl.scala 575:19]
|
|
ic_miss_buff_data_in <= io.ifu_axi_rdata @[el2_ifu_mem_ctl.scala 576:21]
|
|
node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 578:42]
|
|
node ifu_bus_arready = and(io.ifu_axi_arready, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 579:45]
|
|
node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 580:51]
|
|
node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 581:49]
|
|
node _T_2535 = and(io.ifu_axi_arvalid, ifu_bus_arready) @[el2_ifu_mem_ctl.scala 582:35]
|
|
node _T_2536 = and(_T_2535, miss_pending) @[el2_ifu_mem_ctl.scala 582:53]
|
|
node _T_2537 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 582:70]
|
|
node _T_2538 = and(_T_2536, _T_2537) @[el2_ifu_mem_ctl.scala 582:68]
|
|
bus_cmd_sent <= _T_2538 @[el2_ifu_mem_ctl.scala 582:16]
|
|
wire bus_last_data_beat : UInt<1>
|
|
bus_last_data_beat <= UInt<1>("h00")
|
|
node _T_2539 = eq(bus_last_data_beat, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 584:50]
|
|
node _T_2540 = and(bus_ifu_wr_en_ff, _T_2539) @[el2_ifu_mem_ctl.scala 584:48]
|
|
node _T_2541 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 584:72]
|
|
node bus_inc_data_beat_cnt = and(_T_2540, _T_2541) @[el2_ifu_mem_ctl.scala 584:70]
|
|
node _T_2542 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 585:68]
|
|
node _T_2543 = or(ic_act_miss_f, _T_2542) @[el2_ifu_mem_ctl.scala 585:48]
|
|
node bus_reset_data_beat_cnt = or(_T_2543, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 585:91]
|
|
node _T_2544 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 586:32]
|
|
node _T_2545 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 586:57]
|
|
node bus_hold_data_beat_cnt = and(_T_2544, _T_2545) @[el2_ifu_mem_ctl.scala 586:55]
|
|
wire bus_data_beat_count : UInt<3>
|
|
bus_data_beat_count <= UInt<1>("h00")
|
|
node _T_2546 = add(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 588:115]
|
|
node _T_2547 = tail(_T_2546, 1) @[el2_ifu_mem_ctl.scala 588:115]
|
|
node _T_2548 = mux(bus_reset_data_beat_cnt, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2549 = mux(bus_inc_data_beat_cnt, _T_2547, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2550 = mux(bus_hold_data_beat_cnt, bus_data_beat_count, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2551 = or(_T_2548, _T_2549) @[Mux.scala 27:72]
|
|
node _T_2552 = or(_T_2551, _T_2550) @[Mux.scala 27:72]
|
|
wire _T_2553 : UInt<3> @[Mux.scala 27:72]
|
|
_T_2553 <= _T_2552 @[Mux.scala 27:72]
|
|
bus_new_data_beat_count <= _T_2553 @[el2_ifu_mem_ctl.scala 588:27]
|
|
reg _T_2554 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 589:56]
|
|
_T_2554 <= bus_new_data_beat_count @[el2_ifu_mem_ctl.scala 589:56]
|
|
bus_data_beat_count <= _T_2554 @[el2_ifu_mem_ctl.scala 589:23]
|
|
node _T_2555 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 590:49]
|
|
node _T_2556 = eq(scnd_miss_req, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 590:73]
|
|
node _T_2557 = and(_T_2555, _T_2556) @[el2_ifu_mem_ctl.scala 590:71]
|
|
node _T_2558 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 590:116]
|
|
node _T_2559 = and(last_data_recieved_ff, _T_2558) @[el2_ifu_mem_ctl.scala 590:114]
|
|
node last_data_recieved_in = or(_T_2557, _T_2559) @[el2_ifu_mem_ctl.scala 590:89]
|
|
reg _T_2560 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 591:58]
|
|
_T_2560 <= last_data_recieved_in @[el2_ifu_mem_ctl.scala 591:58]
|
|
last_data_recieved_ff <= _T_2560 @[el2_ifu_mem_ctl.scala 591:25]
|
|
node _T_2561 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 593:35]
|
|
node _T_2562 = bits(imb_ff, 4, 2) @[el2_ifu_mem_ctl.scala 593:56]
|
|
node _T_2563 = bits(imb_scnd_ff, 4, 2) @[el2_ifu_mem_ctl.scala 594:39]
|
|
node _T_2564 = add(bus_rd_addr_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 595:45]
|
|
node _T_2565 = tail(_T_2564, 1) @[el2_ifu_mem_ctl.scala 595:45]
|
|
node _T_2566 = mux(bus_cmd_sent, _T_2565, bus_rd_addr_count) @[el2_ifu_mem_ctl.scala 595:12]
|
|
node _T_2567 = mux(scnd_miss_req_q, _T_2563, _T_2566) @[el2_ifu_mem_ctl.scala 594:10]
|
|
node bus_new_rd_addr_count = mux(_T_2561, _T_2562, _T_2567) @[el2_ifu_mem_ctl.scala 593:34]
|
|
node _T_2568 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 596:81]
|
|
node _T_2569 = or(_T_2568, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 596:97]
|
|
reg _T_2570 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_2569 : @[Reg.scala 28:19]
|
|
_T_2570 <= bus_new_rd_addr_count @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
bus_rd_addr_count <= _T_2570 @[el2_ifu_mem_ctl.scala 596:21]
|
|
node _T_2571 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 598:48]
|
|
node _T_2572 = and(_T_2571, miss_pending) @[el2_ifu_mem_ctl.scala 598:68]
|
|
node _T_2573 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 598:85]
|
|
node bus_inc_cmd_beat_cnt = and(_T_2572, _T_2573) @[el2_ifu_mem_ctl.scala 598:83]
|
|
node _T_2574 = eq(uncacheable_miss_in, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 599:51]
|
|
node _T_2575 = and(ic_act_miss_f, _T_2574) @[el2_ifu_mem_ctl.scala 599:49]
|
|
node bus_reset_cmd_beat_cnt_0 = or(_T_2575, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 599:73]
|
|
node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[el2_ifu_mem_ctl.scala 600:57]
|
|
node _T_2576 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 601:31]
|
|
node _T_2577 = or(ic_act_miss_f, scnd_miss_req) @[el2_ifu_mem_ctl.scala 601:71]
|
|
node _T_2578 = or(_T_2577, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 601:87]
|
|
node _T_2579 = eq(_T_2578, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 601:55]
|
|
node bus_hold_cmd_beat_cnt = and(_T_2576, _T_2579) @[el2_ifu_mem_ctl.scala 601:53]
|
|
node _T_2580 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 602:46]
|
|
node bus_cmd_beat_en = or(_T_2580, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 602:62]
|
|
node _T_2581 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[el2_ifu_mem_ctl.scala 603:107]
|
|
node _T_2582 = add(bus_cmd_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 604:46]
|
|
node _T_2583 = tail(_T_2582, 1) @[el2_ifu_mem_ctl.scala 604:46]
|
|
node _T_2584 = mux(bus_reset_cmd_beat_cnt_0, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2585 = mux(_T_2581, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2586 = mux(bus_inc_cmd_beat_cnt, _T_2583, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2587 = mux(bus_hold_cmd_beat_cnt, bus_cmd_beat_count, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2588 = or(_T_2584, _T_2585) @[Mux.scala 27:72]
|
|
node _T_2589 = or(_T_2588, _T_2586) @[Mux.scala 27:72]
|
|
node _T_2590 = or(_T_2589, _T_2587) @[Mux.scala 27:72]
|
|
wire bus_new_cmd_beat_count : UInt<3> @[Mux.scala 27:72]
|
|
bus_new_cmd_beat_count <= _T_2590 @[Mux.scala 27:72]
|
|
node _T_2591 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 605:84]
|
|
node _T_2592 = or(_T_2591, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 605:100]
|
|
node _T_2593 = and(_T_2592, bus_cmd_beat_en) @[el2_ifu_mem_ctl.scala 605:125]
|
|
reg _T_2594 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_2593 : @[Reg.scala 28:19]
|
|
_T_2594 <= bus_new_cmd_beat_count @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
bus_cmd_beat_count <= _T_2594 @[el2_ifu_mem_ctl.scala 605:22]
|
|
node _T_2595 = eq(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 606:69]
|
|
node _T_2596 = andr(bus_data_beat_count) @[el2_ifu_mem_ctl.scala 606:101]
|
|
node _T_2597 = mux(uncacheable_miss_ff, _T_2595, _T_2596) @[el2_ifu_mem_ctl.scala 606:28]
|
|
bus_last_data_beat <= _T_2597 @[el2_ifu_mem_ctl.scala 606:22]
|
|
node _T_2598 = and(ifu_bus_rvalid, miss_pending) @[el2_ifu_mem_ctl.scala 607:35]
|
|
bus_ifu_wr_en <= _T_2598 @[el2_ifu_mem_ctl.scala 607:17]
|
|
node _T_2599 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 608:41]
|
|
bus_ifu_wr_en_ff <= _T_2599 @[el2_ifu_mem_ctl.scala 608:20]
|
|
node _T_2600 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 609:44]
|
|
node _T_2601 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 609:61]
|
|
node _T_2602 = and(_T_2600, _T_2601) @[el2_ifu_mem_ctl.scala 609:59]
|
|
node _T_2603 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 609:103]
|
|
node _T_2604 = eq(_T_2603, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 609:84]
|
|
node _T_2605 = and(_T_2602, _T_2604) @[el2_ifu_mem_ctl.scala 609:82]
|
|
node _T_2606 = and(_T_2605, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 609:108]
|
|
bus_ifu_wr_en_ff_q <= _T_2606 @[el2_ifu_mem_ctl.scala 609:22]
|
|
node _T_2607 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 610:51]
|
|
node _T_2608 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 610:68]
|
|
node bus_ifu_wr_en_ff_wo_err = and(_T_2607, _T_2608) @[el2_ifu_mem_ctl.scala 610:66]
|
|
reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 611:61]
|
|
ic_act_miss_f_delayed <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 611:61]
|
|
node _T_2609 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 612:66]
|
|
node _T_2610 = and(ic_act_miss_f_delayed, _T_2609) @[el2_ifu_mem_ctl.scala 612:53]
|
|
node _T_2611 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 612:86]
|
|
node _T_2612 = and(_T_2610, _T_2611) @[el2_ifu_mem_ctl.scala 612:84]
|
|
reset_tag_valid_for_miss <= _T_2612 @[el2_ifu_mem_ctl.scala 612:28]
|
|
node _T_2613 = orr(io.ifu_axi_rresp) @[el2_ifu_mem_ctl.scala 613:47]
|
|
node _T_2614 = and(_T_2613, ifu_bus_rvalid) @[el2_ifu_mem_ctl.scala 613:50]
|
|
node _T_2615 = and(_T_2614, miss_pending) @[el2_ifu_mem_ctl.scala 613:68]
|
|
bus_ifu_wr_data_error <= _T_2615 @[el2_ifu_mem_ctl.scala 613:25]
|
|
node _T_2616 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 614:48]
|
|
node _T_2617 = and(_T_2616, ifu_bus_rvalid_ff) @[el2_ifu_mem_ctl.scala 614:52]
|
|
node _T_2618 = and(_T_2617, miss_pending) @[el2_ifu_mem_ctl.scala 614:73]
|
|
bus_ifu_wr_data_error_ff <= _T_2618 @[el2_ifu_mem_ctl.scala 614:28]
|
|
wire ifc_dma_access_ok_d : UInt<1>
|
|
ifc_dma_access_ok_d <= UInt<1>("h00")
|
|
reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 616:62]
|
|
ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[el2_ifu_mem_ctl.scala 616:62]
|
|
node _T_2619 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[el2_ifu_mem_ctl.scala 617:43]
|
|
ic_crit_wd_rdy <= _T_2619 @[el2_ifu_mem_ctl.scala 617:18]
|
|
node _T_2620 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 618:35]
|
|
last_beat <= _T_2620 @[el2_ifu_mem_ctl.scala 618:13]
|
|
reset_beat_cnt <= bus_reset_data_beat_cnt @[el2_ifu_mem_ctl.scala 619:18]
|
|
node _T_2621 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 621:50]
|
|
node _T_2622 = and(io.ifc_dma_access_ok, _T_2621) @[el2_ifu_mem_ctl.scala 621:47]
|
|
node _T_2623 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 621:70]
|
|
node _T_2624 = and(_T_2622, _T_2623) @[el2_ifu_mem_ctl.scala 621:68]
|
|
ifc_dma_access_ok_d <= _T_2624 @[el2_ifu_mem_ctl.scala 621:23]
|
|
node _T_2625 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 622:54]
|
|
node _T_2626 = and(io.ifc_dma_access_ok, _T_2625) @[el2_ifu_mem_ctl.scala 622:51]
|
|
node _T_2627 = and(_T_2626, ifc_dma_access_ok_prev) @[el2_ifu_mem_ctl.scala 622:72]
|
|
node _T_2628 = eq(perr_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 622:111]
|
|
node _T_2629 = and(_T_2627, _T_2628) @[el2_ifu_mem_ctl.scala 622:97]
|
|
node _T_2630 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 622:129]
|
|
node ifc_dma_access_q_ok = and(_T_2629, _T_2630) @[el2_ifu_mem_ctl.scala 622:127]
|
|
io.iccm_ready <= ifc_dma_access_q_ok @[el2_ifu_mem_ctl.scala 623:17]
|
|
reg _T_2631 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 624:51]
|
|
_T_2631 <= io.dma_iccm_req @[el2_ifu_mem_ctl.scala 624:51]
|
|
dma_iccm_req_f <= _T_2631 @[el2_ifu_mem_ctl.scala 624:18]
|
|
node _T_2632 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 625:40]
|
|
node _T_2633 = and(_T_2632, io.dma_mem_write) @[el2_ifu_mem_ctl.scala 625:58]
|
|
node _T_2634 = or(_T_2633, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 625:79]
|
|
io.iccm_wren <= _T_2634 @[el2_ifu_mem_ctl.scala 625:16]
|
|
node _T_2635 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 626:40]
|
|
node _T_2636 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 626:60]
|
|
node _T_2637 = and(_T_2635, _T_2636) @[el2_ifu_mem_ctl.scala 626:58]
|
|
node _T_2638 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 626:104]
|
|
node _T_2639 = or(_T_2637, _T_2638) @[el2_ifu_mem_ctl.scala 626:79]
|
|
io.iccm_rden <= _T_2639 @[el2_ifu_mem_ctl.scala 626:16]
|
|
node _T_2640 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 627:43]
|
|
node _T_2641 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 627:63]
|
|
node iccm_dma_rden = and(_T_2640, _T_2641) @[el2_ifu_mem_ctl.scala 627:61]
|
|
node _T_2642 = bits(io.dma_iccm_req, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2643 = mux(_T_2642, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2644 = and(_T_2643, io.dma_mem_sz) @[el2_ifu_mem_ctl.scala 628:47]
|
|
io.iccm_wr_size <= _T_2644 @[el2_ifu_mem_ctl.scala 628:19]
|
|
node _T_2645 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 629:54]
|
|
wire _T_2646 : UInt<1>[18] @[el2_lib.scala 250:18]
|
|
wire _T_2647 : UInt<1>[18] @[el2_lib.scala 251:18]
|
|
wire _T_2648 : UInt<1>[18] @[el2_lib.scala 252:18]
|
|
wire _T_2649 : UInt<1>[15] @[el2_lib.scala 253:18]
|
|
wire _T_2650 : UInt<1>[15] @[el2_lib.scala 254:18]
|
|
wire _T_2651 : UInt<1>[6] @[el2_lib.scala 255:18]
|
|
node _T_2652 = bits(_T_2645, 0, 0) @[el2_lib.scala 262:36]
|
|
_T_2647[0] <= _T_2652 @[el2_lib.scala 262:30]
|
|
node _T_2653 = bits(_T_2645, 0, 0) @[el2_lib.scala 263:36]
|
|
_T_2648[0] <= _T_2653 @[el2_lib.scala 263:30]
|
|
node _T_2654 = bits(_T_2645, 0, 0) @[el2_lib.scala 266:36]
|
|
_T_2651[0] <= _T_2654 @[el2_lib.scala 266:30]
|
|
node _T_2655 = bits(_T_2645, 1, 1) @[el2_lib.scala 261:36]
|
|
_T_2646[0] <= _T_2655 @[el2_lib.scala 261:30]
|
|
node _T_2656 = bits(_T_2645, 1, 1) @[el2_lib.scala 263:36]
|
|
_T_2648[1] <= _T_2656 @[el2_lib.scala 263:30]
|
|
node _T_2657 = bits(_T_2645, 1, 1) @[el2_lib.scala 266:36]
|
|
_T_2651[1] <= _T_2657 @[el2_lib.scala 266:30]
|
|
node _T_2658 = bits(_T_2645, 2, 2) @[el2_lib.scala 263:36]
|
|
_T_2648[2] <= _T_2658 @[el2_lib.scala 263:30]
|
|
node _T_2659 = bits(_T_2645, 2, 2) @[el2_lib.scala 266:36]
|
|
_T_2651[2] <= _T_2659 @[el2_lib.scala 266:30]
|
|
node _T_2660 = bits(_T_2645, 3, 3) @[el2_lib.scala 261:36]
|
|
_T_2646[1] <= _T_2660 @[el2_lib.scala 261:30]
|
|
node _T_2661 = bits(_T_2645, 3, 3) @[el2_lib.scala 262:36]
|
|
_T_2647[1] <= _T_2661 @[el2_lib.scala 262:30]
|
|
node _T_2662 = bits(_T_2645, 3, 3) @[el2_lib.scala 266:36]
|
|
_T_2651[3] <= _T_2662 @[el2_lib.scala 266:30]
|
|
node _T_2663 = bits(_T_2645, 4, 4) @[el2_lib.scala 262:36]
|
|
_T_2647[2] <= _T_2663 @[el2_lib.scala 262:30]
|
|
node _T_2664 = bits(_T_2645, 4, 4) @[el2_lib.scala 266:36]
|
|
_T_2651[4] <= _T_2664 @[el2_lib.scala 266:30]
|
|
node _T_2665 = bits(_T_2645, 5, 5) @[el2_lib.scala 261:36]
|
|
_T_2646[2] <= _T_2665 @[el2_lib.scala 261:30]
|
|
node _T_2666 = bits(_T_2645, 5, 5) @[el2_lib.scala 266:36]
|
|
_T_2651[5] <= _T_2666 @[el2_lib.scala 266:30]
|
|
node _T_2667 = bits(_T_2645, 6, 6) @[el2_lib.scala 261:36]
|
|
_T_2646[3] <= _T_2667 @[el2_lib.scala 261:30]
|
|
node _T_2668 = bits(_T_2645, 6, 6) @[el2_lib.scala 262:36]
|
|
_T_2647[3] <= _T_2668 @[el2_lib.scala 262:30]
|
|
node _T_2669 = bits(_T_2645, 6, 6) @[el2_lib.scala 263:36]
|
|
_T_2648[3] <= _T_2669 @[el2_lib.scala 263:30]
|
|
node _T_2670 = bits(_T_2645, 6, 6) @[el2_lib.scala 264:36]
|
|
_T_2649[0] <= _T_2670 @[el2_lib.scala 264:30]
|
|
node _T_2671 = bits(_T_2645, 6, 6) @[el2_lib.scala 265:36]
|
|
_T_2650[0] <= _T_2671 @[el2_lib.scala 265:30]
|
|
node _T_2672 = bits(_T_2645, 7, 7) @[el2_lib.scala 262:36]
|
|
_T_2647[4] <= _T_2672 @[el2_lib.scala 262:30]
|
|
node _T_2673 = bits(_T_2645, 7, 7) @[el2_lib.scala 263:36]
|
|
_T_2648[4] <= _T_2673 @[el2_lib.scala 263:30]
|
|
node _T_2674 = bits(_T_2645, 7, 7) @[el2_lib.scala 264:36]
|
|
_T_2649[1] <= _T_2674 @[el2_lib.scala 264:30]
|
|
node _T_2675 = bits(_T_2645, 7, 7) @[el2_lib.scala 265:36]
|
|
_T_2650[1] <= _T_2675 @[el2_lib.scala 265:30]
|
|
node _T_2676 = bits(_T_2645, 8, 8) @[el2_lib.scala 261:36]
|
|
_T_2646[4] <= _T_2676 @[el2_lib.scala 261:30]
|
|
node _T_2677 = bits(_T_2645, 8, 8) @[el2_lib.scala 263:36]
|
|
_T_2648[5] <= _T_2677 @[el2_lib.scala 263:30]
|
|
node _T_2678 = bits(_T_2645, 8, 8) @[el2_lib.scala 264:36]
|
|
_T_2649[2] <= _T_2678 @[el2_lib.scala 264:30]
|
|
node _T_2679 = bits(_T_2645, 8, 8) @[el2_lib.scala 265:36]
|
|
_T_2650[2] <= _T_2679 @[el2_lib.scala 265:30]
|
|
node _T_2680 = bits(_T_2645, 9, 9) @[el2_lib.scala 263:36]
|
|
_T_2648[6] <= _T_2680 @[el2_lib.scala 263:30]
|
|
node _T_2681 = bits(_T_2645, 9, 9) @[el2_lib.scala 264:36]
|
|
_T_2649[3] <= _T_2681 @[el2_lib.scala 264:30]
|
|
node _T_2682 = bits(_T_2645, 9, 9) @[el2_lib.scala 265:36]
|
|
_T_2650[3] <= _T_2682 @[el2_lib.scala 265:30]
|
|
node _T_2683 = bits(_T_2645, 10, 10) @[el2_lib.scala 261:36]
|
|
_T_2646[5] <= _T_2683 @[el2_lib.scala 261:30]
|
|
node _T_2684 = bits(_T_2645, 10, 10) @[el2_lib.scala 262:36]
|
|
_T_2647[5] <= _T_2684 @[el2_lib.scala 262:30]
|
|
node _T_2685 = bits(_T_2645, 10, 10) @[el2_lib.scala 264:36]
|
|
_T_2649[4] <= _T_2685 @[el2_lib.scala 264:30]
|
|
node _T_2686 = bits(_T_2645, 10, 10) @[el2_lib.scala 265:36]
|
|
_T_2650[4] <= _T_2686 @[el2_lib.scala 265:30]
|
|
node _T_2687 = bits(_T_2645, 11, 11) @[el2_lib.scala 262:36]
|
|
_T_2647[6] <= _T_2687 @[el2_lib.scala 262:30]
|
|
node _T_2688 = bits(_T_2645, 11, 11) @[el2_lib.scala 264:36]
|
|
_T_2649[5] <= _T_2688 @[el2_lib.scala 264:30]
|
|
node _T_2689 = bits(_T_2645, 11, 11) @[el2_lib.scala 265:36]
|
|
_T_2650[5] <= _T_2689 @[el2_lib.scala 265:30]
|
|
node _T_2690 = bits(_T_2645, 12, 12) @[el2_lib.scala 261:36]
|
|
_T_2646[6] <= _T_2690 @[el2_lib.scala 261:30]
|
|
node _T_2691 = bits(_T_2645, 12, 12) @[el2_lib.scala 264:36]
|
|
_T_2649[6] <= _T_2691 @[el2_lib.scala 264:30]
|
|
node _T_2692 = bits(_T_2645, 12, 12) @[el2_lib.scala 265:36]
|
|
_T_2650[6] <= _T_2692 @[el2_lib.scala 265:30]
|
|
node _T_2693 = bits(_T_2645, 13, 13) @[el2_lib.scala 264:36]
|
|
_T_2649[7] <= _T_2693 @[el2_lib.scala 264:30]
|
|
node _T_2694 = bits(_T_2645, 13, 13) @[el2_lib.scala 265:36]
|
|
_T_2650[7] <= _T_2694 @[el2_lib.scala 265:30]
|
|
node _T_2695 = bits(_T_2645, 14, 14) @[el2_lib.scala 261:36]
|
|
_T_2646[7] <= _T_2695 @[el2_lib.scala 261:30]
|
|
node _T_2696 = bits(_T_2645, 14, 14) @[el2_lib.scala 262:36]
|
|
_T_2647[7] <= _T_2696 @[el2_lib.scala 262:30]
|
|
node _T_2697 = bits(_T_2645, 14, 14) @[el2_lib.scala 263:36]
|
|
_T_2648[7] <= _T_2697 @[el2_lib.scala 263:30]
|
|
node _T_2698 = bits(_T_2645, 14, 14) @[el2_lib.scala 265:36]
|
|
_T_2650[8] <= _T_2698 @[el2_lib.scala 265:30]
|
|
node _T_2699 = bits(_T_2645, 15, 15) @[el2_lib.scala 262:36]
|
|
_T_2647[8] <= _T_2699 @[el2_lib.scala 262:30]
|
|
node _T_2700 = bits(_T_2645, 15, 15) @[el2_lib.scala 263:36]
|
|
_T_2648[8] <= _T_2700 @[el2_lib.scala 263:30]
|
|
node _T_2701 = bits(_T_2645, 15, 15) @[el2_lib.scala 265:36]
|
|
_T_2650[9] <= _T_2701 @[el2_lib.scala 265:30]
|
|
node _T_2702 = bits(_T_2645, 16, 16) @[el2_lib.scala 261:36]
|
|
_T_2646[8] <= _T_2702 @[el2_lib.scala 261:30]
|
|
node _T_2703 = bits(_T_2645, 16, 16) @[el2_lib.scala 263:36]
|
|
_T_2648[9] <= _T_2703 @[el2_lib.scala 263:30]
|
|
node _T_2704 = bits(_T_2645, 16, 16) @[el2_lib.scala 265:36]
|
|
_T_2650[10] <= _T_2704 @[el2_lib.scala 265:30]
|
|
node _T_2705 = bits(_T_2645, 17, 17) @[el2_lib.scala 263:36]
|
|
_T_2648[10] <= _T_2705 @[el2_lib.scala 263:30]
|
|
node _T_2706 = bits(_T_2645, 17, 17) @[el2_lib.scala 265:36]
|
|
_T_2650[11] <= _T_2706 @[el2_lib.scala 265:30]
|
|
node _T_2707 = bits(_T_2645, 18, 18) @[el2_lib.scala 261:36]
|
|
_T_2646[9] <= _T_2707 @[el2_lib.scala 261:30]
|
|
node _T_2708 = bits(_T_2645, 18, 18) @[el2_lib.scala 262:36]
|
|
_T_2647[9] <= _T_2708 @[el2_lib.scala 262:30]
|
|
node _T_2709 = bits(_T_2645, 18, 18) @[el2_lib.scala 265:36]
|
|
_T_2650[12] <= _T_2709 @[el2_lib.scala 265:30]
|
|
node _T_2710 = bits(_T_2645, 19, 19) @[el2_lib.scala 262:36]
|
|
_T_2647[10] <= _T_2710 @[el2_lib.scala 262:30]
|
|
node _T_2711 = bits(_T_2645, 19, 19) @[el2_lib.scala 265:36]
|
|
_T_2650[13] <= _T_2711 @[el2_lib.scala 265:30]
|
|
node _T_2712 = bits(_T_2645, 20, 20) @[el2_lib.scala 261:36]
|
|
_T_2646[10] <= _T_2712 @[el2_lib.scala 261:30]
|
|
node _T_2713 = bits(_T_2645, 20, 20) @[el2_lib.scala 265:36]
|
|
_T_2650[14] <= _T_2713 @[el2_lib.scala 265:30]
|
|
node _T_2714 = bits(_T_2645, 21, 21) @[el2_lib.scala 261:36]
|
|
_T_2646[11] <= _T_2714 @[el2_lib.scala 261:30]
|
|
node _T_2715 = bits(_T_2645, 21, 21) @[el2_lib.scala 262:36]
|
|
_T_2647[11] <= _T_2715 @[el2_lib.scala 262:30]
|
|
node _T_2716 = bits(_T_2645, 21, 21) @[el2_lib.scala 263:36]
|
|
_T_2648[11] <= _T_2716 @[el2_lib.scala 263:30]
|
|
node _T_2717 = bits(_T_2645, 21, 21) @[el2_lib.scala 264:36]
|
|
_T_2649[8] <= _T_2717 @[el2_lib.scala 264:30]
|
|
node _T_2718 = bits(_T_2645, 22, 22) @[el2_lib.scala 262:36]
|
|
_T_2647[12] <= _T_2718 @[el2_lib.scala 262:30]
|
|
node _T_2719 = bits(_T_2645, 22, 22) @[el2_lib.scala 263:36]
|
|
_T_2648[12] <= _T_2719 @[el2_lib.scala 263:30]
|
|
node _T_2720 = bits(_T_2645, 22, 22) @[el2_lib.scala 264:36]
|
|
_T_2649[9] <= _T_2720 @[el2_lib.scala 264:30]
|
|
node _T_2721 = bits(_T_2645, 23, 23) @[el2_lib.scala 261:36]
|
|
_T_2646[12] <= _T_2721 @[el2_lib.scala 261:30]
|
|
node _T_2722 = bits(_T_2645, 23, 23) @[el2_lib.scala 263:36]
|
|
_T_2648[13] <= _T_2722 @[el2_lib.scala 263:30]
|
|
node _T_2723 = bits(_T_2645, 23, 23) @[el2_lib.scala 264:36]
|
|
_T_2649[10] <= _T_2723 @[el2_lib.scala 264:30]
|
|
node _T_2724 = bits(_T_2645, 24, 24) @[el2_lib.scala 263:36]
|
|
_T_2648[14] <= _T_2724 @[el2_lib.scala 263:30]
|
|
node _T_2725 = bits(_T_2645, 24, 24) @[el2_lib.scala 264:36]
|
|
_T_2649[11] <= _T_2725 @[el2_lib.scala 264:30]
|
|
node _T_2726 = bits(_T_2645, 25, 25) @[el2_lib.scala 261:36]
|
|
_T_2646[13] <= _T_2726 @[el2_lib.scala 261:30]
|
|
node _T_2727 = bits(_T_2645, 25, 25) @[el2_lib.scala 262:36]
|
|
_T_2647[13] <= _T_2727 @[el2_lib.scala 262:30]
|
|
node _T_2728 = bits(_T_2645, 25, 25) @[el2_lib.scala 264:36]
|
|
_T_2649[12] <= _T_2728 @[el2_lib.scala 264:30]
|
|
node _T_2729 = bits(_T_2645, 26, 26) @[el2_lib.scala 262:36]
|
|
_T_2647[14] <= _T_2729 @[el2_lib.scala 262:30]
|
|
node _T_2730 = bits(_T_2645, 26, 26) @[el2_lib.scala 264:36]
|
|
_T_2649[13] <= _T_2730 @[el2_lib.scala 264:30]
|
|
node _T_2731 = bits(_T_2645, 27, 27) @[el2_lib.scala 261:36]
|
|
_T_2646[14] <= _T_2731 @[el2_lib.scala 261:30]
|
|
node _T_2732 = bits(_T_2645, 27, 27) @[el2_lib.scala 264:36]
|
|
_T_2649[14] <= _T_2732 @[el2_lib.scala 264:30]
|
|
node _T_2733 = bits(_T_2645, 28, 28) @[el2_lib.scala 261:36]
|
|
_T_2646[15] <= _T_2733 @[el2_lib.scala 261:30]
|
|
node _T_2734 = bits(_T_2645, 28, 28) @[el2_lib.scala 262:36]
|
|
_T_2647[15] <= _T_2734 @[el2_lib.scala 262:30]
|
|
node _T_2735 = bits(_T_2645, 28, 28) @[el2_lib.scala 263:36]
|
|
_T_2648[15] <= _T_2735 @[el2_lib.scala 263:30]
|
|
node _T_2736 = bits(_T_2645, 29, 29) @[el2_lib.scala 262:36]
|
|
_T_2647[16] <= _T_2736 @[el2_lib.scala 262:30]
|
|
node _T_2737 = bits(_T_2645, 29, 29) @[el2_lib.scala 263:36]
|
|
_T_2648[16] <= _T_2737 @[el2_lib.scala 263:30]
|
|
node _T_2738 = bits(_T_2645, 30, 30) @[el2_lib.scala 261:36]
|
|
_T_2646[16] <= _T_2738 @[el2_lib.scala 261:30]
|
|
node _T_2739 = bits(_T_2645, 30, 30) @[el2_lib.scala 263:36]
|
|
_T_2648[17] <= _T_2739 @[el2_lib.scala 263:30]
|
|
node _T_2740 = bits(_T_2645, 31, 31) @[el2_lib.scala 261:36]
|
|
_T_2646[17] <= _T_2740 @[el2_lib.scala 261:30]
|
|
node _T_2741 = bits(_T_2645, 31, 31) @[el2_lib.scala 262:36]
|
|
_T_2647[17] <= _T_2741 @[el2_lib.scala 262:30]
|
|
node _T_2742 = cat(_T_2646[1], _T_2646[0]) @[el2_lib.scala 268:22]
|
|
node _T_2743 = cat(_T_2646[3], _T_2646[2]) @[el2_lib.scala 268:22]
|
|
node _T_2744 = cat(_T_2743, _T_2742) @[el2_lib.scala 268:22]
|
|
node _T_2745 = cat(_T_2646[5], _T_2646[4]) @[el2_lib.scala 268:22]
|
|
node _T_2746 = cat(_T_2646[8], _T_2646[7]) @[el2_lib.scala 268:22]
|
|
node _T_2747 = cat(_T_2746, _T_2646[6]) @[el2_lib.scala 268:22]
|
|
node _T_2748 = cat(_T_2747, _T_2745) @[el2_lib.scala 268:22]
|
|
node _T_2749 = cat(_T_2748, _T_2744) @[el2_lib.scala 268:22]
|
|
node _T_2750 = cat(_T_2646[10], _T_2646[9]) @[el2_lib.scala 268:22]
|
|
node _T_2751 = cat(_T_2646[12], _T_2646[11]) @[el2_lib.scala 268:22]
|
|
node _T_2752 = cat(_T_2751, _T_2750) @[el2_lib.scala 268:22]
|
|
node _T_2753 = cat(_T_2646[14], _T_2646[13]) @[el2_lib.scala 268:22]
|
|
node _T_2754 = cat(_T_2646[17], _T_2646[16]) @[el2_lib.scala 268:22]
|
|
node _T_2755 = cat(_T_2754, _T_2646[15]) @[el2_lib.scala 268:22]
|
|
node _T_2756 = cat(_T_2755, _T_2753) @[el2_lib.scala 268:22]
|
|
node _T_2757 = cat(_T_2756, _T_2752) @[el2_lib.scala 268:22]
|
|
node _T_2758 = cat(_T_2757, _T_2749) @[el2_lib.scala 268:22]
|
|
node _T_2759 = xorr(_T_2758) @[el2_lib.scala 268:29]
|
|
node _T_2760 = cat(_T_2647[1], _T_2647[0]) @[el2_lib.scala 268:39]
|
|
node _T_2761 = cat(_T_2647[3], _T_2647[2]) @[el2_lib.scala 268:39]
|
|
node _T_2762 = cat(_T_2761, _T_2760) @[el2_lib.scala 268:39]
|
|
node _T_2763 = cat(_T_2647[5], _T_2647[4]) @[el2_lib.scala 268:39]
|
|
node _T_2764 = cat(_T_2647[8], _T_2647[7]) @[el2_lib.scala 268:39]
|
|
node _T_2765 = cat(_T_2764, _T_2647[6]) @[el2_lib.scala 268:39]
|
|
node _T_2766 = cat(_T_2765, _T_2763) @[el2_lib.scala 268:39]
|
|
node _T_2767 = cat(_T_2766, _T_2762) @[el2_lib.scala 268:39]
|
|
node _T_2768 = cat(_T_2647[10], _T_2647[9]) @[el2_lib.scala 268:39]
|
|
node _T_2769 = cat(_T_2647[12], _T_2647[11]) @[el2_lib.scala 268:39]
|
|
node _T_2770 = cat(_T_2769, _T_2768) @[el2_lib.scala 268:39]
|
|
node _T_2771 = cat(_T_2647[14], _T_2647[13]) @[el2_lib.scala 268:39]
|
|
node _T_2772 = cat(_T_2647[17], _T_2647[16]) @[el2_lib.scala 268:39]
|
|
node _T_2773 = cat(_T_2772, _T_2647[15]) @[el2_lib.scala 268:39]
|
|
node _T_2774 = cat(_T_2773, _T_2771) @[el2_lib.scala 268:39]
|
|
node _T_2775 = cat(_T_2774, _T_2770) @[el2_lib.scala 268:39]
|
|
node _T_2776 = cat(_T_2775, _T_2767) @[el2_lib.scala 268:39]
|
|
node _T_2777 = xorr(_T_2776) @[el2_lib.scala 268:46]
|
|
node _T_2778 = cat(_T_2648[1], _T_2648[0]) @[el2_lib.scala 268:56]
|
|
node _T_2779 = cat(_T_2648[3], _T_2648[2]) @[el2_lib.scala 268:56]
|
|
node _T_2780 = cat(_T_2779, _T_2778) @[el2_lib.scala 268:56]
|
|
node _T_2781 = cat(_T_2648[5], _T_2648[4]) @[el2_lib.scala 268:56]
|
|
node _T_2782 = cat(_T_2648[8], _T_2648[7]) @[el2_lib.scala 268:56]
|
|
node _T_2783 = cat(_T_2782, _T_2648[6]) @[el2_lib.scala 268:56]
|
|
node _T_2784 = cat(_T_2783, _T_2781) @[el2_lib.scala 268:56]
|
|
node _T_2785 = cat(_T_2784, _T_2780) @[el2_lib.scala 268:56]
|
|
node _T_2786 = cat(_T_2648[10], _T_2648[9]) @[el2_lib.scala 268:56]
|
|
node _T_2787 = cat(_T_2648[12], _T_2648[11]) @[el2_lib.scala 268:56]
|
|
node _T_2788 = cat(_T_2787, _T_2786) @[el2_lib.scala 268:56]
|
|
node _T_2789 = cat(_T_2648[14], _T_2648[13]) @[el2_lib.scala 268:56]
|
|
node _T_2790 = cat(_T_2648[17], _T_2648[16]) @[el2_lib.scala 268:56]
|
|
node _T_2791 = cat(_T_2790, _T_2648[15]) @[el2_lib.scala 268:56]
|
|
node _T_2792 = cat(_T_2791, _T_2789) @[el2_lib.scala 268:56]
|
|
node _T_2793 = cat(_T_2792, _T_2788) @[el2_lib.scala 268:56]
|
|
node _T_2794 = cat(_T_2793, _T_2785) @[el2_lib.scala 268:56]
|
|
node _T_2795 = xorr(_T_2794) @[el2_lib.scala 268:63]
|
|
node _T_2796 = cat(_T_2649[2], _T_2649[1]) @[el2_lib.scala 268:73]
|
|
node _T_2797 = cat(_T_2796, _T_2649[0]) @[el2_lib.scala 268:73]
|
|
node _T_2798 = cat(_T_2649[4], _T_2649[3]) @[el2_lib.scala 268:73]
|
|
node _T_2799 = cat(_T_2649[6], _T_2649[5]) @[el2_lib.scala 268:73]
|
|
node _T_2800 = cat(_T_2799, _T_2798) @[el2_lib.scala 268:73]
|
|
node _T_2801 = cat(_T_2800, _T_2797) @[el2_lib.scala 268:73]
|
|
node _T_2802 = cat(_T_2649[8], _T_2649[7]) @[el2_lib.scala 268:73]
|
|
node _T_2803 = cat(_T_2649[10], _T_2649[9]) @[el2_lib.scala 268:73]
|
|
node _T_2804 = cat(_T_2803, _T_2802) @[el2_lib.scala 268:73]
|
|
node _T_2805 = cat(_T_2649[12], _T_2649[11]) @[el2_lib.scala 268:73]
|
|
node _T_2806 = cat(_T_2649[14], _T_2649[13]) @[el2_lib.scala 268:73]
|
|
node _T_2807 = cat(_T_2806, _T_2805) @[el2_lib.scala 268:73]
|
|
node _T_2808 = cat(_T_2807, _T_2804) @[el2_lib.scala 268:73]
|
|
node _T_2809 = cat(_T_2808, _T_2801) @[el2_lib.scala 268:73]
|
|
node _T_2810 = xorr(_T_2809) @[el2_lib.scala 268:80]
|
|
node _T_2811 = cat(_T_2650[2], _T_2650[1]) @[el2_lib.scala 268:90]
|
|
node _T_2812 = cat(_T_2811, _T_2650[0]) @[el2_lib.scala 268:90]
|
|
node _T_2813 = cat(_T_2650[4], _T_2650[3]) @[el2_lib.scala 268:90]
|
|
node _T_2814 = cat(_T_2650[6], _T_2650[5]) @[el2_lib.scala 268:90]
|
|
node _T_2815 = cat(_T_2814, _T_2813) @[el2_lib.scala 268:90]
|
|
node _T_2816 = cat(_T_2815, _T_2812) @[el2_lib.scala 268:90]
|
|
node _T_2817 = cat(_T_2650[8], _T_2650[7]) @[el2_lib.scala 268:90]
|
|
node _T_2818 = cat(_T_2650[10], _T_2650[9]) @[el2_lib.scala 268:90]
|
|
node _T_2819 = cat(_T_2818, _T_2817) @[el2_lib.scala 268:90]
|
|
node _T_2820 = cat(_T_2650[12], _T_2650[11]) @[el2_lib.scala 268:90]
|
|
node _T_2821 = cat(_T_2650[14], _T_2650[13]) @[el2_lib.scala 268:90]
|
|
node _T_2822 = cat(_T_2821, _T_2820) @[el2_lib.scala 268:90]
|
|
node _T_2823 = cat(_T_2822, _T_2819) @[el2_lib.scala 268:90]
|
|
node _T_2824 = cat(_T_2823, _T_2816) @[el2_lib.scala 268:90]
|
|
node _T_2825 = xorr(_T_2824) @[el2_lib.scala 268:97]
|
|
node _T_2826 = cat(_T_2651[2], _T_2651[1]) @[el2_lib.scala 268:107]
|
|
node _T_2827 = cat(_T_2826, _T_2651[0]) @[el2_lib.scala 268:107]
|
|
node _T_2828 = cat(_T_2651[5], _T_2651[4]) @[el2_lib.scala 268:107]
|
|
node _T_2829 = cat(_T_2828, _T_2651[3]) @[el2_lib.scala 268:107]
|
|
node _T_2830 = cat(_T_2829, _T_2827) @[el2_lib.scala 268:107]
|
|
node _T_2831 = xorr(_T_2830) @[el2_lib.scala 268:114]
|
|
node _T_2832 = cat(_T_2810, _T_2825) @[Cat.scala 29:58]
|
|
node _T_2833 = cat(_T_2832, _T_2831) @[Cat.scala 29:58]
|
|
node _T_2834 = cat(_T_2759, _T_2777) @[Cat.scala 29:58]
|
|
node _T_2835 = cat(_T_2834, _T_2795) @[Cat.scala 29:58]
|
|
node _T_2836 = cat(_T_2835, _T_2833) @[Cat.scala 29:58]
|
|
node _T_2837 = xorr(_T_2645) @[el2_lib.scala 269:13]
|
|
node _T_2838 = xorr(_T_2836) @[el2_lib.scala 269:23]
|
|
node _T_2839 = xor(_T_2837, _T_2838) @[el2_lib.scala 269:18]
|
|
node _T_2840 = cat(_T_2839, _T_2836) @[Cat.scala 29:58]
|
|
node _T_2841 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 629:93]
|
|
wire _T_2842 : UInt<1>[18] @[el2_lib.scala 250:18]
|
|
wire _T_2843 : UInt<1>[18] @[el2_lib.scala 251:18]
|
|
wire _T_2844 : UInt<1>[18] @[el2_lib.scala 252:18]
|
|
wire _T_2845 : UInt<1>[15] @[el2_lib.scala 253:18]
|
|
wire _T_2846 : UInt<1>[15] @[el2_lib.scala 254:18]
|
|
wire _T_2847 : UInt<1>[6] @[el2_lib.scala 255:18]
|
|
node _T_2848 = bits(_T_2841, 0, 0) @[el2_lib.scala 262:36]
|
|
_T_2843[0] <= _T_2848 @[el2_lib.scala 262:30]
|
|
node _T_2849 = bits(_T_2841, 0, 0) @[el2_lib.scala 263:36]
|
|
_T_2844[0] <= _T_2849 @[el2_lib.scala 263:30]
|
|
node _T_2850 = bits(_T_2841, 0, 0) @[el2_lib.scala 266:36]
|
|
_T_2847[0] <= _T_2850 @[el2_lib.scala 266:30]
|
|
node _T_2851 = bits(_T_2841, 1, 1) @[el2_lib.scala 261:36]
|
|
_T_2842[0] <= _T_2851 @[el2_lib.scala 261:30]
|
|
node _T_2852 = bits(_T_2841, 1, 1) @[el2_lib.scala 263:36]
|
|
_T_2844[1] <= _T_2852 @[el2_lib.scala 263:30]
|
|
node _T_2853 = bits(_T_2841, 1, 1) @[el2_lib.scala 266:36]
|
|
_T_2847[1] <= _T_2853 @[el2_lib.scala 266:30]
|
|
node _T_2854 = bits(_T_2841, 2, 2) @[el2_lib.scala 263:36]
|
|
_T_2844[2] <= _T_2854 @[el2_lib.scala 263:30]
|
|
node _T_2855 = bits(_T_2841, 2, 2) @[el2_lib.scala 266:36]
|
|
_T_2847[2] <= _T_2855 @[el2_lib.scala 266:30]
|
|
node _T_2856 = bits(_T_2841, 3, 3) @[el2_lib.scala 261:36]
|
|
_T_2842[1] <= _T_2856 @[el2_lib.scala 261:30]
|
|
node _T_2857 = bits(_T_2841, 3, 3) @[el2_lib.scala 262:36]
|
|
_T_2843[1] <= _T_2857 @[el2_lib.scala 262:30]
|
|
node _T_2858 = bits(_T_2841, 3, 3) @[el2_lib.scala 266:36]
|
|
_T_2847[3] <= _T_2858 @[el2_lib.scala 266:30]
|
|
node _T_2859 = bits(_T_2841, 4, 4) @[el2_lib.scala 262:36]
|
|
_T_2843[2] <= _T_2859 @[el2_lib.scala 262:30]
|
|
node _T_2860 = bits(_T_2841, 4, 4) @[el2_lib.scala 266:36]
|
|
_T_2847[4] <= _T_2860 @[el2_lib.scala 266:30]
|
|
node _T_2861 = bits(_T_2841, 5, 5) @[el2_lib.scala 261:36]
|
|
_T_2842[2] <= _T_2861 @[el2_lib.scala 261:30]
|
|
node _T_2862 = bits(_T_2841, 5, 5) @[el2_lib.scala 266:36]
|
|
_T_2847[5] <= _T_2862 @[el2_lib.scala 266:30]
|
|
node _T_2863 = bits(_T_2841, 6, 6) @[el2_lib.scala 261:36]
|
|
_T_2842[3] <= _T_2863 @[el2_lib.scala 261:30]
|
|
node _T_2864 = bits(_T_2841, 6, 6) @[el2_lib.scala 262:36]
|
|
_T_2843[3] <= _T_2864 @[el2_lib.scala 262:30]
|
|
node _T_2865 = bits(_T_2841, 6, 6) @[el2_lib.scala 263:36]
|
|
_T_2844[3] <= _T_2865 @[el2_lib.scala 263:30]
|
|
node _T_2866 = bits(_T_2841, 6, 6) @[el2_lib.scala 264:36]
|
|
_T_2845[0] <= _T_2866 @[el2_lib.scala 264:30]
|
|
node _T_2867 = bits(_T_2841, 6, 6) @[el2_lib.scala 265:36]
|
|
_T_2846[0] <= _T_2867 @[el2_lib.scala 265:30]
|
|
node _T_2868 = bits(_T_2841, 7, 7) @[el2_lib.scala 262:36]
|
|
_T_2843[4] <= _T_2868 @[el2_lib.scala 262:30]
|
|
node _T_2869 = bits(_T_2841, 7, 7) @[el2_lib.scala 263:36]
|
|
_T_2844[4] <= _T_2869 @[el2_lib.scala 263:30]
|
|
node _T_2870 = bits(_T_2841, 7, 7) @[el2_lib.scala 264:36]
|
|
_T_2845[1] <= _T_2870 @[el2_lib.scala 264:30]
|
|
node _T_2871 = bits(_T_2841, 7, 7) @[el2_lib.scala 265:36]
|
|
_T_2846[1] <= _T_2871 @[el2_lib.scala 265:30]
|
|
node _T_2872 = bits(_T_2841, 8, 8) @[el2_lib.scala 261:36]
|
|
_T_2842[4] <= _T_2872 @[el2_lib.scala 261:30]
|
|
node _T_2873 = bits(_T_2841, 8, 8) @[el2_lib.scala 263:36]
|
|
_T_2844[5] <= _T_2873 @[el2_lib.scala 263:30]
|
|
node _T_2874 = bits(_T_2841, 8, 8) @[el2_lib.scala 264:36]
|
|
_T_2845[2] <= _T_2874 @[el2_lib.scala 264:30]
|
|
node _T_2875 = bits(_T_2841, 8, 8) @[el2_lib.scala 265:36]
|
|
_T_2846[2] <= _T_2875 @[el2_lib.scala 265:30]
|
|
node _T_2876 = bits(_T_2841, 9, 9) @[el2_lib.scala 263:36]
|
|
_T_2844[6] <= _T_2876 @[el2_lib.scala 263:30]
|
|
node _T_2877 = bits(_T_2841, 9, 9) @[el2_lib.scala 264:36]
|
|
_T_2845[3] <= _T_2877 @[el2_lib.scala 264:30]
|
|
node _T_2878 = bits(_T_2841, 9, 9) @[el2_lib.scala 265:36]
|
|
_T_2846[3] <= _T_2878 @[el2_lib.scala 265:30]
|
|
node _T_2879 = bits(_T_2841, 10, 10) @[el2_lib.scala 261:36]
|
|
_T_2842[5] <= _T_2879 @[el2_lib.scala 261:30]
|
|
node _T_2880 = bits(_T_2841, 10, 10) @[el2_lib.scala 262:36]
|
|
_T_2843[5] <= _T_2880 @[el2_lib.scala 262:30]
|
|
node _T_2881 = bits(_T_2841, 10, 10) @[el2_lib.scala 264:36]
|
|
_T_2845[4] <= _T_2881 @[el2_lib.scala 264:30]
|
|
node _T_2882 = bits(_T_2841, 10, 10) @[el2_lib.scala 265:36]
|
|
_T_2846[4] <= _T_2882 @[el2_lib.scala 265:30]
|
|
node _T_2883 = bits(_T_2841, 11, 11) @[el2_lib.scala 262:36]
|
|
_T_2843[6] <= _T_2883 @[el2_lib.scala 262:30]
|
|
node _T_2884 = bits(_T_2841, 11, 11) @[el2_lib.scala 264:36]
|
|
_T_2845[5] <= _T_2884 @[el2_lib.scala 264:30]
|
|
node _T_2885 = bits(_T_2841, 11, 11) @[el2_lib.scala 265:36]
|
|
_T_2846[5] <= _T_2885 @[el2_lib.scala 265:30]
|
|
node _T_2886 = bits(_T_2841, 12, 12) @[el2_lib.scala 261:36]
|
|
_T_2842[6] <= _T_2886 @[el2_lib.scala 261:30]
|
|
node _T_2887 = bits(_T_2841, 12, 12) @[el2_lib.scala 264:36]
|
|
_T_2845[6] <= _T_2887 @[el2_lib.scala 264:30]
|
|
node _T_2888 = bits(_T_2841, 12, 12) @[el2_lib.scala 265:36]
|
|
_T_2846[6] <= _T_2888 @[el2_lib.scala 265:30]
|
|
node _T_2889 = bits(_T_2841, 13, 13) @[el2_lib.scala 264:36]
|
|
_T_2845[7] <= _T_2889 @[el2_lib.scala 264:30]
|
|
node _T_2890 = bits(_T_2841, 13, 13) @[el2_lib.scala 265:36]
|
|
_T_2846[7] <= _T_2890 @[el2_lib.scala 265:30]
|
|
node _T_2891 = bits(_T_2841, 14, 14) @[el2_lib.scala 261:36]
|
|
_T_2842[7] <= _T_2891 @[el2_lib.scala 261:30]
|
|
node _T_2892 = bits(_T_2841, 14, 14) @[el2_lib.scala 262:36]
|
|
_T_2843[7] <= _T_2892 @[el2_lib.scala 262:30]
|
|
node _T_2893 = bits(_T_2841, 14, 14) @[el2_lib.scala 263:36]
|
|
_T_2844[7] <= _T_2893 @[el2_lib.scala 263:30]
|
|
node _T_2894 = bits(_T_2841, 14, 14) @[el2_lib.scala 265:36]
|
|
_T_2846[8] <= _T_2894 @[el2_lib.scala 265:30]
|
|
node _T_2895 = bits(_T_2841, 15, 15) @[el2_lib.scala 262:36]
|
|
_T_2843[8] <= _T_2895 @[el2_lib.scala 262:30]
|
|
node _T_2896 = bits(_T_2841, 15, 15) @[el2_lib.scala 263:36]
|
|
_T_2844[8] <= _T_2896 @[el2_lib.scala 263:30]
|
|
node _T_2897 = bits(_T_2841, 15, 15) @[el2_lib.scala 265:36]
|
|
_T_2846[9] <= _T_2897 @[el2_lib.scala 265:30]
|
|
node _T_2898 = bits(_T_2841, 16, 16) @[el2_lib.scala 261:36]
|
|
_T_2842[8] <= _T_2898 @[el2_lib.scala 261:30]
|
|
node _T_2899 = bits(_T_2841, 16, 16) @[el2_lib.scala 263:36]
|
|
_T_2844[9] <= _T_2899 @[el2_lib.scala 263:30]
|
|
node _T_2900 = bits(_T_2841, 16, 16) @[el2_lib.scala 265:36]
|
|
_T_2846[10] <= _T_2900 @[el2_lib.scala 265:30]
|
|
node _T_2901 = bits(_T_2841, 17, 17) @[el2_lib.scala 263:36]
|
|
_T_2844[10] <= _T_2901 @[el2_lib.scala 263:30]
|
|
node _T_2902 = bits(_T_2841, 17, 17) @[el2_lib.scala 265:36]
|
|
_T_2846[11] <= _T_2902 @[el2_lib.scala 265:30]
|
|
node _T_2903 = bits(_T_2841, 18, 18) @[el2_lib.scala 261:36]
|
|
_T_2842[9] <= _T_2903 @[el2_lib.scala 261:30]
|
|
node _T_2904 = bits(_T_2841, 18, 18) @[el2_lib.scala 262:36]
|
|
_T_2843[9] <= _T_2904 @[el2_lib.scala 262:30]
|
|
node _T_2905 = bits(_T_2841, 18, 18) @[el2_lib.scala 265:36]
|
|
_T_2846[12] <= _T_2905 @[el2_lib.scala 265:30]
|
|
node _T_2906 = bits(_T_2841, 19, 19) @[el2_lib.scala 262:36]
|
|
_T_2843[10] <= _T_2906 @[el2_lib.scala 262:30]
|
|
node _T_2907 = bits(_T_2841, 19, 19) @[el2_lib.scala 265:36]
|
|
_T_2846[13] <= _T_2907 @[el2_lib.scala 265:30]
|
|
node _T_2908 = bits(_T_2841, 20, 20) @[el2_lib.scala 261:36]
|
|
_T_2842[10] <= _T_2908 @[el2_lib.scala 261:30]
|
|
node _T_2909 = bits(_T_2841, 20, 20) @[el2_lib.scala 265:36]
|
|
_T_2846[14] <= _T_2909 @[el2_lib.scala 265:30]
|
|
node _T_2910 = bits(_T_2841, 21, 21) @[el2_lib.scala 261:36]
|
|
_T_2842[11] <= _T_2910 @[el2_lib.scala 261:30]
|
|
node _T_2911 = bits(_T_2841, 21, 21) @[el2_lib.scala 262:36]
|
|
_T_2843[11] <= _T_2911 @[el2_lib.scala 262:30]
|
|
node _T_2912 = bits(_T_2841, 21, 21) @[el2_lib.scala 263:36]
|
|
_T_2844[11] <= _T_2912 @[el2_lib.scala 263:30]
|
|
node _T_2913 = bits(_T_2841, 21, 21) @[el2_lib.scala 264:36]
|
|
_T_2845[8] <= _T_2913 @[el2_lib.scala 264:30]
|
|
node _T_2914 = bits(_T_2841, 22, 22) @[el2_lib.scala 262:36]
|
|
_T_2843[12] <= _T_2914 @[el2_lib.scala 262:30]
|
|
node _T_2915 = bits(_T_2841, 22, 22) @[el2_lib.scala 263:36]
|
|
_T_2844[12] <= _T_2915 @[el2_lib.scala 263:30]
|
|
node _T_2916 = bits(_T_2841, 22, 22) @[el2_lib.scala 264:36]
|
|
_T_2845[9] <= _T_2916 @[el2_lib.scala 264:30]
|
|
node _T_2917 = bits(_T_2841, 23, 23) @[el2_lib.scala 261:36]
|
|
_T_2842[12] <= _T_2917 @[el2_lib.scala 261:30]
|
|
node _T_2918 = bits(_T_2841, 23, 23) @[el2_lib.scala 263:36]
|
|
_T_2844[13] <= _T_2918 @[el2_lib.scala 263:30]
|
|
node _T_2919 = bits(_T_2841, 23, 23) @[el2_lib.scala 264:36]
|
|
_T_2845[10] <= _T_2919 @[el2_lib.scala 264:30]
|
|
node _T_2920 = bits(_T_2841, 24, 24) @[el2_lib.scala 263:36]
|
|
_T_2844[14] <= _T_2920 @[el2_lib.scala 263:30]
|
|
node _T_2921 = bits(_T_2841, 24, 24) @[el2_lib.scala 264:36]
|
|
_T_2845[11] <= _T_2921 @[el2_lib.scala 264:30]
|
|
node _T_2922 = bits(_T_2841, 25, 25) @[el2_lib.scala 261:36]
|
|
_T_2842[13] <= _T_2922 @[el2_lib.scala 261:30]
|
|
node _T_2923 = bits(_T_2841, 25, 25) @[el2_lib.scala 262:36]
|
|
_T_2843[13] <= _T_2923 @[el2_lib.scala 262:30]
|
|
node _T_2924 = bits(_T_2841, 25, 25) @[el2_lib.scala 264:36]
|
|
_T_2845[12] <= _T_2924 @[el2_lib.scala 264:30]
|
|
node _T_2925 = bits(_T_2841, 26, 26) @[el2_lib.scala 262:36]
|
|
_T_2843[14] <= _T_2925 @[el2_lib.scala 262:30]
|
|
node _T_2926 = bits(_T_2841, 26, 26) @[el2_lib.scala 264:36]
|
|
_T_2845[13] <= _T_2926 @[el2_lib.scala 264:30]
|
|
node _T_2927 = bits(_T_2841, 27, 27) @[el2_lib.scala 261:36]
|
|
_T_2842[14] <= _T_2927 @[el2_lib.scala 261:30]
|
|
node _T_2928 = bits(_T_2841, 27, 27) @[el2_lib.scala 264:36]
|
|
_T_2845[14] <= _T_2928 @[el2_lib.scala 264:30]
|
|
node _T_2929 = bits(_T_2841, 28, 28) @[el2_lib.scala 261:36]
|
|
_T_2842[15] <= _T_2929 @[el2_lib.scala 261:30]
|
|
node _T_2930 = bits(_T_2841, 28, 28) @[el2_lib.scala 262:36]
|
|
_T_2843[15] <= _T_2930 @[el2_lib.scala 262:30]
|
|
node _T_2931 = bits(_T_2841, 28, 28) @[el2_lib.scala 263:36]
|
|
_T_2844[15] <= _T_2931 @[el2_lib.scala 263:30]
|
|
node _T_2932 = bits(_T_2841, 29, 29) @[el2_lib.scala 262:36]
|
|
_T_2843[16] <= _T_2932 @[el2_lib.scala 262:30]
|
|
node _T_2933 = bits(_T_2841, 29, 29) @[el2_lib.scala 263:36]
|
|
_T_2844[16] <= _T_2933 @[el2_lib.scala 263:30]
|
|
node _T_2934 = bits(_T_2841, 30, 30) @[el2_lib.scala 261:36]
|
|
_T_2842[16] <= _T_2934 @[el2_lib.scala 261:30]
|
|
node _T_2935 = bits(_T_2841, 30, 30) @[el2_lib.scala 263:36]
|
|
_T_2844[17] <= _T_2935 @[el2_lib.scala 263:30]
|
|
node _T_2936 = bits(_T_2841, 31, 31) @[el2_lib.scala 261:36]
|
|
_T_2842[17] <= _T_2936 @[el2_lib.scala 261:30]
|
|
node _T_2937 = bits(_T_2841, 31, 31) @[el2_lib.scala 262:36]
|
|
_T_2843[17] <= _T_2937 @[el2_lib.scala 262:30]
|
|
node _T_2938 = cat(_T_2842[1], _T_2842[0]) @[el2_lib.scala 268:22]
|
|
node _T_2939 = cat(_T_2842[3], _T_2842[2]) @[el2_lib.scala 268:22]
|
|
node _T_2940 = cat(_T_2939, _T_2938) @[el2_lib.scala 268:22]
|
|
node _T_2941 = cat(_T_2842[5], _T_2842[4]) @[el2_lib.scala 268:22]
|
|
node _T_2942 = cat(_T_2842[8], _T_2842[7]) @[el2_lib.scala 268:22]
|
|
node _T_2943 = cat(_T_2942, _T_2842[6]) @[el2_lib.scala 268:22]
|
|
node _T_2944 = cat(_T_2943, _T_2941) @[el2_lib.scala 268:22]
|
|
node _T_2945 = cat(_T_2944, _T_2940) @[el2_lib.scala 268:22]
|
|
node _T_2946 = cat(_T_2842[10], _T_2842[9]) @[el2_lib.scala 268:22]
|
|
node _T_2947 = cat(_T_2842[12], _T_2842[11]) @[el2_lib.scala 268:22]
|
|
node _T_2948 = cat(_T_2947, _T_2946) @[el2_lib.scala 268:22]
|
|
node _T_2949 = cat(_T_2842[14], _T_2842[13]) @[el2_lib.scala 268:22]
|
|
node _T_2950 = cat(_T_2842[17], _T_2842[16]) @[el2_lib.scala 268:22]
|
|
node _T_2951 = cat(_T_2950, _T_2842[15]) @[el2_lib.scala 268:22]
|
|
node _T_2952 = cat(_T_2951, _T_2949) @[el2_lib.scala 268:22]
|
|
node _T_2953 = cat(_T_2952, _T_2948) @[el2_lib.scala 268:22]
|
|
node _T_2954 = cat(_T_2953, _T_2945) @[el2_lib.scala 268:22]
|
|
node _T_2955 = xorr(_T_2954) @[el2_lib.scala 268:29]
|
|
node _T_2956 = cat(_T_2843[1], _T_2843[0]) @[el2_lib.scala 268:39]
|
|
node _T_2957 = cat(_T_2843[3], _T_2843[2]) @[el2_lib.scala 268:39]
|
|
node _T_2958 = cat(_T_2957, _T_2956) @[el2_lib.scala 268:39]
|
|
node _T_2959 = cat(_T_2843[5], _T_2843[4]) @[el2_lib.scala 268:39]
|
|
node _T_2960 = cat(_T_2843[8], _T_2843[7]) @[el2_lib.scala 268:39]
|
|
node _T_2961 = cat(_T_2960, _T_2843[6]) @[el2_lib.scala 268:39]
|
|
node _T_2962 = cat(_T_2961, _T_2959) @[el2_lib.scala 268:39]
|
|
node _T_2963 = cat(_T_2962, _T_2958) @[el2_lib.scala 268:39]
|
|
node _T_2964 = cat(_T_2843[10], _T_2843[9]) @[el2_lib.scala 268:39]
|
|
node _T_2965 = cat(_T_2843[12], _T_2843[11]) @[el2_lib.scala 268:39]
|
|
node _T_2966 = cat(_T_2965, _T_2964) @[el2_lib.scala 268:39]
|
|
node _T_2967 = cat(_T_2843[14], _T_2843[13]) @[el2_lib.scala 268:39]
|
|
node _T_2968 = cat(_T_2843[17], _T_2843[16]) @[el2_lib.scala 268:39]
|
|
node _T_2969 = cat(_T_2968, _T_2843[15]) @[el2_lib.scala 268:39]
|
|
node _T_2970 = cat(_T_2969, _T_2967) @[el2_lib.scala 268:39]
|
|
node _T_2971 = cat(_T_2970, _T_2966) @[el2_lib.scala 268:39]
|
|
node _T_2972 = cat(_T_2971, _T_2963) @[el2_lib.scala 268:39]
|
|
node _T_2973 = xorr(_T_2972) @[el2_lib.scala 268:46]
|
|
node _T_2974 = cat(_T_2844[1], _T_2844[0]) @[el2_lib.scala 268:56]
|
|
node _T_2975 = cat(_T_2844[3], _T_2844[2]) @[el2_lib.scala 268:56]
|
|
node _T_2976 = cat(_T_2975, _T_2974) @[el2_lib.scala 268:56]
|
|
node _T_2977 = cat(_T_2844[5], _T_2844[4]) @[el2_lib.scala 268:56]
|
|
node _T_2978 = cat(_T_2844[8], _T_2844[7]) @[el2_lib.scala 268:56]
|
|
node _T_2979 = cat(_T_2978, _T_2844[6]) @[el2_lib.scala 268:56]
|
|
node _T_2980 = cat(_T_2979, _T_2977) @[el2_lib.scala 268:56]
|
|
node _T_2981 = cat(_T_2980, _T_2976) @[el2_lib.scala 268:56]
|
|
node _T_2982 = cat(_T_2844[10], _T_2844[9]) @[el2_lib.scala 268:56]
|
|
node _T_2983 = cat(_T_2844[12], _T_2844[11]) @[el2_lib.scala 268:56]
|
|
node _T_2984 = cat(_T_2983, _T_2982) @[el2_lib.scala 268:56]
|
|
node _T_2985 = cat(_T_2844[14], _T_2844[13]) @[el2_lib.scala 268:56]
|
|
node _T_2986 = cat(_T_2844[17], _T_2844[16]) @[el2_lib.scala 268:56]
|
|
node _T_2987 = cat(_T_2986, _T_2844[15]) @[el2_lib.scala 268:56]
|
|
node _T_2988 = cat(_T_2987, _T_2985) @[el2_lib.scala 268:56]
|
|
node _T_2989 = cat(_T_2988, _T_2984) @[el2_lib.scala 268:56]
|
|
node _T_2990 = cat(_T_2989, _T_2981) @[el2_lib.scala 268:56]
|
|
node _T_2991 = xorr(_T_2990) @[el2_lib.scala 268:63]
|
|
node _T_2992 = cat(_T_2845[2], _T_2845[1]) @[el2_lib.scala 268:73]
|
|
node _T_2993 = cat(_T_2992, _T_2845[0]) @[el2_lib.scala 268:73]
|
|
node _T_2994 = cat(_T_2845[4], _T_2845[3]) @[el2_lib.scala 268:73]
|
|
node _T_2995 = cat(_T_2845[6], _T_2845[5]) @[el2_lib.scala 268:73]
|
|
node _T_2996 = cat(_T_2995, _T_2994) @[el2_lib.scala 268:73]
|
|
node _T_2997 = cat(_T_2996, _T_2993) @[el2_lib.scala 268:73]
|
|
node _T_2998 = cat(_T_2845[8], _T_2845[7]) @[el2_lib.scala 268:73]
|
|
node _T_2999 = cat(_T_2845[10], _T_2845[9]) @[el2_lib.scala 268:73]
|
|
node _T_3000 = cat(_T_2999, _T_2998) @[el2_lib.scala 268:73]
|
|
node _T_3001 = cat(_T_2845[12], _T_2845[11]) @[el2_lib.scala 268:73]
|
|
node _T_3002 = cat(_T_2845[14], _T_2845[13]) @[el2_lib.scala 268:73]
|
|
node _T_3003 = cat(_T_3002, _T_3001) @[el2_lib.scala 268:73]
|
|
node _T_3004 = cat(_T_3003, _T_3000) @[el2_lib.scala 268:73]
|
|
node _T_3005 = cat(_T_3004, _T_2997) @[el2_lib.scala 268:73]
|
|
node _T_3006 = xorr(_T_3005) @[el2_lib.scala 268:80]
|
|
node _T_3007 = cat(_T_2846[2], _T_2846[1]) @[el2_lib.scala 268:90]
|
|
node _T_3008 = cat(_T_3007, _T_2846[0]) @[el2_lib.scala 268:90]
|
|
node _T_3009 = cat(_T_2846[4], _T_2846[3]) @[el2_lib.scala 268:90]
|
|
node _T_3010 = cat(_T_2846[6], _T_2846[5]) @[el2_lib.scala 268:90]
|
|
node _T_3011 = cat(_T_3010, _T_3009) @[el2_lib.scala 268:90]
|
|
node _T_3012 = cat(_T_3011, _T_3008) @[el2_lib.scala 268:90]
|
|
node _T_3013 = cat(_T_2846[8], _T_2846[7]) @[el2_lib.scala 268:90]
|
|
node _T_3014 = cat(_T_2846[10], _T_2846[9]) @[el2_lib.scala 268:90]
|
|
node _T_3015 = cat(_T_3014, _T_3013) @[el2_lib.scala 268:90]
|
|
node _T_3016 = cat(_T_2846[12], _T_2846[11]) @[el2_lib.scala 268:90]
|
|
node _T_3017 = cat(_T_2846[14], _T_2846[13]) @[el2_lib.scala 268:90]
|
|
node _T_3018 = cat(_T_3017, _T_3016) @[el2_lib.scala 268:90]
|
|
node _T_3019 = cat(_T_3018, _T_3015) @[el2_lib.scala 268:90]
|
|
node _T_3020 = cat(_T_3019, _T_3012) @[el2_lib.scala 268:90]
|
|
node _T_3021 = xorr(_T_3020) @[el2_lib.scala 268:97]
|
|
node _T_3022 = cat(_T_2847[2], _T_2847[1]) @[el2_lib.scala 268:107]
|
|
node _T_3023 = cat(_T_3022, _T_2847[0]) @[el2_lib.scala 268:107]
|
|
node _T_3024 = cat(_T_2847[5], _T_2847[4]) @[el2_lib.scala 268:107]
|
|
node _T_3025 = cat(_T_3024, _T_2847[3]) @[el2_lib.scala 268:107]
|
|
node _T_3026 = cat(_T_3025, _T_3023) @[el2_lib.scala 268:107]
|
|
node _T_3027 = xorr(_T_3026) @[el2_lib.scala 268:114]
|
|
node _T_3028 = cat(_T_3006, _T_3021) @[Cat.scala 29:58]
|
|
node _T_3029 = cat(_T_3028, _T_3027) @[Cat.scala 29:58]
|
|
node _T_3030 = cat(_T_2955, _T_2973) @[Cat.scala 29:58]
|
|
node _T_3031 = cat(_T_3030, _T_2991) @[Cat.scala 29:58]
|
|
node _T_3032 = cat(_T_3031, _T_3029) @[Cat.scala 29:58]
|
|
node _T_3033 = xorr(_T_2841) @[el2_lib.scala 269:13]
|
|
node _T_3034 = xorr(_T_3032) @[el2_lib.scala 269:23]
|
|
node _T_3035 = xor(_T_3033, _T_3034) @[el2_lib.scala 269:18]
|
|
node _T_3036 = cat(_T_3035, _T_3032) @[Cat.scala 29:58]
|
|
node dma_mem_ecc = cat(_T_2840, _T_3036) @[Cat.scala 29:58]
|
|
wire iccm_ecc_corr_data_ff : UInt<39>
|
|
iccm_ecc_corr_data_ff <= UInt<1>("h00")
|
|
node _T_3037 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 631:67]
|
|
node _T_3038 = eq(_T_3037, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 631:45]
|
|
node _T_3039 = and(iccm_correct_ecc, _T_3038) @[el2_ifu_mem_ctl.scala 631:43]
|
|
node _T_3040 = cat(iccm_ecc_corr_data_ff, iccm_ecc_corr_data_ff) @[Cat.scala 29:58]
|
|
node _T_3041 = bits(dma_mem_ecc, 13, 7) @[el2_ifu_mem_ctl.scala 632:20]
|
|
node _T_3042 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 632:43]
|
|
node _T_3043 = bits(dma_mem_ecc, 6, 0) @[el2_ifu_mem_ctl.scala 632:63]
|
|
node _T_3044 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 632:86]
|
|
node _T_3045 = cat(_T_3043, _T_3044) @[Cat.scala 29:58]
|
|
node _T_3046 = cat(_T_3041, _T_3042) @[Cat.scala 29:58]
|
|
node _T_3047 = cat(_T_3046, _T_3045) @[Cat.scala 29:58]
|
|
node _T_3048 = mux(_T_3039, _T_3040, _T_3047) @[el2_ifu_mem_ctl.scala 631:25]
|
|
io.iccm_wr_data <= _T_3048 @[el2_ifu_mem_ctl.scala 631:19]
|
|
wire iccm_corrected_data : UInt<32>[2] @[el2_ifu_mem_ctl.scala 633:33]
|
|
iccm_corrected_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 634:26]
|
|
iccm_corrected_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 635:26]
|
|
wire dma_mem_addr_ff : UInt<2>
|
|
dma_mem_addr_ff <= UInt<1>("h00")
|
|
node _T_3049 = bits(dma_mem_addr_ff, 0, 0) @[el2_ifu_mem_ctl.scala 637:51]
|
|
node _T_3050 = bits(_T_3049, 0, 0) @[el2_ifu_mem_ctl.scala 637:55]
|
|
node iccm_dma_rdata_1_muxed = mux(_T_3050, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 637:35]
|
|
wire iccm_double_ecc_error : UInt<2>
|
|
iccm_double_ecc_error <= UInt<1>("h00")
|
|
node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 639:53]
|
|
node _T_3051 = cat(io.dma_mem_addr, io.dma_mem_addr) @[Cat.scala 29:58]
|
|
node _T_3052 = cat(iccm_dma_rdata_1_muxed, iccm_corrected_data[0]) @[Cat.scala 29:58]
|
|
node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3051, _T_3052) @[el2_ifu_mem_ctl.scala 640:30]
|
|
reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 641:54]
|
|
dma_mem_tag_ff <= io.dma_mem_tag @[el2_ifu_mem_ctl.scala 641:54]
|
|
reg iccm_dma_rtag : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 642:69]
|
|
iccm_dma_rtag <= dma_mem_tag_ff @[el2_ifu_mem_ctl.scala 642:69]
|
|
io.iccm_dma_rtag <= iccm_dma_rtag @[el2_ifu_mem_ctl.scala 643:20]
|
|
node _T_3053 = bits(io.dma_mem_addr, 3, 2) @[el2_ifu_mem_ctl.scala 645:69]
|
|
reg _T_3054 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 645:53]
|
|
_T_3054 <= _T_3053 @[el2_ifu_mem_ctl.scala 645:53]
|
|
dma_mem_addr_ff <= _T_3054 @[el2_ifu_mem_ctl.scala 645:19]
|
|
reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 646:59]
|
|
iccm_dma_rvalid_in <= iccm_dma_rden @[el2_ifu_mem_ctl.scala 646:59]
|
|
reg iccm_dma_rvalid : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 647:71]
|
|
iccm_dma_rvalid <= iccm_dma_rvalid_in @[el2_ifu_mem_ctl.scala 647:71]
|
|
io.iccm_dma_rvalid <= iccm_dma_rvalid @[el2_ifu_mem_ctl.scala 648:22]
|
|
reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 649:74]
|
|
iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 649:74]
|
|
io.iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 650:25]
|
|
reg iccm_dma_rdata : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 651:70]
|
|
iccm_dma_rdata <= iccm_dma_rdata_in @[el2_ifu_mem_ctl.scala 651:70]
|
|
io.iccm_dma_rdata <= iccm_dma_rdata @[el2_ifu_mem_ctl.scala 652:21]
|
|
wire iccm_ecc_corr_index_ff : UInt<14>
|
|
iccm_ecc_corr_index_ff <= UInt<1>("h00")
|
|
node _T_3055 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 654:46]
|
|
node _T_3056 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 654:67]
|
|
node _T_3057 = and(_T_3055, _T_3056) @[el2_ifu_mem_ctl.scala 654:65]
|
|
node _T_3058 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 655:31]
|
|
node _T_3059 = eq(_T_3058, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 655:9]
|
|
node _T_3060 = and(_T_3059, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 655:50]
|
|
node _T_3061 = cat(iccm_ecc_corr_index_ff, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_3062 = bits(io.ifc_fetch_addr_bf, 15, 0) @[el2_ifu_mem_ctl.scala 655:124]
|
|
node _T_3063 = mux(_T_3060, _T_3061, _T_3062) @[el2_ifu_mem_ctl.scala 655:8]
|
|
node _T_3064 = mux(_T_3057, io.dma_mem_addr, _T_3063) @[el2_ifu_mem_ctl.scala 654:25]
|
|
io.iccm_rw_addr <= _T_3064 @[el2_ifu_mem_ctl.scala 654:19]
|
|
node ic_fetch_val_int_f = cat(UInt<2>("h00"), io.ic_fetch_val_f) @[Cat.scala 29:58]
|
|
node _T_3065 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 657:76]
|
|
node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3065) @[el2_ifu_mem_ctl.scala 657:53]
|
|
node _T_3066 = bits(ic_fetch_val_shift_right, 1, 0) @[el2_ifu_mem_ctl.scala 660:75]
|
|
node _T_3067 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 660:93]
|
|
node _T_3068 = and(_T_3066, _T_3067) @[el2_ifu_mem_ctl.scala 660:91]
|
|
node _T_3069 = and(_T_3068, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 660:113]
|
|
node _T_3070 = or(_T_3069, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 660:130]
|
|
node _T_3071 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 660:154]
|
|
node _T_3072 = and(_T_3070, _T_3071) @[el2_ifu_mem_ctl.scala 660:152]
|
|
node _T_3073 = bits(ic_fetch_val_shift_right, 3, 2) @[el2_ifu_mem_ctl.scala 660:75]
|
|
node _T_3074 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 660:93]
|
|
node _T_3075 = and(_T_3073, _T_3074) @[el2_ifu_mem_ctl.scala 660:91]
|
|
node _T_3076 = and(_T_3075, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 660:113]
|
|
node _T_3077 = or(_T_3076, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 660:130]
|
|
node _T_3078 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 660:154]
|
|
node _T_3079 = and(_T_3077, _T_3078) @[el2_ifu_mem_ctl.scala 660:152]
|
|
node iccm_ecc_word_enable = cat(_T_3079, _T_3072) @[Cat.scala 29:58]
|
|
node _T_3080 = bits(iccm_ecc_word_enable, 0, 0) @[el2_ifu_mem_ctl.scala 661:73]
|
|
node _T_3081 = bits(io.iccm_rd_data_ecc, 31, 0) @[el2_ifu_mem_ctl.scala 661:93]
|
|
node _T_3082 = bits(io.iccm_rd_data_ecc, 38, 32) @[el2_ifu_mem_ctl.scala 661:128]
|
|
wire _T_3083 : UInt<1>[18] @[el2_lib.scala 281:18]
|
|
wire _T_3084 : UInt<1>[18] @[el2_lib.scala 282:18]
|
|
wire _T_3085 : UInt<1>[18] @[el2_lib.scala 283:18]
|
|
wire _T_3086 : UInt<1>[15] @[el2_lib.scala 284:18]
|
|
wire _T_3087 : UInt<1>[15] @[el2_lib.scala 285:18]
|
|
wire _T_3088 : UInt<1>[6] @[el2_lib.scala 286:18]
|
|
node _T_3089 = bits(_T_3081, 0, 0) @[el2_lib.scala 293:36]
|
|
_T_3083[0] <= _T_3089 @[el2_lib.scala 293:30]
|
|
node _T_3090 = bits(_T_3081, 0, 0) @[el2_lib.scala 294:36]
|
|
_T_3084[0] <= _T_3090 @[el2_lib.scala 294:30]
|
|
node _T_3091 = bits(_T_3081, 1, 1) @[el2_lib.scala 293:36]
|
|
_T_3083[1] <= _T_3091 @[el2_lib.scala 293:30]
|
|
node _T_3092 = bits(_T_3081, 1, 1) @[el2_lib.scala 295:36]
|
|
_T_3085[0] <= _T_3092 @[el2_lib.scala 295:30]
|
|
node _T_3093 = bits(_T_3081, 2, 2) @[el2_lib.scala 294:36]
|
|
_T_3084[1] <= _T_3093 @[el2_lib.scala 294:30]
|
|
node _T_3094 = bits(_T_3081, 2, 2) @[el2_lib.scala 295:36]
|
|
_T_3085[1] <= _T_3094 @[el2_lib.scala 295:30]
|
|
node _T_3095 = bits(_T_3081, 3, 3) @[el2_lib.scala 293:36]
|
|
_T_3083[2] <= _T_3095 @[el2_lib.scala 293:30]
|
|
node _T_3096 = bits(_T_3081, 3, 3) @[el2_lib.scala 294:36]
|
|
_T_3084[2] <= _T_3096 @[el2_lib.scala 294:30]
|
|
node _T_3097 = bits(_T_3081, 3, 3) @[el2_lib.scala 295:36]
|
|
_T_3085[2] <= _T_3097 @[el2_lib.scala 295:30]
|
|
node _T_3098 = bits(_T_3081, 4, 4) @[el2_lib.scala 293:36]
|
|
_T_3083[3] <= _T_3098 @[el2_lib.scala 293:30]
|
|
node _T_3099 = bits(_T_3081, 4, 4) @[el2_lib.scala 296:36]
|
|
_T_3086[0] <= _T_3099 @[el2_lib.scala 296:30]
|
|
node _T_3100 = bits(_T_3081, 5, 5) @[el2_lib.scala 294:36]
|
|
_T_3084[3] <= _T_3100 @[el2_lib.scala 294:30]
|
|
node _T_3101 = bits(_T_3081, 5, 5) @[el2_lib.scala 296:36]
|
|
_T_3086[1] <= _T_3101 @[el2_lib.scala 296:30]
|
|
node _T_3102 = bits(_T_3081, 6, 6) @[el2_lib.scala 293:36]
|
|
_T_3083[4] <= _T_3102 @[el2_lib.scala 293:30]
|
|
node _T_3103 = bits(_T_3081, 6, 6) @[el2_lib.scala 294:36]
|
|
_T_3084[4] <= _T_3103 @[el2_lib.scala 294:30]
|
|
node _T_3104 = bits(_T_3081, 6, 6) @[el2_lib.scala 296:36]
|
|
_T_3086[2] <= _T_3104 @[el2_lib.scala 296:30]
|
|
node _T_3105 = bits(_T_3081, 7, 7) @[el2_lib.scala 295:36]
|
|
_T_3085[3] <= _T_3105 @[el2_lib.scala 295:30]
|
|
node _T_3106 = bits(_T_3081, 7, 7) @[el2_lib.scala 296:36]
|
|
_T_3086[3] <= _T_3106 @[el2_lib.scala 296:30]
|
|
node _T_3107 = bits(_T_3081, 8, 8) @[el2_lib.scala 293:36]
|
|
_T_3083[5] <= _T_3107 @[el2_lib.scala 293:30]
|
|
node _T_3108 = bits(_T_3081, 8, 8) @[el2_lib.scala 295:36]
|
|
_T_3085[4] <= _T_3108 @[el2_lib.scala 295:30]
|
|
node _T_3109 = bits(_T_3081, 8, 8) @[el2_lib.scala 296:36]
|
|
_T_3086[4] <= _T_3109 @[el2_lib.scala 296:30]
|
|
node _T_3110 = bits(_T_3081, 9, 9) @[el2_lib.scala 294:36]
|
|
_T_3084[5] <= _T_3110 @[el2_lib.scala 294:30]
|
|
node _T_3111 = bits(_T_3081, 9, 9) @[el2_lib.scala 295:36]
|
|
_T_3085[5] <= _T_3111 @[el2_lib.scala 295:30]
|
|
node _T_3112 = bits(_T_3081, 9, 9) @[el2_lib.scala 296:36]
|
|
_T_3086[5] <= _T_3112 @[el2_lib.scala 296:30]
|
|
node _T_3113 = bits(_T_3081, 10, 10) @[el2_lib.scala 293:36]
|
|
_T_3083[6] <= _T_3113 @[el2_lib.scala 293:30]
|
|
node _T_3114 = bits(_T_3081, 10, 10) @[el2_lib.scala 294:36]
|
|
_T_3084[6] <= _T_3114 @[el2_lib.scala 294:30]
|
|
node _T_3115 = bits(_T_3081, 10, 10) @[el2_lib.scala 295:36]
|
|
_T_3085[6] <= _T_3115 @[el2_lib.scala 295:30]
|
|
node _T_3116 = bits(_T_3081, 10, 10) @[el2_lib.scala 296:36]
|
|
_T_3086[6] <= _T_3116 @[el2_lib.scala 296:30]
|
|
node _T_3117 = bits(_T_3081, 11, 11) @[el2_lib.scala 293:36]
|
|
_T_3083[7] <= _T_3117 @[el2_lib.scala 293:30]
|
|
node _T_3118 = bits(_T_3081, 11, 11) @[el2_lib.scala 297:36]
|
|
_T_3087[0] <= _T_3118 @[el2_lib.scala 297:30]
|
|
node _T_3119 = bits(_T_3081, 12, 12) @[el2_lib.scala 294:36]
|
|
_T_3084[7] <= _T_3119 @[el2_lib.scala 294:30]
|
|
node _T_3120 = bits(_T_3081, 12, 12) @[el2_lib.scala 297:36]
|
|
_T_3087[1] <= _T_3120 @[el2_lib.scala 297:30]
|
|
node _T_3121 = bits(_T_3081, 13, 13) @[el2_lib.scala 293:36]
|
|
_T_3083[8] <= _T_3121 @[el2_lib.scala 293:30]
|
|
node _T_3122 = bits(_T_3081, 13, 13) @[el2_lib.scala 294:36]
|
|
_T_3084[8] <= _T_3122 @[el2_lib.scala 294:30]
|
|
node _T_3123 = bits(_T_3081, 13, 13) @[el2_lib.scala 297:36]
|
|
_T_3087[2] <= _T_3123 @[el2_lib.scala 297:30]
|
|
node _T_3124 = bits(_T_3081, 14, 14) @[el2_lib.scala 295:36]
|
|
_T_3085[7] <= _T_3124 @[el2_lib.scala 295:30]
|
|
node _T_3125 = bits(_T_3081, 14, 14) @[el2_lib.scala 297:36]
|
|
_T_3087[3] <= _T_3125 @[el2_lib.scala 297:30]
|
|
node _T_3126 = bits(_T_3081, 15, 15) @[el2_lib.scala 293:36]
|
|
_T_3083[9] <= _T_3126 @[el2_lib.scala 293:30]
|
|
node _T_3127 = bits(_T_3081, 15, 15) @[el2_lib.scala 295:36]
|
|
_T_3085[8] <= _T_3127 @[el2_lib.scala 295:30]
|
|
node _T_3128 = bits(_T_3081, 15, 15) @[el2_lib.scala 297:36]
|
|
_T_3087[4] <= _T_3128 @[el2_lib.scala 297:30]
|
|
node _T_3129 = bits(_T_3081, 16, 16) @[el2_lib.scala 294:36]
|
|
_T_3084[9] <= _T_3129 @[el2_lib.scala 294:30]
|
|
node _T_3130 = bits(_T_3081, 16, 16) @[el2_lib.scala 295:36]
|
|
_T_3085[9] <= _T_3130 @[el2_lib.scala 295:30]
|
|
node _T_3131 = bits(_T_3081, 16, 16) @[el2_lib.scala 297:36]
|
|
_T_3087[5] <= _T_3131 @[el2_lib.scala 297:30]
|
|
node _T_3132 = bits(_T_3081, 17, 17) @[el2_lib.scala 293:36]
|
|
_T_3083[10] <= _T_3132 @[el2_lib.scala 293:30]
|
|
node _T_3133 = bits(_T_3081, 17, 17) @[el2_lib.scala 294:36]
|
|
_T_3084[10] <= _T_3133 @[el2_lib.scala 294:30]
|
|
node _T_3134 = bits(_T_3081, 17, 17) @[el2_lib.scala 295:36]
|
|
_T_3085[10] <= _T_3134 @[el2_lib.scala 295:30]
|
|
node _T_3135 = bits(_T_3081, 17, 17) @[el2_lib.scala 297:36]
|
|
_T_3087[6] <= _T_3135 @[el2_lib.scala 297:30]
|
|
node _T_3136 = bits(_T_3081, 18, 18) @[el2_lib.scala 296:36]
|
|
_T_3086[7] <= _T_3136 @[el2_lib.scala 296:30]
|
|
node _T_3137 = bits(_T_3081, 18, 18) @[el2_lib.scala 297:36]
|
|
_T_3087[7] <= _T_3137 @[el2_lib.scala 297:30]
|
|
node _T_3138 = bits(_T_3081, 19, 19) @[el2_lib.scala 293:36]
|
|
_T_3083[11] <= _T_3138 @[el2_lib.scala 293:30]
|
|
node _T_3139 = bits(_T_3081, 19, 19) @[el2_lib.scala 296:36]
|
|
_T_3086[8] <= _T_3139 @[el2_lib.scala 296:30]
|
|
node _T_3140 = bits(_T_3081, 19, 19) @[el2_lib.scala 297:36]
|
|
_T_3087[8] <= _T_3140 @[el2_lib.scala 297:30]
|
|
node _T_3141 = bits(_T_3081, 20, 20) @[el2_lib.scala 294:36]
|
|
_T_3084[11] <= _T_3141 @[el2_lib.scala 294:30]
|
|
node _T_3142 = bits(_T_3081, 20, 20) @[el2_lib.scala 296:36]
|
|
_T_3086[9] <= _T_3142 @[el2_lib.scala 296:30]
|
|
node _T_3143 = bits(_T_3081, 20, 20) @[el2_lib.scala 297:36]
|
|
_T_3087[9] <= _T_3143 @[el2_lib.scala 297:30]
|
|
node _T_3144 = bits(_T_3081, 21, 21) @[el2_lib.scala 293:36]
|
|
_T_3083[12] <= _T_3144 @[el2_lib.scala 293:30]
|
|
node _T_3145 = bits(_T_3081, 21, 21) @[el2_lib.scala 294:36]
|
|
_T_3084[12] <= _T_3145 @[el2_lib.scala 294:30]
|
|
node _T_3146 = bits(_T_3081, 21, 21) @[el2_lib.scala 296:36]
|
|
_T_3086[10] <= _T_3146 @[el2_lib.scala 296:30]
|
|
node _T_3147 = bits(_T_3081, 21, 21) @[el2_lib.scala 297:36]
|
|
_T_3087[10] <= _T_3147 @[el2_lib.scala 297:30]
|
|
node _T_3148 = bits(_T_3081, 22, 22) @[el2_lib.scala 295:36]
|
|
_T_3085[11] <= _T_3148 @[el2_lib.scala 295:30]
|
|
node _T_3149 = bits(_T_3081, 22, 22) @[el2_lib.scala 296:36]
|
|
_T_3086[11] <= _T_3149 @[el2_lib.scala 296:30]
|
|
node _T_3150 = bits(_T_3081, 22, 22) @[el2_lib.scala 297:36]
|
|
_T_3087[11] <= _T_3150 @[el2_lib.scala 297:30]
|
|
node _T_3151 = bits(_T_3081, 23, 23) @[el2_lib.scala 293:36]
|
|
_T_3083[13] <= _T_3151 @[el2_lib.scala 293:30]
|
|
node _T_3152 = bits(_T_3081, 23, 23) @[el2_lib.scala 295:36]
|
|
_T_3085[12] <= _T_3152 @[el2_lib.scala 295:30]
|
|
node _T_3153 = bits(_T_3081, 23, 23) @[el2_lib.scala 296:36]
|
|
_T_3086[12] <= _T_3153 @[el2_lib.scala 296:30]
|
|
node _T_3154 = bits(_T_3081, 23, 23) @[el2_lib.scala 297:36]
|
|
_T_3087[12] <= _T_3154 @[el2_lib.scala 297:30]
|
|
node _T_3155 = bits(_T_3081, 24, 24) @[el2_lib.scala 294:36]
|
|
_T_3084[13] <= _T_3155 @[el2_lib.scala 294:30]
|
|
node _T_3156 = bits(_T_3081, 24, 24) @[el2_lib.scala 295:36]
|
|
_T_3085[13] <= _T_3156 @[el2_lib.scala 295:30]
|
|
node _T_3157 = bits(_T_3081, 24, 24) @[el2_lib.scala 296:36]
|
|
_T_3086[13] <= _T_3157 @[el2_lib.scala 296:30]
|
|
node _T_3158 = bits(_T_3081, 24, 24) @[el2_lib.scala 297:36]
|
|
_T_3087[13] <= _T_3158 @[el2_lib.scala 297:30]
|
|
node _T_3159 = bits(_T_3081, 25, 25) @[el2_lib.scala 293:36]
|
|
_T_3083[14] <= _T_3159 @[el2_lib.scala 293:30]
|
|
node _T_3160 = bits(_T_3081, 25, 25) @[el2_lib.scala 294:36]
|
|
_T_3084[14] <= _T_3160 @[el2_lib.scala 294:30]
|
|
node _T_3161 = bits(_T_3081, 25, 25) @[el2_lib.scala 295:36]
|
|
_T_3085[14] <= _T_3161 @[el2_lib.scala 295:30]
|
|
node _T_3162 = bits(_T_3081, 25, 25) @[el2_lib.scala 296:36]
|
|
_T_3086[14] <= _T_3162 @[el2_lib.scala 296:30]
|
|
node _T_3163 = bits(_T_3081, 25, 25) @[el2_lib.scala 297:36]
|
|
_T_3087[14] <= _T_3163 @[el2_lib.scala 297:30]
|
|
node _T_3164 = bits(_T_3081, 26, 26) @[el2_lib.scala 293:36]
|
|
_T_3083[15] <= _T_3164 @[el2_lib.scala 293:30]
|
|
node _T_3165 = bits(_T_3081, 26, 26) @[el2_lib.scala 298:36]
|
|
_T_3088[0] <= _T_3165 @[el2_lib.scala 298:30]
|
|
node _T_3166 = bits(_T_3081, 27, 27) @[el2_lib.scala 294:36]
|
|
_T_3084[15] <= _T_3166 @[el2_lib.scala 294:30]
|
|
node _T_3167 = bits(_T_3081, 27, 27) @[el2_lib.scala 298:36]
|
|
_T_3088[1] <= _T_3167 @[el2_lib.scala 298:30]
|
|
node _T_3168 = bits(_T_3081, 28, 28) @[el2_lib.scala 293:36]
|
|
_T_3083[16] <= _T_3168 @[el2_lib.scala 293:30]
|
|
node _T_3169 = bits(_T_3081, 28, 28) @[el2_lib.scala 294:36]
|
|
_T_3084[16] <= _T_3169 @[el2_lib.scala 294:30]
|
|
node _T_3170 = bits(_T_3081, 28, 28) @[el2_lib.scala 298:36]
|
|
_T_3088[2] <= _T_3170 @[el2_lib.scala 298:30]
|
|
node _T_3171 = bits(_T_3081, 29, 29) @[el2_lib.scala 295:36]
|
|
_T_3085[15] <= _T_3171 @[el2_lib.scala 295:30]
|
|
node _T_3172 = bits(_T_3081, 29, 29) @[el2_lib.scala 298:36]
|
|
_T_3088[3] <= _T_3172 @[el2_lib.scala 298:30]
|
|
node _T_3173 = bits(_T_3081, 30, 30) @[el2_lib.scala 293:36]
|
|
_T_3083[17] <= _T_3173 @[el2_lib.scala 293:30]
|
|
node _T_3174 = bits(_T_3081, 30, 30) @[el2_lib.scala 295:36]
|
|
_T_3085[16] <= _T_3174 @[el2_lib.scala 295:30]
|
|
node _T_3175 = bits(_T_3081, 30, 30) @[el2_lib.scala 298:36]
|
|
_T_3088[4] <= _T_3175 @[el2_lib.scala 298:30]
|
|
node _T_3176 = bits(_T_3081, 31, 31) @[el2_lib.scala 294:36]
|
|
_T_3084[17] <= _T_3176 @[el2_lib.scala 294:30]
|
|
node _T_3177 = bits(_T_3081, 31, 31) @[el2_lib.scala 295:36]
|
|
_T_3085[17] <= _T_3177 @[el2_lib.scala 295:30]
|
|
node _T_3178 = bits(_T_3081, 31, 31) @[el2_lib.scala 298:36]
|
|
_T_3088[5] <= _T_3178 @[el2_lib.scala 298:30]
|
|
node _T_3179 = xorr(_T_3081) @[el2_lib.scala 301:30]
|
|
node _T_3180 = xorr(_T_3082) @[el2_lib.scala 301:44]
|
|
node _T_3181 = xor(_T_3179, _T_3180) @[el2_lib.scala 301:35]
|
|
node _T_3182 = not(UInt<1>("h00")) @[el2_lib.scala 301:52]
|
|
node _T_3183 = and(_T_3181, _T_3182) @[el2_lib.scala 301:50]
|
|
node _T_3184 = bits(_T_3082, 5, 5) @[el2_lib.scala 301:68]
|
|
node _T_3185 = cat(_T_3088[2], _T_3088[1]) @[el2_lib.scala 301:76]
|
|
node _T_3186 = cat(_T_3185, _T_3088[0]) @[el2_lib.scala 301:76]
|
|
node _T_3187 = cat(_T_3088[5], _T_3088[4]) @[el2_lib.scala 301:76]
|
|
node _T_3188 = cat(_T_3187, _T_3088[3]) @[el2_lib.scala 301:76]
|
|
node _T_3189 = cat(_T_3188, _T_3186) @[el2_lib.scala 301:76]
|
|
node _T_3190 = xorr(_T_3189) @[el2_lib.scala 301:83]
|
|
node _T_3191 = xor(_T_3184, _T_3190) @[el2_lib.scala 301:71]
|
|
node _T_3192 = bits(_T_3082, 4, 4) @[el2_lib.scala 301:95]
|
|
node _T_3193 = cat(_T_3087[2], _T_3087[1]) @[el2_lib.scala 301:103]
|
|
node _T_3194 = cat(_T_3193, _T_3087[0]) @[el2_lib.scala 301:103]
|
|
node _T_3195 = cat(_T_3087[4], _T_3087[3]) @[el2_lib.scala 301:103]
|
|
node _T_3196 = cat(_T_3087[6], _T_3087[5]) @[el2_lib.scala 301:103]
|
|
node _T_3197 = cat(_T_3196, _T_3195) @[el2_lib.scala 301:103]
|
|
node _T_3198 = cat(_T_3197, _T_3194) @[el2_lib.scala 301:103]
|
|
node _T_3199 = cat(_T_3087[8], _T_3087[7]) @[el2_lib.scala 301:103]
|
|
node _T_3200 = cat(_T_3087[10], _T_3087[9]) @[el2_lib.scala 301:103]
|
|
node _T_3201 = cat(_T_3200, _T_3199) @[el2_lib.scala 301:103]
|
|
node _T_3202 = cat(_T_3087[12], _T_3087[11]) @[el2_lib.scala 301:103]
|
|
node _T_3203 = cat(_T_3087[14], _T_3087[13]) @[el2_lib.scala 301:103]
|
|
node _T_3204 = cat(_T_3203, _T_3202) @[el2_lib.scala 301:103]
|
|
node _T_3205 = cat(_T_3204, _T_3201) @[el2_lib.scala 301:103]
|
|
node _T_3206 = cat(_T_3205, _T_3198) @[el2_lib.scala 301:103]
|
|
node _T_3207 = xorr(_T_3206) @[el2_lib.scala 301:110]
|
|
node _T_3208 = xor(_T_3192, _T_3207) @[el2_lib.scala 301:98]
|
|
node _T_3209 = bits(_T_3082, 3, 3) @[el2_lib.scala 301:122]
|
|
node _T_3210 = cat(_T_3086[2], _T_3086[1]) @[el2_lib.scala 301:130]
|
|
node _T_3211 = cat(_T_3210, _T_3086[0]) @[el2_lib.scala 301:130]
|
|
node _T_3212 = cat(_T_3086[4], _T_3086[3]) @[el2_lib.scala 301:130]
|
|
node _T_3213 = cat(_T_3086[6], _T_3086[5]) @[el2_lib.scala 301:130]
|
|
node _T_3214 = cat(_T_3213, _T_3212) @[el2_lib.scala 301:130]
|
|
node _T_3215 = cat(_T_3214, _T_3211) @[el2_lib.scala 301:130]
|
|
node _T_3216 = cat(_T_3086[8], _T_3086[7]) @[el2_lib.scala 301:130]
|
|
node _T_3217 = cat(_T_3086[10], _T_3086[9]) @[el2_lib.scala 301:130]
|
|
node _T_3218 = cat(_T_3217, _T_3216) @[el2_lib.scala 301:130]
|
|
node _T_3219 = cat(_T_3086[12], _T_3086[11]) @[el2_lib.scala 301:130]
|
|
node _T_3220 = cat(_T_3086[14], _T_3086[13]) @[el2_lib.scala 301:130]
|
|
node _T_3221 = cat(_T_3220, _T_3219) @[el2_lib.scala 301:130]
|
|
node _T_3222 = cat(_T_3221, _T_3218) @[el2_lib.scala 301:130]
|
|
node _T_3223 = cat(_T_3222, _T_3215) @[el2_lib.scala 301:130]
|
|
node _T_3224 = xorr(_T_3223) @[el2_lib.scala 301:137]
|
|
node _T_3225 = xor(_T_3209, _T_3224) @[el2_lib.scala 301:125]
|
|
node _T_3226 = bits(_T_3082, 2, 2) @[el2_lib.scala 301:149]
|
|
node _T_3227 = cat(_T_3085[1], _T_3085[0]) @[el2_lib.scala 301:157]
|
|
node _T_3228 = cat(_T_3085[3], _T_3085[2]) @[el2_lib.scala 301:157]
|
|
node _T_3229 = cat(_T_3228, _T_3227) @[el2_lib.scala 301:157]
|
|
node _T_3230 = cat(_T_3085[5], _T_3085[4]) @[el2_lib.scala 301:157]
|
|
node _T_3231 = cat(_T_3085[8], _T_3085[7]) @[el2_lib.scala 301:157]
|
|
node _T_3232 = cat(_T_3231, _T_3085[6]) @[el2_lib.scala 301:157]
|
|
node _T_3233 = cat(_T_3232, _T_3230) @[el2_lib.scala 301:157]
|
|
node _T_3234 = cat(_T_3233, _T_3229) @[el2_lib.scala 301:157]
|
|
node _T_3235 = cat(_T_3085[10], _T_3085[9]) @[el2_lib.scala 301:157]
|
|
node _T_3236 = cat(_T_3085[12], _T_3085[11]) @[el2_lib.scala 301:157]
|
|
node _T_3237 = cat(_T_3236, _T_3235) @[el2_lib.scala 301:157]
|
|
node _T_3238 = cat(_T_3085[14], _T_3085[13]) @[el2_lib.scala 301:157]
|
|
node _T_3239 = cat(_T_3085[17], _T_3085[16]) @[el2_lib.scala 301:157]
|
|
node _T_3240 = cat(_T_3239, _T_3085[15]) @[el2_lib.scala 301:157]
|
|
node _T_3241 = cat(_T_3240, _T_3238) @[el2_lib.scala 301:157]
|
|
node _T_3242 = cat(_T_3241, _T_3237) @[el2_lib.scala 301:157]
|
|
node _T_3243 = cat(_T_3242, _T_3234) @[el2_lib.scala 301:157]
|
|
node _T_3244 = xorr(_T_3243) @[el2_lib.scala 301:164]
|
|
node _T_3245 = xor(_T_3226, _T_3244) @[el2_lib.scala 301:152]
|
|
node _T_3246 = bits(_T_3082, 1, 1) @[el2_lib.scala 301:176]
|
|
node _T_3247 = cat(_T_3084[1], _T_3084[0]) @[el2_lib.scala 301:184]
|
|
node _T_3248 = cat(_T_3084[3], _T_3084[2]) @[el2_lib.scala 301:184]
|
|
node _T_3249 = cat(_T_3248, _T_3247) @[el2_lib.scala 301:184]
|
|
node _T_3250 = cat(_T_3084[5], _T_3084[4]) @[el2_lib.scala 301:184]
|
|
node _T_3251 = cat(_T_3084[8], _T_3084[7]) @[el2_lib.scala 301:184]
|
|
node _T_3252 = cat(_T_3251, _T_3084[6]) @[el2_lib.scala 301:184]
|
|
node _T_3253 = cat(_T_3252, _T_3250) @[el2_lib.scala 301:184]
|
|
node _T_3254 = cat(_T_3253, _T_3249) @[el2_lib.scala 301:184]
|
|
node _T_3255 = cat(_T_3084[10], _T_3084[9]) @[el2_lib.scala 301:184]
|
|
node _T_3256 = cat(_T_3084[12], _T_3084[11]) @[el2_lib.scala 301:184]
|
|
node _T_3257 = cat(_T_3256, _T_3255) @[el2_lib.scala 301:184]
|
|
node _T_3258 = cat(_T_3084[14], _T_3084[13]) @[el2_lib.scala 301:184]
|
|
node _T_3259 = cat(_T_3084[17], _T_3084[16]) @[el2_lib.scala 301:184]
|
|
node _T_3260 = cat(_T_3259, _T_3084[15]) @[el2_lib.scala 301:184]
|
|
node _T_3261 = cat(_T_3260, _T_3258) @[el2_lib.scala 301:184]
|
|
node _T_3262 = cat(_T_3261, _T_3257) @[el2_lib.scala 301:184]
|
|
node _T_3263 = cat(_T_3262, _T_3254) @[el2_lib.scala 301:184]
|
|
node _T_3264 = xorr(_T_3263) @[el2_lib.scala 301:191]
|
|
node _T_3265 = xor(_T_3246, _T_3264) @[el2_lib.scala 301:179]
|
|
node _T_3266 = bits(_T_3082, 0, 0) @[el2_lib.scala 301:203]
|
|
node _T_3267 = cat(_T_3083[1], _T_3083[0]) @[el2_lib.scala 301:211]
|
|
node _T_3268 = cat(_T_3083[3], _T_3083[2]) @[el2_lib.scala 301:211]
|
|
node _T_3269 = cat(_T_3268, _T_3267) @[el2_lib.scala 301:211]
|
|
node _T_3270 = cat(_T_3083[5], _T_3083[4]) @[el2_lib.scala 301:211]
|
|
node _T_3271 = cat(_T_3083[8], _T_3083[7]) @[el2_lib.scala 301:211]
|
|
node _T_3272 = cat(_T_3271, _T_3083[6]) @[el2_lib.scala 301:211]
|
|
node _T_3273 = cat(_T_3272, _T_3270) @[el2_lib.scala 301:211]
|
|
node _T_3274 = cat(_T_3273, _T_3269) @[el2_lib.scala 301:211]
|
|
node _T_3275 = cat(_T_3083[10], _T_3083[9]) @[el2_lib.scala 301:211]
|
|
node _T_3276 = cat(_T_3083[12], _T_3083[11]) @[el2_lib.scala 301:211]
|
|
node _T_3277 = cat(_T_3276, _T_3275) @[el2_lib.scala 301:211]
|
|
node _T_3278 = cat(_T_3083[14], _T_3083[13]) @[el2_lib.scala 301:211]
|
|
node _T_3279 = cat(_T_3083[17], _T_3083[16]) @[el2_lib.scala 301:211]
|
|
node _T_3280 = cat(_T_3279, _T_3083[15]) @[el2_lib.scala 301:211]
|
|
node _T_3281 = cat(_T_3280, _T_3278) @[el2_lib.scala 301:211]
|
|
node _T_3282 = cat(_T_3281, _T_3277) @[el2_lib.scala 301:211]
|
|
node _T_3283 = cat(_T_3282, _T_3274) @[el2_lib.scala 301:211]
|
|
node _T_3284 = xorr(_T_3283) @[el2_lib.scala 301:218]
|
|
node _T_3285 = xor(_T_3266, _T_3284) @[el2_lib.scala 301:206]
|
|
node _T_3286 = cat(_T_3245, _T_3265) @[Cat.scala 29:58]
|
|
node _T_3287 = cat(_T_3286, _T_3285) @[Cat.scala 29:58]
|
|
node _T_3288 = cat(_T_3208, _T_3225) @[Cat.scala 29:58]
|
|
node _T_3289 = cat(_T_3183, _T_3191) @[Cat.scala 29:58]
|
|
node _T_3290 = cat(_T_3289, _T_3288) @[Cat.scala 29:58]
|
|
node _T_3291 = cat(_T_3290, _T_3287) @[Cat.scala 29:58]
|
|
node _T_3292 = neq(_T_3291, UInt<1>("h00")) @[el2_lib.scala 302:44]
|
|
node _T_3293 = and(_T_3080, _T_3292) @[el2_lib.scala 302:32]
|
|
node _T_3294 = bits(_T_3291, 6, 6) @[el2_lib.scala 302:64]
|
|
node _T_3295 = and(_T_3293, _T_3294) @[el2_lib.scala 302:53]
|
|
node _T_3296 = neq(_T_3291, UInt<1>("h00")) @[el2_lib.scala 303:44]
|
|
node _T_3297 = and(_T_3080, _T_3296) @[el2_lib.scala 303:32]
|
|
node _T_3298 = bits(_T_3291, 6, 6) @[el2_lib.scala 303:65]
|
|
node _T_3299 = not(_T_3298) @[el2_lib.scala 303:55]
|
|
node _T_3300 = and(_T_3297, _T_3299) @[el2_lib.scala 303:53]
|
|
wire _T_3301 : UInt<1>[39] @[el2_lib.scala 304:26]
|
|
node _T_3302 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3303 = eq(_T_3302, UInt<1>("h01")) @[el2_lib.scala 307:41]
|
|
_T_3301[0] <= _T_3303 @[el2_lib.scala 307:23]
|
|
node _T_3304 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3305 = eq(_T_3304, UInt<2>("h02")) @[el2_lib.scala 307:41]
|
|
_T_3301[1] <= _T_3305 @[el2_lib.scala 307:23]
|
|
node _T_3306 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3307 = eq(_T_3306, UInt<2>("h03")) @[el2_lib.scala 307:41]
|
|
_T_3301[2] <= _T_3307 @[el2_lib.scala 307:23]
|
|
node _T_3308 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3309 = eq(_T_3308, UInt<3>("h04")) @[el2_lib.scala 307:41]
|
|
_T_3301[3] <= _T_3309 @[el2_lib.scala 307:23]
|
|
node _T_3310 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3311 = eq(_T_3310, UInt<3>("h05")) @[el2_lib.scala 307:41]
|
|
_T_3301[4] <= _T_3311 @[el2_lib.scala 307:23]
|
|
node _T_3312 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3313 = eq(_T_3312, UInt<3>("h06")) @[el2_lib.scala 307:41]
|
|
_T_3301[5] <= _T_3313 @[el2_lib.scala 307:23]
|
|
node _T_3314 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3315 = eq(_T_3314, UInt<3>("h07")) @[el2_lib.scala 307:41]
|
|
_T_3301[6] <= _T_3315 @[el2_lib.scala 307:23]
|
|
node _T_3316 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3317 = eq(_T_3316, UInt<4>("h08")) @[el2_lib.scala 307:41]
|
|
_T_3301[7] <= _T_3317 @[el2_lib.scala 307:23]
|
|
node _T_3318 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3319 = eq(_T_3318, UInt<4>("h09")) @[el2_lib.scala 307:41]
|
|
_T_3301[8] <= _T_3319 @[el2_lib.scala 307:23]
|
|
node _T_3320 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3321 = eq(_T_3320, UInt<4>("h0a")) @[el2_lib.scala 307:41]
|
|
_T_3301[9] <= _T_3321 @[el2_lib.scala 307:23]
|
|
node _T_3322 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3323 = eq(_T_3322, UInt<4>("h0b")) @[el2_lib.scala 307:41]
|
|
_T_3301[10] <= _T_3323 @[el2_lib.scala 307:23]
|
|
node _T_3324 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3325 = eq(_T_3324, UInt<4>("h0c")) @[el2_lib.scala 307:41]
|
|
_T_3301[11] <= _T_3325 @[el2_lib.scala 307:23]
|
|
node _T_3326 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3327 = eq(_T_3326, UInt<4>("h0d")) @[el2_lib.scala 307:41]
|
|
_T_3301[12] <= _T_3327 @[el2_lib.scala 307:23]
|
|
node _T_3328 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3329 = eq(_T_3328, UInt<4>("h0e")) @[el2_lib.scala 307:41]
|
|
_T_3301[13] <= _T_3329 @[el2_lib.scala 307:23]
|
|
node _T_3330 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3331 = eq(_T_3330, UInt<4>("h0f")) @[el2_lib.scala 307:41]
|
|
_T_3301[14] <= _T_3331 @[el2_lib.scala 307:23]
|
|
node _T_3332 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3333 = eq(_T_3332, UInt<5>("h010")) @[el2_lib.scala 307:41]
|
|
_T_3301[15] <= _T_3333 @[el2_lib.scala 307:23]
|
|
node _T_3334 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3335 = eq(_T_3334, UInt<5>("h011")) @[el2_lib.scala 307:41]
|
|
_T_3301[16] <= _T_3335 @[el2_lib.scala 307:23]
|
|
node _T_3336 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3337 = eq(_T_3336, UInt<5>("h012")) @[el2_lib.scala 307:41]
|
|
_T_3301[17] <= _T_3337 @[el2_lib.scala 307:23]
|
|
node _T_3338 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3339 = eq(_T_3338, UInt<5>("h013")) @[el2_lib.scala 307:41]
|
|
_T_3301[18] <= _T_3339 @[el2_lib.scala 307:23]
|
|
node _T_3340 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3341 = eq(_T_3340, UInt<5>("h014")) @[el2_lib.scala 307:41]
|
|
_T_3301[19] <= _T_3341 @[el2_lib.scala 307:23]
|
|
node _T_3342 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3343 = eq(_T_3342, UInt<5>("h015")) @[el2_lib.scala 307:41]
|
|
_T_3301[20] <= _T_3343 @[el2_lib.scala 307:23]
|
|
node _T_3344 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3345 = eq(_T_3344, UInt<5>("h016")) @[el2_lib.scala 307:41]
|
|
_T_3301[21] <= _T_3345 @[el2_lib.scala 307:23]
|
|
node _T_3346 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3347 = eq(_T_3346, UInt<5>("h017")) @[el2_lib.scala 307:41]
|
|
_T_3301[22] <= _T_3347 @[el2_lib.scala 307:23]
|
|
node _T_3348 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3349 = eq(_T_3348, UInt<5>("h018")) @[el2_lib.scala 307:41]
|
|
_T_3301[23] <= _T_3349 @[el2_lib.scala 307:23]
|
|
node _T_3350 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3351 = eq(_T_3350, UInt<5>("h019")) @[el2_lib.scala 307:41]
|
|
_T_3301[24] <= _T_3351 @[el2_lib.scala 307:23]
|
|
node _T_3352 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3353 = eq(_T_3352, UInt<5>("h01a")) @[el2_lib.scala 307:41]
|
|
_T_3301[25] <= _T_3353 @[el2_lib.scala 307:23]
|
|
node _T_3354 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3355 = eq(_T_3354, UInt<5>("h01b")) @[el2_lib.scala 307:41]
|
|
_T_3301[26] <= _T_3355 @[el2_lib.scala 307:23]
|
|
node _T_3356 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3357 = eq(_T_3356, UInt<5>("h01c")) @[el2_lib.scala 307:41]
|
|
_T_3301[27] <= _T_3357 @[el2_lib.scala 307:23]
|
|
node _T_3358 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3359 = eq(_T_3358, UInt<5>("h01d")) @[el2_lib.scala 307:41]
|
|
_T_3301[28] <= _T_3359 @[el2_lib.scala 307:23]
|
|
node _T_3360 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3361 = eq(_T_3360, UInt<5>("h01e")) @[el2_lib.scala 307:41]
|
|
_T_3301[29] <= _T_3361 @[el2_lib.scala 307:23]
|
|
node _T_3362 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3363 = eq(_T_3362, UInt<5>("h01f")) @[el2_lib.scala 307:41]
|
|
_T_3301[30] <= _T_3363 @[el2_lib.scala 307:23]
|
|
node _T_3364 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3365 = eq(_T_3364, UInt<6>("h020")) @[el2_lib.scala 307:41]
|
|
_T_3301[31] <= _T_3365 @[el2_lib.scala 307:23]
|
|
node _T_3366 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3367 = eq(_T_3366, UInt<6>("h021")) @[el2_lib.scala 307:41]
|
|
_T_3301[32] <= _T_3367 @[el2_lib.scala 307:23]
|
|
node _T_3368 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3369 = eq(_T_3368, UInt<6>("h022")) @[el2_lib.scala 307:41]
|
|
_T_3301[33] <= _T_3369 @[el2_lib.scala 307:23]
|
|
node _T_3370 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3371 = eq(_T_3370, UInt<6>("h023")) @[el2_lib.scala 307:41]
|
|
_T_3301[34] <= _T_3371 @[el2_lib.scala 307:23]
|
|
node _T_3372 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3373 = eq(_T_3372, UInt<6>("h024")) @[el2_lib.scala 307:41]
|
|
_T_3301[35] <= _T_3373 @[el2_lib.scala 307:23]
|
|
node _T_3374 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3375 = eq(_T_3374, UInt<6>("h025")) @[el2_lib.scala 307:41]
|
|
_T_3301[36] <= _T_3375 @[el2_lib.scala 307:23]
|
|
node _T_3376 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3377 = eq(_T_3376, UInt<6>("h026")) @[el2_lib.scala 307:41]
|
|
_T_3301[37] <= _T_3377 @[el2_lib.scala 307:23]
|
|
node _T_3378 = bits(_T_3291, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3379 = eq(_T_3378, UInt<6>("h027")) @[el2_lib.scala 307:41]
|
|
_T_3301[38] <= _T_3379 @[el2_lib.scala 307:23]
|
|
node _T_3380 = bits(_T_3082, 6, 6) @[el2_lib.scala 309:37]
|
|
node _T_3381 = bits(_T_3081, 31, 26) @[el2_lib.scala 309:45]
|
|
node _T_3382 = bits(_T_3082, 5, 5) @[el2_lib.scala 309:60]
|
|
node _T_3383 = bits(_T_3081, 25, 11) @[el2_lib.scala 309:68]
|
|
node _T_3384 = bits(_T_3082, 4, 4) @[el2_lib.scala 309:83]
|
|
node _T_3385 = bits(_T_3081, 10, 4) @[el2_lib.scala 309:91]
|
|
node _T_3386 = bits(_T_3082, 3, 3) @[el2_lib.scala 309:105]
|
|
node _T_3387 = bits(_T_3081, 3, 1) @[el2_lib.scala 309:113]
|
|
node _T_3388 = bits(_T_3082, 2, 2) @[el2_lib.scala 309:126]
|
|
node _T_3389 = bits(_T_3081, 0, 0) @[el2_lib.scala 309:134]
|
|
node _T_3390 = bits(_T_3082, 1, 0) @[el2_lib.scala 309:145]
|
|
node _T_3391 = cat(_T_3389, _T_3390) @[Cat.scala 29:58]
|
|
node _T_3392 = cat(_T_3386, _T_3387) @[Cat.scala 29:58]
|
|
node _T_3393 = cat(_T_3392, _T_3388) @[Cat.scala 29:58]
|
|
node _T_3394 = cat(_T_3393, _T_3391) @[Cat.scala 29:58]
|
|
node _T_3395 = cat(_T_3383, _T_3384) @[Cat.scala 29:58]
|
|
node _T_3396 = cat(_T_3395, _T_3385) @[Cat.scala 29:58]
|
|
node _T_3397 = cat(_T_3380, _T_3381) @[Cat.scala 29:58]
|
|
node _T_3398 = cat(_T_3397, _T_3382) @[Cat.scala 29:58]
|
|
node _T_3399 = cat(_T_3398, _T_3396) @[Cat.scala 29:58]
|
|
node _T_3400 = cat(_T_3399, _T_3394) @[Cat.scala 29:58]
|
|
node _T_3401 = bits(_T_3295, 0, 0) @[el2_lib.scala 310:49]
|
|
node _T_3402 = cat(_T_3301[1], _T_3301[0]) @[el2_lib.scala 310:69]
|
|
node _T_3403 = cat(_T_3301[3], _T_3301[2]) @[el2_lib.scala 310:69]
|
|
node _T_3404 = cat(_T_3403, _T_3402) @[el2_lib.scala 310:69]
|
|
node _T_3405 = cat(_T_3301[5], _T_3301[4]) @[el2_lib.scala 310:69]
|
|
node _T_3406 = cat(_T_3301[8], _T_3301[7]) @[el2_lib.scala 310:69]
|
|
node _T_3407 = cat(_T_3406, _T_3301[6]) @[el2_lib.scala 310:69]
|
|
node _T_3408 = cat(_T_3407, _T_3405) @[el2_lib.scala 310:69]
|
|
node _T_3409 = cat(_T_3408, _T_3404) @[el2_lib.scala 310:69]
|
|
node _T_3410 = cat(_T_3301[10], _T_3301[9]) @[el2_lib.scala 310:69]
|
|
node _T_3411 = cat(_T_3301[13], _T_3301[12]) @[el2_lib.scala 310:69]
|
|
node _T_3412 = cat(_T_3411, _T_3301[11]) @[el2_lib.scala 310:69]
|
|
node _T_3413 = cat(_T_3412, _T_3410) @[el2_lib.scala 310:69]
|
|
node _T_3414 = cat(_T_3301[15], _T_3301[14]) @[el2_lib.scala 310:69]
|
|
node _T_3415 = cat(_T_3301[18], _T_3301[17]) @[el2_lib.scala 310:69]
|
|
node _T_3416 = cat(_T_3415, _T_3301[16]) @[el2_lib.scala 310:69]
|
|
node _T_3417 = cat(_T_3416, _T_3414) @[el2_lib.scala 310:69]
|
|
node _T_3418 = cat(_T_3417, _T_3413) @[el2_lib.scala 310:69]
|
|
node _T_3419 = cat(_T_3418, _T_3409) @[el2_lib.scala 310:69]
|
|
node _T_3420 = cat(_T_3301[20], _T_3301[19]) @[el2_lib.scala 310:69]
|
|
node _T_3421 = cat(_T_3301[23], _T_3301[22]) @[el2_lib.scala 310:69]
|
|
node _T_3422 = cat(_T_3421, _T_3301[21]) @[el2_lib.scala 310:69]
|
|
node _T_3423 = cat(_T_3422, _T_3420) @[el2_lib.scala 310:69]
|
|
node _T_3424 = cat(_T_3301[25], _T_3301[24]) @[el2_lib.scala 310:69]
|
|
node _T_3425 = cat(_T_3301[28], _T_3301[27]) @[el2_lib.scala 310:69]
|
|
node _T_3426 = cat(_T_3425, _T_3301[26]) @[el2_lib.scala 310:69]
|
|
node _T_3427 = cat(_T_3426, _T_3424) @[el2_lib.scala 310:69]
|
|
node _T_3428 = cat(_T_3427, _T_3423) @[el2_lib.scala 310:69]
|
|
node _T_3429 = cat(_T_3301[30], _T_3301[29]) @[el2_lib.scala 310:69]
|
|
node _T_3430 = cat(_T_3301[33], _T_3301[32]) @[el2_lib.scala 310:69]
|
|
node _T_3431 = cat(_T_3430, _T_3301[31]) @[el2_lib.scala 310:69]
|
|
node _T_3432 = cat(_T_3431, _T_3429) @[el2_lib.scala 310:69]
|
|
node _T_3433 = cat(_T_3301[35], _T_3301[34]) @[el2_lib.scala 310:69]
|
|
node _T_3434 = cat(_T_3301[38], _T_3301[37]) @[el2_lib.scala 310:69]
|
|
node _T_3435 = cat(_T_3434, _T_3301[36]) @[el2_lib.scala 310:69]
|
|
node _T_3436 = cat(_T_3435, _T_3433) @[el2_lib.scala 310:69]
|
|
node _T_3437 = cat(_T_3436, _T_3432) @[el2_lib.scala 310:69]
|
|
node _T_3438 = cat(_T_3437, _T_3428) @[el2_lib.scala 310:69]
|
|
node _T_3439 = cat(_T_3438, _T_3419) @[el2_lib.scala 310:69]
|
|
node _T_3440 = xor(_T_3439, _T_3400) @[el2_lib.scala 310:76]
|
|
node _T_3441 = mux(_T_3401, _T_3440, _T_3400) @[el2_lib.scala 310:31]
|
|
node _T_3442 = bits(_T_3441, 37, 32) @[el2_lib.scala 312:37]
|
|
node _T_3443 = bits(_T_3441, 30, 16) @[el2_lib.scala 312:61]
|
|
node _T_3444 = bits(_T_3441, 14, 8) @[el2_lib.scala 312:86]
|
|
node _T_3445 = bits(_T_3441, 6, 4) @[el2_lib.scala 312:110]
|
|
node _T_3446 = bits(_T_3441, 2, 2) @[el2_lib.scala 312:133]
|
|
node _T_3447 = cat(_T_3445, _T_3446) @[Cat.scala 29:58]
|
|
node _T_3448 = cat(_T_3442, _T_3443) @[Cat.scala 29:58]
|
|
node _T_3449 = cat(_T_3448, _T_3444) @[Cat.scala 29:58]
|
|
node _T_3450 = cat(_T_3449, _T_3447) @[Cat.scala 29:58]
|
|
node _T_3451 = bits(_T_3441, 38, 38) @[el2_lib.scala 313:39]
|
|
node _T_3452 = bits(_T_3291, 6, 0) @[el2_lib.scala 313:56]
|
|
node _T_3453 = eq(_T_3452, UInt<7>("h040")) @[el2_lib.scala 313:62]
|
|
node _T_3454 = xor(_T_3451, _T_3453) @[el2_lib.scala 313:44]
|
|
node _T_3455 = bits(_T_3441, 31, 31) @[el2_lib.scala 313:102]
|
|
node _T_3456 = bits(_T_3441, 15, 15) @[el2_lib.scala 313:124]
|
|
node _T_3457 = bits(_T_3441, 7, 7) @[el2_lib.scala 313:146]
|
|
node _T_3458 = bits(_T_3441, 3, 3) @[el2_lib.scala 313:167]
|
|
node _T_3459 = bits(_T_3441, 1, 0) @[el2_lib.scala 313:188]
|
|
node _T_3460 = cat(_T_3457, _T_3458) @[Cat.scala 29:58]
|
|
node _T_3461 = cat(_T_3460, _T_3459) @[Cat.scala 29:58]
|
|
node _T_3462 = cat(_T_3454, _T_3455) @[Cat.scala 29:58]
|
|
node _T_3463 = cat(_T_3462, _T_3456) @[Cat.scala 29:58]
|
|
node _T_3464 = cat(_T_3463, _T_3461) @[Cat.scala 29:58]
|
|
node _T_3465 = bits(iccm_ecc_word_enable, 1, 1) @[el2_ifu_mem_ctl.scala 661:73]
|
|
node _T_3466 = bits(io.iccm_rd_data_ecc, 70, 39) @[el2_ifu_mem_ctl.scala 661:93]
|
|
node _T_3467 = bits(io.iccm_rd_data_ecc, 77, 71) @[el2_ifu_mem_ctl.scala 661:128]
|
|
wire _T_3468 : UInt<1>[18] @[el2_lib.scala 281:18]
|
|
wire _T_3469 : UInt<1>[18] @[el2_lib.scala 282:18]
|
|
wire _T_3470 : UInt<1>[18] @[el2_lib.scala 283:18]
|
|
wire _T_3471 : UInt<1>[15] @[el2_lib.scala 284:18]
|
|
wire _T_3472 : UInt<1>[15] @[el2_lib.scala 285:18]
|
|
wire _T_3473 : UInt<1>[6] @[el2_lib.scala 286:18]
|
|
node _T_3474 = bits(_T_3466, 0, 0) @[el2_lib.scala 293:36]
|
|
_T_3468[0] <= _T_3474 @[el2_lib.scala 293:30]
|
|
node _T_3475 = bits(_T_3466, 0, 0) @[el2_lib.scala 294:36]
|
|
_T_3469[0] <= _T_3475 @[el2_lib.scala 294:30]
|
|
node _T_3476 = bits(_T_3466, 1, 1) @[el2_lib.scala 293:36]
|
|
_T_3468[1] <= _T_3476 @[el2_lib.scala 293:30]
|
|
node _T_3477 = bits(_T_3466, 1, 1) @[el2_lib.scala 295:36]
|
|
_T_3470[0] <= _T_3477 @[el2_lib.scala 295:30]
|
|
node _T_3478 = bits(_T_3466, 2, 2) @[el2_lib.scala 294:36]
|
|
_T_3469[1] <= _T_3478 @[el2_lib.scala 294:30]
|
|
node _T_3479 = bits(_T_3466, 2, 2) @[el2_lib.scala 295:36]
|
|
_T_3470[1] <= _T_3479 @[el2_lib.scala 295:30]
|
|
node _T_3480 = bits(_T_3466, 3, 3) @[el2_lib.scala 293:36]
|
|
_T_3468[2] <= _T_3480 @[el2_lib.scala 293:30]
|
|
node _T_3481 = bits(_T_3466, 3, 3) @[el2_lib.scala 294:36]
|
|
_T_3469[2] <= _T_3481 @[el2_lib.scala 294:30]
|
|
node _T_3482 = bits(_T_3466, 3, 3) @[el2_lib.scala 295:36]
|
|
_T_3470[2] <= _T_3482 @[el2_lib.scala 295:30]
|
|
node _T_3483 = bits(_T_3466, 4, 4) @[el2_lib.scala 293:36]
|
|
_T_3468[3] <= _T_3483 @[el2_lib.scala 293:30]
|
|
node _T_3484 = bits(_T_3466, 4, 4) @[el2_lib.scala 296:36]
|
|
_T_3471[0] <= _T_3484 @[el2_lib.scala 296:30]
|
|
node _T_3485 = bits(_T_3466, 5, 5) @[el2_lib.scala 294:36]
|
|
_T_3469[3] <= _T_3485 @[el2_lib.scala 294:30]
|
|
node _T_3486 = bits(_T_3466, 5, 5) @[el2_lib.scala 296:36]
|
|
_T_3471[1] <= _T_3486 @[el2_lib.scala 296:30]
|
|
node _T_3487 = bits(_T_3466, 6, 6) @[el2_lib.scala 293:36]
|
|
_T_3468[4] <= _T_3487 @[el2_lib.scala 293:30]
|
|
node _T_3488 = bits(_T_3466, 6, 6) @[el2_lib.scala 294:36]
|
|
_T_3469[4] <= _T_3488 @[el2_lib.scala 294:30]
|
|
node _T_3489 = bits(_T_3466, 6, 6) @[el2_lib.scala 296:36]
|
|
_T_3471[2] <= _T_3489 @[el2_lib.scala 296:30]
|
|
node _T_3490 = bits(_T_3466, 7, 7) @[el2_lib.scala 295:36]
|
|
_T_3470[3] <= _T_3490 @[el2_lib.scala 295:30]
|
|
node _T_3491 = bits(_T_3466, 7, 7) @[el2_lib.scala 296:36]
|
|
_T_3471[3] <= _T_3491 @[el2_lib.scala 296:30]
|
|
node _T_3492 = bits(_T_3466, 8, 8) @[el2_lib.scala 293:36]
|
|
_T_3468[5] <= _T_3492 @[el2_lib.scala 293:30]
|
|
node _T_3493 = bits(_T_3466, 8, 8) @[el2_lib.scala 295:36]
|
|
_T_3470[4] <= _T_3493 @[el2_lib.scala 295:30]
|
|
node _T_3494 = bits(_T_3466, 8, 8) @[el2_lib.scala 296:36]
|
|
_T_3471[4] <= _T_3494 @[el2_lib.scala 296:30]
|
|
node _T_3495 = bits(_T_3466, 9, 9) @[el2_lib.scala 294:36]
|
|
_T_3469[5] <= _T_3495 @[el2_lib.scala 294:30]
|
|
node _T_3496 = bits(_T_3466, 9, 9) @[el2_lib.scala 295:36]
|
|
_T_3470[5] <= _T_3496 @[el2_lib.scala 295:30]
|
|
node _T_3497 = bits(_T_3466, 9, 9) @[el2_lib.scala 296:36]
|
|
_T_3471[5] <= _T_3497 @[el2_lib.scala 296:30]
|
|
node _T_3498 = bits(_T_3466, 10, 10) @[el2_lib.scala 293:36]
|
|
_T_3468[6] <= _T_3498 @[el2_lib.scala 293:30]
|
|
node _T_3499 = bits(_T_3466, 10, 10) @[el2_lib.scala 294:36]
|
|
_T_3469[6] <= _T_3499 @[el2_lib.scala 294:30]
|
|
node _T_3500 = bits(_T_3466, 10, 10) @[el2_lib.scala 295:36]
|
|
_T_3470[6] <= _T_3500 @[el2_lib.scala 295:30]
|
|
node _T_3501 = bits(_T_3466, 10, 10) @[el2_lib.scala 296:36]
|
|
_T_3471[6] <= _T_3501 @[el2_lib.scala 296:30]
|
|
node _T_3502 = bits(_T_3466, 11, 11) @[el2_lib.scala 293:36]
|
|
_T_3468[7] <= _T_3502 @[el2_lib.scala 293:30]
|
|
node _T_3503 = bits(_T_3466, 11, 11) @[el2_lib.scala 297:36]
|
|
_T_3472[0] <= _T_3503 @[el2_lib.scala 297:30]
|
|
node _T_3504 = bits(_T_3466, 12, 12) @[el2_lib.scala 294:36]
|
|
_T_3469[7] <= _T_3504 @[el2_lib.scala 294:30]
|
|
node _T_3505 = bits(_T_3466, 12, 12) @[el2_lib.scala 297:36]
|
|
_T_3472[1] <= _T_3505 @[el2_lib.scala 297:30]
|
|
node _T_3506 = bits(_T_3466, 13, 13) @[el2_lib.scala 293:36]
|
|
_T_3468[8] <= _T_3506 @[el2_lib.scala 293:30]
|
|
node _T_3507 = bits(_T_3466, 13, 13) @[el2_lib.scala 294:36]
|
|
_T_3469[8] <= _T_3507 @[el2_lib.scala 294:30]
|
|
node _T_3508 = bits(_T_3466, 13, 13) @[el2_lib.scala 297:36]
|
|
_T_3472[2] <= _T_3508 @[el2_lib.scala 297:30]
|
|
node _T_3509 = bits(_T_3466, 14, 14) @[el2_lib.scala 295:36]
|
|
_T_3470[7] <= _T_3509 @[el2_lib.scala 295:30]
|
|
node _T_3510 = bits(_T_3466, 14, 14) @[el2_lib.scala 297:36]
|
|
_T_3472[3] <= _T_3510 @[el2_lib.scala 297:30]
|
|
node _T_3511 = bits(_T_3466, 15, 15) @[el2_lib.scala 293:36]
|
|
_T_3468[9] <= _T_3511 @[el2_lib.scala 293:30]
|
|
node _T_3512 = bits(_T_3466, 15, 15) @[el2_lib.scala 295:36]
|
|
_T_3470[8] <= _T_3512 @[el2_lib.scala 295:30]
|
|
node _T_3513 = bits(_T_3466, 15, 15) @[el2_lib.scala 297:36]
|
|
_T_3472[4] <= _T_3513 @[el2_lib.scala 297:30]
|
|
node _T_3514 = bits(_T_3466, 16, 16) @[el2_lib.scala 294:36]
|
|
_T_3469[9] <= _T_3514 @[el2_lib.scala 294:30]
|
|
node _T_3515 = bits(_T_3466, 16, 16) @[el2_lib.scala 295:36]
|
|
_T_3470[9] <= _T_3515 @[el2_lib.scala 295:30]
|
|
node _T_3516 = bits(_T_3466, 16, 16) @[el2_lib.scala 297:36]
|
|
_T_3472[5] <= _T_3516 @[el2_lib.scala 297:30]
|
|
node _T_3517 = bits(_T_3466, 17, 17) @[el2_lib.scala 293:36]
|
|
_T_3468[10] <= _T_3517 @[el2_lib.scala 293:30]
|
|
node _T_3518 = bits(_T_3466, 17, 17) @[el2_lib.scala 294:36]
|
|
_T_3469[10] <= _T_3518 @[el2_lib.scala 294:30]
|
|
node _T_3519 = bits(_T_3466, 17, 17) @[el2_lib.scala 295:36]
|
|
_T_3470[10] <= _T_3519 @[el2_lib.scala 295:30]
|
|
node _T_3520 = bits(_T_3466, 17, 17) @[el2_lib.scala 297:36]
|
|
_T_3472[6] <= _T_3520 @[el2_lib.scala 297:30]
|
|
node _T_3521 = bits(_T_3466, 18, 18) @[el2_lib.scala 296:36]
|
|
_T_3471[7] <= _T_3521 @[el2_lib.scala 296:30]
|
|
node _T_3522 = bits(_T_3466, 18, 18) @[el2_lib.scala 297:36]
|
|
_T_3472[7] <= _T_3522 @[el2_lib.scala 297:30]
|
|
node _T_3523 = bits(_T_3466, 19, 19) @[el2_lib.scala 293:36]
|
|
_T_3468[11] <= _T_3523 @[el2_lib.scala 293:30]
|
|
node _T_3524 = bits(_T_3466, 19, 19) @[el2_lib.scala 296:36]
|
|
_T_3471[8] <= _T_3524 @[el2_lib.scala 296:30]
|
|
node _T_3525 = bits(_T_3466, 19, 19) @[el2_lib.scala 297:36]
|
|
_T_3472[8] <= _T_3525 @[el2_lib.scala 297:30]
|
|
node _T_3526 = bits(_T_3466, 20, 20) @[el2_lib.scala 294:36]
|
|
_T_3469[11] <= _T_3526 @[el2_lib.scala 294:30]
|
|
node _T_3527 = bits(_T_3466, 20, 20) @[el2_lib.scala 296:36]
|
|
_T_3471[9] <= _T_3527 @[el2_lib.scala 296:30]
|
|
node _T_3528 = bits(_T_3466, 20, 20) @[el2_lib.scala 297:36]
|
|
_T_3472[9] <= _T_3528 @[el2_lib.scala 297:30]
|
|
node _T_3529 = bits(_T_3466, 21, 21) @[el2_lib.scala 293:36]
|
|
_T_3468[12] <= _T_3529 @[el2_lib.scala 293:30]
|
|
node _T_3530 = bits(_T_3466, 21, 21) @[el2_lib.scala 294:36]
|
|
_T_3469[12] <= _T_3530 @[el2_lib.scala 294:30]
|
|
node _T_3531 = bits(_T_3466, 21, 21) @[el2_lib.scala 296:36]
|
|
_T_3471[10] <= _T_3531 @[el2_lib.scala 296:30]
|
|
node _T_3532 = bits(_T_3466, 21, 21) @[el2_lib.scala 297:36]
|
|
_T_3472[10] <= _T_3532 @[el2_lib.scala 297:30]
|
|
node _T_3533 = bits(_T_3466, 22, 22) @[el2_lib.scala 295:36]
|
|
_T_3470[11] <= _T_3533 @[el2_lib.scala 295:30]
|
|
node _T_3534 = bits(_T_3466, 22, 22) @[el2_lib.scala 296:36]
|
|
_T_3471[11] <= _T_3534 @[el2_lib.scala 296:30]
|
|
node _T_3535 = bits(_T_3466, 22, 22) @[el2_lib.scala 297:36]
|
|
_T_3472[11] <= _T_3535 @[el2_lib.scala 297:30]
|
|
node _T_3536 = bits(_T_3466, 23, 23) @[el2_lib.scala 293:36]
|
|
_T_3468[13] <= _T_3536 @[el2_lib.scala 293:30]
|
|
node _T_3537 = bits(_T_3466, 23, 23) @[el2_lib.scala 295:36]
|
|
_T_3470[12] <= _T_3537 @[el2_lib.scala 295:30]
|
|
node _T_3538 = bits(_T_3466, 23, 23) @[el2_lib.scala 296:36]
|
|
_T_3471[12] <= _T_3538 @[el2_lib.scala 296:30]
|
|
node _T_3539 = bits(_T_3466, 23, 23) @[el2_lib.scala 297:36]
|
|
_T_3472[12] <= _T_3539 @[el2_lib.scala 297:30]
|
|
node _T_3540 = bits(_T_3466, 24, 24) @[el2_lib.scala 294:36]
|
|
_T_3469[13] <= _T_3540 @[el2_lib.scala 294:30]
|
|
node _T_3541 = bits(_T_3466, 24, 24) @[el2_lib.scala 295:36]
|
|
_T_3470[13] <= _T_3541 @[el2_lib.scala 295:30]
|
|
node _T_3542 = bits(_T_3466, 24, 24) @[el2_lib.scala 296:36]
|
|
_T_3471[13] <= _T_3542 @[el2_lib.scala 296:30]
|
|
node _T_3543 = bits(_T_3466, 24, 24) @[el2_lib.scala 297:36]
|
|
_T_3472[13] <= _T_3543 @[el2_lib.scala 297:30]
|
|
node _T_3544 = bits(_T_3466, 25, 25) @[el2_lib.scala 293:36]
|
|
_T_3468[14] <= _T_3544 @[el2_lib.scala 293:30]
|
|
node _T_3545 = bits(_T_3466, 25, 25) @[el2_lib.scala 294:36]
|
|
_T_3469[14] <= _T_3545 @[el2_lib.scala 294:30]
|
|
node _T_3546 = bits(_T_3466, 25, 25) @[el2_lib.scala 295:36]
|
|
_T_3470[14] <= _T_3546 @[el2_lib.scala 295:30]
|
|
node _T_3547 = bits(_T_3466, 25, 25) @[el2_lib.scala 296:36]
|
|
_T_3471[14] <= _T_3547 @[el2_lib.scala 296:30]
|
|
node _T_3548 = bits(_T_3466, 25, 25) @[el2_lib.scala 297:36]
|
|
_T_3472[14] <= _T_3548 @[el2_lib.scala 297:30]
|
|
node _T_3549 = bits(_T_3466, 26, 26) @[el2_lib.scala 293:36]
|
|
_T_3468[15] <= _T_3549 @[el2_lib.scala 293:30]
|
|
node _T_3550 = bits(_T_3466, 26, 26) @[el2_lib.scala 298:36]
|
|
_T_3473[0] <= _T_3550 @[el2_lib.scala 298:30]
|
|
node _T_3551 = bits(_T_3466, 27, 27) @[el2_lib.scala 294:36]
|
|
_T_3469[15] <= _T_3551 @[el2_lib.scala 294:30]
|
|
node _T_3552 = bits(_T_3466, 27, 27) @[el2_lib.scala 298:36]
|
|
_T_3473[1] <= _T_3552 @[el2_lib.scala 298:30]
|
|
node _T_3553 = bits(_T_3466, 28, 28) @[el2_lib.scala 293:36]
|
|
_T_3468[16] <= _T_3553 @[el2_lib.scala 293:30]
|
|
node _T_3554 = bits(_T_3466, 28, 28) @[el2_lib.scala 294:36]
|
|
_T_3469[16] <= _T_3554 @[el2_lib.scala 294:30]
|
|
node _T_3555 = bits(_T_3466, 28, 28) @[el2_lib.scala 298:36]
|
|
_T_3473[2] <= _T_3555 @[el2_lib.scala 298:30]
|
|
node _T_3556 = bits(_T_3466, 29, 29) @[el2_lib.scala 295:36]
|
|
_T_3470[15] <= _T_3556 @[el2_lib.scala 295:30]
|
|
node _T_3557 = bits(_T_3466, 29, 29) @[el2_lib.scala 298:36]
|
|
_T_3473[3] <= _T_3557 @[el2_lib.scala 298:30]
|
|
node _T_3558 = bits(_T_3466, 30, 30) @[el2_lib.scala 293:36]
|
|
_T_3468[17] <= _T_3558 @[el2_lib.scala 293:30]
|
|
node _T_3559 = bits(_T_3466, 30, 30) @[el2_lib.scala 295:36]
|
|
_T_3470[16] <= _T_3559 @[el2_lib.scala 295:30]
|
|
node _T_3560 = bits(_T_3466, 30, 30) @[el2_lib.scala 298:36]
|
|
_T_3473[4] <= _T_3560 @[el2_lib.scala 298:30]
|
|
node _T_3561 = bits(_T_3466, 31, 31) @[el2_lib.scala 294:36]
|
|
_T_3469[17] <= _T_3561 @[el2_lib.scala 294:30]
|
|
node _T_3562 = bits(_T_3466, 31, 31) @[el2_lib.scala 295:36]
|
|
_T_3470[17] <= _T_3562 @[el2_lib.scala 295:30]
|
|
node _T_3563 = bits(_T_3466, 31, 31) @[el2_lib.scala 298:36]
|
|
_T_3473[5] <= _T_3563 @[el2_lib.scala 298:30]
|
|
node _T_3564 = xorr(_T_3466) @[el2_lib.scala 301:30]
|
|
node _T_3565 = xorr(_T_3467) @[el2_lib.scala 301:44]
|
|
node _T_3566 = xor(_T_3564, _T_3565) @[el2_lib.scala 301:35]
|
|
node _T_3567 = not(UInt<1>("h00")) @[el2_lib.scala 301:52]
|
|
node _T_3568 = and(_T_3566, _T_3567) @[el2_lib.scala 301:50]
|
|
node _T_3569 = bits(_T_3467, 5, 5) @[el2_lib.scala 301:68]
|
|
node _T_3570 = cat(_T_3473[2], _T_3473[1]) @[el2_lib.scala 301:76]
|
|
node _T_3571 = cat(_T_3570, _T_3473[0]) @[el2_lib.scala 301:76]
|
|
node _T_3572 = cat(_T_3473[5], _T_3473[4]) @[el2_lib.scala 301:76]
|
|
node _T_3573 = cat(_T_3572, _T_3473[3]) @[el2_lib.scala 301:76]
|
|
node _T_3574 = cat(_T_3573, _T_3571) @[el2_lib.scala 301:76]
|
|
node _T_3575 = xorr(_T_3574) @[el2_lib.scala 301:83]
|
|
node _T_3576 = xor(_T_3569, _T_3575) @[el2_lib.scala 301:71]
|
|
node _T_3577 = bits(_T_3467, 4, 4) @[el2_lib.scala 301:95]
|
|
node _T_3578 = cat(_T_3472[2], _T_3472[1]) @[el2_lib.scala 301:103]
|
|
node _T_3579 = cat(_T_3578, _T_3472[0]) @[el2_lib.scala 301:103]
|
|
node _T_3580 = cat(_T_3472[4], _T_3472[3]) @[el2_lib.scala 301:103]
|
|
node _T_3581 = cat(_T_3472[6], _T_3472[5]) @[el2_lib.scala 301:103]
|
|
node _T_3582 = cat(_T_3581, _T_3580) @[el2_lib.scala 301:103]
|
|
node _T_3583 = cat(_T_3582, _T_3579) @[el2_lib.scala 301:103]
|
|
node _T_3584 = cat(_T_3472[8], _T_3472[7]) @[el2_lib.scala 301:103]
|
|
node _T_3585 = cat(_T_3472[10], _T_3472[9]) @[el2_lib.scala 301:103]
|
|
node _T_3586 = cat(_T_3585, _T_3584) @[el2_lib.scala 301:103]
|
|
node _T_3587 = cat(_T_3472[12], _T_3472[11]) @[el2_lib.scala 301:103]
|
|
node _T_3588 = cat(_T_3472[14], _T_3472[13]) @[el2_lib.scala 301:103]
|
|
node _T_3589 = cat(_T_3588, _T_3587) @[el2_lib.scala 301:103]
|
|
node _T_3590 = cat(_T_3589, _T_3586) @[el2_lib.scala 301:103]
|
|
node _T_3591 = cat(_T_3590, _T_3583) @[el2_lib.scala 301:103]
|
|
node _T_3592 = xorr(_T_3591) @[el2_lib.scala 301:110]
|
|
node _T_3593 = xor(_T_3577, _T_3592) @[el2_lib.scala 301:98]
|
|
node _T_3594 = bits(_T_3467, 3, 3) @[el2_lib.scala 301:122]
|
|
node _T_3595 = cat(_T_3471[2], _T_3471[1]) @[el2_lib.scala 301:130]
|
|
node _T_3596 = cat(_T_3595, _T_3471[0]) @[el2_lib.scala 301:130]
|
|
node _T_3597 = cat(_T_3471[4], _T_3471[3]) @[el2_lib.scala 301:130]
|
|
node _T_3598 = cat(_T_3471[6], _T_3471[5]) @[el2_lib.scala 301:130]
|
|
node _T_3599 = cat(_T_3598, _T_3597) @[el2_lib.scala 301:130]
|
|
node _T_3600 = cat(_T_3599, _T_3596) @[el2_lib.scala 301:130]
|
|
node _T_3601 = cat(_T_3471[8], _T_3471[7]) @[el2_lib.scala 301:130]
|
|
node _T_3602 = cat(_T_3471[10], _T_3471[9]) @[el2_lib.scala 301:130]
|
|
node _T_3603 = cat(_T_3602, _T_3601) @[el2_lib.scala 301:130]
|
|
node _T_3604 = cat(_T_3471[12], _T_3471[11]) @[el2_lib.scala 301:130]
|
|
node _T_3605 = cat(_T_3471[14], _T_3471[13]) @[el2_lib.scala 301:130]
|
|
node _T_3606 = cat(_T_3605, _T_3604) @[el2_lib.scala 301:130]
|
|
node _T_3607 = cat(_T_3606, _T_3603) @[el2_lib.scala 301:130]
|
|
node _T_3608 = cat(_T_3607, _T_3600) @[el2_lib.scala 301:130]
|
|
node _T_3609 = xorr(_T_3608) @[el2_lib.scala 301:137]
|
|
node _T_3610 = xor(_T_3594, _T_3609) @[el2_lib.scala 301:125]
|
|
node _T_3611 = bits(_T_3467, 2, 2) @[el2_lib.scala 301:149]
|
|
node _T_3612 = cat(_T_3470[1], _T_3470[0]) @[el2_lib.scala 301:157]
|
|
node _T_3613 = cat(_T_3470[3], _T_3470[2]) @[el2_lib.scala 301:157]
|
|
node _T_3614 = cat(_T_3613, _T_3612) @[el2_lib.scala 301:157]
|
|
node _T_3615 = cat(_T_3470[5], _T_3470[4]) @[el2_lib.scala 301:157]
|
|
node _T_3616 = cat(_T_3470[8], _T_3470[7]) @[el2_lib.scala 301:157]
|
|
node _T_3617 = cat(_T_3616, _T_3470[6]) @[el2_lib.scala 301:157]
|
|
node _T_3618 = cat(_T_3617, _T_3615) @[el2_lib.scala 301:157]
|
|
node _T_3619 = cat(_T_3618, _T_3614) @[el2_lib.scala 301:157]
|
|
node _T_3620 = cat(_T_3470[10], _T_3470[9]) @[el2_lib.scala 301:157]
|
|
node _T_3621 = cat(_T_3470[12], _T_3470[11]) @[el2_lib.scala 301:157]
|
|
node _T_3622 = cat(_T_3621, _T_3620) @[el2_lib.scala 301:157]
|
|
node _T_3623 = cat(_T_3470[14], _T_3470[13]) @[el2_lib.scala 301:157]
|
|
node _T_3624 = cat(_T_3470[17], _T_3470[16]) @[el2_lib.scala 301:157]
|
|
node _T_3625 = cat(_T_3624, _T_3470[15]) @[el2_lib.scala 301:157]
|
|
node _T_3626 = cat(_T_3625, _T_3623) @[el2_lib.scala 301:157]
|
|
node _T_3627 = cat(_T_3626, _T_3622) @[el2_lib.scala 301:157]
|
|
node _T_3628 = cat(_T_3627, _T_3619) @[el2_lib.scala 301:157]
|
|
node _T_3629 = xorr(_T_3628) @[el2_lib.scala 301:164]
|
|
node _T_3630 = xor(_T_3611, _T_3629) @[el2_lib.scala 301:152]
|
|
node _T_3631 = bits(_T_3467, 1, 1) @[el2_lib.scala 301:176]
|
|
node _T_3632 = cat(_T_3469[1], _T_3469[0]) @[el2_lib.scala 301:184]
|
|
node _T_3633 = cat(_T_3469[3], _T_3469[2]) @[el2_lib.scala 301:184]
|
|
node _T_3634 = cat(_T_3633, _T_3632) @[el2_lib.scala 301:184]
|
|
node _T_3635 = cat(_T_3469[5], _T_3469[4]) @[el2_lib.scala 301:184]
|
|
node _T_3636 = cat(_T_3469[8], _T_3469[7]) @[el2_lib.scala 301:184]
|
|
node _T_3637 = cat(_T_3636, _T_3469[6]) @[el2_lib.scala 301:184]
|
|
node _T_3638 = cat(_T_3637, _T_3635) @[el2_lib.scala 301:184]
|
|
node _T_3639 = cat(_T_3638, _T_3634) @[el2_lib.scala 301:184]
|
|
node _T_3640 = cat(_T_3469[10], _T_3469[9]) @[el2_lib.scala 301:184]
|
|
node _T_3641 = cat(_T_3469[12], _T_3469[11]) @[el2_lib.scala 301:184]
|
|
node _T_3642 = cat(_T_3641, _T_3640) @[el2_lib.scala 301:184]
|
|
node _T_3643 = cat(_T_3469[14], _T_3469[13]) @[el2_lib.scala 301:184]
|
|
node _T_3644 = cat(_T_3469[17], _T_3469[16]) @[el2_lib.scala 301:184]
|
|
node _T_3645 = cat(_T_3644, _T_3469[15]) @[el2_lib.scala 301:184]
|
|
node _T_3646 = cat(_T_3645, _T_3643) @[el2_lib.scala 301:184]
|
|
node _T_3647 = cat(_T_3646, _T_3642) @[el2_lib.scala 301:184]
|
|
node _T_3648 = cat(_T_3647, _T_3639) @[el2_lib.scala 301:184]
|
|
node _T_3649 = xorr(_T_3648) @[el2_lib.scala 301:191]
|
|
node _T_3650 = xor(_T_3631, _T_3649) @[el2_lib.scala 301:179]
|
|
node _T_3651 = bits(_T_3467, 0, 0) @[el2_lib.scala 301:203]
|
|
node _T_3652 = cat(_T_3468[1], _T_3468[0]) @[el2_lib.scala 301:211]
|
|
node _T_3653 = cat(_T_3468[3], _T_3468[2]) @[el2_lib.scala 301:211]
|
|
node _T_3654 = cat(_T_3653, _T_3652) @[el2_lib.scala 301:211]
|
|
node _T_3655 = cat(_T_3468[5], _T_3468[4]) @[el2_lib.scala 301:211]
|
|
node _T_3656 = cat(_T_3468[8], _T_3468[7]) @[el2_lib.scala 301:211]
|
|
node _T_3657 = cat(_T_3656, _T_3468[6]) @[el2_lib.scala 301:211]
|
|
node _T_3658 = cat(_T_3657, _T_3655) @[el2_lib.scala 301:211]
|
|
node _T_3659 = cat(_T_3658, _T_3654) @[el2_lib.scala 301:211]
|
|
node _T_3660 = cat(_T_3468[10], _T_3468[9]) @[el2_lib.scala 301:211]
|
|
node _T_3661 = cat(_T_3468[12], _T_3468[11]) @[el2_lib.scala 301:211]
|
|
node _T_3662 = cat(_T_3661, _T_3660) @[el2_lib.scala 301:211]
|
|
node _T_3663 = cat(_T_3468[14], _T_3468[13]) @[el2_lib.scala 301:211]
|
|
node _T_3664 = cat(_T_3468[17], _T_3468[16]) @[el2_lib.scala 301:211]
|
|
node _T_3665 = cat(_T_3664, _T_3468[15]) @[el2_lib.scala 301:211]
|
|
node _T_3666 = cat(_T_3665, _T_3663) @[el2_lib.scala 301:211]
|
|
node _T_3667 = cat(_T_3666, _T_3662) @[el2_lib.scala 301:211]
|
|
node _T_3668 = cat(_T_3667, _T_3659) @[el2_lib.scala 301:211]
|
|
node _T_3669 = xorr(_T_3668) @[el2_lib.scala 301:218]
|
|
node _T_3670 = xor(_T_3651, _T_3669) @[el2_lib.scala 301:206]
|
|
node _T_3671 = cat(_T_3630, _T_3650) @[Cat.scala 29:58]
|
|
node _T_3672 = cat(_T_3671, _T_3670) @[Cat.scala 29:58]
|
|
node _T_3673 = cat(_T_3593, _T_3610) @[Cat.scala 29:58]
|
|
node _T_3674 = cat(_T_3568, _T_3576) @[Cat.scala 29:58]
|
|
node _T_3675 = cat(_T_3674, _T_3673) @[Cat.scala 29:58]
|
|
node _T_3676 = cat(_T_3675, _T_3672) @[Cat.scala 29:58]
|
|
node _T_3677 = neq(_T_3676, UInt<1>("h00")) @[el2_lib.scala 302:44]
|
|
node _T_3678 = and(_T_3465, _T_3677) @[el2_lib.scala 302:32]
|
|
node _T_3679 = bits(_T_3676, 6, 6) @[el2_lib.scala 302:64]
|
|
node _T_3680 = and(_T_3678, _T_3679) @[el2_lib.scala 302:53]
|
|
node _T_3681 = neq(_T_3676, UInt<1>("h00")) @[el2_lib.scala 303:44]
|
|
node _T_3682 = and(_T_3465, _T_3681) @[el2_lib.scala 303:32]
|
|
node _T_3683 = bits(_T_3676, 6, 6) @[el2_lib.scala 303:65]
|
|
node _T_3684 = not(_T_3683) @[el2_lib.scala 303:55]
|
|
node _T_3685 = and(_T_3682, _T_3684) @[el2_lib.scala 303:53]
|
|
wire _T_3686 : UInt<1>[39] @[el2_lib.scala 304:26]
|
|
node _T_3687 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3688 = eq(_T_3687, UInt<1>("h01")) @[el2_lib.scala 307:41]
|
|
_T_3686[0] <= _T_3688 @[el2_lib.scala 307:23]
|
|
node _T_3689 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3690 = eq(_T_3689, UInt<2>("h02")) @[el2_lib.scala 307:41]
|
|
_T_3686[1] <= _T_3690 @[el2_lib.scala 307:23]
|
|
node _T_3691 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3692 = eq(_T_3691, UInt<2>("h03")) @[el2_lib.scala 307:41]
|
|
_T_3686[2] <= _T_3692 @[el2_lib.scala 307:23]
|
|
node _T_3693 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3694 = eq(_T_3693, UInt<3>("h04")) @[el2_lib.scala 307:41]
|
|
_T_3686[3] <= _T_3694 @[el2_lib.scala 307:23]
|
|
node _T_3695 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3696 = eq(_T_3695, UInt<3>("h05")) @[el2_lib.scala 307:41]
|
|
_T_3686[4] <= _T_3696 @[el2_lib.scala 307:23]
|
|
node _T_3697 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3698 = eq(_T_3697, UInt<3>("h06")) @[el2_lib.scala 307:41]
|
|
_T_3686[5] <= _T_3698 @[el2_lib.scala 307:23]
|
|
node _T_3699 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3700 = eq(_T_3699, UInt<3>("h07")) @[el2_lib.scala 307:41]
|
|
_T_3686[6] <= _T_3700 @[el2_lib.scala 307:23]
|
|
node _T_3701 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3702 = eq(_T_3701, UInt<4>("h08")) @[el2_lib.scala 307:41]
|
|
_T_3686[7] <= _T_3702 @[el2_lib.scala 307:23]
|
|
node _T_3703 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3704 = eq(_T_3703, UInt<4>("h09")) @[el2_lib.scala 307:41]
|
|
_T_3686[8] <= _T_3704 @[el2_lib.scala 307:23]
|
|
node _T_3705 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3706 = eq(_T_3705, UInt<4>("h0a")) @[el2_lib.scala 307:41]
|
|
_T_3686[9] <= _T_3706 @[el2_lib.scala 307:23]
|
|
node _T_3707 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3708 = eq(_T_3707, UInt<4>("h0b")) @[el2_lib.scala 307:41]
|
|
_T_3686[10] <= _T_3708 @[el2_lib.scala 307:23]
|
|
node _T_3709 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3710 = eq(_T_3709, UInt<4>("h0c")) @[el2_lib.scala 307:41]
|
|
_T_3686[11] <= _T_3710 @[el2_lib.scala 307:23]
|
|
node _T_3711 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3712 = eq(_T_3711, UInt<4>("h0d")) @[el2_lib.scala 307:41]
|
|
_T_3686[12] <= _T_3712 @[el2_lib.scala 307:23]
|
|
node _T_3713 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3714 = eq(_T_3713, UInt<4>("h0e")) @[el2_lib.scala 307:41]
|
|
_T_3686[13] <= _T_3714 @[el2_lib.scala 307:23]
|
|
node _T_3715 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3716 = eq(_T_3715, UInt<4>("h0f")) @[el2_lib.scala 307:41]
|
|
_T_3686[14] <= _T_3716 @[el2_lib.scala 307:23]
|
|
node _T_3717 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3718 = eq(_T_3717, UInt<5>("h010")) @[el2_lib.scala 307:41]
|
|
_T_3686[15] <= _T_3718 @[el2_lib.scala 307:23]
|
|
node _T_3719 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3720 = eq(_T_3719, UInt<5>("h011")) @[el2_lib.scala 307:41]
|
|
_T_3686[16] <= _T_3720 @[el2_lib.scala 307:23]
|
|
node _T_3721 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3722 = eq(_T_3721, UInt<5>("h012")) @[el2_lib.scala 307:41]
|
|
_T_3686[17] <= _T_3722 @[el2_lib.scala 307:23]
|
|
node _T_3723 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3724 = eq(_T_3723, UInt<5>("h013")) @[el2_lib.scala 307:41]
|
|
_T_3686[18] <= _T_3724 @[el2_lib.scala 307:23]
|
|
node _T_3725 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3726 = eq(_T_3725, UInt<5>("h014")) @[el2_lib.scala 307:41]
|
|
_T_3686[19] <= _T_3726 @[el2_lib.scala 307:23]
|
|
node _T_3727 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3728 = eq(_T_3727, UInt<5>("h015")) @[el2_lib.scala 307:41]
|
|
_T_3686[20] <= _T_3728 @[el2_lib.scala 307:23]
|
|
node _T_3729 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3730 = eq(_T_3729, UInt<5>("h016")) @[el2_lib.scala 307:41]
|
|
_T_3686[21] <= _T_3730 @[el2_lib.scala 307:23]
|
|
node _T_3731 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3732 = eq(_T_3731, UInt<5>("h017")) @[el2_lib.scala 307:41]
|
|
_T_3686[22] <= _T_3732 @[el2_lib.scala 307:23]
|
|
node _T_3733 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3734 = eq(_T_3733, UInt<5>("h018")) @[el2_lib.scala 307:41]
|
|
_T_3686[23] <= _T_3734 @[el2_lib.scala 307:23]
|
|
node _T_3735 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3736 = eq(_T_3735, UInt<5>("h019")) @[el2_lib.scala 307:41]
|
|
_T_3686[24] <= _T_3736 @[el2_lib.scala 307:23]
|
|
node _T_3737 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3738 = eq(_T_3737, UInt<5>("h01a")) @[el2_lib.scala 307:41]
|
|
_T_3686[25] <= _T_3738 @[el2_lib.scala 307:23]
|
|
node _T_3739 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3740 = eq(_T_3739, UInt<5>("h01b")) @[el2_lib.scala 307:41]
|
|
_T_3686[26] <= _T_3740 @[el2_lib.scala 307:23]
|
|
node _T_3741 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3742 = eq(_T_3741, UInt<5>("h01c")) @[el2_lib.scala 307:41]
|
|
_T_3686[27] <= _T_3742 @[el2_lib.scala 307:23]
|
|
node _T_3743 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3744 = eq(_T_3743, UInt<5>("h01d")) @[el2_lib.scala 307:41]
|
|
_T_3686[28] <= _T_3744 @[el2_lib.scala 307:23]
|
|
node _T_3745 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3746 = eq(_T_3745, UInt<5>("h01e")) @[el2_lib.scala 307:41]
|
|
_T_3686[29] <= _T_3746 @[el2_lib.scala 307:23]
|
|
node _T_3747 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3748 = eq(_T_3747, UInt<5>("h01f")) @[el2_lib.scala 307:41]
|
|
_T_3686[30] <= _T_3748 @[el2_lib.scala 307:23]
|
|
node _T_3749 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3750 = eq(_T_3749, UInt<6>("h020")) @[el2_lib.scala 307:41]
|
|
_T_3686[31] <= _T_3750 @[el2_lib.scala 307:23]
|
|
node _T_3751 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3752 = eq(_T_3751, UInt<6>("h021")) @[el2_lib.scala 307:41]
|
|
_T_3686[32] <= _T_3752 @[el2_lib.scala 307:23]
|
|
node _T_3753 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3754 = eq(_T_3753, UInt<6>("h022")) @[el2_lib.scala 307:41]
|
|
_T_3686[33] <= _T_3754 @[el2_lib.scala 307:23]
|
|
node _T_3755 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3756 = eq(_T_3755, UInt<6>("h023")) @[el2_lib.scala 307:41]
|
|
_T_3686[34] <= _T_3756 @[el2_lib.scala 307:23]
|
|
node _T_3757 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3758 = eq(_T_3757, UInt<6>("h024")) @[el2_lib.scala 307:41]
|
|
_T_3686[35] <= _T_3758 @[el2_lib.scala 307:23]
|
|
node _T_3759 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3760 = eq(_T_3759, UInt<6>("h025")) @[el2_lib.scala 307:41]
|
|
_T_3686[36] <= _T_3760 @[el2_lib.scala 307:23]
|
|
node _T_3761 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3762 = eq(_T_3761, UInt<6>("h026")) @[el2_lib.scala 307:41]
|
|
_T_3686[37] <= _T_3762 @[el2_lib.scala 307:23]
|
|
node _T_3763 = bits(_T_3676, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3764 = eq(_T_3763, UInt<6>("h027")) @[el2_lib.scala 307:41]
|
|
_T_3686[38] <= _T_3764 @[el2_lib.scala 307:23]
|
|
node _T_3765 = bits(_T_3467, 6, 6) @[el2_lib.scala 309:37]
|
|
node _T_3766 = bits(_T_3466, 31, 26) @[el2_lib.scala 309:45]
|
|
node _T_3767 = bits(_T_3467, 5, 5) @[el2_lib.scala 309:60]
|
|
node _T_3768 = bits(_T_3466, 25, 11) @[el2_lib.scala 309:68]
|
|
node _T_3769 = bits(_T_3467, 4, 4) @[el2_lib.scala 309:83]
|
|
node _T_3770 = bits(_T_3466, 10, 4) @[el2_lib.scala 309:91]
|
|
node _T_3771 = bits(_T_3467, 3, 3) @[el2_lib.scala 309:105]
|
|
node _T_3772 = bits(_T_3466, 3, 1) @[el2_lib.scala 309:113]
|
|
node _T_3773 = bits(_T_3467, 2, 2) @[el2_lib.scala 309:126]
|
|
node _T_3774 = bits(_T_3466, 0, 0) @[el2_lib.scala 309:134]
|
|
node _T_3775 = bits(_T_3467, 1, 0) @[el2_lib.scala 309:145]
|
|
node _T_3776 = cat(_T_3774, _T_3775) @[Cat.scala 29:58]
|
|
node _T_3777 = cat(_T_3771, _T_3772) @[Cat.scala 29:58]
|
|
node _T_3778 = cat(_T_3777, _T_3773) @[Cat.scala 29:58]
|
|
node _T_3779 = cat(_T_3778, _T_3776) @[Cat.scala 29:58]
|
|
node _T_3780 = cat(_T_3768, _T_3769) @[Cat.scala 29:58]
|
|
node _T_3781 = cat(_T_3780, _T_3770) @[Cat.scala 29:58]
|
|
node _T_3782 = cat(_T_3765, _T_3766) @[Cat.scala 29:58]
|
|
node _T_3783 = cat(_T_3782, _T_3767) @[Cat.scala 29:58]
|
|
node _T_3784 = cat(_T_3783, _T_3781) @[Cat.scala 29:58]
|
|
node _T_3785 = cat(_T_3784, _T_3779) @[Cat.scala 29:58]
|
|
node _T_3786 = bits(_T_3680, 0, 0) @[el2_lib.scala 310:49]
|
|
node _T_3787 = cat(_T_3686[1], _T_3686[0]) @[el2_lib.scala 310:69]
|
|
node _T_3788 = cat(_T_3686[3], _T_3686[2]) @[el2_lib.scala 310:69]
|
|
node _T_3789 = cat(_T_3788, _T_3787) @[el2_lib.scala 310:69]
|
|
node _T_3790 = cat(_T_3686[5], _T_3686[4]) @[el2_lib.scala 310:69]
|
|
node _T_3791 = cat(_T_3686[8], _T_3686[7]) @[el2_lib.scala 310:69]
|
|
node _T_3792 = cat(_T_3791, _T_3686[6]) @[el2_lib.scala 310:69]
|
|
node _T_3793 = cat(_T_3792, _T_3790) @[el2_lib.scala 310:69]
|
|
node _T_3794 = cat(_T_3793, _T_3789) @[el2_lib.scala 310:69]
|
|
node _T_3795 = cat(_T_3686[10], _T_3686[9]) @[el2_lib.scala 310:69]
|
|
node _T_3796 = cat(_T_3686[13], _T_3686[12]) @[el2_lib.scala 310:69]
|
|
node _T_3797 = cat(_T_3796, _T_3686[11]) @[el2_lib.scala 310:69]
|
|
node _T_3798 = cat(_T_3797, _T_3795) @[el2_lib.scala 310:69]
|
|
node _T_3799 = cat(_T_3686[15], _T_3686[14]) @[el2_lib.scala 310:69]
|
|
node _T_3800 = cat(_T_3686[18], _T_3686[17]) @[el2_lib.scala 310:69]
|
|
node _T_3801 = cat(_T_3800, _T_3686[16]) @[el2_lib.scala 310:69]
|
|
node _T_3802 = cat(_T_3801, _T_3799) @[el2_lib.scala 310:69]
|
|
node _T_3803 = cat(_T_3802, _T_3798) @[el2_lib.scala 310:69]
|
|
node _T_3804 = cat(_T_3803, _T_3794) @[el2_lib.scala 310:69]
|
|
node _T_3805 = cat(_T_3686[20], _T_3686[19]) @[el2_lib.scala 310:69]
|
|
node _T_3806 = cat(_T_3686[23], _T_3686[22]) @[el2_lib.scala 310:69]
|
|
node _T_3807 = cat(_T_3806, _T_3686[21]) @[el2_lib.scala 310:69]
|
|
node _T_3808 = cat(_T_3807, _T_3805) @[el2_lib.scala 310:69]
|
|
node _T_3809 = cat(_T_3686[25], _T_3686[24]) @[el2_lib.scala 310:69]
|
|
node _T_3810 = cat(_T_3686[28], _T_3686[27]) @[el2_lib.scala 310:69]
|
|
node _T_3811 = cat(_T_3810, _T_3686[26]) @[el2_lib.scala 310:69]
|
|
node _T_3812 = cat(_T_3811, _T_3809) @[el2_lib.scala 310:69]
|
|
node _T_3813 = cat(_T_3812, _T_3808) @[el2_lib.scala 310:69]
|
|
node _T_3814 = cat(_T_3686[30], _T_3686[29]) @[el2_lib.scala 310:69]
|
|
node _T_3815 = cat(_T_3686[33], _T_3686[32]) @[el2_lib.scala 310:69]
|
|
node _T_3816 = cat(_T_3815, _T_3686[31]) @[el2_lib.scala 310:69]
|
|
node _T_3817 = cat(_T_3816, _T_3814) @[el2_lib.scala 310:69]
|
|
node _T_3818 = cat(_T_3686[35], _T_3686[34]) @[el2_lib.scala 310:69]
|
|
node _T_3819 = cat(_T_3686[38], _T_3686[37]) @[el2_lib.scala 310:69]
|
|
node _T_3820 = cat(_T_3819, _T_3686[36]) @[el2_lib.scala 310:69]
|
|
node _T_3821 = cat(_T_3820, _T_3818) @[el2_lib.scala 310:69]
|
|
node _T_3822 = cat(_T_3821, _T_3817) @[el2_lib.scala 310:69]
|
|
node _T_3823 = cat(_T_3822, _T_3813) @[el2_lib.scala 310:69]
|
|
node _T_3824 = cat(_T_3823, _T_3804) @[el2_lib.scala 310:69]
|
|
node _T_3825 = xor(_T_3824, _T_3785) @[el2_lib.scala 310:76]
|
|
node _T_3826 = mux(_T_3786, _T_3825, _T_3785) @[el2_lib.scala 310:31]
|
|
node _T_3827 = bits(_T_3826, 37, 32) @[el2_lib.scala 312:37]
|
|
node _T_3828 = bits(_T_3826, 30, 16) @[el2_lib.scala 312:61]
|
|
node _T_3829 = bits(_T_3826, 14, 8) @[el2_lib.scala 312:86]
|
|
node _T_3830 = bits(_T_3826, 6, 4) @[el2_lib.scala 312:110]
|
|
node _T_3831 = bits(_T_3826, 2, 2) @[el2_lib.scala 312:133]
|
|
node _T_3832 = cat(_T_3830, _T_3831) @[Cat.scala 29:58]
|
|
node _T_3833 = cat(_T_3827, _T_3828) @[Cat.scala 29:58]
|
|
node _T_3834 = cat(_T_3833, _T_3829) @[Cat.scala 29:58]
|
|
node _T_3835 = cat(_T_3834, _T_3832) @[Cat.scala 29:58]
|
|
node _T_3836 = bits(_T_3826, 38, 38) @[el2_lib.scala 313:39]
|
|
node _T_3837 = bits(_T_3676, 6, 0) @[el2_lib.scala 313:56]
|
|
node _T_3838 = eq(_T_3837, UInt<7>("h040")) @[el2_lib.scala 313:62]
|
|
node _T_3839 = xor(_T_3836, _T_3838) @[el2_lib.scala 313:44]
|
|
node _T_3840 = bits(_T_3826, 31, 31) @[el2_lib.scala 313:102]
|
|
node _T_3841 = bits(_T_3826, 15, 15) @[el2_lib.scala 313:124]
|
|
node _T_3842 = bits(_T_3826, 7, 7) @[el2_lib.scala 313:146]
|
|
node _T_3843 = bits(_T_3826, 3, 3) @[el2_lib.scala 313:167]
|
|
node _T_3844 = bits(_T_3826, 1, 0) @[el2_lib.scala 313:188]
|
|
node _T_3845 = cat(_T_3842, _T_3843) @[Cat.scala 29:58]
|
|
node _T_3846 = cat(_T_3845, _T_3844) @[Cat.scala 29:58]
|
|
node _T_3847 = cat(_T_3839, _T_3840) @[Cat.scala 29:58]
|
|
node _T_3848 = cat(_T_3847, _T_3841) @[Cat.scala 29:58]
|
|
node _T_3849 = cat(_T_3848, _T_3846) @[Cat.scala 29:58]
|
|
wire iccm_corrected_ecc : UInt<7>[2] @[el2_ifu_mem_ctl.scala 662:32]
|
|
wire _T_3850 : UInt<7>[2] @[el2_ifu_mem_ctl.scala 663:32]
|
|
_T_3850[0] <= _T_3464 @[el2_ifu_mem_ctl.scala 663:32]
|
|
_T_3850[1] <= _T_3849 @[el2_ifu_mem_ctl.scala 663:32]
|
|
iccm_corrected_ecc[0] <= _T_3850[0] @[el2_ifu_mem_ctl.scala 663:22]
|
|
iccm_corrected_ecc[1] <= _T_3850[1] @[el2_ifu_mem_ctl.scala 663:22]
|
|
wire _T_3851 : UInt<32>[2] @[el2_ifu_mem_ctl.scala 664:33]
|
|
_T_3851[0] <= _T_3450 @[el2_ifu_mem_ctl.scala 664:33]
|
|
_T_3851[1] <= _T_3835 @[el2_ifu_mem_ctl.scala 664:33]
|
|
iccm_corrected_data[0] <= _T_3851[0] @[el2_ifu_mem_ctl.scala 664:23]
|
|
iccm_corrected_data[1] <= _T_3851[1] @[el2_ifu_mem_ctl.scala 664:23]
|
|
node _T_3852 = cat(_T_3295, _T_3680) @[Cat.scala 29:58]
|
|
iccm_single_ecc_error <= _T_3852 @[el2_ifu_mem_ctl.scala 665:25]
|
|
node _T_3853 = cat(_T_3300, _T_3685) @[Cat.scala 29:58]
|
|
iccm_double_ecc_error <= _T_3853 @[el2_ifu_mem_ctl.scala 666:25]
|
|
node _T_3854 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 667:54]
|
|
node _T_3855 = and(_T_3854, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 667:58]
|
|
node _T_3856 = and(_T_3855, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 667:78]
|
|
io.iccm_rd_ecc_single_err <= _T_3856 @[el2_ifu_mem_ctl.scala 667:29]
|
|
node _T_3857 = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 668:54]
|
|
node _T_3858 = and(_T_3857, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 668:58]
|
|
io.iccm_rd_ecc_double_err <= _T_3858 @[el2_ifu_mem_ctl.scala 668:29]
|
|
node _T_3859 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 669:60]
|
|
node _T_3860 = bits(_T_3859, 0, 0) @[el2_ifu_mem_ctl.scala 669:64]
|
|
node iccm_corrected_data_f_mux = mux(_T_3860, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 669:38]
|
|
node _T_3861 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 670:59]
|
|
node _T_3862 = bits(_T_3861, 0, 0) @[el2_ifu_mem_ctl.scala 670:63]
|
|
node iccm_corrected_ecc_f_mux = mux(_T_3862, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[el2_ifu_mem_ctl.scala 670:37]
|
|
wire iccm_rd_ecc_single_err_ff : UInt<1>
|
|
iccm_rd_ecc_single_err_ff <= UInt<1>("h00")
|
|
node _T_3863 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 672:76]
|
|
node _T_3864 = and(io.iccm_rd_ecc_single_err, _T_3863) @[el2_ifu_mem_ctl.scala 672:74]
|
|
node _T_3865 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 672:106]
|
|
node _T_3866 = and(_T_3864, _T_3865) @[el2_ifu_mem_ctl.scala 672:104]
|
|
node iccm_ecc_write_status = or(_T_3866, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 672:127]
|
|
node _T_3867 = or(io.iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[el2_ifu_mem_ctl.scala 673:67]
|
|
node _T_3868 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 673:98]
|
|
node iccm_rd_ecc_single_err_hold_in = and(_T_3867, _T_3868) @[el2_ifu_mem_ctl.scala 673:96]
|
|
iccm_error_start <= io.iccm_rd_ecc_single_err @[el2_ifu_mem_ctl.scala 674:20]
|
|
wire iccm_rw_addr_f : UInt<14>
|
|
iccm_rw_addr_f <= UInt<1>("h00")
|
|
node _T_3869 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 676:57]
|
|
node _T_3870 = bits(_T_3869, 0, 0) @[el2_ifu_mem_ctl.scala 676:67]
|
|
node _T_3871 = add(iccm_rw_addr_f, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 676:102]
|
|
node _T_3872 = tail(_T_3871, 1) @[el2_ifu_mem_ctl.scala 676:102]
|
|
node iccm_ecc_corr_index_in = mux(_T_3870, iccm_rw_addr_f, _T_3872) @[el2_ifu_mem_ctl.scala 676:35]
|
|
node _T_3873 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_mem_ctl.scala 677:67]
|
|
reg _T_3874 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 677:51]
|
|
_T_3874 <= _T_3873 @[el2_ifu_mem_ctl.scala 677:51]
|
|
iccm_rw_addr_f <= _T_3874 @[el2_ifu_mem_ctl.scala 677:18]
|
|
reg _T_3875 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 678:62]
|
|
_T_3875 <= iccm_rd_ecc_single_err_hold_in @[el2_ifu_mem_ctl.scala 678:62]
|
|
iccm_rd_ecc_single_err_ff <= _T_3875 @[el2_ifu_mem_ctl.scala 678:29]
|
|
node _T_3876 = cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux) @[Cat.scala 29:58]
|
|
node _T_3877 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 679:152]
|
|
reg _T_3878 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3877 : @[Reg.scala 28:19]
|
|
_T_3878 <= _T_3876 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
iccm_ecc_corr_data_ff <= _T_3878 @[el2_ifu_mem_ctl.scala 679:25]
|
|
node _T_3879 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 680:119]
|
|
reg _T_3880 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3879 : @[Reg.scala 28:19]
|
|
_T_3880 <= iccm_ecc_corr_index_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
iccm_ecc_corr_index_ff <= _T_3880 @[el2_ifu_mem_ctl.scala 680:26]
|
|
node _T_3881 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 681:41]
|
|
node _T_3882 = and(io.ifc_fetch_req_bf, _T_3881) @[el2_ifu_mem_ctl.scala 681:39]
|
|
node _T_3883 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 681:72]
|
|
node _T_3884 = and(_T_3882, _T_3883) @[el2_ifu_mem_ctl.scala 681:70]
|
|
node _T_3885 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 682:19]
|
|
node _T_3886 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 682:34]
|
|
node _T_3887 = and(_T_3885, _T_3886) @[el2_ifu_mem_ctl.scala 682:32]
|
|
node _T_3888 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 683:19]
|
|
node _T_3889 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 683:39]
|
|
node _T_3890 = and(_T_3888, _T_3889) @[el2_ifu_mem_ctl.scala 683:37]
|
|
node _T_3891 = or(_T_3887, _T_3890) @[el2_ifu_mem_ctl.scala 682:88]
|
|
node _T_3892 = eq(miss_state, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 684:19]
|
|
node _T_3893 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 684:43]
|
|
node _T_3894 = and(_T_3892, _T_3893) @[el2_ifu_mem_ctl.scala 684:41]
|
|
node _T_3895 = or(_T_3891, _T_3894) @[el2_ifu_mem_ctl.scala 683:88]
|
|
node _T_3896 = eq(miss_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 685:19]
|
|
node _T_3897 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 685:37]
|
|
node _T_3898 = and(_T_3896, _T_3897) @[el2_ifu_mem_ctl.scala 685:35]
|
|
node _T_3899 = or(_T_3895, _T_3898) @[el2_ifu_mem_ctl.scala 684:88]
|
|
node _T_3900 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 686:19]
|
|
node _T_3901 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 686:40]
|
|
node _T_3902 = and(_T_3900, _T_3901) @[el2_ifu_mem_ctl.scala 686:38]
|
|
node _T_3903 = or(_T_3899, _T_3902) @[el2_ifu_mem_ctl.scala 685:88]
|
|
node _T_3904 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 687:19]
|
|
node _T_3905 = and(_T_3904, miss_state_en) @[el2_ifu_mem_ctl.scala 687:37]
|
|
node _T_3906 = eq(miss_nxtstate, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 687:71]
|
|
node _T_3907 = and(_T_3905, _T_3906) @[el2_ifu_mem_ctl.scala 687:54]
|
|
node _T_3908 = or(_T_3903, _T_3907) @[el2_ifu_mem_ctl.scala 686:57]
|
|
node _T_3909 = eq(_T_3908, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 682:5]
|
|
node _T_3910 = and(_T_3884, _T_3909) @[el2_ifu_mem_ctl.scala 681:96]
|
|
node _T_3911 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 688:28]
|
|
node _T_3912 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 688:52]
|
|
node _T_3913 = and(_T_3911, _T_3912) @[el2_ifu_mem_ctl.scala 688:50]
|
|
node _T_3914 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 688:83]
|
|
node _T_3915 = and(_T_3913, _T_3914) @[el2_ifu_mem_ctl.scala 688:81]
|
|
node _T_3916 = or(_T_3910, _T_3915) @[el2_ifu_mem_ctl.scala 687:93]
|
|
io.ic_rd_en <= _T_3916 @[el2_ifu_mem_ctl.scala 681:15]
|
|
wire bus_ic_wr_en : UInt<1>
|
|
bus_ic_wr_en <= UInt<1>("h00")
|
|
node _T_3917 = bits(write_ic_16_bytes, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_3918 = mux(_T_3917, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_3919 = and(bus_ic_wr_en, _T_3918) @[el2_ifu_mem_ctl.scala 690:31]
|
|
io.ic_wr_en <= _T_3919 @[el2_ifu_mem_ctl.scala 690:15]
|
|
node _T_3920 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 691:59]
|
|
node _T_3921 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 691:91]
|
|
node _T_3922 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 691:127]
|
|
node _T_3923 = or(_T_3922, stream_eol_f) @[el2_ifu_mem_ctl.scala 691:151]
|
|
node _T_3924 = eq(_T_3923, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:106]
|
|
node _T_3925 = and(_T_3921, _T_3924) @[el2_ifu_mem_ctl.scala 691:104]
|
|
node _T_3926 = or(_T_3920, _T_3925) @[el2_ifu_mem_ctl.scala 691:77]
|
|
node _T_3927 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 691:191]
|
|
node _T_3928 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:205]
|
|
node _T_3929 = and(_T_3927, _T_3928) @[el2_ifu_mem_ctl.scala 691:203]
|
|
node _T_3930 = eq(_T_3929, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:172]
|
|
node _T_3931 = and(_T_3926, _T_3930) @[el2_ifu_mem_ctl.scala 691:170]
|
|
node _T_3932 = eq(_T_3931, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:44]
|
|
node _T_3933 = and(write_ic_16_bytes, _T_3932) @[el2_ifu_mem_ctl.scala 691:42]
|
|
io.ic_write_stall <= _T_3933 @[el2_ifu_mem_ctl.scala 691:21]
|
|
reg _T_3934 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 692:53]
|
|
_T_3934 <= io.dec_tlu_fence_i_wb @[el2_ifu_mem_ctl.scala 692:53]
|
|
reset_all_tags <= _T_3934 @[el2_ifu_mem_ctl.scala 692:18]
|
|
node _T_3935 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 694:20]
|
|
node _T_3936 = or(reset_ic_in, reset_ic_ff) @[el2_ifu_mem_ctl.scala 694:64]
|
|
node _T_3937 = eq(_T_3936, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 694:50]
|
|
node _T_3938 = and(_T_3935, _T_3937) @[el2_ifu_mem_ctl.scala 694:48]
|
|
node _T_3939 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 694:81]
|
|
node ic_valid = and(_T_3938, _T_3939) @[el2_ifu_mem_ctl.scala 694:79]
|
|
node _T_3940 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 695:61]
|
|
node _T_3941 = and(_T_3940, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 695:82]
|
|
node _T_3942 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 695:123]
|
|
node _T_3943 = bits(ifu_status_wr_addr, 11, 5) @[el2_ifu_mem_ctl.scala 696:25]
|
|
node ifu_status_wr_addr_w_debug = mux(_T_3941, _T_3942, _T_3943) @[el2_ifu_mem_ctl.scala 695:41]
|
|
reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 698:14]
|
|
ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[el2_ifu_mem_ctl.scala 698:14]
|
|
wire way_status_wr_en : UInt<1>
|
|
way_status_wr_en <= UInt<1>("h00")
|
|
node _T_3944 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 701:74]
|
|
node way_status_wr_en_w_debug = or(way_status_wr_en, _T_3944) @[el2_ifu_mem_ctl.scala 701:53]
|
|
reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 703:14]
|
|
way_status_wr_en_ff <= way_status_wr_en_w_debug @[el2_ifu_mem_ctl.scala 703:14]
|
|
wire way_status_new : UInt<1>
|
|
way_status_new <= UInt<1>("h00")
|
|
node _T_3945 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 706:56]
|
|
node _T_3946 = bits(io.ic_debug_wr_data, 4, 4) @[el2_ifu_mem_ctl.scala 707:59]
|
|
node _T_3947 = bits(io.ic_debug_wr_data, 6, 4) @[el2_ifu_mem_ctl.scala 707:83]
|
|
node _T_3948 = mux(UInt<1>("h01"), _T_3946, _T_3947) @[el2_ifu_mem_ctl.scala 707:10]
|
|
node way_status_new_w_debug = mux(_T_3945, _T_3948, way_status_new) @[el2_ifu_mem_ctl.scala 706:37]
|
|
reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 709:14]
|
|
way_status_new_ff <= way_status_new_w_debug @[el2_ifu_mem_ctl.scala 709:14]
|
|
node _T_3949 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_0 = eq(_T_3949, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3950 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_1 = eq(_T_3950, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3951 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_2 = eq(_T_3951, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3952 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_3 = eq(_T_3952, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3953 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_4 = eq(_T_3953, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3954 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_5 = eq(_T_3954, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3955 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_6 = eq(_T_3955, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3956 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_7 = eq(_T_3956, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3957 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_8 = eq(_T_3957, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3958 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_9 = eq(_T_3958, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3959 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_10 = eq(_T_3959, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3960 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_11 = eq(_T_3960, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3961 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_12 = eq(_T_3961, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3962 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_13 = eq(_T_3962, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3963 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_14 = eq(_T_3963, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
node _T_3964 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89]
|
|
node way_status_clken_15 = eq(_T_3964, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 711:132]
|
|
wire way_status_out : UInt<1>[128] @[el2_ifu_mem_ctl.scala 713:30]
|
|
node _T_3965 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_3966 = and(_T_3965, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_3967 = and(_T_3966, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_3968 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3967 : @[Reg.scala 28:19]
|
|
_T_3968 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[0] <= _T_3968 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_3969 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_3970 = and(_T_3969, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_3971 = and(_T_3970, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_3972 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3971 : @[Reg.scala 28:19]
|
|
_T_3972 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[1] <= _T_3972 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_3973 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_3974 = and(_T_3973, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_3975 = and(_T_3974, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_3976 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3975 : @[Reg.scala 28:19]
|
|
_T_3976 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[2] <= _T_3976 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_3977 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_3978 = and(_T_3977, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_3979 = and(_T_3978, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_3980 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3979 : @[Reg.scala 28:19]
|
|
_T_3980 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[3] <= _T_3980 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_3981 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_3982 = and(_T_3981, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_3983 = and(_T_3982, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_3984 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3983 : @[Reg.scala 28:19]
|
|
_T_3984 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[4] <= _T_3984 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_3985 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_3986 = and(_T_3985, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_3987 = and(_T_3986, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_3988 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3987 : @[Reg.scala 28:19]
|
|
_T_3988 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[5] <= _T_3988 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_3989 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_3990 = and(_T_3989, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_3991 = and(_T_3990, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_3992 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3991 : @[Reg.scala 28:19]
|
|
_T_3992 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[6] <= _T_3992 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_3993 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_3994 = and(_T_3993, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_3995 = and(_T_3994, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_3996 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3995 : @[Reg.scala 28:19]
|
|
_T_3996 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[7] <= _T_3996 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_3997 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_3998 = and(_T_3997, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_3999 = and(_T_3998, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4000 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3999 : @[Reg.scala 28:19]
|
|
_T_4000 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[8] <= _T_4000 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4001 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4002 = and(_T_4001, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4003 = and(_T_4002, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4004 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4003 : @[Reg.scala 28:19]
|
|
_T_4004 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[9] <= _T_4004 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4005 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4006 = and(_T_4005, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4007 = and(_T_4006, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4008 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4007 : @[Reg.scala 28:19]
|
|
_T_4008 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[10] <= _T_4008 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4009 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4010 = and(_T_4009, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4011 = and(_T_4010, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4012 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4011 : @[Reg.scala 28:19]
|
|
_T_4012 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[11] <= _T_4012 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4013 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4014 = and(_T_4013, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4015 = and(_T_4014, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4016 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4015 : @[Reg.scala 28:19]
|
|
_T_4016 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[12] <= _T_4016 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4017 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4018 = and(_T_4017, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4019 = and(_T_4018, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4020 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4019 : @[Reg.scala 28:19]
|
|
_T_4020 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[13] <= _T_4020 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4021 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4022 = and(_T_4021, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4023 = and(_T_4022, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4024 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4023 : @[Reg.scala 28:19]
|
|
_T_4024 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[14] <= _T_4024 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4025 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4026 = and(_T_4025, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4027 = and(_T_4026, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4028 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4027 : @[Reg.scala 28:19]
|
|
_T_4028 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[15] <= _T_4028 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4029 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4030 = and(_T_4029, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4031 = and(_T_4030, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4032 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4031 : @[Reg.scala 28:19]
|
|
_T_4032 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[16] <= _T_4032 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4033 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4034 = and(_T_4033, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4035 = and(_T_4034, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4036 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4035 : @[Reg.scala 28:19]
|
|
_T_4036 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[17] <= _T_4036 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4037 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4038 = and(_T_4037, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4039 = and(_T_4038, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4040 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4039 : @[Reg.scala 28:19]
|
|
_T_4040 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[18] <= _T_4040 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4041 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4042 = and(_T_4041, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4043 = and(_T_4042, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4044 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4043 : @[Reg.scala 28:19]
|
|
_T_4044 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[19] <= _T_4044 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4045 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4046 = and(_T_4045, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4047 = and(_T_4046, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4048 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4047 : @[Reg.scala 28:19]
|
|
_T_4048 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[20] <= _T_4048 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4049 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4050 = and(_T_4049, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4051 = and(_T_4050, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4052 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4051 : @[Reg.scala 28:19]
|
|
_T_4052 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[21] <= _T_4052 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4053 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4054 = and(_T_4053, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4055 = and(_T_4054, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4056 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4055 : @[Reg.scala 28:19]
|
|
_T_4056 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[22] <= _T_4056 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4057 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4058 = and(_T_4057, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4059 = and(_T_4058, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4060 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4059 : @[Reg.scala 28:19]
|
|
_T_4060 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[23] <= _T_4060 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4061 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4062 = and(_T_4061, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4063 = and(_T_4062, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4064 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4063 : @[Reg.scala 28:19]
|
|
_T_4064 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[24] <= _T_4064 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4065 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4066 = and(_T_4065, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4067 = and(_T_4066, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4068 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4067 : @[Reg.scala 28:19]
|
|
_T_4068 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[25] <= _T_4068 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4069 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4070 = and(_T_4069, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4071 = and(_T_4070, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4072 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4071 : @[Reg.scala 28:19]
|
|
_T_4072 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[26] <= _T_4072 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4073 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4074 = and(_T_4073, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4075 = and(_T_4074, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4076 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4075 : @[Reg.scala 28:19]
|
|
_T_4076 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[27] <= _T_4076 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4077 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4078 = and(_T_4077, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4079 = and(_T_4078, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4080 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4079 : @[Reg.scala 28:19]
|
|
_T_4080 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[28] <= _T_4080 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4081 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4082 = and(_T_4081, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4083 = and(_T_4082, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4084 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4083 : @[Reg.scala 28:19]
|
|
_T_4084 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[29] <= _T_4084 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4085 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4086 = and(_T_4085, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4087 = and(_T_4086, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4088 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4087 : @[Reg.scala 28:19]
|
|
_T_4088 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[30] <= _T_4088 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4089 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4090 = and(_T_4089, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4091 = and(_T_4090, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4092 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4091 : @[Reg.scala 28:19]
|
|
_T_4092 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[31] <= _T_4092 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4093 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4094 = and(_T_4093, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4095 = and(_T_4094, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4096 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4095 : @[Reg.scala 28:19]
|
|
_T_4096 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[32] <= _T_4096 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4097 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4098 = and(_T_4097, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4099 = and(_T_4098, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4100 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4099 : @[Reg.scala 28:19]
|
|
_T_4100 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[33] <= _T_4100 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4101 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4102 = and(_T_4101, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4103 = and(_T_4102, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4104 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4103 : @[Reg.scala 28:19]
|
|
_T_4104 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[34] <= _T_4104 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4105 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4106 = and(_T_4105, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4107 = and(_T_4106, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4108 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4107 : @[Reg.scala 28:19]
|
|
_T_4108 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[35] <= _T_4108 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4109 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4110 = and(_T_4109, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4111 = and(_T_4110, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4111 : @[Reg.scala 28:19]
|
|
_T_4112 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[36] <= _T_4112 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4113 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4114 = and(_T_4113, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4115 = and(_T_4114, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4116 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4115 : @[Reg.scala 28:19]
|
|
_T_4116 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[37] <= _T_4116 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4117 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4118 = and(_T_4117, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4119 = and(_T_4118, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4120 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4119 : @[Reg.scala 28:19]
|
|
_T_4120 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[38] <= _T_4120 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4121 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4122 = and(_T_4121, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4123 = and(_T_4122, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4124 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4123 : @[Reg.scala 28:19]
|
|
_T_4124 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[39] <= _T_4124 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4125 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4126 = and(_T_4125, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4127 = and(_T_4126, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4128 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4127 : @[Reg.scala 28:19]
|
|
_T_4128 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[40] <= _T_4128 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4129 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4130 = and(_T_4129, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4131 = and(_T_4130, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4132 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4131 : @[Reg.scala 28:19]
|
|
_T_4132 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[41] <= _T_4132 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4133 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4134 = and(_T_4133, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4135 = and(_T_4134, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4136 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4135 : @[Reg.scala 28:19]
|
|
_T_4136 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[42] <= _T_4136 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4137 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4138 = and(_T_4137, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4139 = and(_T_4138, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4140 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4139 : @[Reg.scala 28:19]
|
|
_T_4140 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[43] <= _T_4140 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4141 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4142 = and(_T_4141, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4143 = and(_T_4142, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4144 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4143 : @[Reg.scala 28:19]
|
|
_T_4144 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[44] <= _T_4144 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4145 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4146 = and(_T_4145, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4147 = and(_T_4146, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4148 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4147 : @[Reg.scala 28:19]
|
|
_T_4148 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[45] <= _T_4148 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4149 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4150 = and(_T_4149, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4151 = and(_T_4150, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4152 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4151 : @[Reg.scala 28:19]
|
|
_T_4152 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[46] <= _T_4152 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4153 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4154 = and(_T_4153, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4155 = and(_T_4154, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4156 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4155 : @[Reg.scala 28:19]
|
|
_T_4156 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[47] <= _T_4156 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4157 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4158 = and(_T_4157, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4159 = and(_T_4158, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4160 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4159 : @[Reg.scala 28:19]
|
|
_T_4160 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[48] <= _T_4160 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4161 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4162 = and(_T_4161, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4163 = and(_T_4162, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4164 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4163 : @[Reg.scala 28:19]
|
|
_T_4164 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[49] <= _T_4164 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4165 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4166 = and(_T_4165, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4167 = and(_T_4166, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4167 : @[Reg.scala 28:19]
|
|
_T_4168 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[50] <= _T_4168 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4169 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4170 = and(_T_4169, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4171 = and(_T_4170, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4171 : @[Reg.scala 28:19]
|
|
_T_4172 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[51] <= _T_4172 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4173 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4174 = and(_T_4173, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4175 = and(_T_4174, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4176 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4175 : @[Reg.scala 28:19]
|
|
_T_4176 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[52] <= _T_4176 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4177 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4178 = and(_T_4177, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4179 = and(_T_4178, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4180 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4179 : @[Reg.scala 28:19]
|
|
_T_4180 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[53] <= _T_4180 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4181 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4182 = and(_T_4181, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4183 = and(_T_4182, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4184 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4183 : @[Reg.scala 28:19]
|
|
_T_4184 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[54] <= _T_4184 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4185 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4186 = and(_T_4185, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4187 = and(_T_4186, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4188 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4187 : @[Reg.scala 28:19]
|
|
_T_4188 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[55] <= _T_4188 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4189 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4190 = and(_T_4189, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4191 = and(_T_4190, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4192 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4191 : @[Reg.scala 28:19]
|
|
_T_4192 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[56] <= _T_4192 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4193 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4194 = and(_T_4193, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4195 = and(_T_4194, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4196 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4195 : @[Reg.scala 28:19]
|
|
_T_4196 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[57] <= _T_4196 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4197 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4198 = and(_T_4197, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4199 = and(_T_4198, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4200 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4199 : @[Reg.scala 28:19]
|
|
_T_4200 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[58] <= _T_4200 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4201 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4202 = and(_T_4201, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4203 = and(_T_4202, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4204 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4203 : @[Reg.scala 28:19]
|
|
_T_4204 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[59] <= _T_4204 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4205 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4206 = and(_T_4205, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4207 = and(_T_4206, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4208 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4207 : @[Reg.scala 28:19]
|
|
_T_4208 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[60] <= _T_4208 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4209 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4210 = and(_T_4209, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4211 = and(_T_4210, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4212 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4211 : @[Reg.scala 28:19]
|
|
_T_4212 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[61] <= _T_4212 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4213 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4214 = and(_T_4213, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4215 = and(_T_4214, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4216 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4215 : @[Reg.scala 28:19]
|
|
_T_4216 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[62] <= _T_4216 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4217 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4218 = and(_T_4217, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4219 = and(_T_4218, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4220 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4219 : @[Reg.scala 28:19]
|
|
_T_4220 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[63] <= _T_4220 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4221 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4222 = and(_T_4221, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4223 = and(_T_4222, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4224 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4223 : @[Reg.scala 28:19]
|
|
_T_4224 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[64] <= _T_4224 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4225 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4226 = and(_T_4225, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4227 = and(_T_4226, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4228 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4227 : @[Reg.scala 28:19]
|
|
_T_4228 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[65] <= _T_4228 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4229 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4230 = and(_T_4229, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4231 = and(_T_4230, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4232 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4231 : @[Reg.scala 28:19]
|
|
_T_4232 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[66] <= _T_4232 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4233 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4234 = and(_T_4233, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4235 = and(_T_4234, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4236 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4235 : @[Reg.scala 28:19]
|
|
_T_4236 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[67] <= _T_4236 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4237 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4238 = and(_T_4237, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4239 = and(_T_4238, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4240 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4239 : @[Reg.scala 28:19]
|
|
_T_4240 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[68] <= _T_4240 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4241 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4242 = and(_T_4241, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4243 = and(_T_4242, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4244 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4243 : @[Reg.scala 28:19]
|
|
_T_4244 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[69] <= _T_4244 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4245 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4246 = and(_T_4245, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4247 = and(_T_4246, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4248 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4247 : @[Reg.scala 28:19]
|
|
_T_4248 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[70] <= _T_4248 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4249 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4250 = and(_T_4249, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4251 = and(_T_4250, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4252 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4251 : @[Reg.scala 28:19]
|
|
_T_4252 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[71] <= _T_4252 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4253 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4254 = and(_T_4253, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4255 = and(_T_4254, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4256 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4255 : @[Reg.scala 28:19]
|
|
_T_4256 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[72] <= _T_4256 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4257 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4258 = and(_T_4257, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4259 = and(_T_4258, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4260 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4259 : @[Reg.scala 28:19]
|
|
_T_4260 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[73] <= _T_4260 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4261 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4262 = and(_T_4261, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4263 = and(_T_4262, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4264 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4263 : @[Reg.scala 28:19]
|
|
_T_4264 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[74] <= _T_4264 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4265 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4266 = and(_T_4265, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4267 = and(_T_4266, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4268 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4267 : @[Reg.scala 28:19]
|
|
_T_4268 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[75] <= _T_4268 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4269 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4270 = and(_T_4269, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4271 = and(_T_4270, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4272 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4271 : @[Reg.scala 28:19]
|
|
_T_4272 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[76] <= _T_4272 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4273 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4274 = and(_T_4273, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4275 = and(_T_4274, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4276 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4275 : @[Reg.scala 28:19]
|
|
_T_4276 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[77] <= _T_4276 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4277 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4278 = and(_T_4277, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4279 = and(_T_4278, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4280 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4279 : @[Reg.scala 28:19]
|
|
_T_4280 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[78] <= _T_4280 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4281 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4282 = and(_T_4281, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4283 = and(_T_4282, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4284 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4283 : @[Reg.scala 28:19]
|
|
_T_4284 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[79] <= _T_4284 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4285 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4286 = and(_T_4285, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4287 = and(_T_4286, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4288 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4287 : @[Reg.scala 28:19]
|
|
_T_4288 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[80] <= _T_4288 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4289 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4290 = and(_T_4289, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4291 = and(_T_4290, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4292 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4291 : @[Reg.scala 28:19]
|
|
_T_4292 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[81] <= _T_4292 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4293 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4294 = and(_T_4293, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4295 = and(_T_4294, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4296 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4295 : @[Reg.scala 28:19]
|
|
_T_4296 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[82] <= _T_4296 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4297 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4298 = and(_T_4297, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4299 = and(_T_4298, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4300 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4299 : @[Reg.scala 28:19]
|
|
_T_4300 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[83] <= _T_4300 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4301 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4302 = and(_T_4301, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4303 = and(_T_4302, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4304 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4303 : @[Reg.scala 28:19]
|
|
_T_4304 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[84] <= _T_4304 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4305 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4306 = and(_T_4305, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4307 = and(_T_4306, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4308 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4307 : @[Reg.scala 28:19]
|
|
_T_4308 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[85] <= _T_4308 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4309 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4310 = and(_T_4309, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4311 = and(_T_4310, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4312 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4311 : @[Reg.scala 28:19]
|
|
_T_4312 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[86] <= _T_4312 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4313 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4314 = and(_T_4313, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4315 = and(_T_4314, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4316 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4315 : @[Reg.scala 28:19]
|
|
_T_4316 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[87] <= _T_4316 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4317 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4318 = and(_T_4317, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4319 = and(_T_4318, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4320 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4319 : @[Reg.scala 28:19]
|
|
_T_4320 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[88] <= _T_4320 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4321 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4322 = and(_T_4321, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4323 = and(_T_4322, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4324 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4323 : @[Reg.scala 28:19]
|
|
_T_4324 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[89] <= _T_4324 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4325 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4326 = and(_T_4325, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4327 = and(_T_4326, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4328 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4327 : @[Reg.scala 28:19]
|
|
_T_4328 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[90] <= _T_4328 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4329 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4330 = and(_T_4329, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4331 = and(_T_4330, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4332 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4331 : @[Reg.scala 28:19]
|
|
_T_4332 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[91] <= _T_4332 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4333 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4334 = and(_T_4333, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4335 = and(_T_4334, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4336 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4335 : @[Reg.scala 28:19]
|
|
_T_4336 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[92] <= _T_4336 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4337 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4338 = and(_T_4337, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4339 = and(_T_4338, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4340 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4339 : @[Reg.scala 28:19]
|
|
_T_4340 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[93] <= _T_4340 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4341 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4342 = and(_T_4341, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4343 = and(_T_4342, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4344 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4343 : @[Reg.scala 28:19]
|
|
_T_4344 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[94] <= _T_4344 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4345 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4346 = and(_T_4345, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4347 = and(_T_4346, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4348 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4347 : @[Reg.scala 28:19]
|
|
_T_4348 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[95] <= _T_4348 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4349 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4350 = and(_T_4349, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4351 = and(_T_4350, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4352 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4351 : @[Reg.scala 28:19]
|
|
_T_4352 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[96] <= _T_4352 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4353 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4354 = and(_T_4353, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4355 = and(_T_4354, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4356 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4355 : @[Reg.scala 28:19]
|
|
_T_4356 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[97] <= _T_4356 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4357 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4358 = and(_T_4357, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4359 = and(_T_4358, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4360 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4359 : @[Reg.scala 28:19]
|
|
_T_4360 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[98] <= _T_4360 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4361 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4362 = and(_T_4361, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4363 = and(_T_4362, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4364 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4363 : @[Reg.scala 28:19]
|
|
_T_4364 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[99] <= _T_4364 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4365 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4366 = and(_T_4365, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4367 = and(_T_4366, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4368 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4367 : @[Reg.scala 28:19]
|
|
_T_4368 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[100] <= _T_4368 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4369 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4370 = and(_T_4369, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4371 = and(_T_4370, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4372 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4371 : @[Reg.scala 28:19]
|
|
_T_4372 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[101] <= _T_4372 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4373 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4374 = and(_T_4373, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4375 = and(_T_4374, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4376 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4375 : @[Reg.scala 28:19]
|
|
_T_4376 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[102] <= _T_4376 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4377 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4378 = and(_T_4377, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4379 = and(_T_4378, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4380 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4379 : @[Reg.scala 28:19]
|
|
_T_4380 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[103] <= _T_4380 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4381 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4382 = and(_T_4381, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4383 = and(_T_4382, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4384 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4383 : @[Reg.scala 28:19]
|
|
_T_4384 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[104] <= _T_4384 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4385 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4386 = and(_T_4385, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4387 = and(_T_4386, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4388 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4387 : @[Reg.scala 28:19]
|
|
_T_4388 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[105] <= _T_4388 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4389 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4390 = and(_T_4389, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4391 = and(_T_4390, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4392 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4391 : @[Reg.scala 28:19]
|
|
_T_4392 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[106] <= _T_4392 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4393 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4394 = and(_T_4393, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4395 = and(_T_4394, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4396 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4395 : @[Reg.scala 28:19]
|
|
_T_4396 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[107] <= _T_4396 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4397 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4398 = and(_T_4397, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4399 = and(_T_4398, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4400 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4399 : @[Reg.scala 28:19]
|
|
_T_4400 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[108] <= _T_4400 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4401 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4402 = and(_T_4401, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4403 = and(_T_4402, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4404 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4403 : @[Reg.scala 28:19]
|
|
_T_4404 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[109] <= _T_4404 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4405 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4406 = and(_T_4405, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4407 = and(_T_4406, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4408 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4407 : @[Reg.scala 28:19]
|
|
_T_4408 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[110] <= _T_4408 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4409 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4410 = and(_T_4409, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4411 = and(_T_4410, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4412 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4411 : @[Reg.scala 28:19]
|
|
_T_4412 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[111] <= _T_4412 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4413 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4414 = and(_T_4413, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4415 = and(_T_4414, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4416 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4415 : @[Reg.scala 28:19]
|
|
_T_4416 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[112] <= _T_4416 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4417 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4418 = and(_T_4417, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4419 = and(_T_4418, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4420 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4419 : @[Reg.scala 28:19]
|
|
_T_4420 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[113] <= _T_4420 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4421 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4422 = and(_T_4421, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4423 = and(_T_4422, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4424 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4423 : @[Reg.scala 28:19]
|
|
_T_4424 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[114] <= _T_4424 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4425 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4426 = and(_T_4425, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4427 = and(_T_4426, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4428 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4427 : @[Reg.scala 28:19]
|
|
_T_4428 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[115] <= _T_4428 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4429 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4430 = and(_T_4429, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4431 = and(_T_4430, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4432 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4431 : @[Reg.scala 28:19]
|
|
_T_4432 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[116] <= _T_4432 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4433 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4434 = and(_T_4433, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4435 = and(_T_4434, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4436 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4435 : @[Reg.scala 28:19]
|
|
_T_4436 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[117] <= _T_4436 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4437 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4438 = and(_T_4437, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4439 = and(_T_4438, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4440 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4439 : @[Reg.scala 28:19]
|
|
_T_4440 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[118] <= _T_4440 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4441 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4442 = and(_T_4441, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4443 = and(_T_4442, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4444 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4443 : @[Reg.scala 28:19]
|
|
_T_4444 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[119] <= _T_4444 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4445 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4446 = and(_T_4445, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4447 = and(_T_4446, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4448 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4447 : @[Reg.scala 28:19]
|
|
_T_4448 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[120] <= _T_4448 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4449 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4450 = and(_T_4449, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4451 = and(_T_4450, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4452 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4451 : @[Reg.scala 28:19]
|
|
_T_4452 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[121] <= _T_4452 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4453 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4454 = and(_T_4453, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4455 = and(_T_4454, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4456 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4455 : @[Reg.scala 28:19]
|
|
_T_4456 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[122] <= _T_4456 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4457 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4458 = and(_T_4457, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4459 = and(_T_4458, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4460 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4459 : @[Reg.scala 28:19]
|
|
_T_4460 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[123] <= _T_4460 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4461 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4462 = and(_T_4461, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4463 = and(_T_4462, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4464 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4463 : @[Reg.scala 28:19]
|
|
_T_4464 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[124] <= _T_4464 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4465 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4466 = and(_T_4465, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4467 = and(_T_4466, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4468 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4467 : @[Reg.scala 28:19]
|
|
_T_4468 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[125] <= _T_4468 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4469 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4470 = and(_T_4469, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4471 = and(_T_4470, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4472 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4471 : @[Reg.scala 28:19]
|
|
_T_4472 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[126] <= _T_4472 @[el2_ifu_mem_ctl.scala 715:33]
|
|
node _T_4473 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93]
|
|
node _T_4474 = and(_T_4473, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102]
|
|
node _T_4475 = and(_T_4474, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124]
|
|
reg _T_4476 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_4475 : @[Reg.scala 28:19]
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_T_4476 <= way_status_new_ff @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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way_status_out[127] <= _T_4476 @[el2_ifu_mem_ctl.scala 715:33]
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node _T_4477 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:121]
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node _T_4478 = bits(_T_4477, 0, 0) @[Bitwise.scala 72:15]
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node _T_4479 = mux(_T_4478, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4480 = and(_T_4479, way_status_out[0]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4481 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:121]
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node _T_4482 = bits(_T_4481, 0, 0) @[Bitwise.scala 72:15]
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node _T_4483 = mux(_T_4482, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4484 = and(_T_4483, way_status_out[1]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4485 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:121]
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node _T_4486 = bits(_T_4485, 0, 0) @[Bitwise.scala 72:15]
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node _T_4487 = mux(_T_4486, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4488 = and(_T_4487, way_status_out[2]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4489 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:121]
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node _T_4490 = bits(_T_4489, 0, 0) @[Bitwise.scala 72:15]
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node _T_4491 = mux(_T_4490, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4492 = and(_T_4491, way_status_out[3]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4493 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:121]
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node _T_4494 = bits(_T_4493, 0, 0) @[Bitwise.scala 72:15]
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node _T_4495 = mux(_T_4494, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4496 = and(_T_4495, way_status_out[4]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4497 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4498 = bits(_T_4497, 0, 0) @[Bitwise.scala 72:15]
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node _T_4499 = mux(_T_4498, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4500 = and(_T_4499, way_status_out[5]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4501 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4502 = bits(_T_4501, 0, 0) @[Bitwise.scala 72:15]
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node _T_4503 = mux(_T_4502, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4504 = and(_T_4503, way_status_out[6]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4505 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4506 = bits(_T_4505, 0, 0) @[Bitwise.scala 72:15]
|
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node _T_4507 = mux(_T_4506, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
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node _T_4508 = and(_T_4507, way_status_out[7]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4509 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4510 = bits(_T_4509, 0, 0) @[Bitwise.scala 72:15]
|
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node _T_4511 = mux(_T_4510, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
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node _T_4512 = and(_T_4511, way_status_out[8]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4513 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4514 = bits(_T_4513, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4515 = mux(_T_4514, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4516 = and(_T_4515, way_status_out[9]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4517 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4518 = bits(_T_4517, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4519 = mux(_T_4518, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4520 = and(_T_4519, way_status_out[10]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4521 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4522 = bits(_T_4521, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4523 = mux(_T_4522, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4524 = and(_T_4523, way_status_out[11]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4525 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 716:121]
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|
node _T_4526 = bits(_T_4525, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4527 = mux(_T_4526, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4528 = and(_T_4527, way_status_out[12]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4529 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4530 = bits(_T_4529, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4531 = mux(_T_4530, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4532 = and(_T_4531, way_status_out[13]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4533 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 716:121]
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|
node _T_4534 = bits(_T_4533, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4535 = mux(_T_4534, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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|
node _T_4536 = and(_T_4535, way_status_out[14]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4537 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 716:121]
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|
node _T_4538 = bits(_T_4537, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4539 = mux(_T_4538, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4540 = and(_T_4539, way_status_out[15]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4541 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4542 = bits(_T_4541, 0, 0) @[Bitwise.scala 72:15]
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|
node _T_4543 = mux(_T_4542, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4544 = and(_T_4543, way_status_out[16]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4545 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 716:121]
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node _T_4546 = bits(_T_4545, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4547 = mux(_T_4546, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4548 = and(_T_4547, way_status_out[17]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4549 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 716:121]
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node _T_4550 = bits(_T_4549, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4551 = mux(_T_4550, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4552 = and(_T_4551, way_status_out[18]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4553 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 716:121]
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node _T_4554 = bits(_T_4553, 0, 0) @[Bitwise.scala 72:15]
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|
node _T_4555 = mux(_T_4554, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4556 = and(_T_4555, way_status_out[19]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4557 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 716:121]
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node _T_4558 = bits(_T_4557, 0, 0) @[Bitwise.scala 72:15]
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node _T_4559 = mux(_T_4558, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4560 = and(_T_4559, way_status_out[20]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4561 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 716:121]
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node _T_4562 = bits(_T_4561, 0, 0) @[Bitwise.scala 72:15]
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|
node _T_4563 = mux(_T_4562, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4564 = and(_T_4563, way_status_out[21]) @[el2_ifu_mem_ctl.scala 716:130]
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node _T_4565 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 716:121]
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node _T_4566 = bits(_T_4565, 0, 0) @[Bitwise.scala 72:15]
|
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node _T_4567 = mux(_T_4566, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
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node _T_4568 = and(_T_4567, way_status_out[22]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4569 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4570 = bits(_T_4569, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4571 = mux(_T_4570, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4572 = and(_T_4571, way_status_out[23]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4573 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4574 = bits(_T_4573, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4575 = mux(_T_4574, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
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node _T_4576 = and(_T_4575, way_status_out[24]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4577 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4578 = bits(_T_4577, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4579 = mux(_T_4578, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4580 = and(_T_4579, way_status_out[25]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4581 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4582 = bits(_T_4581, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4583 = mux(_T_4582, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4584 = and(_T_4583, way_status_out[26]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4585 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4586 = bits(_T_4585, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4587 = mux(_T_4586, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4588 = and(_T_4587, way_status_out[27]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4589 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4590 = bits(_T_4589, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4591 = mux(_T_4590, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4592 = and(_T_4591, way_status_out[28]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4593 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4594 = bits(_T_4593, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4595 = mux(_T_4594, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4596 = and(_T_4595, way_status_out[29]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4597 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4598 = bits(_T_4597, 0, 0) @[Bitwise.scala 72:15]
|
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node _T_4599 = mux(_T_4598, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
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node _T_4600 = and(_T_4599, way_status_out[30]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4601 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4602 = bits(_T_4601, 0, 0) @[Bitwise.scala 72:15]
|
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node _T_4603 = mux(_T_4602, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
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node _T_4604 = and(_T_4603, way_status_out[31]) @[el2_ifu_mem_ctl.scala 716:130]
|
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node _T_4605 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4606 = bits(_T_4605, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4607 = mux(_T_4606, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4608 = and(_T_4607, way_status_out[32]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4609 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 716:121]
|
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node _T_4610 = bits(_T_4609, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4611 = mux(_T_4610, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4612 = and(_T_4611, way_status_out[33]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4613 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4614 = bits(_T_4613, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4615 = mux(_T_4614, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4616 = and(_T_4615, way_status_out[34]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4617 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4618 = bits(_T_4617, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4619 = mux(_T_4618, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4620 = and(_T_4619, way_status_out[35]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4621 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4622 = bits(_T_4621, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4623 = mux(_T_4622, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4624 = and(_T_4623, way_status_out[36]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4625 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4626 = bits(_T_4625, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4627 = mux(_T_4626, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4628 = and(_T_4627, way_status_out[37]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4629 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4630 = bits(_T_4629, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4631 = mux(_T_4630, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4632 = and(_T_4631, way_status_out[38]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4633 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4634 = bits(_T_4633, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4635 = mux(_T_4634, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4636 = and(_T_4635, way_status_out[39]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4637 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4638 = bits(_T_4637, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4639 = mux(_T_4638, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4640 = and(_T_4639, way_status_out[40]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4641 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4642 = bits(_T_4641, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4643 = mux(_T_4642, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4644 = and(_T_4643, way_status_out[41]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4645 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4646 = bits(_T_4645, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4647 = mux(_T_4646, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4648 = and(_T_4647, way_status_out[42]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4649 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4650 = bits(_T_4649, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4651 = mux(_T_4650, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4652 = and(_T_4651, way_status_out[43]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4653 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4654 = bits(_T_4653, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4655 = mux(_T_4654, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4656 = and(_T_4655, way_status_out[44]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4657 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4658 = bits(_T_4657, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4659 = mux(_T_4658, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4660 = and(_T_4659, way_status_out[45]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4661 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4662 = bits(_T_4661, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4663 = mux(_T_4662, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4664 = and(_T_4663, way_status_out[46]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4665 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4666 = bits(_T_4665, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4667 = mux(_T_4666, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4668 = and(_T_4667, way_status_out[47]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4669 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4670 = bits(_T_4669, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4671 = mux(_T_4670, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4672 = and(_T_4671, way_status_out[48]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4673 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4674 = bits(_T_4673, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4675 = mux(_T_4674, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4676 = and(_T_4675, way_status_out[49]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4677 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4678 = bits(_T_4677, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4679 = mux(_T_4678, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4680 = and(_T_4679, way_status_out[50]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4681 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4682 = bits(_T_4681, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4683 = mux(_T_4682, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4684 = and(_T_4683, way_status_out[51]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4685 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4686 = bits(_T_4685, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4687 = mux(_T_4686, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4688 = and(_T_4687, way_status_out[52]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4689 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4690 = bits(_T_4689, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4691 = mux(_T_4690, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4692 = and(_T_4691, way_status_out[53]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4693 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4694 = bits(_T_4693, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4695 = mux(_T_4694, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4696 = and(_T_4695, way_status_out[54]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4697 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4698 = bits(_T_4697, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4699 = mux(_T_4698, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4700 = and(_T_4699, way_status_out[55]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4701 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4702 = bits(_T_4701, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4703 = mux(_T_4702, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4704 = and(_T_4703, way_status_out[56]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4705 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4706 = bits(_T_4705, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4707 = mux(_T_4706, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4708 = and(_T_4707, way_status_out[57]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4709 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4710 = bits(_T_4709, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4711 = mux(_T_4710, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4712 = and(_T_4711, way_status_out[58]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4713 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4714 = bits(_T_4713, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4715 = mux(_T_4714, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4716 = and(_T_4715, way_status_out[59]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4717 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4718 = bits(_T_4717, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4719 = mux(_T_4718, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4720 = and(_T_4719, way_status_out[60]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4721 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4722 = bits(_T_4721, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4723 = mux(_T_4722, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4724 = and(_T_4723, way_status_out[61]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4725 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4726 = bits(_T_4725, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4727 = mux(_T_4726, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4728 = and(_T_4727, way_status_out[62]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4729 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4730 = bits(_T_4729, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4731 = mux(_T_4730, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4732 = and(_T_4731, way_status_out[63]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4733 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4734 = bits(_T_4733, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4735 = mux(_T_4734, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4736 = and(_T_4735, way_status_out[64]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4737 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4738 = bits(_T_4737, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4739 = mux(_T_4738, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4740 = and(_T_4739, way_status_out[65]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4741 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4742 = bits(_T_4741, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4743 = mux(_T_4742, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4744 = and(_T_4743, way_status_out[66]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4745 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4746 = bits(_T_4745, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4747 = mux(_T_4746, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4748 = and(_T_4747, way_status_out[67]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4749 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4750 = bits(_T_4749, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4751 = mux(_T_4750, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4752 = and(_T_4751, way_status_out[68]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4753 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4754 = bits(_T_4753, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4755 = mux(_T_4754, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4756 = and(_T_4755, way_status_out[69]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4757 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4758 = bits(_T_4757, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4759 = mux(_T_4758, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4760 = and(_T_4759, way_status_out[70]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4761 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4762 = bits(_T_4761, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4763 = mux(_T_4762, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4764 = and(_T_4763, way_status_out[71]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4765 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4766 = bits(_T_4765, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4767 = mux(_T_4766, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4768 = and(_T_4767, way_status_out[72]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4769 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4770 = bits(_T_4769, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4771 = mux(_T_4770, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4772 = and(_T_4771, way_status_out[73]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4773 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4774 = bits(_T_4773, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4775 = mux(_T_4774, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4776 = and(_T_4775, way_status_out[74]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4777 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4778 = bits(_T_4777, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4779 = mux(_T_4778, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4780 = and(_T_4779, way_status_out[75]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4781 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4782 = bits(_T_4781, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4783 = mux(_T_4782, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4784 = and(_T_4783, way_status_out[76]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4785 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4786 = bits(_T_4785, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4787 = mux(_T_4786, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4788 = and(_T_4787, way_status_out[77]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4789 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4790 = bits(_T_4789, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4791 = mux(_T_4790, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4792 = and(_T_4791, way_status_out[78]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4793 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4794 = bits(_T_4793, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4795 = mux(_T_4794, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4796 = and(_T_4795, way_status_out[79]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4797 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4798 = bits(_T_4797, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4799 = mux(_T_4798, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4800 = and(_T_4799, way_status_out[80]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4801 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4802 = bits(_T_4801, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4803 = mux(_T_4802, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4804 = and(_T_4803, way_status_out[81]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4805 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4806 = bits(_T_4805, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4807 = mux(_T_4806, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4808 = and(_T_4807, way_status_out[82]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4809 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4810 = bits(_T_4809, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4811 = mux(_T_4810, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4812 = and(_T_4811, way_status_out[83]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4813 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4814 = bits(_T_4813, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4815 = mux(_T_4814, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4816 = and(_T_4815, way_status_out[84]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4817 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4818 = bits(_T_4817, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4819 = mux(_T_4818, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4820 = and(_T_4819, way_status_out[85]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4821 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4822 = bits(_T_4821, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4823 = mux(_T_4822, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4824 = and(_T_4823, way_status_out[86]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4825 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4826 = bits(_T_4825, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4827 = mux(_T_4826, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4828 = and(_T_4827, way_status_out[87]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4829 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4830 = bits(_T_4829, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4831 = mux(_T_4830, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4832 = and(_T_4831, way_status_out[88]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4833 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4834 = bits(_T_4833, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4835 = mux(_T_4834, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4836 = and(_T_4835, way_status_out[89]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4837 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4838 = bits(_T_4837, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4839 = mux(_T_4838, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4840 = and(_T_4839, way_status_out[90]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4841 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4842 = bits(_T_4841, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4843 = mux(_T_4842, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4844 = and(_T_4843, way_status_out[91]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4845 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4846 = bits(_T_4845, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4847 = mux(_T_4846, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4848 = and(_T_4847, way_status_out[92]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4849 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4850 = bits(_T_4849, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4851 = mux(_T_4850, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4852 = and(_T_4851, way_status_out[93]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4853 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4854 = bits(_T_4853, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4855 = mux(_T_4854, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4856 = and(_T_4855, way_status_out[94]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4857 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4858 = bits(_T_4857, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4859 = mux(_T_4858, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4860 = and(_T_4859, way_status_out[95]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4861 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4862 = bits(_T_4861, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4863 = mux(_T_4862, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4864 = and(_T_4863, way_status_out[96]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4865 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4866 = bits(_T_4865, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4867 = mux(_T_4866, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4868 = and(_T_4867, way_status_out[97]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4869 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4870 = bits(_T_4869, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4871 = mux(_T_4870, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4872 = and(_T_4871, way_status_out[98]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4873 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4874 = bits(_T_4873, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4875 = mux(_T_4874, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4876 = and(_T_4875, way_status_out[99]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4877 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4878 = bits(_T_4877, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4879 = mux(_T_4878, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4880 = and(_T_4879, way_status_out[100]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4881 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4882 = bits(_T_4881, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4883 = mux(_T_4882, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4884 = and(_T_4883, way_status_out[101]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4885 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4886 = bits(_T_4885, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4887 = mux(_T_4886, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4888 = and(_T_4887, way_status_out[102]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4889 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4890 = bits(_T_4889, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4891 = mux(_T_4890, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4892 = and(_T_4891, way_status_out[103]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4893 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4894 = bits(_T_4893, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4895 = mux(_T_4894, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4896 = and(_T_4895, way_status_out[104]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4897 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4898 = bits(_T_4897, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4899 = mux(_T_4898, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4900 = and(_T_4899, way_status_out[105]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4901 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4902 = bits(_T_4901, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4903 = mux(_T_4902, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4904 = and(_T_4903, way_status_out[106]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4905 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4906 = bits(_T_4905, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4907 = mux(_T_4906, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4908 = and(_T_4907, way_status_out[107]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4909 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4910 = bits(_T_4909, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4911 = mux(_T_4910, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4912 = and(_T_4911, way_status_out[108]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4913 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4914 = bits(_T_4913, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4915 = mux(_T_4914, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4916 = and(_T_4915, way_status_out[109]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4917 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4918 = bits(_T_4917, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4919 = mux(_T_4918, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4920 = and(_T_4919, way_status_out[110]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4921 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4922 = bits(_T_4921, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4923 = mux(_T_4922, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4924 = and(_T_4923, way_status_out[111]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4925 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4926 = bits(_T_4925, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4927 = mux(_T_4926, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4928 = and(_T_4927, way_status_out[112]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4929 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4930 = bits(_T_4929, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4931 = mux(_T_4930, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4932 = and(_T_4931, way_status_out[113]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4933 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4934 = bits(_T_4933, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4935 = mux(_T_4934, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4936 = and(_T_4935, way_status_out[114]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4937 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4938 = bits(_T_4937, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4939 = mux(_T_4938, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4940 = and(_T_4939, way_status_out[115]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4941 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4942 = bits(_T_4941, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4943 = mux(_T_4942, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4944 = and(_T_4943, way_status_out[116]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4945 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4946 = bits(_T_4945, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4947 = mux(_T_4946, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4948 = and(_T_4947, way_status_out[117]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4949 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4950 = bits(_T_4949, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4951 = mux(_T_4950, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4952 = and(_T_4951, way_status_out[118]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4953 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4954 = bits(_T_4953, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4955 = mux(_T_4954, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4956 = and(_T_4955, way_status_out[119]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4957 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4958 = bits(_T_4957, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4959 = mux(_T_4958, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4960 = and(_T_4959, way_status_out[120]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4961 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4962 = bits(_T_4961, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4963 = mux(_T_4962, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4964 = and(_T_4963, way_status_out[121]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4965 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4966 = bits(_T_4965, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4967 = mux(_T_4966, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4968 = and(_T_4967, way_status_out[122]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4969 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4970 = bits(_T_4969, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4971 = mux(_T_4970, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4972 = and(_T_4971, way_status_out[123]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4973 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4974 = bits(_T_4973, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4975 = mux(_T_4974, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4976 = and(_T_4975, way_status_out[124]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4977 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4978 = bits(_T_4977, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4979 = mux(_T_4978, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4980 = and(_T_4979, way_status_out[125]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4981 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4982 = bits(_T_4981, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4983 = mux(_T_4982, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4984 = and(_T_4983, way_status_out[126]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4985 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 716:121]
|
|
node _T_4986 = bits(_T_4985, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4987 = mux(_T_4986, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4988 = and(_T_4987, way_status_out[127]) @[el2_ifu_mem_ctl.scala 716:130]
|
|
node _T_4989 = cat(_T_4988, _T_4984) @[Cat.scala 29:58]
|
|
node _T_4990 = cat(_T_4989, _T_4980) @[Cat.scala 29:58]
|
|
node _T_4991 = cat(_T_4990, _T_4976) @[Cat.scala 29:58]
|
|
node _T_4992 = cat(_T_4991, _T_4972) @[Cat.scala 29:58]
|
|
node _T_4993 = cat(_T_4992, _T_4968) @[Cat.scala 29:58]
|
|
node _T_4994 = cat(_T_4993, _T_4964) @[Cat.scala 29:58]
|
|
node _T_4995 = cat(_T_4994, _T_4960) @[Cat.scala 29:58]
|
|
node _T_4996 = cat(_T_4995, _T_4956) @[Cat.scala 29:58]
|
|
node _T_4997 = cat(_T_4996, _T_4952) @[Cat.scala 29:58]
|
|
node _T_4998 = cat(_T_4997, _T_4948) @[Cat.scala 29:58]
|
|
node _T_4999 = cat(_T_4998, _T_4944) @[Cat.scala 29:58]
|
|
node _T_5000 = cat(_T_4999, _T_4940) @[Cat.scala 29:58]
|
|
node _T_5001 = cat(_T_5000, _T_4936) @[Cat.scala 29:58]
|
|
node _T_5002 = cat(_T_5001, _T_4932) @[Cat.scala 29:58]
|
|
node _T_5003 = cat(_T_5002, _T_4928) @[Cat.scala 29:58]
|
|
node _T_5004 = cat(_T_5003, _T_4924) @[Cat.scala 29:58]
|
|
node _T_5005 = cat(_T_5004, _T_4920) @[Cat.scala 29:58]
|
|
node _T_5006 = cat(_T_5005, _T_4916) @[Cat.scala 29:58]
|
|
node _T_5007 = cat(_T_5006, _T_4912) @[Cat.scala 29:58]
|
|
node _T_5008 = cat(_T_5007, _T_4908) @[Cat.scala 29:58]
|
|
node _T_5009 = cat(_T_5008, _T_4904) @[Cat.scala 29:58]
|
|
node _T_5010 = cat(_T_5009, _T_4900) @[Cat.scala 29:58]
|
|
node _T_5011 = cat(_T_5010, _T_4896) @[Cat.scala 29:58]
|
|
node _T_5012 = cat(_T_5011, _T_4892) @[Cat.scala 29:58]
|
|
node _T_5013 = cat(_T_5012, _T_4888) @[Cat.scala 29:58]
|
|
node _T_5014 = cat(_T_5013, _T_4884) @[Cat.scala 29:58]
|
|
node _T_5015 = cat(_T_5014, _T_4880) @[Cat.scala 29:58]
|
|
node _T_5016 = cat(_T_5015, _T_4876) @[Cat.scala 29:58]
|
|
node _T_5017 = cat(_T_5016, _T_4872) @[Cat.scala 29:58]
|
|
node _T_5018 = cat(_T_5017, _T_4868) @[Cat.scala 29:58]
|
|
node _T_5019 = cat(_T_5018, _T_4864) @[Cat.scala 29:58]
|
|
node _T_5020 = cat(_T_5019, _T_4860) @[Cat.scala 29:58]
|
|
node _T_5021 = cat(_T_5020, _T_4856) @[Cat.scala 29:58]
|
|
node _T_5022 = cat(_T_5021, _T_4852) @[Cat.scala 29:58]
|
|
node _T_5023 = cat(_T_5022, _T_4848) @[Cat.scala 29:58]
|
|
node _T_5024 = cat(_T_5023, _T_4844) @[Cat.scala 29:58]
|
|
node _T_5025 = cat(_T_5024, _T_4840) @[Cat.scala 29:58]
|
|
node _T_5026 = cat(_T_5025, _T_4836) @[Cat.scala 29:58]
|
|
node _T_5027 = cat(_T_5026, _T_4832) @[Cat.scala 29:58]
|
|
node _T_5028 = cat(_T_5027, _T_4828) @[Cat.scala 29:58]
|
|
node _T_5029 = cat(_T_5028, _T_4824) @[Cat.scala 29:58]
|
|
node _T_5030 = cat(_T_5029, _T_4820) @[Cat.scala 29:58]
|
|
node _T_5031 = cat(_T_5030, _T_4816) @[Cat.scala 29:58]
|
|
node _T_5032 = cat(_T_5031, _T_4812) @[Cat.scala 29:58]
|
|
node _T_5033 = cat(_T_5032, _T_4808) @[Cat.scala 29:58]
|
|
node _T_5034 = cat(_T_5033, _T_4804) @[Cat.scala 29:58]
|
|
node _T_5035 = cat(_T_5034, _T_4800) @[Cat.scala 29:58]
|
|
node _T_5036 = cat(_T_5035, _T_4796) @[Cat.scala 29:58]
|
|
node _T_5037 = cat(_T_5036, _T_4792) @[Cat.scala 29:58]
|
|
node _T_5038 = cat(_T_5037, _T_4788) @[Cat.scala 29:58]
|
|
node _T_5039 = cat(_T_5038, _T_4784) @[Cat.scala 29:58]
|
|
node _T_5040 = cat(_T_5039, _T_4780) @[Cat.scala 29:58]
|
|
node _T_5041 = cat(_T_5040, _T_4776) @[Cat.scala 29:58]
|
|
node _T_5042 = cat(_T_5041, _T_4772) @[Cat.scala 29:58]
|
|
node _T_5043 = cat(_T_5042, _T_4768) @[Cat.scala 29:58]
|
|
node _T_5044 = cat(_T_5043, _T_4764) @[Cat.scala 29:58]
|
|
node _T_5045 = cat(_T_5044, _T_4760) @[Cat.scala 29:58]
|
|
node _T_5046 = cat(_T_5045, _T_4756) @[Cat.scala 29:58]
|
|
node _T_5047 = cat(_T_5046, _T_4752) @[Cat.scala 29:58]
|
|
node _T_5048 = cat(_T_5047, _T_4748) @[Cat.scala 29:58]
|
|
node _T_5049 = cat(_T_5048, _T_4744) @[Cat.scala 29:58]
|
|
node _T_5050 = cat(_T_5049, _T_4740) @[Cat.scala 29:58]
|
|
node _T_5051 = cat(_T_5050, _T_4736) @[Cat.scala 29:58]
|
|
node _T_5052 = cat(_T_5051, _T_4732) @[Cat.scala 29:58]
|
|
node _T_5053 = cat(_T_5052, _T_4728) @[Cat.scala 29:58]
|
|
node _T_5054 = cat(_T_5053, _T_4724) @[Cat.scala 29:58]
|
|
node _T_5055 = cat(_T_5054, _T_4720) @[Cat.scala 29:58]
|
|
node _T_5056 = cat(_T_5055, _T_4716) @[Cat.scala 29:58]
|
|
node _T_5057 = cat(_T_5056, _T_4712) @[Cat.scala 29:58]
|
|
node _T_5058 = cat(_T_5057, _T_4708) @[Cat.scala 29:58]
|
|
node _T_5059 = cat(_T_5058, _T_4704) @[Cat.scala 29:58]
|
|
node _T_5060 = cat(_T_5059, _T_4700) @[Cat.scala 29:58]
|
|
node _T_5061 = cat(_T_5060, _T_4696) @[Cat.scala 29:58]
|
|
node _T_5062 = cat(_T_5061, _T_4692) @[Cat.scala 29:58]
|
|
node _T_5063 = cat(_T_5062, _T_4688) @[Cat.scala 29:58]
|
|
node _T_5064 = cat(_T_5063, _T_4684) @[Cat.scala 29:58]
|
|
node _T_5065 = cat(_T_5064, _T_4680) @[Cat.scala 29:58]
|
|
node _T_5066 = cat(_T_5065, _T_4676) @[Cat.scala 29:58]
|
|
node _T_5067 = cat(_T_5066, _T_4672) @[Cat.scala 29:58]
|
|
node _T_5068 = cat(_T_5067, _T_4668) @[Cat.scala 29:58]
|
|
node _T_5069 = cat(_T_5068, _T_4664) @[Cat.scala 29:58]
|
|
node _T_5070 = cat(_T_5069, _T_4660) @[Cat.scala 29:58]
|
|
node _T_5071 = cat(_T_5070, _T_4656) @[Cat.scala 29:58]
|
|
node _T_5072 = cat(_T_5071, _T_4652) @[Cat.scala 29:58]
|
|
node _T_5073 = cat(_T_5072, _T_4648) @[Cat.scala 29:58]
|
|
node _T_5074 = cat(_T_5073, _T_4644) @[Cat.scala 29:58]
|
|
node _T_5075 = cat(_T_5074, _T_4640) @[Cat.scala 29:58]
|
|
node _T_5076 = cat(_T_5075, _T_4636) @[Cat.scala 29:58]
|
|
node _T_5077 = cat(_T_5076, _T_4632) @[Cat.scala 29:58]
|
|
node _T_5078 = cat(_T_5077, _T_4628) @[Cat.scala 29:58]
|
|
node _T_5079 = cat(_T_5078, _T_4624) @[Cat.scala 29:58]
|
|
node _T_5080 = cat(_T_5079, _T_4620) @[Cat.scala 29:58]
|
|
node _T_5081 = cat(_T_5080, _T_4616) @[Cat.scala 29:58]
|
|
node _T_5082 = cat(_T_5081, _T_4612) @[Cat.scala 29:58]
|
|
node _T_5083 = cat(_T_5082, _T_4608) @[Cat.scala 29:58]
|
|
node _T_5084 = cat(_T_5083, _T_4604) @[Cat.scala 29:58]
|
|
node _T_5085 = cat(_T_5084, _T_4600) @[Cat.scala 29:58]
|
|
node _T_5086 = cat(_T_5085, _T_4596) @[Cat.scala 29:58]
|
|
node _T_5087 = cat(_T_5086, _T_4592) @[Cat.scala 29:58]
|
|
node _T_5088 = cat(_T_5087, _T_4588) @[Cat.scala 29:58]
|
|
node _T_5089 = cat(_T_5088, _T_4584) @[Cat.scala 29:58]
|
|
node _T_5090 = cat(_T_5089, _T_4580) @[Cat.scala 29:58]
|
|
node _T_5091 = cat(_T_5090, _T_4576) @[Cat.scala 29:58]
|
|
node _T_5092 = cat(_T_5091, _T_4572) @[Cat.scala 29:58]
|
|
node _T_5093 = cat(_T_5092, _T_4568) @[Cat.scala 29:58]
|
|
node _T_5094 = cat(_T_5093, _T_4564) @[Cat.scala 29:58]
|
|
node _T_5095 = cat(_T_5094, _T_4560) @[Cat.scala 29:58]
|
|
node _T_5096 = cat(_T_5095, _T_4556) @[Cat.scala 29:58]
|
|
node _T_5097 = cat(_T_5096, _T_4552) @[Cat.scala 29:58]
|
|
node _T_5098 = cat(_T_5097, _T_4548) @[Cat.scala 29:58]
|
|
node _T_5099 = cat(_T_5098, _T_4544) @[Cat.scala 29:58]
|
|
node _T_5100 = cat(_T_5099, _T_4540) @[Cat.scala 29:58]
|
|
node _T_5101 = cat(_T_5100, _T_4536) @[Cat.scala 29:58]
|
|
node _T_5102 = cat(_T_5101, _T_4532) @[Cat.scala 29:58]
|
|
node _T_5103 = cat(_T_5102, _T_4528) @[Cat.scala 29:58]
|
|
node _T_5104 = cat(_T_5103, _T_4524) @[Cat.scala 29:58]
|
|
node _T_5105 = cat(_T_5104, _T_4520) @[Cat.scala 29:58]
|
|
node _T_5106 = cat(_T_5105, _T_4516) @[Cat.scala 29:58]
|
|
node _T_5107 = cat(_T_5106, _T_4512) @[Cat.scala 29:58]
|
|
node _T_5108 = cat(_T_5107, _T_4508) @[Cat.scala 29:58]
|
|
node _T_5109 = cat(_T_5108, _T_4504) @[Cat.scala 29:58]
|
|
node _T_5110 = cat(_T_5109, _T_4500) @[Cat.scala 29:58]
|
|
node _T_5111 = cat(_T_5110, _T_4496) @[Cat.scala 29:58]
|
|
node _T_5112 = cat(_T_5111, _T_4492) @[Cat.scala 29:58]
|
|
node _T_5113 = cat(_T_5112, _T_4488) @[Cat.scala 29:58]
|
|
node _T_5114 = cat(_T_5113, _T_4484) @[Cat.scala 29:58]
|
|
node _T_5115 = cat(_T_5114, _T_4480) @[Cat.scala 29:58]
|
|
way_status <= _T_5115 @[el2_ifu_mem_ctl.scala 716:16]
|
|
node _T_5116 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 717:61]
|
|
node _T_5117 = and(_T_5116, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 717:82]
|
|
node _T_5118 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 718:23]
|
|
node _T_5119 = bits(ifu_ic_rw_int_addr, 11, 5) @[el2_ifu_mem_ctl.scala 718:89]
|
|
node ifu_ic_rw_int_addr_w_debug = mux(_T_5117, _T_5118, _T_5119) @[el2_ifu_mem_ctl.scala 717:41]
|
|
reg _T_5120 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 720:14]
|
|
_T_5120 <= ifu_ic_rw_int_addr_w_debug @[el2_ifu_mem_ctl.scala 720:14]
|
|
ifu_ic_rw_int_addr_ff <= _T_5120 @[el2_ifu_mem_ctl.scala 719:27]
|
|
wire ifu_tag_wren : UInt<2>
|
|
ifu_tag_wren <= UInt<1>("h00")
|
|
wire ic_debug_tag_wr_en : UInt<2>
|
|
ic_debug_tag_wr_en <= UInt<1>("h00")
|
|
node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[el2_ifu_mem_ctl.scala 724:45]
|
|
reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 726:14]
|
|
ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[el2_ifu_mem_ctl.scala 726:14]
|
|
node _T_5121 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 728:50]
|
|
node _T_5122 = bits(io.ic_debug_wr_data, 0, 0) @[el2_ifu_mem_ctl.scala 728:94]
|
|
node ic_valid_w_debug = mux(_T_5121, _T_5122, ic_valid) @[el2_ifu_mem_ctl.scala 728:31]
|
|
reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 730:14]
|
|
ic_valid_ff <= ic_valid_w_debug @[el2_ifu_mem_ctl.scala 730:14]
|
|
node _T_5123 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35]
|
|
node _T_5124 = eq(_T_5123, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 734:82]
|
|
node _T_5125 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 734:108]
|
|
node _T_5126 = and(_T_5124, _T_5125) @[el2_ifu_mem_ctl.scala 734:91]
|
|
node _T_5127 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27]
|
|
node _T_5128 = eq(_T_5127, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 735:74]
|
|
node _T_5129 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 735:101]
|
|
node _T_5130 = and(_T_5128, _T_5129) @[el2_ifu_mem_ctl.scala 735:83]
|
|
node _T_5131 = or(_T_5126, _T_5130) @[el2_ifu_mem_ctl.scala 734:113]
|
|
node _T_5132 = or(_T_5131, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106]
|
|
node _T_5133 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35]
|
|
node _T_5134 = eq(_T_5133, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 734:82]
|
|
node _T_5135 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 734:108]
|
|
node _T_5136 = and(_T_5134, _T_5135) @[el2_ifu_mem_ctl.scala 734:91]
|
|
node _T_5137 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27]
|
|
node _T_5138 = eq(_T_5137, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 735:74]
|
|
node _T_5139 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 735:101]
|
|
node _T_5140 = and(_T_5138, _T_5139) @[el2_ifu_mem_ctl.scala 735:83]
|
|
node _T_5141 = or(_T_5136, _T_5140) @[el2_ifu_mem_ctl.scala 734:113]
|
|
node _T_5142 = or(_T_5141, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106]
|
|
node tag_valid_clken_0 = cat(_T_5132, _T_5142) @[Cat.scala 29:58]
|
|
node _T_5143 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35]
|
|
node _T_5144 = eq(_T_5143, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 734:82]
|
|
node _T_5145 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 734:108]
|
|
node _T_5146 = and(_T_5144, _T_5145) @[el2_ifu_mem_ctl.scala 734:91]
|
|
node _T_5147 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27]
|
|
node _T_5148 = eq(_T_5147, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 735:74]
|
|
node _T_5149 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 735:101]
|
|
node _T_5150 = and(_T_5148, _T_5149) @[el2_ifu_mem_ctl.scala 735:83]
|
|
node _T_5151 = or(_T_5146, _T_5150) @[el2_ifu_mem_ctl.scala 734:113]
|
|
node _T_5152 = or(_T_5151, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106]
|
|
node _T_5153 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35]
|
|
node _T_5154 = eq(_T_5153, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 734:82]
|
|
node _T_5155 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 734:108]
|
|
node _T_5156 = and(_T_5154, _T_5155) @[el2_ifu_mem_ctl.scala 734:91]
|
|
node _T_5157 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27]
|
|
node _T_5158 = eq(_T_5157, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 735:74]
|
|
node _T_5159 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 735:101]
|
|
node _T_5160 = and(_T_5158, _T_5159) @[el2_ifu_mem_ctl.scala 735:83]
|
|
node _T_5161 = or(_T_5156, _T_5160) @[el2_ifu_mem_ctl.scala 734:113]
|
|
node _T_5162 = or(_T_5161, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106]
|
|
node tag_valid_clken_1 = cat(_T_5152, _T_5162) @[Cat.scala 29:58]
|
|
node _T_5163 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35]
|
|
node _T_5164 = eq(_T_5163, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 734:82]
|
|
node _T_5165 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 734:108]
|
|
node _T_5166 = and(_T_5164, _T_5165) @[el2_ifu_mem_ctl.scala 734:91]
|
|
node _T_5167 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27]
|
|
node _T_5168 = eq(_T_5167, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 735:74]
|
|
node _T_5169 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 735:101]
|
|
node _T_5170 = and(_T_5168, _T_5169) @[el2_ifu_mem_ctl.scala 735:83]
|
|
node _T_5171 = or(_T_5166, _T_5170) @[el2_ifu_mem_ctl.scala 734:113]
|
|
node _T_5172 = or(_T_5171, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106]
|
|
node _T_5173 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35]
|
|
node _T_5174 = eq(_T_5173, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 734:82]
|
|
node _T_5175 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 734:108]
|
|
node _T_5176 = and(_T_5174, _T_5175) @[el2_ifu_mem_ctl.scala 734:91]
|
|
node _T_5177 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27]
|
|
node _T_5178 = eq(_T_5177, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 735:74]
|
|
node _T_5179 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 735:101]
|
|
node _T_5180 = and(_T_5178, _T_5179) @[el2_ifu_mem_ctl.scala 735:83]
|
|
node _T_5181 = or(_T_5176, _T_5180) @[el2_ifu_mem_ctl.scala 734:113]
|
|
node _T_5182 = or(_T_5181, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106]
|
|
node tag_valid_clken_2 = cat(_T_5172, _T_5182) @[Cat.scala 29:58]
|
|
node _T_5183 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35]
|
|
node _T_5184 = eq(_T_5183, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 734:82]
|
|
node _T_5185 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 734:108]
|
|
node _T_5186 = and(_T_5184, _T_5185) @[el2_ifu_mem_ctl.scala 734:91]
|
|
node _T_5187 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27]
|
|
node _T_5188 = eq(_T_5187, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 735:74]
|
|
node _T_5189 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 735:101]
|
|
node _T_5190 = and(_T_5188, _T_5189) @[el2_ifu_mem_ctl.scala 735:83]
|
|
node _T_5191 = or(_T_5186, _T_5190) @[el2_ifu_mem_ctl.scala 734:113]
|
|
node _T_5192 = or(_T_5191, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106]
|
|
node _T_5193 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35]
|
|
node _T_5194 = eq(_T_5193, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 734:82]
|
|
node _T_5195 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 734:108]
|
|
node _T_5196 = and(_T_5194, _T_5195) @[el2_ifu_mem_ctl.scala 734:91]
|
|
node _T_5197 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27]
|
|
node _T_5198 = eq(_T_5197, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 735:74]
|
|
node _T_5199 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 735:101]
|
|
node _T_5200 = and(_T_5198, _T_5199) @[el2_ifu_mem_ctl.scala 735:83]
|
|
node _T_5201 = or(_T_5196, _T_5200) @[el2_ifu_mem_ctl.scala 734:113]
|
|
node _T_5202 = or(_T_5201, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106]
|
|
node tag_valid_clken_3 = cat(_T_5192, _T_5202) @[Cat.scala 29:58]
|
|
wire ic_tag_valid_out : UInt<1>[128][2] @[el2_ifu_mem_ctl.scala 738:32]
|
|
node _T_5203 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5204 = eq(_T_5203, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5205 = and(ic_valid_ff, _T_5204) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5206 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5207 = and(_T_5205, _T_5206) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5208 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5209 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5210 = and(_T_5208, _T_5209) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5211 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5212 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5213 = and(_T_5211, _T_5212) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5214 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5215 = and(_T_5213, _T_5214) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5216 = or(_T_5210, _T_5215) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5217 = bits(_T_5216, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5218 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5217 : @[Reg.scala 28:19]
|
|
_T_5218 <= _T_5207 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][0] <= _T_5218 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5219 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5220 = eq(_T_5219, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5221 = and(ic_valid_ff, _T_5220) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5222 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5223 = and(_T_5221, _T_5222) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5224 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5225 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5226 = and(_T_5224, _T_5225) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5227 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5228 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5229 = and(_T_5227, _T_5228) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5230 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5231 = and(_T_5229, _T_5230) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5232 = or(_T_5226, _T_5231) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5233 = bits(_T_5232, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5234 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5233 : @[Reg.scala 28:19]
|
|
_T_5234 <= _T_5223 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][1] <= _T_5234 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5235 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5236 = eq(_T_5235, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5237 = and(ic_valid_ff, _T_5236) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5238 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5239 = and(_T_5237, _T_5238) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5240 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5241 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5242 = and(_T_5240, _T_5241) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5243 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5244 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5245 = and(_T_5243, _T_5244) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5246 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5247 = and(_T_5245, _T_5246) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5248 = or(_T_5242, _T_5247) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5249 = bits(_T_5248, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5250 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5249 : @[Reg.scala 28:19]
|
|
_T_5250 <= _T_5239 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][2] <= _T_5250 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5251 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5252 = eq(_T_5251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5253 = and(ic_valid_ff, _T_5252) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5254 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5255 = and(_T_5253, _T_5254) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5256 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5257 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5258 = and(_T_5256, _T_5257) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5259 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5260 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5261 = and(_T_5259, _T_5260) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5262 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5263 = and(_T_5261, _T_5262) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5264 = or(_T_5258, _T_5263) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5265 = bits(_T_5264, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5266 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5265 : @[Reg.scala 28:19]
|
|
_T_5266 <= _T_5255 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][3] <= _T_5266 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5267 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5268 = eq(_T_5267, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5269 = and(ic_valid_ff, _T_5268) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5270 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5271 = and(_T_5269, _T_5270) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5272 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5273 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5274 = and(_T_5272, _T_5273) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5275 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5276 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5277 = and(_T_5275, _T_5276) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5278 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5279 = and(_T_5277, _T_5278) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5280 = or(_T_5274, _T_5279) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5281 = bits(_T_5280, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5282 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5281 : @[Reg.scala 28:19]
|
|
_T_5282 <= _T_5271 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][4] <= _T_5282 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5283 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5284 = eq(_T_5283, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5285 = and(ic_valid_ff, _T_5284) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5286 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5287 = and(_T_5285, _T_5286) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5288 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5289 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5290 = and(_T_5288, _T_5289) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5291 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5292 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5293 = and(_T_5291, _T_5292) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5294 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5295 = and(_T_5293, _T_5294) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5296 = or(_T_5290, _T_5295) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5297 = bits(_T_5296, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5298 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5297 : @[Reg.scala 28:19]
|
|
_T_5298 <= _T_5287 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][5] <= _T_5298 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5299 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5300 = eq(_T_5299, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5301 = and(ic_valid_ff, _T_5300) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5302 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5303 = and(_T_5301, _T_5302) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5304 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5305 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5306 = and(_T_5304, _T_5305) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5307 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5308 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5309 = and(_T_5307, _T_5308) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5310 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5311 = and(_T_5309, _T_5310) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5312 = or(_T_5306, _T_5311) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5313 = bits(_T_5312, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5314 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5313 : @[Reg.scala 28:19]
|
|
_T_5314 <= _T_5303 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][6] <= _T_5314 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5315 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5316 = eq(_T_5315, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5317 = and(ic_valid_ff, _T_5316) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5318 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5319 = and(_T_5317, _T_5318) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5320 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5321 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5322 = and(_T_5320, _T_5321) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5323 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5324 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5325 = and(_T_5323, _T_5324) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5326 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5327 = and(_T_5325, _T_5326) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5328 = or(_T_5322, _T_5327) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5329 = bits(_T_5328, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5330 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5329 : @[Reg.scala 28:19]
|
|
_T_5330 <= _T_5319 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][7] <= _T_5330 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5331 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5332 = eq(_T_5331, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5333 = and(ic_valid_ff, _T_5332) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5334 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5335 = and(_T_5333, _T_5334) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5336 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5337 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5338 = and(_T_5336, _T_5337) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5339 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5340 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5341 = and(_T_5339, _T_5340) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5342 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5343 = and(_T_5341, _T_5342) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5344 = or(_T_5338, _T_5343) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5345 = bits(_T_5344, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5346 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5345 : @[Reg.scala 28:19]
|
|
_T_5346 <= _T_5335 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][8] <= _T_5346 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5347 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5348 = eq(_T_5347, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5349 = and(ic_valid_ff, _T_5348) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5350 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5351 = and(_T_5349, _T_5350) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5352 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5353 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5354 = and(_T_5352, _T_5353) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5355 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5356 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5357 = and(_T_5355, _T_5356) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5358 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5359 = and(_T_5357, _T_5358) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5360 = or(_T_5354, _T_5359) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5361 = bits(_T_5360, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5362 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5361 : @[Reg.scala 28:19]
|
|
_T_5362 <= _T_5351 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][9] <= _T_5362 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5363 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5364 = eq(_T_5363, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5365 = and(ic_valid_ff, _T_5364) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5366 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5367 = and(_T_5365, _T_5366) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5368 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5369 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5370 = and(_T_5368, _T_5369) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5371 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5372 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5373 = and(_T_5371, _T_5372) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5374 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5375 = and(_T_5373, _T_5374) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5376 = or(_T_5370, _T_5375) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5377 = bits(_T_5376, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5378 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5377 : @[Reg.scala 28:19]
|
|
_T_5378 <= _T_5367 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][10] <= _T_5378 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5379 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5380 = eq(_T_5379, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5381 = and(ic_valid_ff, _T_5380) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5382 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5383 = and(_T_5381, _T_5382) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5384 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5385 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5386 = and(_T_5384, _T_5385) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5387 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5388 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5389 = and(_T_5387, _T_5388) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5390 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5391 = and(_T_5389, _T_5390) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5392 = or(_T_5386, _T_5391) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5393 = bits(_T_5392, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5394 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5393 : @[Reg.scala 28:19]
|
|
_T_5394 <= _T_5383 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][11] <= _T_5394 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5395 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5396 = eq(_T_5395, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5397 = and(ic_valid_ff, _T_5396) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5398 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5399 = and(_T_5397, _T_5398) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5400 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5401 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5402 = and(_T_5400, _T_5401) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5403 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5404 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5405 = and(_T_5403, _T_5404) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5406 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5407 = and(_T_5405, _T_5406) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5408 = or(_T_5402, _T_5407) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5409 = bits(_T_5408, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5410 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5409 : @[Reg.scala 28:19]
|
|
_T_5410 <= _T_5399 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][12] <= _T_5410 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5411 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5412 = eq(_T_5411, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5413 = and(ic_valid_ff, _T_5412) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5414 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5415 = and(_T_5413, _T_5414) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5416 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5417 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5418 = and(_T_5416, _T_5417) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5419 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5420 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5421 = and(_T_5419, _T_5420) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5422 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5423 = and(_T_5421, _T_5422) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5424 = or(_T_5418, _T_5423) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5425 = bits(_T_5424, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5426 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5425 : @[Reg.scala 28:19]
|
|
_T_5426 <= _T_5415 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][13] <= _T_5426 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5427 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5428 = eq(_T_5427, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5429 = and(ic_valid_ff, _T_5428) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5430 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5431 = and(_T_5429, _T_5430) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5432 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5433 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5434 = and(_T_5432, _T_5433) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5435 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5436 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5437 = and(_T_5435, _T_5436) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5438 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5439 = and(_T_5437, _T_5438) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5440 = or(_T_5434, _T_5439) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5441 = bits(_T_5440, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5442 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5441 : @[Reg.scala 28:19]
|
|
_T_5442 <= _T_5431 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][14] <= _T_5442 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5443 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5444 = eq(_T_5443, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5445 = and(ic_valid_ff, _T_5444) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5446 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5447 = and(_T_5445, _T_5446) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5448 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5449 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5450 = and(_T_5448, _T_5449) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5451 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5452 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5453 = and(_T_5451, _T_5452) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5454 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5455 = and(_T_5453, _T_5454) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5456 = or(_T_5450, _T_5455) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5457 = bits(_T_5456, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5458 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5457 : @[Reg.scala 28:19]
|
|
_T_5458 <= _T_5447 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][15] <= _T_5458 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5459 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5460 = eq(_T_5459, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5461 = and(ic_valid_ff, _T_5460) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5462 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5463 = and(_T_5461, _T_5462) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5464 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5465 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5466 = and(_T_5464, _T_5465) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5467 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5468 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5469 = and(_T_5467, _T_5468) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5470 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5471 = and(_T_5469, _T_5470) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5472 = or(_T_5466, _T_5471) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5473 = bits(_T_5472, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5474 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5473 : @[Reg.scala 28:19]
|
|
_T_5474 <= _T_5463 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][16] <= _T_5474 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5475 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5476 = eq(_T_5475, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5477 = and(ic_valid_ff, _T_5476) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5478 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5479 = and(_T_5477, _T_5478) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5480 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5481 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5482 = and(_T_5480, _T_5481) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5483 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5484 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5485 = and(_T_5483, _T_5484) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5486 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5487 = and(_T_5485, _T_5486) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5488 = or(_T_5482, _T_5487) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5489 = bits(_T_5488, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5490 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5489 : @[Reg.scala 28:19]
|
|
_T_5490 <= _T_5479 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][17] <= _T_5490 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5491 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5492 = eq(_T_5491, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5493 = and(ic_valid_ff, _T_5492) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5494 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5495 = and(_T_5493, _T_5494) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5496 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5497 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5498 = and(_T_5496, _T_5497) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5499 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5500 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5501 = and(_T_5499, _T_5500) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5502 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5503 = and(_T_5501, _T_5502) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5504 = or(_T_5498, _T_5503) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5505 = bits(_T_5504, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5506 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5505 : @[Reg.scala 28:19]
|
|
_T_5506 <= _T_5495 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][18] <= _T_5506 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5507 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5508 = eq(_T_5507, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5509 = and(ic_valid_ff, _T_5508) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5510 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5511 = and(_T_5509, _T_5510) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5512 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5513 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5514 = and(_T_5512, _T_5513) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5515 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5516 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5517 = and(_T_5515, _T_5516) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5518 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5519 = and(_T_5517, _T_5518) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5520 = or(_T_5514, _T_5519) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5521 = bits(_T_5520, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5522 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5521 : @[Reg.scala 28:19]
|
|
_T_5522 <= _T_5511 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][19] <= _T_5522 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5523 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5524 = eq(_T_5523, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5525 = and(ic_valid_ff, _T_5524) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5526 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5527 = and(_T_5525, _T_5526) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5528 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5529 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5530 = and(_T_5528, _T_5529) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5531 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5532 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5533 = and(_T_5531, _T_5532) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5534 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5535 = and(_T_5533, _T_5534) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5536 = or(_T_5530, _T_5535) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5537 = bits(_T_5536, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5538 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5537 : @[Reg.scala 28:19]
|
|
_T_5538 <= _T_5527 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][20] <= _T_5538 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5539 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5540 = eq(_T_5539, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5541 = and(ic_valid_ff, _T_5540) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5542 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5543 = and(_T_5541, _T_5542) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5544 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5545 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5546 = and(_T_5544, _T_5545) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5547 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5548 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5549 = and(_T_5547, _T_5548) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5550 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5551 = and(_T_5549, _T_5550) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5552 = or(_T_5546, _T_5551) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5553 = bits(_T_5552, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5554 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5553 : @[Reg.scala 28:19]
|
|
_T_5554 <= _T_5543 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][21] <= _T_5554 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5555 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5556 = eq(_T_5555, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5557 = and(ic_valid_ff, _T_5556) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5558 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5559 = and(_T_5557, _T_5558) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5560 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5561 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5562 = and(_T_5560, _T_5561) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5563 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5564 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5565 = and(_T_5563, _T_5564) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5566 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5567 = and(_T_5565, _T_5566) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5568 = or(_T_5562, _T_5567) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5569 = bits(_T_5568, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5570 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5569 : @[Reg.scala 28:19]
|
|
_T_5570 <= _T_5559 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][22] <= _T_5570 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5571 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5572 = eq(_T_5571, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5573 = and(ic_valid_ff, _T_5572) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5574 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5575 = and(_T_5573, _T_5574) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5576 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5577 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5578 = and(_T_5576, _T_5577) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5579 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5580 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5581 = and(_T_5579, _T_5580) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5582 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5583 = and(_T_5581, _T_5582) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5584 = or(_T_5578, _T_5583) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5585 = bits(_T_5584, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5586 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5585 : @[Reg.scala 28:19]
|
|
_T_5586 <= _T_5575 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][23] <= _T_5586 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5587 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5588 = eq(_T_5587, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5589 = and(ic_valid_ff, _T_5588) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5590 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5591 = and(_T_5589, _T_5590) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5592 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5593 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5594 = and(_T_5592, _T_5593) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5595 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5596 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5597 = and(_T_5595, _T_5596) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5598 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5599 = and(_T_5597, _T_5598) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5600 = or(_T_5594, _T_5599) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5601 = bits(_T_5600, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5602 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5601 : @[Reg.scala 28:19]
|
|
_T_5602 <= _T_5591 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][24] <= _T_5602 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5603 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5604 = eq(_T_5603, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5605 = and(ic_valid_ff, _T_5604) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5606 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5607 = and(_T_5605, _T_5606) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5608 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5609 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5610 = and(_T_5608, _T_5609) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5611 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5612 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5613 = and(_T_5611, _T_5612) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5614 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5615 = and(_T_5613, _T_5614) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5616 = or(_T_5610, _T_5615) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5617 = bits(_T_5616, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5618 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5617 : @[Reg.scala 28:19]
|
|
_T_5618 <= _T_5607 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][25] <= _T_5618 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5619 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5620 = eq(_T_5619, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5621 = and(ic_valid_ff, _T_5620) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5622 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5623 = and(_T_5621, _T_5622) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5624 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5625 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5626 = and(_T_5624, _T_5625) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5627 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5628 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5629 = and(_T_5627, _T_5628) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5630 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5631 = and(_T_5629, _T_5630) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5632 = or(_T_5626, _T_5631) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5633 = bits(_T_5632, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5634 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5633 : @[Reg.scala 28:19]
|
|
_T_5634 <= _T_5623 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][26] <= _T_5634 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5635 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5636 = eq(_T_5635, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5637 = and(ic_valid_ff, _T_5636) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5638 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5639 = and(_T_5637, _T_5638) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5640 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5641 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5642 = and(_T_5640, _T_5641) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5643 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5644 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5645 = and(_T_5643, _T_5644) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5646 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5647 = and(_T_5645, _T_5646) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5648 = or(_T_5642, _T_5647) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5649 = bits(_T_5648, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5650 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5649 : @[Reg.scala 28:19]
|
|
_T_5650 <= _T_5639 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][27] <= _T_5650 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5651 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5652 = eq(_T_5651, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5653 = and(ic_valid_ff, _T_5652) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5654 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5655 = and(_T_5653, _T_5654) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5656 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5657 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5658 = and(_T_5656, _T_5657) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5659 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5660 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5661 = and(_T_5659, _T_5660) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5662 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5663 = and(_T_5661, _T_5662) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5664 = or(_T_5658, _T_5663) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5665 = bits(_T_5664, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5666 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5665 : @[Reg.scala 28:19]
|
|
_T_5666 <= _T_5655 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][28] <= _T_5666 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5667 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5668 = eq(_T_5667, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5669 = and(ic_valid_ff, _T_5668) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5670 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5671 = and(_T_5669, _T_5670) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5672 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5673 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5674 = and(_T_5672, _T_5673) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5675 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5676 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5677 = and(_T_5675, _T_5676) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5678 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5679 = and(_T_5677, _T_5678) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5680 = or(_T_5674, _T_5679) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5681 = bits(_T_5680, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5682 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5681 : @[Reg.scala 28:19]
|
|
_T_5682 <= _T_5671 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][29] <= _T_5682 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5683 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5684 = eq(_T_5683, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5685 = and(ic_valid_ff, _T_5684) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5686 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5687 = and(_T_5685, _T_5686) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5688 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5689 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5690 = and(_T_5688, _T_5689) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5691 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5692 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5693 = and(_T_5691, _T_5692) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5694 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5695 = and(_T_5693, _T_5694) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5696 = or(_T_5690, _T_5695) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5697 = bits(_T_5696, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5698 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5697 : @[Reg.scala 28:19]
|
|
_T_5698 <= _T_5687 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][30] <= _T_5698 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5699 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5700 = eq(_T_5699, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5701 = and(ic_valid_ff, _T_5700) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5702 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5703 = and(_T_5701, _T_5702) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5704 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5705 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5706 = and(_T_5704, _T_5705) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5707 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5708 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5709 = and(_T_5707, _T_5708) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5710 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5711 = and(_T_5709, _T_5710) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5712 = or(_T_5706, _T_5711) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5713 = bits(_T_5712, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5714 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5713 : @[Reg.scala 28:19]
|
|
_T_5714 <= _T_5703 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][31] <= _T_5714 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5715 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5716 = eq(_T_5715, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5717 = and(ic_valid_ff, _T_5716) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5718 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5719 = and(_T_5717, _T_5718) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5720 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5721 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5722 = and(_T_5720, _T_5721) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5723 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5724 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5725 = and(_T_5723, _T_5724) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5726 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5727 = and(_T_5725, _T_5726) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5728 = or(_T_5722, _T_5727) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5729 = bits(_T_5728, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5730 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5729 : @[Reg.scala 28:19]
|
|
_T_5730 <= _T_5719 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][0] <= _T_5730 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5731 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5732 = eq(_T_5731, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5733 = and(ic_valid_ff, _T_5732) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5734 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5735 = and(_T_5733, _T_5734) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5736 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5737 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5738 = and(_T_5736, _T_5737) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5739 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5740 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5741 = and(_T_5739, _T_5740) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5742 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5743 = and(_T_5741, _T_5742) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5744 = or(_T_5738, _T_5743) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5745 = bits(_T_5744, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5746 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5745 : @[Reg.scala 28:19]
|
|
_T_5746 <= _T_5735 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][1] <= _T_5746 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5747 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5748 = eq(_T_5747, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5749 = and(ic_valid_ff, _T_5748) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5750 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5751 = and(_T_5749, _T_5750) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5752 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5753 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5754 = and(_T_5752, _T_5753) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5755 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5756 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5757 = and(_T_5755, _T_5756) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5758 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5759 = and(_T_5757, _T_5758) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5760 = or(_T_5754, _T_5759) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5761 = bits(_T_5760, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5762 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5761 : @[Reg.scala 28:19]
|
|
_T_5762 <= _T_5751 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][2] <= _T_5762 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5763 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5764 = eq(_T_5763, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5765 = and(ic_valid_ff, _T_5764) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5766 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5767 = and(_T_5765, _T_5766) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5768 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5769 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5770 = and(_T_5768, _T_5769) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5771 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5772 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5773 = and(_T_5771, _T_5772) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5774 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5775 = and(_T_5773, _T_5774) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5776 = or(_T_5770, _T_5775) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5777 = bits(_T_5776, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5778 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5777 : @[Reg.scala 28:19]
|
|
_T_5778 <= _T_5767 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][3] <= _T_5778 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5779 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5780 = eq(_T_5779, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5781 = and(ic_valid_ff, _T_5780) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5782 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5783 = and(_T_5781, _T_5782) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5784 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5785 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5786 = and(_T_5784, _T_5785) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5787 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5788 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5789 = and(_T_5787, _T_5788) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5790 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5791 = and(_T_5789, _T_5790) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5792 = or(_T_5786, _T_5791) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5793 = bits(_T_5792, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5794 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5793 : @[Reg.scala 28:19]
|
|
_T_5794 <= _T_5783 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][4] <= _T_5794 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5795 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5796 = eq(_T_5795, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5797 = and(ic_valid_ff, _T_5796) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5799 = and(_T_5797, _T_5798) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5800 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5801 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5802 = and(_T_5800, _T_5801) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5803 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5804 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5805 = and(_T_5803, _T_5804) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5806 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5807 = and(_T_5805, _T_5806) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5808 = or(_T_5802, _T_5807) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5809 = bits(_T_5808, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5810 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5809 : @[Reg.scala 28:19]
|
|
_T_5810 <= _T_5799 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][5] <= _T_5810 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5811 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5812 = eq(_T_5811, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5813 = and(ic_valid_ff, _T_5812) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5814 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5815 = and(_T_5813, _T_5814) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5816 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5817 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5818 = and(_T_5816, _T_5817) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5819 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5820 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5821 = and(_T_5819, _T_5820) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5822 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5823 = and(_T_5821, _T_5822) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5824 = or(_T_5818, _T_5823) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5825 = bits(_T_5824, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5826 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5825 : @[Reg.scala 28:19]
|
|
_T_5826 <= _T_5815 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][6] <= _T_5826 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5827 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5828 = eq(_T_5827, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5829 = and(ic_valid_ff, _T_5828) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5830 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5831 = and(_T_5829, _T_5830) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5832 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5833 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5834 = and(_T_5832, _T_5833) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5835 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5836 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5837 = and(_T_5835, _T_5836) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5838 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5839 = and(_T_5837, _T_5838) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5840 = or(_T_5834, _T_5839) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5841 = bits(_T_5840, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5842 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5841 : @[Reg.scala 28:19]
|
|
_T_5842 <= _T_5831 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][7] <= _T_5842 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5843 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5844 = eq(_T_5843, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5845 = and(ic_valid_ff, _T_5844) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5846 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5847 = and(_T_5845, _T_5846) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5848 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5849 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5850 = and(_T_5848, _T_5849) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5851 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5852 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5853 = and(_T_5851, _T_5852) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5854 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5855 = and(_T_5853, _T_5854) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5856 = or(_T_5850, _T_5855) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5857 = bits(_T_5856, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5858 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5857 : @[Reg.scala 28:19]
|
|
_T_5858 <= _T_5847 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][8] <= _T_5858 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5859 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5860 = eq(_T_5859, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5861 = and(ic_valid_ff, _T_5860) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5862 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5863 = and(_T_5861, _T_5862) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5864 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5865 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5866 = and(_T_5864, _T_5865) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5867 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5868 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5869 = and(_T_5867, _T_5868) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5870 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5871 = and(_T_5869, _T_5870) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5872 = or(_T_5866, _T_5871) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5873 = bits(_T_5872, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5874 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5873 : @[Reg.scala 28:19]
|
|
_T_5874 <= _T_5863 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][9] <= _T_5874 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5875 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5876 = eq(_T_5875, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5877 = and(ic_valid_ff, _T_5876) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5878 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5879 = and(_T_5877, _T_5878) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5880 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5881 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5882 = and(_T_5880, _T_5881) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5883 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5884 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5885 = and(_T_5883, _T_5884) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5886 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5887 = and(_T_5885, _T_5886) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5888 = or(_T_5882, _T_5887) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5889 = bits(_T_5888, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5890 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5889 : @[Reg.scala 28:19]
|
|
_T_5890 <= _T_5879 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][10] <= _T_5890 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5891 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5892 = eq(_T_5891, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5893 = and(ic_valid_ff, _T_5892) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5894 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5895 = and(_T_5893, _T_5894) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5896 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5897 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5898 = and(_T_5896, _T_5897) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5899 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5900 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5901 = and(_T_5899, _T_5900) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5902 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5903 = and(_T_5901, _T_5902) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5904 = or(_T_5898, _T_5903) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5905 = bits(_T_5904, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5906 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5905 : @[Reg.scala 28:19]
|
|
_T_5906 <= _T_5895 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][11] <= _T_5906 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5907 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5908 = eq(_T_5907, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5909 = and(ic_valid_ff, _T_5908) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5910 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5911 = and(_T_5909, _T_5910) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5912 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5913 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5914 = and(_T_5912, _T_5913) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5915 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5916 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5917 = and(_T_5915, _T_5916) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5918 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5919 = and(_T_5917, _T_5918) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5920 = or(_T_5914, _T_5919) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5921 = bits(_T_5920, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5922 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5921 : @[Reg.scala 28:19]
|
|
_T_5922 <= _T_5911 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][12] <= _T_5922 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5923 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5924 = eq(_T_5923, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5925 = and(ic_valid_ff, _T_5924) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5926 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5927 = and(_T_5925, _T_5926) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5928 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5929 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5930 = and(_T_5928, _T_5929) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5931 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5932 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5933 = and(_T_5931, _T_5932) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5934 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5935 = and(_T_5933, _T_5934) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5936 = or(_T_5930, _T_5935) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5937 = bits(_T_5936, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5938 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5937 : @[Reg.scala 28:19]
|
|
_T_5938 <= _T_5927 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][13] <= _T_5938 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5939 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5940 = eq(_T_5939, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5941 = and(ic_valid_ff, _T_5940) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5942 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5943 = and(_T_5941, _T_5942) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5944 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5945 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5946 = and(_T_5944, _T_5945) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5947 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5948 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5949 = and(_T_5947, _T_5948) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5950 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5951 = and(_T_5949, _T_5950) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5952 = or(_T_5946, _T_5951) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5953 = bits(_T_5952, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5954 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5953 : @[Reg.scala 28:19]
|
|
_T_5954 <= _T_5943 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][14] <= _T_5954 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5955 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5956 = eq(_T_5955, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5957 = and(ic_valid_ff, _T_5956) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5958 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5959 = and(_T_5957, _T_5958) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5960 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5961 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5962 = and(_T_5960, _T_5961) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5963 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5964 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5965 = and(_T_5963, _T_5964) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5966 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5967 = and(_T_5965, _T_5966) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5968 = or(_T_5962, _T_5967) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5969 = bits(_T_5968, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5970 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5969 : @[Reg.scala 28:19]
|
|
_T_5970 <= _T_5959 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][15] <= _T_5970 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5971 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5972 = eq(_T_5971, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5973 = and(ic_valid_ff, _T_5972) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5974 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5975 = and(_T_5973, _T_5974) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5976 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5977 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5978 = and(_T_5976, _T_5977) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5979 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5980 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5981 = and(_T_5979, _T_5980) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5982 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5983 = and(_T_5981, _T_5982) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_5984 = or(_T_5978, _T_5983) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_5985 = bits(_T_5984, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_5986 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5985 : @[Reg.scala 28:19]
|
|
_T_5986 <= _T_5975 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][16] <= _T_5986 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_5987 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_5988 = eq(_T_5987, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_5989 = and(ic_valid_ff, _T_5988) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_5990 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_5991 = and(_T_5989, _T_5990) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_5992 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_5993 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_5994 = and(_T_5992, _T_5993) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_5995 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_5996 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_5997 = and(_T_5995, _T_5996) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_5998 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_5999 = and(_T_5997, _T_5998) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6000 = or(_T_5994, _T_5999) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6001 = bits(_T_6000, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6002 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6001 : @[Reg.scala 28:19]
|
|
_T_6002 <= _T_5991 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][17] <= _T_6002 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6003 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6004 = eq(_T_6003, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6005 = and(ic_valid_ff, _T_6004) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6006 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6007 = and(_T_6005, _T_6006) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6008 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6009 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6010 = and(_T_6008, _T_6009) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6011 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6012 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6013 = and(_T_6011, _T_6012) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6014 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6015 = and(_T_6013, _T_6014) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6016 = or(_T_6010, _T_6015) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6017 = bits(_T_6016, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6018 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6017 : @[Reg.scala 28:19]
|
|
_T_6018 <= _T_6007 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][18] <= _T_6018 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6019 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6020 = eq(_T_6019, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6021 = and(ic_valid_ff, _T_6020) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6022 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6023 = and(_T_6021, _T_6022) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6024 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6025 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6026 = and(_T_6024, _T_6025) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6027 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6028 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6029 = and(_T_6027, _T_6028) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6030 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6031 = and(_T_6029, _T_6030) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6032 = or(_T_6026, _T_6031) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6033 = bits(_T_6032, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6034 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6033 : @[Reg.scala 28:19]
|
|
_T_6034 <= _T_6023 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][19] <= _T_6034 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6035 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6036 = eq(_T_6035, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6037 = and(ic_valid_ff, _T_6036) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6038 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6039 = and(_T_6037, _T_6038) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6040 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6041 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6042 = and(_T_6040, _T_6041) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6043 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6044 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6045 = and(_T_6043, _T_6044) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6046 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6047 = and(_T_6045, _T_6046) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6048 = or(_T_6042, _T_6047) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6049 = bits(_T_6048, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6050 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6049 : @[Reg.scala 28:19]
|
|
_T_6050 <= _T_6039 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][20] <= _T_6050 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6051 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6052 = eq(_T_6051, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6053 = and(ic_valid_ff, _T_6052) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6054 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6055 = and(_T_6053, _T_6054) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6056 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6057 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6058 = and(_T_6056, _T_6057) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6059 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6060 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6061 = and(_T_6059, _T_6060) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6062 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6063 = and(_T_6061, _T_6062) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6064 = or(_T_6058, _T_6063) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6065 = bits(_T_6064, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6066 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6065 : @[Reg.scala 28:19]
|
|
_T_6066 <= _T_6055 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][21] <= _T_6066 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6067 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6068 = eq(_T_6067, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6069 = and(ic_valid_ff, _T_6068) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6070 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6071 = and(_T_6069, _T_6070) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6072 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6073 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6074 = and(_T_6072, _T_6073) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6075 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6076 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6077 = and(_T_6075, _T_6076) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6078 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6079 = and(_T_6077, _T_6078) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6080 = or(_T_6074, _T_6079) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6081 = bits(_T_6080, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6082 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6081 : @[Reg.scala 28:19]
|
|
_T_6082 <= _T_6071 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][22] <= _T_6082 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6083 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6084 = eq(_T_6083, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6085 = and(ic_valid_ff, _T_6084) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6086 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6087 = and(_T_6085, _T_6086) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6088 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6089 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6090 = and(_T_6088, _T_6089) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6091 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6092 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6093 = and(_T_6091, _T_6092) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6094 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6095 = and(_T_6093, _T_6094) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6096 = or(_T_6090, _T_6095) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6097 = bits(_T_6096, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6098 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6097 : @[Reg.scala 28:19]
|
|
_T_6098 <= _T_6087 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][23] <= _T_6098 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6099 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6100 = eq(_T_6099, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6101 = and(ic_valid_ff, _T_6100) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6102 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6103 = and(_T_6101, _T_6102) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6104 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6105 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6106 = and(_T_6104, _T_6105) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6107 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6108 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6109 = and(_T_6107, _T_6108) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6110 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6111 = and(_T_6109, _T_6110) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6112 = or(_T_6106, _T_6111) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6113 = bits(_T_6112, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6114 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6113 : @[Reg.scala 28:19]
|
|
_T_6114 <= _T_6103 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][24] <= _T_6114 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6115 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6116 = eq(_T_6115, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6117 = and(ic_valid_ff, _T_6116) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6118 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6119 = and(_T_6117, _T_6118) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6120 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6121 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6122 = and(_T_6120, _T_6121) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6123 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6124 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6125 = and(_T_6123, _T_6124) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6126 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6127 = and(_T_6125, _T_6126) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6128 = or(_T_6122, _T_6127) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6129 = bits(_T_6128, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6130 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6129 : @[Reg.scala 28:19]
|
|
_T_6130 <= _T_6119 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][25] <= _T_6130 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6131 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6132 = eq(_T_6131, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6133 = and(ic_valid_ff, _T_6132) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6134 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6135 = and(_T_6133, _T_6134) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6136 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6137 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6138 = and(_T_6136, _T_6137) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6139 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6140 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6141 = and(_T_6139, _T_6140) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6142 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6143 = and(_T_6141, _T_6142) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6144 = or(_T_6138, _T_6143) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6145 = bits(_T_6144, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6146 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6145 : @[Reg.scala 28:19]
|
|
_T_6146 <= _T_6135 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][26] <= _T_6146 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6147 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6148 = eq(_T_6147, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6149 = and(ic_valid_ff, _T_6148) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6150 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6151 = and(_T_6149, _T_6150) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6152 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6153 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6154 = and(_T_6152, _T_6153) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6155 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6156 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6157 = and(_T_6155, _T_6156) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6158 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6159 = and(_T_6157, _T_6158) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6160 = or(_T_6154, _T_6159) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6161 = bits(_T_6160, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6162 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6161 : @[Reg.scala 28:19]
|
|
_T_6162 <= _T_6151 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][27] <= _T_6162 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6163 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6164 = eq(_T_6163, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6165 = and(ic_valid_ff, _T_6164) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6166 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6167 = and(_T_6165, _T_6166) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6168 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6169 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6170 = and(_T_6168, _T_6169) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6171 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6172 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6173 = and(_T_6171, _T_6172) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6174 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6175 = and(_T_6173, _T_6174) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6176 = or(_T_6170, _T_6175) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6177 = bits(_T_6176, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6178 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6177 : @[Reg.scala 28:19]
|
|
_T_6178 <= _T_6167 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][28] <= _T_6178 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6179 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6180 = eq(_T_6179, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6181 = and(ic_valid_ff, _T_6180) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6182 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6183 = and(_T_6181, _T_6182) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6184 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6185 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6186 = and(_T_6184, _T_6185) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6187 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6188 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6189 = and(_T_6187, _T_6188) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6190 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6191 = and(_T_6189, _T_6190) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6192 = or(_T_6186, _T_6191) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6193 = bits(_T_6192, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6194 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6193 : @[Reg.scala 28:19]
|
|
_T_6194 <= _T_6183 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][29] <= _T_6194 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6195 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6196 = eq(_T_6195, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6197 = and(ic_valid_ff, _T_6196) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6199 = and(_T_6197, _T_6198) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6200 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6201 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6202 = and(_T_6200, _T_6201) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6203 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6204 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6205 = and(_T_6203, _T_6204) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6206 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6207 = and(_T_6205, _T_6206) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6208 = or(_T_6202, _T_6207) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6209 = bits(_T_6208, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6210 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6209 : @[Reg.scala 28:19]
|
|
_T_6210 <= _T_6199 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][30] <= _T_6210 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6211 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6212 = eq(_T_6211, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6213 = and(ic_valid_ff, _T_6212) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6214 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6215 = and(_T_6213, _T_6214) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6216 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6217 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6218 = and(_T_6216, _T_6217) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6219 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6220 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6221 = and(_T_6219, _T_6220) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6222 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6223 = and(_T_6221, _T_6222) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6224 = or(_T_6218, _T_6223) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6225 = bits(_T_6224, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6226 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6225 : @[Reg.scala 28:19]
|
|
_T_6226 <= _T_6215 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][31] <= _T_6226 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6227 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6228 = eq(_T_6227, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6229 = and(ic_valid_ff, _T_6228) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6230 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6231 = and(_T_6229, _T_6230) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6232 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6233 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6234 = and(_T_6232, _T_6233) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6235 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6236 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6237 = and(_T_6235, _T_6236) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6238 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6239 = and(_T_6237, _T_6238) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6240 = or(_T_6234, _T_6239) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6241 = bits(_T_6240, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6242 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6241 : @[Reg.scala 28:19]
|
|
_T_6242 <= _T_6231 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][32] <= _T_6242 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6243 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6244 = eq(_T_6243, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6245 = and(ic_valid_ff, _T_6244) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6246 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6247 = and(_T_6245, _T_6246) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6248 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6249 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6250 = and(_T_6248, _T_6249) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6251 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6252 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6253 = and(_T_6251, _T_6252) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6254 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6255 = and(_T_6253, _T_6254) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6256 = or(_T_6250, _T_6255) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6257 = bits(_T_6256, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6258 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6257 : @[Reg.scala 28:19]
|
|
_T_6258 <= _T_6247 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][33] <= _T_6258 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6259 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6260 = eq(_T_6259, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6261 = and(ic_valid_ff, _T_6260) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6262 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6263 = and(_T_6261, _T_6262) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6264 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6265 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6266 = and(_T_6264, _T_6265) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6267 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6268 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6269 = and(_T_6267, _T_6268) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6270 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6271 = and(_T_6269, _T_6270) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6272 = or(_T_6266, _T_6271) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6273 = bits(_T_6272, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6274 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6273 : @[Reg.scala 28:19]
|
|
_T_6274 <= _T_6263 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][34] <= _T_6274 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6275 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6276 = eq(_T_6275, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6277 = and(ic_valid_ff, _T_6276) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6278 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6279 = and(_T_6277, _T_6278) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6280 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6281 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6282 = and(_T_6280, _T_6281) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6283 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6284 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6285 = and(_T_6283, _T_6284) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6286 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6287 = and(_T_6285, _T_6286) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6288 = or(_T_6282, _T_6287) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6289 = bits(_T_6288, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6290 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6289 : @[Reg.scala 28:19]
|
|
_T_6290 <= _T_6279 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][35] <= _T_6290 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6291 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6292 = eq(_T_6291, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6293 = and(ic_valid_ff, _T_6292) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6294 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6295 = and(_T_6293, _T_6294) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6296 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6297 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6298 = and(_T_6296, _T_6297) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6299 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6300 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6301 = and(_T_6299, _T_6300) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6302 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6303 = and(_T_6301, _T_6302) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6304 = or(_T_6298, _T_6303) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6305 = bits(_T_6304, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6306 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6305 : @[Reg.scala 28:19]
|
|
_T_6306 <= _T_6295 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][36] <= _T_6306 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6307 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6308 = eq(_T_6307, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6309 = and(ic_valid_ff, _T_6308) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6310 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6311 = and(_T_6309, _T_6310) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6312 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6313 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6314 = and(_T_6312, _T_6313) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6315 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6316 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6317 = and(_T_6315, _T_6316) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6318 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6319 = and(_T_6317, _T_6318) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6320 = or(_T_6314, _T_6319) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6321 = bits(_T_6320, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6322 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6321 : @[Reg.scala 28:19]
|
|
_T_6322 <= _T_6311 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][37] <= _T_6322 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6323 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6324 = eq(_T_6323, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6325 = and(ic_valid_ff, _T_6324) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6326 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6327 = and(_T_6325, _T_6326) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6328 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6329 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6330 = and(_T_6328, _T_6329) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6331 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6332 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6333 = and(_T_6331, _T_6332) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6334 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6335 = and(_T_6333, _T_6334) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6336 = or(_T_6330, _T_6335) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6337 = bits(_T_6336, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6338 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6337 : @[Reg.scala 28:19]
|
|
_T_6338 <= _T_6327 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][38] <= _T_6338 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6339 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6340 = eq(_T_6339, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6341 = and(ic_valid_ff, _T_6340) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6342 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6343 = and(_T_6341, _T_6342) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6344 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6345 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6346 = and(_T_6344, _T_6345) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6347 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6348 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6349 = and(_T_6347, _T_6348) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6350 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6351 = and(_T_6349, _T_6350) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6352 = or(_T_6346, _T_6351) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6353 = bits(_T_6352, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6354 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6353 : @[Reg.scala 28:19]
|
|
_T_6354 <= _T_6343 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][39] <= _T_6354 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6355 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6356 = eq(_T_6355, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6357 = and(ic_valid_ff, _T_6356) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6358 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6359 = and(_T_6357, _T_6358) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6360 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6361 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6362 = and(_T_6360, _T_6361) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6363 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6364 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6365 = and(_T_6363, _T_6364) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6366 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6367 = and(_T_6365, _T_6366) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6368 = or(_T_6362, _T_6367) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6369 = bits(_T_6368, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6370 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6369 : @[Reg.scala 28:19]
|
|
_T_6370 <= _T_6359 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][40] <= _T_6370 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6371 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6372 = eq(_T_6371, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6373 = and(ic_valid_ff, _T_6372) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6374 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6375 = and(_T_6373, _T_6374) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6376 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6377 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6378 = and(_T_6376, _T_6377) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6379 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6380 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6381 = and(_T_6379, _T_6380) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6382 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6383 = and(_T_6381, _T_6382) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6384 = or(_T_6378, _T_6383) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6385 = bits(_T_6384, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6386 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6385 : @[Reg.scala 28:19]
|
|
_T_6386 <= _T_6375 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][41] <= _T_6386 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6387 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6388 = eq(_T_6387, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6389 = and(ic_valid_ff, _T_6388) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6390 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6391 = and(_T_6389, _T_6390) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6392 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6393 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6394 = and(_T_6392, _T_6393) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6395 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6396 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6397 = and(_T_6395, _T_6396) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6398 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6399 = and(_T_6397, _T_6398) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6400 = or(_T_6394, _T_6399) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6401 = bits(_T_6400, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6402 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6401 : @[Reg.scala 28:19]
|
|
_T_6402 <= _T_6391 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][42] <= _T_6402 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6403 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6404 = eq(_T_6403, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6405 = and(ic_valid_ff, _T_6404) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6406 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6407 = and(_T_6405, _T_6406) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6408 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6409 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6410 = and(_T_6408, _T_6409) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6411 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6412 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6413 = and(_T_6411, _T_6412) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6414 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6415 = and(_T_6413, _T_6414) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6416 = or(_T_6410, _T_6415) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6417 = bits(_T_6416, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6418 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6417 : @[Reg.scala 28:19]
|
|
_T_6418 <= _T_6407 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][43] <= _T_6418 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6419 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6420 = eq(_T_6419, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6421 = and(ic_valid_ff, _T_6420) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6422 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6423 = and(_T_6421, _T_6422) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6424 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6425 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6426 = and(_T_6424, _T_6425) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6427 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6428 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6429 = and(_T_6427, _T_6428) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6430 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6431 = and(_T_6429, _T_6430) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6432 = or(_T_6426, _T_6431) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6433 = bits(_T_6432, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6434 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6433 : @[Reg.scala 28:19]
|
|
_T_6434 <= _T_6423 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][44] <= _T_6434 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6435 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6436 = eq(_T_6435, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6437 = and(ic_valid_ff, _T_6436) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6438 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6439 = and(_T_6437, _T_6438) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6440 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6441 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6442 = and(_T_6440, _T_6441) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6443 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6444 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6445 = and(_T_6443, _T_6444) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6446 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6447 = and(_T_6445, _T_6446) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6448 = or(_T_6442, _T_6447) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6449 = bits(_T_6448, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6450 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6449 : @[Reg.scala 28:19]
|
|
_T_6450 <= _T_6439 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][45] <= _T_6450 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6451 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6452 = eq(_T_6451, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6453 = and(ic_valid_ff, _T_6452) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6454 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6455 = and(_T_6453, _T_6454) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6456 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6457 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6458 = and(_T_6456, _T_6457) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6459 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6460 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6461 = and(_T_6459, _T_6460) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6462 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6463 = and(_T_6461, _T_6462) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6464 = or(_T_6458, _T_6463) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6465 = bits(_T_6464, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6466 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6465 : @[Reg.scala 28:19]
|
|
_T_6466 <= _T_6455 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][46] <= _T_6466 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6467 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6468 = eq(_T_6467, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6469 = and(ic_valid_ff, _T_6468) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6470 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6471 = and(_T_6469, _T_6470) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6472 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6473 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6474 = and(_T_6472, _T_6473) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6475 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6476 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6477 = and(_T_6475, _T_6476) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6478 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6479 = and(_T_6477, _T_6478) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6480 = or(_T_6474, _T_6479) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6481 = bits(_T_6480, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6482 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6481 : @[Reg.scala 28:19]
|
|
_T_6482 <= _T_6471 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][47] <= _T_6482 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6483 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6484 = eq(_T_6483, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6485 = and(ic_valid_ff, _T_6484) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6486 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6487 = and(_T_6485, _T_6486) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6488 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6489 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6490 = and(_T_6488, _T_6489) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6491 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6492 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6493 = and(_T_6491, _T_6492) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6494 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6495 = and(_T_6493, _T_6494) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6496 = or(_T_6490, _T_6495) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6497 = bits(_T_6496, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6498 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6497 : @[Reg.scala 28:19]
|
|
_T_6498 <= _T_6487 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][48] <= _T_6498 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6499 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6500 = eq(_T_6499, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6501 = and(ic_valid_ff, _T_6500) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6502 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6503 = and(_T_6501, _T_6502) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6504 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6505 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6506 = and(_T_6504, _T_6505) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6507 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6508 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6509 = and(_T_6507, _T_6508) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6510 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6511 = and(_T_6509, _T_6510) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6512 = or(_T_6506, _T_6511) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6513 = bits(_T_6512, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6514 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6513 : @[Reg.scala 28:19]
|
|
_T_6514 <= _T_6503 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][49] <= _T_6514 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6515 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6516 = eq(_T_6515, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6517 = and(ic_valid_ff, _T_6516) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6518 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6519 = and(_T_6517, _T_6518) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6520 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6521 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6522 = and(_T_6520, _T_6521) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6523 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6524 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6525 = and(_T_6523, _T_6524) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6526 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6527 = and(_T_6525, _T_6526) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6528 = or(_T_6522, _T_6527) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6529 = bits(_T_6528, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6530 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6529 : @[Reg.scala 28:19]
|
|
_T_6530 <= _T_6519 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][50] <= _T_6530 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6531 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6532 = eq(_T_6531, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6533 = and(ic_valid_ff, _T_6532) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6534 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6535 = and(_T_6533, _T_6534) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6536 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6537 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6538 = and(_T_6536, _T_6537) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6539 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6540 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6541 = and(_T_6539, _T_6540) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6542 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6543 = and(_T_6541, _T_6542) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6544 = or(_T_6538, _T_6543) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6545 = bits(_T_6544, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6546 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6545 : @[Reg.scala 28:19]
|
|
_T_6546 <= _T_6535 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][51] <= _T_6546 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6547 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6548 = eq(_T_6547, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6549 = and(ic_valid_ff, _T_6548) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6550 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6551 = and(_T_6549, _T_6550) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6552 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6553 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6554 = and(_T_6552, _T_6553) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6555 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6556 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6557 = and(_T_6555, _T_6556) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6558 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6559 = and(_T_6557, _T_6558) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6560 = or(_T_6554, _T_6559) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6561 = bits(_T_6560, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6562 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6561 : @[Reg.scala 28:19]
|
|
_T_6562 <= _T_6551 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][52] <= _T_6562 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6563 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6564 = eq(_T_6563, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6565 = and(ic_valid_ff, _T_6564) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6566 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6567 = and(_T_6565, _T_6566) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6568 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6569 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6570 = and(_T_6568, _T_6569) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6571 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6572 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6573 = and(_T_6571, _T_6572) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6574 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6575 = and(_T_6573, _T_6574) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6576 = or(_T_6570, _T_6575) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6577 = bits(_T_6576, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6578 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6577 : @[Reg.scala 28:19]
|
|
_T_6578 <= _T_6567 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][53] <= _T_6578 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6579 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6580 = eq(_T_6579, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6581 = and(ic_valid_ff, _T_6580) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6582 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6583 = and(_T_6581, _T_6582) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6584 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6585 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6586 = and(_T_6584, _T_6585) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6587 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6588 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6589 = and(_T_6587, _T_6588) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6590 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6591 = and(_T_6589, _T_6590) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6592 = or(_T_6586, _T_6591) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6593 = bits(_T_6592, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6594 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6593 : @[Reg.scala 28:19]
|
|
_T_6594 <= _T_6583 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][54] <= _T_6594 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6595 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6596 = eq(_T_6595, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6597 = and(ic_valid_ff, _T_6596) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6598 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6599 = and(_T_6597, _T_6598) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6600 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6601 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6602 = and(_T_6600, _T_6601) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6603 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6604 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6605 = and(_T_6603, _T_6604) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6606 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6607 = and(_T_6605, _T_6606) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6608 = or(_T_6602, _T_6607) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6609 = bits(_T_6608, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6610 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6609 : @[Reg.scala 28:19]
|
|
_T_6610 <= _T_6599 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][55] <= _T_6610 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6611 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6612 = eq(_T_6611, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6613 = and(ic_valid_ff, _T_6612) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6614 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6615 = and(_T_6613, _T_6614) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6616 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6617 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6618 = and(_T_6616, _T_6617) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6619 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6620 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6621 = and(_T_6619, _T_6620) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6622 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6623 = and(_T_6621, _T_6622) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6624 = or(_T_6618, _T_6623) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6625 = bits(_T_6624, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6626 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6625 : @[Reg.scala 28:19]
|
|
_T_6626 <= _T_6615 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][56] <= _T_6626 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6627 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6628 = eq(_T_6627, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6629 = and(ic_valid_ff, _T_6628) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6630 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6631 = and(_T_6629, _T_6630) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6632 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6633 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6634 = and(_T_6632, _T_6633) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6635 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6636 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6637 = and(_T_6635, _T_6636) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6638 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6639 = and(_T_6637, _T_6638) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6640 = or(_T_6634, _T_6639) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6641 = bits(_T_6640, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6642 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6641 : @[Reg.scala 28:19]
|
|
_T_6642 <= _T_6631 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][57] <= _T_6642 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6643 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6644 = eq(_T_6643, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6645 = and(ic_valid_ff, _T_6644) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6646 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6647 = and(_T_6645, _T_6646) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6648 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6649 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6650 = and(_T_6648, _T_6649) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6651 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6652 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6653 = and(_T_6651, _T_6652) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6654 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6655 = and(_T_6653, _T_6654) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6656 = or(_T_6650, _T_6655) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6657 = bits(_T_6656, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6658 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6657 : @[Reg.scala 28:19]
|
|
_T_6658 <= _T_6647 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][58] <= _T_6658 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6659 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6660 = eq(_T_6659, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6661 = and(ic_valid_ff, _T_6660) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6662 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6663 = and(_T_6661, _T_6662) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6664 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6665 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6666 = and(_T_6664, _T_6665) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6667 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6668 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6669 = and(_T_6667, _T_6668) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6670 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6671 = and(_T_6669, _T_6670) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6672 = or(_T_6666, _T_6671) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6673 = bits(_T_6672, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6674 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6673 : @[Reg.scala 28:19]
|
|
_T_6674 <= _T_6663 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][59] <= _T_6674 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6675 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6676 = eq(_T_6675, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6677 = and(ic_valid_ff, _T_6676) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6678 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6679 = and(_T_6677, _T_6678) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6680 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6681 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6682 = and(_T_6680, _T_6681) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6683 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6684 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6685 = and(_T_6683, _T_6684) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6686 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6687 = and(_T_6685, _T_6686) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6688 = or(_T_6682, _T_6687) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6689 = bits(_T_6688, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6690 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6689 : @[Reg.scala 28:19]
|
|
_T_6690 <= _T_6679 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][60] <= _T_6690 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6691 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6692 = eq(_T_6691, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6693 = and(ic_valid_ff, _T_6692) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6694 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6695 = and(_T_6693, _T_6694) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6696 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6697 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6698 = and(_T_6696, _T_6697) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6699 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6700 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6701 = and(_T_6699, _T_6700) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6702 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6703 = and(_T_6701, _T_6702) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6704 = or(_T_6698, _T_6703) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6705 = bits(_T_6704, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6706 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6705 : @[Reg.scala 28:19]
|
|
_T_6706 <= _T_6695 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][61] <= _T_6706 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6707 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6708 = eq(_T_6707, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6709 = and(ic_valid_ff, _T_6708) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6710 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6711 = and(_T_6709, _T_6710) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6712 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6713 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6714 = and(_T_6712, _T_6713) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6715 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6716 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6717 = and(_T_6715, _T_6716) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6718 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6719 = and(_T_6717, _T_6718) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6720 = or(_T_6714, _T_6719) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6721 = bits(_T_6720, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6722 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6721 : @[Reg.scala 28:19]
|
|
_T_6722 <= _T_6711 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][62] <= _T_6722 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6723 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6724 = eq(_T_6723, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6725 = and(ic_valid_ff, _T_6724) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6726 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6727 = and(_T_6725, _T_6726) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6728 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6729 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6730 = and(_T_6728, _T_6729) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6731 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6732 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6733 = and(_T_6731, _T_6732) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6734 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6735 = and(_T_6733, _T_6734) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6736 = or(_T_6730, _T_6735) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6737 = bits(_T_6736, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6738 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6737 : @[Reg.scala 28:19]
|
|
_T_6738 <= _T_6727 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][63] <= _T_6738 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6739 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6740 = eq(_T_6739, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6741 = and(ic_valid_ff, _T_6740) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6742 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6743 = and(_T_6741, _T_6742) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6744 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6745 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6746 = and(_T_6744, _T_6745) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6747 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6748 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6749 = and(_T_6747, _T_6748) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6750 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6751 = and(_T_6749, _T_6750) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6752 = or(_T_6746, _T_6751) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6753 = bits(_T_6752, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6754 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6753 : @[Reg.scala 28:19]
|
|
_T_6754 <= _T_6743 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][32] <= _T_6754 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6755 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6756 = eq(_T_6755, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6757 = and(ic_valid_ff, _T_6756) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6758 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6759 = and(_T_6757, _T_6758) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6760 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6761 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6762 = and(_T_6760, _T_6761) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6763 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6764 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6765 = and(_T_6763, _T_6764) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6766 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6767 = and(_T_6765, _T_6766) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6768 = or(_T_6762, _T_6767) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6769 = bits(_T_6768, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6770 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6769 : @[Reg.scala 28:19]
|
|
_T_6770 <= _T_6759 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][33] <= _T_6770 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6771 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6772 = eq(_T_6771, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6773 = and(ic_valid_ff, _T_6772) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6774 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6775 = and(_T_6773, _T_6774) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6776 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6777 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6778 = and(_T_6776, _T_6777) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6779 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6780 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6781 = and(_T_6779, _T_6780) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6782 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6783 = and(_T_6781, _T_6782) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6784 = or(_T_6778, _T_6783) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6785 = bits(_T_6784, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6786 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6785 : @[Reg.scala 28:19]
|
|
_T_6786 <= _T_6775 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][34] <= _T_6786 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6787 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6788 = eq(_T_6787, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6789 = and(ic_valid_ff, _T_6788) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6790 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6791 = and(_T_6789, _T_6790) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6792 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6793 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6794 = and(_T_6792, _T_6793) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6795 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6796 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6797 = and(_T_6795, _T_6796) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6798 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6799 = and(_T_6797, _T_6798) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6800 = or(_T_6794, _T_6799) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6801 = bits(_T_6800, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6802 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6801 : @[Reg.scala 28:19]
|
|
_T_6802 <= _T_6791 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][35] <= _T_6802 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6803 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6804 = eq(_T_6803, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6805 = and(ic_valid_ff, _T_6804) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6806 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6807 = and(_T_6805, _T_6806) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6808 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6809 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6810 = and(_T_6808, _T_6809) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6811 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6812 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6813 = and(_T_6811, _T_6812) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6814 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6815 = and(_T_6813, _T_6814) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6816 = or(_T_6810, _T_6815) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6817 = bits(_T_6816, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6818 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6817 : @[Reg.scala 28:19]
|
|
_T_6818 <= _T_6807 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][36] <= _T_6818 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6819 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6820 = eq(_T_6819, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6821 = and(ic_valid_ff, _T_6820) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6822 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6823 = and(_T_6821, _T_6822) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6824 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6825 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6826 = and(_T_6824, _T_6825) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6827 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6828 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6829 = and(_T_6827, _T_6828) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6830 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6831 = and(_T_6829, _T_6830) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6832 = or(_T_6826, _T_6831) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6833 = bits(_T_6832, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6834 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6833 : @[Reg.scala 28:19]
|
|
_T_6834 <= _T_6823 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][37] <= _T_6834 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6835 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6836 = eq(_T_6835, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6837 = and(ic_valid_ff, _T_6836) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6838 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6839 = and(_T_6837, _T_6838) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6840 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6841 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6842 = and(_T_6840, _T_6841) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6843 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6844 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6845 = and(_T_6843, _T_6844) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6846 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6847 = and(_T_6845, _T_6846) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6848 = or(_T_6842, _T_6847) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6849 = bits(_T_6848, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6850 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6849 : @[Reg.scala 28:19]
|
|
_T_6850 <= _T_6839 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][38] <= _T_6850 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6851 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6852 = eq(_T_6851, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6853 = and(ic_valid_ff, _T_6852) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6854 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6855 = and(_T_6853, _T_6854) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6856 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6857 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6858 = and(_T_6856, _T_6857) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6859 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6860 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6861 = and(_T_6859, _T_6860) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6862 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6863 = and(_T_6861, _T_6862) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6864 = or(_T_6858, _T_6863) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6865 = bits(_T_6864, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6866 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6865 : @[Reg.scala 28:19]
|
|
_T_6866 <= _T_6855 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][39] <= _T_6866 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6867 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6868 = eq(_T_6867, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6869 = and(ic_valid_ff, _T_6868) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6870 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6871 = and(_T_6869, _T_6870) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6872 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6873 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6874 = and(_T_6872, _T_6873) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6875 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6876 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6877 = and(_T_6875, _T_6876) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6878 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6879 = and(_T_6877, _T_6878) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6880 = or(_T_6874, _T_6879) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6881 = bits(_T_6880, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6882 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6881 : @[Reg.scala 28:19]
|
|
_T_6882 <= _T_6871 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][40] <= _T_6882 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6883 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6884 = eq(_T_6883, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6885 = and(ic_valid_ff, _T_6884) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6886 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6887 = and(_T_6885, _T_6886) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6888 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6889 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6890 = and(_T_6888, _T_6889) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6891 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6892 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6893 = and(_T_6891, _T_6892) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6894 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6895 = and(_T_6893, _T_6894) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6896 = or(_T_6890, _T_6895) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6897 = bits(_T_6896, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6898 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6897 : @[Reg.scala 28:19]
|
|
_T_6898 <= _T_6887 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][41] <= _T_6898 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6899 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6900 = eq(_T_6899, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6901 = and(ic_valid_ff, _T_6900) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6902 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6903 = and(_T_6901, _T_6902) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6904 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6905 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6906 = and(_T_6904, _T_6905) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6907 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6908 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6909 = and(_T_6907, _T_6908) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6910 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6911 = and(_T_6909, _T_6910) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6912 = or(_T_6906, _T_6911) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6913 = bits(_T_6912, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6914 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6913 : @[Reg.scala 28:19]
|
|
_T_6914 <= _T_6903 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][42] <= _T_6914 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6915 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6916 = eq(_T_6915, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6917 = and(ic_valid_ff, _T_6916) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6918 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6919 = and(_T_6917, _T_6918) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6920 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6921 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6922 = and(_T_6920, _T_6921) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6923 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6924 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6925 = and(_T_6923, _T_6924) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6926 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6927 = and(_T_6925, _T_6926) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6928 = or(_T_6922, _T_6927) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6929 = bits(_T_6928, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6930 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6929 : @[Reg.scala 28:19]
|
|
_T_6930 <= _T_6919 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][43] <= _T_6930 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6931 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6932 = eq(_T_6931, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6933 = and(ic_valid_ff, _T_6932) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6934 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6935 = and(_T_6933, _T_6934) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6936 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6937 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6938 = and(_T_6936, _T_6937) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6939 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6940 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6941 = and(_T_6939, _T_6940) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6942 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6943 = and(_T_6941, _T_6942) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6944 = or(_T_6938, _T_6943) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6945 = bits(_T_6944, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6946 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6945 : @[Reg.scala 28:19]
|
|
_T_6946 <= _T_6935 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][44] <= _T_6946 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6947 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6948 = eq(_T_6947, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6949 = and(ic_valid_ff, _T_6948) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6950 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6951 = and(_T_6949, _T_6950) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6952 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6953 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6954 = and(_T_6952, _T_6953) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6955 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6956 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6957 = and(_T_6955, _T_6956) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6958 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6959 = and(_T_6957, _T_6958) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6960 = or(_T_6954, _T_6959) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6961 = bits(_T_6960, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6962 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6961 : @[Reg.scala 28:19]
|
|
_T_6962 <= _T_6951 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][45] <= _T_6962 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6963 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6964 = eq(_T_6963, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6965 = and(ic_valid_ff, _T_6964) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6966 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6967 = and(_T_6965, _T_6966) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6968 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6969 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6970 = and(_T_6968, _T_6969) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6971 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6972 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6973 = and(_T_6971, _T_6972) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6974 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6975 = and(_T_6973, _T_6974) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6976 = or(_T_6970, _T_6975) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6977 = bits(_T_6976, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6978 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6977 : @[Reg.scala 28:19]
|
|
_T_6978 <= _T_6967 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][46] <= _T_6978 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6979 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6980 = eq(_T_6979, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6981 = and(ic_valid_ff, _T_6980) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6982 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6983 = and(_T_6981, _T_6982) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_6984 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_6985 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_6986 = and(_T_6984, _T_6985) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_6987 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_6988 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_6989 = and(_T_6987, _T_6988) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_6990 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_6991 = and(_T_6989, _T_6990) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_6992 = or(_T_6986, _T_6991) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_6993 = bits(_T_6992, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_6994 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6993 : @[Reg.scala 28:19]
|
|
_T_6994 <= _T_6983 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][47] <= _T_6994 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_6995 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_6996 = eq(_T_6995, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_6997 = and(ic_valid_ff, _T_6996) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_6998 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_6999 = and(_T_6997, _T_6998) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7000 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7001 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7002 = and(_T_7000, _T_7001) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7003 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7004 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7005 = and(_T_7003, _T_7004) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7006 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7007 = and(_T_7005, _T_7006) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7008 = or(_T_7002, _T_7007) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7009 = bits(_T_7008, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7010 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7009 : @[Reg.scala 28:19]
|
|
_T_7010 <= _T_6999 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][48] <= _T_7010 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7011 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7012 = eq(_T_7011, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7013 = and(ic_valid_ff, _T_7012) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7014 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7015 = and(_T_7013, _T_7014) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7016 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7017 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7018 = and(_T_7016, _T_7017) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7019 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7020 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7021 = and(_T_7019, _T_7020) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7022 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7023 = and(_T_7021, _T_7022) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7024 = or(_T_7018, _T_7023) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7025 = bits(_T_7024, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7026 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7025 : @[Reg.scala 28:19]
|
|
_T_7026 <= _T_7015 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][49] <= _T_7026 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7027 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7028 = eq(_T_7027, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7029 = and(ic_valid_ff, _T_7028) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7030 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7031 = and(_T_7029, _T_7030) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7032 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7033 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7034 = and(_T_7032, _T_7033) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7035 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7036 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7037 = and(_T_7035, _T_7036) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7038 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7039 = and(_T_7037, _T_7038) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7040 = or(_T_7034, _T_7039) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7041 = bits(_T_7040, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7042 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7041 : @[Reg.scala 28:19]
|
|
_T_7042 <= _T_7031 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][50] <= _T_7042 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7043 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7044 = eq(_T_7043, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7045 = and(ic_valid_ff, _T_7044) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7046 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7047 = and(_T_7045, _T_7046) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7048 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7049 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7050 = and(_T_7048, _T_7049) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7051 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7052 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7053 = and(_T_7051, _T_7052) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7054 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7055 = and(_T_7053, _T_7054) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7056 = or(_T_7050, _T_7055) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7057 = bits(_T_7056, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7058 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7057 : @[Reg.scala 28:19]
|
|
_T_7058 <= _T_7047 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][51] <= _T_7058 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7059 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7060 = eq(_T_7059, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7061 = and(ic_valid_ff, _T_7060) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7062 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7063 = and(_T_7061, _T_7062) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7064 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7065 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7066 = and(_T_7064, _T_7065) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7067 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7068 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7069 = and(_T_7067, _T_7068) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7070 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7071 = and(_T_7069, _T_7070) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7072 = or(_T_7066, _T_7071) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7073 = bits(_T_7072, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7074 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7073 : @[Reg.scala 28:19]
|
|
_T_7074 <= _T_7063 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][52] <= _T_7074 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7075 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7076 = eq(_T_7075, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7077 = and(ic_valid_ff, _T_7076) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7078 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7079 = and(_T_7077, _T_7078) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7080 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7081 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7082 = and(_T_7080, _T_7081) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7083 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7084 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7085 = and(_T_7083, _T_7084) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7086 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7087 = and(_T_7085, _T_7086) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7088 = or(_T_7082, _T_7087) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7089 = bits(_T_7088, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7090 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7089 : @[Reg.scala 28:19]
|
|
_T_7090 <= _T_7079 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][53] <= _T_7090 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7091 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7092 = eq(_T_7091, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7093 = and(ic_valid_ff, _T_7092) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7094 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7095 = and(_T_7093, _T_7094) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7096 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7097 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7098 = and(_T_7096, _T_7097) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7099 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7100 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7101 = and(_T_7099, _T_7100) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7102 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7103 = and(_T_7101, _T_7102) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7104 = or(_T_7098, _T_7103) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7105 = bits(_T_7104, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7106 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7105 : @[Reg.scala 28:19]
|
|
_T_7106 <= _T_7095 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][54] <= _T_7106 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7107 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7108 = eq(_T_7107, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7109 = and(ic_valid_ff, _T_7108) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7110 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7111 = and(_T_7109, _T_7110) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7112 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7113 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7114 = and(_T_7112, _T_7113) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7115 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7116 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7117 = and(_T_7115, _T_7116) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7118 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7119 = and(_T_7117, _T_7118) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7120 = or(_T_7114, _T_7119) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7121 = bits(_T_7120, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7122 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7121 : @[Reg.scala 28:19]
|
|
_T_7122 <= _T_7111 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][55] <= _T_7122 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7123 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7124 = eq(_T_7123, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7125 = and(ic_valid_ff, _T_7124) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7126 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7127 = and(_T_7125, _T_7126) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7128 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7129 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7130 = and(_T_7128, _T_7129) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7131 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7132 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7133 = and(_T_7131, _T_7132) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7134 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7135 = and(_T_7133, _T_7134) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7136 = or(_T_7130, _T_7135) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7137 = bits(_T_7136, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7138 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7137 : @[Reg.scala 28:19]
|
|
_T_7138 <= _T_7127 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][56] <= _T_7138 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7139 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7140 = eq(_T_7139, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7141 = and(ic_valid_ff, _T_7140) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7142 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7143 = and(_T_7141, _T_7142) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7144 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7145 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7146 = and(_T_7144, _T_7145) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7147 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7148 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7149 = and(_T_7147, _T_7148) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7150 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7151 = and(_T_7149, _T_7150) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7152 = or(_T_7146, _T_7151) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7153 = bits(_T_7152, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7154 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7153 : @[Reg.scala 28:19]
|
|
_T_7154 <= _T_7143 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][57] <= _T_7154 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7155 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7156 = eq(_T_7155, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7157 = and(ic_valid_ff, _T_7156) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7158 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7159 = and(_T_7157, _T_7158) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7160 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7161 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7162 = and(_T_7160, _T_7161) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7163 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7164 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7165 = and(_T_7163, _T_7164) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7166 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7167 = and(_T_7165, _T_7166) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7168 = or(_T_7162, _T_7167) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7169 = bits(_T_7168, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7170 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7169 : @[Reg.scala 28:19]
|
|
_T_7170 <= _T_7159 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][58] <= _T_7170 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7171 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7172 = eq(_T_7171, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7173 = and(ic_valid_ff, _T_7172) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7174 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7175 = and(_T_7173, _T_7174) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7176 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7177 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7178 = and(_T_7176, _T_7177) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7179 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7180 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7181 = and(_T_7179, _T_7180) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7182 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7183 = and(_T_7181, _T_7182) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7184 = or(_T_7178, _T_7183) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7185 = bits(_T_7184, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7186 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7185 : @[Reg.scala 28:19]
|
|
_T_7186 <= _T_7175 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][59] <= _T_7186 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7187 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7188 = eq(_T_7187, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7189 = and(ic_valid_ff, _T_7188) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7190 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7191 = and(_T_7189, _T_7190) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7192 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7193 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7194 = and(_T_7192, _T_7193) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7195 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7196 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7197 = and(_T_7195, _T_7196) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7198 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7199 = and(_T_7197, _T_7198) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7200 = or(_T_7194, _T_7199) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7201 = bits(_T_7200, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7202 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7201 : @[Reg.scala 28:19]
|
|
_T_7202 <= _T_7191 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][60] <= _T_7202 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7203 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7204 = eq(_T_7203, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7205 = and(ic_valid_ff, _T_7204) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7206 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7207 = and(_T_7205, _T_7206) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7208 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7209 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7210 = and(_T_7208, _T_7209) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7211 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7212 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7213 = and(_T_7211, _T_7212) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7214 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7215 = and(_T_7213, _T_7214) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7216 = or(_T_7210, _T_7215) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7217 = bits(_T_7216, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7218 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7217 : @[Reg.scala 28:19]
|
|
_T_7218 <= _T_7207 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][61] <= _T_7218 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7219 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7220 = eq(_T_7219, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7221 = and(ic_valid_ff, _T_7220) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7222 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7223 = and(_T_7221, _T_7222) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7224 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7225 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7226 = and(_T_7224, _T_7225) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7227 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7228 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7229 = and(_T_7227, _T_7228) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7230 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7231 = and(_T_7229, _T_7230) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7232 = or(_T_7226, _T_7231) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7233 = bits(_T_7232, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7234 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7233 : @[Reg.scala 28:19]
|
|
_T_7234 <= _T_7223 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][62] <= _T_7234 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7235 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7236 = eq(_T_7235, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7237 = and(ic_valid_ff, _T_7236) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7238 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7239 = and(_T_7237, _T_7238) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7240 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7241 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7242 = and(_T_7240, _T_7241) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7243 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7244 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7245 = and(_T_7243, _T_7244) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7246 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7247 = and(_T_7245, _T_7246) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7248 = or(_T_7242, _T_7247) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7249 = bits(_T_7248, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7250 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7249 : @[Reg.scala 28:19]
|
|
_T_7250 <= _T_7239 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][63] <= _T_7250 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7251 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7252 = eq(_T_7251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7253 = and(ic_valid_ff, _T_7252) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7254 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7255 = and(_T_7253, _T_7254) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7256 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7257 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7258 = and(_T_7256, _T_7257) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7259 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7260 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7261 = and(_T_7259, _T_7260) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7262 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7263 = and(_T_7261, _T_7262) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7264 = or(_T_7258, _T_7263) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7265 = bits(_T_7264, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7266 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7265 : @[Reg.scala 28:19]
|
|
_T_7266 <= _T_7255 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][64] <= _T_7266 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7267 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7268 = eq(_T_7267, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7269 = and(ic_valid_ff, _T_7268) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7270 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7271 = and(_T_7269, _T_7270) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7272 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7273 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7274 = and(_T_7272, _T_7273) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7275 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7276 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7277 = and(_T_7275, _T_7276) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7278 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7279 = and(_T_7277, _T_7278) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7280 = or(_T_7274, _T_7279) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7281 = bits(_T_7280, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7282 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7281 : @[Reg.scala 28:19]
|
|
_T_7282 <= _T_7271 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][65] <= _T_7282 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7283 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7284 = eq(_T_7283, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7285 = and(ic_valid_ff, _T_7284) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7286 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7287 = and(_T_7285, _T_7286) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7288 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7289 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7290 = and(_T_7288, _T_7289) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7291 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7292 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7293 = and(_T_7291, _T_7292) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7294 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7295 = and(_T_7293, _T_7294) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7296 = or(_T_7290, _T_7295) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7297 = bits(_T_7296, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7298 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7297 : @[Reg.scala 28:19]
|
|
_T_7298 <= _T_7287 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][66] <= _T_7298 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7299 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7300 = eq(_T_7299, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7301 = and(ic_valid_ff, _T_7300) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7302 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7303 = and(_T_7301, _T_7302) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7304 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7305 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7306 = and(_T_7304, _T_7305) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7307 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7308 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7309 = and(_T_7307, _T_7308) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7310 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7311 = and(_T_7309, _T_7310) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7312 = or(_T_7306, _T_7311) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7313 = bits(_T_7312, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7314 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7313 : @[Reg.scala 28:19]
|
|
_T_7314 <= _T_7303 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][67] <= _T_7314 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7315 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7316 = eq(_T_7315, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7317 = and(ic_valid_ff, _T_7316) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7318 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7319 = and(_T_7317, _T_7318) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7320 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7321 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7322 = and(_T_7320, _T_7321) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7323 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7324 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7325 = and(_T_7323, _T_7324) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7326 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7327 = and(_T_7325, _T_7326) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7328 = or(_T_7322, _T_7327) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7329 = bits(_T_7328, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7330 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7329 : @[Reg.scala 28:19]
|
|
_T_7330 <= _T_7319 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][68] <= _T_7330 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7331 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7332 = eq(_T_7331, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7333 = and(ic_valid_ff, _T_7332) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7334 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7335 = and(_T_7333, _T_7334) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7336 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7337 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7338 = and(_T_7336, _T_7337) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7339 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7340 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7341 = and(_T_7339, _T_7340) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7342 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7343 = and(_T_7341, _T_7342) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7344 = or(_T_7338, _T_7343) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7345 = bits(_T_7344, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7346 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7345 : @[Reg.scala 28:19]
|
|
_T_7346 <= _T_7335 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][69] <= _T_7346 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7347 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7348 = eq(_T_7347, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7349 = and(ic_valid_ff, _T_7348) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7350 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7351 = and(_T_7349, _T_7350) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7352 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7353 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7354 = and(_T_7352, _T_7353) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7355 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7356 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7357 = and(_T_7355, _T_7356) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7358 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7359 = and(_T_7357, _T_7358) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7360 = or(_T_7354, _T_7359) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7361 = bits(_T_7360, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7362 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7361 : @[Reg.scala 28:19]
|
|
_T_7362 <= _T_7351 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][70] <= _T_7362 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7363 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7364 = eq(_T_7363, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7365 = and(ic_valid_ff, _T_7364) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7366 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7367 = and(_T_7365, _T_7366) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7368 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7369 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7370 = and(_T_7368, _T_7369) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7371 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7372 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7373 = and(_T_7371, _T_7372) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7374 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7375 = and(_T_7373, _T_7374) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7376 = or(_T_7370, _T_7375) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7377 = bits(_T_7376, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7378 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7377 : @[Reg.scala 28:19]
|
|
_T_7378 <= _T_7367 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][71] <= _T_7378 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7379 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7380 = eq(_T_7379, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7381 = and(ic_valid_ff, _T_7380) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7382 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7383 = and(_T_7381, _T_7382) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7384 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7385 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7386 = and(_T_7384, _T_7385) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7387 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7388 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7389 = and(_T_7387, _T_7388) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7390 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7391 = and(_T_7389, _T_7390) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7392 = or(_T_7386, _T_7391) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7393 = bits(_T_7392, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7394 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7393 : @[Reg.scala 28:19]
|
|
_T_7394 <= _T_7383 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][72] <= _T_7394 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7395 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7396 = eq(_T_7395, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7397 = and(ic_valid_ff, _T_7396) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7398 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7399 = and(_T_7397, _T_7398) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7400 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7401 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7402 = and(_T_7400, _T_7401) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7403 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7404 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7405 = and(_T_7403, _T_7404) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7406 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7407 = and(_T_7405, _T_7406) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7408 = or(_T_7402, _T_7407) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7409 = bits(_T_7408, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7410 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7409 : @[Reg.scala 28:19]
|
|
_T_7410 <= _T_7399 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][73] <= _T_7410 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7411 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7412 = eq(_T_7411, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7413 = and(ic_valid_ff, _T_7412) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7414 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7415 = and(_T_7413, _T_7414) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7416 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7417 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7418 = and(_T_7416, _T_7417) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7419 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7420 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7421 = and(_T_7419, _T_7420) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7422 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7423 = and(_T_7421, _T_7422) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7424 = or(_T_7418, _T_7423) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7425 = bits(_T_7424, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7426 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7425 : @[Reg.scala 28:19]
|
|
_T_7426 <= _T_7415 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][74] <= _T_7426 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7427 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7428 = eq(_T_7427, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7429 = and(ic_valid_ff, _T_7428) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7430 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7431 = and(_T_7429, _T_7430) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7432 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7433 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7434 = and(_T_7432, _T_7433) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7435 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7436 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7437 = and(_T_7435, _T_7436) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7438 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7439 = and(_T_7437, _T_7438) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7440 = or(_T_7434, _T_7439) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7441 = bits(_T_7440, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7442 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7441 : @[Reg.scala 28:19]
|
|
_T_7442 <= _T_7431 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][75] <= _T_7442 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7443 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7444 = eq(_T_7443, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7445 = and(ic_valid_ff, _T_7444) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7446 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7447 = and(_T_7445, _T_7446) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7448 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7449 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7450 = and(_T_7448, _T_7449) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7451 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7452 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7453 = and(_T_7451, _T_7452) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7454 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7455 = and(_T_7453, _T_7454) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7456 = or(_T_7450, _T_7455) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7457 = bits(_T_7456, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7458 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7457 : @[Reg.scala 28:19]
|
|
_T_7458 <= _T_7447 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][76] <= _T_7458 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7459 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7460 = eq(_T_7459, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7461 = and(ic_valid_ff, _T_7460) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7462 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7463 = and(_T_7461, _T_7462) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7464 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7465 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7466 = and(_T_7464, _T_7465) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7467 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7468 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7469 = and(_T_7467, _T_7468) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7470 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7471 = and(_T_7469, _T_7470) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7472 = or(_T_7466, _T_7471) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7473 = bits(_T_7472, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7474 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7473 : @[Reg.scala 28:19]
|
|
_T_7474 <= _T_7463 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][77] <= _T_7474 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7475 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7476 = eq(_T_7475, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7477 = and(ic_valid_ff, _T_7476) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7478 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7479 = and(_T_7477, _T_7478) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7480 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7481 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7482 = and(_T_7480, _T_7481) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7483 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7484 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7485 = and(_T_7483, _T_7484) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7486 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7487 = and(_T_7485, _T_7486) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7488 = or(_T_7482, _T_7487) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7489 = bits(_T_7488, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7490 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7489 : @[Reg.scala 28:19]
|
|
_T_7490 <= _T_7479 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][78] <= _T_7490 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7491 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7492 = eq(_T_7491, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7493 = and(ic_valid_ff, _T_7492) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7494 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7495 = and(_T_7493, _T_7494) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7496 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7497 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7498 = and(_T_7496, _T_7497) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7499 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7500 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7501 = and(_T_7499, _T_7500) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7502 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7503 = and(_T_7501, _T_7502) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7504 = or(_T_7498, _T_7503) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7505 = bits(_T_7504, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7506 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7505 : @[Reg.scala 28:19]
|
|
_T_7506 <= _T_7495 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][79] <= _T_7506 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7507 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7508 = eq(_T_7507, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7509 = and(ic_valid_ff, _T_7508) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7510 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7511 = and(_T_7509, _T_7510) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7512 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7513 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7514 = and(_T_7512, _T_7513) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7515 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7516 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7517 = and(_T_7515, _T_7516) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7518 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7519 = and(_T_7517, _T_7518) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7520 = or(_T_7514, _T_7519) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7521 = bits(_T_7520, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7522 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7521 : @[Reg.scala 28:19]
|
|
_T_7522 <= _T_7511 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][80] <= _T_7522 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7523 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7524 = eq(_T_7523, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7525 = and(ic_valid_ff, _T_7524) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7526 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7527 = and(_T_7525, _T_7526) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7528 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7529 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7530 = and(_T_7528, _T_7529) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7531 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7532 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7533 = and(_T_7531, _T_7532) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7534 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7535 = and(_T_7533, _T_7534) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7536 = or(_T_7530, _T_7535) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7537 = bits(_T_7536, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7538 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7537 : @[Reg.scala 28:19]
|
|
_T_7538 <= _T_7527 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][81] <= _T_7538 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7539 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7540 = eq(_T_7539, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7541 = and(ic_valid_ff, _T_7540) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7542 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7543 = and(_T_7541, _T_7542) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7544 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7545 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7546 = and(_T_7544, _T_7545) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7547 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7548 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7549 = and(_T_7547, _T_7548) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7550 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7551 = and(_T_7549, _T_7550) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7552 = or(_T_7546, _T_7551) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7553 = bits(_T_7552, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7554 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7553 : @[Reg.scala 28:19]
|
|
_T_7554 <= _T_7543 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][82] <= _T_7554 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7555 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7556 = eq(_T_7555, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7557 = and(ic_valid_ff, _T_7556) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7558 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7559 = and(_T_7557, _T_7558) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7560 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7561 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7562 = and(_T_7560, _T_7561) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7563 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7564 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7565 = and(_T_7563, _T_7564) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7566 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7567 = and(_T_7565, _T_7566) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7568 = or(_T_7562, _T_7567) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7569 = bits(_T_7568, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7570 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7569 : @[Reg.scala 28:19]
|
|
_T_7570 <= _T_7559 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][83] <= _T_7570 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7571 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7572 = eq(_T_7571, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7573 = and(ic_valid_ff, _T_7572) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7574 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7575 = and(_T_7573, _T_7574) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7576 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7577 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7578 = and(_T_7576, _T_7577) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7579 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7580 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7581 = and(_T_7579, _T_7580) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7582 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7583 = and(_T_7581, _T_7582) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7584 = or(_T_7578, _T_7583) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7585 = bits(_T_7584, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7586 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7585 : @[Reg.scala 28:19]
|
|
_T_7586 <= _T_7575 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][84] <= _T_7586 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7587 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7588 = eq(_T_7587, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7589 = and(ic_valid_ff, _T_7588) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7590 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7591 = and(_T_7589, _T_7590) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7592 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7593 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7594 = and(_T_7592, _T_7593) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7595 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7596 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7597 = and(_T_7595, _T_7596) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7598 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7599 = and(_T_7597, _T_7598) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7600 = or(_T_7594, _T_7599) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7601 = bits(_T_7600, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7602 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7601 : @[Reg.scala 28:19]
|
|
_T_7602 <= _T_7591 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][85] <= _T_7602 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7603 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7604 = eq(_T_7603, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7605 = and(ic_valid_ff, _T_7604) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7606 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7607 = and(_T_7605, _T_7606) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7608 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7609 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7610 = and(_T_7608, _T_7609) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7611 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7612 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7613 = and(_T_7611, _T_7612) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7614 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7615 = and(_T_7613, _T_7614) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7616 = or(_T_7610, _T_7615) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7617 = bits(_T_7616, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7618 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7617 : @[Reg.scala 28:19]
|
|
_T_7618 <= _T_7607 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][86] <= _T_7618 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7619 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7620 = eq(_T_7619, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7621 = and(ic_valid_ff, _T_7620) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7622 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7623 = and(_T_7621, _T_7622) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7624 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7625 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7626 = and(_T_7624, _T_7625) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7627 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7628 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7629 = and(_T_7627, _T_7628) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7630 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7631 = and(_T_7629, _T_7630) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7632 = or(_T_7626, _T_7631) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7633 = bits(_T_7632, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7634 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7633 : @[Reg.scala 28:19]
|
|
_T_7634 <= _T_7623 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][87] <= _T_7634 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7635 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7636 = eq(_T_7635, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7637 = and(ic_valid_ff, _T_7636) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7638 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7639 = and(_T_7637, _T_7638) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7640 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7641 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7642 = and(_T_7640, _T_7641) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7643 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7644 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7645 = and(_T_7643, _T_7644) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7646 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7647 = and(_T_7645, _T_7646) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7648 = or(_T_7642, _T_7647) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7649 = bits(_T_7648, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7650 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7649 : @[Reg.scala 28:19]
|
|
_T_7650 <= _T_7639 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][88] <= _T_7650 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7651 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7652 = eq(_T_7651, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7653 = and(ic_valid_ff, _T_7652) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7654 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7655 = and(_T_7653, _T_7654) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7656 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7657 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7658 = and(_T_7656, _T_7657) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7659 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7660 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7661 = and(_T_7659, _T_7660) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7662 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7663 = and(_T_7661, _T_7662) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7664 = or(_T_7658, _T_7663) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7665 = bits(_T_7664, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7666 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7665 : @[Reg.scala 28:19]
|
|
_T_7666 <= _T_7655 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][89] <= _T_7666 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7667 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7668 = eq(_T_7667, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7669 = and(ic_valid_ff, _T_7668) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7670 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7671 = and(_T_7669, _T_7670) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7672 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7673 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7674 = and(_T_7672, _T_7673) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7675 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7676 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7677 = and(_T_7675, _T_7676) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7678 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7679 = and(_T_7677, _T_7678) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7680 = or(_T_7674, _T_7679) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7681 = bits(_T_7680, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7682 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7681 : @[Reg.scala 28:19]
|
|
_T_7682 <= _T_7671 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][90] <= _T_7682 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7683 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7684 = eq(_T_7683, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7685 = and(ic_valid_ff, _T_7684) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7686 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7687 = and(_T_7685, _T_7686) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7688 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7689 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7690 = and(_T_7688, _T_7689) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7691 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7692 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7693 = and(_T_7691, _T_7692) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7694 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7695 = and(_T_7693, _T_7694) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7696 = or(_T_7690, _T_7695) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7697 = bits(_T_7696, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7698 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7697 : @[Reg.scala 28:19]
|
|
_T_7698 <= _T_7687 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][91] <= _T_7698 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7699 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7700 = eq(_T_7699, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7701 = and(ic_valid_ff, _T_7700) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7702 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7703 = and(_T_7701, _T_7702) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7704 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7705 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7706 = and(_T_7704, _T_7705) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7707 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7708 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7709 = and(_T_7707, _T_7708) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7710 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7711 = and(_T_7709, _T_7710) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7712 = or(_T_7706, _T_7711) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7713 = bits(_T_7712, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7714 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7713 : @[Reg.scala 28:19]
|
|
_T_7714 <= _T_7703 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][92] <= _T_7714 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7715 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7716 = eq(_T_7715, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7717 = and(ic_valid_ff, _T_7716) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7718 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7719 = and(_T_7717, _T_7718) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7720 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7721 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7722 = and(_T_7720, _T_7721) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7723 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7724 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7725 = and(_T_7723, _T_7724) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7726 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7727 = and(_T_7725, _T_7726) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7728 = or(_T_7722, _T_7727) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7729 = bits(_T_7728, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7730 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7729 : @[Reg.scala 28:19]
|
|
_T_7730 <= _T_7719 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][93] <= _T_7730 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7731 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7732 = eq(_T_7731, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7733 = and(ic_valid_ff, _T_7732) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7734 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7735 = and(_T_7733, _T_7734) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7736 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7737 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7738 = and(_T_7736, _T_7737) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7739 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7740 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7741 = and(_T_7739, _T_7740) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7742 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7743 = and(_T_7741, _T_7742) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7744 = or(_T_7738, _T_7743) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7745 = bits(_T_7744, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7746 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7745 : @[Reg.scala 28:19]
|
|
_T_7746 <= _T_7735 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][94] <= _T_7746 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7747 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7748 = eq(_T_7747, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7749 = and(ic_valid_ff, _T_7748) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7750 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7751 = and(_T_7749, _T_7750) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7752 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7753 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7754 = and(_T_7752, _T_7753) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7755 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7756 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7757 = and(_T_7755, _T_7756) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7758 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7759 = and(_T_7757, _T_7758) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7760 = or(_T_7754, _T_7759) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7761 = bits(_T_7760, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7762 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7761 : @[Reg.scala 28:19]
|
|
_T_7762 <= _T_7751 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][95] <= _T_7762 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7763 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7764 = eq(_T_7763, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7765 = and(ic_valid_ff, _T_7764) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7766 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7767 = and(_T_7765, _T_7766) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7768 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7769 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7770 = and(_T_7768, _T_7769) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7771 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7772 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7773 = and(_T_7771, _T_7772) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7774 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7775 = and(_T_7773, _T_7774) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7776 = or(_T_7770, _T_7775) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7777 = bits(_T_7776, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7778 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7777 : @[Reg.scala 28:19]
|
|
_T_7778 <= _T_7767 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][64] <= _T_7778 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7779 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7780 = eq(_T_7779, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7781 = and(ic_valid_ff, _T_7780) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7782 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7783 = and(_T_7781, _T_7782) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7784 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7785 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7786 = and(_T_7784, _T_7785) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7787 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7788 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7789 = and(_T_7787, _T_7788) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7790 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7791 = and(_T_7789, _T_7790) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7792 = or(_T_7786, _T_7791) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7793 = bits(_T_7792, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7794 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7793 : @[Reg.scala 28:19]
|
|
_T_7794 <= _T_7783 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][65] <= _T_7794 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7795 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7796 = eq(_T_7795, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7797 = and(ic_valid_ff, _T_7796) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7799 = and(_T_7797, _T_7798) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7800 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7801 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7802 = and(_T_7800, _T_7801) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7803 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7804 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7805 = and(_T_7803, _T_7804) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7806 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7807 = and(_T_7805, _T_7806) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7808 = or(_T_7802, _T_7807) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7809 = bits(_T_7808, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7810 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7809 : @[Reg.scala 28:19]
|
|
_T_7810 <= _T_7799 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][66] <= _T_7810 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7811 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7812 = eq(_T_7811, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7813 = and(ic_valid_ff, _T_7812) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7814 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7815 = and(_T_7813, _T_7814) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7816 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7817 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7818 = and(_T_7816, _T_7817) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7819 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7820 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7821 = and(_T_7819, _T_7820) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7822 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7823 = and(_T_7821, _T_7822) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7824 = or(_T_7818, _T_7823) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7825 = bits(_T_7824, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7826 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7825 : @[Reg.scala 28:19]
|
|
_T_7826 <= _T_7815 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][67] <= _T_7826 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7827 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7828 = eq(_T_7827, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7829 = and(ic_valid_ff, _T_7828) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7830 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7831 = and(_T_7829, _T_7830) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7832 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7833 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7834 = and(_T_7832, _T_7833) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7835 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7836 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7837 = and(_T_7835, _T_7836) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7838 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7839 = and(_T_7837, _T_7838) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7840 = or(_T_7834, _T_7839) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7841 = bits(_T_7840, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7842 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7841 : @[Reg.scala 28:19]
|
|
_T_7842 <= _T_7831 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][68] <= _T_7842 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7843 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7844 = eq(_T_7843, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7845 = and(ic_valid_ff, _T_7844) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7846 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7847 = and(_T_7845, _T_7846) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7848 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7849 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7850 = and(_T_7848, _T_7849) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7851 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7852 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7853 = and(_T_7851, _T_7852) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7854 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7855 = and(_T_7853, _T_7854) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7856 = or(_T_7850, _T_7855) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7857 = bits(_T_7856, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7858 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7857 : @[Reg.scala 28:19]
|
|
_T_7858 <= _T_7847 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][69] <= _T_7858 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7859 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7860 = eq(_T_7859, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7861 = and(ic_valid_ff, _T_7860) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7862 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7863 = and(_T_7861, _T_7862) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7864 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7865 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7866 = and(_T_7864, _T_7865) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7867 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7868 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7869 = and(_T_7867, _T_7868) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7870 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7871 = and(_T_7869, _T_7870) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7872 = or(_T_7866, _T_7871) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7873 = bits(_T_7872, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7874 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7873 : @[Reg.scala 28:19]
|
|
_T_7874 <= _T_7863 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][70] <= _T_7874 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7875 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7876 = eq(_T_7875, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7877 = and(ic_valid_ff, _T_7876) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7878 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7879 = and(_T_7877, _T_7878) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7880 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7881 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7882 = and(_T_7880, _T_7881) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7883 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7884 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7885 = and(_T_7883, _T_7884) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7886 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7887 = and(_T_7885, _T_7886) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7888 = or(_T_7882, _T_7887) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7889 = bits(_T_7888, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7890 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7889 : @[Reg.scala 28:19]
|
|
_T_7890 <= _T_7879 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][71] <= _T_7890 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7891 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7892 = eq(_T_7891, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7893 = and(ic_valid_ff, _T_7892) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7894 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7895 = and(_T_7893, _T_7894) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7896 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7897 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7898 = and(_T_7896, _T_7897) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7899 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7900 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7901 = and(_T_7899, _T_7900) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7902 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7903 = and(_T_7901, _T_7902) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7904 = or(_T_7898, _T_7903) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7905 = bits(_T_7904, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7906 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7905 : @[Reg.scala 28:19]
|
|
_T_7906 <= _T_7895 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][72] <= _T_7906 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7907 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7908 = eq(_T_7907, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7909 = and(ic_valid_ff, _T_7908) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7910 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7911 = and(_T_7909, _T_7910) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7912 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7913 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7914 = and(_T_7912, _T_7913) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7915 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7916 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7917 = and(_T_7915, _T_7916) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7918 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7919 = and(_T_7917, _T_7918) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7920 = or(_T_7914, _T_7919) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7921 = bits(_T_7920, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7922 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7921 : @[Reg.scala 28:19]
|
|
_T_7922 <= _T_7911 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][73] <= _T_7922 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7923 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7924 = eq(_T_7923, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7925 = and(ic_valid_ff, _T_7924) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7926 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7927 = and(_T_7925, _T_7926) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7928 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7929 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7930 = and(_T_7928, _T_7929) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7931 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7932 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7933 = and(_T_7931, _T_7932) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7934 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7935 = and(_T_7933, _T_7934) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7936 = or(_T_7930, _T_7935) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7937 = bits(_T_7936, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7938 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7937 : @[Reg.scala 28:19]
|
|
_T_7938 <= _T_7927 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][74] <= _T_7938 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7939 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7940 = eq(_T_7939, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7941 = and(ic_valid_ff, _T_7940) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7942 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7943 = and(_T_7941, _T_7942) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7944 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7945 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7946 = and(_T_7944, _T_7945) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7947 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7948 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7949 = and(_T_7947, _T_7948) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7950 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7951 = and(_T_7949, _T_7950) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7952 = or(_T_7946, _T_7951) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7953 = bits(_T_7952, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7954 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7953 : @[Reg.scala 28:19]
|
|
_T_7954 <= _T_7943 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][75] <= _T_7954 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7955 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7956 = eq(_T_7955, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7957 = and(ic_valid_ff, _T_7956) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7958 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7959 = and(_T_7957, _T_7958) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7960 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7961 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7962 = and(_T_7960, _T_7961) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7963 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7964 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7965 = and(_T_7963, _T_7964) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7966 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7967 = and(_T_7965, _T_7966) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7968 = or(_T_7962, _T_7967) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7969 = bits(_T_7968, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7970 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7969 : @[Reg.scala 28:19]
|
|
_T_7970 <= _T_7959 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][76] <= _T_7970 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7971 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7972 = eq(_T_7971, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7973 = and(ic_valid_ff, _T_7972) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7974 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7975 = and(_T_7973, _T_7974) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7976 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7977 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7978 = and(_T_7976, _T_7977) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7979 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7980 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7981 = and(_T_7979, _T_7980) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7982 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7983 = and(_T_7981, _T_7982) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_7984 = or(_T_7978, _T_7983) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_7985 = bits(_T_7984, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_7986 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7985 : @[Reg.scala 28:19]
|
|
_T_7986 <= _T_7975 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][77] <= _T_7986 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_7987 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_7988 = eq(_T_7987, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_7989 = and(ic_valid_ff, _T_7988) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_7990 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_7991 = and(_T_7989, _T_7990) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_7992 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_7993 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_7994 = and(_T_7992, _T_7993) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_7995 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_7996 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_7997 = and(_T_7995, _T_7996) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_7998 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_7999 = and(_T_7997, _T_7998) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8000 = or(_T_7994, _T_7999) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8001 = bits(_T_8000, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8002 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8001 : @[Reg.scala 28:19]
|
|
_T_8002 <= _T_7991 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][78] <= _T_8002 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8003 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8004 = eq(_T_8003, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8005 = and(ic_valid_ff, _T_8004) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8006 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8007 = and(_T_8005, _T_8006) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8008 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8009 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8010 = and(_T_8008, _T_8009) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8011 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8012 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8013 = and(_T_8011, _T_8012) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8014 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8015 = and(_T_8013, _T_8014) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8016 = or(_T_8010, _T_8015) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8017 = bits(_T_8016, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8018 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8017 : @[Reg.scala 28:19]
|
|
_T_8018 <= _T_8007 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][79] <= _T_8018 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8019 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8020 = eq(_T_8019, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8021 = and(ic_valid_ff, _T_8020) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8022 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8023 = and(_T_8021, _T_8022) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8024 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8025 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8026 = and(_T_8024, _T_8025) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8027 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8028 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8029 = and(_T_8027, _T_8028) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8030 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8031 = and(_T_8029, _T_8030) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8032 = or(_T_8026, _T_8031) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8033 = bits(_T_8032, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8034 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8033 : @[Reg.scala 28:19]
|
|
_T_8034 <= _T_8023 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][80] <= _T_8034 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8035 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8036 = eq(_T_8035, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8037 = and(ic_valid_ff, _T_8036) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8038 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8039 = and(_T_8037, _T_8038) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8040 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8041 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8042 = and(_T_8040, _T_8041) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8043 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8044 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8045 = and(_T_8043, _T_8044) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8046 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8047 = and(_T_8045, _T_8046) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8048 = or(_T_8042, _T_8047) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8049 = bits(_T_8048, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8050 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8049 : @[Reg.scala 28:19]
|
|
_T_8050 <= _T_8039 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][81] <= _T_8050 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8051 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8052 = eq(_T_8051, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8053 = and(ic_valid_ff, _T_8052) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8054 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8055 = and(_T_8053, _T_8054) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8056 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8057 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8058 = and(_T_8056, _T_8057) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8059 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8060 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8061 = and(_T_8059, _T_8060) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8062 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8063 = and(_T_8061, _T_8062) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8064 = or(_T_8058, _T_8063) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8065 = bits(_T_8064, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8066 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8065 : @[Reg.scala 28:19]
|
|
_T_8066 <= _T_8055 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][82] <= _T_8066 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8067 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8068 = eq(_T_8067, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8069 = and(ic_valid_ff, _T_8068) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8070 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8071 = and(_T_8069, _T_8070) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8072 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8073 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8074 = and(_T_8072, _T_8073) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8075 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8076 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8077 = and(_T_8075, _T_8076) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8078 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8079 = and(_T_8077, _T_8078) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8080 = or(_T_8074, _T_8079) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8081 = bits(_T_8080, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8082 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8081 : @[Reg.scala 28:19]
|
|
_T_8082 <= _T_8071 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][83] <= _T_8082 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8083 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8084 = eq(_T_8083, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8085 = and(ic_valid_ff, _T_8084) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8086 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8087 = and(_T_8085, _T_8086) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8088 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8089 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8090 = and(_T_8088, _T_8089) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8091 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8092 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8093 = and(_T_8091, _T_8092) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8094 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8095 = and(_T_8093, _T_8094) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8096 = or(_T_8090, _T_8095) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8097 = bits(_T_8096, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8098 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8097 : @[Reg.scala 28:19]
|
|
_T_8098 <= _T_8087 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][84] <= _T_8098 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8099 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8100 = eq(_T_8099, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8101 = and(ic_valid_ff, _T_8100) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8102 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8103 = and(_T_8101, _T_8102) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8104 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8105 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8106 = and(_T_8104, _T_8105) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8107 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8108 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8109 = and(_T_8107, _T_8108) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8110 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8111 = and(_T_8109, _T_8110) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8112 = or(_T_8106, _T_8111) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8113 = bits(_T_8112, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8114 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8113 : @[Reg.scala 28:19]
|
|
_T_8114 <= _T_8103 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][85] <= _T_8114 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8115 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8116 = eq(_T_8115, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8117 = and(ic_valid_ff, _T_8116) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8118 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8119 = and(_T_8117, _T_8118) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8120 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8121 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8122 = and(_T_8120, _T_8121) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8123 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8124 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8125 = and(_T_8123, _T_8124) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8126 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8127 = and(_T_8125, _T_8126) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8128 = or(_T_8122, _T_8127) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8129 = bits(_T_8128, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8130 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8129 : @[Reg.scala 28:19]
|
|
_T_8130 <= _T_8119 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][86] <= _T_8130 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8131 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8132 = eq(_T_8131, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8133 = and(ic_valid_ff, _T_8132) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8134 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8135 = and(_T_8133, _T_8134) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8136 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8137 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8138 = and(_T_8136, _T_8137) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8139 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8140 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8141 = and(_T_8139, _T_8140) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8142 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8143 = and(_T_8141, _T_8142) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8144 = or(_T_8138, _T_8143) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8145 = bits(_T_8144, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8146 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8145 : @[Reg.scala 28:19]
|
|
_T_8146 <= _T_8135 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][87] <= _T_8146 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8147 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8148 = eq(_T_8147, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8149 = and(ic_valid_ff, _T_8148) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8150 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8151 = and(_T_8149, _T_8150) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8152 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8153 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8154 = and(_T_8152, _T_8153) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8155 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8156 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8157 = and(_T_8155, _T_8156) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8158 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8159 = and(_T_8157, _T_8158) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8160 = or(_T_8154, _T_8159) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8161 = bits(_T_8160, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8162 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8161 : @[Reg.scala 28:19]
|
|
_T_8162 <= _T_8151 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][88] <= _T_8162 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8163 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8164 = eq(_T_8163, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8165 = and(ic_valid_ff, _T_8164) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8166 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8167 = and(_T_8165, _T_8166) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8168 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8169 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8170 = and(_T_8168, _T_8169) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8171 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8172 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8173 = and(_T_8171, _T_8172) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8174 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8175 = and(_T_8173, _T_8174) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8176 = or(_T_8170, _T_8175) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8177 = bits(_T_8176, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8178 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8177 : @[Reg.scala 28:19]
|
|
_T_8178 <= _T_8167 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][89] <= _T_8178 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8179 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8180 = eq(_T_8179, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8181 = and(ic_valid_ff, _T_8180) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8182 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8183 = and(_T_8181, _T_8182) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8184 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8185 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8186 = and(_T_8184, _T_8185) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8187 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8188 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8189 = and(_T_8187, _T_8188) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8190 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8191 = and(_T_8189, _T_8190) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8192 = or(_T_8186, _T_8191) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8193 = bits(_T_8192, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8194 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8193 : @[Reg.scala 28:19]
|
|
_T_8194 <= _T_8183 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][90] <= _T_8194 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8195 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8196 = eq(_T_8195, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8197 = and(ic_valid_ff, _T_8196) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8199 = and(_T_8197, _T_8198) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8201 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8202 = and(_T_8200, _T_8201) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8203 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8204 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8205 = and(_T_8203, _T_8204) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8206 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8207 = and(_T_8205, _T_8206) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8208 = or(_T_8202, _T_8207) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8209 = bits(_T_8208, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8210 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8209 : @[Reg.scala 28:19]
|
|
_T_8210 <= _T_8199 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][91] <= _T_8210 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8211 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8212 = eq(_T_8211, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8213 = and(ic_valid_ff, _T_8212) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8214 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8215 = and(_T_8213, _T_8214) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8216 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8217 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8218 = and(_T_8216, _T_8217) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8219 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8220 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8221 = and(_T_8219, _T_8220) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8222 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8223 = and(_T_8221, _T_8222) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8224 = or(_T_8218, _T_8223) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8225 = bits(_T_8224, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8226 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8225 : @[Reg.scala 28:19]
|
|
_T_8226 <= _T_8215 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][92] <= _T_8226 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8227 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8228 = eq(_T_8227, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8229 = and(ic_valid_ff, _T_8228) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8230 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8231 = and(_T_8229, _T_8230) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8232 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8233 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8234 = and(_T_8232, _T_8233) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8235 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8236 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8237 = and(_T_8235, _T_8236) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8238 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8239 = and(_T_8237, _T_8238) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8240 = or(_T_8234, _T_8239) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8241 = bits(_T_8240, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8242 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8241 : @[Reg.scala 28:19]
|
|
_T_8242 <= _T_8231 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][93] <= _T_8242 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8243 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8244 = eq(_T_8243, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8245 = and(ic_valid_ff, _T_8244) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8246 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8247 = and(_T_8245, _T_8246) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8248 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8249 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8250 = and(_T_8248, _T_8249) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8251 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8252 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8253 = and(_T_8251, _T_8252) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8254 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8255 = and(_T_8253, _T_8254) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8256 = or(_T_8250, _T_8255) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8257 = bits(_T_8256, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8258 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8257 : @[Reg.scala 28:19]
|
|
_T_8258 <= _T_8247 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][94] <= _T_8258 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8259 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8260 = eq(_T_8259, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8261 = and(ic_valid_ff, _T_8260) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8262 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8263 = and(_T_8261, _T_8262) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8264 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8265 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8266 = and(_T_8264, _T_8265) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8267 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8268 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8269 = and(_T_8267, _T_8268) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8270 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8271 = and(_T_8269, _T_8270) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8272 = or(_T_8266, _T_8271) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8273 = bits(_T_8272, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8274 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8273 : @[Reg.scala 28:19]
|
|
_T_8274 <= _T_8263 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][95] <= _T_8274 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8275 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8276 = eq(_T_8275, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8277 = and(ic_valid_ff, _T_8276) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8278 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8279 = and(_T_8277, _T_8278) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8280 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8281 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8282 = and(_T_8280, _T_8281) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8283 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8284 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8285 = and(_T_8283, _T_8284) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8286 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8287 = and(_T_8285, _T_8286) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8288 = or(_T_8282, _T_8287) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8289 = bits(_T_8288, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8290 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8289 : @[Reg.scala 28:19]
|
|
_T_8290 <= _T_8279 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][96] <= _T_8290 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8291 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8292 = eq(_T_8291, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8293 = and(ic_valid_ff, _T_8292) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8294 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8295 = and(_T_8293, _T_8294) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8296 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8297 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8298 = and(_T_8296, _T_8297) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8299 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8300 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8301 = and(_T_8299, _T_8300) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8302 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8303 = and(_T_8301, _T_8302) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8304 = or(_T_8298, _T_8303) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8305 = bits(_T_8304, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8306 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8305 : @[Reg.scala 28:19]
|
|
_T_8306 <= _T_8295 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][97] <= _T_8306 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8307 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8308 = eq(_T_8307, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8309 = and(ic_valid_ff, _T_8308) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8310 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8311 = and(_T_8309, _T_8310) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8312 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8313 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8314 = and(_T_8312, _T_8313) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8315 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8316 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8317 = and(_T_8315, _T_8316) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8318 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8319 = and(_T_8317, _T_8318) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8320 = or(_T_8314, _T_8319) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8321 = bits(_T_8320, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8322 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8321 : @[Reg.scala 28:19]
|
|
_T_8322 <= _T_8311 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][98] <= _T_8322 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8323 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8324 = eq(_T_8323, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8325 = and(ic_valid_ff, _T_8324) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8326 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8327 = and(_T_8325, _T_8326) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8328 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8329 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8330 = and(_T_8328, _T_8329) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8331 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8332 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8333 = and(_T_8331, _T_8332) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8334 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8335 = and(_T_8333, _T_8334) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8336 = or(_T_8330, _T_8335) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8337 = bits(_T_8336, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8338 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8337 : @[Reg.scala 28:19]
|
|
_T_8338 <= _T_8327 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][99] <= _T_8338 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8339 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8340 = eq(_T_8339, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8341 = and(ic_valid_ff, _T_8340) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8342 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8343 = and(_T_8341, _T_8342) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8344 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8345 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8346 = and(_T_8344, _T_8345) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8347 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8348 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8349 = and(_T_8347, _T_8348) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8350 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8351 = and(_T_8349, _T_8350) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8352 = or(_T_8346, _T_8351) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8353 = bits(_T_8352, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8354 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8353 : @[Reg.scala 28:19]
|
|
_T_8354 <= _T_8343 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][100] <= _T_8354 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8355 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8356 = eq(_T_8355, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8357 = and(ic_valid_ff, _T_8356) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8358 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8359 = and(_T_8357, _T_8358) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8360 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8361 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8362 = and(_T_8360, _T_8361) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8363 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8364 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8365 = and(_T_8363, _T_8364) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8366 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8367 = and(_T_8365, _T_8366) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8368 = or(_T_8362, _T_8367) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8369 = bits(_T_8368, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8370 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8369 : @[Reg.scala 28:19]
|
|
_T_8370 <= _T_8359 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][101] <= _T_8370 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8371 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8372 = eq(_T_8371, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8373 = and(ic_valid_ff, _T_8372) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8374 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8375 = and(_T_8373, _T_8374) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8376 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8377 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8378 = and(_T_8376, _T_8377) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8379 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8380 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8381 = and(_T_8379, _T_8380) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8382 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8383 = and(_T_8381, _T_8382) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8384 = or(_T_8378, _T_8383) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8385 = bits(_T_8384, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8386 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8385 : @[Reg.scala 28:19]
|
|
_T_8386 <= _T_8375 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][102] <= _T_8386 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8387 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8388 = eq(_T_8387, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8389 = and(ic_valid_ff, _T_8388) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8390 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8391 = and(_T_8389, _T_8390) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8392 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8393 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8394 = and(_T_8392, _T_8393) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8395 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8396 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8397 = and(_T_8395, _T_8396) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8398 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8399 = and(_T_8397, _T_8398) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8400 = or(_T_8394, _T_8399) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8401 = bits(_T_8400, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8402 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8401 : @[Reg.scala 28:19]
|
|
_T_8402 <= _T_8391 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][103] <= _T_8402 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8403 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8404 = eq(_T_8403, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8405 = and(ic_valid_ff, _T_8404) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8406 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8407 = and(_T_8405, _T_8406) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8408 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8409 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8410 = and(_T_8408, _T_8409) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8411 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8412 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8413 = and(_T_8411, _T_8412) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8414 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8415 = and(_T_8413, _T_8414) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8416 = or(_T_8410, _T_8415) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8417 = bits(_T_8416, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8418 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8417 : @[Reg.scala 28:19]
|
|
_T_8418 <= _T_8407 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][104] <= _T_8418 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8419 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8420 = eq(_T_8419, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8421 = and(ic_valid_ff, _T_8420) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8422 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8423 = and(_T_8421, _T_8422) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8424 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8425 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8426 = and(_T_8424, _T_8425) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8427 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8428 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8429 = and(_T_8427, _T_8428) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8430 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8431 = and(_T_8429, _T_8430) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8432 = or(_T_8426, _T_8431) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8433 = bits(_T_8432, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8434 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8433 : @[Reg.scala 28:19]
|
|
_T_8434 <= _T_8423 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][105] <= _T_8434 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8435 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8436 = eq(_T_8435, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8437 = and(ic_valid_ff, _T_8436) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8438 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8439 = and(_T_8437, _T_8438) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8440 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8441 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8442 = and(_T_8440, _T_8441) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8443 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8444 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8445 = and(_T_8443, _T_8444) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8446 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8447 = and(_T_8445, _T_8446) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8448 = or(_T_8442, _T_8447) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8449 = bits(_T_8448, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8450 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8449 : @[Reg.scala 28:19]
|
|
_T_8450 <= _T_8439 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][106] <= _T_8450 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8451 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8452 = eq(_T_8451, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8453 = and(ic_valid_ff, _T_8452) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8454 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8455 = and(_T_8453, _T_8454) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8456 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8457 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8458 = and(_T_8456, _T_8457) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8459 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8460 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8461 = and(_T_8459, _T_8460) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8462 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8463 = and(_T_8461, _T_8462) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8464 = or(_T_8458, _T_8463) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8465 = bits(_T_8464, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8466 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8465 : @[Reg.scala 28:19]
|
|
_T_8466 <= _T_8455 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][107] <= _T_8466 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8467 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8468 = eq(_T_8467, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8469 = and(ic_valid_ff, _T_8468) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8470 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8471 = and(_T_8469, _T_8470) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8472 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8473 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8474 = and(_T_8472, _T_8473) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8475 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8476 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8477 = and(_T_8475, _T_8476) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8478 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8479 = and(_T_8477, _T_8478) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8480 = or(_T_8474, _T_8479) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8481 = bits(_T_8480, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8482 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8481 : @[Reg.scala 28:19]
|
|
_T_8482 <= _T_8471 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][108] <= _T_8482 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8483 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8484 = eq(_T_8483, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8485 = and(ic_valid_ff, _T_8484) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8486 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8487 = and(_T_8485, _T_8486) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8488 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8489 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8490 = and(_T_8488, _T_8489) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8491 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8492 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8493 = and(_T_8491, _T_8492) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8494 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8495 = and(_T_8493, _T_8494) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8496 = or(_T_8490, _T_8495) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8497 = bits(_T_8496, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8498 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8497 : @[Reg.scala 28:19]
|
|
_T_8498 <= _T_8487 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][109] <= _T_8498 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8499 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8500 = eq(_T_8499, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8501 = and(ic_valid_ff, _T_8500) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8502 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8503 = and(_T_8501, _T_8502) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8504 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8505 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8506 = and(_T_8504, _T_8505) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8507 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8508 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8509 = and(_T_8507, _T_8508) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8510 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8511 = and(_T_8509, _T_8510) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8512 = or(_T_8506, _T_8511) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8513 = bits(_T_8512, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8514 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8513 : @[Reg.scala 28:19]
|
|
_T_8514 <= _T_8503 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][110] <= _T_8514 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8515 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8516 = eq(_T_8515, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8517 = and(ic_valid_ff, _T_8516) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8518 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8519 = and(_T_8517, _T_8518) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8520 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8521 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8522 = and(_T_8520, _T_8521) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8523 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8524 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8525 = and(_T_8523, _T_8524) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8526 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8527 = and(_T_8525, _T_8526) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8528 = or(_T_8522, _T_8527) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8529 = bits(_T_8528, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8530 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8529 : @[Reg.scala 28:19]
|
|
_T_8530 <= _T_8519 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][111] <= _T_8530 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8531 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8532 = eq(_T_8531, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8533 = and(ic_valid_ff, _T_8532) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8534 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8535 = and(_T_8533, _T_8534) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8536 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8537 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8538 = and(_T_8536, _T_8537) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8539 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8540 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8541 = and(_T_8539, _T_8540) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8542 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8543 = and(_T_8541, _T_8542) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8544 = or(_T_8538, _T_8543) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8545 = bits(_T_8544, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8546 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8545 : @[Reg.scala 28:19]
|
|
_T_8546 <= _T_8535 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][112] <= _T_8546 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8547 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8548 = eq(_T_8547, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8549 = and(ic_valid_ff, _T_8548) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8550 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8551 = and(_T_8549, _T_8550) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8552 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8553 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8554 = and(_T_8552, _T_8553) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8555 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8556 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8557 = and(_T_8555, _T_8556) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8558 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8559 = and(_T_8557, _T_8558) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8560 = or(_T_8554, _T_8559) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8561 = bits(_T_8560, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8562 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8561 : @[Reg.scala 28:19]
|
|
_T_8562 <= _T_8551 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][113] <= _T_8562 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8563 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8564 = eq(_T_8563, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8565 = and(ic_valid_ff, _T_8564) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8566 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8567 = and(_T_8565, _T_8566) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8568 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8569 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8570 = and(_T_8568, _T_8569) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8571 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8572 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8573 = and(_T_8571, _T_8572) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8574 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8575 = and(_T_8573, _T_8574) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8576 = or(_T_8570, _T_8575) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8577 = bits(_T_8576, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8578 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8577 : @[Reg.scala 28:19]
|
|
_T_8578 <= _T_8567 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][114] <= _T_8578 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8579 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8580 = eq(_T_8579, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8581 = and(ic_valid_ff, _T_8580) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8582 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8583 = and(_T_8581, _T_8582) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8584 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8585 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8586 = and(_T_8584, _T_8585) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8587 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8588 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8589 = and(_T_8587, _T_8588) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8590 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8591 = and(_T_8589, _T_8590) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8592 = or(_T_8586, _T_8591) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8593 = bits(_T_8592, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8594 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8593 : @[Reg.scala 28:19]
|
|
_T_8594 <= _T_8583 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][115] <= _T_8594 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8595 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8596 = eq(_T_8595, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8597 = and(ic_valid_ff, _T_8596) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8598 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8599 = and(_T_8597, _T_8598) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8600 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8601 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8602 = and(_T_8600, _T_8601) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8603 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8604 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8605 = and(_T_8603, _T_8604) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8606 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8607 = and(_T_8605, _T_8606) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8608 = or(_T_8602, _T_8607) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8609 = bits(_T_8608, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8610 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8609 : @[Reg.scala 28:19]
|
|
_T_8610 <= _T_8599 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][116] <= _T_8610 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8611 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8612 = eq(_T_8611, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8613 = and(ic_valid_ff, _T_8612) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8614 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8615 = and(_T_8613, _T_8614) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8616 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8617 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8618 = and(_T_8616, _T_8617) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8619 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8620 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8621 = and(_T_8619, _T_8620) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8622 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8623 = and(_T_8621, _T_8622) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8624 = or(_T_8618, _T_8623) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8625 = bits(_T_8624, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8626 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8625 : @[Reg.scala 28:19]
|
|
_T_8626 <= _T_8615 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][117] <= _T_8626 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8627 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8628 = eq(_T_8627, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8629 = and(ic_valid_ff, _T_8628) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8630 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8631 = and(_T_8629, _T_8630) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8632 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8633 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8634 = and(_T_8632, _T_8633) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8635 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8636 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8637 = and(_T_8635, _T_8636) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8638 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8639 = and(_T_8637, _T_8638) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8640 = or(_T_8634, _T_8639) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8641 = bits(_T_8640, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8642 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8641 : @[Reg.scala 28:19]
|
|
_T_8642 <= _T_8631 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][118] <= _T_8642 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8643 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8644 = eq(_T_8643, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8645 = and(ic_valid_ff, _T_8644) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8646 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8647 = and(_T_8645, _T_8646) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8648 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8649 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8650 = and(_T_8648, _T_8649) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8651 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8652 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8653 = and(_T_8651, _T_8652) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8654 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8655 = and(_T_8653, _T_8654) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8656 = or(_T_8650, _T_8655) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8657 = bits(_T_8656, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8658 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8657 : @[Reg.scala 28:19]
|
|
_T_8658 <= _T_8647 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][119] <= _T_8658 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8659 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8660 = eq(_T_8659, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8661 = and(ic_valid_ff, _T_8660) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8662 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8663 = and(_T_8661, _T_8662) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8664 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8665 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8666 = and(_T_8664, _T_8665) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8667 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8668 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8669 = and(_T_8667, _T_8668) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8670 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8671 = and(_T_8669, _T_8670) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8672 = or(_T_8666, _T_8671) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8673 = bits(_T_8672, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8674 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8673 : @[Reg.scala 28:19]
|
|
_T_8674 <= _T_8663 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][120] <= _T_8674 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8675 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8676 = eq(_T_8675, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8677 = and(ic_valid_ff, _T_8676) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8678 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8679 = and(_T_8677, _T_8678) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8680 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8681 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8682 = and(_T_8680, _T_8681) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8683 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8684 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8685 = and(_T_8683, _T_8684) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8686 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8687 = and(_T_8685, _T_8686) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8688 = or(_T_8682, _T_8687) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8689 = bits(_T_8688, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8690 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8689 : @[Reg.scala 28:19]
|
|
_T_8690 <= _T_8679 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][121] <= _T_8690 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8691 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8692 = eq(_T_8691, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8693 = and(ic_valid_ff, _T_8692) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8694 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8695 = and(_T_8693, _T_8694) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8696 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8697 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8698 = and(_T_8696, _T_8697) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8699 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8700 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8701 = and(_T_8699, _T_8700) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8702 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8703 = and(_T_8701, _T_8702) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8704 = or(_T_8698, _T_8703) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8705 = bits(_T_8704, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8706 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8705 : @[Reg.scala 28:19]
|
|
_T_8706 <= _T_8695 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][122] <= _T_8706 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8707 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8708 = eq(_T_8707, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8709 = and(ic_valid_ff, _T_8708) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8710 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8711 = and(_T_8709, _T_8710) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8712 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8713 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8714 = and(_T_8712, _T_8713) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8715 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8716 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8717 = and(_T_8715, _T_8716) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8718 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8719 = and(_T_8717, _T_8718) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8720 = or(_T_8714, _T_8719) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8721 = bits(_T_8720, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8722 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8721 : @[Reg.scala 28:19]
|
|
_T_8722 <= _T_8711 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][123] <= _T_8722 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8723 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8724 = eq(_T_8723, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8725 = and(ic_valid_ff, _T_8724) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8726 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8727 = and(_T_8725, _T_8726) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8728 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8729 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8730 = and(_T_8728, _T_8729) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8731 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8732 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8733 = and(_T_8731, _T_8732) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8734 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8735 = and(_T_8733, _T_8734) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8736 = or(_T_8730, _T_8735) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8737 = bits(_T_8736, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8738 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8737 : @[Reg.scala 28:19]
|
|
_T_8738 <= _T_8727 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][124] <= _T_8738 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8739 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8740 = eq(_T_8739, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8741 = and(ic_valid_ff, _T_8740) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8742 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8743 = and(_T_8741, _T_8742) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8744 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8745 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8746 = and(_T_8744, _T_8745) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8747 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8748 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8749 = and(_T_8747, _T_8748) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8750 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8751 = and(_T_8749, _T_8750) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8752 = or(_T_8746, _T_8751) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8753 = bits(_T_8752, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8754 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8753 : @[Reg.scala 28:19]
|
|
_T_8754 <= _T_8743 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][125] <= _T_8754 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8755 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8756 = eq(_T_8755, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8757 = and(ic_valid_ff, _T_8756) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8758 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8759 = and(_T_8757, _T_8758) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8760 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8761 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8762 = and(_T_8760, _T_8761) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8763 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8764 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8765 = and(_T_8763, _T_8764) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8766 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8767 = and(_T_8765, _T_8766) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8768 = or(_T_8762, _T_8767) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8769 = bits(_T_8768, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8770 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8769 : @[Reg.scala 28:19]
|
|
_T_8770 <= _T_8759 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][126] <= _T_8770 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8771 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8772 = eq(_T_8771, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8773 = and(ic_valid_ff, _T_8772) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8774 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8775 = and(_T_8773, _T_8774) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8776 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8777 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8778 = and(_T_8776, _T_8777) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8779 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8780 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8781 = and(_T_8779, _T_8780) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8782 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8783 = and(_T_8781, _T_8782) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8784 = or(_T_8778, _T_8783) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8785 = bits(_T_8784, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8786 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8785 : @[Reg.scala 28:19]
|
|
_T_8786 <= _T_8775 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][127] <= _T_8786 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8787 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8788 = eq(_T_8787, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8789 = and(ic_valid_ff, _T_8788) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8790 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8791 = and(_T_8789, _T_8790) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8792 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8793 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8794 = and(_T_8792, _T_8793) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8795 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8796 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8797 = and(_T_8795, _T_8796) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8798 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8799 = and(_T_8797, _T_8798) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8800 = or(_T_8794, _T_8799) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8801 = bits(_T_8800, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8802 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8801 : @[Reg.scala 28:19]
|
|
_T_8802 <= _T_8791 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][96] <= _T_8802 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8803 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8804 = eq(_T_8803, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8805 = and(ic_valid_ff, _T_8804) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8806 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8807 = and(_T_8805, _T_8806) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8808 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8809 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8810 = and(_T_8808, _T_8809) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8811 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8812 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8813 = and(_T_8811, _T_8812) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8814 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8815 = and(_T_8813, _T_8814) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8816 = or(_T_8810, _T_8815) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8817 = bits(_T_8816, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8818 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8817 : @[Reg.scala 28:19]
|
|
_T_8818 <= _T_8807 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][97] <= _T_8818 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8819 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8820 = eq(_T_8819, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8821 = and(ic_valid_ff, _T_8820) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8822 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8823 = and(_T_8821, _T_8822) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8824 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8825 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8826 = and(_T_8824, _T_8825) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8827 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8828 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8829 = and(_T_8827, _T_8828) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8830 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8831 = and(_T_8829, _T_8830) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8832 = or(_T_8826, _T_8831) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8833 = bits(_T_8832, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8834 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8833 : @[Reg.scala 28:19]
|
|
_T_8834 <= _T_8823 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][98] <= _T_8834 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8835 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8836 = eq(_T_8835, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8837 = and(ic_valid_ff, _T_8836) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8838 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8839 = and(_T_8837, _T_8838) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8841 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8842 = and(_T_8840, _T_8841) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8843 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8844 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8845 = and(_T_8843, _T_8844) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8846 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8847 = and(_T_8845, _T_8846) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8848 = or(_T_8842, _T_8847) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8849 = bits(_T_8848, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8850 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8849 : @[Reg.scala 28:19]
|
|
_T_8850 <= _T_8839 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][99] <= _T_8850 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8851 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8852 = eq(_T_8851, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8853 = and(ic_valid_ff, _T_8852) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8854 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8855 = and(_T_8853, _T_8854) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8856 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8857 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8858 = and(_T_8856, _T_8857) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8859 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8860 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8861 = and(_T_8859, _T_8860) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8862 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8863 = and(_T_8861, _T_8862) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8864 = or(_T_8858, _T_8863) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8865 = bits(_T_8864, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8866 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8865 : @[Reg.scala 28:19]
|
|
_T_8866 <= _T_8855 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][100] <= _T_8866 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8867 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8868 = eq(_T_8867, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8869 = and(ic_valid_ff, _T_8868) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8870 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8871 = and(_T_8869, _T_8870) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8872 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8873 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8874 = and(_T_8872, _T_8873) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8875 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8876 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8877 = and(_T_8875, _T_8876) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8878 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8879 = and(_T_8877, _T_8878) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8880 = or(_T_8874, _T_8879) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8881 = bits(_T_8880, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8882 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8881 : @[Reg.scala 28:19]
|
|
_T_8882 <= _T_8871 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][101] <= _T_8882 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8883 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8884 = eq(_T_8883, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8885 = and(ic_valid_ff, _T_8884) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8886 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8887 = and(_T_8885, _T_8886) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8888 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8889 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8890 = and(_T_8888, _T_8889) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8891 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8892 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8893 = and(_T_8891, _T_8892) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8894 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8895 = and(_T_8893, _T_8894) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8896 = or(_T_8890, _T_8895) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8897 = bits(_T_8896, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8898 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8897 : @[Reg.scala 28:19]
|
|
_T_8898 <= _T_8887 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][102] <= _T_8898 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8899 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8900 = eq(_T_8899, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8901 = and(ic_valid_ff, _T_8900) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8902 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8903 = and(_T_8901, _T_8902) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8904 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8905 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8906 = and(_T_8904, _T_8905) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8907 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8908 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8909 = and(_T_8907, _T_8908) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8910 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8911 = and(_T_8909, _T_8910) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8912 = or(_T_8906, _T_8911) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8913 = bits(_T_8912, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8914 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8913 : @[Reg.scala 28:19]
|
|
_T_8914 <= _T_8903 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][103] <= _T_8914 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8915 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8916 = eq(_T_8915, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8917 = and(ic_valid_ff, _T_8916) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8918 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8919 = and(_T_8917, _T_8918) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8920 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8921 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8922 = and(_T_8920, _T_8921) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8923 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8924 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8925 = and(_T_8923, _T_8924) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8926 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8927 = and(_T_8925, _T_8926) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8928 = or(_T_8922, _T_8927) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8929 = bits(_T_8928, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8930 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8929 : @[Reg.scala 28:19]
|
|
_T_8930 <= _T_8919 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][104] <= _T_8930 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8931 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8932 = eq(_T_8931, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8933 = and(ic_valid_ff, _T_8932) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8934 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8935 = and(_T_8933, _T_8934) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8936 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8937 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8938 = and(_T_8936, _T_8937) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8939 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8940 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8941 = and(_T_8939, _T_8940) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8942 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8943 = and(_T_8941, _T_8942) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8944 = or(_T_8938, _T_8943) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8945 = bits(_T_8944, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8946 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8945 : @[Reg.scala 28:19]
|
|
_T_8946 <= _T_8935 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][105] <= _T_8946 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8947 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8948 = eq(_T_8947, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8949 = and(ic_valid_ff, _T_8948) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8950 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8951 = and(_T_8949, _T_8950) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8952 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8953 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8954 = and(_T_8952, _T_8953) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8955 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8956 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8957 = and(_T_8955, _T_8956) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8958 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8959 = and(_T_8957, _T_8958) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8960 = or(_T_8954, _T_8959) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8961 = bits(_T_8960, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8962 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8961 : @[Reg.scala 28:19]
|
|
_T_8962 <= _T_8951 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][106] <= _T_8962 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8963 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8964 = eq(_T_8963, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8965 = and(ic_valid_ff, _T_8964) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8966 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8967 = and(_T_8965, _T_8966) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8968 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8969 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8970 = and(_T_8968, _T_8969) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8971 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8972 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8973 = and(_T_8971, _T_8972) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8974 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8975 = and(_T_8973, _T_8974) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8976 = or(_T_8970, _T_8975) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8977 = bits(_T_8976, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8978 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8977 : @[Reg.scala 28:19]
|
|
_T_8978 <= _T_8967 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][107] <= _T_8978 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8979 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8980 = eq(_T_8979, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8981 = and(ic_valid_ff, _T_8980) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8982 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8983 = and(_T_8981, _T_8982) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_8984 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_8985 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_8986 = and(_T_8984, _T_8985) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_8987 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_8988 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_8989 = and(_T_8987, _T_8988) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_8990 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_8991 = and(_T_8989, _T_8990) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_8992 = or(_T_8986, _T_8991) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_8993 = bits(_T_8992, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_8994 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8993 : @[Reg.scala 28:19]
|
|
_T_8994 <= _T_8983 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][108] <= _T_8994 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_8995 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_8996 = eq(_T_8995, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_8997 = and(ic_valid_ff, _T_8996) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_8998 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_8999 = and(_T_8997, _T_8998) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9000 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9001 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9002 = and(_T_9000, _T_9001) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9003 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9004 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9005 = and(_T_9003, _T_9004) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9006 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9007 = and(_T_9005, _T_9006) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9008 = or(_T_9002, _T_9007) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9009 = bits(_T_9008, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9010 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9009 : @[Reg.scala 28:19]
|
|
_T_9010 <= _T_8999 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][109] <= _T_9010 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9011 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9012 = eq(_T_9011, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9013 = and(ic_valid_ff, _T_9012) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9014 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9015 = and(_T_9013, _T_9014) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9016 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9017 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9018 = and(_T_9016, _T_9017) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9019 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9020 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9021 = and(_T_9019, _T_9020) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9022 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9023 = and(_T_9021, _T_9022) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9024 = or(_T_9018, _T_9023) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9025 = bits(_T_9024, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9026 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9025 : @[Reg.scala 28:19]
|
|
_T_9026 <= _T_9015 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][110] <= _T_9026 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9027 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9028 = eq(_T_9027, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9029 = and(ic_valid_ff, _T_9028) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9030 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9031 = and(_T_9029, _T_9030) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9032 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9033 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9034 = and(_T_9032, _T_9033) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9035 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9036 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9037 = and(_T_9035, _T_9036) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9038 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9039 = and(_T_9037, _T_9038) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9040 = or(_T_9034, _T_9039) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9041 = bits(_T_9040, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9042 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9041 : @[Reg.scala 28:19]
|
|
_T_9042 <= _T_9031 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][111] <= _T_9042 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9043 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9044 = eq(_T_9043, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9045 = and(ic_valid_ff, _T_9044) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9046 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9047 = and(_T_9045, _T_9046) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9048 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9049 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9050 = and(_T_9048, _T_9049) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9051 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9052 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9053 = and(_T_9051, _T_9052) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9054 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9055 = and(_T_9053, _T_9054) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9056 = or(_T_9050, _T_9055) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9057 = bits(_T_9056, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9058 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9057 : @[Reg.scala 28:19]
|
|
_T_9058 <= _T_9047 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][112] <= _T_9058 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9059 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9060 = eq(_T_9059, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9061 = and(ic_valid_ff, _T_9060) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9062 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9063 = and(_T_9061, _T_9062) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9064 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9065 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9066 = and(_T_9064, _T_9065) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9067 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9068 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9069 = and(_T_9067, _T_9068) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9070 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9071 = and(_T_9069, _T_9070) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9072 = or(_T_9066, _T_9071) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9073 = bits(_T_9072, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9074 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9073 : @[Reg.scala 28:19]
|
|
_T_9074 <= _T_9063 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][113] <= _T_9074 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9075 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9076 = eq(_T_9075, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9077 = and(ic_valid_ff, _T_9076) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9078 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9079 = and(_T_9077, _T_9078) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9080 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9081 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9082 = and(_T_9080, _T_9081) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9083 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9084 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9085 = and(_T_9083, _T_9084) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9086 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9087 = and(_T_9085, _T_9086) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9088 = or(_T_9082, _T_9087) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9089 = bits(_T_9088, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9090 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9089 : @[Reg.scala 28:19]
|
|
_T_9090 <= _T_9079 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][114] <= _T_9090 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9091 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9092 = eq(_T_9091, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9093 = and(ic_valid_ff, _T_9092) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9094 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9095 = and(_T_9093, _T_9094) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9096 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9097 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9098 = and(_T_9096, _T_9097) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9099 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9100 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9101 = and(_T_9099, _T_9100) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9102 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9103 = and(_T_9101, _T_9102) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9104 = or(_T_9098, _T_9103) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9105 = bits(_T_9104, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9106 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9105 : @[Reg.scala 28:19]
|
|
_T_9106 <= _T_9095 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][115] <= _T_9106 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9107 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9108 = eq(_T_9107, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9109 = and(ic_valid_ff, _T_9108) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9110 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9111 = and(_T_9109, _T_9110) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9112 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9113 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9114 = and(_T_9112, _T_9113) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9115 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9116 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9117 = and(_T_9115, _T_9116) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9118 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9119 = and(_T_9117, _T_9118) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9120 = or(_T_9114, _T_9119) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9121 = bits(_T_9120, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9122 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9121 : @[Reg.scala 28:19]
|
|
_T_9122 <= _T_9111 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][116] <= _T_9122 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9123 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9124 = eq(_T_9123, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9125 = and(ic_valid_ff, _T_9124) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9126 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9127 = and(_T_9125, _T_9126) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9128 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9129 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9130 = and(_T_9128, _T_9129) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9131 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9132 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9133 = and(_T_9131, _T_9132) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9134 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9135 = and(_T_9133, _T_9134) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9136 = or(_T_9130, _T_9135) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9137 = bits(_T_9136, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9138 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9137 : @[Reg.scala 28:19]
|
|
_T_9138 <= _T_9127 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][117] <= _T_9138 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9139 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9140 = eq(_T_9139, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9141 = and(ic_valid_ff, _T_9140) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9142 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9143 = and(_T_9141, _T_9142) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9144 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9145 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9146 = and(_T_9144, _T_9145) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9147 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9148 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9149 = and(_T_9147, _T_9148) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9150 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9151 = and(_T_9149, _T_9150) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9152 = or(_T_9146, _T_9151) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9153 = bits(_T_9152, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9154 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9153 : @[Reg.scala 28:19]
|
|
_T_9154 <= _T_9143 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][118] <= _T_9154 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9155 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9156 = eq(_T_9155, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9157 = and(ic_valid_ff, _T_9156) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9158 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9159 = and(_T_9157, _T_9158) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9160 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9161 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9162 = and(_T_9160, _T_9161) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9163 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9164 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9165 = and(_T_9163, _T_9164) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9166 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9167 = and(_T_9165, _T_9166) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9168 = or(_T_9162, _T_9167) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9169 = bits(_T_9168, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9170 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9169 : @[Reg.scala 28:19]
|
|
_T_9170 <= _T_9159 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][119] <= _T_9170 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9171 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9172 = eq(_T_9171, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9173 = and(ic_valid_ff, _T_9172) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9174 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9175 = and(_T_9173, _T_9174) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9176 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9177 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9178 = and(_T_9176, _T_9177) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9179 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9180 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9181 = and(_T_9179, _T_9180) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9182 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9183 = and(_T_9181, _T_9182) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9184 = or(_T_9178, _T_9183) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9185 = bits(_T_9184, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9186 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9185 : @[Reg.scala 28:19]
|
|
_T_9186 <= _T_9175 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][120] <= _T_9186 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9187 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9188 = eq(_T_9187, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9189 = and(ic_valid_ff, _T_9188) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9190 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9191 = and(_T_9189, _T_9190) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9192 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9193 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9194 = and(_T_9192, _T_9193) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9195 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9196 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9197 = and(_T_9195, _T_9196) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9198 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9199 = and(_T_9197, _T_9198) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9200 = or(_T_9194, _T_9199) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9201 = bits(_T_9200, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9202 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9201 : @[Reg.scala 28:19]
|
|
_T_9202 <= _T_9191 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][121] <= _T_9202 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9203 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9204 = eq(_T_9203, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9205 = and(ic_valid_ff, _T_9204) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9206 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9207 = and(_T_9205, _T_9206) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9208 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9209 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9210 = and(_T_9208, _T_9209) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9211 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9212 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9213 = and(_T_9211, _T_9212) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9214 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9215 = and(_T_9213, _T_9214) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9216 = or(_T_9210, _T_9215) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9217 = bits(_T_9216, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9218 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9217 : @[Reg.scala 28:19]
|
|
_T_9218 <= _T_9207 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][122] <= _T_9218 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9219 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9220 = eq(_T_9219, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9221 = and(ic_valid_ff, _T_9220) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9222 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9223 = and(_T_9221, _T_9222) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9224 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9225 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9226 = and(_T_9224, _T_9225) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9227 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9228 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9229 = and(_T_9227, _T_9228) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9230 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9231 = and(_T_9229, _T_9230) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9232 = or(_T_9226, _T_9231) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9233 = bits(_T_9232, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9234 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9233 : @[Reg.scala 28:19]
|
|
_T_9234 <= _T_9223 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][123] <= _T_9234 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9235 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9236 = eq(_T_9235, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9237 = and(ic_valid_ff, _T_9236) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9238 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9239 = and(_T_9237, _T_9238) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9240 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9241 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9242 = and(_T_9240, _T_9241) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9243 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9244 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9245 = and(_T_9243, _T_9244) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9246 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9247 = and(_T_9245, _T_9246) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9248 = or(_T_9242, _T_9247) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9249 = bits(_T_9248, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9250 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9249 : @[Reg.scala 28:19]
|
|
_T_9250 <= _T_9239 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][124] <= _T_9250 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9251 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9252 = eq(_T_9251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9253 = and(ic_valid_ff, _T_9252) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9254 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9255 = and(_T_9253, _T_9254) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9256 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9257 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9258 = and(_T_9256, _T_9257) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9259 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9260 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9261 = and(_T_9259, _T_9260) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9262 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9263 = and(_T_9261, _T_9262) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9264 = or(_T_9258, _T_9263) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9265 = bits(_T_9264, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9266 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9265 : @[Reg.scala 28:19]
|
|
_T_9266 <= _T_9255 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][125] <= _T_9266 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9267 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9268 = eq(_T_9267, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9269 = and(ic_valid_ff, _T_9268) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9270 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9271 = and(_T_9269, _T_9270) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9272 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9273 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9274 = and(_T_9272, _T_9273) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9275 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9276 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9277 = and(_T_9275, _T_9276) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9278 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9279 = and(_T_9277, _T_9278) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9280 = or(_T_9274, _T_9279) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9281 = bits(_T_9280, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9282 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9281 : @[Reg.scala 28:19]
|
|
_T_9282 <= _T_9271 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][126] <= _T_9282 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9283 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82]
|
|
node _T_9284 = eq(_T_9283, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66]
|
|
node _T_9285 = and(ic_valid_ff, _T_9284) @[el2_ifu_mem_ctl.scala 740:64]
|
|
node _T_9286 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91]
|
|
node _T_9287 = and(_T_9285, _T_9286) @[el2_ifu_mem_ctl.scala 740:89]
|
|
node _T_9288 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 741:36]
|
|
node _T_9289 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75]
|
|
node _T_9290 = and(_T_9288, _T_9289) @[el2_ifu_mem_ctl.scala 741:58]
|
|
node _T_9291 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 741:101]
|
|
node _T_9292 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140]
|
|
node _T_9293 = and(_T_9291, _T_9292) @[el2_ifu_mem_ctl.scala 741:123]
|
|
node _T_9294 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163]
|
|
node _T_9295 = and(_T_9293, _T_9294) @[el2_ifu_mem_ctl.scala 741:144]
|
|
node _T_9296 = or(_T_9290, _T_9295) @[el2_ifu_mem_ctl.scala 741:80]
|
|
node _T_9297 = bits(_T_9296, 0, 0) @[el2_ifu_mem_ctl.scala 741:168]
|
|
reg _T_9298 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9297 : @[Reg.scala 28:19]
|
|
_T_9298 <= _T_9287 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][127] <= _T_9298 @[el2_ifu_mem_ctl.scala 740:39]
|
|
node _T_9299 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9300 = mux(_T_9299, UInt<1>("h00"), ic_tag_valid_out[0][0]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9301 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9302 = mux(_T_9301, UInt<1>("h00"), ic_tag_valid_out[0][1]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9303 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9304 = mux(_T_9303, UInt<1>("h00"), ic_tag_valid_out[0][2]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9305 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9306 = mux(_T_9305, UInt<1>("h00"), ic_tag_valid_out[0][3]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9307 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9308 = mux(_T_9307, UInt<1>("h00"), ic_tag_valid_out[0][4]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9309 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9310 = mux(_T_9309, UInt<1>("h00"), ic_tag_valid_out[0][5]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9311 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9312 = mux(_T_9311, UInt<1>("h00"), ic_tag_valid_out[0][6]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9313 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9314 = mux(_T_9313, UInt<1>("h00"), ic_tag_valid_out[0][7]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9315 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9316 = mux(_T_9315, UInt<1>("h00"), ic_tag_valid_out[0][8]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9317 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9318 = mux(_T_9317, UInt<1>("h00"), ic_tag_valid_out[0][9]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9319 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9320 = mux(_T_9319, UInt<1>("h00"), ic_tag_valid_out[0][10]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9321 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9322 = mux(_T_9321, UInt<1>("h00"), ic_tag_valid_out[0][11]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9323 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9324 = mux(_T_9323, UInt<1>("h00"), ic_tag_valid_out[0][12]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9325 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9326 = mux(_T_9325, UInt<1>("h00"), ic_tag_valid_out[0][13]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9327 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9328 = mux(_T_9327, UInt<1>("h00"), ic_tag_valid_out[0][14]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9329 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9330 = mux(_T_9329, UInt<1>("h00"), ic_tag_valid_out[0][15]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9331 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9332 = mux(_T_9331, UInt<1>("h00"), ic_tag_valid_out[0][16]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9333 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9334 = mux(_T_9333, UInt<1>("h00"), ic_tag_valid_out[0][17]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9335 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9336 = mux(_T_9335, UInt<1>("h00"), ic_tag_valid_out[0][18]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9337 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9338 = mux(_T_9337, UInt<1>("h00"), ic_tag_valid_out[0][19]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9339 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9340 = mux(_T_9339, UInt<1>("h00"), ic_tag_valid_out[0][20]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9341 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9342 = mux(_T_9341, UInt<1>("h00"), ic_tag_valid_out[0][21]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9343 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9344 = mux(_T_9343, UInt<1>("h00"), ic_tag_valid_out[0][22]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9345 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9346 = mux(_T_9345, UInt<1>("h00"), ic_tag_valid_out[0][23]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9347 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9348 = mux(_T_9347, UInt<1>("h00"), ic_tag_valid_out[0][24]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9349 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9350 = mux(_T_9349, UInt<1>("h00"), ic_tag_valid_out[0][25]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9351 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9352 = mux(_T_9351, UInt<1>("h00"), ic_tag_valid_out[0][26]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9353 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9354 = mux(_T_9353, UInt<1>("h00"), ic_tag_valid_out[0][27]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9355 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9356 = mux(_T_9355, UInt<1>("h00"), ic_tag_valid_out[0][28]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9357 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9358 = mux(_T_9357, UInt<1>("h00"), ic_tag_valid_out[0][29]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9359 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9360 = mux(_T_9359, UInt<1>("h00"), ic_tag_valid_out[0][30]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9361 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9362 = mux(_T_9361, UInt<1>("h00"), ic_tag_valid_out[0][31]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9363 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9364 = mux(_T_9363, UInt<1>("h00"), ic_tag_valid_out[0][32]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9365 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9366 = mux(_T_9365, UInt<1>("h00"), ic_tag_valid_out[0][33]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9367 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9368 = mux(_T_9367, UInt<1>("h00"), ic_tag_valid_out[0][34]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9369 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9370 = mux(_T_9369, UInt<1>("h00"), ic_tag_valid_out[0][35]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9371 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9372 = mux(_T_9371, UInt<1>("h00"), ic_tag_valid_out[0][36]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9373 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9374 = mux(_T_9373, UInt<1>("h00"), ic_tag_valid_out[0][37]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9375 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9376 = mux(_T_9375, UInt<1>("h00"), ic_tag_valid_out[0][38]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9377 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9378 = mux(_T_9377, UInt<1>("h00"), ic_tag_valid_out[0][39]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9379 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9380 = mux(_T_9379, UInt<1>("h00"), ic_tag_valid_out[0][40]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9381 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9382 = mux(_T_9381, UInt<1>("h00"), ic_tag_valid_out[0][41]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9383 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9384 = mux(_T_9383, UInt<1>("h00"), ic_tag_valid_out[0][42]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9385 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9386 = mux(_T_9385, UInt<1>("h00"), ic_tag_valid_out[0][43]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9387 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9388 = mux(_T_9387, UInt<1>("h00"), ic_tag_valid_out[0][44]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9389 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9390 = mux(_T_9389, UInt<1>("h00"), ic_tag_valid_out[0][45]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9391 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9392 = mux(_T_9391, UInt<1>("h00"), ic_tag_valid_out[0][46]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9393 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9394 = mux(_T_9393, UInt<1>("h00"), ic_tag_valid_out[0][47]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9395 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9396 = mux(_T_9395, UInt<1>("h00"), ic_tag_valid_out[0][48]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9397 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9398 = mux(_T_9397, UInt<1>("h00"), ic_tag_valid_out[0][49]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9399 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9400 = mux(_T_9399, UInt<1>("h00"), ic_tag_valid_out[0][50]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9401 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9402 = mux(_T_9401, UInt<1>("h00"), ic_tag_valid_out[0][51]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9403 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9404 = mux(_T_9403, UInt<1>("h00"), ic_tag_valid_out[0][52]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9405 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9406 = mux(_T_9405, UInt<1>("h00"), ic_tag_valid_out[0][53]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9407 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9408 = mux(_T_9407, UInt<1>("h00"), ic_tag_valid_out[0][54]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9409 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9410 = mux(_T_9409, UInt<1>("h00"), ic_tag_valid_out[0][55]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9411 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9412 = mux(_T_9411, UInt<1>("h00"), ic_tag_valid_out[0][56]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9413 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9414 = mux(_T_9413, UInt<1>("h00"), ic_tag_valid_out[0][57]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9415 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9416 = mux(_T_9415, UInt<1>("h00"), ic_tag_valid_out[0][58]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9417 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9418 = mux(_T_9417, UInt<1>("h00"), ic_tag_valid_out[0][59]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9419 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9420 = mux(_T_9419, UInt<1>("h00"), ic_tag_valid_out[0][60]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9421 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9422 = mux(_T_9421, UInt<1>("h00"), ic_tag_valid_out[0][61]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9423 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9424 = mux(_T_9423, UInt<1>("h00"), ic_tag_valid_out[0][62]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9425 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9426 = mux(_T_9425, UInt<1>("h00"), ic_tag_valid_out[0][63]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9427 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9428 = mux(_T_9427, UInt<1>("h00"), ic_tag_valid_out[0][64]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9429 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9430 = mux(_T_9429, UInt<1>("h00"), ic_tag_valid_out[0][65]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9431 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9432 = mux(_T_9431, UInt<1>("h00"), ic_tag_valid_out[0][66]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9433 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9434 = mux(_T_9433, UInt<1>("h00"), ic_tag_valid_out[0][67]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9435 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9436 = mux(_T_9435, UInt<1>("h00"), ic_tag_valid_out[0][68]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9437 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9438 = mux(_T_9437, UInt<1>("h00"), ic_tag_valid_out[0][69]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9439 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9440 = mux(_T_9439, UInt<1>("h00"), ic_tag_valid_out[0][70]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9441 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9442 = mux(_T_9441, UInt<1>("h00"), ic_tag_valid_out[0][71]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9443 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9444 = mux(_T_9443, UInt<1>("h00"), ic_tag_valid_out[0][72]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9445 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9446 = mux(_T_9445, UInt<1>("h00"), ic_tag_valid_out[0][73]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9447 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9448 = mux(_T_9447, UInt<1>("h00"), ic_tag_valid_out[0][74]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9449 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9450 = mux(_T_9449, UInt<1>("h00"), ic_tag_valid_out[0][75]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9451 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9452 = mux(_T_9451, UInt<1>("h00"), ic_tag_valid_out[0][76]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9453 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9454 = mux(_T_9453, UInt<1>("h00"), ic_tag_valid_out[0][77]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9455 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9456 = mux(_T_9455, UInt<1>("h00"), ic_tag_valid_out[0][78]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9457 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9458 = mux(_T_9457, UInt<1>("h00"), ic_tag_valid_out[0][79]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9459 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9460 = mux(_T_9459, UInt<1>("h00"), ic_tag_valid_out[0][80]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9461 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9462 = mux(_T_9461, UInt<1>("h00"), ic_tag_valid_out[0][81]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9463 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9464 = mux(_T_9463, UInt<1>("h00"), ic_tag_valid_out[0][82]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9465 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9466 = mux(_T_9465, UInt<1>("h00"), ic_tag_valid_out[0][83]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9467 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9468 = mux(_T_9467, UInt<1>("h00"), ic_tag_valid_out[0][84]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9469 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9470 = mux(_T_9469, UInt<1>("h00"), ic_tag_valid_out[0][85]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9471 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9472 = mux(_T_9471, UInt<1>("h00"), ic_tag_valid_out[0][86]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9473 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9474 = mux(_T_9473, UInt<1>("h00"), ic_tag_valid_out[0][87]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9475 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9476 = mux(_T_9475, UInt<1>("h00"), ic_tag_valid_out[0][88]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9477 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9478 = mux(_T_9477, UInt<1>("h00"), ic_tag_valid_out[0][89]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9479 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9480 = mux(_T_9479, UInt<1>("h00"), ic_tag_valid_out[0][90]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9481 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9482 = mux(_T_9481, UInt<1>("h00"), ic_tag_valid_out[0][91]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9483 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9484 = mux(_T_9483, UInt<1>("h00"), ic_tag_valid_out[0][92]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9485 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9486 = mux(_T_9485, UInt<1>("h00"), ic_tag_valid_out[0][93]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9487 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9488 = mux(_T_9487, UInt<1>("h00"), ic_tag_valid_out[0][94]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9489 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9490 = mux(_T_9489, UInt<1>("h00"), ic_tag_valid_out[0][95]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9491 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9492 = mux(_T_9491, UInt<1>("h00"), ic_tag_valid_out[0][96]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9493 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9494 = mux(_T_9493, UInt<1>("h00"), ic_tag_valid_out[0][97]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9495 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9496 = mux(_T_9495, UInt<1>("h00"), ic_tag_valid_out[0][98]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9497 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9498 = mux(_T_9497, UInt<1>("h00"), ic_tag_valid_out[0][99]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9499 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9500 = mux(_T_9499, UInt<1>("h00"), ic_tag_valid_out[0][100]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9501 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9502 = mux(_T_9501, UInt<1>("h00"), ic_tag_valid_out[0][101]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9503 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9504 = mux(_T_9503, UInt<1>("h00"), ic_tag_valid_out[0][102]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9505 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9506 = mux(_T_9505, UInt<1>("h00"), ic_tag_valid_out[0][103]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9507 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9508 = mux(_T_9507, UInt<1>("h00"), ic_tag_valid_out[0][104]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9509 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9510 = mux(_T_9509, UInt<1>("h00"), ic_tag_valid_out[0][105]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9511 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9512 = mux(_T_9511, UInt<1>("h00"), ic_tag_valid_out[0][106]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9513 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9514 = mux(_T_9513, UInt<1>("h00"), ic_tag_valid_out[0][107]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9516 = mux(_T_9515, UInt<1>("h00"), ic_tag_valid_out[0][108]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9517 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9518 = mux(_T_9517, UInt<1>("h00"), ic_tag_valid_out[0][109]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9519 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9520 = mux(_T_9519, UInt<1>("h00"), ic_tag_valid_out[0][110]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9521 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9522 = mux(_T_9521, UInt<1>("h00"), ic_tag_valid_out[0][111]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9523 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9524 = mux(_T_9523, UInt<1>("h00"), ic_tag_valid_out[0][112]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9526 = mux(_T_9525, UInt<1>("h00"), ic_tag_valid_out[0][113]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9527 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9528 = mux(_T_9527, UInt<1>("h00"), ic_tag_valid_out[0][114]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9529 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9530 = mux(_T_9529, UInt<1>("h00"), ic_tag_valid_out[0][115]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9531 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9532 = mux(_T_9531, UInt<1>("h00"), ic_tag_valid_out[0][116]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9533 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9534 = mux(_T_9533, UInt<1>("h00"), ic_tag_valid_out[0][117]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9535 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9536 = mux(_T_9535, UInt<1>("h00"), ic_tag_valid_out[0][118]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9537 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9538 = mux(_T_9537, UInt<1>("h00"), ic_tag_valid_out[0][119]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9539 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9540 = mux(_T_9539, UInt<1>("h00"), ic_tag_valid_out[0][120]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9541 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9542 = mux(_T_9541, UInt<1>("h00"), ic_tag_valid_out[0][121]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9543 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9544 = mux(_T_9543, UInt<1>("h00"), ic_tag_valid_out[0][122]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9546 = mux(_T_9545, UInt<1>("h00"), ic_tag_valid_out[0][123]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9547 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9548 = mux(_T_9547, UInt<1>("h00"), ic_tag_valid_out[0][124]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9549 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9550 = mux(_T_9549, UInt<1>("h00"), ic_tag_valid_out[0][125]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9551 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9552 = mux(_T_9551, UInt<1>("h00"), ic_tag_valid_out[0][126]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9553 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9554 = mux(_T_9553, UInt<1>("h00"), ic_tag_valid_out[0][127]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9555 = or(_T_9300, _T_9302) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9556 = or(_T_9555, _T_9304) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9557 = or(_T_9556, _T_9306) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9558 = or(_T_9557, _T_9308) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9559 = or(_T_9558, _T_9310) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9560 = or(_T_9559, _T_9312) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9561 = or(_T_9560, _T_9314) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9562 = or(_T_9561, _T_9316) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9563 = or(_T_9562, _T_9318) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9564 = or(_T_9563, _T_9320) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9565 = or(_T_9564, _T_9322) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9566 = or(_T_9565, _T_9324) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9567 = or(_T_9566, _T_9326) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9568 = or(_T_9567, _T_9328) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9569 = or(_T_9568, _T_9330) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9570 = or(_T_9569, _T_9332) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9571 = or(_T_9570, _T_9334) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9572 = or(_T_9571, _T_9336) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9573 = or(_T_9572, _T_9338) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9574 = or(_T_9573, _T_9340) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9575 = or(_T_9574, _T_9342) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9576 = or(_T_9575, _T_9344) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9577 = or(_T_9576, _T_9346) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9578 = or(_T_9577, _T_9348) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9579 = or(_T_9578, _T_9350) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9580 = or(_T_9579, _T_9352) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9581 = or(_T_9580, _T_9354) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9582 = or(_T_9581, _T_9356) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9583 = or(_T_9582, _T_9358) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9584 = or(_T_9583, _T_9360) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9585 = or(_T_9584, _T_9362) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9586 = or(_T_9585, _T_9364) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9587 = or(_T_9586, _T_9366) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9588 = or(_T_9587, _T_9368) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9589 = or(_T_9588, _T_9370) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9590 = or(_T_9589, _T_9372) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9591 = or(_T_9590, _T_9374) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9592 = or(_T_9591, _T_9376) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9593 = or(_T_9592, _T_9378) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9594 = or(_T_9593, _T_9380) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9595 = or(_T_9594, _T_9382) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9596 = or(_T_9595, _T_9384) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9597 = or(_T_9596, _T_9386) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9598 = or(_T_9597, _T_9388) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9599 = or(_T_9598, _T_9390) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9600 = or(_T_9599, _T_9392) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9601 = or(_T_9600, _T_9394) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9602 = or(_T_9601, _T_9396) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9603 = or(_T_9602, _T_9398) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9604 = or(_T_9603, _T_9400) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9605 = or(_T_9604, _T_9402) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9606 = or(_T_9605, _T_9404) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9607 = or(_T_9606, _T_9406) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9608 = or(_T_9607, _T_9408) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9609 = or(_T_9608, _T_9410) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9610 = or(_T_9609, _T_9412) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9611 = or(_T_9610, _T_9414) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9612 = or(_T_9611, _T_9416) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9613 = or(_T_9612, _T_9418) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9614 = or(_T_9613, _T_9420) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9615 = or(_T_9614, _T_9422) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9616 = or(_T_9615, _T_9424) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9617 = or(_T_9616, _T_9426) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9618 = or(_T_9617, _T_9428) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9619 = or(_T_9618, _T_9430) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9620 = or(_T_9619, _T_9432) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9621 = or(_T_9620, _T_9434) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9622 = or(_T_9621, _T_9436) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9623 = or(_T_9622, _T_9438) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9624 = or(_T_9623, _T_9440) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9625 = or(_T_9624, _T_9442) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9626 = or(_T_9625, _T_9444) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9627 = or(_T_9626, _T_9446) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9628 = or(_T_9627, _T_9448) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9629 = or(_T_9628, _T_9450) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9630 = or(_T_9629, _T_9452) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9631 = or(_T_9630, _T_9454) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9632 = or(_T_9631, _T_9456) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9633 = or(_T_9632, _T_9458) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9634 = or(_T_9633, _T_9460) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9635 = or(_T_9634, _T_9462) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9636 = or(_T_9635, _T_9464) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9637 = or(_T_9636, _T_9466) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9638 = or(_T_9637, _T_9468) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9639 = or(_T_9638, _T_9470) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9640 = or(_T_9639, _T_9472) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9641 = or(_T_9640, _T_9474) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9642 = or(_T_9641, _T_9476) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9643 = or(_T_9642, _T_9478) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9644 = or(_T_9643, _T_9480) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9645 = or(_T_9644, _T_9482) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9646 = or(_T_9645, _T_9484) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9647 = or(_T_9646, _T_9486) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9648 = or(_T_9647, _T_9488) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9649 = or(_T_9648, _T_9490) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9650 = or(_T_9649, _T_9492) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9651 = or(_T_9650, _T_9494) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9652 = or(_T_9651, _T_9496) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9653 = or(_T_9652, _T_9498) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9654 = or(_T_9653, _T_9500) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9655 = or(_T_9654, _T_9502) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9656 = or(_T_9655, _T_9504) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9657 = or(_T_9656, _T_9506) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9658 = or(_T_9657, _T_9508) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9659 = or(_T_9658, _T_9510) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9660 = or(_T_9659, _T_9512) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9661 = or(_T_9660, _T_9514) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9662 = or(_T_9661, _T_9516) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9663 = or(_T_9662, _T_9518) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9664 = or(_T_9663, _T_9520) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9665 = or(_T_9664, _T_9522) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9666 = or(_T_9665, _T_9524) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9667 = or(_T_9666, _T_9526) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9668 = or(_T_9667, _T_9528) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9669 = or(_T_9668, _T_9530) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9670 = or(_T_9669, _T_9532) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9671 = or(_T_9670, _T_9534) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9672 = or(_T_9671, _T_9536) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9673 = or(_T_9672, _T_9538) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9674 = or(_T_9673, _T_9540) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9675 = or(_T_9674, _T_9542) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9676 = or(_T_9675, _T_9544) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9677 = or(_T_9676, _T_9546) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9678 = or(_T_9677, _T_9548) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9679 = or(_T_9678, _T_9550) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9680 = or(_T_9679, _T_9552) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9681 = or(_T_9680, _T_9554) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9682 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9683 = mux(_T_9682, UInt<1>("h00"), ic_tag_valid_out[1][0]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9684 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9685 = mux(_T_9684, UInt<1>("h00"), ic_tag_valid_out[1][1]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9686 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9687 = mux(_T_9686, UInt<1>("h00"), ic_tag_valid_out[1][2]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9688 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9689 = mux(_T_9688, UInt<1>("h00"), ic_tag_valid_out[1][3]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9690 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9691 = mux(_T_9690, UInt<1>("h00"), ic_tag_valid_out[1][4]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9692 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9693 = mux(_T_9692, UInt<1>("h00"), ic_tag_valid_out[1][5]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9694 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9695 = mux(_T_9694, UInt<1>("h00"), ic_tag_valid_out[1][6]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9696 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9697 = mux(_T_9696, UInt<1>("h00"), ic_tag_valid_out[1][7]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9698 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9699 = mux(_T_9698, UInt<1>("h00"), ic_tag_valid_out[1][8]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9700 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9701 = mux(_T_9700, UInt<1>("h00"), ic_tag_valid_out[1][9]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9702 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9703 = mux(_T_9702, UInt<1>("h00"), ic_tag_valid_out[1][10]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9704 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9705 = mux(_T_9704, UInt<1>("h00"), ic_tag_valid_out[1][11]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9706 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9707 = mux(_T_9706, UInt<1>("h00"), ic_tag_valid_out[1][12]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9708 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9709 = mux(_T_9708, UInt<1>("h00"), ic_tag_valid_out[1][13]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9710 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9711 = mux(_T_9710, UInt<1>("h00"), ic_tag_valid_out[1][14]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9712 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9713 = mux(_T_9712, UInt<1>("h00"), ic_tag_valid_out[1][15]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9714 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9715 = mux(_T_9714, UInt<1>("h00"), ic_tag_valid_out[1][16]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9716 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9717 = mux(_T_9716, UInt<1>("h00"), ic_tag_valid_out[1][17]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9718 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9719 = mux(_T_9718, UInt<1>("h00"), ic_tag_valid_out[1][18]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9720 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9721 = mux(_T_9720, UInt<1>("h00"), ic_tag_valid_out[1][19]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9722 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9723 = mux(_T_9722, UInt<1>("h00"), ic_tag_valid_out[1][20]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9724 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9725 = mux(_T_9724, UInt<1>("h00"), ic_tag_valid_out[1][21]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9726 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9727 = mux(_T_9726, UInt<1>("h00"), ic_tag_valid_out[1][22]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9728 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9729 = mux(_T_9728, UInt<1>("h00"), ic_tag_valid_out[1][23]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9730 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9731 = mux(_T_9730, UInt<1>("h00"), ic_tag_valid_out[1][24]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9732 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9733 = mux(_T_9732, UInt<1>("h00"), ic_tag_valid_out[1][25]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9734 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9735 = mux(_T_9734, UInt<1>("h00"), ic_tag_valid_out[1][26]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9736 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9737 = mux(_T_9736, UInt<1>("h00"), ic_tag_valid_out[1][27]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9738 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9739 = mux(_T_9738, UInt<1>("h00"), ic_tag_valid_out[1][28]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9740 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9741 = mux(_T_9740, UInt<1>("h00"), ic_tag_valid_out[1][29]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9742 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9743 = mux(_T_9742, UInt<1>("h00"), ic_tag_valid_out[1][30]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9744 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9745 = mux(_T_9744, UInt<1>("h00"), ic_tag_valid_out[1][31]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9746 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9747 = mux(_T_9746, UInt<1>("h00"), ic_tag_valid_out[1][32]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9748 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9749 = mux(_T_9748, UInt<1>("h00"), ic_tag_valid_out[1][33]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9750 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9751 = mux(_T_9750, UInt<1>("h00"), ic_tag_valid_out[1][34]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9752 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9753 = mux(_T_9752, UInt<1>("h00"), ic_tag_valid_out[1][35]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9754 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9755 = mux(_T_9754, UInt<1>("h00"), ic_tag_valid_out[1][36]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9756 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9757 = mux(_T_9756, UInt<1>("h00"), ic_tag_valid_out[1][37]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9758 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9759 = mux(_T_9758, UInt<1>("h00"), ic_tag_valid_out[1][38]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9760 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9761 = mux(_T_9760, UInt<1>("h00"), ic_tag_valid_out[1][39]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9762 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9763 = mux(_T_9762, UInt<1>("h00"), ic_tag_valid_out[1][40]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9764 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9765 = mux(_T_9764, UInt<1>("h00"), ic_tag_valid_out[1][41]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9766 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9767 = mux(_T_9766, UInt<1>("h00"), ic_tag_valid_out[1][42]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9768 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9769 = mux(_T_9768, UInt<1>("h00"), ic_tag_valid_out[1][43]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9770 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9771 = mux(_T_9770, UInt<1>("h00"), ic_tag_valid_out[1][44]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9772 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9773 = mux(_T_9772, UInt<1>("h00"), ic_tag_valid_out[1][45]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9774 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9775 = mux(_T_9774, UInt<1>("h00"), ic_tag_valid_out[1][46]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9776 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9777 = mux(_T_9776, UInt<1>("h00"), ic_tag_valid_out[1][47]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9778 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9779 = mux(_T_9778, UInt<1>("h00"), ic_tag_valid_out[1][48]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9780 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9781 = mux(_T_9780, UInt<1>("h00"), ic_tag_valid_out[1][49]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9782 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9783 = mux(_T_9782, UInt<1>("h00"), ic_tag_valid_out[1][50]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9784 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9785 = mux(_T_9784, UInt<1>("h00"), ic_tag_valid_out[1][51]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9786 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9787 = mux(_T_9786, UInt<1>("h00"), ic_tag_valid_out[1][52]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9788 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9789 = mux(_T_9788, UInt<1>("h00"), ic_tag_valid_out[1][53]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9790 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9791 = mux(_T_9790, UInt<1>("h00"), ic_tag_valid_out[1][54]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9792 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9793 = mux(_T_9792, UInt<1>("h00"), ic_tag_valid_out[1][55]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9794 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9795 = mux(_T_9794, UInt<1>("h00"), ic_tag_valid_out[1][56]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9796 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9797 = mux(_T_9796, UInt<1>("h00"), ic_tag_valid_out[1][57]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9798 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9799 = mux(_T_9798, UInt<1>("h00"), ic_tag_valid_out[1][58]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9800 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9801 = mux(_T_9800, UInt<1>("h00"), ic_tag_valid_out[1][59]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9802 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9803 = mux(_T_9802, UInt<1>("h00"), ic_tag_valid_out[1][60]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9804 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9805 = mux(_T_9804, UInt<1>("h00"), ic_tag_valid_out[1][61]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9806 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9807 = mux(_T_9806, UInt<1>("h00"), ic_tag_valid_out[1][62]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9808 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9809 = mux(_T_9808, UInt<1>("h00"), ic_tag_valid_out[1][63]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9810 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9811 = mux(_T_9810, UInt<1>("h00"), ic_tag_valid_out[1][64]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9812 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9813 = mux(_T_9812, UInt<1>("h00"), ic_tag_valid_out[1][65]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9814 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9815 = mux(_T_9814, UInt<1>("h00"), ic_tag_valid_out[1][66]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9816 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9817 = mux(_T_9816, UInt<1>("h00"), ic_tag_valid_out[1][67]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9818 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9819 = mux(_T_9818, UInt<1>("h00"), ic_tag_valid_out[1][68]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9820 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9821 = mux(_T_9820, UInt<1>("h00"), ic_tag_valid_out[1][69]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9822 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9823 = mux(_T_9822, UInt<1>("h00"), ic_tag_valid_out[1][70]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9824 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9825 = mux(_T_9824, UInt<1>("h00"), ic_tag_valid_out[1][71]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9826 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9827 = mux(_T_9826, UInt<1>("h00"), ic_tag_valid_out[1][72]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9828 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9829 = mux(_T_9828, UInt<1>("h00"), ic_tag_valid_out[1][73]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9830 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9831 = mux(_T_9830, UInt<1>("h00"), ic_tag_valid_out[1][74]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9832 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9833 = mux(_T_9832, UInt<1>("h00"), ic_tag_valid_out[1][75]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9834 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9835 = mux(_T_9834, UInt<1>("h00"), ic_tag_valid_out[1][76]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9836 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9837 = mux(_T_9836, UInt<1>("h00"), ic_tag_valid_out[1][77]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9838 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9839 = mux(_T_9838, UInt<1>("h00"), ic_tag_valid_out[1][78]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9841 = mux(_T_9840, UInt<1>("h00"), ic_tag_valid_out[1][79]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9842 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9843 = mux(_T_9842, UInt<1>("h00"), ic_tag_valid_out[1][80]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9844 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9845 = mux(_T_9844, UInt<1>("h00"), ic_tag_valid_out[1][81]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9846 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9847 = mux(_T_9846, UInt<1>("h00"), ic_tag_valid_out[1][82]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9848 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9849 = mux(_T_9848, UInt<1>("h00"), ic_tag_valid_out[1][83]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9850 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9851 = mux(_T_9850, UInt<1>("h00"), ic_tag_valid_out[1][84]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9852 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9853 = mux(_T_9852, UInt<1>("h00"), ic_tag_valid_out[1][85]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9854 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9855 = mux(_T_9854, UInt<1>("h00"), ic_tag_valid_out[1][86]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9856 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9857 = mux(_T_9856, UInt<1>("h00"), ic_tag_valid_out[1][87]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9858 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9859 = mux(_T_9858, UInt<1>("h00"), ic_tag_valid_out[1][88]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9860 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9861 = mux(_T_9860, UInt<1>("h00"), ic_tag_valid_out[1][89]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9862 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9863 = mux(_T_9862, UInt<1>("h00"), ic_tag_valid_out[1][90]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9864 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9865 = mux(_T_9864, UInt<1>("h00"), ic_tag_valid_out[1][91]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9866 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9867 = mux(_T_9866, UInt<1>("h00"), ic_tag_valid_out[1][92]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9868 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9869 = mux(_T_9868, UInt<1>("h00"), ic_tag_valid_out[1][93]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9870 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9871 = mux(_T_9870, UInt<1>("h00"), ic_tag_valid_out[1][94]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9872 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9873 = mux(_T_9872, UInt<1>("h00"), ic_tag_valid_out[1][95]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9874 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9875 = mux(_T_9874, UInt<1>("h00"), ic_tag_valid_out[1][96]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9876 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9877 = mux(_T_9876, UInt<1>("h00"), ic_tag_valid_out[1][97]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9878 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9879 = mux(_T_9878, UInt<1>("h00"), ic_tag_valid_out[1][98]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9880 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9881 = mux(_T_9880, UInt<1>("h00"), ic_tag_valid_out[1][99]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9882 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9883 = mux(_T_9882, UInt<1>("h00"), ic_tag_valid_out[1][100]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9884 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9885 = mux(_T_9884, UInt<1>("h00"), ic_tag_valid_out[1][101]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9886 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9887 = mux(_T_9886, UInt<1>("h00"), ic_tag_valid_out[1][102]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9888 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9889 = mux(_T_9888, UInt<1>("h00"), ic_tag_valid_out[1][103]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9890 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9891 = mux(_T_9890, UInt<1>("h00"), ic_tag_valid_out[1][104]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9892 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9893 = mux(_T_9892, UInt<1>("h00"), ic_tag_valid_out[1][105]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9894 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9895 = mux(_T_9894, UInt<1>("h00"), ic_tag_valid_out[1][106]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9896 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9897 = mux(_T_9896, UInt<1>("h00"), ic_tag_valid_out[1][107]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9898 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9899 = mux(_T_9898, UInt<1>("h00"), ic_tag_valid_out[1][108]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9900 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9901 = mux(_T_9900, UInt<1>("h00"), ic_tag_valid_out[1][109]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9902 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9903 = mux(_T_9902, UInt<1>("h00"), ic_tag_valid_out[1][110]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9904 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9905 = mux(_T_9904, UInt<1>("h00"), ic_tag_valid_out[1][111]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9906 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9907 = mux(_T_9906, UInt<1>("h00"), ic_tag_valid_out[1][112]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9908 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9909 = mux(_T_9908, UInt<1>("h00"), ic_tag_valid_out[1][113]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9910 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9911 = mux(_T_9910, UInt<1>("h00"), ic_tag_valid_out[1][114]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9912 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9913 = mux(_T_9912, UInt<1>("h00"), ic_tag_valid_out[1][115]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9914 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9915 = mux(_T_9914, UInt<1>("h00"), ic_tag_valid_out[1][116]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9916 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9917 = mux(_T_9916, UInt<1>("h00"), ic_tag_valid_out[1][117]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9918 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9919 = mux(_T_9918, UInt<1>("h00"), ic_tag_valid_out[1][118]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9920 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9921 = mux(_T_9920, UInt<1>("h00"), ic_tag_valid_out[1][119]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9922 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9923 = mux(_T_9922, UInt<1>("h00"), ic_tag_valid_out[1][120]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9924 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9925 = mux(_T_9924, UInt<1>("h00"), ic_tag_valid_out[1][121]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9926 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9927 = mux(_T_9926, UInt<1>("h00"), ic_tag_valid_out[1][122]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9928 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9929 = mux(_T_9928, UInt<1>("h00"), ic_tag_valid_out[1][123]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9930 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9931 = mux(_T_9930, UInt<1>("h00"), ic_tag_valid_out[1][124]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9932 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9933 = mux(_T_9932, UInt<1>("h00"), ic_tag_valid_out[1][125]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9934 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9935 = mux(_T_9934, UInt<1>("h00"), ic_tag_valid_out[1][126]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9936 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 744:33]
|
|
node _T_9937 = mux(_T_9936, UInt<1>("h00"), ic_tag_valid_out[1][127]) @[el2_ifu_mem_ctl.scala 744:10]
|
|
node _T_9938 = or(_T_9683, _T_9685) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9939 = or(_T_9938, _T_9687) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9940 = or(_T_9939, _T_9689) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9941 = or(_T_9940, _T_9691) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9942 = or(_T_9941, _T_9693) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9943 = or(_T_9942, _T_9695) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9944 = or(_T_9943, _T_9697) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9945 = or(_T_9944, _T_9699) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9946 = or(_T_9945, _T_9701) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9947 = or(_T_9946, _T_9703) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9948 = or(_T_9947, _T_9705) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9949 = or(_T_9948, _T_9707) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9950 = or(_T_9949, _T_9709) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9951 = or(_T_9950, _T_9711) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9952 = or(_T_9951, _T_9713) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9953 = or(_T_9952, _T_9715) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9954 = or(_T_9953, _T_9717) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9955 = or(_T_9954, _T_9719) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9956 = or(_T_9955, _T_9721) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9957 = or(_T_9956, _T_9723) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9958 = or(_T_9957, _T_9725) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9959 = or(_T_9958, _T_9727) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9960 = or(_T_9959, _T_9729) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9961 = or(_T_9960, _T_9731) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9962 = or(_T_9961, _T_9733) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9963 = or(_T_9962, _T_9735) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9964 = or(_T_9963, _T_9737) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9965 = or(_T_9964, _T_9739) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9966 = or(_T_9965, _T_9741) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9967 = or(_T_9966, _T_9743) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9968 = or(_T_9967, _T_9745) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9969 = or(_T_9968, _T_9747) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9970 = or(_T_9969, _T_9749) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9971 = or(_T_9970, _T_9751) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9972 = or(_T_9971, _T_9753) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9973 = or(_T_9972, _T_9755) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9974 = or(_T_9973, _T_9757) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9975 = or(_T_9974, _T_9759) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9976 = or(_T_9975, _T_9761) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9977 = or(_T_9976, _T_9763) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9978 = or(_T_9977, _T_9765) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9979 = or(_T_9978, _T_9767) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9980 = or(_T_9979, _T_9769) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9981 = or(_T_9980, _T_9771) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9982 = or(_T_9981, _T_9773) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9983 = or(_T_9982, _T_9775) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9984 = or(_T_9983, _T_9777) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9985 = or(_T_9984, _T_9779) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9986 = or(_T_9985, _T_9781) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9987 = or(_T_9986, _T_9783) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9988 = or(_T_9987, _T_9785) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9989 = or(_T_9988, _T_9787) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9990 = or(_T_9989, _T_9789) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9991 = or(_T_9990, _T_9791) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9992 = or(_T_9991, _T_9793) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9993 = or(_T_9992, _T_9795) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9994 = or(_T_9993, _T_9797) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9995 = or(_T_9994, _T_9799) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9996 = or(_T_9995, _T_9801) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9997 = or(_T_9996, _T_9803) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9998 = or(_T_9997, _T_9805) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_9999 = or(_T_9998, _T_9807) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10000 = or(_T_9999, _T_9809) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10001 = or(_T_10000, _T_9811) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10002 = or(_T_10001, _T_9813) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10003 = or(_T_10002, _T_9815) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10004 = or(_T_10003, _T_9817) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10005 = or(_T_10004, _T_9819) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10006 = or(_T_10005, _T_9821) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10007 = or(_T_10006, _T_9823) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10008 = or(_T_10007, _T_9825) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10009 = or(_T_10008, _T_9827) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10010 = or(_T_10009, _T_9829) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10011 = or(_T_10010, _T_9831) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10012 = or(_T_10011, _T_9833) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10013 = or(_T_10012, _T_9835) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10014 = or(_T_10013, _T_9837) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10015 = or(_T_10014, _T_9839) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10016 = or(_T_10015, _T_9841) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10017 = or(_T_10016, _T_9843) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10018 = or(_T_10017, _T_9845) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10019 = or(_T_10018, _T_9847) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10020 = or(_T_10019, _T_9849) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10021 = or(_T_10020, _T_9851) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10022 = or(_T_10021, _T_9853) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10023 = or(_T_10022, _T_9855) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10024 = or(_T_10023, _T_9857) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10025 = or(_T_10024, _T_9859) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10026 = or(_T_10025, _T_9861) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10027 = or(_T_10026, _T_9863) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10028 = or(_T_10027, _T_9865) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10029 = or(_T_10028, _T_9867) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10030 = or(_T_10029, _T_9869) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10031 = or(_T_10030, _T_9871) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10032 = or(_T_10031, _T_9873) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10033 = or(_T_10032, _T_9875) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10034 = or(_T_10033, _T_9877) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10035 = or(_T_10034, _T_9879) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10036 = or(_T_10035, _T_9881) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10037 = or(_T_10036, _T_9883) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10038 = or(_T_10037, _T_9885) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10039 = or(_T_10038, _T_9887) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10040 = or(_T_10039, _T_9889) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10041 = or(_T_10040, _T_9891) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10042 = or(_T_10041, _T_9893) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10043 = or(_T_10042, _T_9895) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10044 = or(_T_10043, _T_9897) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10045 = or(_T_10044, _T_9899) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10046 = or(_T_10045, _T_9901) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10047 = or(_T_10046, _T_9903) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10048 = or(_T_10047, _T_9905) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10049 = or(_T_10048, _T_9907) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10050 = or(_T_10049, _T_9909) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10051 = or(_T_10050, _T_9911) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10052 = or(_T_10051, _T_9913) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10053 = or(_T_10052, _T_9915) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10054 = or(_T_10053, _T_9917) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10055 = or(_T_10054, _T_9919) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10056 = or(_T_10055, _T_9921) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10057 = or(_T_10056, _T_9923) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10058 = or(_T_10057, _T_9925) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10059 = or(_T_10058, _T_9927) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10060 = or(_T_10059, _T_9929) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10061 = or(_T_10060, _T_9931) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10062 = or(_T_10061, _T_9933) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10063 = or(_T_10062, _T_9935) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node _T_10064 = or(_T_10063, _T_9937) @[el2_ifu_mem_ctl.scala 744:91]
|
|
node ic_tag_valid_unq = cat(_T_10064, _T_9681) @[Cat.scala 29:58]
|
|
wire way_status_hit_new : UInt<1>
|
|
way_status_hit_new <= UInt<1>("h00")
|
|
node _T_10065 = eq(way_status_mb_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 769:33]
|
|
node _T_10066 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 769:63]
|
|
node _T_10067 = and(_T_10065, _T_10066) @[el2_ifu_mem_ctl.scala 769:51]
|
|
node _T_10068 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 769:79]
|
|
node _T_10069 = and(_T_10067, _T_10068) @[el2_ifu_mem_ctl.scala 769:67]
|
|
node _T_10070 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 769:97]
|
|
node _T_10071 = eq(_T_10070, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 769:86]
|
|
node _T_10072 = or(_T_10069, _T_10071) @[el2_ifu_mem_ctl.scala 769:84]
|
|
replace_way_mb_any[0] <= _T_10072 @[el2_ifu_mem_ctl.scala 769:29]
|
|
node _T_10073 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 770:62]
|
|
node _T_10074 = and(way_status_mb_ff, _T_10073) @[el2_ifu_mem_ctl.scala 770:50]
|
|
node _T_10075 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 770:78]
|
|
node _T_10076 = and(_T_10074, _T_10075) @[el2_ifu_mem_ctl.scala 770:66]
|
|
node _T_10077 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 770:96]
|
|
node _T_10078 = eq(_T_10077, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 770:85]
|
|
node _T_10079 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 770:112]
|
|
node _T_10080 = and(_T_10078, _T_10079) @[el2_ifu_mem_ctl.scala 770:100]
|
|
node _T_10081 = or(_T_10076, _T_10080) @[el2_ifu_mem_ctl.scala 770:83]
|
|
replace_way_mb_any[1] <= _T_10081 @[el2_ifu_mem_ctl.scala 770:29]
|
|
node _T_10082 = bits(io.ic_rd_hit, 0, 0) @[el2_ifu_mem_ctl.scala 771:41]
|
|
way_status_hit_new <= _T_10082 @[el2_ifu_mem_ctl.scala 771:26]
|
|
way_status_rep_new <= replace_way_mb_any[0] @[el2_ifu_mem_ctl.scala 772:26]
|
|
node _T_10083 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 774:47]
|
|
node _T_10084 = bits(_T_10083, 0, 0) @[el2_ifu_mem_ctl.scala 774:60]
|
|
node _T_10085 = mux(_T_10084, way_status_rep_new, way_status_hit_new) @[el2_ifu_mem_ctl.scala 774:26]
|
|
way_status_new <= _T_10085 @[el2_ifu_mem_ctl.scala 774:20]
|
|
node _T_10086 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 775:45]
|
|
node _T_10087 = or(_T_10086, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 775:58]
|
|
way_status_wr_en <= _T_10087 @[el2_ifu_mem_ctl.scala 775:22]
|
|
node _T_10088 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 776:74]
|
|
node bus_wren_0 = and(_T_10088, miss_pending) @[el2_ifu_mem_ctl.scala 776:98]
|
|
node _T_10089 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 776:74]
|
|
node bus_wren_1 = and(_T_10089, miss_pending) @[el2_ifu_mem_ctl.scala 776:98]
|
|
node _T_10090 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 778:84]
|
|
node _T_10091 = and(_T_10090, miss_pending) @[el2_ifu_mem_ctl.scala 778:108]
|
|
node bus_wren_last_0 = and(_T_10091, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 778:123]
|
|
node _T_10092 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 778:84]
|
|
node _T_10093 = and(_T_10092, miss_pending) @[el2_ifu_mem_ctl.scala 778:108]
|
|
node bus_wren_last_1 = and(_T_10093, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 778:123]
|
|
node wren_reset_miss_0 = and(replace_way_mb_any[0], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 779:84]
|
|
node wren_reset_miss_1 = and(replace_way_mb_any[1], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 779:84]
|
|
node _T_10094 = or(bus_wren_last_0, wren_reset_miss_0) @[el2_ifu_mem_ctl.scala 780:73]
|
|
node _T_10095 = or(bus_wren_last_1, wren_reset_miss_1) @[el2_ifu_mem_ctl.scala 780:73]
|
|
node _T_10096 = cat(_T_10095, _T_10094) @[Cat.scala 29:58]
|
|
ifu_tag_wren <= _T_10096 @[el2_ifu_mem_ctl.scala 780:18]
|
|
node _T_10097 = eq(fetch_uncacheable_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 795:63]
|
|
node _T_10098 = and(_T_10097, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 795:85]
|
|
node _T_10099 = bits(_T_10098, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_10100 = mux(_T_10099, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_10101 = and(ic_tag_valid_unq, _T_10100) @[el2_ifu_mem_ctl.scala 795:39]
|
|
io.ic_tag_valid <= _T_10101 @[el2_ifu_mem_ctl.scala 795:19]
|
|
wire ic_debug_rd_en_ff : UInt<1>
|
|
ic_debug_rd_en_ff <= UInt<1>("h00")
|
|
wire ic_debug_way_ff : UInt<2>
|
|
ic_debug_way_ff <= UInt<1>("h00")
|
|
node _T_10102 = bits(ic_debug_rd_en_ff, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_10103 = mux(_T_10102, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_10104 = and(ic_debug_way_ff, _T_10103) @[el2_ifu_mem_ctl.scala 798:67]
|
|
node _T_10105 = and(ic_tag_valid_unq, _T_10104) @[el2_ifu_mem_ctl.scala 798:48]
|
|
node _T_10106 = orr(_T_10105) @[el2_ifu_mem_ctl.scala 798:115]
|
|
ic_debug_tag_val_rd_out <= _T_10106 @[el2_ifu_mem_ctl.scala 798:27]
|
|
reg _T_10107 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 800:57]
|
|
_T_10107 <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 800:57]
|
|
io.ifu_pmu_ic_miss <= _T_10107 @[el2_ifu_mem_ctl.scala 800:22]
|
|
reg _T_10108 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 801:56]
|
|
_T_10108 <= ic_act_hit_f @[el2_ifu_mem_ctl.scala 801:56]
|
|
io.ifu_pmu_ic_hit <= _T_10108 @[el2_ifu_mem_ctl.scala 801:21]
|
|
reg _T_10109 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 802:59]
|
|
_T_10109 <= ifc_bus_acc_fault_f @[el2_ifu_mem_ctl.scala 802:59]
|
|
io.ifu_pmu_bus_error <= _T_10109 @[el2_ifu_mem_ctl.scala 802:24]
|
|
node _T_10110 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 803:80]
|
|
node _T_10111 = and(ifu_bus_arvalid_ff, _T_10110) @[el2_ifu_mem_ctl.scala 803:78]
|
|
node _T_10112 = and(_T_10111, miss_pending) @[el2_ifu_mem_ctl.scala 803:100]
|
|
reg _T_10113 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 803:58]
|
|
_T_10113 <= _T_10112 @[el2_ifu_mem_ctl.scala 803:58]
|
|
io.ifu_pmu_bus_busy <= _T_10113 @[el2_ifu_mem_ctl.scala 803:23]
|
|
reg _T_10114 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 804:58]
|
|
_T_10114 <= bus_cmd_sent @[el2_ifu_mem_ctl.scala 804:58]
|
|
io.ifu_pmu_bus_trxn <= _T_10114 @[el2_ifu_mem_ctl.scala 804:23]
|
|
io.ic_debug_addr <= io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_ifu_mem_ctl.scala 807:20]
|
|
node _T_10115 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[el2_ifu_mem_ctl.scala 808:66]
|
|
io.ic_debug_tag_array <= _T_10115 @[el2_ifu_mem_ctl.scala 808:25]
|
|
io.ic_debug_rd_en <= io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_ifu_mem_ctl.scala 809:21]
|
|
io.ic_debug_wr_en <= io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_ifu_mem_ctl.scala 810:21]
|
|
node _T_10116 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 811:64]
|
|
node _T_10117 = eq(_T_10116, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 811:71]
|
|
node _T_10118 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 811:117]
|
|
node _T_10119 = eq(_T_10118, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 811:124]
|
|
node _T_10120 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 812:43]
|
|
node _T_10121 = eq(_T_10120, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 812:50]
|
|
node _T_10122 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 812:96]
|
|
node _T_10123 = eq(_T_10122, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 812:103]
|
|
node _T_10124 = cat(_T_10121, _T_10123) @[Cat.scala 29:58]
|
|
node _T_10125 = cat(_T_10117, _T_10119) @[Cat.scala 29:58]
|
|
node _T_10126 = cat(_T_10125, _T_10124) @[Cat.scala 29:58]
|
|
io.ic_debug_way <= _T_10126 @[el2_ifu_mem_ctl.scala 811:19]
|
|
node _T_10127 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 813:65]
|
|
node _T_10128 = bits(_T_10127, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_10129 = mux(_T_10128, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_10130 = and(_T_10129, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 813:90]
|
|
ic_debug_tag_wr_en <= _T_10130 @[el2_ifu_mem_ctl.scala 813:22]
|
|
node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 814:53]
|
|
node _T_10131 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 815:72]
|
|
reg _T_10132 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_10131 : @[Reg.scala 28:19]
|
|
_T_10132 <= io.ic_debug_way @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_debug_way_ff <= _T_10132 @[el2_ifu_mem_ctl.scala 815:19]
|
|
node _T_10133 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 816:92]
|
|
reg _T_10134 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_10133 : @[Reg.scala 28:19]
|
|
_T_10134 <= ic_debug_ict_array_sel_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_debug_ict_array_sel_ff <= _T_10134 @[el2_ifu_mem_ctl.scala 816:29]
|
|
reg _T_10135 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 817:54]
|
|
_T_10135 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 817:54]
|
|
ic_debug_rd_en_ff <= _T_10135 @[el2_ifu_mem_ctl.scala 817:21]
|
|
node _T_10136 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 818:111]
|
|
reg _T_10137 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_10136 : @[Reg.scala 28:19]
|
|
_T_10137 <= ic_debug_rd_en_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
io.ifu_ic_debug_rd_data_valid <= _T_10137 @[el2_ifu_mem_ctl.scala 818:33]
|
|
node _T_10138 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10139 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10140 = cat(_T_10139, _T_10138) @[Cat.scala 29:58]
|
|
node _T_10141 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_10142 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_10143 = cat(_T_10142, _T_10141) @[Cat.scala 29:58]
|
|
node _T_10144 = cat(_T_10143, _T_10140) @[Cat.scala 29:58]
|
|
node _T_10145 = orr(_T_10144) @[el2_ifu_mem_ctl.scala 819:213]
|
|
node _T_10146 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10147 = or(_T_10146, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 820:62]
|
|
node _T_10148 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 820:110]
|
|
node _T_10149 = eq(_T_10147, _T_10148) @[el2_ifu_mem_ctl.scala 820:85]
|
|
node _T_10150 = and(UInt<1>("h01"), _T_10149) @[el2_ifu_mem_ctl.scala 820:27]
|
|
node _T_10151 = or(_T_10145, _T_10150) @[el2_ifu_mem_ctl.scala 819:216]
|
|
node _T_10152 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10153 = or(_T_10152, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 821:62]
|
|
node _T_10154 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 821:110]
|
|
node _T_10155 = eq(_T_10153, _T_10154) @[el2_ifu_mem_ctl.scala 821:85]
|
|
node _T_10156 = and(UInt<1>("h01"), _T_10155) @[el2_ifu_mem_ctl.scala 821:27]
|
|
node _T_10157 = or(_T_10151, _T_10156) @[el2_ifu_mem_ctl.scala 820:134]
|
|
node _T_10158 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10159 = or(_T_10158, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 822:62]
|
|
node _T_10160 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 822:110]
|
|
node _T_10161 = eq(_T_10159, _T_10160) @[el2_ifu_mem_ctl.scala 822:85]
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node _T_10162 = and(UInt<1>("h01"), _T_10161) @[el2_ifu_mem_ctl.scala 822:27]
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node _T_10163 = or(_T_10157, _T_10162) @[el2_ifu_mem_ctl.scala 821:134]
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node _T_10164 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10165 = or(_T_10164, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 823:62]
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node _T_10166 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 823:110]
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node _T_10167 = eq(_T_10165, _T_10166) @[el2_ifu_mem_ctl.scala 823:85]
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node _T_10168 = and(UInt<1>("h01"), _T_10167) @[el2_ifu_mem_ctl.scala 823:27]
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node _T_10169 = or(_T_10163, _T_10168) @[el2_ifu_mem_ctl.scala 822:134]
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node _T_10170 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10171 = or(_T_10170, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:62]
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node _T_10172 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:110]
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node _T_10173 = eq(_T_10171, _T_10172) @[el2_ifu_mem_ctl.scala 824:85]
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node _T_10174 = and(UInt<1>("h00"), _T_10173) @[el2_ifu_mem_ctl.scala 824:27]
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node _T_10175 = or(_T_10169, _T_10174) @[el2_ifu_mem_ctl.scala 823:134]
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node _T_10176 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10177 = or(_T_10176, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:62]
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node _T_10178 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:110]
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node _T_10179 = eq(_T_10177, _T_10178) @[el2_ifu_mem_ctl.scala 825:85]
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node _T_10180 = and(UInt<1>("h00"), _T_10179) @[el2_ifu_mem_ctl.scala 825:27]
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node _T_10181 = or(_T_10175, _T_10180) @[el2_ifu_mem_ctl.scala 824:134]
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node _T_10182 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10183 = or(_T_10182, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 826:62]
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node _T_10184 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 826:110]
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node _T_10185 = eq(_T_10183, _T_10184) @[el2_ifu_mem_ctl.scala 826:85]
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node _T_10186 = and(UInt<1>("h00"), _T_10185) @[el2_ifu_mem_ctl.scala 826:27]
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node _T_10187 = or(_T_10181, _T_10186) @[el2_ifu_mem_ctl.scala 825:134]
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node _T_10188 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10189 = or(_T_10188, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 827:62]
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node _T_10190 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 827:110]
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node _T_10191 = eq(_T_10189, _T_10190) @[el2_ifu_mem_ctl.scala 827:85]
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node _T_10192 = and(UInt<1>("h00"), _T_10191) @[el2_ifu_mem_ctl.scala 827:27]
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node ifc_region_acc_okay = or(_T_10187, _T_10192) @[el2_ifu_mem_ctl.scala 826:134]
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node _T_10193 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 828:40]
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node _T_10194 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 828:65]
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node _T_10195 = and(_T_10193, _T_10194) @[el2_ifu_mem_ctl.scala 828:63]
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node ifc_region_acc_fault_memory_bf = and(_T_10195, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 828:86]
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node _T_10196 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 829:63]
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ifc_region_acc_fault_final_bf <= _T_10196 @[el2_ifu_mem_ctl.scala 829:33]
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reg _T_10197 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 830:66]
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_T_10197 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 830:66]
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ifc_region_acc_fault_memory_f <= _T_10197 @[el2_ifu_mem_ctl.scala 830:33]
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