quasar/el2_ifu_iccm_mem.anno.json

54 lines
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_2",
"sources":[
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_3",
"sources":[
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_1",
"sources":[
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_0",
"sources":[
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_iccm_mem"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]