123 lines
3.6 KiB
Verilog
123 lines
3.6 KiB
Verilog
module dmi_jtag_to_core_sync(
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input clock,
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input reset,
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output io_reg_en,
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output io_reg_wr_en
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);
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`ifdef RANDOMIZE_REG_INIT
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reg [31:0] _RAND_0;
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reg [31:0] _RAND_1;
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`endif // RANDOMIZE_REG_INIT
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reg [2:0] rden; // @[dmi_jtag_to_core_sync.scala 25:18]
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reg [2:0] wren; // @[dmi_jtag_to_core_sync.scala 26:18]
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wire _T_8 = ~rden[2]; // @[dmi_jtag_to_core_sync.scala 28:27]
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wire c_rd_en = rden[1] & _T_8; // @[dmi_jtag_to_core_sync.scala 28:25]
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wire _T_11 = ~wren[2]; // @[dmi_jtag_to_core_sync.scala 29:27]
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wire c_wr_en = wren[1] & _T_11; // @[dmi_jtag_to_core_sync.scala 29:25]
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assign io_reg_en = c_wr_en | c_rd_en; // @[dmi_jtag_to_core_sync.scala 19:16 dmi_jtag_to_core_sync.scala 31:13]
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assign io_reg_wr_en = wren[1] & _T_11; // @[dmi_jtag_to_core_sync.scala 20:16 dmi_jtag_to_core_sync.scala 32:16]
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_INVALID_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif
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`ifndef RANDOM
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`define RANDOM $random
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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integer initvar;
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`endif
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`ifndef SYNTHESIS
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif
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initial begin
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`ifdef RANDOMIZE
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`ifdef INIT_RANDOM
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`INIT_RANDOM
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`endif
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`ifndef VERILATOR
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`ifdef RANDOMIZE_DELAY
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#`RANDOMIZE_DELAY begin end
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`else
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#0.002 begin end
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`endif
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`endif
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`ifdef RANDOMIZE_REG_INIT
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_RAND_0 = {1{`RANDOM}};
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rden = _RAND_0[2:0];
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_RAND_1 = {1{`RANDOM}};
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wren = _RAND_1[2:0];
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`endif // RANDOMIZE_REG_INIT
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if (reset) begin
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rden = 3'h0;
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end
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if (reset) begin
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wren = 3'h0;
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end
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`endif // RANDOMIZE
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif
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`endif // SYNTHESIS
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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rden <= 3'h0;
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end else begin
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rden <= {rden[1:0],1'h0};
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end
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end
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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wren <= 3'h0;
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end else begin
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wren <= {wren[1:0],1'h0};
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end
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end
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endmodule
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module dmi_wrapper(
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input clock,
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input reset,
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input io_tck,
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input io_tms,
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input io_tdi,
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output io_tdo,
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output io_tdoEnable,
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input io_core_clk,
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input [31:0] io_jtag_id,
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input [31:0] io_rd_data,
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output [31:0] io_reg_wr_data,
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output [6:0] io_reg_wr_addr,
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output io_reg_en,
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output io_reg_wr_en,
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output io_dmi_hard_reset
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);
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wire i_dmi_jtag_to_core_sync_clock; // @[dmi_wrapper.scala 56:40]
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wire i_dmi_jtag_to_core_sync_reset; // @[dmi_wrapper.scala 56:40]
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wire i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 56:40]
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wire i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 56:40]
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dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync ( // @[dmi_wrapper.scala 56:40]
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.clock(i_dmi_jtag_to_core_sync_clock),
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.reset(i_dmi_jtag_to_core_sync_reset),
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.io_reg_en(i_dmi_jtag_to_core_sync_io_reg_en),
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.io_reg_wr_en(i_dmi_jtag_to_core_sync_io_reg_wr_en)
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);
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assign io_tdo = 1'h0; // @[dmi_wrapper.scala 46:27]
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assign io_tdoEnable = 1'h0; // @[dmi_wrapper.scala 47:27]
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assign io_reg_wr_data = 32'h0; // @[dmi_wrapper.scala 48:27]
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assign io_reg_wr_addr = 7'h0; // @[dmi_wrapper.scala 49:27]
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assign io_reg_en = i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 59:39]
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assign io_reg_wr_en = i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 60:39]
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assign io_dmi_hard_reset = 1'h0; // @[dmi_wrapper.scala 52:27]
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assign i_dmi_jtag_to_core_sync_clock = clock;
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assign i_dmi_jtag_to_core_sync_reset = reset;
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endmodule
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