4674 lines
356 KiB
Plaintext
4674 lines
356 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_pic_ctrl :
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_3 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_3 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_4 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_4 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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module el2_pic_ctrl :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip scan_mode : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, flip extintsrc_req : UInt<32>, flip picm_rdaddr : UInt<32>, flip picm_wraddr : UInt<32>, flip picm_wr_data : UInt<32>, flip picm_wren : UInt<1>, flip picm_rden : UInt<1>, flip picm_mken : UInt<1>, flip meicurpl : UInt<4>, flip meipt : UInt<4>, mexintpend : UInt<1>, claimid : UInt<8>, pl : UInt<4>, picm_rd_data : UInt<32>, mhwakeup : UInt<1>}
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wire GW_CONFIG : UInt<32>
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GW_CONFIG <= UInt<1>("h00")
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wire intpend_rd_out : UInt<32>
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intpend_rd_out <= UInt<32>("h00")
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wire intenable_rd_out : UInt<1>
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intenable_rd_out <= UInt<1>("h00")
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wire intpriority_reg_inv : UInt<4>[32] @[el2_pic_ctl.scala 81:42]
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wire intpend_reg_extended : UInt<64>
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intpend_reg_extended <= UInt<64>("h00")
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wire selected_int_priority : UInt<4>
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selected_int_priority <= UInt<4>("h00")
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wire intpend_w_prior_en : UInt<4>[32] @[el2_pic_ctl.scala 84:42]
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wire intpend_id : UInt<8>[32] @[el2_pic_ctl.scala 85:42]
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wire levelx_intpend_w_prior_en : UInt<4>[10][4] @[el2_pic_ctl.scala 86:42]
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levelx_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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levelx_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158]
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wire levelx_intpend_id : UInt<8>[10][4] @[el2_pic_ctl.scala 88:42]
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levelx_intpend_id[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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levelx_intpend_id[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150]
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wire l2_intpend_w_prior_en_ff : UInt<4>[8] @[el2_pic_ctl.scala 90:42]
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l2_intpend_w_prior_en_ff[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109]
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l2_intpend_w_prior_en_ff[1] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109]
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l2_intpend_w_prior_en_ff[2] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109]
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l2_intpend_w_prior_en_ff[3] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109]
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l2_intpend_w_prior_en_ff[4] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109]
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l2_intpend_w_prior_en_ff[5] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109]
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l2_intpend_w_prior_en_ff[6] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109]
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l2_intpend_w_prior_en_ff[7] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109]
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wire l2_intpend_id_ff : UInt<8>[8] @[el2_pic_ctl.scala 92:42]
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l2_intpend_id_ff[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101]
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l2_intpend_id_ff[1] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101]
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l2_intpend_id_ff[2] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101]
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l2_intpend_id_ff[3] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101]
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l2_intpend_id_ff[4] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101]
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l2_intpend_id_ff[5] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101]
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l2_intpend_id_ff[6] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101]
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l2_intpend_id_ff[7] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101]
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wire config_reg : UInt<1>
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config_reg <= UInt<1>("h00")
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wire intpriord : UInt<1>
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intpriord <= UInt<1>("h00")
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wire prithresh_reg_write : UInt<1>
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prithresh_reg_write <= UInt<1>("h00")
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wire prithresh_reg_read : UInt<1>
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prithresh_reg_read <= UInt<1>("h00")
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wire picm_wren_ff : UInt<1>
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picm_wren_ff <= UInt<1>("h00")
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wire picm_rden_ff : UInt<1>
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picm_rden_ff <= UInt<1>("h00")
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wire picm_raddr_ff : UInt<32>
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picm_raddr_ff <= UInt<32>("h00")
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wire picm_waddr_ff : UInt<32>
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picm_waddr_ff <= UInt<32>("h00")
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wire picm_wr_data_ff : UInt<32>
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picm_wr_data_ff <= UInt<32>("h00")
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wire mask : UInt<4>
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mask <= UInt<4>("h00")
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wire picm_mken_ff : UInt<1>
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picm_mken_ff <= UInt<1>("h00")
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wire claimid_in : UInt<8>
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claimid_in <= UInt<8>("h00")
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wire pic_raddr_c1_clk : Clock @[el2_pic_ctl.scala 109:42]
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wire pic_data_c1_clk : Clock @[el2_pic_ctl.scala 110:42]
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wire pic_pri_c1_clk : Clock @[el2_pic_ctl.scala 111:42]
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wire pic_int_c1_clk : Clock @[el2_pic_ctl.scala 112:42]
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wire gw_config_c1_clk : Clock @[el2_pic_ctl.scala 113:42]
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reg _T : UInt, pic_raddr_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 115:56]
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_T <= io.picm_rdaddr @[el2_pic_ctl.scala 115:56]
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picm_raddr_ff <= _T @[el2_pic_ctl.scala 115:46]
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reg _T_1 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 116:57]
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_T_1 <= io.picm_wraddr @[el2_pic_ctl.scala 116:57]
|
|
picm_waddr_ff <= _T_1 @[el2_pic_ctl.scala 116:46]
|
|
reg _T_2 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 117:55]
|
|
_T_2 <= io.picm_wren @[el2_pic_ctl.scala 117:55]
|
|
picm_wren_ff <= _T_2 @[el2_pic_ctl.scala 117:45]
|
|
reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 118:55]
|
|
_T_3 <= io.picm_rden @[el2_pic_ctl.scala 118:55]
|
|
picm_rden_ff <= _T_3 @[el2_pic_ctl.scala 118:45]
|
|
reg _T_4 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 119:55]
|
|
_T_4 <= io.picm_mken @[el2_pic_ctl.scala 119:55]
|
|
picm_mken_ff <= _T_4 @[el2_pic_ctl.scala 119:45]
|
|
reg _T_5 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 120:58]
|
|
_T_5 <= io.picm_wr_data @[el2_pic_ctl.scala 120:58]
|
|
picm_wr_data_ff <= _T_5 @[el2_pic_ctl.scala 120:48]
|
|
node _T_6 = xor(picm_raddr_ff, UInt<32>("h0f00c2000")) @[el2_pic_ctl.scala 122:59]
|
|
node temp_raddr_intenable_base_match = not(_T_6) @[el2_pic_ctl.scala 122:43]
|
|
node _T_7 = bits(temp_raddr_intenable_base_match, 31, 7) @[el2_pic_ctl.scala 123:71]
|
|
node raddr_intenable_base_match = andr(_T_7) @[el2_pic_ctl.scala 123:89]
|
|
node _T_8 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctl.scala 125:53]
|
|
node raddr_intpriority_base_match = eq(_T_8, UInt<25>("h01e01800")) @[el2_pic_ctl.scala 125:71]
|
|
node _T_9 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctl.scala 126:53]
|
|
node raddr_config_gw_base_match = eq(_T_9, UInt<25>("h01e01880")) @[el2_pic_ctl.scala 126:71]
|
|
node _T_10 = bits(picm_raddr_ff, 31, 0) @[el2_pic_ctl.scala 127:53]
|
|
node raddr_config_pic_match = eq(_T_10, UInt<32>("h0f00c3000")) @[el2_pic_ctl.scala 127:71]
|
|
node _T_11 = bits(picm_raddr_ff, 31, 6) @[el2_pic_ctl.scala 128:53]
|
|
node addr_intpend_base_match = eq(_T_11, UInt<26>("h03c03040")) @[el2_pic_ctl.scala 128:71]
|
|
node _T_12 = bits(picm_waddr_ff, 31, 0) @[el2_pic_ctl.scala 130:53]
|
|
node waddr_config_pic_match = eq(_T_12, UInt<32>("h0f00c3000")) @[el2_pic_ctl.scala 130:71]
|
|
node _T_13 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 131:53]
|
|
node addr_clear_gw_base_match = eq(_T_13, UInt<25>("h01e018a0")) @[el2_pic_ctl.scala 131:71]
|
|
node _T_14 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 132:53]
|
|
node waddr_intpriority_base_match = eq(_T_14, UInt<25>("h01e01800")) @[el2_pic_ctl.scala 132:71]
|
|
node _T_15 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 133:53]
|
|
node waddr_intenable_base_match = eq(_T_15, UInt<25>("h01e01840")) @[el2_pic_ctl.scala 133:71]
|
|
node _T_16 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 134:53]
|
|
node waddr_config_gw_base_match = eq(_T_16, UInt<25>("h01e01880")) @[el2_pic_ctl.scala 134:71]
|
|
node _T_17 = and(picm_rden_ff, picm_wren_ff) @[el2_pic_ctl.scala 135:53]
|
|
node _T_18 = eq(picm_raddr_ff, picm_waddr_ff) @[el2_pic_ctl.scala 135:86]
|
|
node picm_bypass_ff = and(_T_17, _T_18) @[el2_pic_ctl.scala 135:68]
|
|
node _T_19 = or(io.picm_mken, io.picm_rden) @[el2_pic_ctl.scala 139:42]
|
|
node pic_raddr_c1_clken = or(_T_19, io.clk_override) @[el2_pic_ctl.scala 139:57]
|
|
node pic_data_c1_clken = or(io.picm_wren, io.clk_override) @[el2_pic_ctl.scala 140:42]
|
|
node _T_20 = and(waddr_intpriority_base_match, picm_wren_ff) @[el2_pic_ctl.scala 141:59]
|
|
node _T_21 = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctl.scala 141:108]
|
|
node _T_22 = or(_T_20, _T_21) @[el2_pic_ctl.scala 141:76]
|
|
node pic_pri_c1_clken = or(_T_22, io.clk_override) @[el2_pic_ctl.scala 141:124]
|
|
node _T_23 = and(waddr_intenable_base_match, picm_wren_ff) @[el2_pic_ctl.scala 142:57]
|
|
node _T_24 = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctl.scala 142:104]
|
|
node _T_25 = or(_T_23, _T_24) @[el2_pic_ctl.scala 142:74]
|
|
node pic_int_c1_clken = or(_T_25, io.clk_override) @[el2_pic_ctl.scala 142:120]
|
|
node _T_26 = and(waddr_config_gw_base_match, picm_wren_ff) @[el2_pic_ctl.scala 143:59]
|
|
node _T_27 = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctl.scala 143:108]
|
|
node _T_28 = or(_T_26, _T_27) @[el2_pic_ctl.scala 143:76]
|
|
node gw_config_c1_clken = or(_T_28, io.clk_override) @[el2_pic_ctl.scala 143:124]
|
|
inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22]
|
|
rvclkhdr.clock <= clock
|
|
rvclkhdr.reset <= reset
|
|
rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17]
|
|
rvclkhdr.io.en <= pic_raddr_c1_clken @[el2_lib.scala 485:16]
|
|
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
|
pic_raddr_c1_clk <= rvclkhdr.io.l1clk @[el2_pic_ctl.scala 146:21]
|
|
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22]
|
|
rvclkhdr_1.clock <= clock
|
|
rvclkhdr_1.reset <= reset
|
|
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17]
|
|
rvclkhdr_1.io.en <= pic_data_c1_clken @[el2_lib.scala 485:16]
|
|
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
|
pic_data_c1_clk <= rvclkhdr_1.io.l1clk @[el2_pic_ctl.scala 147:21]
|
|
node _T_29 = bits(pic_pri_c1_clken, 0, 0) @[el2_pic_ctl.scala 148:56]
|
|
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22]
|
|
rvclkhdr_2.clock <= clock
|
|
rvclkhdr_2.reset <= reset
|
|
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17]
|
|
rvclkhdr_2.io.en <= _T_29 @[el2_lib.scala 485:16]
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
|
pic_pri_c1_clk <= rvclkhdr_2.io.l1clk @[el2_pic_ctl.scala 148:21]
|
|
node _T_30 = bits(pic_int_c1_clken, 0, 0) @[el2_pic_ctl.scala 149:56]
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 483:22]
|
|
rvclkhdr_3.clock <= clock
|
|
rvclkhdr_3.reset <= reset
|
|
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17]
|
|
rvclkhdr_3.io.en <= _T_30 @[el2_lib.scala 485:16]
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
|
pic_int_c1_clk <= rvclkhdr_3.io.l1clk @[el2_pic_ctl.scala 149:21]
|
|
node _T_31 = bits(gw_config_c1_clken, 0, 0) @[el2_pic_ctl.scala 150:58]
|
|
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 483:22]
|
|
rvclkhdr_4.clock <= clock
|
|
rvclkhdr_4.reset <= reset
|
|
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17]
|
|
rvclkhdr_4.io.en <= _T_31 @[el2_lib.scala 485:16]
|
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
|
gw_config_c1_clk <= rvclkhdr_4.io.l1clk @[el2_pic_ctl.scala 150:21]
|
|
node _T_32 = bits(io.extintsrc_req, 31, 1) @[el2_pic_ctl.scala 153:58]
|
|
reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 176:81]
|
|
_T_33 <= _T_32 @[el2_lib.scala 176:81]
|
|
reg _T_34 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 176:58]
|
|
_T_34 <= _T_33 @[el2_lib.scala 176:58]
|
|
node _T_35 = bits(io.extintsrc_req, 0, 0) @[el2_pic_ctl.scala 153:113]
|
|
node extintsrc_req_sync = cat(_T_34, _T_35) @[Cat.scala 29:58]
|
|
node _T_36 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_37 = eq(_T_36, UInt<1>("h01")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_38 = and(waddr_intpriority_base_match, _T_37) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_1 = and(_T_38, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_39 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_41 = and(waddr_intpriority_base_match, _T_40) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_2 = and(_T_41, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_42 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_43 = eq(_T_42, UInt<2>("h03")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_44 = and(waddr_intpriority_base_match, _T_43) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_3 = and(_T_44, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_45 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_46 = eq(_T_45, UInt<3>("h04")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_47 = and(waddr_intpriority_base_match, _T_46) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_4 = and(_T_47, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_48 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_49 = eq(_T_48, UInt<3>("h05")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_50 = and(waddr_intpriority_base_match, _T_49) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_5 = and(_T_50, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_51 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_52 = eq(_T_51, UInt<3>("h06")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_53 = and(waddr_intpriority_base_match, _T_52) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_6 = and(_T_53, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_54 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_55 = eq(_T_54, UInt<3>("h07")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_56 = and(waddr_intpriority_base_match, _T_55) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_7 = and(_T_56, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_57 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_58 = eq(_T_57, UInt<4>("h08")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_59 = and(waddr_intpriority_base_match, _T_58) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_8 = and(_T_59, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_60 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_61 = eq(_T_60, UInt<4>("h09")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_62 = and(waddr_intpriority_base_match, _T_61) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_9 = and(_T_62, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_63 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_64 = eq(_T_63, UInt<4>("h0a")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_65 = and(waddr_intpriority_base_match, _T_64) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_10 = and(_T_65, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_66 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_67 = eq(_T_66, UInt<4>("h0b")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_68 = and(waddr_intpriority_base_match, _T_67) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_11 = and(_T_68, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_69 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_70 = eq(_T_69, UInt<4>("h0c")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_71 = and(waddr_intpriority_base_match, _T_70) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_12 = and(_T_71, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_72 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_73 = eq(_T_72, UInt<4>("h0d")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_74 = and(waddr_intpriority_base_match, _T_73) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_13 = and(_T_74, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_75 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_76 = eq(_T_75, UInt<4>("h0e")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_77 = and(waddr_intpriority_base_match, _T_76) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_14 = and(_T_77, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_78 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_79 = eq(_T_78, UInt<4>("h0f")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_80 = and(waddr_intpriority_base_match, _T_79) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_15 = and(_T_80, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_81 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_82 = eq(_T_81, UInt<5>("h010")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_83 = and(waddr_intpriority_base_match, _T_82) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_16 = and(_T_83, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_84 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_85 = eq(_T_84, UInt<5>("h011")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_86 = and(waddr_intpriority_base_match, _T_85) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_17 = and(_T_86, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_87 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_88 = eq(_T_87, UInt<5>("h012")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_89 = and(waddr_intpriority_base_match, _T_88) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_18 = and(_T_89, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_90 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_91 = eq(_T_90, UInt<5>("h013")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_92 = and(waddr_intpriority_base_match, _T_91) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_19 = and(_T_92, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_93 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_94 = eq(_T_93, UInt<5>("h014")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_95 = and(waddr_intpriority_base_match, _T_94) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_20 = and(_T_95, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_96 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_97 = eq(_T_96, UInt<5>("h015")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_98 = and(waddr_intpriority_base_match, _T_97) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_21 = and(_T_98, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_99 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_100 = eq(_T_99, UInt<5>("h016")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_101 = and(waddr_intpriority_base_match, _T_100) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_22 = and(_T_101, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_102 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_103 = eq(_T_102, UInt<5>("h017")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_104 = and(waddr_intpriority_base_match, _T_103) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_23 = and(_T_104, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_105 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_106 = eq(_T_105, UInt<5>("h018")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_107 = and(waddr_intpriority_base_match, _T_106) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_24 = and(_T_107, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_108 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_109 = eq(_T_108, UInt<5>("h019")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_110 = and(waddr_intpriority_base_match, _T_109) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_25 = and(_T_110, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_111 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_112 = eq(_T_111, UInt<5>("h01a")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_113 = and(waddr_intpriority_base_match, _T_112) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_26 = and(_T_113, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_114 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_115 = eq(_T_114, UInt<5>("h01b")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_116 = and(waddr_intpriority_base_match, _T_115) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_27 = and(_T_116, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_117 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_118 = eq(_T_117, UInt<5>("h01c")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_119 = and(waddr_intpriority_base_match, _T_118) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_28 = and(_T_119, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_120 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
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node _T_121 = eq(_T_120, UInt<5>("h01d")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_122 = and(waddr_intpriority_base_match, _T_121) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_29 = and(_T_122, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_123 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
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node _T_124 = eq(_T_123, UInt<5>("h01e")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_125 = and(waddr_intpriority_base_match, _T_124) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_30 = and(_T_125, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_126 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122]
|
|
node _T_127 = eq(_T_126, UInt<5>("h01f")) @[el2_pic_ctl.scala 155:139]
|
|
node _T_128 = and(waddr_intpriority_base_match, _T_127) @[el2_pic_ctl.scala 155:106]
|
|
node intpriority_reg_we_31 = and(_T_128, picm_wren_ff) @[el2_pic_ctl.scala 155:153]
|
|
node _T_129 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_130 = eq(_T_129, UInt<1>("h01")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_131 = and(raddr_intpriority_base_match, _T_130) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_1 = and(_T_131, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_132 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_133 = eq(_T_132, UInt<2>("h02")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_134 = and(raddr_intpriority_base_match, _T_133) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_2 = and(_T_134, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_135 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_136 = eq(_T_135, UInt<2>("h03")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_137 = and(raddr_intpriority_base_match, _T_136) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_3 = and(_T_137, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_138 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_139 = eq(_T_138, UInt<3>("h04")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_140 = and(raddr_intpriority_base_match, _T_139) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_4 = and(_T_140, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_141 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_142 = eq(_T_141, UInt<3>("h05")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_143 = and(raddr_intpriority_base_match, _T_142) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_5 = and(_T_143, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_144 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_145 = eq(_T_144, UInt<3>("h06")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_146 = and(raddr_intpriority_base_match, _T_145) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_6 = and(_T_146, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_147 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_148 = eq(_T_147, UInt<3>("h07")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_149 = and(raddr_intpriority_base_match, _T_148) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_7 = and(_T_149, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_150 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_151 = eq(_T_150, UInt<4>("h08")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_152 = and(raddr_intpriority_base_match, _T_151) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_8 = and(_T_152, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_153 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_154 = eq(_T_153, UInt<4>("h09")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_155 = and(raddr_intpriority_base_match, _T_154) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_9 = and(_T_155, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_156 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_157 = eq(_T_156, UInt<4>("h0a")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_158 = and(raddr_intpriority_base_match, _T_157) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_10 = and(_T_158, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_159 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_160 = eq(_T_159, UInt<4>("h0b")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_161 = and(raddr_intpriority_base_match, _T_160) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_11 = and(_T_161, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_162 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_163 = eq(_T_162, UInt<4>("h0c")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_164 = and(raddr_intpriority_base_match, _T_163) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_12 = and(_T_164, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_165 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_166 = eq(_T_165, UInt<4>("h0d")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_167 = and(raddr_intpriority_base_match, _T_166) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_13 = and(_T_167, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_168 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_169 = eq(_T_168, UInt<4>("h0e")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_170 = and(raddr_intpriority_base_match, _T_169) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_14 = and(_T_170, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_171 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_172 = eq(_T_171, UInt<4>("h0f")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_173 = and(raddr_intpriority_base_match, _T_172) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_15 = and(_T_173, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_174 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_175 = eq(_T_174, UInt<5>("h010")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_176 = and(raddr_intpriority_base_match, _T_175) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_16 = and(_T_176, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_177 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_178 = eq(_T_177, UInt<5>("h011")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_179 = and(raddr_intpriority_base_match, _T_178) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_17 = and(_T_179, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_180 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_181 = eq(_T_180, UInt<5>("h012")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_182 = and(raddr_intpriority_base_match, _T_181) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_18 = and(_T_182, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_183 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_184 = eq(_T_183, UInt<5>("h013")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_185 = and(raddr_intpriority_base_match, _T_184) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_19 = and(_T_185, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_186 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_187 = eq(_T_186, UInt<5>("h014")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_188 = and(raddr_intpriority_base_match, _T_187) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_20 = and(_T_188, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_189 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_190 = eq(_T_189, UInt<5>("h015")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_191 = and(raddr_intpriority_base_match, _T_190) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_21 = and(_T_191, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_192 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_193 = eq(_T_192, UInt<5>("h016")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_194 = and(raddr_intpriority_base_match, _T_193) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_22 = and(_T_194, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_195 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_196 = eq(_T_195, UInt<5>("h017")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_197 = and(raddr_intpriority_base_match, _T_196) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_23 = and(_T_197, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_198 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_199 = eq(_T_198, UInt<5>("h018")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_200 = and(raddr_intpriority_base_match, _T_199) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_24 = and(_T_200, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_201 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_202 = eq(_T_201, UInt<5>("h019")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_203 = and(raddr_intpriority_base_match, _T_202) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_25 = and(_T_203, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_204 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_205 = eq(_T_204, UInt<5>("h01a")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_206 = and(raddr_intpriority_base_match, _T_205) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_26 = and(_T_206, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_207 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_208 = eq(_T_207, UInt<5>("h01b")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_209 = and(raddr_intpriority_base_match, _T_208) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_27 = and(_T_209, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_210 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_211 = eq(_T_210, UInt<5>("h01c")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_212 = and(raddr_intpriority_base_match, _T_211) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_28 = and(_T_212, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_213 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_214 = eq(_T_213, UInt<5>("h01d")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_215 = and(raddr_intpriority_base_match, _T_214) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_29 = and(_T_215, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_216 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_217 = eq(_T_216, UInt<5>("h01e")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_218 = and(raddr_intpriority_base_match, _T_217) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_30 = and(_T_218, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_219 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122]
|
|
node _T_220 = eq(_T_219, UInt<5>("h01f")) @[el2_pic_ctl.scala 156:139]
|
|
node _T_221 = and(raddr_intpriority_base_match, _T_220) @[el2_pic_ctl.scala 156:106]
|
|
node intpriority_reg_re_31 = and(_T_221, picm_rden_ff) @[el2_pic_ctl.scala 156:153]
|
|
node _T_222 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_223 = eq(_T_222, UInt<1>("h01")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_224 = and(waddr_intenable_base_match, _T_223) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_1 = and(_T_224, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_225 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_226 = eq(_T_225, UInt<2>("h02")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_227 = and(waddr_intenable_base_match, _T_226) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_2 = and(_T_227, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_228 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_229 = eq(_T_228, UInt<2>("h03")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_230 = and(waddr_intenable_base_match, _T_229) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_3 = and(_T_230, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_231 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_232 = eq(_T_231, UInt<3>("h04")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_233 = and(waddr_intenable_base_match, _T_232) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_4 = and(_T_233, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_234 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_235 = eq(_T_234, UInt<3>("h05")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_236 = and(waddr_intenable_base_match, _T_235) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_5 = and(_T_236, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_237 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_238 = eq(_T_237, UInt<3>("h06")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_239 = and(waddr_intenable_base_match, _T_238) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_6 = and(_T_239, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_240 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_241 = eq(_T_240, UInt<3>("h07")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_242 = and(waddr_intenable_base_match, _T_241) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_7 = and(_T_242, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_243 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_244 = eq(_T_243, UInt<4>("h08")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_245 = and(waddr_intenable_base_match, _T_244) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_8 = and(_T_245, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_246 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_247 = eq(_T_246, UInt<4>("h09")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_248 = and(waddr_intenable_base_match, _T_247) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_9 = and(_T_248, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_249 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
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node _T_250 = eq(_T_249, UInt<4>("h0a")) @[el2_pic_ctl.scala 157:139]
|
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node _T_251 = and(waddr_intenable_base_match, _T_250) @[el2_pic_ctl.scala 157:106]
|
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node intenable_reg_we_10 = and(_T_251, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_252 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
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node _T_253 = eq(_T_252, UInt<4>("h0b")) @[el2_pic_ctl.scala 157:139]
|
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node _T_254 = and(waddr_intenable_base_match, _T_253) @[el2_pic_ctl.scala 157:106]
|
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node intenable_reg_we_11 = and(_T_254, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_255 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
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node _T_256 = eq(_T_255, UInt<4>("h0c")) @[el2_pic_ctl.scala 157:139]
|
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node _T_257 = and(waddr_intenable_base_match, _T_256) @[el2_pic_ctl.scala 157:106]
|
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node intenable_reg_we_12 = and(_T_257, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_258 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
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node _T_259 = eq(_T_258, UInt<4>("h0d")) @[el2_pic_ctl.scala 157:139]
|
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node _T_260 = and(waddr_intenable_base_match, _T_259) @[el2_pic_ctl.scala 157:106]
|
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node intenable_reg_we_13 = and(_T_260, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_261 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
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node _T_262 = eq(_T_261, UInt<4>("h0e")) @[el2_pic_ctl.scala 157:139]
|
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node _T_263 = and(waddr_intenable_base_match, _T_262) @[el2_pic_ctl.scala 157:106]
|
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node intenable_reg_we_14 = and(_T_263, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_264 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
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node _T_265 = eq(_T_264, UInt<4>("h0f")) @[el2_pic_ctl.scala 157:139]
|
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node _T_266 = and(waddr_intenable_base_match, _T_265) @[el2_pic_ctl.scala 157:106]
|
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node intenable_reg_we_15 = and(_T_266, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_267 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
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node _T_268 = eq(_T_267, UInt<5>("h010")) @[el2_pic_ctl.scala 157:139]
|
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node _T_269 = and(waddr_intenable_base_match, _T_268) @[el2_pic_ctl.scala 157:106]
|
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node intenable_reg_we_16 = and(_T_269, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_270 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
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node _T_271 = eq(_T_270, UInt<5>("h011")) @[el2_pic_ctl.scala 157:139]
|
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node _T_272 = and(waddr_intenable_base_match, _T_271) @[el2_pic_ctl.scala 157:106]
|
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node intenable_reg_we_17 = and(_T_272, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_273 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
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node _T_274 = eq(_T_273, UInt<5>("h012")) @[el2_pic_ctl.scala 157:139]
|
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node _T_275 = and(waddr_intenable_base_match, _T_274) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_18 = and(_T_275, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_276 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
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node _T_277 = eq(_T_276, UInt<5>("h013")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_278 = and(waddr_intenable_base_match, _T_277) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_19 = and(_T_278, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_279 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
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node _T_280 = eq(_T_279, UInt<5>("h014")) @[el2_pic_ctl.scala 157:139]
|
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node _T_281 = and(waddr_intenable_base_match, _T_280) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_20 = and(_T_281, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
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node _T_282 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_283 = eq(_T_282, UInt<5>("h015")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_284 = and(waddr_intenable_base_match, _T_283) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_21 = and(_T_284, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_285 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_286 = eq(_T_285, UInt<5>("h016")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_287 = and(waddr_intenable_base_match, _T_286) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_22 = and(_T_287, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_288 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_289 = eq(_T_288, UInt<5>("h017")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_290 = and(waddr_intenable_base_match, _T_289) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_23 = and(_T_290, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_291 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_292 = eq(_T_291, UInt<5>("h018")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_293 = and(waddr_intenable_base_match, _T_292) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_24 = and(_T_293, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_294 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_295 = eq(_T_294, UInt<5>("h019")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_296 = and(waddr_intenable_base_match, _T_295) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_25 = and(_T_296, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_297 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_298 = eq(_T_297, UInt<5>("h01a")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_299 = and(waddr_intenable_base_match, _T_298) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_26 = and(_T_299, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_300 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_301 = eq(_T_300, UInt<5>("h01b")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_302 = and(waddr_intenable_base_match, _T_301) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_27 = and(_T_302, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_303 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_304 = eq(_T_303, UInt<5>("h01c")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_305 = and(waddr_intenable_base_match, _T_304) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_28 = and(_T_305, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_306 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_307 = eq(_T_306, UInt<5>("h01d")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_308 = and(waddr_intenable_base_match, _T_307) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_29 = and(_T_308, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_309 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_310 = eq(_T_309, UInt<5>("h01e")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_311 = and(waddr_intenable_base_match, _T_310) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_30 = and(_T_311, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_312 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122]
|
|
node _T_313 = eq(_T_312, UInt<5>("h01f")) @[el2_pic_ctl.scala 157:139]
|
|
node _T_314 = and(waddr_intenable_base_match, _T_313) @[el2_pic_ctl.scala 157:106]
|
|
node intenable_reg_we_31 = and(_T_314, picm_wren_ff) @[el2_pic_ctl.scala 157:153]
|
|
node _T_315 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_316 = eq(_T_315, UInt<1>("h01")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_317 = and(raddr_intenable_base_match, _T_316) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_1 = and(_T_317, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_318 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_319 = eq(_T_318, UInt<2>("h02")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_320 = and(raddr_intenable_base_match, _T_319) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_2 = and(_T_320, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_321 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_322 = eq(_T_321, UInt<2>("h03")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_323 = and(raddr_intenable_base_match, _T_322) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_3 = and(_T_323, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_324 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_325 = eq(_T_324, UInt<3>("h04")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_326 = and(raddr_intenable_base_match, _T_325) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_4 = and(_T_326, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_327 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_328 = eq(_T_327, UInt<3>("h05")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_329 = and(raddr_intenable_base_match, _T_328) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_5 = and(_T_329, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_330 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_331 = eq(_T_330, UInt<3>("h06")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_332 = and(raddr_intenable_base_match, _T_331) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_6 = and(_T_332, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_333 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_334 = eq(_T_333, UInt<3>("h07")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_335 = and(raddr_intenable_base_match, _T_334) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_7 = and(_T_335, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_336 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_337 = eq(_T_336, UInt<4>("h08")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_338 = and(raddr_intenable_base_match, _T_337) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_8 = and(_T_338, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_339 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_340 = eq(_T_339, UInt<4>("h09")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_341 = and(raddr_intenable_base_match, _T_340) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_9 = and(_T_341, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_342 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_343 = eq(_T_342, UInt<4>("h0a")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_344 = and(raddr_intenable_base_match, _T_343) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_10 = and(_T_344, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_345 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_346 = eq(_T_345, UInt<4>("h0b")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_347 = and(raddr_intenable_base_match, _T_346) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_11 = and(_T_347, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_348 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_349 = eq(_T_348, UInt<4>("h0c")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_350 = and(raddr_intenable_base_match, _T_349) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_12 = and(_T_350, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_351 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_352 = eq(_T_351, UInt<4>("h0d")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_353 = and(raddr_intenable_base_match, _T_352) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_13 = and(_T_353, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_354 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_355 = eq(_T_354, UInt<4>("h0e")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_356 = and(raddr_intenable_base_match, _T_355) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_14 = and(_T_356, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_357 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_358 = eq(_T_357, UInt<4>("h0f")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_359 = and(raddr_intenable_base_match, _T_358) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_15 = and(_T_359, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_360 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_361 = eq(_T_360, UInt<5>("h010")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_362 = and(raddr_intenable_base_match, _T_361) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_16 = and(_T_362, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_363 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_364 = eq(_T_363, UInt<5>("h011")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_365 = and(raddr_intenable_base_match, _T_364) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_17 = and(_T_365, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_366 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_367 = eq(_T_366, UInt<5>("h012")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_368 = and(raddr_intenable_base_match, _T_367) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_18 = and(_T_368, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_369 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_370 = eq(_T_369, UInt<5>("h013")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_371 = and(raddr_intenable_base_match, _T_370) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_19 = and(_T_371, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_372 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_373 = eq(_T_372, UInt<5>("h014")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_374 = and(raddr_intenable_base_match, _T_373) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_20 = and(_T_374, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_375 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_376 = eq(_T_375, UInt<5>("h015")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_377 = and(raddr_intenable_base_match, _T_376) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_21 = and(_T_377, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_378 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_379 = eq(_T_378, UInt<5>("h016")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_380 = and(raddr_intenable_base_match, _T_379) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_22 = and(_T_380, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_381 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_382 = eq(_T_381, UInt<5>("h017")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_383 = and(raddr_intenable_base_match, _T_382) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_23 = and(_T_383, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
|
|
node _T_384 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
|
|
node _T_385 = eq(_T_384, UInt<5>("h018")) @[el2_pic_ctl.scala 158:139]
|
|
node _T_386 = and(raddr_intenable_base_match, _T_385) @[el2_pic_ctl.scala 158:106]
|
|
node intenable_reg_re_24 = and(_T_386, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
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node _T_387 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
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node _T_388 = eq(_T_387, UInt<5>("h019")) @[el2_pic_ctl.scala 158:139]
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node _T_389 = and(raddr_intenable_base_match, _T_388) @[el2_pic_ctl.scala 158:106]
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node intenable_reg_re_25 = and(_T_389, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
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node _T_390 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
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node _T_391 = eq(_T_390, UInt<5>("h01a")) @[el2_pic_ctl.scala 158:139]
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node _T_392 = and(raddr_intenable_base_match, _T_391) @[el2_pic_ctl.scala 158:106]
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node intenable_reg_re_26 = and(_T_392, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
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node _T_393 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
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node _T_394 = eq(_T_393, UInt<5>("h01b")) @[el2_pic_ctl.scala 158:139]
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node _T_395 = and(raddr_intenable_base_match, _T_394) @[el2_pic_ctl.scala 158:106]
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node intenable_reg_re_27 = and(_T_395, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
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node _T_396 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
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node _T_397 = eq(_T_396, UInt<5>("h01c")) @[el2_pic_ctl.scala 158:139]
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node _T_398 = and(raddr_intenable_base_match, _T_397) @[el2_pic_ctl.scala 158:106]
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node intenable_reg_re_28 = and(_T_398, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
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node _T_399 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
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node _T_400 = eq(_T_399, UInt<5>("h01d")) @[el2_pic_ctl.scala 158:139]
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node _T_401 = and(raddr_intenable_base_match, _T_400) @[el2_pic_ctl.scala 158:106]
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node intenable_reg_re_29 = and(_T_401, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
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node _T_402 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
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node _T_403 = eq(_T_402, UInt<5>("h01e")) @[el2_pic_ctl.scala 158:139]
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node _T_404 = and(raddr_intenable_base_match, _T_403) @[el2_pic_ctl.scala 158:106]
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node intenable_reg_re_30 = and(_T_404, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
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node _T_405 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122]
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node _T_406 = eq(_T_405, UInt<5>("h01f")) @[el2_pic_ctl.scala 158:139]
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node _T_407 = and(raddr_intenable_base_match, _T_406) @[el2_pic_ctl.scala 158:106]
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node intenable_reg_re_31 = and(_T_407, picm_rden_ff) @[el2_pic_ctl.scala 158:153]
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node _T_408 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
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node _T_409 = eq(_T_408, UInt<1>("h01")) @[el2_pic_ctl.scala 159:139]
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node _T_410 = and(waddr_config_gw_base_match, _T_409) @[el2_pic_ctl.scala 159:106]
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node gw_config_reg_we_1 = and(_T_410, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
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node _T_411 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
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node _T_412 = eq(_T_411, UInt<2>("h02")) @[el2_pic_ctl.scala 159:139]
|
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node _T_413 = and(waddr_config_gw_base_match, _T_412) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_2 = and(_T_413, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
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node _T_414 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_415 = eq(_T_414, UInt<2>("h03")) @[el2_pic_ctl.scala 159:139]
|
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node _T_416 = and(waddr_config_gw_base_match, _T_415) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_3 = and(_T_416, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_417 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_418 = eq(_T_417, UInt<3>("h04")) @[el2_pic_ctl.scala 159:139]
|
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node _T_419 = and(waddr_config_gw_base_match, _T_418) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_4 = and(_T_419, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
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node _T_420 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_421 = eq(_T_420, UInt<3>("h05")) @[el2_pic_ctl.scala 159:139]
|
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node _T_422 = and(waddr_config_gw_base_match, _T_421) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_5 = and(_T_422, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_423 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_424 = eq(_T_423, UInt<3>("h06")) @[el2_pic_ctl.scala 159:139]
|
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node _T_425 = and(waddr_config_gw_base_match, _T_424) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_6 = and(_T_425, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_426 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_427 = eq(_T_426, UInt<3>("h07")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_428 = and(waddr_config_gw_base_match, _T_427) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_7 = and(_T_428, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_429 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_430 = eq(_T_429, UInt<4>("h08")) @[el2_pic_ctl.scala 159:139]
|
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node _T_431 = and(waddr_config_gw_base_match, _T_430) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_8 = and(_T_431, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_432 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_433 = eq(_T_432, UInt<4>("h09")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_434 = and(waddr_config_gw_base_match, _T_433) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_9 = and(_T_434, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_435 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_436 = eq(_T_435, UInt<4>("h0a")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_437 = and(waddr_config_gw_base_match, _T_436) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_10 = and(_T_437, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_438 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_439 = eq(_T_438, UInt<4>("h0b")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_440 = and(waddr_config_gw_base_match, _T_439) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_11 = and(_T_440, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
|
node _T_441 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_442 = eq(_T_441, UInt<4>("h0c")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_443 = and(waddr_config_gw_base_match, _T_442) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_12 = and(_T_443, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
|
node _T_444 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_445 = eq(_T_444, UInt<4>("h0d")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_446 = and(waddr_config_gw_base_match, _T_445) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_13 = and(_T_446, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_447 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_448 = eq(_T_447, UInt<4>("h0e")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_449 = and(waddr_config_gw_base_match, _T_448) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_14 = and(_T_449, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
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node _T_450 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_451 = eq(_T_450, UInt<4>("h0f")) @[el2_pic_ctl.scala 159:139]
|
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node _T_452 = and(waddr_config_gw_base_match, _T_451) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_15 = and(_T_452, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_453 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_454 = eq(_T_453, UInt<5>("h010")) @[el2_pic_ctl.scala 159:139]
|
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node _T_455 = and(waddr_config_gw_base_match, _T_454) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_16 = and(_T_455, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
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node _T_456 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_457 = eq(_T_456, UInt<5>("h011")) @[el2_pic_ctl.scala 159:139]
|
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node _T_458 = and(waddr_config_gw_base_match, _T_457) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_17 = and(_T_458, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
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node _T_459 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_460 = eq(_T_459, UInt<5>("h012")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_461 = and(waddr_config_gw_base_match, _T_460) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_18 = and(_T_461, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_462 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
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node _T_463 = eq(_T_462, UInt<5>("h013")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_464 = and(waddr_config_gw_base_match, _T_463) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_19 = and(_T_464, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_465 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_466 = eq(_T_465, UInt<5>("h014")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_467 = and(waddr_config_gw_base_match, _T_466) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_20 = and(_T_467, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_468 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_469 = eq(_T_468, UInt<5>("h015")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_470 = and(waddr_config_gw_base_match, _T_469) @[el2_pic_ctl.scala 159:106]
|
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node gw_config_reg_we_21 = and(_T_470, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_471 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_472 = eq(_T_471, UInt<5>("h016")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_473 = and(waddr_config_gw_base_match, _T_472) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_22 = and(_T_473, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_474 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_475 = eq(_T_474, UInt<5>("h017")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_476 = and(waddr_config_gw_base_match, _T_475) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_23 = and(_T_476, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
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node _T_477 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_478 = eq(_T_477, UInt<5>("h018")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_479 = and(waddr_config_gw_base_match, _T_478) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_24 = and(_T_479, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
|
node _T_480 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_481 = eq(_T_480, UInt<5>("h019")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_482 = and(waddr_config_gw_base_match, _T_481) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_25 = and(_T_482, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
|
node _T_483 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_484 = eq(_T_483, UInt<5>("h01a")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_485 = and(waddr_config_gw_base_match, _T_484) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_26 = and(_T_485, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
|
node _T_486 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_487 = eq(_T_486, UInt<5>("h01b")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_488 = and(waddr_config_gw_base_match, _T_487) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_27 = and(_T_488, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
|
node _T_489 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_490 = eq(_T_489, UInt<5>("h01c")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_491 = and(waddr_config_gw_base_match, _T_490) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_28 = and(_T_491, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
|
node _T_492 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_493 = eq(_T_492, UInt<5>("h01d")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_494 = and(waddr_config_gw_base_match, _T_493) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_29 = and(_T_494, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
|
node _T_495 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_496 = eq(_T_495, UInt<5>("h01e")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_497 = and(waddr_config_gw_base_match, _T_496) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_30 = and(_T_497, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
|
node _T_498 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122]
|
|
node _T_499 = eq(_T_498, UInt<5>("h01f")) @[el2_pic_ctl.scala 159:139]
|
|
node _T_500 = and(waddr_config_gw_base_match, _T_499) @[el2_pic_ctl.scala 159:106]
|
|
node gw_config_reg_we_31 = and(_T_500, picm_wren_ff) @[el2_pic_ctl.scala 159:153]
|
|
node _T_501 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_502 = eq(_T_501, UInt<1>("h01")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_503 = and(raddr_config_gw_base_match, _T_502) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_1 = and(_T_503, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_504 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_505 = eq(_T_504, UInt<2>("h02")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_506 = and(raddr_config_gw_base_match, _T_505) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_2 = and(_T_506, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_507 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_508 = eq(_T_507, UInt<2>("h03")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_509 = and(raddr_config_gw_base_match, _T_508) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_3 = and(_T_509, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_510 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_511 = eq(_T_510, UInt<3>("h04")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_512 = and(raddr_config_gw_base_match, _T_511) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_4 = and(_T_512, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_513 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_514 = eq(_T_513, UInt<3>("h05")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_515 = and(raddr_config_gw_base_match, _T_514) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_5 = and(_T_515, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_516 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_517 = eq(_T_516, UInt<3>("h06")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_518 = and(raddr_config_gw_base_match, _T_517) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_6 = and(_T_518, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_519 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_520 = eq(_T_519, UInt<3>("h07")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_521 = and(raddr_config_gw_base_match, _T_520) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_7 = and(_T_521, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_522 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_523 = eq(_T_522, UInt<4>("h08")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_524 = and(raddr_config_gw_base_match, _T_523) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_8 = and(_T_524, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_525 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_526 = eq(_T_525, UInt<4>("h09")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_527 = and(raddr_config_gw_base_match, _T_526) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_9 = and(_T_527, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_528 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_529 = eq(_T_528, UInt<4>("h0a")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_530 = and(raddr_config_gw_base_match, _T_529) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_10 = and(_T_530, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_531 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_532 = eq(_T_531, UInt<4>("h0b")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_533 = and(raddr_config_gw_base_match, _T_532) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_11 = and(_T_533, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_534 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_535 = eq(_T_534, UInt<4>("h0c")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_536 = and(raddr_config_gw_base_match, _T_535) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_12 = and(_T_536, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_537 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_538 = eq(_T_537, UInt<4>("h0d")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_539 = and(raddr_config_gw_base_match, _T_538) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_13 = and(_T_539, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_540 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_541 = eq(_T_540, UInt<4>("h0e")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_542 = and(raddr_config_gw_base_match, _T_541) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_14 = and(_T_542, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_543 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_544 = eq(_T_543, UInt<4>("h0f")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_545 = and(raddr_config_gw_base_match, _T_544) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_15 = and(_T_545, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_546 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_547 = eq(_T_546, UInt<5>("h010")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_548 = and(raddr_config_gw_base_match, _T_547) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_16 = and(_T_548, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_549 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_550 = eq(_T_549, UInt<5>("h011")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_551 = and(raddr_config_gw_base_match, _T_550) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_17 = and(_T_551, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_552 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_553 = eq(_T_552, UInt<5>("h012")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_554 = and(raddr_config_gw_base_match, _T_553) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_18 = and(_T_554, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_555 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_556 = eq(_T_555, UInt<5>("h013")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_557 = and(raddr_config_gw_base_match, _T_556) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_19 = and(_T_557, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_558 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_559 = eq(_T_558, UInt<5>("h014")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_560 = and(raddr_config_gw_base_match, _T_559) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_20 = and(_T_560, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_561 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_562 = eq(_T_561, UInt<5>("h015")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_563 = and(raddr_config_gw_base_match, _T_562) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_21 = and(_T_563, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_564 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_565 = eq(_T_564, UInt<5>("h016")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_566 = and(raddr_config_gw_base_match, _T_565) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_22 = and(_T_566, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_567 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_568 = eq(_T_567, UInt<5>("h017")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_569 = and(raddr_config_gw_base_match, _T_568) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_23 = and(_T_569, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_570 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_571 = eq(_T_570, UInt<5>("h018")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_572 = and(raddr_config_gw_base_match, _T_571) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_24 = and(_T_572, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_573 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_574 = eq(_T_573, UInt<5>("h019")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_575 = and(raddr_config_gw_base_match, _T_574) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_25 = and(_T_575, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_576 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_577 = eq(_T_576, UInt<5>("h01a")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_578 = and(raddr_config_gw_base_match, _T_577) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_26 = and(_T_578, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_579 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_580 = eq(_T_579, UInt<5>("h01b")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_581 = and(raddr_config_gw_base_match, _T_580) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_27 = and(_T_581, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_582 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_583 = eq(_T_582, UInt<5>("h01c")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_584 = and(raddr_config_gw_base_match, _T_583) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_28 = and(_T_584, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_585 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_586 = eq(_T_585, UInt<5>("h01d")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_587 = and(raddr_config_gw_base_match, _T_586) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_29 = and(_T_587, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_588 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_589 = eq(_T_588, UInt<5>("h01e")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_590 = and(raddr_config_gw_base_match, _T_589) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_30 = and(_T_590, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_591 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122]
|
|
node _T_592 = eq(_T_591, UInt<5>("h01f")) @[el2_pic_ctl.scala 160:139]
|
|
node _T_593 = and(raddr_config_gw_base_match, _T_592) @[el2_pic_ctl.scala 160:106]
|
|
node gw_config_reg_re_31 = and(_T_593, picm_rden_ff) @[el2_pic_ctl.scala 160:153]
|
|
node _T_594 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_595 = eq(_T_594, UInt<1>("h01")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_596 = and(addr_clear_gw_base_match, _T_595) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_1 = and(_T_596, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_597 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_598 = eq(_T_597, UInt<2>("h02")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_599 = and(addr_clear_gw_base_match, _T_598) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_2 = and(_T_599, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_600 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_601 = eq(_T_600, UInt<2>("h03")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_602 = and(addr_clear_gw_base_match, _T_601) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_3 = and(_T_602, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_603 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_604 = eq(_T_603, UInt<3>("h04")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_605 = and(addr_clear_gw_base_match, _T_604) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_4 = and(_T_605, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_606 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_607 = eq(_T_606, UInt<3>("h05")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_608 = and(addr_clear_gw_base_match, _T_607) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_5 = and(_T_608, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_609 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_610 = eq(_T_609, UInt<3>("h06")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_611 = and(addr_clear_gw_base_match, _T_610) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_6 = and(_T_611, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_612 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_613 = eq(_T_612, UInt<3>("h07")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_614 = and(addr_clear_gw_base_match, _T_613) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_7 = and(_T_614, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_615 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_616 = eq(_T_615, UInt<4>("h08")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_617 = and(addr_clear_gw_base_match, _T_616) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_8 = and(_T_617, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_618 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_619 = eq(_T_618, UInt<4>("h09")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_620 = and(addr_clear_gw_base_match, _T_619) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_9 = and(_T_620, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_621 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_622 = eq(_T_621, UInt<4>("h0a")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_623 = and(addr_clear_gw_base_match, _T_622) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_10 = and(_T_623, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_624 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_625 = eq(_T_624, UInt<4>("h0b")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_626 = and(addr_clear_gw_base_match, _T_625) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_11 = and(_T_626, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_627 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_628 = eq(_T_627, UInt<4>("h0c")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_629 = and(addr_clear_gw_base_match, _T_628) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_12 = and(_T_629, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_630 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_631 = eq(_T_630, UInt<4>("h0d")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_632 = and(addr_clear_gw_base_match, _T_631) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_13 = and(_T_632, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_633 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_634 = eq(_T_633, UInt<4>("h0e")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_635 = and(addr_clear_gw_base_match, _T_634) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_14 = and(_T_635, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_636 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_637 = eq(_T_636, UInt<4>("h0f")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_638 = and(addr_clear_gw_base_match, _T_637) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_15 = and(_T_638, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_639 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_640 = eq(_T_639, UInt<5>("h010")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_641 = and(addr_clear_gw_base_match, _T_640) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_16 = and(_T_641, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_642 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_643 = eq(_T_642, UInt<5>("h011")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_644 = and(addr_clear_gw_base_match, _T_643) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_17 = and(_T_644, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_645 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_646 = eq(_T_645, UInt<5>("h012")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_647 = and(addr_clear_gw_base_match, _T_646) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_18 = and(_T_647, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_648 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_649 = eq(_T_648, UInt<5>("h013")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_650 = and(addr_clear_gw_base_match, _T_649) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_19 = and(_T_650, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_651 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_652 = eq(_T_651, UInt<5>("h014")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_653 = and(addr_clear_gw_base_match, _T_652) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_20 = and(_T_653, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_654 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_655 = eq(_T_654, UInt<5>("h015")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_656 = and(addr_clear_gw_base_match, _T_655) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_21 = and(_T_656, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_657 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_658 = eq(_T_657, UInt<5>("h016")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_659 = and(addr_clear_gw_base_match, _T_658) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_22 = and(_T_659, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_660 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_661 = eq(_T_660, UInt<5>("h017")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_662 = and(addr_clear_gw_base_match, _T_661) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_23 = and(_T_662, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_663 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_664 = eq(_T_663, UInt<5>("h018")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_665 = and(addr_clear_gw_base_match, _T_664) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_24 = and(_T_665, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_666 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_667 = eq(_T_666, UInt<5>("h019")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_668 = and(addr_clear_gw_base_match, _T_667) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_25 = and(_T_668, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_669 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_670 = eq(_T_669, UInt<5>("h01a")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_671 = and(addr_clear_gw_base_match, _T_670) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_26 = and(_T_671, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_672 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_673 = eq(_T_672, UInt<5>("h01b")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_674 = and(addr_clear_gw_base_match, _T_673) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_27 = and(_T_674, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_675 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_676 = eq(_T_675, UInt<5>("h01c")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_677 = and(addr_clear_gw_base_match, _T_676) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_28 = and(_T_677, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_678 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_679 = eq(_T_678, UInt<5>("h01d")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_680 = and(addr_clear_gw_base_match, _T_679) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_29 = and(_T_680, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_681 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_682 = eq(_T_681, UInt<5>("h01e")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_683 = and(addr_clear_gw_base_match, _T_682) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_30 = and(_T_683, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
node _T_684 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122]
|
|
node _T_685 = eq(_T_684, UInt<5>("h01f")) @[el2_pic_ctl.scala 161:139]
|
|
node _T_686 = and(addr_clear_gw_base_match, _T_685) @[el2_pic_ctl.scala 161:106]
|
|
node gw_clear_reg_we_31 = and(_T_686, picm_wren_ff) @[el2_pic_ctl.scala 161:153]
|
|
wire intpriority_reg : UInt<4>[32] @[el2_pic_ctl.scala 162:32]
|
|
intpriority_reg[0] <= UInt<4>("h00") @[el2_pic_ctl.scala 163:208]
|
|
node _T_687 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_688 = bits(intpriority_reg_we_1, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_689 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_688 : @[Reg.scala 28:19]
|
|
_T_689 <= _T_687 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[1] <= _T_689 @[el2_pic_ctl.scala 163:71]
|
|
node _T_690 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_691 = bits(intpriority_reg_we_2, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_692 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_691 : @[Reg.scala 28:19]
|
|
_T_692 <= _T_690 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[2] <= _T_692 @[el2_pic_ctl.scala 163:71]
|
|
node _T_693 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_694 = bits(intpriority_reg_we_3, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_695 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_694 : @[Reg.scala 28:19]
|
|
_T_695 <= _T_693 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[3] <= _T_695 @[el2_pic_ctl.scala 163:71]
|
|
node _T_696 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_697 = bits(intpriority_reg_we_4, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_698 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_697 : @[Reg.scala 28:19]
|
|
_T_698 <= _T_696 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[4] <= _T_698 @[el2_pic_ctl.scala 163:71]
|
|
node _T_699 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_700 = bits(intpriority_reg_we_5, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_701 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_700 : @[Reg.scala 28:19]
|
|
_T_701 <= _T_699 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[5] <= _T_701 @[el2_pic_ctl.scala 163:71]
|
|
node _T_702 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_703 = bits(intpriority_reg_we_6, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_704 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_703 : @[Reg.scala 28:19]
|
|
_T_704 <= _T_702 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[6] <= _T_704 @[el2_pic_ctl.scala 163:71]
|
|
node _T_705 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_706 = bits(intpriority_reg_we_7, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_707 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_706 : @[Reg.scala 28:19]
|
|
_T_707 <= _T_705 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[7] <= _T_707 @[el2_pic_ctl.scala 163:71]
|
|
node _T_708 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_709 = bits(intpriority_reg_we_8, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_710 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_709 : @[Reg.scala 28:19]
|
|
_T_710 <= _T_708 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[8] <= _T_710 @[el2_pic_ctl.scala 163:71]
|
|
node _T_711 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_712 = bits(intpriority_reg_we_9, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_713 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_712 : @[Reg.scala 28:19]
|
|
_T_713 <= _T_711 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[9] <= _T_713 @[el2_pic_ctl.scala 163:71]
|
|
node _T_714 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_715 = bits(intpriority_reg_we_10, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_716 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_715 : @[Reg.scala 28:19]
|
|
_T_716 <= _T_714 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[10] <= _T_716 @[el2_pic_ctl.scala 163:71]
|
|
node _T_717 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_718 = bits(intpriority_reg_we_11, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_719 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_718 : @[Reg.scala 28:19]
|
|
_T_719 <= _T_717 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[11] <= _T_719 @[el2_pic_ctl.scala 163:71]
|
|
node _T_720 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_721 = bits(intpriority_reg_we_12, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_722 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_721 : @[Reg.scala 28:19]
|
|
_T_722 <= _T_720 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[12] <= _T_722 @[el2_pic_ctl.scala 163:71]
|
|
node _T_723 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_724 = bits(intpriority_reg_we_13, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_725 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_724 : @[Reg.scala 28:19]
|
|
_T_725 <= _T_723 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[13] <= _T_725 @[el2_pic_ctl.scala 163:71]
|
|
node _T_726 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_727 = bits(intpriority_reg_we_14, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_728 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_727 : @[Reg.scala 28:19]
|
|
_T_728 <= _T_726 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[14] <= _T_728 @[el2_pic_ctl.scala 163:71]
|
|
node _T_729 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_730 = bits(intpriority_reg_we_15, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_731 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_730 : @[Reg.scala 28:19]
|
|
_T_731 <= _T_729 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[15] <= _T_731 @[el2_pic_ctl.scala 163:71]
|
|
node _T_732 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_733 = bits(intpriority_reg_we_16, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_734 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_733 : @[Reg.scala 28:19]
|
|
_T_734 <= _T_732 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[16] <= _T_734 @[el2_pic_ctl.scala 163:71]
|
|
node _T_735 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_736 = bits(intpriority_reg_we_17, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_737 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_736 : @[Reg.scala 28:19]
|
|
_T_737 <= _T_735 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[17] <= _T_737 @[el2_pic_ctl.scala 163:71]
|
|
node _T_738 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_739 = bits(intpriority_reg_we_18, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_740 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_739 : @[Reg.scala 28:19]
|
|
_T_740 <= _T_738 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[18] <= _T_740 @[el2_pic_ctl.scala 163:71]
|
|
node _T_741 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_742 = bits(intpriority_reg_we_19, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_743 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_742 : @[Reg.scala 28:19]
|
|
_T_743 <= _T_741 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[19] <= _T_743 @[el2_pic_ctl.scala 163:71]
|
|
node _T_744 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_745 = bits(intpriority_reg_we_20, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_746 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_745 : @[Reg.scala 28:19]
|
|
_T_746 <= _T_744 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[20] <= _T_746 @[el2_pic_ctl.scala 163:71]
|
|
node _T_747 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_748 = bits(intpriority_reg_we_21, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_749 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_748 : @[Reg.scala 28:19]
|
|
_T_749 <= _T_747 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[21] <= _T_749 @[el2_pic_ctl.scala 163:71]
|
|
node _T_750 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_751 = bits(intpriority_reg_we_22, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_752 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_751 : @[Reg.scala 28:19]
|
|
_T_752 <= _T_750 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[22] <= _T_752 @[el2_pic_ctl.scala 163:71]
|
|
node _T_753 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_754 = bits(intpriority_reg_we_23, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_755 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_754 : @[Reg.scala 28:19]
|
|
_T_755 <= _T_753 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[23] <= _T_755 @[el2_pic_ctl.scala 163:71]
|
|
node _T_756 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_757 = bits(intpriority_reg_we_24, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_758 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_757 : @[Reg.scala 28:19]
|
|
_T_758 <= _T_756 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[24] <= _T_758 @[el2_pic_ctl.scala 163:71]
|
|
node _T_759 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_760 = bits(intpriority_reg_we_25, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_761 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_760 : @[Reg.scala 28:19]
|
|
_T_761 <= _T_759 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[25] <= _T_761 @[el2_pic_ctl.scala 163:71]
|
|
node _T_762 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_763 = bits(intpriority_reg_we_26, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_764 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_763 : @[Reg.scala 28:19]
|
|
_T_764 <= _T_762 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[26] <= _T_764 @[el2_pic_ctl.scala 163:71]
|
|
node _T_765 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_766 = bits(intpriority_reg_we_27, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_767 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_766 : @[Reg.scala 28:19]
|
|
_T_767 <= _T_765 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[27] <= _T_767 @[el2_pic_ctl.scala 163:71]
|
|
node _T_768 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_769 = bits(intpriority_reg_we_28, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_770 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_769 : @[Reg.scala 28:19]
|
|
_T_770 <= _T_768 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[28] <= _T_770 @[el2_pic_ctl.scala 163:71]
|
|
node _T_771 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_772 = bits(intpriority_reg_we_29, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_773 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_772 : @[Reg.scala 28:19]
|
|
_T_773 <= _T_771 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[29] <= _T_773 @[el2_pic_ctl.scala 163:71]
|
|
node _T_774 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_775 = bits(intpriority_reg_we_30, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_776 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_775 : @[Reg.scala 28:19]
|
|
_T_776 <= _T_774 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[30] <= _T_776 @[el2_pic_ctl.scala 163:71]
|
|
node _T_777 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125]
|
|
node _T_778 = bits(intpriority_reg_we_31, 0, 0) @[el2_pic_ctl.scala 163:174]
|
|
reg _T_779 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_778 : @[Reg.scala 28:19]
|
|
_T_779 <= _T_777 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intpriority_reg[31] <= _T_779 @[el2_pic_ctl.scala 163:71]
|
|
wire intenable_reg : UInt<1>[32] @[el2_pic_ctl.scala 164:32]
|
|
intenable_reg[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 165:182]
|
|
node _T_780 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_781 = bits(intenable_reg_we_1, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_782 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_781 : @[Reg.scala 28:19]
|
|
_T_782 <= _T_780 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[1] <= _T_782 @[el2_pic_ctl.scala 165:68]
|
|
node _T_783 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_784 = bits(intenable_reg_we_2, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_785 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_784 : @[Reg.scala 28:19]
|
|
_T_785 <= _T_783 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[2] <= _T_785 @[el2_pic_ctl.scala 165:68]
|
|
node _T_786 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_787 = bits(intenable_reg_we_3, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_788 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_787 : @[Reg.scala 28:19]
|
|
_T_788 <= _T_786 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[3] <= _T_788 @[el2_pic_ctl.scala 165:68]
|
|
node _T_789 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_790 = bits(intenable_reg_we_4, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_791 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_790 : @[Reg.scala 28:19]
|
|
_T_791 <= _T_789 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[4] <= _T_791 @[el2_pic_ctl.scala 165:68]
|
|
node _T_792 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_793 = bits(intenable_reg_we_5, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_794 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_793 : @[Reg.scala 28:19]
|
|
_T_794 <= _T_792 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[5] <= _T_794 @[el2_pic_ctl.scala 165:68]
|
|
node _T_795 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_796 = bits(intenable_reg_we_6, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_797 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_796 : @[Reg.scala 28:19]
|
|
_T_797 <= _T_795 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[6] <= _T_797 @[el2_pic_ctl.scala 165:68]
|
|
node _T_798 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_799 = bits(intenable_reg_we_7, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_800 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_799 : @[Reg.scala 28:19]
|
|
_T_800 <= _T_798 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[7] <= _T_800 @[el2_pic_ctl.scala 165:68]
|
|
node _T_801 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_802 = bits(intenable_reg_we_8, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_803 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_802 : @[Reg.scala 28:19]
|
|
_T_803 <= _T_801 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[8] <= _T_803 @[el2_pic_ctl.scala 165:68]
|
|
node _T_804 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_805 = bits(intenable_reg_we_9, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_806 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_805 : @[Reg.scala 28:19]
|
|
_T_806 <= _T_804 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[9] <= _T_806 @[el2_pic_ctl.scala 165:68]
|
|
node _T_807 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_808 = bits(intenable_reg_we_10, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_809 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_808 : @[Reg.scala 28:19]
|
|
_T_809 <= _T_807 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[10] <= _T_809 @[el2_pic_ctl.scala 165:68]
|
|
node _T_810 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_811 = bits(intenable_reg_we_11, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_812 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_811 : @[Reg.scala 28:19]
|
|
_T_812 <= _T_810 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[11] <= _T_812 @[el2_pic_ctl.scala 165:68]
|
|
node _T_813 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_814 = bits(intenable_reg_we_12, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_815 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_814 : @[Reg.scala 28:19]
|
|
_T_815 <= _T_813 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[12] <= _T_815 @[el2_pic_ctl.scala 165:68]
|
|
node _T_816 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_817 = bits(intenable_reg_we_13, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_818 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_817 : @[Reg.scala 28:19]
|
|
_T_818 <= _T_816 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[13] <= _T_818 @[el2_pic_ctl.scala 165:68]
|
|
node _T_819 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_820 = bits(intenable_reg_we_14, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_821 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_820 : @[Reg.scala 28:19]
|
|
_T_821 <= _T_819 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[14] <= _T_821 @[el2_pic_ctl.scala 165:68]
|
|
node _T_822 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_823 = bits(intenable_reg_we_15, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_824 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_823 : @[Reg.scala 28:19]
|
|
_T_824 <= _T_822 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[15] <= _T_824 @[el2_pic_ctl.scala 165:68]
|
|
node _T_825 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_826 = bits(intenable_reg_we_16, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_827 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_826 : @[Reg.scala 28:19]
|
|
_T_827 <= _T_825 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[16] <= _T_827 @[el2_pic_ctl.scala 165:68]
|
|
node _T_828 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_829 = bits(intenable_reg_we_17, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_830 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_829 : @[Reg.scala 28:19]
|
|
_T_830 <= _T_828 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[17] <= _T_830 @[el2_pic_ctl.scala 165:68]
|
|
node _T_831 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_832 = bits(intenable_reg_we_18, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_833 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_832 : @[Reg.scala 28:19]
|
|
_T_833 <= _T_831 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[18] <= _T_833 @[el2_pic_ctl.scala 165:68]
|
|
node _T_834 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_835 = bits(intenable_reg_we_19, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_836 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_835 : @[Reg.scala 28:19]
|
|
_T_836 <= _T_834 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[19] <= _T_836 @[el2_pic_ctl.scala 165:68]
|
|
node _T_837 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_838 = bits(intenable_reg_we_20, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_839 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_838 : @[Reg.scala 28:19]
|
|
_T_839 <= _T_837 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[20] <= _T_839 @[el2_pic_ctl.scala 165:68]
|
|
node _T_840 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_841 = bits(intenable_reg_we_21, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_842 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_841 : @[Reg.scala 28:19]
|
|
_T_842 <= _T_840 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[21] <= _T_842 @[el2_pic_ctl.scala 165:68]
|
|
node _T_843 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_844 = bits(intenable_reg_we_22, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_845 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_844 : @[Reg.scala 28:19]
|
|
_T_845 <= _T_843 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[22] <= _T_845 @[el2_pic_ctl.scala 165:68]
|
|
node _T_846 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_847 = bits(intenable_reg_we_23, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_848 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_847 : @[Reg.scala 28:19]
|
|
_T_848 <= _T_846 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[23] <= _T_848 @[el2_pic_ctl.scala 165:68]
|
|
node _T_849 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_850 = bits(intenable_reg_we_24, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_851 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_850 : @[Reg.scala 28:19]
|
|
_T_851 <= _T_849 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[24] <= _T_851 @[el2_pic_ctl.scala 165:68]
|
|
node _T_852 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_853 = bits(intenable_reg_we_25, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_854 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_853 : @[Reg.scala 28:19]
|
|
_T_854 <= _T_852 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[25] <= _T_854 @[el2_pic_ctl.scala 165:68]
|
|
node _T_855 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_856 = bits(intenable_reg_we_26, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_857 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_856 : @[Reg.scala 28:19]
|
|
_T_857 <= _T_855 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[26] <= _T_857 @[el2_pic_ctl.scala 165:68]
|
|
node _T_858 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_859 = bits(intenable_reg_we_27, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_860 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_859 : @[Reg.scala 28:19]
|
|
_T_860 <= _T_858 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[27] <= _T_860 @[el2_pic_ctl.scala 165:68]
|
|
node _T_861 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_862 = bits(intenable_reg_we_28, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_863 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_862 : @[Reg.scala 28:19]
|
|
_T_863 <= _T_861 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[28] <= _T_863 @[el2_pic_ctl.scala 165:68]
|
|
node _T_864 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_865 = bits(intenable_reg_we_29, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_866 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_865 : @[Reg.scala 28:19]
|
|
_T_866 <= _T_864 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[29] <= _T_866 @[el2_pic_ctl.scala 165:68]
|
|
node _T_867 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_868 = bits(intenable_reg_we_30, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_869 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_868 : @[Reg.scala 28:19]
|
|
_T_869 <= _T_867 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[30] <= _T_869 @[el2_pic_ctl.scala 165:68]
|
|
node _T_870 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122]
|
|
node _T_871 = bits(intenable_reg_we_31, 0, 0) @[el2_pic_ctl.scala 165:150]
|
|
reg _T_872 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_871 : @[Reg.scala 28:19]
|
|
_T_872 <= _T_870 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
intenable_reg[31] <= _T_872 @[el2_pic_ctl.scala 165:68]
|
|
wire gw_config_reg : UInt<2>[32] @[el2_pic_ctl.scala 166:32]
|
|
gw_config_reg[0] <= UInt<2>("h00") @[el2_pic_ctl.scala 167:190]
|
|
node _T_873 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_874 = bits(gw_config_reg_we_1, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_875 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_874 : @[Reg.scala 28:19]
|
|
_T_875 <= _T_873 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[1] <= _T_875 @[el2_pic_ctl.scala 167:70]
|
|
node _T_876 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_877 = bits(gw_config_reg_we_2, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_878 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_877 : @[Reg.scala 28:19]
|
|
_T_878 <= _T_876 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[2] <= _T_878 @[el2_pic_ctl.scala 167:70]
|
|
node _T_879 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_880 = bits(gw_config_reg_we_3, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_881 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_880 : @[Reg.scala 28:19]
|
|
_T_881 <= _T_879 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[3] <= _T_881 @[el2_pic_ctl.scala 167:70]
|
|
node _T_882 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_883 = bits(gw_config_reg_we_4, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_884 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_883 : @[Reg.scala 28:19]
|
|
_T_884 <= _T_882 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[4] <= _T_884 @[el2_pic_ctl.scala 167:70]
|
|
node _T_885 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_886 = bits(gw_config_reg_we_5, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_887 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_886 : @[Reg.scala 28:19]
|
|
_T_887 <= _T_885 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[5] <= _T_887 @[el2_pic_ctl.scala 167:70]
|
|
node _T_888 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_889 = bits(gw_config_reg_we_6, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_890 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_889 : @[Reg.scala 28:19]
|
|
_T_890 <= _T_888 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[6] <= _T_890 @[el2_pic_ctl.scala 167:70]
|
|
node _T_891 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_892 = bits(gw_config_reg_we_7, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_893 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_892 : @[Reg.scala 28:19]
|
|
_T_893 <= _T_891 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[7] <= _T_893 @[el2_pic_ctl.scala 167:70]
|
|
node _T_894 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_895 = bits(gw_config_reg_we_8, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_896 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_895 : @[Reg.scala 28:19]
|
|
_T_896 <= _T_894 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[8] <= _T_896 @[el2_pic_ctl.scala 167:70]
|
|
node _T_897 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_898 = bits(gw_config_reg_we_9, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_899 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_898 : @[Reg.scala 28:19]
|
|
_T_899 <= _T_897 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[9] <= _T_899 @[el2_pic_ctl.scala 167:70]
|
|
node _T_900 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_901 = bits(gw_config_reg_we_10, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_902 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_901 : @[Reg.scala 28:19]
|
|
_T_902 <= _T_900 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[10] <= _T_902 @[el2_pic_ctl.scala 167:70]
|
|
node _T_903 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_904 = bits(gw_config_reg_we_11, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_905 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_904 : @[Reg.scala 28:19]
|
|
_T_905 <= _T_903 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[11] <= _T_905 @[el2_pic_ctl.scala 167:70]
|
|
node _T_906 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_907 = bits(gw_config_reg_we_12, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_908 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_907 : @[Reg.scala 28:19]
|
|
_T_908 <= _T_906 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[12] <= _T_908 @[el2_pic_ctl.scala 167:70]
|
|
node _T_909 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_910 = bits(gw_config_reg_we_13, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_911 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_910 : @[Reg.scala 28:19]
|
|
_T_911 <= _T_909 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[13] <= _T_911 @[el2_pic_ctl.scala 167:70]
|
|
node _T_912 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_913 = bits(gw_config_reg_we_14, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_914 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_913 : @[Reg.scala 28:19]
|
|
_T_914 <= _T_912 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[14] <= _T_914 @[el2_pic_ctl.scala 167:70]
|
|
node _T_915 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_916 = bits(gw_config_reg_we_15, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_917 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_916 : @[Reg.scala 28:19]
|
|
_T_917 <= _T_915 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[15] <= _T_917 @[el2_pic_ctl.scala 167:70]
|
|
node _T_918 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_919 = bits(gw_config_reg_we_16, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_920 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_919 : @[Reg.scala 28:19]
|
|
_T_920 <= _T_918 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[16] <= _T_920 @[el2_pic_ctl.scala 167:70]
|
|
node _T_921 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_922 = bits(gw_config_reg_we_17, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_923 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_922 : @[Reg.scala 28:19]
|
|
_T_923 <= _T_921 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[17] <= _T_923 @[el2_pic_ctl.scala 167:70]
|
|
node _T_924 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_925 = bits(gw_config_reg_we_18, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_926 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_925 : @[Reg.scala 28:19]
|
|
_T_926 <= _T_924 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[18] <= _T_926 @[el2_pic_ctl.scala 167:70]
|
|
node _T_927 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_928 = bits(gw_config_reg_we_19, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_929 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_928 : @[Reg.scala 28:19]
|
|
_T_929 <= _T_927 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[19] <= _T_929 @[el2_pic_ctl.scala 167:70]
|
|
node _T_930 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_931 = bits(gw_config_reg_we_20, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_932 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_931 : @[Reg.scala 28:19]
|
|
_T_932 <= _T_930 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[20] <= _T_932 @[el2_pic_ctl.scala 167:70]
|
|
node _T_933 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_934 = bits(gw_config_reg_we_21, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_935 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_934 : @[Reg.scala 28:19]
|
|
_T_935 <= _T_933 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[21] <= _T_935 @[el2_pic_ctl.scala 167:70]
|
|
node _T_936 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_937 = bits(gw_config_reg_we_22, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_938 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_937 : @[Reg.scala 28:19]
|
|
_T_938 <= _T_936 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[22] <= _T_938 @[el2_pic_ctl.scala 167:70]
|
|
node _T_939 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_940 = bits(gw_config_reg_we_23, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_941 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_940 : @[Reg.scala 28:19]
|
|
_T_941 <= _T_939 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[23] <= _T_941 @[el2_pic_ctl.scala 167:70]
|
|
node _T_942 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_943 = bits(gw_config_reg_we_24, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_944 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_943 : @[Reg.scala 28:19]
|
|
_T_944 <= _T_942 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[24] <= _T_944 @[el2_pic_ctl.scala 167:70]
|
|
node _T_945 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_946 = bits(gw_config_reg_we_25, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_947 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_946 : @[Reg.scala 28:19]
|
|
_T_947 <= _T_945 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[25] <= _T_947 @[el2_pic_ctl.scala 167:70]
|
|
node _T_948 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_949 = bits(gw_config_reg_we_26, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_950 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_949 : @[Reg.scala 28:19]
|
|
_T_950 <= _T_948 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[26] <= _T_950 @[el2_pic_ctl.scala 167:70]
|
|
node _T_951 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_952 = bits(gw_config_reg_we_27, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_953 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_952 : @[Reg.scala 28:19]
|
|
_T_953 <= _T_951 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[27] <= _T_953 @[el2_pic_ctl.scala 167:70]
|
|
node _T_954 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_955 = bits(gw_config_reg_we_28, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_956 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_955 : @[Reg.scala 28:19]
|
|
_T_956 <= _T_954 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[28] <= _T_956 @[el2_pic_ctl.scala 167:70]
|
|
node _T_957 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_958 = bits(gw_config_reg_we_29, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_959 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_958 : @[Reg.scala 28:19]
|
|
_T_959 <= _T_957 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[29] <= _T_959 @[el2_pic_ctl.scala 167:70]
|
|
node _T_960 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_961 = bits(gw_config_reg_we_30, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_962 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_961 : @[Reg.scala 28:19]
|
|
_T_962 <= _T_960 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[30] <= _T_962 @[el2_pic_ctl.scala 167:70]
|
|
node _T_963 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126]
|
|
node _T_964 = bits(gw_config_reg_we_31, 0, 0) @[el2_pic_ctl.scala 167:156]
|
|
reg _T_965 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_964 : @[Reg.scala 28:19]
|
|
_T_965 <= _T_963 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
gw_config_reg[31] <= _T_965 @[el2_pic_ctl.scala 167:70]
|
|
node _T_966 = bits(extintsrc_req_sync, 1, 1) @[el2_pic_ctl.scala 170:43]
|
|
node _T_967 = bits(gw_config_reg[1], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_968 = bits(gw_config_reg[1], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_969 = bits(gw_clear_reg_we_1, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending : UInt<1>
|
|
gw_int_pending <= UInt<1>("h00")
|
|
node _T_970 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 45:50]
|
|
node _T_971 = eq(_T_969, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_972 = and(gw_int_pending, _T_971) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in = or(_T_970, _T_972) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_973 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_973 <= gw_int_pending_in @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending <= _T_973 @[el2_pic_ctl.scala 46:20]
|
|
node _T_974 = bits(_T_968, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_975 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 47:55]
|
|
node _T_976 = or(_T_975, gw_int_pending) @[el2_pic_ctl.scala 47:78]
|
|
node _T_977 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_1 = mux(_T_974, _T_976, _T_977) @[el2_pic_ctl.scala 47:8]
|
|
node _T_978 = bits(extintsrc_req_sync, 2, 2) @[el2_pic_ctl.scala 170:43]
|
|
node _T_979 = bits(gw_config_reg[2], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_980 = bits(gw_config_reg[2], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_981 = bits(gw_clear_reg_we_2, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_1 : UInt<1>
|
|
gw_int_pending_1 <= UInt<1>("h00")
|
|
node _T_982 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 45:50]
|
|
node _T_983 = eq(_T_981, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_984 = and(gw_int_pending_1, _T_983) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_1 = or(_T_982, _T_984) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_985 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_985 <= gw_int_pending_in_1 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_1 <= _T_985 @[el2_pic_ctl.scala 46:20]
|
|
node _T_986 = bits(_T_980, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_987 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 47:55]
|
|
node _T_988 = or(_T_987, gw_int_pending_1) @[el2_pic_ctl.scala 47:78]
|
|
node _T_989 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_2 = mux(_T_986, _T_988, _T_989) @[el2_pic_ctl.scala 47:8]
|
|
node _T_990 = bits(extintsrc_req_sync, 3, 3) @[el2_pic_ctl.scala 170:43]
|
|
node _T_991 = bits(gw_config_reg[3], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_992 = bits(gw_config_reg[3], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_993 = bits(gw_clear_reg_we_3, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_2 : UInt<1>
|
|
gw_int_pending_2 <= UInt<1>("h00")
|
|
node _T_994 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 45:50]
|
|
node _T_995 = eq(_T_993, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_996 = and(gw_int_pending_2, _T_995) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_2 = or(_T_994, _T_996) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_997 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_997 <= gw_int_pending_in_2 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_2 <= _T_997 @[el2_pic_ctl.scala 46:20]
|
|
node _T_998 = bits(_T_992, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_999 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1000 = or(_T_999, gw_int_pending_2) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1001 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_3 = mux(_T_998, _T_1000, _T_1001) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1002 = bits(extintsrc_req_sync, 4, 4) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1003 = bits(gw_config_reg[4], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1004 = bits(gw_config_reg[4], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1005 = bits(gw_clear_reg_we_4, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_3 : UInt<1>
|
|
gw_int_pending_3 <= UInt<1>("h00")
|
|
node _T_1006 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1007 = eq(_T_1005, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1008 = and(gw_int_pending_3, _T_1007) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_3 = or(_T_1006, _T_1008) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1009 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1009 <= gw_int_pending_in_3 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_3 <= _T_1009 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1010 = bits(_T_1004, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1011 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1012 = or(_T_1011, gw_int_pending_3) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1013 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_4 = mux(_T_1010, _T_1012, _T_1013) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1014 = bits(extintsrc_req_sync, 5, 5) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1015 = bits(gw_config_reg[5], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1016 = bits(gw_config_reg[5], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1017 = bits(gw_clear_reg_we_5, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_4 : UInt<1>
|
|
gw_int_pending_4 <= UInt<1>("h00")
|
|
node _T_1018 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1019 = eq(_T_1017, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1020 = and(gw_int_pending_4, _T_1019) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_4 = or(_T_1018, _T_1020) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1021 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1021 <= gw_int_pending_in_4 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_4 <= _T_1021 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1022 = bits(_T_1016, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1023 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1024 = or(_T_1023, gw_int_pending_4) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1025 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_5 = mux(_T_1022, _T_1024, _T_1025) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1026 = bits(extintsrc_req_sync, 6, 6) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1027 = bits(gw_config_reg[6], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1028 = bits(gw_config_reg[6], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1029 = bits(gw_clear_reg_we_6, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_5 : UInt<1>
|
|
gw_int_pending_5 <= UInt<1>("h00")
|
|
node _T_1030 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1031 = eq(_T_1029, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1032 = and(gw_int_pending_5, _T_1031) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_5 = or(_T_1030, _T_1032) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1033 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1033 <= gw_int_pending_in_5 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_5 <= _T_1033 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1034 = bits(_T_1028, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1035 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1036 = or(_T_1035, gw_int_pending_5) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1037 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_6 = mux(_T_1034, _T_1036, _T_1037) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1038 = bits(extintsrc_req_sync, 7, 7) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1039 = bits(gw_config_reg[7], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1040 = bits(gw_config_reg[7], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1041 = bits(gw_clear_reg_we_7, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_6 : UInt<1>
|
|
gw_int_pending_6 <= UInt<1>("h00")
|
|
node _T_1042 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1043 = eq(_T_1041, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1044 = and(gw_int_pending_6, _T_1043) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_6 = or(_T_1042, _T_1044) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1045 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1045 <= gw_int_pending_in_6 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_6 <= _T_1045 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1046 = bits(_T_1040, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1047 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1048 = or(_T_1047, gw_int_pending_6) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1049 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_7 = mux(_T_1046, _T_1048, _T_1049) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1050 = bits(extintsrc_req_sync, 8, 8) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1051 = bits(gw_config_reg[8], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1052 = bits(gw_config_reg[8], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1053 = bits(gw_clear_reg_we_8, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_7 : UInt<1>
|
|
gw_int_pending_7 <= UInt<1>("h00")
|
|
node _T_1054 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1055 = eq(_T_1053, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1056 = and(gw_int_pending_7, _T_1055) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_7 = or(_T_1054, _T_1056) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1057 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1057 <= gw_int_pending_in_7 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_7 <= _T_1057 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1058 = bits(_T_1052, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1059 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1060 = or(_T_1059, gw_int_pending_7) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1061 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_8 = mux(_T_1058, _T_1060, _T_1061) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1062 = bits(extintsrc_req_sync, 9, 9) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1063 = bits(gw_config_reg[9], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1064 = bits(gw_config_reg[9], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1065 = bits(gw_clear_reg_we_9, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_8 : UInt<1>
|
|
gw_int_pending_8 <= UInt<1>("h00")
|
|
node _T_1066 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1067 = eq(_T_1065, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1068 = and(gw_int_pending_8, _T_1067) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_8 = or(_T_1066, _T_1068) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1069 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1069 <= gw_int_pending_in_8 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_8 <= _T_1069 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1070 = bits(_T_1064, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1071 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1072 = or(_T_1071, gw_int_pending_8) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1073 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_9 = mux(_T_1070, _T_1072, _T_1073) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1074 = bits(extintsrc_req_sync, 10, 10) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1075 = bits(gw_config_reg[10], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1076 = bits(gw_config_reg[10], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1077 = bits(gw_clear_reg_we_10, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_9 : UInt<1>
|
|
gw_int_pending_9 <= UInt<1>("h00")
|
|
node _T_1078 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1080 = and(gw_int_pending_9, _T_1079) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_9 = or(_T_1078, _T_1080) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1081 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1081 <= gw_int_pending_in_9 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_9 <= _T_1081 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1082 = bits(_T_1076, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1083 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1084 = or(_T_1083, gw_int_pending_9) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1085 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_10 = mux(_T_1082, _T_1084, _T_1085) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1086 = bits(extintsrc_req_sync, 11, 11) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1087 = bits(gw_config_reg[11], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1088 = bits(gw_config_reg[11], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1089 = bits(gw_clear_reg_we_11, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_10 : UInt<1>
|
|
gw_int_pending_10 <= UInt<1>("h00")
|
|
node _T_1090 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1092 = and(gw_int_pending_10, _T_1091) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_10 = or(_T_1090, _T_1092) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1093 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1093 <= gw_int_pending_in_10 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_10 <= _T_1093 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1094 = bits(_T_1088, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1095 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1096 = or(_T_1095, gw_int_pending_10) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1097 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_11 = mux(_T_1094, _T_1096, _T_1097) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1098 = bits(extintsrc_req_sync, 12, 12) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1099 = bits(gw_config_reg[12], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1100 = bits(gw_config_reg[12], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1101 = bits(gw_clear_reg_we_12, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_11 : UInt<1>
|
|
gw_int_pending_11 <= UInt<1>("h00")
|
|
node _T_1102 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 45:50]
|
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node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1104 = and(gw_int_pending_11, _T_1103) @[el2_pic_ctl.scala 45:90]
|
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node gw_int_pending_in_11 = or(_T_1102, _T_1104) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1105 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1105 <= gw_int_pending_in_11 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_11 <= _T_1105 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1106 = bits(_T_1100, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1107 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 47:55]
|
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node _T_1108 = or(_T_1107, gw_int_pending_11) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1109 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 47:117]
|
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node extintsrc_req_gw_12 = mux(_T_1106, _T_1108, _T_1109) @[el2_pic_ctl.scala 47:8]
|
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node _T_1110 = bits(extintsrc_req_sync, 13, 13) @[el2_pic_ctl.scala 170:43]
|
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node _T_1111 = bits(gw_config_reg[13], 0, 0) @[el2_pic_ctl.scala 170:64]
|
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node _T_1112 = bits(gw_config_reg[13], 1, 1) @[el2_pic_ctl.scala 170:85]
|
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node _T_1113 = bits(gw_clear_reg_we_13, 0, 0) @[el2_pic_ctl.scala 170:115]
|
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wire gw_int_pending_12 : UInt<1>
|
|
gw_int_pending_12 <= UInt<1>("h00")
|
|
node _T_1114 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 45:50]
|
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node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
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node _T_1116 = and(gw_int_pending_12, _T_1115) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_12 = or(_T_1114, _T_1116) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1117 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1117 <= gw_int_pending_in_12 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_12 <= _T_1117 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1118 = bits(_T_1112, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1119 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 47:55]
|
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node _T_1120 = or(_T_1119, gw_int_pending_12) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1121 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_13 = mux(_T_1118, _T_1120, _T_1121) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1122 = bits(extintsrc_req_sync, 14, 14) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1123 = bits(gw_config_reg[14], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1124 = bits(gw_config_reg[14], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1125 = bits(gw_clear_reg_we_14, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_13 : UInt<1>
|
|
gw_int_pending_13 <= UInt<1>("h00")
|
|
node _T_1126 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1128 = and(gw_int_pending_13, _T_1127) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_13 = or(_T_1126, _T_1128) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1129 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1129 <= gw_int_pending_in_13 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_13 <= _T_1129 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1130 = bits(_T_1124, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1131 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1132 = or(_T_1131, gw_int_pending_13) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1133 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_14 = mux(_T_1130, _T_1132, _T_1133) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1134 = bits(extintsrc_req_sync, 15, 15) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1135 = bits(gw_config_reg[15], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1136 = bits(gw_config_reg[15], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1137 = bits(gw_clear_reg_we_15, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_14 : UInt<1>
|
|
gw_int_pending_14 <= UInt<1>("h00")
|
|
node _T_1138 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1140 = and(gw_int_pending_14, _T_1139) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_14 = or(_T_1138, _T_1140) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1141 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1141 <= gw_int_pending_in_14 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_14 <= _T_1141 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1142 = bits(_T_1136, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1143 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1144 = or(_T_1143, gw_int_pending_14) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1145 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_15 = mux(_T_1142, _T_1144, _T_1145) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1146 = bits(extintsrc_req_sync, 16, 16) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1147 = bits(gw_config_reg[16], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1148 = bits(gw_config_reg[16], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1149 = bits(gw_clear_reg_we_16, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_15 : UInt<1>
|
|
gw_int_pending_15 <= UInt<1>("h00")
|
|
node _T_1150 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1152 = and(gw_int_pending_15, _T_1151) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_15 = or(_T_1150, _T_1152) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1153 <= gw_int_pending_in_15 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_15 <= _T_1153 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1154 = bits(_T_1148, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1155 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1156 = or(_T_1155, gw_int_pending_15) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1157 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_16 = mux(_T_1154, _T_1156, _T_1157) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1158 = bits(extintsrc_req_sync, 17, 17) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1159 = bits(gw_config_reg[17], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1160 = bits(gw_config_reg[17], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1161 = bits(gw_clear_reg_we_17, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_16 : UInt<1>
|
|
gw_int_pending_16 <= UInt<1>("h00")
|
|
node _T_1162 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1164 = and(gw_int_pending_16, _T_1163) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_16 = or(_T_1162, _T_1164) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1165 <= gw_int_pending_in_16 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_16 <= _T_1165 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1166 = bits(_T_1160, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1167 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1168 = or(_T_1167, gw_int_pending_16) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1169 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_17 = mux(_T_1166, _T_1168, _T_1169) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1170 = bits(extintsrc_req_sync, 18, 18) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1171 = bits(gw_config_reg[18], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1172 = bits(gw_config_reg[18], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1173 = bits(gw_clear_reg_we_18, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_17 : UInt<1>
|
|
gw_int_pending_17 <= UInt<1>("h00")
|
|
node _T_1174 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1176 = and(gw_int_pending_17, _T_1175) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_17 = or(_T_1174, _T_1176) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1177 <= gw_int_pending_in_17 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_17 <= _T_1177 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1178 = bits(_T_1172, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1179 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1180 = or(_T_1179, gw_int_pending_17) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1181 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_18 = mux(_T_1178, _T_1180, _T_1181) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1182 = bits(extintsrc_req_sync, 19, 19) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1183 = bits(gw_config_reg[19], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1184 = bits(gw_config_reg[19], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1185 = bits(gw_clear_reg_we_19, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_18 : UInt<1>
|
|
gw_int_pending_18 <= UInt<1>("h00")
|
|
node _T_1186 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1188 = and(gw_int_pending_18, _T_1187) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_18 = or(_T_1186, _T_1188) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1189 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1189 <= gw_int_pending_in_18 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_18 <= _T_1189 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1190 = bits(_T_1184, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1191 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1192 = or(_T_1191, gw_int_pending_18) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1193 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_19 = mux(_T_1190, _T_1192, _T_1193) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1194 = bits(extintsrc_req_sync, 20, 20) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1195 = bits(gw_config_reg[20], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1196 = bits(gw_config_reg[20], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1197 = bits(gw_clear_reg_we_20, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_19 : UInt<1>
|
|
gw_int_pending_19 <= UInt<1>("h00")
|
|
node _T_1198 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1200 = and(gw_int_pending_19, _T_1199) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_19 = or(_T_1198, _T_1200) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1201 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1201 <= gw_int_pending_in_19 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_19 <= _T_1201 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1202 = bits(_T_1196, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1203 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1204 = or(_T_1203, gw_int_pending_19) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1205 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_20 = mux(_T_1202, _T_1204, _T_1205) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1206 = bits(extintsrc_req_sync, 21, 21) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1207 = bits(gw_config_reg[21], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1208 = bits(gw_config_reg[21], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1209 = bits(gw_clear_reg_we_21, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_20 : UInt<1>
|
|
gw_int_pending_20 <= UInt<1>("h00")
|
|
node _T_1210 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1212 = and(gw_int_pending_20, _T_1211) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_20 = or(_T_1210, _T_1212) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1213 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1213 <= gw_int_pending_in_20 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_20 <= _T_1213 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1214 = bits(_T_1208, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1215 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1216 = or(_T_1215, gw_int_pending_20) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1217 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_21 = mux(_T_1214, _T_1216, _T_1217) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1218 = bits(extintsrc_req_sync, 22, 22) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1219 = bits(gw_config_reg[22], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1220 = bits(gw_config_reg[22], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1221 = bits(gw_clear_reg_we_22, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_21 : UInt<1>
|
|
gw_int_pending_21 <= UInt<1>("h00")
|
|
node _T_1222 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1223 = eq(_T_1221, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1224 = and(gw_int_pending_21, _T_1223) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_21 = or(_T_1222, _T_1224) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1225 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1225 <= gw_int_pending_in_21 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_21 <= _T_1225 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1226 = bits(_T_1220, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1227 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1228 = or(_T_1227, gw_int_pending_21) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1229 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_22 = mux(_T_1226, _T_1228, _T_1229) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1230 = bits(extintsrc_req_sync, 23, 23) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1231 = bits(gw_config_reg[23], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1232 = bits(gw_config_reg[23], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1233 = bits(gw_clear_reg_we_23, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_22 : UInt<1>
|
|
gw_int_pending_22 <= UInt<1>("h00")
|
|
node _T_1234 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1236 = and(gw_int_pending_22, _T_1235) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_22 = or(_T_1234, _T_1236) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1237 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1237 <= gw_int_pending_in_22 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_22 <= _T_1237 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1238 = bits(_T_1232, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1239 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1240 = or(_T_1239, gw_int_pending_22) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1241 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_23 = mux(_T_1238, _T_1240, _T_1241) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1242 = bits(extintsrc_req_sync, 24, 24) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1243 = bits(gw_config_reg[24], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1244 = bits(gw_config_reg[24], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1245 = bits(gw_clear_reg_we_24, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_23 : UInt<1>
|
|
gw_int_pending_23 <= UInt<1>("h00")
|
|
node _T_1246 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1247 = eq(_T_1245, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1248 = and(gw_int_pending_23, _T_1247) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_23 = or(_T_1246, _T_1248) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1249 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1249 <= gw_int_pending_in_23 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_23 <= _T_1249 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1250 = bits(_T_1244, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1251 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1252 = or(_T_1251, gw_int_pending_23) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1253 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_24 = mux(_T_1250, _T_1252, _T_1253) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1254 = bits(extintsrc_req_sync, 25, 25) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1255 = bits(gw_config_reg[25], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1256 = bits(gw_config_reg[25], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1257 = bits(gw_clear_reg_we_25, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_24 : UInt<1>
|
|
gw_int_pending_24 <= UInt<1>("h00")
|
|
node _T_1258 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1259 = eq(_T_1257, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1260 = and(gw_int_pending_24, _T_1259) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_24 = or(_T_1258, _T_1260) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1261 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1261 <= gw_int_pending_in_24 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_24 <= _T_1261 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1262 = bits(_T_1256, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1263 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1264 = or(_T_1263, gw_int_pending_24) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1265 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_25 = mux(_T_1262, _T_1264, _T_1265) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1266 = bits(extintsrc_req_sync, 26, 26) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1267 = bits(gw_config_reg[26], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1268 = bits(gw_config_reg[26], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1269 = bits(gw_clear_reg_we_26, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_25 : UInt<1>
|
|
gw_int_pending_25 <= UInt<1>("h00")
|
|
node _T_1270 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1272 = and(gw_int_pending_25, _T_1271) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_25 = or(_T_1270, _T_1272) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1273 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1273 <= gw_int_pending_in_25 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_25 <= _T_1273 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1274 = bits(_T_1268, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1275 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1276 = or(_T_1275, gw_int_pending_25) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1277 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_26 = mux(_T_1274, _T_1276, _T_1277) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1278 = bits(extintsrc_req_sync, 27, 27) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1279 = bits(gw_config_reg[27], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1280 = bits(gw_config_reg[27], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1281 = bits(gw_clear_reg_we_27, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_26 : UInt<1>
|
|
gw_int_pending_26 <= UInt<1>("h00")
|
|
node _T_1282 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1283 = eq(_T_1281, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1284 = and(gw_int_pending_26, _T_1283) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_26 = or(_T_1282, _T_1284) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1285 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1285 <= gw_int_pending_in_26 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_26 <= _T_1285 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1286 = bits(_T_1280, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1287 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1288 = or(_T_1287, gw_int_pending_26) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1289 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_27 = mux(_T_1286, _T_1288, _T_1289) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1290 = bits(extintsrc_req_sync, 28, 28) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1291 = bits(gw_config_reg[28], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1292 = bits(gw_config_reg[28], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1293 = bits(gw_clear_reg_we_28, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_27 : UInt<1>
|
|
gw_int_pending_27 <= UInt<1>("h00")
|
|
node _T_1294 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1295 = eq(_T_1293, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1296 = and(gw_int_pending_27, _T_1295) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_27 = or(_T_1294, _T_1296) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1297 <= gw_int_pending_in_27 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_27 <= _T_1297 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1298 = bits(_T_1292, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1299 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1300 = or(_T_1299, gw_int_pending_27) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1301 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_28 = mux(_T_1298, _T_1300, _T_1301) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1302 = bits(extintsrc_req_sync, 29, 29) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1303 = bits(gw_config_reg[29], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1304 = bits(gw_config_reg[29], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1305 = bits(gw_clear_reg_we_29, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_28 : UInt<1>
|
|
gw_int_pending_28 <= UInt<1>("h00")
|
|
node _T_1306 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1308 = and(gw_int_pending_28, _T_1307) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_28 = or(_T_1306, _T_1308) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1309 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1309 <= gw_int_pending_in_28 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_28 <= _T_1309 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1310 = bits(_T_1304, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1311 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1312 = or(_T_1311, gw_int_pending_28) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1313 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_29 = mux(_T_1310, _T_1312, _T_1313) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1314 = bits(extintsrc_req_sync, 30, 30) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1315 = bits(gw_config_reg[30], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1316 = bits(gw_config_reg[30], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1317 = bits(gw_clear_reg_we_30, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_29 : UInt<1>
|
|
gw_int_pending_29 <= UInt<1>("h00")
|
|
node _T_1318 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1319 = eq(_T_1317, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1320 = and(gw_int_pending_29, _T_1319) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_29 = or(_T_1318, _T_1320) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1321 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1321 <= gw_int_pending_in_29 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_29 <= _T_1321 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1322 = bits(_T_1316, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1323 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1324 = or(_T_1323, gw_int_pending_29) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1325 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_30 = mux(_T_1322, _T_1324, _T_1325) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1326 = bits(extintsrc_req_sync, 31, 31) @[el2_pic_ctl.scala 170:43]
|
|
node _T_1327 = bits(gw_config_reg[31], 0, 0) @[el2_pic_ctl.scala 170:64]
|
|
node _T_1328 = bits(gw_config_reg[31], 1, 1) @[el2_pic_ctl.scala 170:85]
|
|
node _T_1329 = bits(gw_clear_reg_we_31, 0, 0) @[el2_pic_ctl.scala 170:115]
|
|
wire gw_int_pending_30 : UInt<1>
|
|
gw_int_pending_30 <= UInt<1>("h00")
|
|
node _T_1330 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 45:50]
|
|
node _T_1331 = eq(_T_1329, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92]
|
|
node _T_1332 = and(gw_int_pending_30, _T_1331) @[el2_pic_ctl.scala 45:90]
|
|
node gw_int_pending_in_30 = or(_T_1330, _T_1332) @[el2_pic_ctl.scala 45:72]
|
|
reg _T_1333 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30]
|
|
_T_1333 <= gw_int_pending_in_30 @[el2_pic_ctl.scala 46:30]
|
|
gw_int_pending_30 <= _T_1333 @[el2_pic_ctl.scala 46:20]
|
|
node _T_1334 = bits(_T_1328, 0, 0) @[el2_pic_ctl.scala 47:30]
|
|
node _T_1335 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 47:55]
|
|
node _T_1336 = or(_T_1335, gw_int_pending_30) @[el2_pic_ctl.scala 47:78]
|
|
node _T_1337 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 47:117]
|
|
node extintsrc_req_gw_31 = mux(_T_1334, _T_1336, _T_1337) @[el2_pic_ctl.scala 47:8]
|
|
node _T_1338 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1339 = not(intpriority_reg[0]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1340 = mux(_T_1338, _T_1339, intpriority_reg[0]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[0] <= _T_1340 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1341 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1342 = not(intpriority_reg[1]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1343 = mux(_T_1341, _T_1342, intpriority_reg[1]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[1] <= _T_1343 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1344 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1345 = not(intpriority_reg[2]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1346 = mux(_T_1344, _T_1345, intpriority_reg[2]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[2] <= _T_1346 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1347 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1348 = not(intpriority_reg[3]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1349 = mux(_T_1347, _T_1348, intpriority_reg[3]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[3] <= _T_1349 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1350 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1351 = not(intpriority_reg[4]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1352 = mux(_T_1350, _T_1351, intpriority_reg[4]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[4] <= _T_1352 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1353 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1354 = not(intpriority_reg[5]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1355 = mux(_T_1353, _T_1354, intpriority_reg[5]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[5] <= _T_1355 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1356 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1357 = not(intpriority_reg[6]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1358 = mux(_T_1356, _T_1357, intpriority_reg[6]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[6] <= _T_1358 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1359 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1360 = not(intpriority_reg[7]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1361 = mux(_T_1359, _T_1360, intpriority_reg[7]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[7] <= _T_1361 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1362 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1363 = not(intpriority_reg[8]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1364 = mux(_T_1362, _T_1363, intpriority_reg[8]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[8] <= _T_1364 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1365 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1366 = not(intpriority_reg[9]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1367 = mux(_T_1365, _T_1366, intpriority_reg[9]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[9] <= _T_1367 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1368 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1369 = not(intpriority_reg[10]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1370 = mux(_T_1368, _T_1369, intpriority_reg[10]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[10] <= _T_1370 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1371 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1372 = not(intpriority_reg[11]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1373 = mux(_T_1371, _T_1372, intpriority_reg[11]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[11] <= _T_1373 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1374 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1375 = not(intpriority_reg[12]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1376 = mux(_T_1374, _T_1375, intpriority_reg[12]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[12] <= _T_1376 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1377 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1378 = not(intpriority_reg[13]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1379 = mux(_T_1377, _T_1378, intpriority_reg[13]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[13] <= _T_1379 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1380 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1381 = not(intpriority_reg[14]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1382 = mux(_T_1380, _T_1381, intpriority_reg[14]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[14] <= _T_1382 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1383 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1384 = not(intpriority_reg[15]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1385 = mux(_T_1383, _T_1384, intpriority_reg[15]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[15] <= _T_1385 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1386 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1387 = not(intpriority_reg[16]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1388 = mux(_T_1386, _T_1387, intpriority_reg[16]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[16] <= _T_1388 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1389 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1390 = not(intpriority_reg[17]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1391 = mux(_T_1389, _T_1390, intpriority_reg[17]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[17] <= _T_1391 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1392 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1393 = not(intpriority_reg[18]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1394 = mux(_T_1392, _T_1393, intpriority_reg[18]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[18] <= _T_1394 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1395 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1396 = not(intpriority_reg[19]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1397 = mux(_T_1395, _T_1396, intpriority_reg[19]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[19] <= _T_1397 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1398 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1399 = not(intpriority_reg[20]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1400 = mux(_T_1398, _T_1399, intpriority_reg[20]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[20] <= _T_1400 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1401 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1402 = not(intpriority_reg[21]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1403 = mux(_T_1401, _T_1402, intpriority_reg[21]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[21] <= _T_1403 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1404 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1405 = not(intpriority_reg[22]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1406 = mux(_T_1404, _T_1405, intpriority_reg[22]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[22] <= _T_1406 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1407 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1408 = not(intpriority_reg[23]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1409 = mux(_T_1407, _T_1408, intpriority_reg[23]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[23] <= _T_1409 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1410 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1411 = not(intpriority_reg[24]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1412 = mux(_T_1410, _T_1411, intpriority_reg[24]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[24] <= _T_1412 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1413 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1414 = not(intpriority_reg[25]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1415 = mux(_T_1413, _T_1414, intpriority_reg[25]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[25] <= _T_1415 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1416 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1417 = not(intpriority_reg[26]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1418 = mux(_T_1416, _T_1417, intpriority_reg[26]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[26] <= _T_1418 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1419 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1420 = not(intpriority_reg[27]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1421 = mux(_T_1419, _T_1420, intpriority_reg[27]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[27] <= _T_1421 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1422 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1423 = not(intpriority_reg[28]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1424 = mux(_T_1422, _T_1423, intpriority_reg[28]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[28] <= _T_1424 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1425 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1426 = not(intpriority_reg[29]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1427 = mux(_T_1425, _T_1426, intpriority_reg[29]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[29] <= _T_1427 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1428 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1429 = not(intpriority_reg[30]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1430 = mux(_T_1428, _T_1429, intpriority_reg[30]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[30] <= _T_1430 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1431 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81]
|
|
node _T_1432 = not(intpriority_reg[31]) @[el2_pic_ctl.scala 174:89]
|
|
node _T_1433 = mux(_T_1431, _T_1432, intpriority_reg[31]) @[el2_pic_ctl.scala 174:70]
|
|
intpriority_reg_inv[31] <= _T_1433 @[el2_pic_ctl.scala 174:64]
|
|
node _T_1434 = and(UInt<1>("h00"), intenable_reg[0]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1435 = bits(_T_1434, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1436 = mux(_T_1435, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1437 = and(_T_1436, intpriority_reg_inv[0]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[0] <= _T_1437 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1438 = and(extintsrc_req_gw_1, intenable_reg[1]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1439 = bits(_T_1438, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1440 = mux(_T_1439, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1441 = and(_T_1440, intpriority_reg_inv[1]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[1] <= _T_1441 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1442 = and(extintsrc_req_gw_2, intenable_reg[2]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1443 = bits(_T_1442, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1444 = mux(_T_1443, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1445 = and(_T_1444, intpriority_reg_inv[2]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[2] <= _T_1445 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1446 = and(extintsrc_req_gw_3, intenable_reg[3]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1447 = bits(_T_1446, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1448 = mux(_T_1447, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1449 = and(_T_1448, intpriority_reg_inv[3]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[3] <= _T_1449 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1450 = and(extintsrc_req_gw_4, intenable_reg[4]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1451 = bits(_T_1450, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1452 = mux(_T_1451, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1453 = and(_T_1452, intpriority_reg_inv[4]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[4] <= _T_1453 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1454 = and(extintsrc_req_gw_5, intenable_reg[5]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1455 = bits(_T_1454, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1456 = mux(_T_1455, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1457 = and(_T_1456, intpriority_reg_inv[5]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[5] <= _T_1457 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1458 = and(extintsrc_req_gw_6, intenable_reg[6]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1459 = bits(_T_1458, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1460 = mux(_T_1459, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1461 = and(_T_1460, intpriority_reg_inv[6]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[6] <= _T_1461 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1462 = and(extintsrc_req_gw_7, intenable_reg[7]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1463 = bits(_T_1462, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1464 = mux(_T_1463, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1465 = and(_T_1464, intpriority_reg_inv[7]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[7] <= _T_1465 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1466 = and(extintsrc_req_gw_8, intenable_reg[8]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1467 = bits(_T_1466, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1468 = mux(_T_1467, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1469 = and(_T_1468, intpriority_reg_inv[8]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[8] <= _T_1469 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1470 = and(extintsrc_req_gw_9, intenable_reg[9]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1471 = bits(_T_1470, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1472 = mux(_T_1471, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1473 = and(_T_1472, intpriority_reg_inv[9]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[9] <= _T_1473 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1474 = and(extintsrc_req_gw_10, intenable_reg[10]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1475 = bits(_T_1474, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1476 = mux(_T_1475, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1477 = and(_T_1476, intpriority_reg_inv[10]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[10] <= _T_1477 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1478 = and(extintsrc_req_gw_11, intenable_reg[11]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1479 = bits(_T_1478, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1480 = mux(_T_1479, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1481 = and(_T_1480, intpriority_reg_inv[11]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[11] <= _T_1481 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1482 = and(extintsrc_req_gw_12, intenable_reg[12]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1483 = bits(_T_1482, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1484 = mux(_T_1483, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1485 = and(_T_1484, intpriority_reg_inv[12]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[12] <= _T_1485 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1486 = and(extintsrc_req_gw_13, intenable_reg[13]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1487 = bits(_T_1486, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1488 = mux(_T_1487, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1489 = and(_T_1488, intpriority_reg_inv[13]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[13] <= _T_1489 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1490 = and(extintsrc_req_gw_14, intenable_reg[14]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1491 = bits(_T_1490, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1492 = mux(_T_1491, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1493 = and(_T_1492, intpriority_reg_inv[14]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[14] <= _T_1493 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1494 = and(extintsrc_req_gw_15, intenable_reg[15]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1495 = bits(_T_1494, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1496 = mux(_T_1495, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1497 = and(_T_1496, intpriority_reg_inv[15]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[15] <= _T_1497 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1498 = and(extintsrc_req_gw_16, intenable_reg[16]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1499 = bits(_T_1498, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1500 = mux(_T_1499, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1501 = and(_T_1500, intpriority_reg_inv[16]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[16] <= _T_1501 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1502 = and(extintsrc_req_gw_17, intenable_reg[17]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1503 = bits(_T_1502, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1504 = mux(_T_1503, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1505 = and(_T_1504, intpriority_reg_inv[17]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[17] <= _T_1505 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1506 = and(extintsrc_req_gw_18, intenable_reg[18]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1507 = bits(_T_1506, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1508 = mux(_T_1507, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1509 = and(_T_1508, intpriority_reg_inv[18]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[18] <= _T_1509 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1510 = and(extintsrc_req_gw_19, intenable_reg[19]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1511 = bits(_T_1510, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1512 = mux(_T_1511, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1513 = and(_T_1512, intpriority_reg_inv[19]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[19] <= _T_1513 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1514 = and(extintsrc_req_gw_20, intenable_reg[20]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1515 = bits(_T_1514, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1516 = mux(_T_1515, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1517 = and(_T_1516, intpriority_reg_inv[20]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[20] <= _T_1517 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1518 = and(extintsrc_req_gw_21, intenable_reg[21]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1519 = bits(_T_1518, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1520 = mux(_T_1519, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1521 = and(_T_1520, intpriority_reg_inv[21]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[21] <= _T_1521 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1522 = and(extintsrc_req_gw_22, intenable_reg[22]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1523 = bits(_T_1522, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1524 = mux(_T_1523, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1525 = and(_T_1524, intpriority_reg_inv[22]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[22] <= _T_1525 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1526 = and(extintsrc_req_gw_23, intenable_reg[23]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1527 = bits(_T_1526, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1528 = mux(_T_1527, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1529 = and(_T_1528, intpriority_reg_inv[23]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[23] <= _T_1529 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1530 = and(extintsrc_req_gw_24, intenable_reg[24]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1531 = bits(_T_1530, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1532 = mux(_T_1531, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1533 = and(_T_1532, intpriority_reg_inv[24]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[24] <= _T_1533 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1534 = and(extintsrc_req_gw_25, intenable_reg[25]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1535 = bits(_T_1534, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1536 = mux(_T_1535, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1537 = and(_T_1536, intpriority_reg_inv[25]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[25] <= _T_1537 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1538 = and(extintsrc_req_gw_26, intenable_reg[26]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1539 = bits(_T_1538, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1540 = mux(_T_1539, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1541 = and(_T_1540, intpriority_reg_inv[26]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[26] <= _T_1541 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1542 = and(extintsrc_req_gw_27, intenable_reg[27]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1543 = bits(_T_1542, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1544 = mux(_T_1543, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1545 = and(_T_1544, intpriority_reg_inv[27]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[27] <= _T_1545 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1546 = and(extintsrc_req_gw_28, intenable_reg[28]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1547 = bits(_T_1546, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1548 = mux(_T_1547, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1549 = and(_T_1548, intpriority_reg_inv[28]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[28] <= _T_1549 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1550 = and(extintsrc_req_gw_29, intenable_reg[29]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1551 = bits(_T_1550, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1552 = mux(_T_1551, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1553 = and(_T_1552, intpriority_reg_inv[29]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[29] <= _T_1553 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1554 = and(extintsrc_req_gw_30, intenable_reg[30]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1555 = bits(_T_1554, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1556 = mux(_T_1555, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1557 = and(_T_1556, intpriority_reg_inv[30]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[30] <= _T_1557 @[el2_pic_ctl.scala 175:63]
|
|
node _T_1558 = and(extintsrc_req_gw_31, intenable_reg[31]) @[el2_pic_ctl.scala 175:109]
|
|
node _T_1559 = bits(_T_1558, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1560 = mux(_T_1559, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1561 = and(_T_1560, intpriority_reg_inv[31]) @[el2_pic_ctl.scala 175:129]
|
|
intpend_w_prior_en[31] <= _T_1561 @[el2_pic_ctl.scala 175:63]
|
|
intpend_id[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[1] <= UInt<1>("h01") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[2] <= UInt<2>("h02") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[3] <= UInt<2>("h03") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[4] <= UInt<3>("h04") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[5] <= UInt<3>("h05") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[6] <= UInt<3>("h06") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[7] <= UInt<3>("h07") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[8] <= UInt<4>("h08") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[9] <= UInt<4>("h09") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[10] <= UInt<4>("h0a") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[11] <= UInt<4>("h0b") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[12] <= UInt<4>("h0c") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[13] <= UInt<4>("h0d") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[14] <= UInt<4>("h0e") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[15] <= UInt<4>("h0f") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[16] <= UInt<5>("h010") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[17] <= UInt<5>("h011") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[18] <= UInt<5>("h012") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[19] <= UInt<5>("h013") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[20] <= UInt<5>("h014") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[21] <= UInt<5>("h015") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[22] <= UInt<5>("h016") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[23] <= UInt<5>("h017") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[24] <= UInt<5>("h018") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[25] <= UInt<5>("h019") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[26] <= UInt<5>("h01a") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[27] <= UInt<5>("h01b") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[28] <= UInt<5>("h01c") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[29] <= UInt<5>("h01d") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[30] <= UInt<5>("h01e") @[el2_pic_ctl.scala 176:55]
|
|
intpend_id[31] <= UInt<5>("h01f") @[el2_pic_ctl.scala 176:55]
|
|
wire level_intpend_w_prior_en : UInt<4>[34][6] @[el2_pic_ctl.scala 227:40]
|
|
wire level_intpend_id : UInt<8>[34][6] @[el2_pic_ctl.scala 228:32]
|
|
level_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[0][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[0][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[1][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[1][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[2][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[2][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[3][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[3][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[4][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[4][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
level_intpend_w_prior_en[5][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38]
|
|
level_intpend_id[5][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30]
|
|
node _T_1562 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1563 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
level_intpend_w_prior_en[0][0] <= intpend_w_prior_en[0] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][1] <= intpend_w_prior_en[1] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][2] <= intpend_w_prior_en[2] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][3] <= intpend_w_prior_en[3] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][4] <= intpend_w_prior_en[4] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][5] <= intpend_w_prior_en[5] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][6] <= intpend_w_prior_en[6] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][7] <= intpend_w_prior_en[7] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][8] <= intpend_w_prior_en[8] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][9] <= intpend_w_prior_en[9] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][10] <= intpend_w_prior_en[10] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][11] <= intpend_w_prior_en[11] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][12] <= intpend_w_prior_en[12] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][13] <= intpend_w_prior_en[13] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][14] <= intpend_w_prior_en[14] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][15] <= intpend_w_prior_en[15] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][16] <= intpend_w_prior_en[16] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][17] <= intpend_w_prior_en[17] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][18] <= intpend_w_prior_en[18] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][19] <= intpend_w_prior_en[19] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][20] <= intpend_w_prior_en[20] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][21] <= intpend_w_prior_en[21] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][22] <= intpend_w_prior_en[22] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][23] <= intpend_w_prior_en[23] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][24] <= intpend_w_prior_en[24] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][25] <= intpend_w_prior_en[25] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][26] <= intpend_w_prior_en[26] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][27] <= intpend_w_prior_en[27] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][28] <= intpend_w_prior_en[28] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][29] <= intpend_w_prior_en[29] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][30] <= intpend_w_prior_en[30] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][31] <= intpend_w_prior_en[31] @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][32] <= _T_1562 @[el2_pic_ctl.scala 234:33]
|
|
level_intpend_w_prior_en[0][33] <= _T_1563 @[el2_pic_ctl.scala 234:33]
|
|
node _T_1564 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1565 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
level_intpend_id[0][0] <= intpend_id[0] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][1] <= intpend_id[1] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][2] <= intpend_id[2] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][3] <= intpend_id[3] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][4] <= intpend_id[4] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][5] <= intpend_id[5] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][6] <= intpend_id[6] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][7] <= intpend_id[7] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][8] <= intpend_id[8] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][9] <= intpend_id[9] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][10] <= intpend_id[10] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][11] <= intpend_id[11] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][12] <= intpend_id[12] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][13] <= intpend_id[13] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][14] <= intpend_id[14] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][15] <= intpend_id[15] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][16] <= intpend_id[16] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][17] <= intpend_id[17] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][18] <= intpend_id[18] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][19] <= intpend_id[19] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][20] <= intpend_id[20] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][21] <= intpend_id[21] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][22] <= intpend_id[22] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][23] <= intpend_id[23] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][24] <= intpend_id[24] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][25] <= intpend_id[25] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][26] <= intpend_id[26] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][27] <= intpend_id[27] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][28] <= intpend_id[28] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][29] <= intpend_id[29] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][30] <= intpend_id[30] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][31] <= intpend_id[31] @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][32] <= _T_1564 @[el2_pic_ctl.scala 235:33]
|
|
level_intpend_id[0][33] <= _T_1565 @[el2_pic_ctl.scala 235:33]
|
|
wire out_id : UInt<8>
|
|
out_id <= UInt<1>("h00")
|
|
wire out_priority : UInt<4>
|
|
out_priority <= UInt<1>("h00")
|
|
node _T_1566 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1567 = mux(_T_1566, level_intpend_id[0][1], level_intpend_id[0][0]) @[el2_pic_ctl.scala 38:18]
|
|
out_id <= _T_1567 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1568 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1569 = mux(_T_1568, level_intpend_w_prior_en[0][1], level_intpend_w_prior_en[0][0]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority <= _T_1569 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][0] <= out_id @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][0] <= out_priority @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_1 : UInt<8>
|
|
out_id_1 <= UInt<1>("h00")
|
|
wire out_priority_1 : UInt<4>
|
|
out_priority_1 <= UInt<1>("h00")
|
|
node _T_1570 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1571 = mux(_T_1570, level_intpend_id[0][3], level_intpend_id[0][2]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_1 <= _T_1571 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1572 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1573 = mux(_T_1572, level_intpend_w_prior_en[0][3], level_intpend_w_prior_en[0][2]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_1 <= _T_1573 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][1] <= out_id_1 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][1] <= out_priority_1 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_2 : UInt<8>
|
|
out_id_2 <= UInt<1>("h00")
|
|
wire out_priority_2 : UInt<4>
|
|
out_priority_2 <= UInt<1>("h00")
|
|
node _T_1574 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1575 = mux(_T_1574, level_intpend_id[0][5], level_intpend_id[0][4]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_2 <= _T_1575 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1576 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1577 = mux(_T_1576, level_intpend_w_prior_en[0][5], level_intpend_w_prior_en[0][4]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_2 <= _T_1577 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][2] <= out_id_2 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][2] <= out_priority_2 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_3 : UInt<8>
|
|
out_id_3 <= UInt<1>("h00")
|
|
wire out_priority_3 : UInt<4>
|
|
out_priority_3 <= UInt<1>("h00")
|
|
node _T_1578 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1579 = mux(_T_1578, level_intpend_id[0][7], level_intpend_id[0][6]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_3 <= _T_1579 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1580 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1581 = mux(_T_1580, level_intpend_w_prior_en[0][7], level_intpend_w_prior_en[0][6]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_3 <= _T_1581 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][3] <= out_id_3 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][3] <= out_priority_3 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_4 : UInt<8>
|
|
out_id_4 <= UInt<1>("h00")
|
|
wire out_priority_4 : UInt<4>
|
|
out_priority_4 <= UInt<1>("h00")
|
|
node _T_1582 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1583 = mux(_T_1582, level_intpend_id[0][9], level_intpend_id[0][8]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_4 <= _T_1583 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1584 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1585 = mux(_T_1584, level_intpend_w_prior_en[0][9], level_intpend_w_prior_en[0][8]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_4 <= _T_1585 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][4] <= out_id_4 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][4] <= out_priority_4 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_5 : UInt<8>
|
|
out_id_5 <= UInt<1>("h00")
|
|
wire out_priority_5 : UInt<4>
|
|
out_priority_5 <= UInt<1>("h00")
|
|
node _T_1586 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1587 = mux(_T_1586, level_intpend_id[0][11], level_intpend_id[0][10]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_5 <= _T_1587 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1588 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1589 = mux(_T_1588, level_intpend_w_prior_en[0][11], level_intpend_w_prior_en[0][10]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_5 <= _T_1589 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][5] <= out_id_5 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][5] <= out_priority_5 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_6 : UInt<8>
|
|
out_id_6 <= UInt<1>("h00")
|
|
wire out_priority_6 : UInt<4>
|
|
out_priority_6 <= UInt<1>("h00")
|
|
node _T_1590 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1591 = mux(_T_1590, level_intpend_id[0][13], level_intpend_id[0][12]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_6 <= _T_1591 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1592 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1593 = mux(_T_1592, level_intpend_w_prior_en[0][13], level_intpend_w_prior_en[0][12]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_6 <= _T_1593 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][6] <= out_id_6 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][6] <= out_priority_6 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_7 : UInt<8>
|
|
out_id_7 <= UInt<1>("h00")
|
|
wire out_priority_7 : UInt<4>
|
|
out_priority_7 <= UInt<1>("h00")
|
|
node _T_1594 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1595 = mux(_T_1594, level_intpend_id[0][15], level_intpend_id[0][14]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_7 <= _T_1595 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1596 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1597 = mux(_T_1596, level_intpend_w_prior_en[0][15], level_intpend_w_prior_en[0][14]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_7 <= _T_1597 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][7] <= out_id_7 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][7] <= out_priority_7 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_8 : UInt<8>
|
|
out_id_8 <= UInt<1>("h00")
|
|
wire out_priority_8 : UInt<4>
|
|
out_priority_8 <= UInt<1>("h00")
|
|
node _T_1598 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1599 = mux(_T_1598, level_intpend_id[0][17], level_intpend_id[0][16]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_8 <= _T_1599 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1600 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1601 = mux(_T_1600, level_intpend_w_prior_en[0][17], level_intpend_w_prior_en[0][16]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_8 <= _T_1601 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][8] <= out_id_8 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][8] <= out_priority_8 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_9 : UInt<8>
|
|
out_id_9 <= UInt<1>("h00")
|
|
wire out_priority_9 : UInt<4>
|
|
out_priority_9 <= UInt<1>("h00")
|
|
node _T_1602 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1603 = mux(_T_1602, level_intpend_id[0][19], level_intpend_id[0][18]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_9 <= _T_1603 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1604 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1605 = mux(_T_1604, level_intpend_w_prior_en[0][19], level_intpend_w_prior_en[0][18]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_9 <= _T_1605 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][9] <= out_id_9 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][9] <= out_priority_9 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_10 : UInt<8>
|
|
out_id_10 <= UInt<1>("h00")
|
|
wire out_priority_10 : UInt<4>
|
|
out_priority_10 <= UInt<1>("h00")
|
|
node _T_1606 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1607 = mux(_T_1606, level_intpend_id[0][21], level_intpend_id[0][20]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_10 <= _T_1607 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1608 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1609 = mux(_T_1608, level_intpend_w_prior_en[0][21], level_intpend_w_prior_en[0][20]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_10 <= _T_1609 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][10] <= out_id_10 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][10] <= out_priority_10 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_11 : UInt<8>
|
|
out_id_11 <= UInt<1>("h00")
|
|
wire out_priority_11 : UInt<4>
|
|
out_priority_11 <= UInt<1>("h00")
|
|
node _T_1610 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1611 = mux(_T_1610, level_intpend_id[0][23], level_intpend_id[0][22]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_11 <= _T_1611 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1612 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1613 = mux(_T_1612, level_intpend_w_prior_en[0][23], level_intpend_w_prior_en[0][22]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_11 <= _T_1613 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][11] <= out_id_11 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][11] <= out_priority_11 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_12 : UInt<8>
|
|
out_id_12 <= UInt<1>("h00")
|
|
wire out_priority_12 : UInt<4>
|
|
out_priority_12 <= UInt<1>("h00")
|
|
node _T_1614 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1615 = mux(_T_1614, level_intpend_id[0][25], level_intpend_id[0][24]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_12 <= _T_1615 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1616 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1617 = mux(_T_1616, level_intpend_w_prior_en[0][25], level_intpend_w_prior_en[0][24]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_12 <= _T_1617 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][12] <= out_id_12 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][12] <= out_priority_12 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_13 : UInt<8>
|
|
out_id_13 <= UInt<1>("h00")
|
|
wire out_priority_13 : UInt<4>
|
|
out_priority_13 <= UInt<1>("h00")
|
|
node _T_1618 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1619 = mux(_T_1618, level_intpend_id[0][27], level_intpend_id[0][26]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_13 <= _T_1619 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1620 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1621 = mux(_T_1620, level_intpend_w_prior_en[0][27], level_intpend_w_prior_en[0][26]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_13 <= _T_1621 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][13] <= out_id_13 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][13] <= out_priority_13 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_14 : UInt<8>
|
|
out_id_14 <= UInt<1>("h00")
|
|
wire out_priority_14 : UInt<4>
|
|
out_priority_14 <= UInt<1>("h00")
|
|
node _T_1622 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1623 = mux(_T_1622, level_intpend_id[0][29], level_intpend_id[0][28]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_14 <= _T_1623 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1624 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1625 = mux(_T_1624, level_intpend_w_prior_en[0][29], level_intpend_w_prior_en[0][28]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_14 <= _T_1625 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][14] <= out_id_14 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][14] <= out_priority_14 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_15 : UInt<8>
|
|
out_id_15 <= UInt<1>("h00")
|
|
wire out_priority_15 : UInt<4>
|
|
out_priority_15 <= UInt<1>("h00")
|
|
node _T_1626 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1627 = mux(_T_1626, level_intpend_id[0][31], level_intpend_id[0][30]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_15 <= _T_1627 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1628 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1629 = mux(_T_1628, level_intpend_w_prior_en[0][31], level_intpend_w_prior_en[0][30]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_15 <= _T_1629 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][15] <= out_id_15 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][15] <= out_priority_15 @[el2_pic_ctl.scala 247:43]
|
|
level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46]
|
|
level_intpend_id[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46]
|
|
wire out_id_16 : UInt<8>
|
|
out_id_16 <= UInt<1>("h00")
|
|
wire out_priority_16 : UInt<4>
|
|
out_priority_16 <= UInt<1>("h00")
|
|
node _T_1630 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1631 = mux(_T_1630, level_intpend_id[0][33], level_intpend_id[0][32]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_16 <= _T_1631 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1632 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1633 = mux(_T_1632, level_intpend_w_prior_en[0][33], level_intpend_w_prior_en[0][32]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_16 <= _T_1633 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[1][16] <= out_id_16 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[1][16] <= out_priority_16 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_17 : UInt<8>
|
|
out_id_17 <= UInt<1>("h00")
|
|
wire out_priority_17 : UInt<4>
|
|
out_priority_17 <= UInt<1>("h00")
|
|
node _T_1634 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1635 = mux(_T_1634, level_intpend_id[1][1], level_intpend_id[1][0]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_17 <= _T_1635 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1636 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1637 = mux(_T_1636, level_intpend_w_prior_en[1][1], level_intpend_w_prior_en[1][0]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_17 <= _T_1637 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[2][0] <= out_id_17 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[2][0] <= out_priority_17 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_18 : UInt<8>
|
|
out_id_18 <= UInt<1>("h00")
|
|
wire out_priority_18 : UInt<4>
|
|
out_priority_18 <= UInt<1>("h00")
|
|
node _T_1638 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1639 = mux(_T_1638, level_intpend_id[1][3], level_intpend_id[1][2]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_18 <= _T_1639 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1640 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1641 = mux(_T_1640, level_intpend_w_prior_en[1][3], level_intpend_w_prior_en[1][2]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_18 <= _T_1641 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[2][1] <= out_id_18 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[2][1] <= out_priority_18 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_19 : UInt<8>
|
|
out_id_19 <= UInt<1>("h00")
|
|
wire out_priority_19 : UInt<4>
|
|
out_priority_19 <= UInt<1>("h00")
|
|
node _T_1642 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1643 = mux(_T_1642, level_intpend_id[1][5], level_intpend_id[1][4]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_19 <= _T_1643 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1644 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1645 = mux(_T_1644, level_intpend_w_prior_en[1][5], level_intpend_w_prior_en[1][4]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_19 <= _T_1645 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[2][2] <= out_id_19 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[2][2] <= out_priority_19 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_20 : UInt<8>
|
|
out_id_20 <= UInt<1>("h00")
|
|
wire out_priority_20 : UInt<4>
|
|
out_priority_20 <= UInt<1>("h00")
|
|
node _T_1646 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1647 = mux(_T_1646, level_intpend_id[1][7], level_intpend_id[1][6]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_20 <= _T_1647 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1648 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1649 = mux(_T_1648, level_intpend_w_prior_en[1][7], level_intpend_w_prior_en[1][6]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_20 <= _T_1649 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[2][3] <= out_id_20 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[2][3] <= out_priority_20 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_21 : UInt<8>
|
|
out_id_21 <= UInt<1>("h00")
|
|
wire out_priority_21 : UInt<4>
|
|
out_priority_21 <= UInt<1>("h00")
|
|
node _T_1650 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1651 = mux(_T_1650, level_intpend_id[1][9], level_intpend_id[1][8]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_21 <= _T_1651 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1652 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1653 = mux(_T_1652, level_intpend_w_prior_en[1][9], level_intpend_w_prior_en[1][8]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_21 <= _T_1653 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[2][4] <= out_id_21 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[2][4] <= out_priority_21 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_22 : UInt<8>
|
|
out_id_22 <= UInt<1>("h00")
|
|
wire out_priority_22 : UInt<4>
|
|
out_priority_22 <= UInt<1>("h00")
|
|
node _T_1654 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1655 = mux(_T_1654, level_intpend_id[1][11], level_intpend_id[1][10]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_22 <= _T_1655 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1656 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1657 = mux(_T_1656, level_intpend_w_prior_en[1][11], level_intpend_w_prior_en[1][10]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_22 <= _T_1657 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[2][5] <= out_id_22 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[2][5] <= out_priority_22 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_23 : UInt<8>
|
|
out_id_23 <= UInt<1>("h00")
|
|
wire out_priority_23 : UInt<4>
|
|
out_priority_23 <= UInt<1>("h00")
|
|
node _T_1658 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1659 = mux(_T_1658, level_intpend_id[1][13], level_intpend_id[1][12]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_23 <= _T_1659 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1660 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1661 = mux(_T_1660, level_intpend_w_prior_en[1][13], level_intpend_w_prior_en[1][12]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_23 <= _T_1661 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[2][6] <= out_id_23 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[2][6] <= out_priority_23 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_24 : UInt<8>
|
|
out_id_24 <= UInt<1>("h00")
|
|
wire out_priority_24 : UInt<4>
|
|
out_priority_24 <= UInt<1>("h00")
|
|
node _T_1662 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1663 = mux(_T_1662, level_intpend_id[1][15], level_intpend_id[1][14]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_24 <= _T_1663 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1664 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1665 = mux(_T_1664, level_intpend_w_prior_en[1][15], level_intpend_w_prior_en[1][14]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_24 <= _T_1665 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[2][7] <= out_id_24 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[2][7] <= out_priority_24 @[el2_pic_ctl.scala 247:43]
|
|
level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46]
|
|
level_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46]
|
|
wire out_id_25 : UInt<8>
|
|
out_id_25 <= UInt<1>("h00")
|
|
wire out_priority_25 : UInt<4>
|
|
out_priority_25 <= UInt<1>("h00")
|
|
node _T_1666 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1667 = mux(_T_1666, level_intpend_id[1][17], level_intpend_id[1][16]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_25 <= _T_1667 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1668 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1669 = mux(_T_1668, level_intpend_w_prior_en[1][17], level_intpend_w_prior_en[1][16]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_25 <= _T_1669 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[2][8] <= out_id_25 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[2][8] <= out_priority_25 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_26 : UInt<8>
|
|
out_id_26 <= UInt<1>("h00")
|
|
wire out_priority_26 : UInt<4>
|
|
out_priority_26 <= UInt<1>("h00")
|
|
node _T_1670 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1671 = mux(_T_1670, level_intpend_id[2][1], level_intpend_id[2][0]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_26 <= _T_1671 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1672 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1673 = mux(_T_1672, level_intpend_w_prior_en[2][1], level_intpend_w_prior_en[2][0]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_26 <= _T_1673 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[3][0] <= out_id_26 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[3][0] <= out_priority_26 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_27 : UInt<8>
|
|
out_id_27 <= UInt<1>("h00")
|
|
wire out_priority_27 : UInt<4>
|
|
out_priority_27 <= UInt<1>("h00")
|
|
node _T_1674 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1675 = mux(_T_1674, level_intpend_id[2][3], level_intpend_id[2][2]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_27 <= _T_1675 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1676 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1677 = mux(_T_1676, level_intpend_w_prior_en[2][3], level_intpend_w_prior_en[2][2]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_27 <= _T_1677 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[3][1] <= out_id_27 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[3][1] <= out_priority_27 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_28 : UInt<8>
|
|
out_id_28 <= UInt<1>("h00")
|
|
wire out_priority_28 : UInt<4>
|
|
out_priority_28 <= UInt<1>("h00")
|
|
node _T_1678 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1679 = mux(_T_1678, level_intpend_id[2][5], level_intpend_id[2][4]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_28 <= _T_1679 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1680 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1681 = mux(_T_1680, level_intpend_w_prior_en[2][5], level_intpend_w_prior_en[2][4]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_28 <= _T_1681 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[3][2] <= out_id_28 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[3][2] <= out_priority_28 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_29 : UInt<8>
|
|
out_id_29 <= UInt<1>("h00")
|
|
wire out_priority_29 : UInt<4>
|
|
out_priority_29 <= UInt<1>("h00")
|
|
node _T_1682 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1683 = mux(_T_1682, level_intpend_id[2][7], level_intpend_id[2][6]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_29 <= _T_1683 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1684 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1685 = mux(_T_1684, level_intpend_w_prior_en[2][7], level_intpend_w_prior_en[2][6]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_29 <= _T_1685 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[3][3] <= out_id_29 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[3][3] <= out_priority_29 @[el2_pic_ctl.scala 247:43]
|
|
level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46]
|
|
level_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46]
|
|
wire out_id_30 : UInt<8>
|
|
out_id_30 <= UInt<1>("h00")
|
|
wire out_priority_30 : UInt<4>
|
|
out_priority_30 <= UInt<1>("h00")
|
|
node _T_1686 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1687 = mux(_T_1686, level_intpend_id[2][9], level_intpend_id[2][8]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_30 <= _T_1687 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1688 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1689 = mux(_T_1688, level_intpend_w_prior_en[2][9], level_intpend_w_prior_en[2][8]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_30 <= _T_1689 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[3][4] <= out_id_30 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[3][4] <= out_priority_30 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_31 : UInt<8>
|
|
out_id_31 <= UInt<1>("h00")
|
|
wire out_priority_31 : UInt<4>
|
|
out_priority_31 <= UInt<1>("h00")
|
|
node _T_1690 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1691 = mux(_T_1690, level_intpend_id[3][1], level_intpend_id[3][0]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_31 <= _T_1691 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1692 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1693 = mux(_T_1692, level_intpend_w_prior_en[3][1], level_intpend_w_prior_en[3][0]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_31 <= _T_1693 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[4][0] <= out_id_31 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[4][0] <= out_priority_31 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_32 : UInt<8>
|
|
out_id_32 <= UInt<1>("h00")
|
|
wire out_priority_32 : UInt<4>
|
|
out_priority_32 <= UInt<1>("h00")
|
|
node _T_1694 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1695 = mux(_T_1694, level_intpend_id[3][3], level_intpend_id[3][2]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_32 <= _T_1695 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1696 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1697 = mux(_T_1696, level_intpend_w_prior_en[3][3], level_intpend_w_prior_en[3][2]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_32 <= _T_1697 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[4][1] <= out_id_32 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[4][1] <= out_priority_32 @[el2_pic_ctl.scala 247:43]
|
|
level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46]
|
|
level_intpend_id[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46]
|
|
wire out_id_33 : UInt<8>
|
|
out_id_33 <= UInt<1>("h00")
|
|
wire out_priority_33 : UInt<4>
|
|
out_priority_33 <= UInt<1>("h00")
|
|
node _T_1698 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1699 = mux(_T_1698, level_intpend_id[3][5], level_intpend_id[3][4]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_33 <= _T_1699 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1700 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1701 = mux(_T_1700, level_intpend_w_prior_en[3][5], level_intpend_w_prior_en[3][4]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_33 <= _T_1701 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[4][2] <= out_id_33 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[4][2] <= out_priority_33 @[el2_pic_ctl.scala 247:43]
|
|
wire out_id_34 : UInt<8>
|
|
out_id_34 <= UInt<1>("h00")
|
|
wire out_priority_34 : UInt<4>
|
|
out_priority_34 <= UInt<1>("h00")
|
|
node _T_1702 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1703 = mux(_T_1702, level_intpend_id[4][1], level_intpend_id[4][0]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_34 <= _T_1703 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1704 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1705 = mux(_T_1704, level_intpend_w_prior_en[4][1], level_intpend_w_prior_en[4][0]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_34 <= _T_1705 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[5][0] <= out_id_34 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[5][0] <= out_priority_34 @[el2_pic_ctl.scala 247:43]
|
|
level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46]
|
|
level_intpend_id[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46]
|
|
wire out_id_35 : UInt<8>
|
|
out_id_35 <= UInt<1>("h00")
|
|
wire out_priority_35 : UInt<4>
|
|
out_priority_35 <= UInt<1>("h00")
|
|
node _T_1706 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[el2_pic_ctl.scala 38:29]
|
|
node _T_1707 = mux(_T_1706, level_intpend_id[4][3], level_intpend_id[4][2]) @[el2_pic_ctl.scala 38:18]
|
|
out_id_35 <= _T_1707 @[el2_pic_ctl.scala 38:12]
|
|
node _T_1708 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[el2_pic_ctl.scala 39:35]
|
|
node _T_1709 = mux(_T_1708, level_intpend_w_prior_en[4][3], level_intpend_w_prior_en[4][2]) @[el2_pic_ctl.scala 39:24]
|
|
out_priority_35 <= _T_1709 @[el2_pic_ctl.scala 39:18]
|
|
level_intpend_id[5][1] <= out_id_35 @[el2_pic_ctl.scala 246:43]
|
|
level_intpend_w_prior_en[5][1] <= out_priority_35 @[el2_pic_ctl.scala 247:43]
|
|
claimid_in <= level_intpend_id[5][0] @[el2_pic_ctl.scala 250:29]
|
|
selected_int_priority <= level_intpend_w_prior_en[5][0] @[el2_pic_ctl.scala 251:29]
|
|
node config_reg_we = and(waddr_config_pic_match, picm_wren_ff) @[el2_pic_ctl.scala 263:47]
|
|
node config_reg_re = and(raddr_config_pic_match, picm_rden_ff) @[el2_pic_ctl.scala 264:47]
|
|
node config_reg_in = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 265:39]
|
|
node _T_1710 = bits(config_reg_we, 0, 0) @[el2_pic_ctl.scala 266:82]
|
|
reg _T_1711 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1710 : @[Reg.scala 28:19]
|
|
_T_1711 <= config_reg_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
config_reg <= _T_1711 @[el2_pic_ctl.scala 266:37]
|
|
intpriord <= config_reg @[el2_pic_ctl.scala 267:14]
|
|
node _T_1712 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 275:31]
|
|
node _T_1713 = not(selected_int_priority) @[el2_pic_ctl.scala 275:38]
|
|
node pl_in_q = mux(_T_1712, _T_1713, selected_int_priority) @[el2_pic_ctl.scala 275:20]
|
|
reg _T_1714 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 276:47]
|
|
_T_1714 <= claimid_in @[el2_pic_ctl.scala 276:47]
|
|
io.claimid <= _T_1714 @[el2_pic_ctl.scala 276:37]
|
|
reg _T_1715 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 277:42]
|
|
_T_1715 <= pl_in_q @[el2_pic_ctl.scala 277:42]
|
|
io.pl <= _T_1715 @[el2_pic_ctl.scala 277:32]
|
|
node _T_1716 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 278:33]
|
|
node _T_1717 = not(io.meipt) @[el2_pic_ctl.scala 278:40]
|
|
node meipt_inv = mux(_T_1716, _T_1717, io.meipt) @[el2_pic_ctl.scala 278:22]
|
|
node _T_1718 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 279:36]
|
|
node _T_1719 = not(io.meicurpl) @[el2_pic_ctl.scala 279:43]
|
|
node meicurpl_inv = mux(_T_1718, _T_1719, io.meicurpl) @[el2_pic_ctl.scala 279:25]
|
|
node _T_1720 = gt(selected_int_priority, meipt_inv) @[el2_pic_ctl.scala 280:47]
|
|
node _T_1721 = gt(selected_int_priority, meicurpl_inv) @[el2_pic_ctl.scala 280:86]
|
|
node mexintpend_in = and(_T_1720, _T_1721) @[el2_pic_ctl.scala 280:60]
|
|
reg _T_1722 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 281:50]
|
|
_T_1722 <= mexintpend_in @[el2_pic_ctl.scala 281:50]
|
|
io.mexintpend <= _T_1722 @[el2_pic_ctl.scala 281:17]
|
|
node _T_1723 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 282:30]
|
|
node maxint = mux(_T_1723, UInt<1>("h00"), UInt<4>("h0f")) @[el2_pic_ctl.scala 282:19]
|
|
node mhwakeup_in = eq(pl_in_q, maxint) @[el2_pic_ctl.scala 283:29]
|
|
reg _T_1724 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 284:48]
|
|
_T_1724 <= mhwakeup_in @[el2_pic_ctl.scala 284:48]
|
|
io.mhwakeup <= _T_1724 @[el2_pic_ctl.scala 284:15]
|
|
node intpend_reg_read = and(addr_intpend_base_match, picm_rden_ff) @[el2_pic_ctl.scala 290:60]
|
|
node intpriority_reg_read = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctl.scala 291:60]
|
|
node intenable_reg_read = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctl.scala 292:60]
|
|
node gw_config_reg_read = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctl.scala 293:60]
|
|
node _T_1725 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1726 = cat(extintsrc_req_gw_31, extintsrc_req_gw_30) @[Cat.scala 29:58]
|
|
node _T_1727 = cat(_T_1726, extintsrc_req_gw_29) @[Cat.scala 29:58]
|
|
node _T_1728 = cat(_T_1727, extintsrc_req_gw_28) @[Cat.scala 29:58]
|
|
node _T_1729 = cat(_T_1728, extintsrc_req_gw_27) @[Cat.scala 29:58]
|
|
node _T_1730 = cat(_T_1729, extintsrc_req_gw_26) @[Cat.scala 29:58]
|
|
node _T_1731 = cat(_T_1730, extintsrc_req_gw_25) @[Cat.scala 29:58]
|
|
node _T_1732 = cat(_T_1731, extintsrc_req_gw_24) @[Cat.scala 29:58]
|
|
node _T_1733 = cat(_T_1732, extintsrc_req_gw_23) @[Cat.scala 29:58]
|
|
node _T_1734 = cat(_T_1733, extintsrc_req_gw_22) @[Cat.scala 29:58]
|
|
node _T_1735 = cat(_T_1734, extintsrc_req_gw_21) @[Cat.scala 29:58]
|
|
node _T_1736 = cat(_T_1735, extintsrc_req_gw_20) @[Cat.scala 29:58]
|
|
node _T_1737 = cat(_T_1736, extintsrc_req_gw_19) @[Cat.scala 29:58]
|
|
node _T_1738 = cat(_T_1737, extintsrc_req_gw_18) @[Cat.scala 29:58]
|
|
node _T_1739 = cat(_T_1738, extintsrc_req_gw_17) @[Cat.scala 29:58]
|
|
node _T_1740 = cat(_T_1739, extintsrc_req_gw_16) @[Cat.scala 29:58]
|
|
node _T_1741 = cat(_T_1740, extintsrc_req_gw_15) @[Cat.scala 29:58]
|
|
node _T_1742 = cat(_T_1741, extintsrc_req_gw_14) @[Cat.scala 29:58]
|
|
node _T_1743 = cat(_T_1742, extintsrc_req_gw_13) @[Cat.scala 29:58]
|
|
node _T_1744 = cat(_T_1743, extintsrc_req_gw_12) @[Cat.scala 29:58]
|
|
node _T_1745 = cat(_T_1744, extintsrc_req_gw_11) @[Cat.scala 29:58]
|
|
node _T_1746 = cat(_T_1745, extintsrc_req_gw_10) @[Cat.scala 29:58]
|
|
node _T_1747 = cat(_T_1746, extintsrc_req_gw_9) @[Cat.scala 29:58]
|
|
node _T_1748 = cat(_T_1747, extintsrc_req_gw_8) @[Cat.scala 29:58]
|
|
node _T_1749 = cat(_T_1748, extintsrc_req_gw_7) @[Cat.scala 29:58]
|
|
node _T_1750 = cat(_T_1749, extintsrc_req_gw_6) @[Cat.scala 29:58]
|
|
node _T_1751 = cat(_T_1750, extintsrc_req_gw_5) @[Cat.scala 29:58]
|
|
node _T_1752 = cat(_T_1751, extintsrc_req_gw_4) @[Cat.scala 29:58]
|
|
node _T_1753 = cat(_T_1752, extintsrc_req_gw_3) @[Cat.scala 29:58]
|
|
node _T_1754 = cat(_T_1753, extintsrc_req_gw_2) @[Cat.scala 29:58]
|
|
node _T_1755 = cat(_T_1754, extintsrc_req_gw_1) @[Cat.scala 29:58]
|
|
node _T_1756 = cat(_T_1755, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_1757 = cat(_T_1725, _T_1756) @[Cat.scala 29:58]
|
|
intpend_reg_extended <= _T_1757 @[el2_pic_ctl.scala 295:25]
|
|
wire intpend_rd_part_out : UInt<32>[2] @[el2_pic_ctl.scala 297:33]
|
|
node _T_1758 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctl.scala 298:98]
|
|
node _T_1759 = and(intpend_reg_read, _T_1758) @[el2_pic_ctl.scala 298:83]
|
|
node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[el2_pic_ctl.scala 298:105]
|
|
node _T_1761 = bits(_T_1760, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1762 = mux(_T_1761, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1763 = bits(intpend_reg_extended, 31, 0) @[el2_pic_ctl.scala 298:141]
|
|
node _T_1764 = and(_T_1762, _T_1763) @[el2_pic_ctl.scala 298:119]
|
|
intpend_rd_part_out[0] <= _T_1764 @[el2_pic_ctl.scala 298:54]
|
|
node _T_1765 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctl.scala 298:98]
|
|
node _T_1766 = and(intpend_reg_read, _T_1765) @[el2_pic_ctl.scala 298:83]
|
|
node _T_1767 = eq(_T_1766, UInt<1>("h01")) @[el2_pic_ctl.scala 298:105]
|
|
node _T_1768 = bits(_T_1767, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1769 = mux(_T_1768, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1770 = bits(intpend_reg_extended, 63, 32) @[el2_pic_ctl.scala 298:141]
|
|
node _T_1771 = and(_T_1769, _T_1770) @[el2_pic_ctl.scala 298:119]
|
|
intpend_rd_part_out[1] <= _T_1771 @[el2_pic_ctl.scala 298:54]
|
|
node _T_1772 = or(intpend_rd_part_out[0], intpend_rd_part_out[1]) @[el2_pic_ctl.scala 299:89]
|
|
intpend_rd_out <= _T_1772 @[el2_pic_ctl.scala 299:26]
|
|
when UInt<1>("h00") : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[0] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1773 = bits(intenable_reg_re_1, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1773 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[1] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1774 = bits(intenable_reg_re_2, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1774 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[2] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1775 = bits(intenable_reg_re_3, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1775 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[3] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1776 = bits(intenable_reg_re_4, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1776 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[4] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1777 = bits(intenable_reg_re_5, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1777 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[5] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1778 = bits(intenable_reg_re_6, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1778 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[6] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1779 = bits(intenable_reg_re_7, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1779 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[7] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1780 = bits(intenable_reg_re_8, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1780 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[8] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1781 = bits(intenable_reg_re_9, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1781 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[9] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1782 = bits(intenable_reg_re_10, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1782 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[10] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1783 = bits(intenable_reg_re_11, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1783 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[11] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1784 = bits(intenable_reg_re_12, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1784 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[12] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1785 = bits(intenable_reg_re_13, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1785 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[13] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1786 = bits(intenable_reg_re_14, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1786 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[14] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1787 = bits(intenable_reg_re_15, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1787 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[15] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1788 = bits(intenable_reg_re_16, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1788 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[16] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1789 = bits(intenable_reg_re_17, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1789 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[17] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1790 = bits(intenable_reg_re_18, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1790 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[18] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1791 = bits(intenable_reg_re_19, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1791 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[19] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1792 = bits(intenable_reg_re_20, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1792 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[20] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1793 = bits(intenable_reg_re_21, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1793 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[21] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1794 = bits(intenable_reg_re_22, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1794 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[22] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1795 = bits(intenable_reg_re_23, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1795 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[23] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1796 = bits(intenable_reg_re_24, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1796 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[24] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1797 = bits(intenable_reg_re_25, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1797 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[25] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1798 = bits(intenable_reg_re_26, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1798 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[26] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1799 = bits(intenable_reg_re_27, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1799 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[27] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1800 = bits(intenable_reg_re_28, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1800 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[28] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1801 = bits(intenable_reg_re_29, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1801 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[29] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1802 = bits(intenable_reg_re_30, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1802 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[30] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1803 = bits(intenable_reg_re_31, 0, 0) @[el2_pic_ctl.scala 300:69]
|
|
when _T_1803 : @[el2_pic_ctl.scala 300:76]
|
|
intenable_rd_out <= intenable_reg[31] @[el2_pic_ctl.scala 300:95]
|
|
skip @[el2_pic_ctl.scala 300:76]
|
|
else : @[el2_pic_ctl.scala 300:126]
|
|
intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144]
|
|
skip @[el2_pic_ctl.scala 300:126]
|
|
node _T_1804 = bits(intpriority_reg_re_1, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1805 = bits(intpriority_reg_re_2, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1806 = bits(intpriority_reg_re_3, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1807 = bits(intpriority_reg_re_4, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1808 = bits(intpriority_reg_re_5, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1809 = bits(intpriority_reg_re_6, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1810 = bits(intpriority_reg_re_7, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1811 = bits(intpriority_reg_re_8, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1812 = bits(intpriority_reg_re_9, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1813 = bits(intpriority_reg_re_10, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1814 = bits(intpriority_reg_re_11, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1815 = bits(intpriority_reg_re_12, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1816 = bits(intpriority_reg_re_13, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1817 = bits(intpriority_reg_re_14, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1818 = bits(intpriority_reg_re_15, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1819 = bits(intpriority_reg_re_16, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1820 = bits(intpriority_reg_re_17, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1821 = bits(intpriority_reg_re_18, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1822 = bits(intpriority_reg_re_19, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1823 = bits(intpriority_reg_re_20, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1824 = bits(intpriority_reg_re_21, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1825 = bits(intpriority_reg_re_22, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1826 = bits(intpriority_reg_re_23, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1827 = bits(intpriority_reg_re_24, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1828 = bits(intpriority_reg_re_25, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1829 = bits(intpriority_reg_re_26, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1830 = bits(intpriority_reg_re_27, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1831 = bits(intpriority_reg_re_28, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1832 = bits(intpriority_reg_re_29, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1833 = bits(intpriority_reg_re_30, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1834 = bits(intpriority_reg_re_31, 0, 0) @[el2_pic_ctl.scala 302:102]
|
|
node _T_1835 = mux(_T_1834, intpriority_reg[31], UInt<1>("h00")) @[Mux.scala 98:16]
|
|
node _T_1836 = mux(_T_1833, intpriority_reg[30], _T_1835) @[Mux.scala 98:16]
|
|
node _T_1837 = mux(_T_1832, intpriority_reg[29], _T_1836) @[Mux.scala 98:16]
|
|
node _T_1838 = mux(_T_1831, intpriority_reg[28], _T_1837) @[Mux.scala 98:16]
|
|
node _T_1839 = mux(_T_1830, intpriority_reg[27], _T_1838) @[Mux.scala 98:16]
|
|
node _T_1840 = mux(_T_1829, intpriority_reg[26], _T_1839) @[Mux.scala 98:16]
|
|
node _T_1841 = mux(_T_1828, intpriority_reg[25], _T_1840) @[Mux.scala 98:16]
|
|
node _T_1842 = mux(_T_1827, intpriority_reg[24], _T_1841) @[Mux.scala 98:16]
|
|
node _T_1843 = mux(_T_1826, intpriority_reg[23], _T_1842) @[Mux.scala 98:16]
|
|
node _T_1844 = mux(_T_1825, intpriority_reg[22], _T_1843) @[Mux.scala 98:16]
|
|
node _T_1845 = mux(_T_1824, intpriority_reg[21], _T_1844) @[Mux.scala 98:16]
|
|
node _T_1846 = mux(_T_1823, intpriority_reg[20], _T_1845) @[Mux.scala 98:16]
|
|
node _T_1847 = mux(_T_1822, intpriority_reg[19], _T_1846) @[Mux.scala 98:16]
|
|
node _T_1848 = mux(_T_1821, intpriority_reg[18], _T_1847) @[Mux.scala 98:16]
|
|
node _T_1849 = mux(_T_1820, intpriority_reg[17], _T_1848) @[Mux.scala 98:16]
|
|
node _T_1850 = mux(_T_1819, intpriority_reg[16], _T_1849) @[Mux.scala 98:16]
|
|
node _T_1851 = mux(_T_1818, intpriority_reg[15], _T_1850) @[Mux.scala 98:16]
|
|
node _T_1852 = mux(_T_1817, intpriority_reg[14], _T_1851) @[Mux.scala 98:16]
|
|
node _T_1853 = mux(_T_1816, intpriority_reg[13], _T_1852) @[Mux.scala 98:16]
|
|
node _T_1854 = mux(_T_1815, intpriority_reg[12], _T_1853) @[Mux.scala 98:16]
|
|
node _T_1855 = mux(_T_1814, intpriority_reg[11], _T_1854) @[Mux.scala 98:16]
|
|
node _T_1856 = mux(_T_1813, intpriority_reg[10], _T_1855) @[Mux.scala 98:16]
|
|
node _T_1857 = mux(_T_1812, intpriority_reg[9], _T_1856) @[Mux.scala 98:16]
|
|
node _T_1858 = mux(_T_1811, intpriority_reg[8], _T_1857) @[Mux.scala 98:16]
|
|
node _T_1859 = mux(_T_1810, intpriority_reg[7], _T_1858) @[Mux.scala 98:16]
|
|
node _T_1860 = mux(_T_1809, intpriority_reg[6], _T_1859) @[Mux.scala 98:16]
|
|
node _T_1861 = mux(_T_1808, intpriority_reg[5], _T_1860) @[Mux.scala 98:16]
|
|
node _T_1862 = mux(_T_1807, intpriority_reg[4], _T_1861) @[Mux.scala 98:16]
|
|
node _T_1863 = mux(_T_1806, intpriority_reg[3], _T_1862) @[Mux.scala 98:16]
|
|
node _T_1864 = mux(_T_1805, intpriority_reg[2], _T_1863) @[Mux.scala 98:16]
|
|
node _T_1865 = mux(_T_1804, intpriority_reg[1], _T_1864) @[Mux.scala 98:16]
|
|
node intpriority_rd_out = mux(UInt<1>("h00"), intpriority_reg[0], _T_1865) @[Mux.scala 98:16]
|
|
node _T_1866 = bits(gw_config_reg_re_1, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1867 = bits(gw_config_reg_re_2, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1868 = bits(gw_config_reg_re_3, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1869 = bits(gw_config_reg_re_4, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1870 = bits(gw_config_reg_re_5, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1871 = bits(gw_config_reg_re_6, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1872 = bits(gw_config_reg_re_7, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1873 = bits(gw_config_reg_re_8, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1874 = bits(gw_config_reg_re_9, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1875 = bits(gw_config_reg_re_10, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1876 = bits(gw_config_reg_re_11, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1877 = bits(gw_config_reg_re_12, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1878 = bits(gw_config_reg_re_13, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1879 = bits(gw_config_reg_re_14, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1880 = bits(gw_config_reg_re_15, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1881 = bits(gw_config_reg_re_16, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1882 = bits(gw_config_reg_re_17, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1883 = bits(gw_config_reg_re_18, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1884 = bits(gw_config_reg_re_19, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1885 = bits(gw_config_reg_re_20, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1886 = bits(gw_config_reg_re_21, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1887 = bits(gw_config_reg_re_22, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1888 = bits(gw_config_reg_re_23, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1889 = bits(gw_config_reg_re_24, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1890 = bits(gw_config_reg_re_25, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1891 = bits(gw_config_reg_re_26, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1892 = bits(gw_config_reg_re_27, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1893 = bits(gw_config_reg_re_28, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1894 = bits(gw_config_reg_re_29, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1895 = bits(gw_config_reg_re_30, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1896 = bits(gw_config_reg_re_31, 0, 0) @[el2_pic_ctl.scala 303:100]
|
|
node _T_1897 = mux(_T_1896, gw_config_reg[31], UInt<1>("h00")) @[Mux.scala 98:16]
|
|
node _T_1898 = mux(_T_1895, gw_config_reg[30], _T_1897) @[Mux.scala 98:16]
|
|
node _T_1899 = mux(_T_1894, gw_config_reg[29], _T_1898) @[Mux.scala 98:16]
|
|
node _T_1900 = mux(_T_1893, gw_config_reg[28], _T_1899) @[Mux.scala 98:16]
|
|
node _T_1901 = mux(_T_1892, gw_config_reg[27], _T_1900) @[Mux.scala 98:16]
|
|
node _T_1902 = mux(_T_1891, gw_config_reg[26], _T_1901) @[Mux.scala 98:16]
|
|
node _T_1903 = mux(_T_1890, gw_config_reg[25], _T_1902) @[Mux.scala 98:16]
|
|
node _T_1904 = mux(_T_1889, gw_config_reg[24], _T_1903) @[Mux.scala 98:16]
|
|
node _T_1905 = mux(_T_1888, gw_config_reg[23], _T_1904) @[Mux.scala 98:16]
|
|
node _T_1906 = mux(_T_1887, gw_config_reg[22], _T_1905) @[Mux.scala 98:16]
|
|
node _T_1907 = mux(_T_1886, gw_config_reg[21], _T_1906) @[Mux.scala 98:16]
|
|
node _T_1908 = mux(_T_1885, gw_config_reg[20], _T_1907) @[Mux.scala 98:16]
|
|
node _T_1909 = mux(_T_1884, gw_config_reg[19], _T_1908) @[Mux.scala 98:16]
|
|
node _T_1910 = mux(_T_1883, gw_config_reg[18], _T_1909) @[Mux.scala 98:16]
|
|
node _T_1911 = mux(_T_1882, gw_config_reg[17], _T_1910) @[Mux.scala 98:16]
|
|
node _T_1912 = mux(_T_1881, gw_config_reg[16], _T_1911) @[Mux.scala 98:16]
|
|
node _T_1913 = mux(_T_1880, gw_config_reg[15], _T_1912) @[Mux.scala 98:16]
|
|
node _T_1914 = mux(_T_1879, gw_config_reg[14], _T_1913) @[Mux.scala 98:16]
|
|
node _T_1915 = mux(_T_1878, gw_config_reg[13], _T_1914) @[Mux.scala 98:16]
|
|
node _T_1916 = mux(_T_1877, gw_config_reg[12], _T_1915) @[Mux.scala 98:16]
|
|
node _T_1917 = mux(_T_1876, gw_config_reg[11], _T_1916) @[Mux.scala 98:16]
|
|
node _T_1918 = mux(_T_1875, gw_config_reg[10], _T_1917) @[Mux.scala 98:16]
|
|
node _T_1919 = mux(_T_1874, gw_config_reg[9], _T_1918) @[Mux.scala 98:16]
|
|
node _T_1920 = mux(_T_1873, gw_config_reg[8], _T_1919) @[Mux.scala 98:16]
|
|
node _T_1921 = mux(_T_1872, gw_config_reg[7], _T_1920) @[Mux.scala 98:16]
|
|
node _T_1922 = mux(_T_1871, gw_config_reg[6], _T_1921) @[Mux.scala 98:16]
|
|
node _T_1923 = mux(_T_1870, gw_config_reg[5], _T_1922) @[Mux.scala 98:16]
|
|
node _T_1924 = mux(_T_1869, gw_config_reg[4], _T_1923) @[Mux.scala 98:16]
|
|
node _T_1925 = mux(_T_1868, gw_config_reg[3], _T_1924) @[Mux.scala 98:16]
|
|
node _T_1926 = mux(_T_1867, gw_config_reg[2], _T_1925) @[Mux.scala 98:16]
|
|
node _T_1927 = mux(_T_1866, gw_config_reg[1], _T_1926) @[Mux.scala 98:16]
|
|
node gw_config_rd_out = mux(UInt<1>("h00"), gw_config_reg[0], _T_1927) @[Mux.scala 98:16]
|
|
wire picm_rd_data_in : UInt<32>
|
|
picm_rd_data_in <= UInt<1>("h00")
|
|
node _T_1928 = bits(intpend_reg_read, 0, 0) @[el2_pic_ctl.scala 308:22]
|
|
node _T_1929 = bits(intpriority_reg_read, 0, 0) @[el2_pic_ctl.scala 309:26]
|
|
node _T_1930 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1931 = cat(_T_1930, intpriority_rd_out) @[Cat.scala 29:58]
|
|
node _T_1932 = bits(intenable_reg_read, 0, 0) @[el2_pic_ctl.scala 310:24]
|
|
node _T_1933 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1934 = cat(_T_1933, intenable_rd_out) @[Cat.scala 29:58]
|
|
node _T_1935 = bits(gw_config_reg_read, 0, 0) @[el2_pic_ctl.scala 311:24]
|
|
node _T_1936 = mux(UInt<1>("h00"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1937 = cat(_T_1936, gw_config_rd_out) @[Cat.scala 29:58]
|
|
node _T_1938 = bits(config_reg_re, 0, 0) @[el2_pic_ctl.scala 312:19]
|
|
node _T_1939 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1940 = cat(_T_1939, config_reg) @[Cat.scala 29:58]
|
|
node _T_1941 = bits(mask, 3, 3) @[el2_pic_ctl.scala 313:25]
|
|
node _T_1942 = and(picm_mken_ff, _T_1941) @[el2_pic_ctl.scala 313:19]
|
|
node _T_1943 = bits(_T_1942, 0, 0) @[el2_pic_ctl.scala 313:30]
|
|
node _T_1944 = mux(UInt<1>("h00"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1945 = cat(_T_1944, UInt<2>("h03")) @[Cat.scala 29:58]
|
|
node _T_1946 = bits(mask, 2, 2) @[el2_pic_ctl.scala 314:25]
|
|
node _T_1947 = and(picm_mken_ff, _T_1946) @[el2_pic_ctl.scala 314:19]
|
|
node _T_1948 = bits(_T_1947, 0, 0) @[el2_pic_ctl.scala 314:30]
|
|
node _T_1949 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1950 = cat(_T_1949, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_1951 = bits(mask, 1, 1) @[el2_pic_ctl.scala 315:25]
|
|
node _T_1952 = and(picm_mken_ff, _T_1951) @[el2_pic_ctl.scala 315:19]
|
|
node _T_1953 = bits(_T_1952, 0, 0) @[el2_pic_ctl.scala 315:30]
|
|
node _T_1954 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1955 = cat(_T_1954, UInt<4>("h0f")) @[Cat.scala 29:58]
|
|
node _T_1956 = bits(mask, 0, 0) @[el2_pic_ctl.scala 316:25]
|
|
node _T_1957 = and(picm_mken_ff, _T_1956) @[el2_pic_ctl.scala 316:19]
|
|
node _T_1958 = bits(_T_1957, 0, 0) @[el2_pic_ctl.scala 316:30]
|
|
node _T_1959 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1960 = mux(_T_1928, intpend_rd_out, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1961 = mux(_T_1929, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1962 = mux(_T_1932, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1963 = mux(_T_1935, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1964 = mux(_T_1938, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1965 = mux(_T_1943, _T_1945, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1966 = mux(_T_1948, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1967 = mux(_T_1953, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1968 = mux(_T_1958, _T_1959, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1969 = or(_T_1960, _T_1961) @[Mux.scala 27:72]
|
|
node _T_1970 = or(_T_1969, _T_1962) @[Mux.scala 27:72]
|
|
node _T_1971 = or(_T_1970, _T_1963) @[Mux.scala 27:72]
|
|
node _T_1972 = or(_T_1971, _T_1964) @[Mux.scala 27:72]
|
|
node _T_1973 = or(_T_1972, _T_1965) @[Mux.scala 27:72]
|
|
node _T_1974 = or(_T_1973, _T_1966) @[Mux.scala 27:72]
|
|
node _T_1975 = or(_T_1974, _T_1967) @[Mux.scala 27:72]
|
|
node _T_1976 = or(_T_1975, _T_1968) @[Mux.scala 27:72]
|
|
wire _T_1977 : UInt<32> @[Mux.scala 27:72]
|
|
_T_1977 <= _T_1976 @[Mux.scala 27:72]
|
|
picm_rd_data_in <= _T_1977 @[el2_pic_ctl.scala 307:19]
|
|
node _T_1978 = bits(picm_bypass_ff, 0, 0) @[el2_pic_ctl.scala 319:41]
|
|
node _T_1979 = mux(_T_1978, picm_wr_data_ff, picm_rd_data_in) @[el2_pic_ctl.scala 319:25]
|
|
io.picm_rd_data <= _T_1979 @[el2_pic_ctl.scala 319:19]
|
|
node address = bits(picm_raddr_ff, 14, 0) @[el2_pic_ctl.scala 320:30]
|
|
mask <= UInt<4>("h01") @[el2_pic_ctl.scala 322:8]
|
|
node _T_1980 = eq(UInt<15>("h03000"), address) @[Conditional.scala 37:30]
|
|
when _T_1980 : @[Conditional.scala 40:58]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 324:44]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1981 = eq(UInt<15>("h04004"), address) @[Conditional.scala 37:30]
|
|
when _T_1981 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 325:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1982 = eq(UInt<15>("h04008"), address) @[Conditional.scala 37:30]
|
|
when _T_1982 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 326:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1983 = eq(UInt<15>("h0400c"), address) @[Conditional.scala 37:30]
|
|
when _T_1983 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 327:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1984 = eq(UInt<15>("h04010"), address) @[Conditional.scala 37:30]
|
|
when _T_1984 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 328:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1985 = eq(UInt<15>("h04014"), address) @[Conditional.scala 37:30]
|
|
when _T_1985 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 329:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1986 = eq(UInt<15>("h04018"), address) @[Conditional.scala 37:30]
|
|
when _T_1986 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 330:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1987 = eq(UInt<15>("h0401c"), address) @[Conditional.scala 37:30]
|
|
when _T_1987 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 331:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1988 = eq(UInt<15>("h04020"), address) @[Conditional.scala 37:30]
|
|
when _T_1988 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 332:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1989 = eq(UInt<15>("h04024"), address) @[Conditional.scala 37:30]
|
|
when _T_1989 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 333:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1990 = eq(UInt<15>("h04028"), address) @[Conditional.scala 37:30]
|
|
when _T_1990 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 334:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1991 = eq(UInt<15>("h0402c"), address) @[Conditional.scala 37:30]
|
|
when _T_1991 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 335:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1992 = eq(UInt<15>("h04030"), address) @[Conditional.scala 37:30]
|
|
when _T_1992 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 336:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1993 = eq(UInt<15>("h04034"), address) @[Conditional.scala 37:30]
|
|
when _T_1993 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 337:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1994 = eq(UInt<15>("h04038"), address) @[Conditional.scala 37:30]
|
|
when _T_1994 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 338:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1995 = eq(UInt<15>("h0403c"), address) @[Conditional.scala 37:30]
|
|
when _T_1995 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 339:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1996 = eq(UInt<15>("h04040"), address) @[Conditional.scala 37:30]
|
|
when _T_1996 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 340:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1997 = eq(UInt<15>("h04044"), address) @[Conditional.scala 37:30]
|
|
when _T_1997 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 341:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1998 = eq(UInt<15>("h04048"), address) @[Conditional.scala 37:30]
|
|
when _T_1998 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 342:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_1999 = eq(UInt<15>("h0404c"), address) @[Conditional.scala 37:30]
|
|
when _T_1999 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 343:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2000 = eq(UInt<15>("h04050"), address) @[Conditional.scala 37:30]
|
|
when _T_2000 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 344:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2001 = eq(UInt<15>("h04054"), address) @[Conditional.scala 37:30]
|
|
when _T_2001 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 345:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2002 = eq(UInt<15>("h04058"), address) @[Conditional.scala 37:30]
|
|
when _T_2002 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 346:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2003 = eq(UInt<15>("h0405c"), address) @[Conditional.scala 37:30]
|
|
when _T_2003 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 347:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2004 = eq(UInt<15>("h04060"), address) @[Conditional.scala 37:30]
|
|
when _T_2004 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 348:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2005 = eq(UInt<15>("h04064"), address) @[Conditional.scala 37:30]
|
|
when _T_2005 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 349:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2006 = eq(UInt<15>("h04068"), address) @[Conditional.scala 37:30]
|
|
when _T_2006 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 350:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2007 = eq(UInt<15>("h0406c"), address) @[Conditional.scala 37:30]
|
|
when _T_2007 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 351:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2008 = eq(UInt<15>("h04070"), address) @[Conditional.scala 37:30]
|
|
when _T_2008 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 352:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2009 = eq(UInt<15>("h04074"), address) @[Conditional.scala 37:30]
|
|
when _T_2009 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 353:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2010 = eq(UInt<15>("h04078"), address) @[Conditional.scala 37:30]
|
|
when _T_2010 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 354:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2011 = eq(UInt<15>("h0407c"), address) @[Conditional.scala 37:30]
|
|
when _T_2011 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h08") @[el2_pic_ctl.scala 355:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2012 = eq(UInt<15>("h02004"), address) @[Conditional.scala 37:30]
|
|
when _T_2012 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 356:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2013 = eq(UInt<15>("h02008"), address) @[Conditional.scala 37:30]
|
|
when _T_2013 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 357:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2014 = eq(UInt<15>("h0200c"), address) @[Conditional.scala 37:30]
|
|
when _T_2014 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 358:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2015 = eq(UInt<15>("h02010"), address) @[Conditional.scala 37:30]
|
|
when _T_2015 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 359:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2016 = eq(UInt<15>("h02014"), address) @[Conditional.scala 37:30]
|
|
when _T_2016 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 360:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2017 = eq(UInt<15>("h02018"), address) @[Conditional.scala 37:30]
|
|
when _T_2017 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 361:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2018 = eq(UInt<15>("h0201c"), address) @[Conditional.scala 37:30]
|
|
when _T_2018 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 362:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2019 = eq(UInt<15>("h02020"), address) @[Conditional.scala 37:30]
|
|
when _T_2019 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 363:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2020 = eq(UInt<15>("h02024"), address) @[Conditional.scala 37:30]
|
|
when _T_2020 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 364:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2021 = eq(UInt<15>("h02028"), address) @[Conditional.scala 37:30]
|
|
when _T_2021 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 365:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2022 = eq(UInt<15>("h0202c"), address) @[Conditional.scala 37:30]
|
|
when _T_2022 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 366:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2023 = eq(UInt<15>("h02030"), address) @[Conditional.scala 37:30]
|
|
when _T_2023 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 367:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2024 = eq(UInt<15>("h02034"), address) @[Conditional.scala 37:30]
|
|
when _T_2024 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 368:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2025 = eq(UInt<15>("h02038"), address) @[Conditional.scala 37:30]
|
|
when _T_2025 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 369:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2026 = eq(UInt<15>("h0203c"), address) @[Conditional.scala 37:30]
|
|
when _T_2026 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 370:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2027 = eq(UInt<15>("h02040"), address) @[Conditional.scala 37:30]
|
|
when _T_2027 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 371:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2028 = eq(UInt<15>("h02044"), address) @[Conditional.scala 37:30]
|
|
when _T_2028 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 372:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2029 = eq(UInt<15>("h02048"), address) @[Conditional.scala 37:30]
|
|
when _T_2029 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 373:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2030 = eq(UInt<15>("h0204c"), address) @[Conditional.scala 37:30]
|
|
when _T_2030 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 374:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2031 = eq(UInt<15>("h02050"), address) @[Conditional.scala 37:30]
|
|
when _T_2031 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 375:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2032 = eq(UInt<15>("h02054"), address) @[Conditional.scala 37:30]
|
|
when _T_2032 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 376:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2033 = eq(UInt<15>("h02058"), address) @[Conditional.scala 37:30]
|
|
when _T_2033 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 377:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2034 = eq(UInt<15>("h0205c"), address) @[Conditional.scala 37:30]
|
|
when _T_2034 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 378:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2035 = eq(UInt<15>("h02060"), address) @[Conditional.scala 37:30]
|
|
when _T_2035 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 379:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2036 = eq(UInt<15>("h02064"), address) @[Conditional.scala 37:30]
|
|
when _T_2036 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 380:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2037 = eq(UInt<15>("h02068"), address) @[Conditional.scala 37:30]
|
|
when _T_2037 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 381:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2038 = eq(UInt<15>("h0206c"), address) @[Conditional.scala 37:30]
|
|
when _T_2038 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 382:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2039 = eq(UInt<15>("h02070"), address) @[Conditional.scala 37:30]
|
|
when _T_2039 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 383:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2040 = eq(UInt<15>("h02074"), address) @[Conditional.scala 37:30]
|
|
when _T_2040 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 384:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2041 = eq(UInt<15>("h02078"), address) @[Conditional.scala 37:30]
|
|
when _T_2041 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 385:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2042 = eq(UInt<15>("h0207c"), address) @[Conditional.scala 37:30]
|
|
when _T_2042 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h04") @[el2_pic_ctl.scala 386:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2043 = eq(UInt<15>("h04"), address) @[Conditional.scala 37:30]
|
|
when _T_2043 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 387:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2044 = eq(UInt<15>("h08"), address) @[Conditional.scala 37:30]
|
|
when _T_2044 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 388:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2045 = eq(UInt<15>("h0c"), address) @[Conditional.scala 37:30]
|
|
when _T_2045 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 389:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2046 = eq(UInt<15>("h010"), address) @[Conditional.scala 37:30]
|
|
when _T_2046 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 390:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2047 = eq(UInt<15>("h014"), address) @[Conditional.scala 37:30]
|
|
when _T_2047 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 391:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2048 = eq(UInt<15>("h018"), address) @[Conditional.scala 37:30]
|
|
when _T_2048 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 392:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2049 = eq(UInt<15>("h01c"), address) @[Conditional.scala 37:30]
|
|
when _T_2049 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 393:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2050 = eq(UInt<15>("h020"), address) @[Conditional.scala 37:30]
|
|
when _T_2050 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 394:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2051 = eq(UInt<15>("h024"), address) @[Conditional.scala 37:30]
|
|
when _T_2051 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 395:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2052 = eq(UInt<15>("h028"), address) @[Conditional.scala 37:30]
|
|
when _T_2052 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 396:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2053 = eq(UInt<15>("h02c"), address) @[Conditional.scala 37:30]
|
|
when _T_2053 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 397:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2054 = eq(UInt<15>("h030"), address) @[Conditional.scala 37:30]
|
|
when _T_2054 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 398:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2055 = eq(UInt<15>("h034"), address) @[Conditional.scala 37:30]
|
|
when _T_2055 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 399:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2056 = eq(UInt<15>("h038"), address) @[Conditional.scala 37:30]
|
|
when _T_2056 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 400:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2057 = eq(UInt<15>("h03c"), address) @[Conditional.scala 37:30]
|
|
when _T_2057 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 401:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2058 = eq(UInt<15>("h040"), address) @[Conditional.scala 37:30]
|
|
when _T_2058 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 402:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2059 = eq(UInt<15>("h044"), address) @[Conditional.scala 37:30]
|
|
when _T_2059 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 403:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2060 = eq(UInt<15>("h048"), address) @[Conditional.scala 37:30]
|
|
when _T_2060 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 404:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2061 = eq(UInt<15>("h04c"), address) @[Conditional.scala 37:30]
|
|
when _T_2061 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 405:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2062 = eq(UInt<15>("h050"), address) @[Conditional.scala 37:30]
|
|
when _T_2062 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 406:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2063 = eq(UInt<15>("h054"), address) @[Conditional.scala 37:30]
|
|
when _T_2063 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 407:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2064 = eq(UInt<15>("h058"), address) @[Conditional.scala 37:30]
|
|
when _T_2064 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 408:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2065 = eq(UInt<15>("h05c"), address) @[Conditional.scala 37:30]
|
|
when _T_2065 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 409:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2066 = eq(UInt<15>("h060"), address) @[Conditional.scala 37:30]
|
|
when _T_2066 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 410:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2067 = eq(UInt<15>("h064"), address) @[Conditional.scala 37:30]
|
|
when _T_2067 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 411:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2068 = eq(UInt<15>("h068"), address) @[Conditional.scala 37:30]
|
|
when _T_2068 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 412:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2069 = eq(UInt<15>("h06c"), address) @[Conditional.scala 37:30]
|
|
when _T_2069 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 413:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2070 = eq(UInt<15>("h070"), address) @[Conditional.scala 37:30]
|
|
when _T_2070 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 414:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2071 = eq(UInt<15>("h074"), address) @[Conditional.scala 37:30]
|
|
when _T_2071 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 415:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2072 = eq(UInt<15>("h078"), address) @[Conditional.scala 37:30]
|
|
when _T_2072 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 416:44]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2073 = eq(UInt<15>("h07c"), address) @[Conditional.scala 37:30]
|
|
when _T_2073 : @[Conditional.scala 39:67]
|
|
mask <= UInt<4>("h02") @[el2_pic_ctl.scala 417:44]
|
|
skip @[Conditional.scala 39:67]
|
|
|