82589 lines
4.0 MiB
82589 lines
4.0 MiB
module rvclkhdr(
|
|
output io_l1clk,
|
|
input io_clk,
|
|
input io_en,
|
|
input io_scan_mode
|
|
);
|
|
wire clkhdr_Q; // @[el2_lib.scala 474:26]
|
|
wire clkhdr_CK; // @[el2_lib.scala 474:26]
|
|
wire clkhdr_EN; // @[el2_lib.scala 474:26]
|
|
wire clkhdr_SE; // @[el2_lib.scala 474:26]
|
|
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
|
|
.Q(clkhdr_Q),
|
|
.CK(clkhdr_CK),
|
|
.EN(clkhdr_EN),
|
|
.SE(clkhdr_SE)
|
|
);
|
|
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
|
|
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
|
|
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
|
|
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
|
|
endmodule
|
|
module el2_ifu_mem_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_free_clk,
|
|
input io_active_clk,
|
|
input io_exu_flush_final,
|
|
input io_dec_tlu_flush_lower_wb,
|
|
input io_dec_tlu_flush_err_wb,
|
|
input io_dec_tlu_i0_commit_cmt,
|
|
input io_dec_tlu_force_halt,
|
|
input [30:0] io_ifc_fetch_addr_bf,
|
|
input io_ifc_fetch_uncacheable_bf,
|
|
input io_ifc_fetch_req_bf,
|
|
input io_ifc_fetch_req_bf_raw,
|
|
input io_ifc_iccm_access_bf,
|
|
input io_ifc_region_acc_fault_bf,
|
|
input io_ifc_dma_access_ok,
|
|
input io_dec_tlu_fence_i_wb,
|
|
input io_ifu_bp_hit_taken_f,
|
|
input io_ifu_bp_inst_mask_f,
|
|
input io_ifu_axi_arready,
|
|
input io_ifu_axi_rvalid,
|
|
input [2:0] io_ifu_axi_rid,
|
|
input [63:0] io_ifu_axi_rdata,
|
|
input [1:0] io_ifu_axi_rresp,
|
|
input io_ifu_bus_clk_en,
|
|
input io_dma_iccm_req,
|
|
input [31:0] io_dma_mem_addr,
|
|
input [2:0] io_dma_mem_sz,
|
|
input io_dma_mem_write,
|
|
input [63:0] io_dma_mem_wdata,
|
|
input [2:0] io_dma_mem_tag,
|
|
input [63:0] io_ic_rd_data,
|
|
input [70:0] io_ic_debug_rd_data,
|
|
input [25:0] io_ictag_debug_rd_data,
|
|
input [1:0] io_ic_eccerr,
|
|
input [1:0] io_ic_rd_hit,
|
|
input io_ic_tag_perr,
|
|
input [63:0] io_iccm_rd_data,
|
|
input [77:0] io_iccm_rd_data_ecc,
|
|
input [1:0] io_ifu_fetch_val,
|
|
input [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata,
|
|
input [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics,
|
|
input io_dec_tlu_ic_diag_pkt_icache_rd_valid,
|
|
input io_dec_tlu_ic_diag_pkt_icache_wr_valid,
|
|
output io_ifu_miss_state_idle,
|
|
output io_ifu_ic_mb_empty,
|
|
output io_ic_dma_active,
|
|
output io_ic_write_stall,
|
|
output io_ifu_pmu_ic_miss,
|
|
output io_ifu_pmu_ic_hit,
|
|
output io_ifu_pmu_bus_error,
|
|
output io_ifu_pmu_bus_busy,
|
|
output io_ifu_pmu_bus_trxn,
|
|
output io_ifu_axi_arvalid,
|
|
output [2:0] io_ifu_axi_arid,
|
|
output [31:0] io_ifu_axi_araddr,
|
|
output [3:0] io_ifu_axi_arregion,
|
|
output io_ifu_axi_rready,
|
|
output io_iccm_dma_ecc_error,
|
|
output io_iccm_dma_rvalid,
|
|
output [63:0] io_iccm_dma_rdata,
|
|
output [2:0] io_iccm_dma_rtag,
|
|
output io_iccm_ready,
|
|
output [30:0] io_ic_rw_addr,
|
|
output [1:0] io_ic_wr_en,
|
|
output io_ic_rd_en,
|
|
output [70:0] io_ic_wr_data_0,
|
|
output [70:0] io_ic_wr_data_1,
|
|
output [70:0] io_ic_debug_wr_data,
|
|
output [70:0] io_ifu_ic_debug_rd_data,
|
|
output [9:0] io_ic_debug_addr,
|
|
output io_ic_debug_rd_en,
|
|
output io_ic_debug_wr_en,
|
|
output io_ic_debug_tag_array,
|
|
output [1:0] io_ic_debug_way,
|
|
output [1:0] io_ic_tag_valid,
|
|
output [14:0] io_iccm_rw_addr,
|
|
output io_iccm_wren,
|
|
output io_iccm_rden,
|
|
output [77:0] io_iccm_wr_data,
|
|
output [2:0] io_iccm_wr_size,
|
|
output io_ic_hit_f,
|
|
output io_ic_access_fault_f,
|
|
output [1:0] io_ic_access_fault_type_f,
|
|
output io_iccm_rd_ecc_single_err,
|
|
output io_iccm_rd_ecc_double_err,
|
|
output io_ic_error_start,
|
|
output io_ifu_async_error_start,
|
|
output io_iccm_dma_sb_error,
|
|
output [1:0] io_ic_fetch_val_f,
|
|
output [31:0] io_ic_data_f,
|
|
output [63:0] io_ic_premux_data,
|
|
output io_ic_sel_premux_data,
|
|
input io_dec_tlu_core_ecc_disable,
|
|
output io_ifu_ic_debug_rd_data_valid,
|
|
output io_iccm_buf_correct_ecc,
|
|
output io_iccm_correction_state,
|
|
input io_scan_mode
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
reg [31:0] _RAND_75;
|
|
reg [31:0] _RAND_76;
|
|
reg [31:0] _RAND_77;
|
|
reg [31:0] _RAND_78;
|
|
reg [31:0] _RAND_79;
|
|
reg [31:0] _RAND_80;
|
|
reg [31:0] _RAND_81;
|
|
reg [31:0] _RAND_82;
|
|
reg [31:0] _RAND_83;
|
|
reg [31:0] _RAND_84;
|
|
reg [31:0] _RAND_85;
|
|
reg [31:0] _RAND_86;
|
|
reg [31:0] _RAND_87;
|
|
reg [31:0] _RAND_88;
|
|
reg [31:0] _RAND_89;
|
|
reg [31:0] _RAND_90;
|
|
reg [31:0] _RAND_91;
|
|
reg [31:0] _RAND_92;
|
|
reg [31:0] _RAND_93;
|
|
reg [31:0] _RAND_94;
|
|
reg [31:0] _RAND_95;
|
|
reg [31:0] _RAND_96;
|
|
reg [31:0] _RAND_97;
|
|
reg [31:0] _RAND_98;
|
|
reg [31:0] _RAND_99;
|
|
reg [31:0] _RAND_100;
|
|
reg [31:0] _RAND_101;
|
|
reg [31:0] _RAND_102;
|
|
reg [31:0] _RAND_103;
|
|
reg [31:0] _RAND_104;
|
|
reg [31:0] _RAND_105;
|
|
reg [31:0] _RAND_106;
|
|
reg [31:0] _RAND_107;
|
|
reg [31:0] _RAND_108;
|
|
reg [31:0] _RAND_109;
|
|
reg [31:0] _RAND_110;
|
|
reg [31:0] _RAND_111;
|
|
reg [31:0] _RAND_112;
|
|
reg [31:0] _RAND_113;
|
|
reg [31:0] _RAND_114;
|
|
reg [31:0] _RAND_115;
|
|
reg [31:0] _RAND_116;
|
|
reg [31:0] _RAND_117;
|
|
reg [31:0] _RAND_118;
|
|
reg [31:0] _RAND_119;
|
|
reg [31:0] _RAND_120;
|
|
reg [31:0] _RAND_121;
|
|
reg [31:0] _RAND_122;
|
|
reg [31:0] _RAND_123;
|
|
reg [31:0] _RAND_124;
|
|
reg [31:0] _RAND_125;
|
|
reg [31:0] _RAND_126;
|
|
reg [31:0] _RAND_127;
|
|
reg [31:0] _RAND_128;
|
|
reg [31:0] _RAND_129;
|
|
reg [31:0] _RAND_130;
|
|
reg [31:0] _RAND_131;
|
|
reg [31:0] _RAND_132;
|
|
reg [31:0] _RAND_133;
|
|
reg [31:0] _RAND_134;
|
|
reg [31:0] _RAND_135;
|
|
reg [31:0] _RAND_136;
|
|
reg [31:0] _RAND_137;
|
|
reg [31:0] _RAND_138;
|
|
reg [31:0] _RAND_139;
|
|
reg [31:0] _RAND_140;
|
|
reg [31:0] _RAND_141;
|
|
reg [31:0] _RAND_142;
|
|
reg [31:0] _RAND_143;
|
|
reg [31:0] _RAND_144;
|
|
reg [31:0] _RAND_145;
|
|
reg [31:0] _RAND_146;
|
|
reg [31:0] _RAND_147;
|
|
reg [31:0] _RAND_148;
|
|
reg [31:0] _RAND_149;
|
|
reg [31:0] _RAND_150;
|
|
reg [31:0] _RAND_151;
|
|
reg [31:0] _RAND_152;
|
|
reg [31:0] _RAND_153;
|
|
reg [31:0] _RAND_154;
|
|
reg [31:0] _RAND_155;
|
|
reg [31:0] _RAND_156;
|
|
reg [31:0] _RAND_157;
|
|
reg [31:0] _RAND_158;
|
|
reg [31:0] _RAND_159;
|
|
reg [31:0] _RAND_160;
|
|
reg [31:0] _RAND_161;
|
|
reg [31:0] _RAND_162;
|
|
reg [31:0] _RAND_163;
|
|
reg [63:0] _RAND_164;
|
|
reg [31:0] _RAND_165;
|
|
reg [31:0] _RAND_166;
|
|
reg [31:0] _RAND_167;
|
|
reg [31:0] _RAND_168;
|
|
reg [31:0] _RAND_169;
|
|
reg [31:0] _RAND_170;
|
|
reg [31:0] _RAND_171;
|
|
reg [31:0] _RAND_172;
|
|
reg [31:0] _RAND_173;
|
|
reg [31:0] _RAND_174;
|
|
reg [31:0] _RAND_175;
|
|
reg [31:0] _RAND_176;
|
|
reg [31:0] _RAND_177;
|
|
reg [31:0] _RAND_178;
|
|
reg [31:0] _RAND_179;
|
|
reg [31:0] _RAND_180;
|
|
reg [31:0] _RAND_181;
|
|
reg [31:0] _RAND_182;
|
|
reg [31:0] _RAND_183;
|
|
reg [31:0] _RAND_184;
|
|
reg [31:0] _RAND_185;
|
|
reg [31:0] _RAND_186;
|
|
reg [31:0] _RAND_187;
|
|
reg [31:0] _RAND_188;
|
|
reg [31:0] _RAND_189;
|
|
reg [31:0] _RAND_190;
|
|
reg [31:0] _RAND_191;
|
|
reg [31:0] _RAND_192;
|
|
reg [31:0] _RAND_193;
|
|
reg [31:0] _RAND_194;
|
|
reg [31:0] _RAND_195;
|
|
reg [31:0] _RAND_196;
|
|
reg [31:0] _RAND_197;
|
|
reg [31:0] _RAND_198;
|
|
reg [31:0] _RAND_199;
|
|
reg [31:0] _RAND_200;
|
|
reg [31:0] _RAND_201;
|
|
reg [31:0] _RAND_202;
|
|
reg [31:0] _RAND_203;
|
|
reg [31:0] _RAND_204;
|
|
reg [31:0] _RAND_205;
|
|
reg [31:0] _RAND_206;
|
|
reg [31:0] _RAND_207;
|
|
reg [31:0] _RAND_208;
|
|
reg [31:0] _RAND_209;
|
|
reg [31:0] _RAND_210;
|
|
reg [31:0] _RAND_211;
|
|
reg [31:0] _RAND_212;
|
|
reg [31:0] _RAND_213;
|
|
reg [31:0] _RAND_214;
|
|
reg [31:0] _RAND_215;
|
|
reg [31:0] _RAND_216;
|
|
reg [31:0] _RAND_217;
|
|
reg [31:0] _RAND_218;
|
|
reg [31:0] _RAND_219;
|
|
reg [31:0] _RAND_220;
|
|
reg [31:0] _RAND_221;
|
|
reg [31:0] _RAND_222;
|
|
reg [31:0] _RAND_223;
|
|
reg [31:0] _RAND_224;
|
|
reg [31:0] _RAND_225;
|
|
reg [31:0] _RAND_226;
|
|
reg [31:0] _RAND_227;
|
|
reg [31:0] _RAND_228;
|
|
reg [31:0] _RAND_229;
|
|
reg [31:0] _RAND_230;
|
|
reg [31:0] _RAND_231;
|
|
reg [31:0] _RAND_232;
|
|
reg [31:0] _RAND_233;
|
|
reg [31:0] _RAND_234;
|
|
reg [31:0] _RAND_235;
|
|
reg [31:0] _RAND_236;
|
|
reg [31:0] _RAND_237;
|
|
reg [31:0] _RAND_238;
|
|
reg [31:0] _RAND_239;
|
|
reg [31:0] _RAND_240;
|
|
reg [31:0] _RAND_241;
|
|
reg [31:0] _RAND_242;
|
|
reg [31:0] _RAND_243;
|
|
reg [31:0] _RAND_244;
|
|
reg [31:0] _RAND_245;
|
|
reg [31:0] _RAND_246;
|
|
reg [31:0] _RAND_247;
|
|
reg [31:0] _RAND_248;
|
|
reg [31:0] _RAND_249;
|
|
reg [31:0] _RAND_250;
|
|
reg [31:0] _RAND_251;
|
|
reg [31:0] _RAND_252;
|
|
reg [31:0] _RAND_253;
|
|
reg [31:0] _RAND_254;
|
|
reg [31:0] _RAND_255;
|
|
reg [31:0] _RAND_256;
|
|
reg [31:0] _RAND_257;
|
|
reg [31:0] _RAND_258;
|
|
reg [31:0] _RAND_259;
|
|
reg [31:0] _RAND_260;
|
|
reg [31:0] _RAND_261;
|
|
reg [31:0] _RAND_262;
|
|
reg [31:0] _RAND_263;
|
|
reg [31:0] _RAND_264;
|
|
reg [31:0] _RAND_265;
|
|
reg [31:0] _RAND_266;
|
|
reg [31:0] _RAND_267;
|
|
reg [31:0] _RAND_268;
|
|
reg [31:0] _RAND_269;
|
|
reg [31:0] _RAND_270;
|
|
reg [31:0] _RAND_271;
|
|
reg [31:0] _RAND_272;
|
|
reg [31:0] _RAND_273;
|
|
reg [31:0] _RAND_274;
|
|
reg [31:0] _RAND_275;
|
|
reg [31:0] _RAND_276;
|
|
reg [31:0] _RAND_277;
|
|
reg [31:0] _RAND_278;
|
|
reg [31:0] _RAND_279;
|
|
reg [31:0] _RAND_280;
|
|
reg [31:0] _RAND_281;
|
|
reg [31:0] _RAND_282;
|
|
reg [31:0] _RAND_283;
|
|
reg [31:0] _RAND_284;
|
|
reg [31:0] _RAND_285;
|
|
reg [31:0] _RAND_286;
|
|
reg [31:0] _RAND_287;
|
|
reg [31:0] _RAND_288;
|
|
reg [31:0] _RAND_289;
|
|
reg [31:0] _RAND_290;
|
|
reg [31:0] _RAND_291;
|
|
reg [31:0] _RAND_292;
|
|
reg [31:0] _RAND_293;
|
|
reg [31:0] _RAND_294;
|
|
reg [31:0] _RAND_295;
|
|
reg [31:0] _RAND_296;
|
|
reg [31:0] _RAND_297;
|
|
reg [31:0] _RAND_298;
|
|
reg [31:0] _RAND_299;
|
|
reg [31:0] _RAND_300;
|
|
reg [31:0] _RAND_301;
|
|
reg [31:0] _RAND_302;
|
|
reg [31:0] _RAND_303;
|
|
reg [31:0] _RAND_304;
|
|
reg [31:0] _RAND_305;
|
|
reg [31:0] _RAND_306;
|
|
reg [31:0] _RAND_307;
|
|
reg [31:0] _RAND_308;
|
|
reg [31:0] _RAND_309;
|
|
reg [31:0] _RAND_310;
|
|
reg [31:0] _RAND_311;
|
|
reg [31:0] _RAND_312;
|
|
reg [31:0] _RAND_313;
|
|
reg [31:0] _RAND_314;
|
|
reg [31:0] _RAND_315;
|
|
reg [31:0] _RAND_316;
|
|
reg [31:0] _RAND_317;
|
|
reg [31:0] _RAND_318;
|
|
reg [31:0] _RAND_319;
|
|
reg [31:0] _RAND_320;
|
|
reg [31:0] _RAND_321;
|
|
reg [31:0] _RAND_322;
|
|
reg [31:0] _RAND_323;
|
|
reg [31:0] _RAND_324;
|
|
reg [31:0] _RAND_325;
|
|
reg [31:0] _RAND_326;
|
|
reg [31:0] _RAND_327;
|
|
reg [31:0] _RAND_328;
|
|
reg [31:0] _RAND_329;
|
|
reg [31:0] _RAND_330;
|
|
reg [31:0] _RAND_331;
|
|
reg [31:0] _RAND_332;
|
|
reg [31:0] _RAND_333;
|
|
reg [31:0] _RAND_334;
|
|
reg [31:0] _RAND_335;
|
|
reg [31:0] _RAND_336;
|
|
reg [31:0] _RAND_337;
|
|
reg [31:0] _RAND_338;
|
|
reg [31:0] _RAND_339;
|
|
reg [31:0] _RAND_340;
|
|
reg [31:0] _RAND_341;
|
|
reg [31:0] _RAND_342;
|
|
reg [31:0] _RAND_343;
|
|
reg [31:0] _RAND_344;
|
|
reg [31:0] _RAND_345;
|
|
reg [31:0] _RAND_346;
|
|
reg [31:0] _RAND_347;
|
|
reg [31:0] _RAND_348;
|
|
reg [31:0] _RAND_349;
|
|
reg [31:0] _RAND_350;
|
|
reg [31:0] _RAND_351;
|
|
reg [31:0] _RAND_352;
|
|
reg [31:0] _RAND_353;
|
|
reg [31:0] _RAND_354;
|
|
reg [31:0] _RAND_355;
|
|
reg [31:0] _RAND_356;
|
|
reg [31:0] _RAND_357;
|
|
reg [31:0] _RAND_358;
|
|
reg [31:0] _RAND_359;
|
|
reg [31:0] _RAND_360;
|
|
reg [31:0] _RAND_361;
|
|
reg [31:0] _RAND_362;
|
|
reg [31:0] _RAND_363;
|
|
reg [31:0] _RAND_364;
|
|
reg [31:0] _RAND_365;
|
|
reg [31:0] _RAND_366;
|
|
reg [31:0] _RAND_367;
|
|
reg [31:0] _RAND_368;
|
|
reg [31:0] _RAND_369;
|
|
reg [31:0] _RAND_370;
|
|
reg [31:0] _RAND_371;
|
|
reg [31:0] _RAND_372;
|
|
reg [31:0] _RAND_373;
|
|
reg [31:0] _RAND_374;
|
|
reg [31:0] _RAND_375;
|
|
reg [31:0] _RAND_376;
|
|
reg [31:0] _RAND_377;
|
|
reg [31:0] _RAND_378;
|
|
reg [31:0] _RAND_379;
|
|
reg [31:0] _RAND_380;
|
|
reg [31:0] _RAND_381;
|
|
reg [31:0] _RAND_382;
|
|
reg [31:0] _RAND_383;
|
|
reg [31:0] _RAND_384;
|
|
reg [31:0] _RAND_385;
|
|
reg [31:0] _RAND_386;
|
|
reg [31:0] _RAND_387;
|
|
reg [31:0] _RAND_388;
|
|
reg [31:0] _RAND_389;
|
|
reg [31:0] _RAND_390;
|
|
reg [31:0] _RAND_391;
|
|
reg [31:0] _RAND_392;
|
|
reg [31:0] _RAND_393;
|
|
reg [31:0] _RAND_394;
|
|
reg [31:0] _RAND_395;
|
|
reg [31:0] _RAND_396;
|
|
reg [31:0] _RAND_397;
|
|
reg [31:0] _RAND_398;
|
|
reg [31:0] _RAND_399;
|
|
reg [31:0] _RAND_400;
|
|
reg [31:0] _RAND_401;
|
|
reg [31:0] _RAND_402;
|
|
reg [31:0] _RAND_403;
|
|
reg [31:0] _RAND_404;
|
|
reg [31:0] _RAND_405;
|
|
reg [31:0] _RAND_406;
|
|
reg [31:0] _RAND_407;
|
|
reg [31:0] _RAND_408;
|
|
reg [31:0] _RAND_409;
|
|
reg [31:0] _RAND_410;
|
|
reg [31:0] _RAND_411;
|
|
reg [31:0] _RAND_412;
|
|
reg [31:0] _RAND_413;
|
|
reg [31:0] _RAND_414;
|
|
reg [31:0] _RAND_415;
|
|
reg [31:0] _RAND_416;
|
|
reg [31:0] _RAND_417;
|
|
reg [31:0] _RAND_418;
|
|
reg [31:0] _RAND_419;
|
|
reg [31:0] _RAND_420;
|
|
reg [31:0] _RAND_421;
|
|
reg [31:0] _RAND_422;
|
|
reg [31:0] _RAND_423;
|
|
reg [31:0] _RAND_424;
|
|
reg [31:0] _RAND_425;
|
|
reg [31:0] _RAND_426;
|
|
reg [31:0] _RAND_427;
|
|
reg [31:0] _RAND_428;
|
|
reg [31:0] _RAND_429;
|
|
reg [31:0] _RAND_430;
|
|
reg [31:0] _RAND_431;
|
|
reg [31:0] _RAND_432;
|
|
reg [31:0] _RAND_433;
|
|
reg [31:0] _RAND_434;
|
|
reg [31:0] _RAND_435;
|
|
reg [31:0] _RAND_436;
|
|
reg [31:0] _RAND_437;
|
|
reg [31:0] _RAND_438;
|
|
reg [31:0] _RAND_439;
|
|
reg [31:0] _RAND_440;
|
|
reg [31:0] _RAND_441;
|
|
reg [95:0] _RAND_442;
|
|
reg [31:0] _RAND_443;
|
|
reg [31:0] _RAND_444;
|
|
reg [31:0] _RAND_445;
|
|
reg [31:0] _RAND_446;
|
|
reg [31:0] _RAND_447;
|
|
reg [31:0] _RAND_448;
|
|
reg [31:0] _RAND_449;
|
|
reg [63:0] _RAND_450;
|
|
reg [31:0] _RAND_451;
|
|
reg [31:0] _RAND_452;
|
|
reg [31:0] _RAND_453;
|
|
reg [31:0] _RAND_454;
|
|
reg [63:0] _RAND_455;
|
|
reg [31:0] _RAND_456;
|
|
reg [31:0] _RAND_457;
|
|
reg [31:0] _RAND_458;
|
|
reg [31:0] _RAND_459;
|
|
reg [31:0] _RAND_460;
|
|
reg [31:0] _RAND_461;
|
|
reg [31:0] _RAND_462;
|
|
reg [31:0] _RAND_463;
|
|
reg [31:0] _RAND_464;
|
|
reg [31:0] _RAND_465;
|
|
reg [31:0] _RAND_466;
|
|
reg [31:0] _RAND_467;
|
|
reg [31:0] _RAND_468;
|
|
reg [31:0] _RAND_469;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_6_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_7_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_8_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_10_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_11_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_12_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_12_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_13_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_13_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_14_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_14_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_15_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_15_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_16_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_16_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_17_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_17_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_18_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_18_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_19_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_19_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_20_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_20_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_21_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_21_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_22_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_22_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_23_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_23_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_24_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_24_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_25_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_25_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_26_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_26_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_27_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_27_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_28_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_28_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_29_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_29_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_30_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_30_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_31_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_31_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_31_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_31_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_32_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_32_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_32_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_32_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_33_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_33_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_33_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_33_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_34_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_34_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_34_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_34_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_35_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_35_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_35_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_35_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_36_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_36_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_36_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_36_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_37_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_37_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_37_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_37_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_38_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_38_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_38_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_38_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_39_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_39_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_39_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_39_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_40_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_40_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_40_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_40_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_41_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_41_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_41_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_41_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_42_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_42_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_42_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_42_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_43_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_43_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_43_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_43_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_44_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_44_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_44_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_44_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_45_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_45_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_45_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_45_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_46_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_46_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_46_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_46_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_47_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_47_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_47_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_47_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_48_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_48_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_48_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_48_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_49_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_49_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_49_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_49_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_50_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_50_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_50_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_50_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_51_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_51_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_51_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_51_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_52_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_52_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_52_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_52_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_53_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_53_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_53_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_53_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_54_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_54_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_54_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_54_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_55_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_55_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_55_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_55_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_56_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_56_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_56_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_56_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_57_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_57_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_57_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_57_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_58_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_58_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_58_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_58_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_59_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_59_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_59_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_59_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_60_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_60_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_60_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_60_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_61_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_61_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_61_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_61_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_62_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_62_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_62_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_62_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_63_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_63_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_63_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_63_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_64_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_64_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_64_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_64_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_65_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_65_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_65_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_65_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_66_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_66_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_66_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_66_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_67_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_67_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_67_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_67_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_68_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_68_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_68_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_68_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_69_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_69_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_69_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_69_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_70_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_70_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_70_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_70_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_71_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_71_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_71_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_71_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_72_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_72_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_72_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_72_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_73_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_73_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_73_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_73_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_74_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_74_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_74_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_74_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_75_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_75_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_75_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_75_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_76_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_76_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_76_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_76_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_77_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_77_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_77_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_77_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_78_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_78_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_78_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_78_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_79_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_79_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_79_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_79_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_80_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_80_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_80_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_80_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_81_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_81_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_81_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_81_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_82_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_82_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_82_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_82_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_83_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_83_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_83_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_83_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_84_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_84_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_84_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_84_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_85_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_85_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_85_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_85_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_86_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_86_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_86_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_86_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_87_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_87_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_87_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_87_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_88_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_88_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_88_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_88_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_89_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_89_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_89_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_89_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_90_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_90_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_90_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_90_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_91_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_91_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_91_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_91_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_92_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_92_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_92_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_92_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_93_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_93_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_93_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_93_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
reg flush_final_f; // @[el2_ifu_mem_ctl.scala 187:30]
|
|
reg ifc_fetch_req_f_raw; // @[el2_ifu_mem_ctl.scala 323:36]
|
|
wire _T_319 = ~io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 324:44]
|
|
wire ifc_fetch_req_f = ifc_fetch_req_f_raw & _T_319; // @[el2_ifu_mem_ctl.scala 324:42]
|
|
wire _T = io_ifc_fetch_req_bf_raw | ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 188:53]
|
|
reg [2:0] miss_state; // @[Reg.scala 27:20]
|
|
wire miss_pending = miss_state != 3'h0; // @[el2_ifu_mem_ctl.scala 255:30]
|
|
wire _T_1 = _T | miss_pending; // @[el2_ifu_mem_ctl.scala 188:71]
|
|
wire _T_2 = _T_1 | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 188:86]
|
|
reg scnd_miss_req_q; // @[el2_ifu_mem_ctl.scala 553:52]
|
|
wire scnd_miss_req = scnd_miss_req_q & _T_319; // @[el2_ifu_mem_ctl.scala 555:36]
|
|
wire debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_mem_ctl.scala 189:42]
|
|
wire [3:0] ic_fetch_val_int_f = {2'h0,io_ic_fetch_val_f}; // @[Cat.scala 29:58]
|
|
reg [30:0] ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 310:63]
|
|
wire [4:0] _GEN_437 = {{1'd0}, ic_fetch_val_int_f}; // @[el2_ifu_mem_ctl.scala 671:53]
|
|
wire [4:0] ic_fetch_val_shift_right = _GEN_437 << ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 671:53]
|
|
wire [1:0] _GEN_438 = {{1'd0}, _T_319}; // @[el2_ifu_mem_ctl.scala 674:91]
|
|
wire [1:0] _T_3079 = ic_fetch_val_shift_right[3:2] & _GEN_438; // @[el2_ifu_mem_ctl.scala 674:91]
|
|
reg ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 325:60]
|
|
wire fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 277:46]
|
|
wire [1:0] _GEN_439 = {{1'd0}, fetch_req_iccm_f}; // @[el2_ifu_mem_ctl.scala 674:113]
|
|
wire [1:0] _T_3080 = _T_3079 & _GEN_439; // @[el2_ifu_mem_ctl.scala 674:113]
|
|
reg iccm_dma_rvalid_in; // @[el2_ifu_mem_ctl.scala 660:59]
|
|
wire [1:0] _GEN_440 = {{1'd0}, iccm_dma_rvalid_in}; // @[el2_ifu_mem_ctl.scala 674:130]
|
|
wire [1:0] _T_3081 = _T_3080 | _GEN_440; // @[el2_ifu_mem_ctl.scala 674:130]
|
|
wire _T_3082 = ~io_dec_tlu_core_ecc_disable; // @[el2_ifu_mem_ctl.scala 674:154]
|
|
wire [1:0] _GEN_441 = {{1'd0}, _T_3082}; // @[el2_ifu_mem_ctl.scala 674:152]
|
|
wire [1:0] _T_3083 = _T_3081 & _GEN_441; // @[el2_ifu_mem_ctl.scala 674:152]
|
|
wire [1:0] _T_3072 = ic_fetch_val_shift_right[1:0] & _GEN_438; // @[el2_ifu_mem_ctl.scala 674:91]
|
|
wire [1:0] _T_3073 = _T_3072 & _GEN_439; // @[el2_ifu_mem_ctl.scala 674:113]
|
|
wire [1:0] _T_3074 = _T_3073 | _GEN_440; // @[el2_ifu_mem_ctl.scala 674:130]
|
|
wire [1:0] _T_3076 = _T_3074 & _GEN_441; // @[el2_ifu_mem_ctl.scala 674:152]
|
|
wire [3:0] iccm_ecc_word_enable = {_T_3083,_T_3076}; // @[Cat.scala 29:58]
|
|
wire _T_3183 = ^io_iccm_rd_data_ecc[31:0]; // @[el2_lib.scala 333:30]
|
|
wire _T_3184 = ^io_iccm_rd_data_ecc[38:32]; // @[el2_lib.scala 333:44]
|
|
wire _T_3185 = _T_3183 ^ _T_3184; // @[el2_lib.scala 333:35]
|
|
wire [5:0] _T_3193 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[29],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[27],io_iccm_rd_data_ecc[26]}; // @[el2_lib.scala 333:76]
|
|
wire _T_3194 = ^_T_3193; // @[el2_lib.scala 333:83]
|
|
wire _T_3195 = io_iccm_rd_data_ecc[37] ^ _T_3194; // @[el2_lib.scala 333:71]
|
|
wire [6:0] _T_3202 = {io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],io_iccm_rd_data_ecc[15],io_iccm_rd_data_ecc[14],io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[12],io_iccm_rd_data_ecc[11]}; // @[el2_lib.scala 333:103]
|
|
wire [14:0] _T_3210 = {io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[18],_T_3202}; // @[el2_lib.scala 333:103]
|
|
wire _T_3211 = ^_T_3210; // @[el2_lib.scala 333:110]
|
|
wire _T_3212 = io_iccm_rd_data_ecc[36] ^ _T_3211; // @[el2_lib.scala 333:98]
|
|
wire [6:0] _T_3219 = {io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[7],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[5],io_iccm_rd_data_ecc[4]}; // @[el2_lib.scala 333:130]
|
|
wire [14:0] _T_3227 = {io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[18],_T_3219}; // @[el2_lib.scala 333:130]
|
|
wire _T_3228 = ^_T_3227; // @[el2_lib.scala 333:137]
|
|
wire _T_3229 = io_iccm_rd_data_ecc[35] ^ _T_3228; // @[el2_lib.scala 333:125]
|
|
wire [8:0] _T_3238 = {io_iccm_rd_data_ecc[15],io_iccm_rd_data_ecc[14],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[7],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[2],io_iccm_rd_data_ecc[1]}; // @[el2_lib.scala 333:157]
|
|
wire [17:0] _T_3247 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[29],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],_T_3238}; // @[el2_lib.scala 333:157]
|
|
wire _T_3248 = ^_T_3247; // @[el2_lib.scala 333:164]
|
|
wire _T_3249 = io_iccm_rd_data_ecc[34] ^ _T_3248; // @[el2_lib.scala 333:152]
|
|
wire [8:0] _T_3258 = {io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[12],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[5],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[2],io_iccm_rd_data_ecc[0]}; // @[el2_lib.scala 333:184]
|
|
wire [17:0] _T_3267 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[27],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],_T_3258}; // @[el2_lib.scala 333:184]
|
|
wire _T_3268 = ^_T_3267; // @[el2_lib.scala 333:191]
|
|
wire _T_3269 = io_iccm_rd_data_ecc[33] ^ _T_3268; // @[el2_lib.scala 333:179]
|
|
wire [8:0] _T_3278 = {io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[11],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[4],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[1],io_iccm_rd_data_ecc[0]}; // @[el2_lib.scala 333:211]
|
|
wire [17:0] _T_3287 = {io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[26],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[15],_T_3278}; // @[el2_lib.scala 333:211]
|
|
wire _T_3288 = ^_T_3287; // @[el2_lib.scala 333:218]
|
|
wire _T_3289 = io_iccm_rd_data_ecc[32] ^ _T_3288; // @[el2_lib.scala 333:206]
|
|
wire [6:0] _T_3295 = {_T_3185,_T_3195,_T_3212,_T_3229,_T_3249,_T_3269,_T_3289}; // @[Cat.scala 29:58]
|
|
wire _T_3296 = _T_3295 != 7'h0; // @[el2_lib.scala 334:44]
|
|
wire _T_3297 = iccm_ecc_word_enable[0] & _T_3296; // @[el2_lib.scala 334:32]
|
|
wire _T_3299 = _T_3297 & _T_3295[6]; // @[el2_lib.scala 334:53]
|
|
wire _T_3568 = ^io_iccm_rd_data_ecc[70:39]; // @[el2_lib.scala 333:30]
|
|
wire _T_3569 = ^io_iccm_rd_data_ecc[77:71]; // @[el2_lib.scala 333:44]
|
|
wire _T_3570 = _T_3568 ^ _T_3569; // @[el2_lib.scala 333:35]
|
|
wire [5:0] _T_3578 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[68],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[66],io_iccm_rd_data_ecc[65]}; // @[el2_lib.scala 333:76]
|
|
wire _T_3579 = ^_T_3578; // @[el2_lib.scala 333:83]
|
|
wire _T_3580 = io_iccm_rd_data_ecc[76] ^ _T_3579; // @[el2_lib.scala 333:71]
|
|
wire [6:0] _T_3587 = {io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],io_iccm_rd_data_ecc[54],io_iccm_rd_data_ecc[53],io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[51],io_iccm_rd_data_ecc[50]}; // @[el2_lib.scala 333:103]
|
|
wire [14:0] _T_3595 = {io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[57],_T_3587}; // @[el2_lib.scala 333:103]
|
|
wire _T_3596 = ^_T_3595; // @[el2_lib.scala 333:110]
|
|
wire _T_3597 = io_iccm_rd_data_ecc[75] ^ _T_3596; // @[el2_lib.scala 333:98]
|
|
wire [6:0] _T_3604 = {io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[46],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[44],io_iccm_rd_data_ecc[43]}; // @[el2_lib.scala 333:130]
|
|
wire [14:0] _T_3612 = {io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[57],_T_3604}; // @[el2_lib.scala 333:130]
|
|
wire _T_3613 = ^_T_3612; // @[el2_lib.scala 333:137]
|
|
wire _T_3614 = io_iccm_rd_data_ecc[74] ^ _T_3613; // @[el2_lib.scala 333:125]
|
|
wire [8:0] _T_3623 = {io_iccm_rd_data_ecc[54],io_iccm_rd_data_ecc[53],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[46],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[41],io_iccm_rd_data_ecc[40]}; // @[el2_lib.scala 333:157]
|
|
wire [17:0] _T_3632 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[68],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],_T_3623}; // @[el2_lib.scala 333:157]
|
|
wire _T_3633 = ^_T_3632; // @[el2_lib.scala 333:164]
|
|
wire _T_3634 = io_iccm_rd_data_ecc[73] ^ _T_3633; // @[el2_lib.scala 333:152]
|
|
wire [8:0] _T_3643 = {io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[51],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[44],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[41],io_iccm_rd_data_ecc[39]}; // @[el2_lib.scala 333:184]
|
|
wire [17:0] _T_3652 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[66],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],_T_3643}; // @[el2_lib.scala 333:184]
|
|
wire _T_3653 = ^_T_3652; // @[el2_lib.scala 333:191]
|
|
wire _T_3654 = io_iccm_rd_data_ecc[72] ^ _T_3653; // @[el2_lib.scala 333:179]
|
|
wire [8:0] _T_3663 = {io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[50],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[43],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[40],io_iccm_rd_data_ecc[39]}; // @[el2_lib.scala 333:211]
|
|
wire [17:0] _T_3672 = {io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[65],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[54],_T_3663}; // @[el2_lib.scala 333:211]
|
|
wire _T_3673 = ^_T_3672; // @[el2_lib.scala 333:218]
|
|
wire _T_3674 = io_iccm_rd_data_ecc[71] ^ _T_3673; // @[el2_lib.scala 333:206]
|
|
wire [6:0] _T_3680 = {_T_3570,_T_3580,_T_3597,_T_3614,_T_3634,_T_3654,_T_3674}; // @[Cat.scala 29:58]
|
|
wire _T_3681 = _T_3680 != 7'h0; // @[el2_lib.scala 334:44]
|
|
wire _T_3682 = iccm_ecc_word_enable[1] & _T_3681; // @[el2_lib.scala 334:32]
|
|
wire _T_3684 = _T_3682 & _T_3680[6]; // @[el2_lib.scala 334:53]
|
|
wire [1:0] iccm_single_ecc_error = {_T_3299,_T_3684}; // @[Cat.scala 29:58]
|
|
wire _T_3 = |iccm_single_ecc_error; // @[el2_ifu_mem_ctl.scala 192:52]
|
|
reg dma_iccm_req_f; // @[el2_ifu_mem_ctl.scala 637:51]
|
|
wire _T_6 = io_iccm_rd_ecc_single_err | io_ic_error_start; // @[el2_ifu_mem_ctl.scala 193:57]
|
|
reg [2:0] perr_state; // @[Reg.scala 27:20]
|
|
wire _T_7 = perr_state == 3'h4; // @[el2_ifu_mem_ctl.scala 194:54]
|
|
wire iccm_correct_ecc = perr_state == 3'h3; // @[el2_ifu_mem_ctl.scala 480:34]
|
|
wire _T_8 = iccm_correct_ecc | _T_7; // @[el2_ifu_mem_ctl.scala 194:40]
|
|
reg [1:0] err_stop_state; // @[Reg.scala 27:20]
|
|
wire _T_9 = err_stop_state == 2'h3; // @[el2_ifu_mem_ctl.scala 194:90]
|
|
wire _T_10 = _T_8 | _T_9; // @[el2_ifu_mem_ctl.scala 194:72]
|
|
wire _T_2476 = 2'h0 == err_stop_state; // @[Conditional.scala 37:30]
|
|
wire _T_2481 = 2'h1 == err_stop_state; // @[Conditional.scala 37:30]
|
|
wire _T_2501 = io_ifu_fetch_val == 2'h3; // @[el2_ifu_mem_ctl.scala 530:48]
|
|
wire two_byte_instr = io_ic_data_f[1:0] != 2'h3; // @[el2_ifu_mem_ctl.scala 393:42]
|
|
wire _T_2503 = io_ifu_fetch_val[0] & two_byte_instr; // @[el2_ifu_mem_ctl.scala 530:79]
|
|
wire _T_2504 = _T_2501 | _T_2503; // @[el2_ifu_mem_ctl.scala 530:56]
|
|
wire _T_2505 = io_exu_flush_final | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 530:122]
|
|
wire _T_2506 = ~_T_2505; // @[el2_ifu_mem_ctl.scala 530:101]
|
|
wire _T_2507 = _T_2504 & _T_2506; // @[el2_ifu_mem_ctl.scala 530:99]
|
|
wire _T_2508 = 2'h2 == err_stop_state; // @[Conditional.scala 37:30]
|
|
wire _T_2522 = io_ifu_fetch_val[0] & _T_319; // @[el2_ifu_mem_ctl.scala 537:45]
|
|
wire _T_2523 = ~io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 537:69]
|
|
wire _T_2524 = _T_2522 & _T_2523; // @[el2_ifu_mem_ctl.scala 537:67]
|
|
wire _T_2525 = 2'h3 == err_stop_state; // @[Conditional.scala 37:30]
|
|
wire _GEN_38 = _T_2508 ? _T_2524 : _T_2525; // @[Conditional.scala 39:67]
|
|
wire _GEN_42 = _T_2481 ? _T_2507 : _GEN_38; // @[Conditional.scala 39:67]
|
|
wire err_stop_fetch = _T_2476 ? 1'h0 : _GEN_42; // @[Conditional.scala 40:58]
|
|
wire _T_11 = _T_10 | err_stop_fetch; // @[el2_ifu_mem_ctl.scala 194:112]
|
|
wire _T_13 = io_ifu_axi_rvalid & io_ifu_bus_clk_en; // @[el2_ifu_mem_ctl.scala 196:44]
|
|
wire _T_14 = _T_13 & io_ifu_axi_rready; // @[el2_ifu_mem_ctl.scala 196:65]
|
|
wire _T_227 = |io_ic_rd_hit; // @[el2_ifu_mem_ctl.scala 285:37]
|
|
wire _T_228 = ~_T_227; // @[el2_ifu_mem_ctl.scala 285:23]
|
|
reg reset_all_tags; // @[el2_ifu_mem_ctl.scala 706:53]
|
|
wire _T_229 = _T_228 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 285:41]
|
|
wire _T_207 = ~ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 276:48]
|
|
wire _T_208 = ifc_fetch_req_f & _T_207; // @[el2_ifu_mem_ctl.scala 276:46]
|
|
reg ifc_region_acc_fault_final_f; // @[el2_ifu_mem_ctl.scala 327:71]
|
|
wire _T_209 = ~ifc_region_acc_fault_final_f; // @[el2_ifu_mem_ctl.scala 276:69]
|
|
wire fetch_req_icache_f = _T_208 & _T_209; // @[el2_ifu_mem_ctl.scala 276:67]
|
|
wire _T_230 = _T_229 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 285:59]
|
|
wire _T_231 = ~miss_pending; // @[el2_ifu_mem_ctl.scala 285:82]
|
|
wire _T_232 = _T_230 & _T_231; // @[el2_ifu_mem_ctl.scala 285:80]
|
|
wire _T_233 = _T_232 | scnd_miss_req; // @[el2_ifu_mem_ctl.scala 285:97]
|
|
wire ic_act_miss_f = _T_233 & _T_209; // @[el2_ifu_mem_ctl.scala 285:114]
|
|
reg ifu_bus_rvalid_unq_ff; // @[el2_ifu_mem_ctl.scala 580:56]
|
|
reg bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 552:61]
|
|
wire ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 594:49]
|
|
wire bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; // @[el2_ifu_mem_ctl.scala 621:41]
|
|
reg uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 312:62]
|
|
reg [2:0] bus_data_beat_count; // @[el2_ifu_mem_ctl.scala 602:56]
|
|
wire _T_2622 = bus_data_beat_count == 3'h1; // @[el2_ifu_mem_ctl.scala 619:69]
|
|
wire _T_2623 = &bus_data_beat_count; // @[el2_ifu_mem_ctl.scala 619:101]
|
|
wire bus_last_data_beat = uncacheable_miss_ff ? _T_2622 : _T_2623; // @[el2_ifu_mem_ctl.scala 619:28]
|
|
wire _T_2574 = bus_ifu_wr_en_ff & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 598:68]
|
|
wire _T_2575 = ic_act_miss_f | _T_2574; // @[el2_ifu_mem_ctl.scala 598:48]
|
|
wire bus_reset_data_beat_cnt = _T_2575 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 598:91]
|
|
wire _T_2571 = ~bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 597:50]
|
|
wire _T_2572 = bus_ifu_wr_en_ff & _T_2571; // @[el2_ifu_mem_ctl.scala 597:48]
|
|
wire _T_2573 = ~io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 597:72]
|
|
wire bus_inc_data_beat_cnt = _T_2572 & _T_2573; // @[el2_ifu_mem_ctl.scala 597:70]
|
|
wire [2:0] _T_2579 = bus_data_beat_count + 3'h1; // @[el2_ifu_mem_ctl.scala 601:115]
|
|
wire [2:0] _T_2581 = bus_inc_data_beat_cnt ? _T_2579 : 3'h0; // @[Mux.scala 27:72]
|
|
wire _T_2576 = ~bus_inc_data_beat_cnt; // @[el2_ifu_mem_ctl.scala 599:32]
|
|
wire _T_2577 = ~bus_reset_data_beat_cnt; // @[el2_ifu_mem_ctl.scala 599:57]
|
|
wire bus_hold_data_beat_cnt = _T_2576 & _T_2577; // @[el2_ifu_mem_ctl.scala 599:55]
|
|
wire [2:0] _T_2582 = bus_hold_data_beat_cnt ? bus_data_beat_count : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] bus_new_data_beat_count = _T_2581 | _T_2582; // @[Mux.scala 27:72]
|
|
wire _T_15 = &bus_new_data_beat_count; // @[el2_ifu_mem_ctl.scala 196:112]
|
|
wire _T_16 = _T_14 & _T_15; // @[el2_ifu_mem_ctl.scala 196:85]
|
|
wire _T_17 = ~uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 197:5]
|
|
wire _T_18 = _T_16 & _T_17; // @[el2_ifu_mem_ctl.scala 196:118]
|
|
wire _T_19 = miss_state == 3'h5; // @[el2_ifu_mem_ctl.scala 197:41]
|
|
wire _T_24 = 3'h0 == miss_state; // @[Conditional.scala 37:30]
|
|
wire _T_26 = ic_act_miss_f & _T_319; // @[el2_ifu_mem_ctl.scala 203:43]
|
|
wire [2:0] _T_28 = _T_26 ? 3'h1 : 3'h2; // @[el2_ifu_mem_ctl.scala 203:27]
|
|
wire _T_31 = 3'h1 == miss_state; // @[Conditional.scala 37:30]
|
|
wire [4:0] byp_fetch_index = ifu_fetch_addr_int_f[4:0]; // @[el2_ifu_mem_ctl.scala 430:45]
|
|
wire _T_2106 = byp_fetch_index[4:2] == 3'h0; // @[el2_ifu_mem_ctl.scala 451:127]
|
|
reg [7:0] ic_miss_buff_data_valid; // @[el2_ifu_mem_ctl.scala 407:60]
|
|
wire _T_2137 = _T_2106 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72]
|
|
wire _T_2110 = byp_fetch_index[4:2] == 3'h1; // @[el2_ifu_mem_ctl.scala 451:127]
|
|
wire _T_2138 = _T_2110 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72]
|
|
wire _T_2145 = _T_2137 | _T_2138; // @[Mux.scala 27:72]
|
|
wire _T_2114 = byp_fetch_index[4:2] == 3'h2; // @[el2_ifu_mem_ctl.scala 451:127]
|
|
wire _T_2139 = _T_2114 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72]
|
|
wire _T_2146 = _T_2145 | _T_2139; // @[Mux.scala 27:72]
|
|
wire _T_2118 = byp_fetch_index[4:2] == 3'h3; // @[el2_ifu_mem_ctl.scala 451:127]
|
|
wire _T_2140 = _T_2118 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72]
|
|
wire _T_2147 = _T_2146 | _T_2140; // @[Mux.scala 27:72]
|
|
wire _T_2122 = byp_fetch_index[4:2] == 3'h4; // @[el2_ifu_mem_ctl.scala 451:127]
|
|
wire _T_2141 = _T_2122 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72]
|
|
wire _T_2148 = _T_2147 | _T_2141; // @[Mux.scala 27:72]
|
|
wire _T_2126 = byp_fetch_index[4:2] == 3'h5; // @[el2_ifu_mem_ctl.scala 451:127]
|
|
wire _T_2142 = _T_2126 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72]
|
|
wire _T_2149 = _T_2148 | _T_2142; // @[Mux.scala 27:72]
|
|
wire _T_2130 = byp_fetch_index[4:2] == 3'h6; // @[el2_ifu_mem_ctl.scala 451:127]
|
|
wire _T_2143 = _T_2130 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72]
|
|
wire _T_2150 = _T_2149 | _T_2143; // @[Mux.scala 27:72]
|
|
wire _T_2134 = byp_fetch_index[4:2] == 3'h7; // @[el2_ifu_mem_ctl.scala 451:127]
|
|
wire _T_2144 = _T_2134 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_valid_bypass_index = _T_2150 | _T_2144; // @[Mux.scala 27:72]
|
|
wire _T_2192 = ~byp_fetch_index[1]; // @[el2_ifu_mem_ctl.scala 453:69]
|
|
wire _T_2193 = ic_miss_buff_data_valid_bypass_index & _T_2192; // @[el2_ifu_mem_ctl.scala 453:67]
|
|
wire _T_2195 = ~byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 453:91]
|
|
wire _T_2196 = _T_2193 & _T_2195; // @[el2_ifu_mem_ctl.scala 453:89]
|
|
wire _T_2201 = _T_2193 & byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 454:65]
|
|
wire _T_2202 = _T_2196 | _T_2201; // @[el2_ifu_mem_ctl.scala 453:112]
|
|
wire _T_2204 = ic_miss_buff_data_valid_bypass_index & byp_fetch_index[1]; // @[el2_ifu_mem_ctl.scala 455:43]
|
|
wire _T_2207 = _T_2204 & _T_2195; // @[el2_ifu_mem_ctl.scala 455:65]
|
|
wire _T_2208 = _T_2202 | _T_2207; // @[el2_ifu_mem_ctl.scala 454:88]
|
|
wire _T_2212 = _T_2204 & byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 456:65]
|
|
wire [2:0] byp_fetch_index_inc = ifu_fetch_addr_int_f[4:2] + 3'h1; // @[el2_ifu_mem_ctl.scala 433:75]
|
|
wire _T_2152 = byp_fetch_index_inc == 3'h0; // @[el2_ifu_mem_ctl.scala 452:110]
|
|
wire _T_2176 = _T_2152 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72]
|
|
wire _T_2155 = byp_fetch_index_inc == 3'h1; // @[el2_ifu_mem_ctl.scala 452:110]
|
|
wire _T_2177 = _T_2155 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72]
|
|
wire _T_2184 = _T_2176 | _T_2177; // @[Mux.scala 27:72]
|
|
wire _T_2158 = byp_fetch_index_inc == 3'h2; // @[el2_ifu_mem_ctl.scala 452:110]
|
|
wire _T_2178 = _T_2158 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72]
|
|
wire _T_2185 = _T_2184 | _T_2178; // @[Mux.scala 27:72]
|
|
wire _T_2161 = byp_fetch_index_inc == 3'h3; // @[el2_ifu_mem_ctl.scala 452:110]
|
|
wire _T_2179 = _T_2161 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72]
|
|
wire _T_2186 = _T_2185 | _T_2179; // @[Mux.scala 27:72]
|
|
wire _T_2164 = byp_fetch_index_inc == 3'h4; // @[el2_ifu_mem_ctl.scala 452:110]
|
|
wire _T_2180 = _T_2164 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72]
|
|
wire _T_2187 = _T_2186 | _T_2180; // @[Mux.scala 27:72]
|
|
wire _T_2167 = byp_fetch_index_inc == 3'h5; // @[el2_ifu_mem_ctl.scala 452:110]
|
|
wire _T_2181 = _T_2167 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72]
|
|
wire _T_2188 = _T_2187 | _T_2181; // @[Mux.scala 27:72]
|
|
wire _T_2170 = byp_fetch_index_inc == 3'h6; // @[el2_ifu_mem_ctl.scala 452:110]
|
|
wire _T_2182 = _T_2170 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72]
|
|
wire _T_2189 = _T_2188 | _T_2182; // @[Mux.scala 27:72]
|
|
wire _T_2173 = byp_fetch_index_inc == 3'h7; // @[el2_ifu_mem_ctl.scala 452:110]
|
|
wire _T_2183 = _T_2173 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_valid_inc_bypass_index = _T_2189 | _T_2183; // @[Mux.scala 27:72]
|
|
wire _T_2213 = _T_2212 & ic_miss_buff_data_valid_inc_bypass_index; // @[el2_ifu_mem_ctl.scala 456:87]
|
|
wire _T_2214 = _T_2208 | _T_2213; // @[el2_ifu_mem_ctl.scala 455:88]
|
|
wire _T_2218 = ic_miss_buff_data_valid_bypass_index & _T_2134; // @[el2_ifu_mem_ctl.scala 457:43]
|
|
wire miss_buff_hit_unq_f = _T_2214 | _T_2218; // @[el2_ifu_mem_ctl.scala 456:131]
|
|
wire _T_2234 = miss_state == 3'h4; // @[el2_ifu_mem_ctl.scala 462:55]
|
|
wire _T_2235 = miss_state == 3'h1; // @[el2_ifu_mem_ctl.scala 462:87]
|
|
wire _T_2236 = _T_2234 | _T_2235; // @[el2_ifu_mem_ctl.scala 462:74]
|
|
wire crit_byp_hit_f = miss_buff_hit_unq_f & _T_2236; // @[el2_ifu_mem_ctl.scala 462:41]
|
|
wire _T_2219 = miss_state == 3'h6; // @[el2_ifu_mem_ctl.scala 459:30]
|
|
reg [30:0] imb_ff; // @[el2_ifu_mem_ctl.scala 313:49]
|
|
wire miss_wrap_f = imb_ff[5] != ifu_fetch_addr_int_f[5]; // @[el2_ifu_mem_ctl.scala 450:51]
|
|
wire _T_2220 = ~miss_wrap_f; // @[el2_ifu_mem_ctl.scala 459:68]
|
|
wire _T_2221 = miss_buff_hit_unq_f & _T_2220; // @[el2_ifu_mem_ctl.scala 459:66]
|
|
wire stream_hit_f = _T_2219 & _T_2221; // @[el2_ifu_mem_ctl.scala 459:43]
|
|
wire _T_215 = crit_byp_hit_f | stream_hit_f; // @[el2_ifu_mem_ctl.scala 280:35]
|
|
wire _T_216 = _T_215 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 280:52]
|
|
wire ic_byp_hit_f = _T_216 & miss_pending; // @[el2_ifu_mem_ctl.scala 280:73]
|
|
reg last_data_recieved_ff; // @[el2_ifu_mem_ctl.scala 604:58]
|
|
wire last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; // @[el2_ifu_mem_ctl.scala 631:35]
|
|
wire _T_32 = bus_ifu_wr_en_ff & last_beat; // @[el2_ifu_mem_ctl.scala 207:113]
|
|
wire _T_33 = last_data_recieved_ff | _T_32; // @[el2_ifu_mem_ctl.scala 207:93]
|
|
wire _T_34 = ic_byp_hit_f & _T_33; // @[el2_ifu_mem_ctl.scala 207:67]
|
|
wire _T_35 = _T_34 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 207:127]
|
|
wire _T_36 = io_dec_tlu_force_halt | _T_35; // @[el2_ifu_mem_ctl.scala 207:51]
|
|
wire _T_38 = ~last_data_recieved_ff; // @[el2_ifu_mem_ctl.scala 208:30]
|
|
wire _T_39 = ic_byp_hit_f & _T_38; // @[el2_ifu_mem_ctl.scala 208:27]
|
|
wire _T_40 = _T_39 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 208:53]
|
|
wire _T_42 = ~ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 209:16]
|
|
wire _T_44 = _T_42 & _T_319; // @[el2_ifu_mem_ctl.scala 209:30]
|
|
wire _T_46 = _T_44 & _T_32; // @[el2_ifu_mem_ctl.scala 209:52]
|
|
wire _T_47 = _T_46 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 209:85]
|
|
wire _T_51 = _T_32 & _T_17; // @[el2_ifu_mem_ctl.scala 210:49]
|
|
wire _T_54 = ic_byp_hit_f & _T_319; // @[el2_ifu_mem_ctl.scala 211:33]
|
|
wire _T_56 = ~_T_32; // @[el2_ifu_mem_ctl.scala 211:57]
|
|
wire _T_57 = _T_54 & _T_56; // @[el2_ifu_mem_ctl.scala 211:55]
|
|
wire ifu_bp_hit_taken_q_f = io_ifu_bp_hit_taken_f & io_ic_hit_f; // @[el2_ifu_mem_ctl.scala 199:52]
|
|
wire _T_58 = ~ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 211:91]
|
|
wire _T_59 = _T_57 & _T_58; // @[el2_ifu_mem_ctl.scala 211:89]
|
|
wire _T_61 = _T_59 & _T_17; // @[el2_ifu_mem_ctl.scala 211:113]
|
|
wire _T_64 = bus_ifu_wr_en_ff & _T_319; // @[el2_ifu_mem_ctl.scala 212:39]
|
|
wire _T_67 = _T_64 & _T_56; // @[el2_ifu_mem_ctl.scala 212:61]
|
|
wire _T_69 = _T_67 & _T_58; // @[el2_ifu_mem_ctl.scala 212:95]
|
|
wire _T_71 = _T_69 & _T_17; // @[el2_ifu_mem_ctl.scala 212:119]
|
|
wire _T_79 = _T_46 & _T_17; // @[el2_ifu_mem_ctl.scala 213:100]
|
|
wire _T_81 = io_exu_flush_final | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 214:44]
|
|
wire _T_84 = _T_81 & _T_56; // @[el2_ifu_mem_ctl.scala 214:68]
|
|
wire [2:0] _T_86 = _T_84 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 214:22]
|
|
wire [2:0] _T_87 = _T_79 ? 3'h0 : _T_86; // @[el2_ifu_mem_ctl.scala 213:20]
|
|
wire [2:0] _T_88 = _T_71 ? 3'h6 : _T_87; // @[el2_ifu_mem_ctl.scala 212:20]
|
|
wire [2:0] _T_89 = _T_61 ? 3'h6 : _T_88; // @[el2_ifu_mem_ctl.scala 211:18]
|
|
wire [2:0] _T_90 = _T_51 ? 3'h0 : _T_89; // @[el2_ifu_mem_ctl.scala 210:16]
|
|
wire [2:0] _T_91 = _T_47 ? 3'h4 : _T_90; // @[el2_ifu_mem_ctl.scala 209:14]
|
|
wire [2:0] _T_92 = _T_40 ? 3'h3 : _T_91; // @[el2_ifu_mem_ctl.scala 208:12]
|
|
wire [2:0] _T_93 = _T_36 ? 3'h0 : _T_92; // @[el2_ifu_mem_ctl.scala 207:27]
|
|
wire _T_102 = 3'h4 == miss_state; // @[Conditional.scala 37:30]
|
|
wire _T_106 = 3'h6 == miss_state; // @[Conditional.scala 37:30]
|
|
wire _T_2231 = byp_fetch_index[4:1] == 4'hf; // @[el2_ifu_mem_ctl.scala 461:60]
|
|
wire _T_2232 = _T_2231 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 461:94]
|
|
wire stream_eol_f = _T_2232 & stream_hit_f; // @[el2_ifu_mem_ctl.scala 461:112]
|
|
wire _T_108 = _T_81 | stream_eol_f; // @[el2_ifu_mem_ctl.scala 222:72]
|
|
wire _T_111 = _T_108 & _T_56; // @[el2_ifu_mem_ctl.scala 222:87]
|
|
wire _T_113 = _T_111 & _T_2573; // @[el2_ifu_mem_ctl.scala 222:122]
|
|
wire [2:0] _T_115 = _T_113 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 222:27]
|
|
wire _T_121 = 3'h3 == miss_state; // @[Conditional.scala 37:30]
|
|
wire _T_124 = io_exu_flush_final & _T_56; // @[el2_ifu_mem_ctl.scala 226:48]
|
|
wire _T_126 = _T_124 & _T_2573; // @[el2_ifu_mem_ctl.scala 226:82]
|
|
wire [2:0] _T_128 = _T_126 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 226:27]
|
|
wire _T_132 = 3'h2 == miss_state; // @[Conditional.scala 37:30]
|
|
wire _T_236 = io_ic_rd_hit == 2'h0; // @[el2_ifu_mem_ctl.scala 286:28]
|
|
wire _T_237 = _T_236 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 286:42]
|
|
wire _T_238 = _T_237 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 286:60]
|
|
wire _T_239 = miss_state == 3'h2; // @[el2_ifu_mem_ctl.scala 286:94]
|
|
wire _T_240 = _T_238 & _T_239; // @[el2_ifu_mem_ctl.scala 286:81]
|
|
wire _T_243 = imb_ff[30:5] != ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 287:39]
|
|
wire _T_244 = _T_240 & _T_243; // @[el2_ifu_mem_ctl.scala 286:111]
|
|
wire _T_246 = _T_244 & _T_17; // @[el2_ifu_mem_ctl.scala 287:91]
|
|
reg sel_mb_addr_ff; // @[el2_ifu_mem_ctl.scala 341:51]
|
|
wire _T_247 = ~sel_mb_addr_ff; // @[el2_ifu_mem_ctl.scala 287:116]
|
|
wire _T_248 = _T_246 & _T_247; // @[el2_ifu_mem_ctl.scala 287:114]
|
|
wire ic_miss_under_miss_f = _T_248 & _T_209; // @[el2_ifu_mem_ctl.scala 287:132]
|
|
wire _T_135 = ic_miss_under_miss_f & _T_56; // @[el2_ifu_mem_ctl.scala 230:50]
|
|
wire _T_137 = _T_135 & _T_2573; // @[el2_ifu_mem_ctl.scala 230:84]
|
|
wire _T_256 = _T_230 & _T_239; // @[el2_ifu_mem_ctl.scala 288:85]
|
|
wire _T_259 = imb_ff[30:5] == ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 289:39]
|
|
wire _T_260 = _T_259 | uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 289:91]
|
|
wire ic_ignore_2nd_miss_f = _T_256 & _T_260; // @[el2_ifu_mem_ctl.scala 288:117]
|
|
wire _T_141 = ic_ignore_2nd_miss_f & _T_56; // @[el2_ifu_mem_ctl.scala 231:35]
|
|
wire _T_143 = _T_141 & _T_2573; // @[el2_ifu_mem_ctl.scala 231:69]
|
|
wire [2:0] _T_145 = _T_143 ? 3'h7 : 3'h0; // @[el2_ifu_mem_ctl.scala 231:12]
|
|
wire [2:0] _T_146 = _T_137 ? 3'h5 : _T_145; // @[el2_ifu_mem_ctl.scala 230:27]
|
|
wire _T_151 = 3'h5 == miss_state; // @[Conditional.scala 37:30]
|
|
wire [2:0] _T_154 = _T_32 ? 3'h0 : 3'h2; // @[el2_ifu_mem_ctl.scala 236:12]
|
|
wire [2:0] _T_155 = io_exu_flush_final ? _T_154 : 3'h1; // @[el2_ifu_mem_ctl.scala 235:62]
|
|
wire [2:0] _T_156 = io_dec_tlu_force_halt ? 3'h0 : _T_155; // @[el2_ifu_mem_ctl.scala 235:27]
|
|
wire _T_160 = 3'h7 == miss_state; // @[Conditional.scala 37:30]
|
|
wire [2:0] _T_164 = io_exu_flush_final ? _T_154 : 3'h0; // @[el2_ifu_mem_ctl.scala 240:62]
|
|
wire [2:0] _T_165 = io_dec_tlu_force_halt ? 3'h0 : _T_164; // @[el2_ifu_mem_ctl.scala 240:27]
|
|
wire [2:0] _GEN_0 = _T_160 ? _T_165 : 3'h0; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_2 = _T_151 ? _T_156 : _GEN_0; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_4 = _T_132 ? _T_146 : _GEN_2; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_6 = _T_121 ? _T_128 : _GEN_4; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_8 = _T_106 ? _T_115 : _GEN_6; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_10 = _T_102 ? 3'h0 : _GEN_8; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_12 = _T_31 ? _T_93 : _GEN_10; // @[Conditional.scala 39:67]
|
|
wire [2:0] miss_nxtstate = _T_24 ? _T_28 : _GEN_12; // @[Conditional.scala 40:58]
|
|
wire _T_20 = miss_nxtstate == 3'h5; // @[el2_ifu_mem_ctl.scala 197:73]
|
|
wire _T_21 = _T_19 | _T_20; // @[el2_ifu_mem_ctl.scala 197:57]
|
|
wire _T_22 = _T_18 & _T_21; // @[el2_ifu_mem_ctl.scala 197:26]
|
|
wire _T_30 = ic_act_miss_f & _T_2573; // @[el2_ifu_mem_ctl.scala 204:38]
|
|
wire _T_94 = io_dec_tlu_force_halt | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 215:46]
|
|
wire _T_95 = _T_94 | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 215:67]
|
|
wire _T_96 = _T_95 | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 215:82]
|
|
wire _T_98 = _T_96 | _T_32; // @[el2_ifu_mem_ctl.scala 215:105]
|
|
wire _T_100 = bus_ifu_wr_en_ff & _T_17; // @[el2_ifu_mem_ctl.scala 215:158]
|
|
wire _T_101 = _T_98 | _T_100; // @[el2_ifu_mem_ctl.scala 215:138]
|
|
wire _T_103 = io_exu_flush_final | flush_final_f; // @[el2_ifu_mem_ctl.scala 219:43]
|
|
wire _T_104 = _T_103 | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 219:59]
|
|
wire _T_105 = _T_104 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 219:74]
|
|
wire _T_119 = _T_108 | _T_32; // @[el2_ifu_mem_ctl.scala 223:84]
|
|
wire _T_120 = _T_119 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 223:118]
|
|
wire _T_130 = io_exu_flush_final | _T_32; // @[el2_ifu_mem_ctl.scala 227:43]
|
|
wire _T_131 = _T_130 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 227:76]
|
|
wire _T_148 = _T_32 | ic_miss_under_miss_f; // @[el2_ifu_mem_ctl.scala 232:55]
|
|
wire _T_149 = _T_148 | ic_ignore_2nd_miss_f; // @[el2_ifu_mem_ctl.scala 232:78]
|
|
wire _T_150 = _T_149 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 232:101]
|
|
wire _T_158 = _T_32 | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 237:55]
|
|
wire _T_159 = _T_158 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 237:76]
|
|
wire _GEN_1 = _T_160 & _T_159; // @[Conditional.scala 39:67]
|
|
wire _GEN_3 = _T_151 ? _T_159 : _GEN_1; // @[Conditional.scala 39:67]
|
|
wire _GEN_5 = _T_132 ? _T_150 : _GEN_3; // @[Conditional.scala 39:67]
|
|
wire _GEN_7 = _T_121 ? _T_131 : _GEN_5; // @[Conditional.scala 39:67]
|
|
wire _GEN_9 = _T_106 ? _T_120 : _GEN_7; // @[Conditional.scala 39:67]
|
|
wire _GEN_11 = _T_102 ? _T_105 : _GEN_9; // @[Conditional.scala 39:67]
|
|
wire _GEN_13 = _T_31 ? _T_101 : _GEN_11; // @[Conditional.scala 39:67]
|
|
wire miss_state_en = _T_24 ? _T_30 : _GEN_13; // @[Conditional.scala 40:58]
|
|
wire _T_174 = ~flush_final_f; // @[el2_ifu_mem_ctl.scala 256:95]
|
|
wire _T_175 = _T_2234 & _T_174; // @[el2_ifu_mem_ctl.scala 256:93]
|
|
wire crit_wd_byp_ok_ff = _T_2235 | _T_175; // @[el2_ifu_mem_ctl.scala 256:58]
|
|
wire _T_178 = miss_pending & _T_56; // @[el2_ifu_mem_ctl.scala 257:36]
|
|
wire _T_180 = _T_2234 & io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 257:106]
|
|
wire _T_181 = ~_T_180; // @[el2_ifu_mem_ctl.scala 257:72]
|
|
wire _T_182 = _T_178 & _T_181; // @[el2_ifu_mem_ctl.scala 257:70]
|
|
wire _T_184 = _T_2234 & crit_byp_hit_f; // @[el2_ifu_mem_ctl.scala 258:57]
|
|
wire _T_185 = ~_T_184; // @[el2_ifu_mem_ctl.scala 258:23]
|
|
wire _T_186 = _T_182 & _T_185; // @[el2_ifu_mem_ctl.scala 257:128]
|
|
wire _T_187 = _T_186 | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 258:77]
|
|
wire _T_188 = miss_nxtstate == 3'h4; // @[el2_ifu_mem_ctl.scala 259:36]
|
|
wire _T_189 = miss_pending & _T_188; // @[el2_ifu_mem_ctl.scala 259:19]
|
|
wire sel_hold_imb = _T_187 | _T_189; // @[el2_ifu_mem_ctl.scala 258:93]
|
|
wire _T_191 = _T_19 | ic_miss_under_miss_f; // @[el2_ifu_mem_ctl.scala 261:57]
|
|
wire sel_hold_imb_scnd = _T_191 & _T_174; // @[el2_ifu_mem_ctl.scala 261:81]
|
|
reg way_status_mb_scnd_ff; // @[el2_ifu_mem_ctl.scala 269:64]
|
|
reg [6:0] ifu_ic_rw_int_addr_ff; // @[el2_ifu_mem_ctl.scala 738:14]
|
|
wire _T_4619 = ifu_ic_rw_int_addr_ff == 7'h0; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_0; // @[Reg.scala 27:20]
|
|
wire _T_4747 = _T_4619 & way_status_out_0; // @[Mux.scala 27:72]
|
|
wire _T_4620 = ifu_ic_rw_int_addr_ff == 7'h1; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_1; // @[Reg.scala 27:20]
|
|
wire _T_4748 = _T_4620 & way_status_out_1; // @[Mux.scala 27:72]
|
|
wire _T_4875 = _T_4747 | _T_4748; // @[Mux.scala 27:72]
|
|
wire _T_4621 = ifu_ic_rw_int_addr_ff == 7'h2; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_2; // @[Reg.scala 27:20]
|
|
wire _T_4749 = _T_4621 & way_status_out_2; // @[Mux.scala 27:72]
|
|
wire _T_4876 = _T_4875 | _T_4749; // @[Mux.scala 27:72]
|
|
wire _T_4622 = ifu_ic_rw_int_addr_ff == 7'h3; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_3; // @[Reg.scala 27:20]
|
|
wire _T_4750 = _T_4622 & way_status_out_3; // @[Mux.scala 27:72]
|
|
wire _T_4877 = _T_4876 | _T_4750; // @[Mux.scala 27:72]
|
|
wire _T_4623 = ifu_ic_rw_int_addr_ff == 7'h4; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_4; // @[Reg.scala 27:20]
|
|
wire _T_4751 = _T_4623 & way_status_out_4; // @[Mux.scala 27:72]
|
|
wire _T_4878 = _T_4877 | _T_4751; // @[Mux.scala 27:72]
|
|
wire _T_4624 = ifu_ic_rw_int_addr_ff == 7'h5; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_5; // @[Reg.scala 27:20]
|
|
wire _T_4752 = _T_4624 & way_status_out_5; // @[Mux.scala 27:72]
|
|
wire _T_4879 = _T_4878 | _T_4752; // @[Mux.scala 27:72]
|
|
wire _T_4625 = ifu_ic_rw_int_addr_ff == 7'h6; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_6; // @[Reg.scala 27:20]
|
|
wire _T_4753 = _T_4625 & way_status_out_6; // @[Mux.scala 27:72]
|
|
wire _T_4880 = _T_4879 | _T_4753; // @[Mux.scala 27:72]
|
|
wire _T_4626 = ifu_ic_rw_int_addr_ff == 7'h7; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_7; // @[Reg.scala 27:20]
|
|
wire _T_4754 = _T_4626 & way_status_out_7; // @[Mux.scala 27:72]
|
|
wire _T_4881 = _T_4880 | _T_4754; // @[Mux.scala 27:72]
|
|
wire _T_4627 = ifu_ic_rw_int_addr_ff == 7'h8; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_8; // @[Reg.scala 27:20]
|
|
wire _T_4755 = _T_4627 & way_status_out_8; // @[Mux.scala 27:72]
|
|
wire _T_4882 = _T_4881 | _T_4755; // @[Mux.scala 27:72]
|
|
wire _T_4628 = ifu_ic_rw_int_addr_ff == 7'h9; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_9; // @[Reg.scala 27:20]
|
|
wire _T_4756 = _T_4628 & way_status_out_9; // @[Mux.scala 27:72]
|
|
wire _T_4883 = _T_4882 | _T_4756; // @[Mux.scala 27:72]
|
|
wire _T_4629 = ifu_ic_rw_int_addr_ff == 7'ha; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_10; // @[Reg.scala 27:20]
|
|
wire _T_4757 = _T_4629 & way_status_out_10; // @[Mux.scala 27:72]
|
|
wire _T_4884 = _T_4883 | _T_4757; // @[Mux.scala 27:72]
|
|
wire _T_4630 = ifu_ic_rw_int_addr_ff == 7'hb; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_11; // @[Reg.scala 27:20]
|
|
wire _T_4758 = _T_4630 & way_status_out_11; // @[Mux.scala 27:72]
|
|
wire _T_4885 = _T_4884 | _T_4758; // @[Mux.scala 27:72]
|
|
wire _T_4631 = ifu_ic_rw_int_addr_ff == 7'hc; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_12; // @[Reg.scala 27:20]
|
|
wire _T_4759 = _T_4631 & way_status_out_12; // @[Mux.scala 27:72]
|
|
wire _T_4886 = _T_4885 | _T_4759; // @[Mux.scala 27:72]
|
|
wire _T_4632 = ifu_ic_rw_int_addr_ff == 7'hd; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_13; // @[Reg.scala 27:20]
|
|
wire _T_4760 = _T_4632 & way_status_out_13; // @[Mux.scala 27:72]
|
|
wire _T_4887 = _T_4886 | _T_4760; // @[Mux.scala 27:72]
|
|
wire _T_4633 = ifu_ic_rw_int_addr_ff == 7'he; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_14; // @[Reg.scala 27:20]
|
|
wire _T_4761 = _T_4633 & way_status_out_14; // @[Mux.scala 27:72]
|
|
wire _T_4888 = _T_4887 | _T_4761; // @[Mux.scala 27:72]
|
|
wire _T_4634 = ifu_ic_rw_int_addr_ff == 7'hf; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_15; // @[Reg.scala 27:20]
|
|
wire _T_4762 = _T_4634 & way_status_out_15; // @[Mux.scala 27:72]
|
|
wire _T_4889 = _T_4888 | _T_4762; // @[Mux.scala 27:72]
|
|
wire _T_4635 = ifu_ic_rw_int_addr_ff == 7'h10; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_16; // @[Reg.scala 27:20]
|
|
wire _T_4763 = _T_4635 & way_status_out_16; // @[Mux.scala 27:72]
|
|
wire _T_4890 = _T_4889 | _T_4763; // @[Mux.scala 27:72]
|
|
wire _T_4636 = ifu_ic_rw_int_addr_ff == 7'h11; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_17; // @[Reg.scala 27:20]
|
|
wire _T_4764 = _T_4636 & way_status_out_17; // @[Mux.scala 27:72]
|
|
wire _T_4891 = _T_4890 | _T_4764; // @[Mux.scala 27:72]
|
|
wire _T_4637 = ifu_ic_rw_int_addr_ff == 7'h12; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_18; // @[Reg.scala 27:20]
|
|
wire _T_4765 = _T_4637 & way_status_out_18; // @[Mux.scala 27:72]
|
|
wire _T_4892 = _T_4891 | _T_4765; // @[Mux.scala 27:72]
|
|
wire _T_4638 = ifu_ic_rw_int_addr_ff == 7'h13; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_19; // @[Reg.scala 27:20]
|
|
wire _T_4766 = _T_4638 & way_status_out_19; // @[Mux.scala 27:72]
|
|
wire _T_4893 = _T_4892 | _T_4766; // @[Mux.scala 27:72]
|
|
wire _T_4639 = ifu_ic_rw_int_addr_ff == 7'h14; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_20; // @[Reg.scala 27:20]
|
|
wire _T_4767 = _T_4639 & way_status_out_20; // @[Mux.scala 27:72]
|
|
wire _T_4894 = _T_4893 | _T_4767; // @[Mux.scala 27:72]
|
|
wire _T_4640 = ifu_ic_rw_int_addr_ff == 7'h15; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_21; // @[Reg.scala 27:20]
|
|
wire _T_4768 = _T_4640 & way_status_out_21; // @[Mux.scala 27:72]
|
|
wire _T_4895 = _T_4894 | _T_4768; // @[Mux.scala 27:72]
|
|
wire _T_4641 = ifu_ic_rw_int_addr_ff == 7'h16; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_22; // @[Reg.scala 27:20]
|
|
wire _T_4769 = _T_4641 & way_status_out_22; // @[Mux.scala 27:72]
|
|
wire _T_4896 = _T_4895 | _T_4769; // @[Mux.scala 27:72]
|
|
wire _T_4642 = ifu_ic_rw_int_addr_ff == 7'h17; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_23; // @[Reg.scala 27:20]
|
|
wire _T_4770 = _T_4642 & way_status_out_23; // @[Mux.scala 27:72]
|
|
wire _T_4897 = _T_4896 | _T_4770; // @[Mux.scala 27:72]
|
|
wire _T_4643 = ifu_ic_rw_int_addr_ff == 7'h18; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_24; // @[Reg.scala 27:20]
|
|
wire _T_4771 = _T_4643 & way_status_out_24; // @[Mux.scala 27:72]
|
|
wire _T_4898 = _T_4897 | _T_4771; // @[Mux.scala 27:72]
|
|
wire _T_4644 = ifu_ic_rw_int_addr_ff == 7'h19; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_25; // @[Reg.scala 27:20]
|
|
wire _T_4772 = _T_4644 & way_status_out_25; // @[Mux.scala 27:72]
|
|
wire _T_4899 = _T_4898 | _T_4772; // @[Mux.scala 27:72]
|
|
wire _T_4645 = ifu_ic_rw_int_addr_ff == 7'h1a; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_26; // @[Reg.scala 27:20]
|
|
wire _T_4773 = _T_4645 & way_status_out_26; // @[Mux.scala 27:72]
|
|
wire _T_4900 = _T_4899 | _T_4773; // @[Mux.scala 27:72]
|
|
wire _T_4646 = ifu_ic_rw_int_addr_ff == 7'h1b; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_27; // @[Reg.scala 27:20]
|
|
wire _T_4774 = _T_4646 & way_status_out_27; // @[Mux.scala 27:72]
|
|
wire _T_4901 = _T_4900 | _T_4774; // @[Mux.scala 27:72]
|
|
wire _T_4647 = ifu_ic_rw_int_addr_ff == 7'h1c; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_28; // @[Reg.scala 27:20]
|
|
wire _T_4775 = _T_4647 & way_status_out_28; // @[Mux.scala 27:72]
|
|
wire _T_4902 = _T_4901 | _T_4775; // @[Mux.scala 27:72]
|
|
wire _T_4648 = ifu_ic_rw_int_addr_ff == 7'h1d; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_29; // @[Reg.scala 27:20]
|
|
wire _T_4776 = _T_4648 & way_status_out_29; // @[Mux.scala 27:72]
|
|
wire _T_4903 = _T_4902 | _T_4776; // @[Mux.scala 27:72]
|
|
wire _T_4649 = ifu_ic_rw_int_addr_ff == 7'h1e; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_30; // @[Reg.scala 27:20]
|
|
wire _T_4777 = _T_4649 & way_status_out_30; // @[Mux.scala 27:72]
|
|
wire _T_4904 = _T_4903 | _T_4777; // @[Mux.scala 27:72]
|
|
wire _T_4650 = ifu_ic_rw_int_addr_ff == 7'h1f; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_31; // @[Reg.scala 27:20]
|
|
wire _T_4778 = _T_4650 & way_status_out_31; // @[Mux.scala 27:72]
|
|
wire _T_4905 = _T_4904 | _T_4778; // @[Mux.scala 27:72]
|
|
wire _T_4651 = ifu_ic_rw_int_addr_ff == 7'h20; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_32; // @[Reg.scala 27:20]
|
|
wire _T_4779 = _T_4651 & way_status_out_32; // @[Mux.scala 27:72]
|
|
wire _T_4906 = _T_4905 | _T_4779; // @[Mux.scala 27:72]
|
|
wire _T_4652 = ifu_ic_rw_int_addr_ff == 7'h21; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_33; // @[Reg.scala 27:20]
|
|
wire _T_4780 = _T_4652 & way_status_out_33; // @[Mux.scala 27:72]
|
|
wire _T_4907 = _T_4906 | _T_4780; // @[Mux.scala 27:72]
|
|
wire _T_4653 = ifu_ic_rw_int_addr_ff == 7'h22; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_34; // @[Reg.scala 27:20]
|
|
wire _T_4781 = _T_4653 & way_status_out_34; // @[Mux.scala 27:72]
|
|
wire _T_4908 = _T_4907 | _T_4781; // @[Mux.scala 27:72]
|
|
wire _T_4654 = ifu_ic_rw_int_addr_ff == 7'h23; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_35; // @[Reg.scala 27:20]
|
|
wire _T_4782 = _T_4654 & way_status_out_35; // @[Mux.scala 27:72]
|
|
wire _T_4909 = _T_4908 | _T_4782; // @[Mux.scala 27:72]
|
|
wire _T_4655 = ifu_ic_rw_int_addr_ff == 7'h24; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_36; // @[Reg.scala 27:20]
|
|
wire _T_4783 = _T_4655 & way_status_out_36; // @[Mux.scala 27:72]
|
|
wire _T_4910 = _T_4909 | _T_4783; // @[Mux.scala 27:72]
|
|
wire _T_4656 = ifu_ic_rw_int_addr_ff == 7'h25; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_37; // @[Reg.scala 27:20]
|
|
wire _T_4784 = _T_4656 & way_status_out_37; // @[Mux.scala 27:72]
|
|
wire _T_4911 = _T_4910 | _T_4784; // @[Mux.scala 27:72]
|
|
wire _T_4657 = ifu_ic_rw_int_addr_ff == 7'h26; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_38; // @[Reg.scala 27:20]
|
|
wire _T_4785 = _T_4657 & way_status_out_38; // @[Mux.scala 27:72]
|
|
wire _T_4912 = _T_4911 | _T_4785; // @[Mux.scala 27:72]
|
|
wire _T_4658 = ifu_ic_rw_int_addr_ff == 7'h27; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_39; // @[Reg.scala 27:20]
|
|
wire _T_4786 = _T_4658 & way_status_out_39; // @[Mux.scala 27:72]
|
|
wire _T_4913 = _T_4912 | _T_4786; // @[Mux.scala 27:72]
|
|
wire _T_4659 = ifu_ic_rw_int_addr_ff == 7'h28; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_40; // @[Reg.scala 27:20]
|
|
wire _T_4787 = _T_4659 & way_status_out_40; // @[Mux.scala 27:72]
|
|
wire _T_4914 = _T_4913 | _T_4787; // @[Mux.scala 27:72]
|
|
wire _T_4660 = ifu_ic_rw_int_addr_ff == 7'h29; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_41; // @[Reg.scala 27:20]
|
|
wire _T_4788 = _T_4660 & way_status_out_41; // @[Mux.scala 27:72]
|
|
wire _T_4915 = _T_4914 | _T_4788; // @[Mux.scala 27:72]
|
|
wire _T_4661 = ifu_ic_rw_int_addr_ff == 7'h2a; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_42; // @[Reg.scala 27:20]
|
|
wire _T_4789 = _T_4661 & way_status_out_42; // @[Mux.scala 27:72]
|
|
wire _T_4916 = _T_4915 | _T_4789; // @[Mux.scala 27:72]
|
|
wire _T_4662 = ifu_ic_rw_int_addr_ff == 7'h2b; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_43; // @[Reg.scala 27:20]
|
|
wire _T_4790 = _T_4662 & way_status_out_43; // @[Mux.scala 27:72]
|
|
wire _T_4917 = _T_4916 | _T_4790; // @[Mux.scala 27:72]
|
|
wire _T_4663 = ifu_ic_rw_int_addr_ff == 7'h2c; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_44; // @[Reg.scala 27:20]
|
|
wire _T_4791 = _T_4663 & way_status_out_44; // @[Mux.scala 27:72]
|
|
wire _T_4918 = _T_4917 | _T_4791; // @[Mux.scala 27:72]
|
|
wire _T_4664 = ifu_ic_rw_int_addr_ff == 7'h2d; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_45; // @[Reg.scala 27:20]
|
|
wire _T_4792 = _T_4664 & way_status_out_45; // @[Mux.scala 27:72]
|
|
wire _T_4919 = _T_4918 | _T_4792; // @[Mux.scala 27:72]
|
|
wire _T_4665 = ifu_ic_rw_int_addr_ff == 7'h2e; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_46; // @[Reg.scala 27:20]
|
|
wire _T_4793 = _T_4665 & way_status_out_46; // @[Mux.scala 27:72]
|
|
wire _T_4920 = _T_4919 | _T_4793; // @[Mux.scala 27:72]
|
|
wire _T_4666 = ifu_ic_rw_int_addr_ff == 7'h2f; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_47; // @[Reg.scala 27:20]
|
|
wire _T_4794 = _T_4666 & way_status_out_47; // @[Mux.scala 27:72]
|
|
wire _T_4921 = _T_4920 | _T_4794; // @[Mux.scala 27:72]
|
|
wire _T_4667 = ifu_ic_rw_int_addr_ff == 7'h30; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_48; // @[Reg.scala 27:20]
|
|
wire _T_4795 = _T_4667 & way_status_out_48; // @[Mux.scala 27:72]
|
|
wire _T_4922 = _T_4921 | _T_4795; // @[Mux.scala 27:72]
|
|
wire _T_4668 = ifu_ic_rw_int_addr_ff == 7'h31; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_49; // @[Reg.scala 27:20]
|
|
wire _T_4796 = _T_4668 & way_status_out_49; // @[Mux.scala 27:72]
|
|
wire _T_4923 = _T_4922 | _T_4796; // @[Mux.scala 27:72]
|
|
wire _T_4669 = ifu_ic_rw_int_addr_ff == 7'h32; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_50; // @[Reg.scala 27:20]
|
|
wire _T_4797 = _T_4669 & way_status_out_50; // @[Mux.scala 27:72]
|
|
wire _T_4924 = _T_4923 | _T_4797; // @[Mux.scala 27:72]
|
|
wire _T_4670 = ifu_ic_rw_int_addr_ff == 7'h33; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_51; // @[Reg.scala 27:20]
|
|
wire _T_4798 = _T_4670 & way_status_out_51; // @[Mux.scala 27:72]
|
|
wire _T_4925 = _T_4924 | _T_4798; // @[Mux.scala 27:72]
|
|
wire _T_4671 = ifu_ic_rw_int_addr_ff == 7'h34; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_52; // @[Reg.scala 27:20]
|
|
wire _T_4799 = _T_4671 & way_status_out_52; // @[Mux.scala 27:72]
|
|
wire _T_4926 = _T_4925 | _T_4799; // @[Mux.scala 27:72]
|
|
wire _T_4672 = ifu_ic_rw_int_addr_ff == 7'h35; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_53; // @[Reg.scala 27:20]
|
|
wire _T_4800 = _T_4672 & way_status_out_53; // @[Mux.scala 27:72]
|
|
wire _T_4927 = _T_4926 | _T_4800; // @[Mux.scala 27:72]
|
|
wire _T_4673 = ifu_ic_rw_int_addr_ff == 7'h36; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_54; // @[Reg.scala 27:20]
|
|
wire _T_4801 = _T_4673 & way_status_out_54; // @[Mux.scala 27:72]
|
|
wire _T_4928 = _T_4927 | _T_4801; // @[Mux.scala 27:72]
|
|
wire _T_4674 = ifu_ic_rw_int_addr_ff == 7'h37; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_55; // @[Reg.scala 27:20]
|
|
wire _T_4802 = _T_4674 & way_status_out_55; // @[Mux.scala 27:72]
|
|
wire _T_4929 = _T_4928 | _T_4802; // @[Mux.scala 27:72]
|
|
wire _T_4675 = ifu_ic_rw_int_addr_ff == 7'h38; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_56; // @[Reg.scala 27:20]
|
|
wire _T_4803 = _T_4675 & way_status_out_56; // @[Mux.scala 27:72]
|
|
wire _T_4930 = _T_4929 | _T_4803; // @[Mux.scala 27:72]
|
|
wire _T_4676 = ifu_ic_rw_int_addr_ff == 7'h39; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_57; // @[Reg.scala 27:20]
|
|
wire _T_4804 = _T_4676 & way_status_out_57; // @[Mux.scala 27:72]
|
|
wire _T_4931 = _T_4930 | _T_4804; // @[Mux.scala 27:72]
|
|
wire _T_4677 = ifu_ic_rw_int_addr_ff == 7'h3a; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_58; // @[Reg.scala 27:20]
|
|
wire _T_4805 = _T_4677 & way_status_out_58; // @[Mux.scala 27:72]
|
|
wire _T_4932 = _T_4931 | _T_4805; // @[Mux.scala 27:72]
|
|
wire _T_4678 = ifu_ic_rw_int_addr_ff == 7'h3b; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_59; // @[Reg.scala 27:20]
|
|
wire _T_4806 = _T_4678 & way_status_out_59; // @[Mux.scala 27:72]
|
|
wire _T_4933 = _T_4932 | _T_4806; // @[Mux.scala 27:72]
|
|
wire _T_4679 = ifu_ic_rw_int_addr_ff == 7'h3c; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_60; // @[Reg.scala 27:20]
|
|
wire _T_4807 = _T_4679 & way_status_out_60; // @[Mux.scala 27:72]
|
|
wire _T_4934 = _T_4933 | _T_4807; // @[Mux.scala 27:72]
|
|
wire _T_4680 = ifu_ic_rw_int_addr_ff == 7'h3d; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_61; // @[Reg.scala 27:20]
|
|
wire _T_4808 = _T_4680 & way_status_out_61; // @[Mux.scala 27:72]
|
|
wire _T_4935 = _T_4934 | _T_4808; // @[Mux.scala 27:72]
|
|
wire _T_4681 = ifu_ic_rw_int_addr_ff == 7'h3e; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_62; // @[Reg.scala 27:20]
|
|
wire _T_4809 = _T_4681 & way_status_out_62; // @[Mux.scala 27:72]
|
|
wire _T_4936 = _T_4935 | _T_4809; // @[Mux.scala 27:72]
|
|
wire _T_4682 = ifu_ic_rw_int_addr_ff == 7'h3f; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_63; // @[Reg.scala 27:20]
|
|
wire _T_4810 = _T_4682 & way_status_out_63; // @[Mux.scala 27:72]
|
|
wire _T_4937 = _T_4936 | _T_4810; // @[Mux.scala 27:72]
|
|
wire _T_4683 = ifu_ic_rw_int_addr_ff == 7'h40; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_64; // @[Reg.scala 27:20]
|
|
wire _T_4811 = _T_4683 & way_status_out_64; // @[Mux.scala 27:72]
|
|
wire _T_4938 = _T_4937 | _T_4811; // @[Mux.scala 27:72]
|
|
wire _T_4684 = ifu_ic_rw_int_addr_ff == 7'h41; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_65; // @[Reg.scala 27:20]
|
|
wire _T_4812 = _T_4684 & way_status_out_65; // @[Mux.scala 27:72]
|
|
wire _T_4939 = _T_4938 | _T_4812; // @[Mux.scala 27:72]
|
|
wire _T_4685 = ifu_ic_rw_int_addr_ff == 7'h42; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_66; // @[Reg.scala 27:20]
|
|
wire _T_4813 = _T_4685 & way_status_out_66; // @[Mux.scala 27:72]
|
|
wire _T_4940 = _T_4939 | _T_4813; // @[Mux.scala 27:72]
|
|
wire _T_4686 = ifu_ic_rw_int_addr_ff == 7'h43; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_67; // @[Reg.scala 27:20]
|
|
wire _T_4814 = _T_4686 & way_status_out_67; // @[Mux.scala 27:72]
|
|
wire _T_4941 = _T_4940 | _T_4814; // @[Mux.scala 27:72]
|
|
wire _T_4687 = ifu_ic_rw_int_addr_ff == 7'h44; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_68; // @[Reg.scala 27:20]
|
|
wire _T_4815 = _T_4687 & way_status_out_68; // @[Mux.scala 27:72]
|
|
wire _T_4942 = _T_4941 | _T_4815; // @[Mux.scala 27:72]
|
|
wire _T_4688 = ifu_ic_rw_int_addr_ff == 7'h45; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_69; // @[Reg.scala 27:20]
|
|
wire _T_4816 = _T_4688 & way_status_out_69; // @[Mux.scala 27:72]
|
|
wire _T_4943 = _T_4942 | _T_4816; // @[Mux.scala 27:72]
|
|
wire _T_4689 = ifu_ic_rw_int_addr_ff == 7'h46; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_70; // @[Reg.scala 27:20]
|
|
wire _T_4817 = _T_4689 & way_status_out_70; // @[Mux.scala 27:72]
|
|
wire _T_4944 = _T_4943 | _T_4817; // @[Mux.scala 27:72]
|
|
wire _T_4690 = ifu_ic_rw_int_addr_ff == 7'h47; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_71; // @[Reg.scala 27:20]
|
|
wire _T_4818 = _T_4690 & way_status_out_71; // @[Mux.scala 27:72]
|
|
wire _T_4945 = _T_4944 | _T_4818; // @[Mux.scala 27:72]
|
|
wire _T_4691 = ifu_ic_rw_int_addr_ff == 7'h48; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_72; // @[Reg.scala 27:20]
|
|
wire _T_4819 = _T_4691 & way_status_out_72; // @[Mux.scala 27:72]
|
|
wire _T_4946 = _T_4945 | _T_4819; // @[Mux.scala 27:72]
|
|
wire _T_4692 = ifu_ic_rw_int_addr_ff == 7'h49; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_73; // @[Reg.scala 27:20]
|
|
wire _T_4820 = _T_4692 & way_status_out_73; // @[Mux.scala 27:72]
|
|
wire _T_4947 = _T_4946 | _T_4820; // @[Mux.scala 27:72]
|
|
wire _T_4693 = ifu_ic_rw_int_addr_ff == 7'h4a; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_74; // @[Reg.scala 27:20]
|
|
wire _T_4821 = _T_4693 & way_status_out_74; // @[Mux.scala 27:72]
|
|
wire _T_4948 = _T_4947 | _T_4821; // @[Mux.scala 27:72]
|
|
wire _T_4694 = ifu_ic_rw_int_addr_ff == 7'h4b; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_75; // @[Reg.scala 27:20]
|
|
wire _T_4822 = _T_4694 & way_status_out_75; // @[Mux.scala 27:72]
|
|
wire _T_4949 = _T_4948 | _T_4822; // @[Mux.scala 27:72]
|
|
wire _T_4695 = ifu_ic_rw_int_addr_ff == 7'h4c; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_76; // @[Reg.scala 27:20]
|
|
wire _T_4823 = _T_4695 & way_status_out_76; // @[Mux.scala 27:72]
|
|
wire _T_4950 = _T_4949 | _T_4823; // @[Mux.scala 27:72]
|
|
wire _T_4696 = ifu_ic_rw_int_addr_ff == 7'h4d; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_77; // @[Reg.scala 27:20]
|
|
wire _T_4824 = _T_4696 & way_status_out_77; // @[Mux.scala 27:72]
|
|
wire _T_4951 = _T_4950 | _T_4824; // @[Mux.scala 27:72]
|
|
wire _T_4697 = ifu_ic_rw_int_addr_ff == 7'h4e; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_78; // @[Reg.scala 27:20]
|
|
wire _T_4825 = _T_4697 & way_status_out_78; // @[Mux.scala 27:72]
|
|
wire _T_4952 = _T_4951 | _T_4825; // @[Mux.scala 27:72]
|
|
wire _T_4698 = ifu_ic_rw_int_addr_ff == 7'h4f; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_79; // @[Reg.scala 27:20]
|
|
wire _T_4826 = _T_4698 & way_status_out_79; // @[Mux.scala 27:72]
|
|
wire _T_4953 = _T_4952 | _T_4826; // @[Mux.scala 27:72]
|
|
wire _T_4699 = ifu_ic_rw_int_addr_ff == 7'h50; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_80; // @[Reg.scala 27:20]
|
|
wire _T_4827 = _T_4699 & way_status_out_80; // @[Mux.scala 27:72]
|
|
wire _T_4954 = _T_4953 | _T_4827; // @[Mux.scala 27:72]
|
|
wire _T_4700 = ifu_ic_rw_int_addr_ff == 7'h51; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_81; // @[Reg.scala 27:20]
|
|
wire _T_4828 = _T_4700 & way_status_out_81; // @[Mux.scala 27:72]
|
|
wire _T_4955 = _T_4954 | _T_4828; // @[Mux.scala 27:72]
|
|
wire _T_4701 = ifu_ic_rw_int_addr_ff == 7'h52; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_82; // @[Reg.scala 27:20]
|
|
wire _T_4829 = _T_4701 & way_status_out_82; // @[Mux.scala 27:72]
|
|
wire _T_4956 = _T_4955 | _T_4829; // @[Mux.scala 27:72]
|
|
wire _T_4702 = ifu_ic_rw_int_addr_ff == 7'h53; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_83; // @[Reg.scala 27:20]
|
|
wire _T_4830 = _T_4702 & way_status_out_83; // @[Mux.scala 27:72]
|
|
wire _T_4957 = _T_4956 | _T_4830; // @[Mux.scala 27:72]
|
|
wire _T_4703 = ifu_ic_rw_int_addr_ff == 7'h54; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_84; // @[Reg.scala 27:20]
|
|
wire _T_4831 = _T_4703 & way_status_out_84; // @[Mux.scala 27:72]
|
|
wire _T_4958 = _T_4957 | _T_4831; // @[Mux.scala 27:72]
|
|
wire _T_4704 = ifu_ic_rw_int_addr_ff == 7'h55; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_85; // @[Reg.scala 27:20]
|
|
wire _T_4832 = _T_4704 & way_status_out_85; // @[Mux.scala 27:72]
|
|
wire _T_4959 = _T_4958 | _T_4832; // @[Mux.scala 27:72]
|
|
wire _T_4705 = ifu_ic_rw_int_addr_ff == 7'h56; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_86; // @[Reg.scala 27:20]
|
|
wire _T_4833 = _T_4705 & way_status_out_86; // @[Mux.scala 27:72]
|
|
wire _T_4960 = _T_4959 | _T_4833; // @[Mux.scala 27:72]
|
|
wire _T_4706 = ifu_ic_rw_int_addr_ff == 7'h57; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_87; // @[Reg.scala 27:20]
|
|
wire _T_4834 = _T_4706 & way_status_out_87; // @[Mux.scala 27:72]
|
|
wire _T_4961 = _T_4960 | _T_4834; // @[Mux.scala 27:72]
|
|
wire _T_4707 = ifu_ic_rw_int_addr_ff == 7'h58; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_88; // @[Reg.scala 27:20]
|
|
wire _T_4835 = _T_4707 & way_status_out_88; // @[Mux.scala 27:72]
|
|
wire _T_4962 = _T_4961 | _T_4835; // @[Mux.scala 27:72]
|
|
wire _T_4708 = ifu_ic_rw_int_addr_ff == 7'h59; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_89; // @[Reg.scala 27:20]
|
|
wire _T_4836 = _T_4708 & way_status_out_89; // @[Mux.scala 27:72]
|
|
wire _T_4963 = _T_4962 | _T_4836; // @[Mux.scala 27:72]
|
|
wire _T_4709 = ifu_ic_rw_int_addr_ff == 7'h5a; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_90; // @[Reg.scala 27:20]
|
|
wire _T_4837 = _T_4709 & way_status_out_90; // @[Mux.scala 27:72]
|
|
wire _T_4964 = _T_4963 | _T_4837; // @[Mux.scala 27:72]
|
|
wire _T_4710 = ifu_ic_rw_int_addr_ff == 7'h5b; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_91; // @[Reg.scala 27:20]
|
|
wire _T_4838 = _T_4710 & way_status_out_91; // @[Mux.scala 27:72]
|
|
wire _T_4965 = _T_4964 | _T_4838; // @[Mux.scala 27:72]
|
|
wire _T_4711 = ifu_ic_rw_int_addr_ff == 7'h5c; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_92; // @[Reg.scala 27:20]
|
|
wire _T_4839 = _T_4711 & way_status_out_92; // @[Mux.scala 27:72]
|
|
wire _T_4966 = _T_4965 | _T_4839; // @[Mux.scala 27:72]
|
|
wire _T_4712 = ifu_ic_rw_int_addr_ff == 7'h5d; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_93; // @[Reg.scala 27:20]
|
|
wire _T_4840 = _T_4712 & way_status_out_93; // @[Mux.scala 27:72]
|
|
wire _T_4967 = _T_4966 | _T_4840; // @[Mux.scala 27:72]
|
|
wire _T_4713 = ifu_ic_rw_int_addr_ff == 7'h5e; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_94; // @[Reg.scala 27:20]
|
|
wire _T_4841 = _T_4713 & way_status_out_94; // @[Mux.scala 27:72]
|
|
wire _T_4968 = _T_4967 | _T_4841; // @[Mux.scala 27:72]
|
|
wire _T_4714 = ifu_ic_rw_int_addr_ff == 7'h5f; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_95; // @[Reg.scala 27:20]
|
|
wire _T_4842 = _T_4714 & way_status_out_95; // @[Mux.scala 27:72]
|
|
wire _T_4969 = _T_4968 | _T_4842; // @[Mux.scala 27:72]
|
|
wire _T_4715 = ifu_ic_rw_int_addr_ff == 7'h60; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_96; // @[Reg.scala 27:20]
|
|
wire _T_4843 = _T_4715 & way_status_out_96; // @[Mux.scala 27:72]
|
|
wire _T_4970 = _T_4969 | _T_4843; // @[Mux.scala 27:72]
|
|
wire _T_4716 = ifu_ic_rw_int_addr_ff == 7'h61; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_97; // @[Reg.scala 27:20]
|
|
wire _T_4844 = _T_4716 & way_status_out_97; // @[Mux.scala 27:72]
|
|
wire _T_4971 = _T_4970 | _T_4844; // @[Mux.scala 27:72]
|
|
wire _T_4717 = ifu_ic_rw_int_addr_ff == 7'h62; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_98; // @[Reg.scala 27:20]
|
|
wire _T_4845 = _T_4717 & way_status_out_98; // @[Mux.scala 27:72]
|
|
wire _T_4972 = _T_4971 | _T_4845; // @[Mux.scala 27:72]
|
|
wire _T_4718 = ifu_ic_rw_int_addr_ff == 7'h63; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_99; // @[Reg.scala 27:20]
|
|
wire _T_4846 = _T_4718 & way_status_out_99; // @[Mux.scala 27:72]
|
|
wire _T_4973 = _T_4972 | _T_4846; // @[Mux.scala 27:72]
|
|
wire _T_4719 = ifu_ic_rw_int_addr_ff == 7'h64; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_100; // @[Reg.scala 27:20]
|
|
wire _T_4847 = _T_4719 & way_status_out_100; // @[Mux.scala 27:72]
|
|
wire _T_4974 = _T_4973 | _T_4847; // @[Mux.scala 27:72]
|
|
wire _T_4720 = ifu_ic_rw_int_addr_ff == 7'h65; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_101; // @[Reg.scala 27:20]
|
|
wire _T_4848 = _T_4720 & way_status_out_101; // @[Mux.scala 27:72]
|
|
wire _T_4975 = _T_4974 | _T_4848; // @[Mux.scala 27:72]
|
|
wire _T_4721 = ifu_ic_rw_int_addr_ff == 7'h66; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_102; // @[Reg.scala 27:20]
|
|
wire _T_4849 = _T_4721 & way_status_out_102; // @[Mux.scala 27:72]
|
|
wire _T_4976 = _T_4975 | _T_4849; // @[Mux.scala 27:72]
|
|
wire _T_4722 = ifu_ic_rw_int_addr_ff == 7'h67; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_103; // @[Reg.scala 27:20]
|
|
wire _T_4850 = _T_4722 & way_status_out_103; // @[Mux.scala 27:72]
|
|
wire _T_4977 = _T_4976 | _T_4850; // @[Mux.scala 27:72]
|
|
wire _T_4723 = ifu_ic_rw_int_addr_ff == 7'h68; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_104; // @[Reg.scala 27:20]
|
|
wire _T_4851 = _T_4723 & way_status_out_104; // @[Mux.scala 27:72]
|
|
wire _T_4978 = _T_4977 | _T_4851; // @[Mux.scala 27:72]
|
|
wire _T_4724 = ifu_ic_rw_int_addr_ff == 7'h69; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_105; // @[Reg.scala 27:20]
|
|
wire _T_4852 = _T_4724 & way_status_out_105; // @[Mux.scala 27:72]
|
|
wire _T_4979 = _T_4978 | _T_4852; // @[Mux.scala 27:72]
|
|
wire _T_4725 = ifu_ic_rw_int_addr_ff == 7'h6a; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_106; // @[Reg.scala 27:20]
|
|
wire _T_4853 = _T_4725 & way_status_out_106; // @[Mux.scala 27:72]
|
|
wire _T_4980 = _T_4979 | _T_4853; // @[Mux.scala 27:72]
|
|
wire _T_4726 = ifu_ic_rw_int_addr_ff == 7'h6b; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_107; // @[Reg.scala 27:20]
|
|
wire _T_4854 = _T_4726 & way_status_out_107; // @[Mux.scala 27:72]
|
|
wire _T_4981 = _T_4980 | _T_4854; // @[Mux.scala 27:72]
|
|
wire _T_4727 = ifu_ic_rw_int_addr_ff == 7'h6c; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_108; // @[Reg.scala 27:20]
|
|
wire _T_4855 = _T_4727 & way_status_out_108; // @[Mux.scala 27:72]
|
|
wire _T_4982 = _T_4981 | _T_4855; // @[Mux.scala 27:72]
|
|
wire _T_4728 = ifu_ic_rw_int_addr_ff == 7'h6d; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_109; // @[Reg.scala 27:20]
|
|
wire _T_4856 = _T_4728 & way_status_out_109; // @[Mux.scala 27:72]
|
|
wire _T_4983 = _T_4982 | _T_4856; // @[Mux.scala 27:72]
|
|
wire _T_4729 = ifu_ic_rw_int_addr_ff == 7'h6e; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_110; // @[Reg.scala 27:20]
|
|
wire _T_4857 = _T_4729 & way_status_out_110; // @[Mux.scala 27:72]
|
|
wire _T_4984 = _T_4983 | _T_4857; // @[Mux.scala 27:72]
|
|
wire _T_4730 = ifu_ic_rw_int_addr_ff == 7'h6f; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_111; // @[Reg.scala 27:20]
|
|
wire _T_4858 = _T_4730 & way_status_out_111; // @[Mux.scala 27:72]
|
|
wire _T_4985 = _T_4984 | _T_4858; // @[Mux.scala 27:72]
|
|
wire _T_4731 = ifu_ic_rw_int_addr_ff == 7'h70; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_112; // @[Reg.scala 27:20]
|
|
wire _T_4859 = _T_4731 & way_status_out_112; // @[Mux.scala 27:72]
|
|
wire _T_4986 = _T_4985 | _T_4859; // @[Mux.scala 27:72]
|
|
wire _T_4732 = ifu_ic_rw_int_addr_ff == 7'h71; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_113; // @[Reg.scala 27:20]
|
|
wire _T_4860 = _T_4732 & way_status_out_113; // @[Mux.scala 27:72]
|
|
wire _T_4987 = _T_4986 | _T_4860; // @[Mux.scala 27:72]
|
|
wire _T_4733 = ifu_ic_rw_int_addr_ff == 7'h72; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_114; // @[Reg.scala 27:20]
|
|
wire _T_4861 = _T_4733 & way_status_out_114; // @[Mux.scala 27:72]
|
|
wire _T_4988 = _T_4987 | _T_4861; // @[Mux.scala 27:72]
|
|
wire _T_4734 = ifu_ic_rw_int_addr_ff == 7'h73; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_115; // @[Reg.scala 27:20]
|
|
wire _T_4862 = _T_4734 & way_status_out_115; // @[Mux.scala 27:72]
|
|
wire _T_4989 = _T_4988 | _T_4862; // @[Mux.scala 27:72]
|
|
wire _T_4735 = ifu_ic_rw_int_addr_ff == 7'h74; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_116; // @[Reg.scala 27:20]
|
|
wire _T_4863 = _T_4735 & way_status_out_116; // @[Mux.scala 27:72]
|
|
wire _T_4990 = _T_4989 | _T_4863; // @[Mux.scala 27:72]
|
|
wire _T_4736 = ifu_ic_rw_int_addr_ff == 7'h75; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_117; // @[Reg.scala 27:20]
|
|
wire _T_4864 = _T_4736 & way_status_out_117; // @[Mux.scala 27:72]
|
|
wire _T_4991 = _T_4990 | _T_4864; // @[Mux.scala 27:72]
|
|
wire _T_4737 = ifu_ic_rw_int_addr_ff == 7'h76; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_118; // @[Reg.scala 27:20]
|
|
wire _T_4865 = _T_4737 & way_status_out_118; // @[Mux.scala 27:72]
|
|
wire _T_4992 = _T_4991 | _T_4865; // @[Mux.scala 27:72]
|
|
wire _T_4738 = ifu_ic_rw_int_addr_ff == 7'h77; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_119; // @[Reg.scala 27:20]
|
|
wire _T_4866 = _T_4738 & way_status_out_119; // @[Mux.scala 27:72]
|
|
wire _T_4993 = _T_4992 | _T_4866; // @[Mux.scala 27:72]
|
|
wire _T_4739 = ifu_ic_rw_int_addr_ff == 7'h78; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_120; // @[Reg.scala 27:20]
|
|
wire _T_4867 = _T_4739 & way_status_out_120; // @[Mux.scala 27:72]
|
|
wire _T_4994 = _T_4993 | _T_4867; // @[Mux.scala 27:72]
|
|
wire _T_4740 = ifu_ic_rw_int_addr_ff == 7'h79; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_121; // @[Reg.scala 27:20]
|
|
wire _T_4868 = _T_4740 & way_status_out_121; // @[Mux.scala 27:72]
|
|
wire _T_4995 = _T_4994 | _T_4868; // @[Mux.scala 27:72]
|
|
wire _T_4741 = ifu_ic_rw_int_addr_ff == 7'h7a; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_122; // @[Reg.scala 27:20]
|
|
wire _T_4869 = _T_4741 & way_status_out_122; // @[Mux.scala 27:72]
|
|
wire _T_4996 = _T_4995 | _T_4869; // @[Mux.scala 27:72]
|
|
wire _T_4742 = ifu_ic_rw_int_addr_ff == 7'h7b; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_123; // @[Reg.scala 27:20]
|
|
wire _T_4870 = _T_4742 & way_status_out_123; // @[Mux.scala 27:72]
|
|
wire _T_4997 = _T_4996 | _T_4870; // @[Mux.scala 27:72]
|
|
wire _T_4743 = ifu_ic_rw_int_addr_ff == 7'h7c; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_124; // @[Reg.scala 27:20]
|
|
wire _T_4871 = _T_4743 & way_status_out_124; // @[Mux.scala 27:72]
|
|
wire _T_4998 = _T_4997 | _T_4871; // @[Mux.scala 27:72]
|
|
wire _T_4744 = ifu_ic_rw_int_addr_ff == 7'h7d; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_125; // @[Reg.scala 27:20]
|
|
wire _T_4872 = _T_4744 & way_status_out_125; // @[Mux.scala 27:72]
|
|
wire _T_4999 = _T_4998 | _T_4872; // @[Mux.scala 27:72]
|
|
wire _T_4745 = ifu_ic_rw_int_addr_ff == 7'h7e; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_126; // @[Reg.scala 27:20]
|
|
wire _T_4873 = _T_4745 & way_status_out_126; // @[Mux.scala 27:72]
|
|
wire _T_5000 = _T_4999 | _T_4873; // @[Mux.scala 27:72]
|
|
wire _T_4746 = ifu_ic_rw_int_addr_ff == 7'h7f; // @[el2_ifu_mem_ctl.scala 734:80]
|
|
reg way_status_out_127; // @[Reg.scala 27:20]
|
|
wire _T_4874 = _T_4746 & way_status_out_127; // @[Mux.scala 27:72]
|
|
wire way_status = _T_5000 | _T_4874; // @[Mux.scala 27:72]
|
|
wire _T_195 = ~reset_all_tags; // @[el2_ifu_mem_ctl.scala 264:96]
|
|
wire [1:0] _T_197 = _T_195 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_198 = _T_197 & io_ic_tag_valid; // @[el2_ifu_mem_ctl.scala 264:113]
|
|
reg [1:0] tagv_mb_scnd_ff; // @[el2_ifu_mem_ctl.scala 270:58]
|
|
reg uncacheable_miss_scnd_ff; // @[el2_ifu_mem_ctl.scala 266:67]
|
|
reg [30:0] imb_scnd_ff; // @[el2_ifu_mem_ctl.scala 268:54]
|
|
wire [2:0] _T_206 = bus_ifu_wr_en_ff ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
reg [2:0] ifu_bus_rid_ff; // @[el2_ifu_mem_ctl.scala 584:46]
|
|
wire [2:0] ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & _T_206; // @[el2_ifu_mem_ctl.scala 273:45]
|
|
wire _T_212 = _T_231 | _T_239; // @[el2_ifu_mem_ctl.scala 278:59]
|
|
wire _T_214 = _T_212 | _T_2219; // @[el2_ifu_mem_ctl.scala 278:91]
|
|
wire ic_iccm_hit_f = fetch_req_iccm_f & _T_214; // @[el2_ifu_mem_ctl.scala 278:41]
|
|
wire _T_219 = _T_227 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 284:39]
|
|
wire _T_221 = _T_219 & _T_195; // @[el2_ifu_mem_ctl.scala 284:60]
|
|
wire _T_225 = _T_221 & _T_212; // @[el2_ifu_mem_ctl.scala 284:78]
|
|
wire ic_act_hit_f = _T_225 & _T_247; // @[el2_ifu_mem_ctl.scala 284:126]
|
|
wire _T_262 = ic_act_hit_f | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 291:31]
|
|
wire _T_263 = _T_262 | ic_iccm_hit_f; // @[el2_ifu_mem_ctl.scala 291:46]
|
|
wire _T_264 = ifc_region_acc_fault_final_f & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 291:94]
|
|
wire _T_268 = sel_hold_imb ? uncacheable_miss_ff : io_ifc_fetch_uncacheable_bf; // @[el2_ifu_mem_ctl.scala 292:84]
|
|
wire uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : _T_268; // @[el2_ifu_mem_ctl.scala 292:32]
|
|
wire _T_274 = imb_ff[11:5] == imb_scnd_ff[11:5]; // @[el2_ifu_mem_ctl.scala 295:79]
|
|
wire _T_275 = _T_274 & scnd_miss_req; // @[el2_ifu_mem_ctl.scala 295:135]
|
|
reg [1:0] ifu_bus_rresp_ff; // @[el2_ifu_mem_ctl.scala 582:51]
|
|
wire _T_2643 = |ifu_bus_rresp_ff; // @[el2_ifu_mem_ctl.scala 627:48]
|
|
wire _T_2644 = _T_2643 & ifu_bus_rvalid_ff; // @[el2_ifu_mem_ctl.scala 627:52]
|
|
wire bus_ifu_wr_data_error_ff = _T_2644 & miss_pending; // @[el2_ifu_mem_ctl.scala 627:73]
|
|
reg ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 369:61]
|
|
wire ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 368:55]
|
|
wire _T_276 = ~ifu_wr_cumulative_err_data; // @[el2_ifu_mem_ctl.scala 295:153]
|
|
wire scnd_miss_index_match = _T_275 & _T_276; // @[el2_ifu_mem_ctl.scala 295:151]
|
|
wire _T_277 = ~scnd_miss_index_match; // @[el2_ifu_mem_ctl.scala 298:47]
|
|
wire _T_278 = scnd_miss_req & _T_277; // @[el2_ifu_mem_ctl.scala 298:45]
|
|
wire _T_280 = scnd_miss_req & scnd_miss_index_match; // @[el2_ifu_mem_ctl.scala 299:26]
|
|
reg way_status_mb_ff; // @[el2_ifu_mem_ctl.scala 319:59]
|
|
wire _T_9704 = ~way_status_mb_ff; // @[el2_ifu_mem_ctl.scala 790:33]
|
|
reg [1:0] tagv_mb_ff; // @[el2_ifu_mem_ctl.scala 320:53]
|
|
wire _T_9706 = _T_9704 & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 790:51]
|
|
wire _T_9708 = _T_9706 & tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 790:67]
|
|
wire _T_9710 = ~tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 790:86]
|
|
wire replace_way_mb_any_0 = _T_9708 | _T_9710; // @[el2_ifu_mem_ctl.scala 790:84]
|
|
wire [1:0] _T_287 = scnd_miss_index_match ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_9713 = way_status_mb_ff & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 791:50]
|
|
wire _T_9715 = _T_9713 & tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 791:66]
|
|
wire _T_9717 = ~tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 791:85]
|
|
wire _T_9719 = _T_9717 & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 791:100]
|
|
wire replace_way_mb_any_1 = _T_9715 | _T_9719; // @[el2_ifu_mem_ctl.scala 791:83]
|
|
wire [1:0] _T_288 = {replace_way_mb_any_1,replace_way_mb_any_0}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_289 = _T_287 & _T_288; // @[el2_ifu_mem_ctl.scala 303:110]
|
|
wire [1:0] _T_290 = tagv_mb_scnd_ff | _T_289; // @[el2_ifu_mem_ctl.scala 303:62]
|
|
wire [1:0] _T_295 = io_ic_tag_valid & _T_197; // @[el2_ifu_mem_ctl.scala 304:56]
|
|
wire _T_297 = ~scnd_miss_req_q; // @[el2_ifu_mem_ctl.scala 307:36]
|
|
wire _T_298 = miss_pending & _T_297; // @[el2_ifu_mem_ctl.scala 307:34]
|
|
reg reset_ic_ff; // @[el2_ifu_mem_ctl.scala 308:25]
|
|
wire _T_299 = reset_all_tags | reset_ic_ff; // @[el2_ifu_mem_ctl.scala 307:72]
|
|
wire reset_ic_in = _T_298 & _T_299; // @[el2_ifu_mem_ctl.scala 307:53]
|
|
reg fetch_uncacheable_ff; // @[el2_ifu_mem_ctl.scala 309:37]
|
|
reg [25:0] miss_addr; // @[el2_ifu_mem_ctl.scala 318:48]
|
|
wire _T_309 = io_ifu_bus_clk_en | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 317:57]
|
|
wire _T_315 = _T_2234 & flush_final_f; // @[el2_ifu_mem_ctl.scala 322:87]
|
|
wire _T_316 = ~_T_315; // @[el2_ifu_mem_ctl.scala 322:55]
|
|
wire _T_317 = io_ifc_fetch_req_bf & _T_316; // @[el2_ifu_mem_ctl.scala 322:53]
|
|
wire _T_2226 = ~_T_2221; // @[el2_ifu_mem_ctl.scala 460:46]
|
|
wire _T_2227 = _T_2219 & _T_2226; // @[el2_ifu_mem_ctl.scala 460:44]
|
|
wire stream_miss_f = _T_2227 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 460:84]
|
|
wire _T_318 = ~stream_miss_f; // @[el2_ifu_mem_ctl.scala 322:106]
|
|
reg ifc_region_acc_fault_f; // @[el2_ifu_mem_ctl.scala 328:68]
|
|
reg [2:0] bus_rd_addr_count; // @[el2_ifu_mem_ctl.scala 609:55]
|
|
wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58]
|
|
wire _T_325 = _T_239 | _T_2219; // @[el2_ifu_mem_ctl.scala 330:55]
|
|
wire _T_328 = _T_325 & _T_56; // @[el2_ifu_mem_ctl.scala 330:82]
|
|
wire _T_2240 = ~ifu_bus_rid_ff[0]; // @[el2_ifu_mem_ctl.scala 465:55]
|
|
wire [2:0] other_tag = {ifu_bus_rid_ff[2:1],_T_2240}; // @[Cat.scala 29:58]
|
|
wire _T_2241 = other_tag == 3'h0; // @[el2_ifu_mem_ctl.scala 466:81]
|
|
wire _T_2265 = _T_2241 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72]
|
|
wire _T_2244 = other_tag == 3'h1; // @[el2_ifu_mem_ctl.scala 466:81]
|
|
wire _T_2266 = _T_2244 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72]
|
|
wire _T_2273 = _T_2265 | _T_2266; // @[Mux.scala 27:72]
|
|
wire _T_2247 = other_tag == 3'h2; // @[el2_ifu_mem_ctl.scala 466:81]
|
|
wire _T_2267 = _T_2247 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72]
|
|
wire _T_2274 = _T_2273 | _T_2267; // @[Mux.scala 27:72]
|
|
wire _T_2250 = other_tag == 3'h3; // @[el2_ifu_mem_ctl.scala 466:81]
|
|
wire _T_2268 = _T_2250 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72]
|
|
wire _T_2275 = _T_2274 | _T_2268; // @[Mux.scala 27:72]
|
|
wire _T_2253 = other_tag == 3'h4; // @[el2_ifu_mem_ctl.scala 466:81]
|
|
wire _T_2269 = _T_2253 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72]
|
|
wire _T_2276 = _T_2275 | _T_2269; // @[Mux.scala 27:72]
|
|
wire _T_2256 = other_tag == 3'h5; // @[el2_ifu_mem_ctl.scala 466:81]
|
|
wire _T_2270 = _T_2256 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72]
|
|
wire _T_2277 = _T_2276 | _T_2270; // @[Mux.scala 27:72]
|
|
wire _T_2259 = other_tag == 3'h6; // @[el2_ifu_mem_ctl.scala 466:81]
|
|
wire _T_2271 = _T_2259 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72]
|
|
wire _T_2278 = _T_2277 | _T_2271; // @[Mux.scala 27:72]
|
|
wire _T_2262 = other_tag == 3'h7; // @[el2_ifu_mem_ctl.scala 466:81]
|
|
wire _T_2272 = _T_2262 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72]
|
|
wire second_half_available = _T_2278 | _T_2272; // @[Mux.scala 27:72]
|
|
wire write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff; // @[el2_ifu_mem_ctl.scala 467:46]
|
|
wire _T_332 = miss_pending & write_ic_16_bytes; // @[el2_ifu_mem_ctl.scala 334:35]
|
|
wire _T_334 = _T_332 & _T_17; // @[el2_ifu_mem_ctl.scala 334:55]
|
|
reg ic_act_miss_f_delayed; // @[el2_ifu_mem_ctl.scala 624:61]
|
|
wire _T_2637 = ic_act_miss_f_delayed & _T_2235; // @[el2_ifu_mem_ctl.scala 625:53]
|
|
wire reset_tag_valid_for_miss = _T_2637 & _T_17; // @[el2_ifu_mem_ctl.scala 625:84]
|
|
wire sel_mb_addr = _T_334 | reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 334:79]
|
|
wire [30:0] _T_338 = {imb_ff[30:5],ic_wr_addr_bits_hi_3,imb_ff[1:0]}; // @[Cat.scala 29:58]
|
|
wire _T_339 = ~sel_mb_addr; // @[el2_ifu_mem_ctl.scala 336:37]
|
|
wire [30:0] _T_340 = sel_mb_addr ? _T_338 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_341 = _T_339 ? io_ifc_fetch_addr_bf : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] ifu_ic_rw_int_addr = _T_340 | _T_341; // @[Mux.scala 27:72]
|
|
wire _T_346 = _T_334 & last_beat; // @[el2_ifu_mem_ctl.scala 338:84]
|
|
wire _T_2631 = ~_T_2643; // @[el2_ifu_mem_ctl.scala 622:84]
|
|
wire _T_2632 = _T_100 & _T_2631; // @[el2_ifu_mem_ctl.scala 622:82]
|
|
wire bus_ifu_wr_en_ff_q = _T_2632 & write_ic_16_bytes; // @[el2_ifu_mem_ctl.scala 622:108]
|
|
wire sel_mb_status_addr = _T_346 & bus_ifu_wr_en_ff_q; // @[el2_ifu_mem_ctl.scala 338:96]
|
|
wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_338 : ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 339:31]
|
|
reg [63:0] ifu_bus_rdata_ff; // @[el2_ifu_mem_ctl.scala 583:48]
|
|
wire [6:0] _T_569 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[57]}; // @[el2_lib.scala 416:13]
|
|
wire _T_570 = ^_T_569; // @[el2_lib.scala 416:20]
|
|
wire [6:0] _T_576 = {ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31],ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[26]}; // @[el2_lib.scala 416:30]
|
|
wire [7:0] _T_583 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33]}; // @[el2_lib.scala 416:30]
|
|
wire [14:0] _T_584 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33],_T_576}; // @[el2_lib.scala 416:30]
|
|
wire [7:0] _T_591 = {ifu_bus_rdata_ff[48],ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[41]}; // @[el2_lib.scala 416:30]
|
|
wire [30:0] _T_600 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_591,_T_584}; // @[el2_lib.scala 416:30]
|
|
wire _T_601 = ^_T_600; // @[el2_lib.scala 416:37]
|
|
wire [6:0] _T_607 = {ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[13],ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[11]}; // @[el2_lib.scala 416:47]
|
|
wire [14:0] _T_615 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_607}; // @[el2_lib.scala 416:47]
|
|
wire [30:0] _T_631 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_591,_T_615}; // @[el2_lib.scala 416:47]
|
|
wire _T_632 = ^_T_631; // @[el2_lib.scala 416:54]
|
|
wire [6:0] _T_638 = {ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[4]}; // @[el2_lib.scala 416:64]
|
|
wire [14:0] _T_646 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_638}; // @[el2_lib.scala 416:64]
|
|
wire [30:0] _T_662 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_583,_T_646}; // @[el2_lib.scala 416:64]
|
|
wire _T_663 = ^_T_662; // @[el2_lib.scala 416:71]
|
|
wire [7:0] _T_670 = {ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[1]}; // @[el2_lib.scala 416:81]
|
|
wire [16:0] _T_679 = {ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],_T_670}; // @[el2_lib.scala 416:81]
|
|
wire [8:0] _T_687 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[el2_lib.scala 416:81]
|
|
wire [17:0] _T_696 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[48],_T_687}; // @[el2_lib.scala 416:81]
|
|
wire [34:0] _T_697 = {_T_696,_T_679}; // @[el2_lib.scala 416:81]
|
|
wire _T_698 = ^_T_697; // @[el2_lib.scala 416:88]
|
|
wire [7:0] _T_705 = {ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[0]}; // @[el2_lib.scala 416:98]
|
|
wire [16:0] _T_714 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[13],_T_705}; // @[el2_lib.scala 416:98]
|
|
wire [8:0] _T_722 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[el2_lib.scala 416:98]
|
|
wire [17:0] _T_731 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[48],_T_722}; // @[el2_lib.scala 416:98]
|
|
wire [34:0] _T_732 = {_T_731,_T_714}; // @[el2_lib.scala 416:98]
|
|
wire _T_733 = ^_T_732; // @[el2_lib.scala 416:105]
|
|
wire [7:0] _T_740 = {ifu_bus_rdata_ff[11],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[4],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[1],ifu_bus_rdata_ff[0]}; // @[el2_lib.scala 416:115]
|
|
wire [16:0] _T_749 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[26],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[13],_T_740}; // @[el2_lib.scala 416:115]
|
|
wire [8:0] _T_757 = {ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[30]}; // @[el2_lib.scala 416:115]
|
|
wire [17:0] _T_766 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[57],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[48],_T_757}; // @[el2_lib.scala 416:115]
|
|
wire [34:0] _T_767 = {_T_766,_T_749}; // @[el2_lib.scala 416:115]
|
|
wire _T_768 = ^_T_767; // @[el2_lib.scala 416:122]
|
|
wire [3:0] _T_2281 = {ifu_bus_rid_ff[2:1],_T_2240,1'h1}; // @[Cat.scala 29:58]
|
|
wire _T_2282 = _T_2281 == 4'h0; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_0; // @[el2_ifu_mem_ctl.scala 403:65]
|
|
wire [31:0] _T_2329 = _T_2282 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_2285 = _T_2281 == 4'h1; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_1; // @[el2_ifu_mem_ctl.scala 404:67]
|
|
wire [31:0] _T_2330 = _T_2285 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2345 = _T_2329 | _T_2330; // @[Mux.scala 27:72]
|
|
wire _T_2288 = _T_2281 == 4'h2; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_2; // @[el2_ifu_mem_ctl.scala 403:65]
|
|
wire [31:0] _T_2331 = _T_2288 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2346 = _T_2345 | _T_2331; // @[Mux.scala 27:72]
|
|
wire _T_2291 = _T_2281 == 4'h3; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_3; // @[el2_ifu_mem_ctl.scala 404:67]
|
|
wire [31:0] _T_2332 = _T_2291 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2347 = _T_2346 | _T_2332; // @[Mux.scala 27:72]
|
|
wire _T_2294 = _T_2281 == 4'h4; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_4; // @[el2_ifu_mem_ctl.scala 403:65]
|
|
wire [31:0] _T_2333 = _T_2294 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2348 = _T_2347 | _T_2333; // @[Mux.scala 27:72]
|
|
wire _T_2297 = _T_2281 == 4'h5; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_5; // @[el2_ifu_mem_ctl.scala 404:67]
|
|
wire [31:0] _T_2334 = _T_2297 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2349 = _T_2348 | _T_2334; // @[Mux.scala 27:72]
|
|
wire _T_2300 = _T_2281 == 4'h6; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_6; // @[el2_ifu_mem_ctl.scala 403:65]
|
|
wire [31:0] _T_2335 = _T_2300 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2350 = _T_2349 | _T_2335; // @[Mux.scala 27:72]
|
|
wire _T_2303 = _T_2281 == 4'h7; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_7; // @[el2_ifu_mem_ctl.scala 404:67]
|
|
wire [31:0] _T_2336 = _T_2303 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2351 = _T_2350 | _T_2336; // @[Mux.scala 27:72]
|
|
wire _T_2306 = _T_2281 == 4'h8; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_8; // @[el2_ifu_mem_ctl.scala 403:65]
|
|
wire [31:0] _T_2337 = _T_2306 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2352 = _T_2351 | _T_2337; // @[Mux.scala 27:72]
|
|
wire _T_2309 = _T_2281 == 4'h9; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_9; // @[el2_ifu_mem_ctl.scala 404:67]
|
|
wire [31:0] _T_2338 = _T_2309 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2353 = _T_2352 | _T_2338; // @[Mux.scala 27:72]
|
|
wire _T_2312 = _T_2281 == 4'ha; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_10; // @[el2_ifu_mem_ctl.scala 403:65]
|
|
wire [31:0] _T_2339 = _T_2312 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2354 = _T_2353 | _T_2339; // @[Mux.scala 27:72]
|
|
wire _T_2315 = _T_2281 == 4'hb; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_11; // @[el2_ifu_mem_ctl.scala 404:67]
|
|
wire [31:0] _T_2340 = _T_2315 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2355 = _T_2354 | _T_2340; // @[Mux.scala 27:72]
|
|
wire _T_2318 = _T_2281 == 4'hc; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_12; // @[el2_ifu_mem_ctl.scala 403:65]
|
|
wire [31:0] _T_2341 = _T_2318 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2356 = _T_2355 | _T_2341; // @[Mux.scala 27:72]
|
|
wire _T_2321 = _T_2281 == 4'hd; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_13; // @[el2_ifu_mem_ctl.scala 404:67]
|
|
wire [31:0] _T_2342 = _T_2321 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2357 = _T_2356 | _T_2342; // @[Mux.scala 27:72]
|
|
wire _T_2324 = _T_2281 == 4'he; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_14; // @[el2_ifu_mem_ctl.scala 403:65]
|
|
wire [31:0] _T_2343 = _T_2324 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2358 = _T_2357 | _T_2343; // @[Mux.scala 27:72]
|
|
wire _T_2327 = _T_2281 == 4'hf; // @[el2_ifu_mem_ctl.scala 468:89]
|
|
reg [31:0] ic_miss_buff_data_15; // @[el2_ifu_mem_ctl.scala 404:67]
|
|
wire [31:0] _T_2344 = _T_2327 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2359 = _T_2358 | _T_2344; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_2361 = {ifu_bus_rid_ff[2:1],_T_2240,1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_2362 = _T_2361 == 4'h0; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2409 = _T_2362 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_2365 = _T_2361 == 4'h1; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2410 = _T_2365 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2425 = _T_2409 | _T_2410; // @[Mux.scala 27:72]
|
|
wire _T_2368 = _T_2361 == 4'h2; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2411 = _T_2368 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2426 = _T_2425 | _T_2411; // @[Mux.scala 27:72]
|
|
wire _T_2371 = _T_2361 == 4'h3; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2412 = _T_2371 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2427 = _T_2426 | _T_2412; // @[Mux.scala 27:72]
|
|
wire _T_2374 = _T_2361 == 4'h4; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2413 = _T_2374 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2428 = _T_2427 | _T_2413; // @[Mux.scala 27:72]
|
|
wire _T_2377 = _T_2361 == 4'h5; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2414 = _T_2377 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2429 = _T_2428 | _T_2414; // @[Mux.scala 27:72]
|
|
wire _T_2380 = _T_2361 == 4'h6; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2415 = _T_2380 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2430 = _T_2429 | _T_2415; // @[Mux.scala 27:72]
|
|
wire _T_2383 = _T_2361 == 4'h7; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2416 = _T_2383 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2431 = _T_2430 | _T_2416; // @[Mux.scala 27:72]
|
|
wire _T_2386 = _T_2361 == 4'h8; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2417 = _T_2386 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2432 = _T_2431 | _T_2417; // @[Mux.scala 27:72]
|
|
wire _T_2389 = _T_2361 == 4'h9; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2418 = _T_2389 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2433 = _T_2432 | _T_2418; // @[Mux.scala 27:72]
|
|
wire _T_2392 = _T_2361 == 4'ha; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2419 = _T_2392 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2434 = _T_2433 | _T_2419; // @[Mux.scala 27:72]
|
|
wire _T_2395 = _T_2361 == 4'hb; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2420 = _T_2395 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2435 = _T_2434 | _T_2420; // @[Mux.scala 27:72]
|
|
wire _T_2398 = _T_2361 == 4'hc; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2421 = _T_2398 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2436 = _T_2435 | _T_2421; // @[Mux.scala 27:72]
|
|
wire _T_2401 = _T_2361 == 4'hd; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2422 = _T_2401 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2437 = _T_2436 | _T_2422; // @[Mux.scala 27:72]
|
|
wire _T_2404 = _T_2361 == 4'he; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2423 = _T_2404 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2438 = _T_2437 | _T_2423; // @[Mux.scala 27:72]
|
|
wire _T_2407 = _T_2361 == 4'hf; // @[el2_ifu_mem_ctl.scala 469:66]
|
|
wire [31:0] _T_2424 = _T_2407 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2439 = _T_2438 | _T_2424; // @[Mux.scala 27:72]
|
|
wire [63:0] ic_miss_buff_half = {_T_2359,_T_2439}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_991 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[57]}; // @[el2_lib.scala 416:13]
|
|
wire _T_992 = ^_T_991; // @[el2_lib.scala 416:20]
|
|
wire [6:0] _T_998 = {ic_miss_buff_half[32],ic_miss_buff_half[31],ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[26]}; // @[el2_lib.scala 416:30]
|
|
wire [7:0] _T_1005 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33]}; // @[el2_lib.scala 416:30]
|
|
wire [14:0] _T_1006 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33],_T_998}; // @[el2_lib.scala 416:30]
|
|
wire [7:0] _T_1013 = {ic_miss_buff_half[48],ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[42],ic_miss_buff_half[41]}; // @[el2_lib.scala 416:30]
|
|
wire [30:0] _T_1022 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1013,_T_1006}; // @[el2_lib.scala 416:30]
|
|
wire _T_1023 = ^_T_1022; // @[el2_lib.scala 416:37]
|
|
wire [6:0] _T_1029 = {ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],ic_miss_buff_half[14],ic_miss_buff_half[13],ic_miss_buff_half[12],ic_miss_buff_half[11]}; // @[el2_lib.scala 416:47]
|
|
wire [14:0] _T_1037 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1029}; // @[el2_lib.scala 416:47]
|
|
wire [30:0] _T_1053 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1013,_T_1037}; // @[el2_lib.scala 416:47]
|
|
wire _T_1054 = ^_T_1053; // @[el2_lib.scala 416:54]
|
|
wire [6:0] _T_1060 = {ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[4]}; // @[el2_lib.scala 416:64]
|
|
wire [14:0] _T_1068 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1060}; // @[el2_lib.scala 416:64]
|
|
wire [30:0] _T_1084 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1005,_T_1068}; // @[el2_lib.scala 416:64]
|
|
wire _T_1085 = ^_T_1084; // @[el2_lib.scala 416:71]
|
|
wire [7:0] _T_1092 = {ic_miss_buff_half[14],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[1]}; // @[el2_lib.scala 416:81]
|
|
wire [16:0] _T_1101 = {ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],_T_1092}; // @[el2_lib.scala 416:81]
|
|
wire [8:0] _T_1109 = {ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[el2_lib.scala 416:81]
|
|
wire [17:0] _T_1118 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[48],_T_1109}; // @[el2_lib.scala 416:81]
|
|
wire [34:0] _T_1119 = {_T_1118,_T_1101}; // @[el2_lib.scala 416:81]
|
|
wire _T_1120 = ^_T_1119; // @[el2_lib.scala 416:88]
|
|
wire [7:0] _T_1127 = {ic_miss_buff_half[12],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[0]}; // @[el2_lib.scala 416:98]
|
|
wire [16:0] _T_1136 = {ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[13],_T_1127}; // @[el2_lib.scala 416:98]
|
|
wire [8:0] _T_1144 = {ic_miss_buff_half[47],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[el2_lib.scala 416:98]
|
|
wire [17:0] _T_1153 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[48],_T_1144}; // @[el2_lib.scala 416:98]
|
|
wire [34:0] _T_1154 = {_T_1153,_T_1136}; // @[el2_lib.scala 416:98]
|
|
wire _T_1155 = ^_T_1154; // @[el2_lib.scala 416:105]
|
|
wire [7:0] _T_1162 = {ic_miss_buff_half[11],ic_miss_buff_half[10],ic_miss_buff_half[8],ic_miss_buff_half[6],ic_miss_buff_half[4],ic_miss_buff_half[3],ic_miss_buff_half[1],ic_miss_buff_half[0]}; // @[el2_lib.scala 416:115]
|
|
wire [16:0] _T_1171 = {ic_miss_buff_half[28],ic_miss_buff_half[26],ic_miss_buff_half[25],ic_miss_buff_half[23],ic_miss_buff_half[21],ic_miss_buff_half[19],ic_miss_buff_half[17],ic_miss_buff_half[15],ic_miss_buff_half[13],_T_1162}; // @[el2_lib.scala 416:115]
|
|
wire [8:0] _T_1179 = {ic_miss_buff_half[46],ic_miss_buff_half[44],ic_miss_buff_half[42],ic_miss_buff_half[40],ic_miss_buff_half[38],ic_miss_buff_half[36],ic_miss_buff_half[34],ic_miss_buff_half[32],ic_miss_buff_half[30]}; // @[el2_lib.scala 416:115]
|
|
wire [17:0] _T_1188 = {ic_miss_buff_half[63],ic_miss_buff_half[61],ic_miss_buff_half[59],ic_miss_buff_half[57],ic_miss_buff_half[56],ic_miss_buff_half[54],ic_miss_buff_half[52],ic_miss_buff_half[50],ic_miss_buff_half[48],_T_1179}; // @[el2_lib.scala 416:115]
|
|
wire [34:0] _T_1189 = {_T_1188,_T_1171}; // @[el2_lib.scala 416:115]
|
|
wire _T_1190 = ^_T_1189; // @[el2_lib.scala 416:122]
|
|
wire [70:0] _T_1235 = {_T_570,_T_601,_T_632,_T_663,_T_698,_T_733,_T_768,ifu_bus_rdata_ff}; // @[Cat.scala 29:58]
|
|
wire [70:0] _T_1234 = {_T_992,_T_1023,_T_1054,_T_1085,_T_1120,_T_1155,_T_1190,_T_2359,_T_2439}; // @[Cat.scala 29:58]
|
|
wire [141:0] _T_1236 = {_T_570,_T_601,_T_632,_T_663,_T_698,_T_733,_T_768,ifu_bus_rdata_ff,_T_1234}; // @[Cat.scala 29:58]
|
|
wire [141:0] _T_1239 = {_T_992,_T_1023,_T_1054,_T_1085,_T_1120,_T_1155,_T_1190,_T_2359,_T_2439,_T_1235}; // @[Cat.scala 29:58]
|
|
wire [141:0] ic_wr_16bytes_data = ifu_bus_rid_ff[0] ? _T_1236 : _T_1239; // @[el2_ifu_mem_ctl.scala 360:28]
|
|
wire _T_1198 = |io_ic_eccerr; // @[el2_ifu_mem_ctl.scala 350:56]
|
|
wire _T_1199 = _T_1198 & ic_act_hit_f; // @[el2_ifu_mem_ctl.scala 350:83]
|
|
wire [4:0] bypass_index = imb_ff[4:0]; // @[el2_ifu_mem_ctl.scala 415:28]
|
|
wire _T_1399 = bypass_index[4:2] == 3'h0; // @[el2_ifu_mem_ctl.scala 417:114]
|
|
wire bus_ifu_wr_en = _T_13 & miss_pending; // @[el2_ifu_mem_ctl.scala 620:35]
|
|
wire _T_1284 = io_ifu_axi_rid == 3'h0; // @[el2_ifu_mem_ctl.scala 399:91]
|
|
wire write_fill_data_0 = bus_ifu_wr_en & _T_1284; // @[el2_ifu_mem_ctl.scala 399:73]
|
|
wire _T_1325 = ~ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 406:118]
|
|
wire _T_1326 = ic_miss_buff_data_valid[0] & _T_1325; // @[el2_ifu_mem_ctl.scala 406:116]
|
|
wire ic_miss_buff_data_valid_in_0 = write_fill_data_0 | _T_1326; // @[el2_ifu_mem_ctl.scala 406:88]
|
|
wire _T_1422 = _T_1399 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72]
|
|
wire _T_1402 = bypass_index[4:2] == 3'h1; // @[el2_ifu_mem_ctl.scala 417:114]
|
|
wire _T_1285 = io_ifu_axi_rid == 3'h1; // @[el2_ifu_mem_ctl.scala 399:91]
|
|
wire write_fill_data_1 = bus_ifu_wr_en & _T_1285; // @[el2_ifu_mem_ctl.scala 399:73]
|
|
wire _T_1329 = ic_miss_buff_data_valid[1] & _T_1325; // @[el2_ifu_mem_ctl.scala 406:116]
|
|
wire ic_miss_buff_data_valid_in_1 = write_fill_data_1 | _T_1329; // @[el2_ifu_mem_ctl.scala 406:88]
|
|
wire _T_1423 = _T_1402 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72]
|
|
wire _T_1430 = _T_1422 | _T_1423; // @[Mux.scala 27:72]
|
|
wire _T_1405 = bypass_index[4:2] == 3'h2; // @[el2_ifu_mem_ctl.scala 417:114]
|
|
wire _T_1286 = io_ifu_axi_rid == 3'h2; // @[el2_ifu_mem_ctl.scala 399:91]
|
|
wire write_fill_data_2 = bus_ifu_wr_en & _T_1286; // @[el2_ifu_mem_ctl.scala 399:73]
|
|
wire _T_1332 = ic_miss_buff_data_valid[2] & _T_1325; // @[el2_ifu_mem_ctl.scala 406:116]
|
|
wire ic_miss_buff_data_valid_in_2 = write_fill_data_2 | _T_1332; // @[el2_ifu_mem_ctl.scala 406:88]
|
|
wire _T_1424 = _T_1405 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72]
|
|
wire _T_1431 = _T_1430 | _T_1424; // @[Mux.scala 27:72]
|
|
wire _T_1408 = bypass_index[4:2] == 3'h3; // @[el2_ifu_mem_ctl.scala 417:114]
|
|
wire _T_1287 = io_ifu_axi_rid == 3'h3; // @[el2_ifu_mem_ctl.scala 399:91]
|
|
wire write_fill_data_3 = bus_ifu_wr_en & _T_1287; // @[el2_ifu_mem_ctl.scala 399:73]
|
|
wire _T_1335 = ic_miss_buff_data_valid[3] & _T_1325; // @[el2_ifu_mem_ctl.scala 406:116]
|
|
wire ic_miss_buff_data_valid_in_3 = write_fill_data_3 | _T_1335; // @[el2_ifu_mem_ctl.scala 406:88]
|
|
wire _T_1425 = _T_1408 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72]
|
|
wire _T_1432 = _T_1431 | _T_1425; // @[Mux.scala 27:72]
|
|
wire _T_1411 = bypass_index[4:2] == 3'h4; // @[el2_ifu_mem_ctl.scala 417:114]
|
|
wire _T_1288 = io_ifu_axi_rid == 3'h4; // @[el2_ifu_mem_ctl.scala 399:91]
|
|
wire write_fill_data_4 = bus_ifu_wr_en & _T_1288; // @[el2_ifu_mem_ctl.scala 399:73]
|
|
wire _T_1338 = ic_miss_buff_data_valid[4] & _T_1325; // @[el2_ifu_mem_ctl.scala 406:116]
|
|
wire ic_miss_buff_data_valid_in_4 = write_fill_data_4 | _T_1338; // @[el2_ifu_mem_ctl.scala 406:88]
|
|
wire _T_1426 = _T_1411 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72]
|
|
wire _T_1433 = _T_1432 | _T_1426; // @[Mux.scala 27:72]
|
|
wire _T_1414 = bypass_index[4:2] == 3'h5; // @[el2_ifu_mem_ctl.scala 417:114]
|
|
wire _T_1289 = io_ifu_axi_rid == 3'h5; // @[el2_ifu_mem_ctl.scala 399:91]
|
|
wire write_fill_data_5 = bus_ifu_wr_en & _T_1289; // @[el2_ifu_mem_ctl.scala 399:73]
|
|
wire _T_1341 = ic_miss_buff_data_valid[5] & _T_1325; // @[el2_ifu_mem_ctl.scala 406:116]
|
|
wire ic_miss_buff_data_valid_in_5 = write_fill_data_5 | _T_1341; // @[el2_ifu_mem_ctl.scala 406:88]
|
|
wire _T_1427 = _T_1414 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72]
|
|
wire _T_1434 = _T_1433 | _T_1427; // @[Mux.scala 27:72]
|
|
wire _T_1417 = bypass_index[4:2] == 3'h6; // @[el2_ifu_mem_ctl.scala 417:114]
|
|
wire _T_1290 = io_ifu_axi_rid == 3'h6; // @[el2_ifu_mem_ctl.scala 399:91]
|
|
wire write_fill_data_6 = bus_ifu_wr_en & _T_1290; // @[el2_ifu_mem_ctl.scala 399:73]
|
|
wire _T_1344 = ic_miss_buff_data_valid[6] & _T_1325; // @[el2_ifu_mem_ctl.scala 406:116]
|
|
wire ic_miss_buff_data_valid_in_6 = write_fill_data_6 | _T_1344; // @[el2_ifu_mem_ctl.scala 406:88]
|
|
wire _T_1428 = _T_1417 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72]
|
|
wire _T_1435 = _T_1434 | _T_1428; // @[Mux.scala 27:72]
|
|
wire _T_1420 = bypass_index[4:2] == 3'h7; // @[el2_ifu_mem_ctl.scala 417:114]
|
|
wire _T_1291 = io_ifu_axi_rid == 3'h7; // @[el2_ifu_mem_ctl.scala 399:91]
|
|
wire write_fill_data_7 = bus_ifu_wr_en & _T_1291; // @[el2_ifu_mem_ctl.scala 399:73]
|
|
wire _T_1347 = ic_miss_buff_data_valid[7] & _T_1325; // @[el2_ifu_mem_ctl.scala 406:116]
|
|
wire ic_miss_buff_data_valid_in_7 = write_fill_data_7 | _T_1347; // @[el2_ifu_mem_ctl.scala 406:88]
|
|
wire _T_1429 = _T_1420 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72]
|
|
wire bypass_valid_value_check = _T_1435 | _T_1429; // @[Mux.scala 27:72]
|
|
wire _T_1438 = ~bypass_index[1]; // @[el2_ifu_mem_ctl.scala 418:58]
|
|
wire _T_1439 = bypass_valid_value_check & _T_1438; // @[el2_ifu_mem_ctl.scala 418:56]
|
|
wire _T_1441 = ~bypass_index[0]; // @[el2_ifu_mem_ctl.scala 418:77]
|
|
wire _T_1442 = _T_1439 & _T_1441; // @[el2_ifu_mem_ctl.scala 418:75]
|
|
wire _T_1447 = _T_1439 & bypass_index[0]; // @[el2_ifu_mem_ctl.scala 419:75]
|
|
wire _T_1448 = _T_1442 | _T_1447; // @[el2_ifu_mem_ctl.scala 418:95]
|
|
wire _T_1450 = bypass_valid_value_check & bypass_index[1]; // @[el2_ifu_mem_ctl.scala 420:56]
|
|
wire _T_1453 = _T_1450 & _T_1441; // @[el2_ifu_mem_ctl.scala 420:74]
|
|
wire _T_1454 = _T_1448 | _T_1453; // @[el2_ifu_mem_ctl.scala 419:94]
|
|
wire _T_1458 = _T_1450 & bypass_index[0]; // @[el2_ifu_mem_ctl.scala 421:51]
|
|
wire [2:0] bypass_index_5_3_inc = bypass_index[4:2] + 3'h1; // @[el2_ifu_mem_ctl.scala 416:70]
|
|
wire _T_1459 = bypass_index_5_3_inc == 3'h0; // @[el2_ifu_mem_ctl.scala 421:132]
|
|
wire _T_1475 = _T_1459 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72]
|
|
wire _T_1461 = bypass_index_5_3_inc == 3'h1; // @[el2_ifu_mem_ctl.scala 421:132]
|
|
wire _T_1476 = _T_1461 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72]
|
|
wire _T_1483 = _T_1475 | _T_1476; // @[Mux.scala 27:72]
|
|
wire _T_1463 = bypass_index_5_3_inc == 3'h2; // @[el2_ifu_mem_ctl.scala 421:132]
|
|
wire _T_1477 = _T_1463 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72]
|
|
wire _T_1484 = _T_1483 | _T_1477; // @[Mux.scala 27:72]
|
|
wire _T_1465 = bypass_index_5_3_inc == 3'h3; // @[el2_ifu_mem_ctl.scala 421:132]
|
|
wire _T_1478 = _T_1465 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72]
|
|
wire _T_1485 = _T_1484 | _T_1478; // @[Mux.scala 27:72]
|
|
wire _T_1467 = bypass_index_5_3_inc == 3'h4; // @[el2_ifu_mem_ctl.scala 421:132]
|
|
wire _T_1479 = _T_1467 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72]
|
|
wire _T_1486 = _T_1485 | _T_1479; // @[Mux.scala 27:72]
|
|
wire _T_1469 = bypass_index_5_3_inc == 3'h5; // @[el2_ifu_mem_ctl.scala 421:132]
|
|
wire _T_1480 = _T_1469 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72]
|
|
wire _T_1487 = _T_1486 | _T_1480; // @[Mux.scala 27:72]
|
|
wire _T_1471 = bypass_index_5_3_inc == 3'h6; // @[el2_ifu_mem_ctl.scala 421:132]
|
|
wire _T_1481 = _T_1471 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72]
|
|
wire _T_1488 = _T_1487 | _T_1481; // @[Mux.scala 27:72]
|
|
wire _T_1473 = bypass_index_5_3_inc == 3'h7; // @[el2_ifu_mem_ctl.scala 421:132]
|
|
wire _T_1482 = _T_1473 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72]
|
|
wire _T_1489 = _T_1488 | _T_1482; // @[Mux.scala 27:72]
|
|
wire _T_1491 = _T_1458 & _T_1489; // @[el2_ifu_mem_ctl.scala 421:69]
|
|
wire _T_1492 = _T_1454 | _T_1491; // @[el2_ifu_mem_ctl.scala 420:94]
|
|
wire [4:0] _GEN_446 = {{2'd0}, bypass_index[4:2]}; // @[el2_ifu_mem_ctl.scala 422:95]
|
|
wire _T_1495 = _GEN_446 == 5'h1f; // @[el2_ifu_mem_ctl.scala 422:95]
|
|
wire _T_1496 = bypass_valid_value_check & _T_1495; // @[el2_ifu_mem_ctl.scala 422:56]
|
|
wire bypass_data_ready_in = _T_1492 | _T_1496; // @[el2_ifu_mem_ctl.scala 421:181]
|
|
wire _T_1497 = bypass_data_ready_in & crit_wd_byp_ok_ff; // @[el2_ifu_mem_ctl.scala 426:53]
|
|
wire _T_1498 = _T_1497 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 426:73]
|
|
wire _T_1500 = _T_1498 & _T_319; // @[el2_ifu_mem_ctl.scala 426:96]
|
|
wire _T_1502 = _T_1500 & _T_58; // @[el2_ifu_mem_ctl.scala 426:118]
|
|
wire _T_1504 = crit_wd_byp_ok_ff & _T_17; // @[el2_ifu_mem_ctl.scala 427:73]
|
|
wire _T_1506 = _T_1504 & _T_319; // @[el2_ifu_mem_ctl.scala 427:96]
|
|
wire _T_1508 = _T_1506 & _T_58; // @[el2_ifu_mem_ctl.scala 427:118]
|
|
wire _T_1509 = _T_1502 | _T_1508; // @[el2_ifu_mem_ctl.scala 426:143]
|
|
reg ic_crit_wd_rdy_new_ff; // @[el2_ifu_mem_ctl.scala 429:58]
|
|
wire _T_1510 = ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff; // @[el2_ifu_mem_ctl.scala 428:54]
|
|
wire _T_1511 = ~fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 428:76]
|
|
wire _T_1512 = _T_1510 & _T_1511; // @[el2_ifu_mem_ctl.scala 428:74]
|
|
wire _T_1514 = _T_1512 & _T_319; // @[el2_ifu_mem_ctl.scala 428:96]
|
|
wire ic_crit_wd_rdy_new_in = _T_1509 | _T_1514; // @[el2_ifu_mem_ctl.scala 427:143]
|
|
wire ic_crit_wd_rdy = ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff; // @[el2_ifu_mem_ctl.scala 630:43]
|
|
wire _T_1251 = ic_crit_wd_rdy | _T_2219; // @[el2_ifu_mem_ctl.scala 373:38]
|
|
wire _T_1253 = _T_1251 | _T_2235; // @[el2_ifu_mem_ctl.scala 373:64]
|
|
wire _T_1254 = ~_T_1253; // @[el2_ifu_mem_ctl.scala 373:21]
|
|
wire _T_1255 = ~fetch_req_iccm_f; // @[el2_ifu_mem_ctl.scala 373:98]
|
|
wire sel_ic_data = _T_1254 & _T_1255; // @[el2_ifu_mem_ctl.scala 373:96]
|
|
wire _T_2442 = io_ic_tag_perr & sel_ic_data; // @[el2_ifu_mem_ctl.scala 473:44]
|
|
wire _T_1608 = ifu_fetch_addr_int_f[1] & ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 440:31]
|
|
reg [7:0] ic_miss_buff_data_error; // @[el2_ifu_mem_ctl.scala 412:60]
|
|
wire _T_1552 = _T_1399 & ic_miss_buff_data_error[0]; // @[Mux.scala 27:72]
|
|
wire _T_1553 = _T_1402 & ic_miss_buff_data_error[1]; // @[Mux.scala 27:72]
|
|
wire _T_1560 = _T_1552 | _T_1553; // @[Mux.scala 27:72]
|
|
wire _T_1554 = _T_1405 & ic_miss_buff_data_error[2]; // @[Mux.scala 27:72]
|
|
wire _T_1561 = _T_1560 | _T_1554; // @[Mux.scala 27:72]
|
|
wire _T_1555 = _T_1408 & ic_miss_buff_data_error[3]; // @[Mux.scala 27:72]
|
|
wire _T_1562 = _T_1561 | _T_1555; // @[Mux.scala 27:72]
|
|
wire _T_1556 = _T_1411 & ic_miss_buff_data_error[4]; // @[Mux.scala 27:72]
|
|
wire _T_1563 = _T_1562 | _T_1556; // @[Mux.scala 27:72]
|
|
wire _T_1557 = _T_1414 & ic_miss_buff_data_error[5]; // @[Mux.scala 27:72]
|
|
wire _T_1564 = _T_1563 | _T_1557; // @[Mux.scala 27:72]
|
|
wire _T_1558 = _T_1417 & ic_miss_buff_data_error[6]; // @[Mux.scala 27:72]
|
|
wire _T_1565 = _T_1564 | _T_1558; // @[Mux.scala 27:72]
|
|
wire _T_1559 = _T_1420 & ic_miss_buff_data_error[7]; // @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_error_bypass = _T_1565 | _T_1559; // @[Mux.scala 27:72]
|
|
wire _T_1591 = _T_2152 & ic_miss_buff_data_error[0]; // @[Mux.scala 27:72]
|
|
wire _T_1592 = _T_2155 & ic_miss_buff_data_error[1]; // @[Mux.scala 27:72]
|
|
wire _T_1599 = _T_1591 | _T_1592; // @[Mux.scala 27:72]
|
|
wire _T_1593 = _T_2158 & ic_miss_buff_data_error[2]; // @[Mux.scala 27:72]
|
|
wire _T_1600 = _T_1599 | _T_1593; // @[Mux.scala 27:72]
|
|
wire _T_1594 = _T_2161 & ic_miss_buff_data_error[3]; // @[Mux.scala 27:72]
|
|
wire _T_1601 = _T_1600 | _T_1594; // @[Mux.scala 27:72]
|
|
wire _T_1595 = _T_2164 & ic_miss_buff_data_error[4]; // @[Mux.scala 27:72]
|
|
wire _T_1602 = _T_1601 | _T_1595; // @[Mux.scala 27:72]
|
|
wire _T_1596 = _T_2167 & ic_miss_buff_data_error[5]; // @[Mux.scala 27:72]
|
|
wire _T_1603 = _T_1602 | _T_1596; // @[Mux.scala 27:72]
|
|
wire _T_1597 = _T_2170 & ic_miss_buff_data_error[6]; // @[Mux.scala 27:72]
|
|
wire _T_1604 = _T_1603 | _T_1597; // @[Mux.scala 27:72]
|
|
wire _T_1598 = _T_2173 & ic_miss_buff_data_error[7]; // @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_error_bypass_inc = _T_1604 | _T_1598; // @[Mux.scala 27:72]
|
|
wire _T_1609 = ic_miss_buff_data_error_bypass | ic_miss_buff_data_error_bypass_inc; // @[el2_ifu_mem_ctl.scala 442:70]
|
|
wire ifu_byp_data_err_new = _T_1608 ? ic_miss_buff_data_error_bypass : _T_1609; // @[el2_ifu_mem_ctl.scala 440:56]
|
|
wire ifc_bus_acc_fault_f = ic_byp_hit_f & ifu_byp_data_err_new; // @[el2_ifu_mem_ctl.scala 384:42]
|
|
wire _T_2443 = ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f; // @[el2_ifu_mem_ctl.scala 473:91]
|
|
wire _T_2444 = ~_T_2443; // @[el2_ifu_mem_ctl.scala 473:60]
|
|
wire ic_rd_parity_final_err = _T_2442 & _T_2444; // @[el2_ifu_mem_ctl.scala 473:58]
|
|
reg ic_debug_ict_array_sel_ff; // @[el2_ifu_mem_ctl.scala 838:63]
|
|
reg ic_tag_valid_out_1_0; // @[Reg.scala 27:20]
|
|
wire _T_9322 = _T_4619 & ic_tag_valid_out_1_0; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
reg ic_tag_valid_out_1_1; // @[Reg.scala 27:20]
|
|
wire _T_9324 = _T_4620 & ic_tag_valid_out_1_1; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9577 = _T_9322 | _T_9324; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_2; // @[Reg.scala 27:20]
|
|
wire _T_9326 = _T_4621 & ic_tag_valid_out_1_2; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9578 = _T_9577 | _T_9326; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_3; // @[Reg.scala 27:20]
|
|
wire _T_9328 = _T_4622 & ic_tag_valid_out_1_3; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9579 = _T_9578 | _T_9328; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_4; // @[Reg.scala 27:20]
|
|
wire _T_9330 = _T_4623 & ic_tag_valid_out_1_4; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9580 = _T_9579 | _T_9330; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_5; // @[Reg.scala 27:20]
|
|
wire _T_9332 = _T_4624 & ic_tag_valid_out_1_5; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9581 = _T_9580 | _T_9332; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_6; // @[Reg.scala 27:20]
|
|
wire _T_9334 = _T_4625 & ic_tag_valid_out_1_6; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9582 = _T_9581 | _T_9334; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_7; // @[Reg.scala 27:20]
|
|
wire _T_9336 = _T_4626 & ic_tag_valid_out_1_7; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9583 = _T_9582 | _T_9336; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_8; // @[Reg.scala 27:20]
|
|
wire _T_9338 = _T_4627 & ic_tag_valid_out_1_8; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9584 = _T_9583 | _T_9338; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_9; // @[Reg.scala 27:20]
|
|
wire _T_9340 = _T_4628 & ic_tag_valid_out_1_9; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9585 = _T_9584 | _T_9340; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_10; // @[Reg.scala 27:20]
|
|
wire _T_9342 = _T_4629 & ic_tag_valid_out_1_10; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9586 = _T_9585 | _T_9342; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_11; // @[Reg.scala 27:20]
|
|
wire _T_9344 = _T_4630 & ic_tag_valid_out_1_11; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9587 = _T_9586 | _T_9344; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_12; // @[Reg.scala 27:20]
|
|
wire _T_9346 = _T_4631 & ic_tag_valid_out_1_12; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9588 = _T_9587 | _T_9346; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_13; // @[Reg.scala 27:20]
|
|
wire _T_9348 = _T_4632 & ic_tag_valid_out_1_13; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9589 = _T_9588 | _T_9348; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_14; // @[Reg.scala 27:20]
|
|
wire _T_9350 = _T_4633 & ic_tag_valid_out_1_14; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9590 = _T_9589 | _T_9350; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_15; // @[Reg.scala 27:20]
|
|
wire _T_9352 = _T_4634 & ic_tag_valid_out_1_15; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9591 = _T_9590 | _T_9352; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_16; // @[Reg.scala 27:20]
|
|
wire _T_9354 = _T_4635 & ic_tag_valid_out_1_16; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9592 = _T_9591 | _T_9354; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_17; // @[Reg.scala 27:20]
|
|
wire _T_9356 = _T_4636 & ic_tag_valid_out_1_17; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9593 = _T_9592 | _T_9356; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_18; // @[Reg.scala 27:20]
|
|
wire _T_9358 = _T_4637 & ic_tag_valid_out_1_18; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9594 = _T_9593 | _T_9358; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_19; // @[Reg.scala 27:20]
|
|
wire _T_9360 = _T_4638 & ic_tag_valid_out_1_19; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9595 = _T_9594 | _T_9360; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_20; // @[Reg.scala 27:20]
|
|
wire _T_9362 = _T_4639 & ic_tag_valid_out_1_20; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9596 = _T_9595 | _T_9362; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_21; // @[Reg.scala 27:20]
|
|
wire _T_9364 = _T_4640 & ic_tag_valid_out_1_21; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9597 = _T_9596 | _T_9364; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_22; // @[Reg.scala 27:20]
|
|
wire _T_9366 = _T_4641 & ic_tag_valid_out_1_22; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9598 = _T_9597 | _T_9366; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_23; // @[Reg.scala 27:20]
|
|
wire _T_9368 = _T_4642 & ic_tag_valid_out_1_23; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9599 = _T_9598 | _T_9368; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_24; // @[Reg.scala 27:20]
|
|
wire _T_9370 = _T_4643 & ic_tag_valid_out_1_24; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9600 = _T_9599 | _T_9370; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_25; // @[Reg.scala 27:20]
|
|
wire _T_9372 = _T_4644 & ic_tag_valid_out_1_25; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9601 = _T_9600 | _T_9372; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_26; // @[Reg.scala 27:20]
|
|
wire _T_9374 = _T_4645 & ic_tag_valid_out_1_26; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9602 = _T_9601 | _T_9374; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_27; // @[Reg.scala 27:20]
|
|
wire _T_9376 = _T_4646 & ic_tag_valid_out_1_27; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9603 = _T_9602 | _T_9376; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_28; // @[Reg.scala 27:20]
|
|
wire _T_9378 = _T_4647 & ic_tag_valid_out_1_28; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9604 = _T_9603 | _T_9378; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_29; // @[Reg.scala 27:20]
|
|
wire _T_9380 = _T_4648 & ic_tag_valid_out_1_29; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9605 = _T_9604 | _T_9380; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_30; // @[Reg.scala 27:20]
|
|
wire _T_9382 = _T_4649 & ic_tag_valid_out_1_30; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9606 = _T_9605 | _T_9382; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_31; // @[Reg.scala 27:20]
|
|
wire _T_9384 = _T_4650 & ic_tag_valid_out_1_31; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9607 = _T_9606 | _T_9384; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_32; // @[Reg.scala 27:20]
|
|
wire _T_9386 = _T_4651 & ic_tag_valid_out_1_32; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9608 = _T_9607 | _T_9386; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_33; // @[Reg.scala 27:20]
|
|
wire _T_9388 = _T_4652 & ic_tag_valid_out_1_33; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9609 = _T_9608 | _T_9388; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_34; // @[Reg.scala 27:20]
|
|
wire _T_9390 = _T_4653 & ic_tag_valid_out_1_34; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9610 = _T_9609 | _T_9390; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_35; // @[Reg.scala 27:20]
|
|
wire _T_9392 = _T_4654 & ic_tag_valid_out_1_35; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9611 = _T_9610 | _T_9392; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_36; // @[Reg.scala 27:20]
|
|
wire _T_9394 = _T_4655 & ic_tag_valid_out_1_36; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9612 = _T_9611 | _T_9394; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_37; // @[Reg.scala 27:20]
|
|
wire _T_9396 = _T_4656 & ic_tag_valid_out_1_37; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9613 = _T_9612 | _T_9396; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_38; // @[Reg.scala 27:20]
|
|
wire _T_9398 = _T_4657 & ic_tag_valid_out_1_38; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9614 = _T_9613 | _T_9398; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_39; // @[Reg.scala 27:20]
|
|
wire _T_9400 = _T_4658 & ic_tag_valid_out_1_39; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9615 = _T_9614 | _T_9400; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_40; // @[Reg.scala 27:20]
|
|
wire _T_9402 = _T_4659 & ic_tag_valid_out_1_40; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9616 = _T_9615 | _T_9402; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_41; // @[Reg.scala 27:20]
|
|
wire _T_9404 = _T_4660 & ic_tag_valid_out_1_41; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9617 = _T_9616 | _T_9404; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_42; // @[Reg.scala 27:20]
|
|
wire _T_9406 = _T_4661 & ic_tag_valid_out_1_42; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9618 = _T_9617 | _T_9406; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_43; // @[Reg.scala 27:20]
|
|
wire _T_9408 = _T_4662 & ic_tag_valid_out_1_43; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9619 = _T_9618 | _T_9408; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_44; // @[Reg.scala 27:20]
|
|
wire _T_9410 = _T_4663 & ic_tag_valid_out_1_44; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9620 = _T_9619 | _T_9410; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_45; // @[Reg.scala 27:20]
|
|
wire _T_9412 = _T_4664 & ic_tag_valid_out_1_45; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9621 = _T_9620 | _T_9412; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_46; // @[Reg.scala 27:20]
|
|
wire _T_9414 = _T_4665 & ic_tag_valid_out_1_46; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9622 = _T_9621 | _T_9414; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_47; // @[Reg.scala 27:20]
|
|
wire _T_9416 = _T_4666 & ic_tag_valid_out_1_47; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9623 = _T_9622 | _T_9416; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_48; // @[Reg.scala 27:20]
|
|
wire _T_9418 = _T_4667 & ic_tag_valid_out_1_48; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9624 = _T_9623 | _T_9418; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_49; // @[Reg.scala 27:20]
|
|
wire _T_9420 = _T_4668 & ic_tag_valid_out_1_49; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9625 = _T_9624 | _T_9420; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_50; // @[Reg.scala 27:20]
|
|
wire _T_9422 = _T_4669 & ic_tag_valid_out_1_50; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9626 = _T_9625 | _T_9422; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_51; // @[Reg.scala 27:20]
|
|
wire _T_9424 = _T_4670 & ic_tag_valid_out_1_51; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9627 = _T_9626 | _T_9424; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_52; // @[Reg.scala 27:20]
|
|
wire _T_9426 = _T_4671 & ic_tag_valid_out_1_52; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9628 = _T_9627 | _T_9426; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_53; // @[Reg.scala 27:20]
|
|
wire _T_9428 = _T_4672 & ic_tag_valid_out_1_53; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9629 = _T_9628 | _T_9428; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_54; // @[Reg.scala 27:20]
|
|
wire _T_9430 = _T_4673 & ic_tag_valid_out_1_54; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9630 = _T_9629 | _T_9430; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_55; // @[Reg.scala 27:20]
|
|
wire _T_9432 = _T_4674 & ic_tag_valid_out_1_55; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9631 = _T_9630 | _T_9432; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_56; // @[Reg.scala 27:20]
|
|
wire _T_9434 = _T_4675 & ic_tag_valid_out_1_56; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9632 = _T_9631 | _T_9434; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_57; // @[Reg.scala 27:20]
|
|
wire _T_9436 = _T_4676 & ic_tag_valid_out_1_57; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9633 = _T_9632 | _T_9436; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_58; // @[Reg.scala 27:20]
|
|
wire _T_9438 = _T_4677 & ic_tag_valid_out_1_58; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9634 = _T_9633 | _T_9438; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_59; // @[Reg.scala 27:20]
|
|
wire _T_9440 = _T_4678 & ic_tag_valid_out_1_59; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9635 = _T_9634 | _T_9440; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_60; // @[Reg.scala 27:20]
|
|
wire _T_9442 = _T_4679 & ic_tag_valid_out_1_60; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9636 = _T_9635 | _T_9442; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_61; // @[Reg.scala 27:20]
|
|
wire _T_9444 = _T_4680 & ic_tag_valid_out_1_61; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9637 = _T_9636 | _T_9444; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_62; // @[Reg.scala 27:20]
|
|
wire _T_9446 = _T_4681 & ic_tag_valid_out_1_62; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9638 = _T_9637 | _T_9446; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_63; // @[Reg.scala 27:20]
|
|
wire _T_9448 = _T_4682 & ic_tag_valid_out_1_63; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9639 = _T_9638 | _T_9448; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_64; // @[Reg.scala 27:20]
|
|
wire _T_9450 = _T_4683 & ic_tag_valid_out_1_64; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9640 = _T_9639 | _T_9450; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_65; // @[Reg.scala 27:20]
|
|
wire _T_9452 = _T_4684 & ic_tag_valid_out_1_65; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9641 = _T_9640 | _T_9452; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_66; // @[Reg.scala 27:20]
|
|
wire _T_9454 = _T_4685 & ic_tag_valid_out_1_66; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9642 = _T_9641 | _T_9454; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_67; // @[Reg.scala 27:20]
|
|
wire _T_9456 = _T_4686 & ic_tag_valid_out_1_67; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9643 = _T_9642 | _T_9456; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_68; // @[Reg.scala 27:20]
|
|
wire _T_9458 = _T_4687 & ic_tag_valid_out_1_68; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9644 = _T_9643 | _T_9458; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_69; // @[Reg.scala 27:20]
|
|
wire _T_9460 = _T_4688 & ic_tag_valid_out_1_69; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9645 = _T_9644 | _T_9460; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_70; // @[Reg.scala 27:20]
|
|
wire _T_9462 = _T_4689 & ic_tag_valid_out_1_70; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9646 = _T_9645 | _T_9462; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_71; // @[Reg.scala 27:20]
|
|
wire _T_9464 = _T_4690 & ic_tag_valid_out_1_71; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9647 = _T_9646 | _T_9464; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_72; // @[Reg.scala 27:20]
|
|
wire _T_9466 = _T_4691 & ic_tag_valid_out_1_72; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9648 = _T_9647 | _T_9466; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_73; // @[Reg.scala 27:20]
|
|
wire _T_9468 = _T_4692 & ic_tag_valid_out_1_73; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9649 = _T_9648 | _T_9468; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_74; // @[Reg.scala 27:20]
|
|
wire _T_9470 = _T_4693 & ic_tag_valid_out_1_74; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9650 = _T_9649 | _T_9470; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_75; // @[Reg.scala 27:20]
|
|
wire _T_9472 = _T_4694 & ic_tag_valid_out_1_75; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9651 = _T_9650 | _T_9472; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_76; // @[Reg.scala 27:20]
|
|
wire _T_9474 = _T_4695 & ic_tag_valid_out_1_76; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9652 = _T_9651 | _T_9474; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_77; // @[Reg.scala 27:20]
|
|
wire _T_9476 = _T_4696 & ic_tag_valid_out_1_77; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9653 = _T_9652 | _T_9476; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_78; // @[Reg.scala 27:20]
|
|
wire _T_9478 = _T_4697 & ic_tag_valid_out_1_78; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9654 = _T_9653 | _T_9478; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_79; // @[Reg.scala 27:20]
|
|
wire _T_9480 = _T_4698 & ic_tag_valid_out_1_79; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9655 = _T_9654 | _T_9480; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_80; // @[Reg.scala 27:20]
|
|
wire _T_9482 = _T_4699 & ic_tag_valid_out_1_80; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9656 = _T_9655 | _T_9482; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_81; // @[Reg.scala 27:20]
|
|
wire _T_9484 = _T_4700 & ic_tag_valid_out_1_81; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9657 = _T_9656 | _T_9484; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_82; // @[Reg.scala 27:20]
|
|
wire _T_9486 = _T_4701 & ic_tag_valid_out_1_82; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9658 = _T_9657 | _T_9486; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_83; // @[Reg.scala 27:20]
|
|
wire _T_9488 = _T_4702 & ic_tag_valid_out_1_83; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9659 = _T_9658 | _T_9488; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_84; // @[Reg.scala 27:20]
|
|
wire _T_9490 = _T_4703 & ic_tag_valid_out_1_84; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9660 = _T_9659 | _T_9490; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_85; // @[Reg.scala 27:20]
|
|
wire _T_9492 = _T_4704 & ic_tag_valid_out_1_85; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9661 = _T_9660 | _T_9492; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_86; // @[Reg.scala 27:20]
|
|
wire _T_9494 = _T_4705 & ic_tag_valid_out_1_86; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9662 = _T_9661 | _T_9494; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_87; // @[Reg.scala 27:20]
|
|
wire _T_9496 = _T_4706 & ic_tag_valid_out_1_87; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9663 = _T_9662 | _T_9496; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_88; // @[Reg.scala 27:20]
|
|
wire _T_9498 = _T_4707 & ic_tag_valid_out_1_88; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9664 = _T_9663 | _T_9498; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_89; // @[Reg.scala 27:20]
|
|
wire _T_9500 = _T_4708 & ic_tag_valid_out_1_89; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9665 = _T_9664 | _T_9500; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_90; // @[Reg.scala 27:20]
|
|
wire _T_9502 = _T_4709 & ic_tag_valid_out_1_90; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9666 = _T_9665 | _T_9502; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_91; // @[Reg.scala 27:20]
|
|
wire _T_9504 = _T_4710 & ic_tag_valid_out_1_91; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9667 = _T_9666 | _T_9504; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_92; // @[Reg.scala 27:20]
|
|
wire _T_9506 = _T_4711 & ic_tag_valid_out_1_92; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9668 = _T_9667 | _T_9506; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_93; // @[Reg.scala 27:20]
|
|
wire _T_9508 = _T_4712 & ic_tag_valid_out_1_93; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9669 = _T_9668 | _T_9508; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_94; // @[Reg.scala 27:20]
|
|
wire _T_9510 = _T_4713 & ic_tag_valid_out_1_94; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9670 = _T_9669 | _T_9510; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_95; // @[Reg.scala 27:20]
|
|
wire _T_9512 = _T_4714 & ic_tag_valid_out_1_95; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9671 = _T_9670 | _T_9512; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_96; // @[Reg.scala 27:20]
|
|
wire _T_9514 = _T_4715 & ic_tag_valid_out_1_96; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9672 = _T_9671 | _T_9514; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_97; // @[Reg.scala 27:20]
|
|
wire _T_9516 = _T_4716 & ic_tag_valid_out_1_97; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9673 = _T_9672 | _T_9516; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_98; // @[Reg.scala 27:20]
|
|
wire _T_9518 = _T_4717 & ic_tag_valid_out_1_98; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9674 = _T_9673 | _T_9518; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_99; // @[Reg.scala 27:20]
|
|
wire _T_9520 = _T_4718 & ic_tag_valid_out_1_99; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9675 = _T_9674 | _T_9520; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_100; // @[Reg.scala 27:20]
|
|
wire _T_9522 = _T_4719 & ic_tag_valid_out_1_100; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9676 = _T_9675 | _T_9522; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_101; // @[Reg.scala 27:20]
|
|
wire _T_9524 = _T_4720 & ic_tag_valid_out_1_101; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9677 = _T_9676 | _T_9524; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_102; // @[Reg.scala 27:20]
|
|
wire _T_9526 = _T_4721 & ic_tag_valid_out_1_102; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9678 = _T_9677 | _T_9526; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_103; // @[Reg.scala 27:20]
|
|
wire _T_9528 = _T_4722 & ic_tag_valid_out_1_103; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9679 = _T_9678 | _T_9528; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_104; // @[Reg.scala 27:20]
|
|
wire _T_9530 = _T_4723 & ic_tag_valid_out_1_104; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9680 = _T_9679 | _T_9530; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_105; // @[Reg.scala 27:20]
|
|
wire _T_9532 = _T_4724 & ic_tag_valid_out_1_105; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9681 = _T_9680 | _T_9532; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_106; // @[Reg.scala 27:20]
|
|
wire _T_9534 = _T_4725 & ic_tag_valid_out_1_106; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9682 = _T_9681 | _T_9534; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_107; // @[Reg.scala 27:20]
|
|
wire _T_9536 = _T_4726 & ic_tag_valid_out_1_107; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9683 = _T_9682 | _T_9536; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_108; // @[Reg.scala 27:20]
|
|
wire _T_9538 = _T_4727 & ic_tag_valid_out_1_108; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9684 = _T_9683 | _T_9538; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_109; // @[Reg.scala 27:20]
|
|
wire _T_9540 = _T_4728 & ic_tag_valid_out_1_109; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9685 = _T_9684 | _T_9540; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_110; // @[Reg.scala 27:20]
|
|
wire _T_9542 = _T_4729 & ic_tag_valid_out_1_110; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9686 = _T_9685 | _T_9542; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_111; // @[Reg.scala 27:20]
|
|
wire _T_9544 = _T_4730 & ic_tag_valid_out_1_111; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9687 = _T_9686 | _T_9544; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_112; // @[Reg.scala 27:20]
|
|
wire _T_9546 = _T_4731 & ic_tag_valid_out_1_112; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9688 = _T_9687 | _T_9546; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_113; // @[Reg.scala 27:20]
|
|
wire _T_9548 = _T_4732 & ic_tag_valid_out_1_113; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9689 = _T_9688 | _T_9548; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_114; // @[Reg.scala 27:20]
|
|
wire _T_9550 = _T_4733 & ic_tag_valid_out_1_114; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9690 = _T_9689 | _T_9550; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_115; // @[Reg.scala 27:20]
|
|
wire _T_9552 = _T_4734 & ic_tag_valid_out_1_115; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9691 = _T_9690 | _T_9552; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_116; // @[Reg.scala 27:20]
|
|
wire _T_9554 = _T_4735 & ic_tag_valid_out_1_116; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9692 = _T_9691 | _T_9554; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_117; // @[Reg.scala 27:20]
|
|
wire _T_9556 = _T_4736 & ic_tag_valid_out_1_117; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9693 = _T_9692 | _T_9556; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_118; // @[Reg.scala 27:20]
|
|
wire _T_9558 = _T_4737 & ic_tag_valid_out_1_118; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9694 = _T_9693 | _T_9558; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_119; // @[Reg.scala 27:20]
|
|
wire _T_9560 = _T_4738 & ic_tag_valid_out_1_119; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9695 = _T_9694 | _T_9560; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_120; // @[Reg.scala 27:20]
|
|
wire _T_9562 = _T_4739 & ic_tag_valid_out_1_120; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9696 = _T_9695 | _T_9562; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_121; // @[Reg.scala 27:20]
|
|
wire _T_9564 = _T_4740 & ic_tag_valid_out_1_121; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9697 = _T_9696 | _T_9564; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_122; // @[Reg.scala 27:20]
|
|
wire _T_9566 = _T_4741 & ic_tag_valid_out_1_122; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9698 = _T_9697 | _T_9566; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_123; // @[Reg.scala 27:20]
|
|
wire _T_9568 = _T_4742 & ic_tag_valid_out_1_123; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9699 = _T_9698 | _T_9568; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_124; // @[Reg.scala 27:20]
|
|
wire _T_9570 = _T_4743 & ic_tag_valid_out_1_124; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9700 = _T_9699 | _T_9570; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_125; // @[Reg.scala 27:20]
|
|
wire _T_9572 = _T_4744 & ic_tag_valid_out_1_125; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9701 = _T_9700 | _T_9572; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_126; // @[Reg.scala 27:20]
|
|
wire _T_9574 = _T_4745 & ic_tag_valid_out_1_126; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9702 = _T_9701 | _T_9574; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_1_127; // @[Reg.scala 27:20]
|
|
wire _T_9576 = _T_4746 & ic_tag_valid_out_1_127; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9703 = _T_9702 | _T_9576; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_0; // @[Reg.scala 27:20]
|
|
wire _T_8939 = _T_4619 & ic_tag_valid_out_0_0; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
reg ic_tag_valid_out_0_1; // @[Reg.scala 27:20]
|
|
wire _T_8941 = _T_4620 & ic_tag_valid_out_0_1; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9194 = _T_8939 | _T_8941; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_2; // @[Reg.scala 27:20]
|
|
wire _T_8943 = _T_4621 & ic_tag_valid_out_0_2; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9195 = _T_9194 | _T_8943; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_3; // @[Reg.scala 27:20]
|
|
wire _T_8945 = _T_4622 & ic_tag_valid_out_0_3; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9196 = _T_9195 | _T_8945; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_4; // @[Reg.scala 27:20]
|
|
wire _T_8947 = _T_4623 & ic_tag_valid_out_0_4; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9197 = _T_9196 | _T_8947; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_5; // @[Reg.scala 27:20]
|
|
wire _T_8949 = _T_4624 & ic_tag_valid_out_0_5; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9198 = _T_9197 | _T_8949; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_6; // @[Reg.scala 27:20]
|
|
wire _T_8951 = _T_4625 & ic_tag_valid_out_0_6; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9199 = _T_9198 | _T_8951; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_7; // @[Reg.scala 27:20]
|
|
wire _T_8953 = _T_4626 & ic_tag_valid_out_0_7; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9200 = _T_9199 | _T_8953; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_8; // @[Reg.scala 27:20]
|
|
wire _T_8955 = _T_4627 & ic_tag_valid_out_0_8; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9201 = _T_9200 | _T_8955; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_9; // @[Reg.scala 27:20]
|
|
wire _T_8957 = _T_4628 & ic_tag_valid_out_0_9; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9202 = _T_9201 | _T_8957; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_10; // @[Reg.scala 27:20]
|
|
wire _T_8959 = _T_4629 & ic_tag_valid_out_0_10; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9203 = _T_9202 | _T_8959; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_11; // @[Reg.scala 27:20]
|
|
wire _T_8961 = _T_4630 & ic_tag_valid_out_0_11; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9204 = _T_9203 | _T_8961; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_12; // @[Reg.scala 27:20]
|
|
wire _T_8963 = _T_4631 & ic_tag_valid_out_0_12; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9205 = _T_9204 | _T_8963; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_13; // @[Reg.scala 27:20]
|
|
wire _T_8965 = _T_4632 & ic_tag_valid_out_0_13; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9206 = _T_9205 | _T_8965; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_14; // @[Reg.scala 27:20]
|
|
wire _T_8967 = _T_4633 & ic_tag_valid_out_0_14; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9207 = _T_9206 | _T_8967; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_15; // @[Reg.scala 27:20]
|
|
wire _T_8969 = _T_4634 & ic_tag_valid_out_0_15; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9208 = _T_9207 | _T_8969; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_16; // @[Reg.scala 27:20]
|
|
wire _T_8971 = _T_4635 & ic_tag_valid_out_0_16; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9209 = _T_9208 | _T_8971; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_17; // @[Reg.scala 27:20]
|
|
wire _T_8973 = _T_4636 & ic_tag_valid_out_0_17; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9210 = _T_9209 | _T_8973; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_18; // @[Reg.scala 27:20]
|
|
wire _T_8975 = _T_4637 & ic_tag_valid_out_0_18; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9211 = _T_9210 | _T_8975; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_19; // @[Reg.scala 27:20]
|
|
wire _T_8977 = _T_4638 & ic_tag_valid_out_0_19; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9212 = _T_9211 | _T_8977; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_20; // @[Reg.scala 27:20]
|
|
wire _T_8979 = _T_4639 & ic_tag_valid_out_0_20; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9213 = _T_9212 | _T_8979; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_21; // @[Reg.scala 27:20]
|
|
wire _T_8981 = _T_4640 & ic_tag_valid_out_0_21; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9214 = _T_9213 | _T_8981; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_22; // @[Reg.scala 27:20]
|
|
wire _T_8983 = _T_4641 & ic_tag_valid_out_0_22; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9215 = _T_9214 | _T_8983; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_23; // @[Reg.scala 27:20]
|
|
wire _T_8985 = _T_4642 & ic_tag_valid_out_0_23; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9216 = _T_9215 | _T_8985; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_24; // @[Reg.scala 27:20]
|
|
wire _T_8987 = _T_4643 & ic_tag_valid_out_0_24; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9217 = _T_9216 | _T_8987; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_25; // @[Reg.scala 27:20]
|
|
wire _T_8989 = _T_4644 & ic_tag_valid_out_0_25; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9218 = _T_9217 | _T_8989; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_26; // @[Reg.scala 27:20]
|
|
wire _T_8991 = _T_4645 & ic_tag_valid_out_0_26; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9219 = _T_9218 | _T_8991; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_27; // @[Reg.scala 27:20]
|
|
wire _T_8993 = _T_4646 & ic_tag_valid_out_0_27; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9220 = _T_9219 | _T_8993; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_28; // @[Reg.scala 27:20]
|
|
wire _T_8995 = _T_4647 & ic_tag_valid_out_0_28; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9221 = _T_9220 | _T_8995; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_29; // @[Reg.scala 27:20]
|
|
wire _T_8997 = _T_4648 & ic_tag_valid_out_0_29; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9222 = _T_9221 | _T_8997; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_30; // @[Reg.scala 27:20]
|
|
wire _T_8999 = _T_4649 & ic_tag_valid_out_0_30; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9223 = _T_9222 | _T_8999; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_31; // @[Reg.scala 27:20]
|
|
wire _T_9001 = _T_4650 & ic_tag_valid_out_0_31; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9224 = _T_9223 | _T_9001; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_32; // @[Reg.scala 27:20]
|
|
wire _T_9003 = _T_4651 & ic_tag_valid_out_0_32; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9225 = _T_9224 | _T_9003; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_33; // @[Reg.scala 27:20]
|
|
wire _T_9005 = _T_4652 & ic_tag_valid_out_0_33; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9226 = _T_9225 | _T_9005; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_34; // @[Reg.scala 27:20]
|
|
wire _T_9007 = _T_4653 & ic_tag_valid_out_0_34; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9227 = _T_9226 | _T_9007; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_35; // @[Reg.scala 27:20]
|
|
wire _T_9009 = _T_4654 & ic_tag_valid_out_0_35; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9228 = _T_9227 | _T_9009; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_36; // @[Reg.scala 27:20]
|
|
wire _T_9011 = _T_4655 & ic_tag_valid_out_0_36; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9229 = _T_9228 | _T_9011; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_37; // @[Reg.scala 27:20]
|
|
wire _T_9013 = _T_4656 & ic_tag_valid_out_0_37; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9230 = _T_9229 | _T_9013; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_38; // @[Reg.scala 27:20]
|
|
wire _T_9015 = _T_4657 & ic_tag_valid_out_0_38; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9231 = _T_9230 | _T_9015; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_39; // @[Reg.scala 27:20]
|
|
wire _T_9017 = _T_4658 & ic_tag_valid_out_0_39; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9232 = _T_9231 | _T_9017; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_40; // @[Reg.scala 27:20]
|
|
wire _T_9019 = _T_4659 & ic_tag_valid_out_0_40; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9233 = _T_9232 | _T_9019; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_41; // @[Reg.scala 27:20]
|
|
wire _T_9021 = _T_4660 & ic_tag_valid_out_0_41; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9234 = _T_9233 | _T_9021; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_42; // @[Reg.scala 27:20]
|
|
wire _T_9023 = _T_4661 & ic_tag_valid_out_0_42; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9235 = _T_9234 | _T_9023; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_43; // @[Reg.scala 27:20]
|
|
wire _T_9025 = _T_4662 & ic_tag_valid_out_0_43; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9236 = _T_9235 | _T_9025; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_44; // @[Reg.scala 27:20]
|
|
wire _T_9027 = _T_4663 & ic_tag_valid_out_0_44; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9237 = _T_9236 | _T_9027; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_45; // @[Reg.scala 27:20]
|
|
wire _T_9029 = _T_4664 & ic_tag_valid_out_0_45; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9238 = _T_9237 | _T_9029; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_46; // @[Reg.scala 27:20]
|
|
wire _T_9031 = _T_4665 & ic_tag_valid_out_0_46; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9239 = _T_9238 | _T_9031; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_47; // @[Reg.scala 27:20]
|
|
wire _T_9033 = _T_4666 & ic_tag_valid_out_0_47; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9240 = _T_9239 | _T_9033; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_48; // @[Reg.scala 27:20]
|
|
wire _T_9035 = _T_4667 & ic_tag_valid_out_0_48; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9241 = _T_9240 | _T_9035; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_49; // @[Reg.scala 27:20]
|
|
wire _T_9037 = _T_4668 & ic_tag_valid_out_0_49; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9242 = _T_9241 | _T_9037; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_50; // @[Reg.scala 27:20]
|
|
wire _T_9039 = _T_4669 & ic_tag_valid_out_0_50; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9243 = _T_9242 | _T_9039; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_51; // @[Reg.scala 27:20]
|
|
wire _T_9041 = _T_4670 & ic_tag_valid_out_0_51; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9244 = _T_9243 | _T_9041; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_52; // @[Reg.scala 27:20]
|
|
wire _T_9043 = _T_4671 & ic_tag_valid_out_0_52; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9245 = _T_9244 | _T_9043; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_53; // @[Reg.scala 27:20]
|
|
wire _T_9045 = _T_4672 & ic_tag_valid_out_0_53; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9246 = _T_9245 | _T_9045; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_54; // @[Reg.scala 27:20]
|
|
wire _T_9047 = _T_4673 & ic_tag_valid_out_0_54; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9247 = _T_9246 | _T_9047; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_55; // @[Reg.scala 27:20]
|
|
wire _T_9049 = _T_4674 & ic_tag_valid_out_0_55; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9248 = _T_9247 | _T_9049; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_56; // @[Reg.scala 27:20]
|
|
wire _T_9051 = _T_4675 & ic_tag_valid_out_0_56; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9249 = _T_9248 | _T_9051; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_57; // @[Reg.scala 27:20]
|
|
wire _T_9053 = _T_4676 & ic_tag_valid_out_0_57; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9250 = _T_9249 | _T_9053; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_58; // @[Reg.scala 27:20]
|
|
wire _T_9055 = _T_4677 & ic_tag_valid_out_0_58; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9251 = _T_9250 | _T_9055; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_59; // @[Reg.scala 27:20]
|
|
wire _T_9057 = _T_4678 & ic_tag_valid_out_0_59; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9252 = _T_9251 | _T_9057; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_60; // @[Reg.scala 27:20]
|
|
wire _T_9059 = _T_4679 & ic_tag_valid_out_0_60; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9253 = _T_9252 | _T_9059; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_61; // @[Reg.scala 27:20]
|
|
wire _T_9061 = _T_4680 & ic_tag_valid_out_0_61; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9254 = _T_9253 | _T_9061; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_62; // @[Reg.scala 27:20]
|
|
wire _T_9063 = _T_4681 & ic_tag_valid_out_0_62; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9255 = _T_9254 | _T_9063; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_63; // @[Reg.scala 27:20]
|
|
wire _T_9065 = _T_4682 & ic_tag_valid_out_0_63; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9256 = _T_9255 | _T_9065; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_64; // @[Reg.scala 27:20]
|
|
wire _T_9067 = _T_4683 & ic_tag_valid_out_0_64; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9257 = _T_9256 | _T_9067; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_65; // @[Reg.scala 27:20]
|
|
wire _T_9069 = _T_4684 & ic_tag_valid_out_0_65; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9258 = _T_9257 | _T_9069; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_66; // @[Reg.scala 27:20]
|
|
wire _T_9071 = _T_4685 & ic_tag_valid_out_0_66; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9259 = _T_9258 | _T_9071; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_67; // @[Reg.scala 27:20]
|
|
wire _T_9073 = _T_4686 & ic_tag_valid_out_0_67; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9260 = _T_9259 | _T_9073; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_68; // @[Reg.scala 27:20]
|
|
wire _T_9075 = _T_4687 & ic_tag_valid_out_0_68; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9261 = _T_9260 | _T_9075; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_69; // @[Reg.scala 27:20]
|
|
wire _T_9077 = _T_4688 & ic_tag_valid_out_0_69; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9262 = _T_9261 | _T_9077; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_70; // @[Reg.scala 27:20]
|
|
wire _T_9079 = _T_4689 & ic_tag_valid_out_0_70; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9263 = _T_9262 | _T_9079; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_71; // @[Reg.scala 27:20]
|
|
wire _T_9081 = _T_4690 & ic_tag_valid_out_0_71; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9264 = _T_9263 | _T_9081; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_72; // @[Reg.scala 27:20]
|
|
wire _T_9083 = _T_4691 & ic_tag_valid_out_0_72; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9265 = _T_9264 | _T_9083; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_73; // @[Reg.scala 27:20]
|
|
wire _T_9085 = _T_4692 & ic_tag_valid_out_0_73; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9266 = _T_9265 | _T_9085; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_74; // @[Reg.scala 27:20]
|
|
wire _T_9087 = _T_4693 & ic_tag_valid_out_0_74; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9267 = _T_9266 | _T_9087; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_75; // @[Reg.scala 27:20]
|
|
wire _T_9089 = _T_4694 & ic_tag_valid_out_0_75; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9268 = _T_9267 | _T_9089; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_76; // @[Reg.scala 27:20]
|
|
wire _T_9091 = _T_4695 & ic_tag_valid_out_0_76; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9269 = _T_9268 | _T_9091; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_77; // @[Reg.scala 27:20]
|
|
wire _T_9093 = _T_4696 & ic_tag_valid_out_0_77; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9270 = _T_9269 | _T_9093; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_78; // @[Reg.scala 27:20]
|
|
wire _T_9095 = _T_4697 & ic_tag_valid_out_0_78; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9271 = _T_9270 | _T_9095; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_79; // @[Reg.scala 27:20]
|
|
wire _T_9097 = _T_4698 & ic_tag_valid_out_0_79; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9272 = _T_9271 | _T_9097; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_80; // @[Reg.scala 27:20]
|
|
wire _T_9099 = _T_4699 & ic_tag_valid_out_0_80; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9273 = _T_9272 | _T_9099; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_81; // @[Reg.scala 27:20]
|
|
wire _T_9101 = _T_4700 & ic_tag_valid_out_0_81; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9274 = _T_9273 | _T_9101; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_82; // @[Reg.scala 27:20]
|
|
wire _T_9103 = _T_4701 & ic_tag_valid_out_0_82; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9275 = _T_9274 | _T_9103; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_83; // @[Reg.scala 27:20]
|
|
wire _T_9105 = _T_4702 & ic_tag_valid_out_0_83; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9276 = _T_9275 | _T_9105; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_84; // @[Reg.scala 27:20]
|
|
wire _T_9107 = _T_4703 & ic_tag_valid_out_0_84; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9277 = _T_9276 | _T_9107; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_85; // @[Reg.scala 27:20]
|
|
wire _T_9109 = _T_4704 & ic_tag_valid_out_0_85; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9278 = _T_9277 | _T_9109; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_86; // @[Reg.scala 27:20]
|
|
wire _T_9111 = _T_4705 & ic_tag_valid_out_0_86; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9279 = _T_9278 | _T_9111; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_87; // @[Reg.scala 27:20]
|
|
wire _T_9113 = _T_4706 & ic_tag_valid_out_0_87; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9280 = _T_9279 | _T_9113; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_88; // @[Reg.scala 27:20]
|
|
wire _T_9115 = _T_4707 & ic_tag_valid_out_0_88; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9281 = _T_9280 | _T_9115; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_89; // @[Reg.scala 27:20]
|
|
wire _T_9117 = _T_4708 & ic_tag_valid_out_0_89; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9282 = _T_9281 | _T_9117; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_90; // @[Reg.scala 27:20]
|
|
wire _T_9119 = _T_4709 & ic_tag_valid_out_0_90; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9283 = _T_9282 | _T_9119; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_91; // @[Reg.scala 27:20]
|
|
wire _T_9121 = _T_4710 & ic_tag_valid_out_0_91; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9284 = _T_9283 | _T_9121; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_92; // @[Reg.scala 27:20]
|
|
wire _T_9123 = _T_4711 & ic_tag_valid_out_0_92; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9285 = _T_9284 | _T_9123; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_93; // @[Reg.scala 27:20]
|
|
wire _T_9125 = _T_4712 & ic_tag_valid_out_0_93; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9286 = _T_9285 | _T_9125; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_94; // @[Reg.scala 27:20]
|
|
wire _T_9127 = _T_4713 & ic_tag_valid_out_0_94; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9287 = _T_9286 | _T_9127; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_95; // @[Reg.scala 27:20]
|
|
wire _T_9129 = _T_4714 & ic_tag_valid_out_0_95; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9288 = _T_9287 | _T_9129; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_96; // @[Reg.scala 27:20]
|
|
wire _T_9131 = _T_4715 & ic_tag_valid_out_0_96; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9289 = _T_9288 | _T_9131; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_97; // @[Reg.scala 27:20]
|
|
wire _T_9133 = _T_4716 & ic_tag_valid_out_0_97; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9290 = _T_9289 | _T_9133; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_98; // @[Reg.scala 27:20]
|
|
wire _T_9135 = _T_4717 & ic_tag_valid_out_0_98; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9291 = _T_9290 | _T_9135; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_99; // @[Reg.scala 27:20]
|
|
wire _T_9137 = _T_4718 & ic_tag_valid_out_0_99; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9292 = _T_9291 | _T_9137; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_100; // @[Reg.scala 27:20]
|
|
wire _T_9139 = _T_4719 & ic_tag_valid_out_0_100; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9293 = _T_9292 | _T_9139; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_101; // @[Reg.scala 27:20]
|
|
wire _T_9141 = _T_4720 & ic_tag_valid_out_0_101; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9294 = _T_9293 | _T_9141; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_102; // @[Reg.scala 27:20]
|
|
wire _T_9143 = _T_4721 & ic_tag_valid_out_0_102; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9295 = _T_9294 | _T_9143; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_103; // @[Reg.scala 27:20]
|
|
wire _T_9145 = _T_4722 & ic_tag_valid_out_0_103; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9296 = _T_9295 | _T_9145; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_104; // @[Reg.scala 27:20]
|
|
wire _T_9147 = _T_4723 & ic_tag_valid_out_0_104; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9297 = _T_9296 | _T_9147; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_105; // @[Reg.scala 27:20]
|
|
wire _T_9149 = _T_4724 & ic_tag_valid_out_0_105; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9298 = _T_9297 | _T_9149; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_106; // @[Reg.scala 27:20]
|
|
wire _T_9151 = _T_4725 & ic_tag_valid_out_0_106; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9299 = _T_9298 | _T_9151; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_107; // @[Reg.scala 27:20]
|
|
wire _T_9153 = _T_4726 & ic_tag_valid_out_0_107; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9300 = _T_9299 | _T_9153; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_108; // @[Reg.scala 27:20]
|
|
wire _T_9155 = _T_4727 & ic_tag_valid_out_0_108; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9301 = _T_9300 | _T_9155; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_109; // @[Reg.scala 27:20]
|
|
wire _T_9157 = _T_4728 & ic_tag_valid_out_0_109; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9302 = _T_9301 | _T_9157; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_110; // @[Reg.scala 27:20]
|
|
wire _T_9159 = _T_4729 & ic_tag_valid_out_0_110; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9303 = _T_9302 | _T_9159; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_111; // @[Reg.scala 27:20]
|
|
wire _T_9161 = _T_4730 & ic_tag_valid_out_0_111; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9304 = _T_9303 | _T_9161; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_112; // @[Reg.scala 27:20]
|
|
wire _T_9163 = _T_4731 & ic_tag_valid_out_0_112; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9305 = _T_9304 | _T_9163; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_113; // @[Reg.scala 27:20]
|
|
wire _T_9165 = _T_4732 & ic_tag_valid_out_0_113; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9306 = _T_9305 | _T_9165; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_114; // @[Reg.scala 27:20]
|
|
wire _T_9167 = _T_4733 & ic_tag_valid_out_0_114; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9307 = _T_9306 | _T_9167; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_115; // @[Reg.scala 27:20]
|
|
wire _T_9169 = _T_4734 & ic_tag_valid_out_0_115; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9308 = _T_9307 | _T_9169; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_116; // @[Reg.scala 27:20]
|
|
wire _T_9171 = _T_4735 & ic_tag_valid_out_0_116; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9309 = _T_9308 | _T_9171; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_117; // @[Reg.scala 27:20]
|
|
wire _T_9173 = _T_4736 & ic_tag_valid_out_0_117; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9310 = _T_9309 | _T_9173; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_118; // @[Reg.scala 27:20]
|
|
wire _T_9175 = _T_4737 & ic_tag_valid_out_0_118; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9311 = _T_9310 | _T_9175; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_119; // @[Reg.scala 27:20]
|
|
wire _T_9177 = _T_4738 & ic_tag_valid_out_0_119; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9312 = _T_9311 | _T_9177; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_120; // @[Reg.scala 27:20]
|
|
wire _T_9179 = _T_4739 & ic_tag_valid_out_0_120; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9313 = _T_9312 | _T_9179; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_121; // @[Reg.scala 27:20]
|
|
wire _T_9181 = _T_4740 & ic_tag_valid_out_0_121; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9314 = _T_9313 | _T_9181; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_122; // @[Reg.scala 27:20]
|
|
wire _T_9183 = _T_4741 & ic_tag_valid_out_0_122; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9315 = _T_9314 | _T_9183; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_123; // @[Reg.scala 27:20]
|
|
wire _T_9185 = _T_4742 & ic_tag_valid_out_0_123; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9316 = _T_9315 | _T_9185; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_124; // @[Reg.scala 27:20]
|
|
wire _T_9187 = _T_4743 & ic_tag_valid_out_0_124; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9317 = _T_9316 | _T_9187; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_125; // @[Reg.scala 27:20]
|
|
wire _T_9189 = _T_4744 & ic_tag_valid_out_0_125; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9318 = _T_9317 | _T_9189; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_126; // @[Reg.scala 27:20]
|
|
wire _T_9191 = _T_4745 & ic_tag_valid_out_0_126; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9319 = _T_9318 | _T_9191; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
reg ic_tag_valid_out_0_127; // @[Reg.scala 27:20]
|
|
wire _T_9193 = _T_4746 & ic_tag_valid_out_0_127; // @[el2_ifu_mem_ctl.scala 765:10]
|
|
wire _T_9320 = _T_9319 | _T_9193; // @[el2_ifu_mem_ctl.scala 765:91]
|
|
wire [1:0] ic_tag_valid_unq = {_T_9703,_T_9320}; // @[Cat.scala 29:58]
|
|
reg [1:0] ic_debug_way_ff; // @[el2_ifu_mem_ctl.scala 837:53]
|
|
reg ic_debug_rd_en_ff; // @[el2_ifu_mem_ctl.scala 839:54]
|
|
wire [1:0] _T_9743 = ic_debug_rd_en_ff ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_9744 = ic_debug_way_ff & _T_9743; // @[el2_ifu_mem_ctl.scala 820:67]
|
|
wire [1:0] _T_9745 = ic_tag_valid_unq & _T_9744; // @[el2_ifu_mem_ctl.scala 820:48]
|
|
wire ic_debug_tag_val_rd_out = |_T_9745; // @[el2_ifu_mem_ctl.scala 820:115]
|
|
wire [65:0] _T_1210 = {2'h0,io_ictag_debug_rd_data[25:21],32'h0,io_ictag_debug_rd_data[20:0],1'h0,way_status,3'h0,ic_debug_tag_val_rd_out}; // @[Cat.scala 29:58]
|
|
reg [70:0] _T_1211; // @[el2_ifu_mem_ctl.scala 356:63]
|
|
wire _T_1249 = ~ifu_byp_data_err_new; // @[el2_ifu_mem_ctl.scala 372:98]
|
|
wire sel_byp_data = _T_1253 & _T_1249; // @[el2_ifu_mem_ctl.scala 372:96]
|
|
wire [63:0] _T_1260 = fetch_req_iccm_f ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire [63:0] _T_1261 = _T_1260 & io_iccm_rd_data; // @[el2_ifu_mem_ctl.scala 379:69]
|
|
wire [63:0] _T_1263 = sel_byp_data ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_2099 = ~ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 448:31]
|
|
wire _T_1612 = ~ifu_fetch_addr_int_f[1]; // @[el2_ifu_mem_ctl.scala 444:38]
|
|
wire [3:0] byp_fetch_index_inc_0 = {byp_fetch_index_inc,1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_1613 = byp_fetch_index_inc_0 == 4'h0; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1661 = _T_1613 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire _T_1616 = byp_fetch_index_inc_0 == 4'h1; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1662 = _T_1616 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1677 = _T_1661 | _T_1662; // @[Mux.scala 27:72]
|
|
wire _T_1619 = byp_fetch_index_inc_0 == 4'h2; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1663 = _T_1619 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1678 = _T_1677 | _T_1663; // @[Mux.scala 27:72]
|
|
wire _T_1622 = byp_fetch_index_inc_0 == 4'h3; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1664 = _T_1622 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1679 = _T_1678 | _T_1664; // @[Mux.scala 27:72]
|
|
wire _T_1625 = byp_fetch_index_inc_0 == 4'h4; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1665 = _T_1625 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1680 = _T_1679 | _T_1665; // @[Mux.scala 27:72]
|
|
wire _T_1628 = byp_fetch_index_inc_0 == 4'h5; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1666 = _T_1628 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1681 = _T_1680 | _T_1666; // @[Mux.scala 27:72]
|
|
wire _T_1631 = byp_fetch_index_inc_0 == 4'h6; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1667 = _T_1631 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1682 = _T_1681 | _T_1667; // @[Mux.scala 27:72]
|
|
wire _T_1634 = byp_fetch_index_inc_0 == 4'h7; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1668 = _T_1634 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1683 = _T_1682 | _T_1668; // @[Mux.scala 27:72]
|
|
wire _T_1637 = byp_fetch_index_inc_0 == 4'h8; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1669 = _T_1637 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1684 = _T_1683 | _T_1669; // @[Mux.scala 27:72]
|
|
wire _T_1640 = byp_fetch_index_inc_0 == 4'h9; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1670 = _T_1640 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1685 = _T_1684 | _T_1670; // @[Mux.scala 27:72]
|
|
wire _T_1643 = byp_fetch_index_inc_0 == 4'ha; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1671 = _T_1643 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1686 = _T_1685 | _T_1671; // @[Mux.scala 27:72]
|
|
wire _T_1646 = byp_fetch_index_inc_0 == 4'hb; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1672 = _T_1646 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1687 = _T_1686 | _T_1672; // @[Mux.scala 27:72]
|
|
wire _T_1649 = byp_fetch_index_inc_0 == 4'hc; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1673 = _T_1649 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1688 = _T_1687 | _T_1673; // @[Mux.scala 27:72]
|
|
wire _T_1652 = byp_fetch_index_inc_0 == 4'hd; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1674 = _T_1652 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1689 = _T_1688 | _T_1674; // @[Mux.scala 27:72]
|
|
wire _T_1655 = byp_fetch_index_inc_0 == 4'he; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1675 = _T_1655 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1690 = _T_1689 | _T_1675; // @[Mux.scala 27:72]
|
|
wire _T_1658 = byp_fetch_index_inc_0 == 4'hf; // @[el2_ifu_mem_ctl.scala 445:73]
|
|
wire [15:0] _T_1676 = _T_1658 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1691 = _T_1690 | _T_1676; // @[Mux.scala 27:72]
|
|
wire [3:0] byp_fetch_index_1 = {ifu_fetch_addr_int_f[4:2],1'h1}; // @[Cat.scala 29:58]
|
|
wire _T_1693 = byp_fetch_index_1 == 4'h0; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1741 = _T_1693 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_1696 = byp_fetch_index_1 == 4'h1; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1742 = _T_1696 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1757 = _T_1741 | _T_1742; // @[Mux.scala 27:72]
|
|
wire _T_1699 = byp_fetch_index_1 == 4'h2; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1743 = _T_1699 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1758 = _T_1757 | _T_1743; // @[Mux.scala 27:72]
|
|
wire _T_1702 = byp_fetch_index_1 == 4'h3; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1744 = _T_1702 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1759 = _T_1758 | _T_1744; // @[Mux.scala 27:72]
|
|
wire _T_1705 = byp_fetch_index_1 == 4'h4; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1745 = _T_1705 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1760 = _T_1759 | _T_1745; // @[Mux.scala 27:72]
|
|
wire _T_1708 = byp_fetch_index_1 == 4'h5; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1746 = _T_1708 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1761 = _T_1760 | _T_1746; // @[Mux.scala 27:72]
|
|
wire _T_1711 = byp_fetch_index_1 == 4'h6; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1747 = _T_1711 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1762 = _T_1761 | _T_1747; // @[Mux.scala 27:72]
|
|
wire _T_1714 = byp_fetch_index_1 == 4'h7; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1748 = _T_1714 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1763 = _T_1762 | _T_1748; // @[Mux.scala 27:72]
|
|
wire _T_1717 = byp_fetch_index_1 == 4'h8; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1749 = _T_1717 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1764 = _T_1763 | _T_1749; // @[Mux.scala 27:72]
|
|
wire _T_1720 = byp_fetch_index_1 == 4'h9; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1750 = _T_1720 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1765 = _T_1764 | _T_1750; // @[Mux.scala 27:72]
|
|
wire _T_1723 = byp_fetch_index_1 == 4'ha; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1751 = _T_1723 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1766 = _T_1765 | _T_1751; // @[Mux.scala 27:72]
|
|
wire _T_1726 = byp_fetch_index_1 == 4'hb; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1752 = _T_1726 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1767 = _T_1766 | _T_1752; // @[Mux.scala 27:72]
|
|
wire _T_1729 = byp_fetch_index_1 == 4'hc; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1753 = _T_1729 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1768 = _T_1767 | _T_1753; // @[Mux.scala 27:72]
|
|
wire _T_1732 = byp_fetch_index_1 == 4'hd; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1754 = _T_1732 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1769 = _T_1768 | _T_1754; // @[Mux.scala 27:72]
|
|
wire _T_1735 = byp_fetch_index_1 == 4'he; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1755 = _T_1735 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1770 = _T_1769 | _T_1755; // @[Mux.scala 27:72]
|
|
wire _T_1738 = byp_fetch_index_1 == 4'hf; // @[el2_ifu_mem_ctl.scala 445:179]
|
|
wire [31:0] _T_1756 = _T_1738 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1771 = _T_1770 | _T_1756; // @[Mux.scala 27:72]
|
|
wire [3:0] byp_fetch_index_0 = {ifu_fetch_addr_int_f[4:2],1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_1773 = byp_fetch_index_0 == 4'h0; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1821 = _T_1773 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_1776 = byp_fetch_index_0 == 4'h1; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1822 = _T_1776 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1837 = _T_1821 | _T_1822; // @[Mux.scala 27:72]
|
|
wire _T_1779 = byp_fetch_index_0 == 4'h2; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1823 = _T_1779 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1838 = _T_1837 | _T_1823; // @[Mux.scala 27:72]
|
|
wire _T_1782 = byp_fetch_index_0 == 4'h3; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1824 = _T_1782 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1839 = _T_1838 | _T_1824; // @[Mux.scala 27:72]
|
|
wire _T_1785 = byp_fetch_index_0 == 4'h4; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1825 = _T_1785 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1840 = _T_1839 | _T_1825; // @[Mux.scala 27:72]
|
|
wire _T_1788 = byp_fetch_index_0 == 4'h5; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1826 = _T_1788 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1841 = _T_1840 | _T_1826; // @[Mux.scala 27:72]
|
|
wire _T_1791 = byp_fetch_index_0 == 4'h6; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1827 = _T_1791 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1842 = _T_1841 | _T_1827; // @[Mux.scala 27:72]
|
|
wire _T_1794 = byp_fetch_index_0 == 4'h7; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1828 = _T_1794 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1843 = _T_1842 | _T_1828; // @[Mux.scala 27:72]
|
|
wire _T_1797 = byp_fetch_index_0 == 4'h8; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1829 = _T_1797 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1844 = _T_1843 | _T_1829; // @[Mux.scala 27:72]
|
|
wire _T_1800 = byp_fetch_index_0 == 4'h9; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1830 = _T_1800 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1845 = _T_1844 | _T_1830; // @[Mux.scala 27:72]
|
|
wire _T_1803 = byp_fetch_index_0 == 4'ha; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1831 = _T_1803 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1846 = _T_1845 | _T_1831; // @[Mux.scala 27:72]
|
|
wire _T_1806 = byp_fetch_index_0 == 4'hb; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1832 = _T_1806 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1847 = _T_1846 | _T_1832; // @[Mux.scala 27:72]
|
|
wire _T_1809 = byp_fetch_index_0 == 4'hc; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1833 = _T_1809 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1848 = _T_1847 | _T_1833; // @[Mux.scala 27:72]
|
|
wire _T_1812 = byp_fetch_index_0 == 4'hd; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1834 = _T_1812 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1849 = _T_1848 | _T_1834; // @[Mux.scala 27:72]
|
|
wire _T_1815 = byp_fetch_index_0 == 4'he; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1835 = _T_1815 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1850 = _T_1849 | _T_1835; // @[Mux.scala 27:72]
|
|
wire _T_1818 = byp_fetch_index_0 == 4'hf; // @[el2_ifu_mem_ctl.scala 445:285]
|
|
wire [31:0] _T_1836 = _T_1818 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1851 = _T_1850 | _T_1836; // @[Mux.scala 27:72]
|
|
wire [79:0] _T_1854 = {_T_1691,_T_1771,_T_1851}; // @[Cat.scala 29:58]
|
|
wire [3:0] byp_fetch_index_inc_1 = {byp_fetch_index_inc,1'h1}; // @[Cat.scala 29:58]
|
|
wire _T_1855 = byp_fetch_index_inc_1 == 4'h0; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1903 = _T_1855 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire _T_1858 = byp_fetch_index_inc_1 == 4'h1; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1904 = _T_1858 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1919 = _T_1903 | _T_1904; // @[Mux.scala 27:72]
|
|
wire _T_1861 = byp_fetch_index_inc_1 == 4'h2; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1905 = _T_1861 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1920 = _T_1919 | _T_1905; // @[Mux.scala 27:72]
|
|
wire _T_1864 = byp_fetch_index_inc_1 == 4'h3; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1906 = _T_1864 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1921 = _T_1920 | _T_1906; // @[Mux.scala 27:72]
|
|
wire _T_1867 = byp_fetch_index_inc_1 == 4'h4; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1907 = _T_1867 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1922 = _T_1921 | _T_1907; // @[Mux.scala 27:72]
|
|
wire _T_1870 = byp_fetch_index_inc_1 == 4'h5; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1908 = _T_1870 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1923 = _T_1922 | _T_1908; // @[Mux.scala 27:72]
|
|
wire _T_1873 = byp_fetch_index_inc_1 == 4'h6; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1909 = _T_1873 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1924 = _T_1923 | _T_1909; // @[Mux.scala 27:72]
|
|
wire _T_1876 = byp_fetch_index_inc_1 == 4'h7; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1910 = _T_1876 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1925 = _T_1924 | _T_1910; // @[Mux.scala 27:72]
|
|
wire _T_1879 = byp_fetch_index_inc_1 == 4'h8; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1911 = _T_1879 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1926 = _T_1925 | _T_1911; // @[Mux.scala 27:72]
|
|
wire _T_1882 = byp_fetch_index_inc_1 == 4'h9; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1912 = _T_1882 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1927 = _T_1926 | _T_1912; // @[Mux.scala 27:72]
|
|
wire _T_1885 = byp_fetch_index_inc_1 == 4'ha; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1913 = _T_1885 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1928 = _T_1927 | _T_1913; // @[Mux.scala 27:72]
|
|
wire _T_1888 = byp_fetch_index_inc_1 == 4'hb; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1914 = _T_1888 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1929 = _T_1928 | _T_1914; // @[Mux.scala 27:72]
|
|
wire _T_1891 = byp_fetch_index_inc_1 == 4'hc; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1915 = _T_1891 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1930 = _T_1929 | _T_1915; // @[Mux.scala 27:72]
|
|
wire _T_1894 = byp_fetch_index_inc_1 == 4'hd; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1916 = _T_1894 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1931 = _T_1930 | _T_1916; // @[Mux.scala 27:72]
|
|
wire _T_1897 = byp_fetch_index_inc_1 == 4'he; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1917 = _T_1897 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1932 = _T_1931 | _T_1917; // @[Mux.scala 27:72]
|
|
wire _T_1900 = byp_fetch_index_inc_1 == 4'hf; // @[el2_ifu_mem_ctl.scala 446:73]
|
|
wire [15:0] _T_1918 = _T_1900 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1933 = _T_1932 | _T_1918; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1983 = _T_1613 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1984 = _T_1616 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1999 = _T_1983 | _T_1984; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1985 = _T_1619 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2000 = _T_1999 | _T_1985; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1986 = _T_1622 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2001 = _T_2000 | _T_1986; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1987 = _T_1625 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2002 = _T_2001 | _T_1987; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1988 = _T_1628 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2003 = _T_2002 | _T_1988; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1989 = _T_1631 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2004 = _T_2003 | _T_1989; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1990 = _T_1634 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2005 = _T_2004 | _T_1990; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1991 = _T_1637 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2006 = _T_2005 | _T_1991; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1992 = _T_1640 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2007 = _T_2006 | _T_1992; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1993 = _T_1643 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2008 = _T_2007 | _T_1993; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1994 = _T_1646 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2009 = _T_2008 | _T_1994; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1995 = _T_1649 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2010 = _T_2009 | _T_1995; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1996 = _T_1652 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2011 = _T_2010 | _T_1996; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1997 = _T_1655 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2012 = _T_2011 | _T_1997; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1998 = _T_1658 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2013 = _T_2012 | _T_1998; // @[Mux.scala 27:72]
|
|
wire [79:0] _T_2096 = {_T_1933,_T_2013,_T_1771}; // @[Cat.scala 29:58]
|
|
wire [79:0] ic_byp_data_only_pre_new = _T_1612 ? _T_1854 : _T_2096; // @[el2_ifu_mem_ctl.scala 444:37]
|
|
wire [79:0] _T_2101 = {16'h0,ic_byp_data_only_pre_new[79:16]}; // @[Cat.scala 29:58]
|
|
wire [79:0] ic_byp_data_only_new = _T_2099 ? ic_byp_data_only_pre_new : _T_2101; // @[el2_ifu_mem_ctl.scala 448:30]
|
|
wire [79:0] _GEN_447 = {{16'd0}, _T_1263}; // @[el2_ifu_mem_ctl.scala 379:114]
|
|
wire [79:0] _T_1264 = _GEN_447 & ic_byp_data_only_new; // @[el2_ifu_mem_ctl.scala 379:114]
|
|
wire [79:0] _GEN_448 = {{16'd0}, _T_1261}; // @[el2_ifu_mem_ctl.scala 379:88]
|
|
wire [79:0] ic_premux_data_temp = _GEN_448 | _T_1264; // @[el2_ifu_mem_ctl.scala 379:88]
|
|
wire fetch_req_f_qual = io_ic_hit_f & _T_319; // @[el2_ifu_mem_ctl.scala 386:38]
|
|
wire [1:0] _T_1273 = ifc_region_acc_fault_f ? 2'h2 : 2'h0; // @[el2_ifu_mem_ctl.scala 390:8]
|
|
wire _T_1275 = fetch_req_f_qual & io_ifu_bp_inst_mask_f; // @[el2_ifu_mem_ctl.scala 392:45]
|
|
wire _T_1277 = byp_fetch_index == 5'h1f; // @[el2_ifu_mem_ctl.scala 392:80]
|
|
wire _T_1278 = ~_T_1277; // @[el2_ifu_mem_ctl.scala 392:71]
|
|
wire _T_1279 = _T_1275 & _T_1278; // @[el2_ifu_mem_ctl.scala 392:69]
|
|
wire _T_1280 = err_stop_state != 2'h2; // @[el2_ifu_mem_ctl.scala 392:131]
|
|
wire _T_1281 = _T_1279 & _T_1280; // @[el2_ifu_mem_ctl.scala 392:114]
|
|
wire [6:0] _T_1353 = {ic_miss_buff_data_valid_in_7,ic_miss_buff_data_valid_in_6,ic_miss_buff_data_valid_in_5,ic_miss_buff_data_valid_in_4,ic_miss_buff_data_valid_in_3,ic_miss_buff_data_valid_in_2,ic_miss_buff_data_valid_in_1}; // @[Cat.scala 29:58]
|
|
wire _T_1359 = ic_miss_buff_data_error[0] & _T_1325; // @[el2_ifu_mem_ctl.scala 411:32]
|
|
wire _T_2640 = |io_ifu_axi_rresp; // @[el2_ifu_mem_ctl.scala 626:47]
|
|
wire _T_2641 = _T_2640 & _T_13; // @[el2_ifu_mem_ctl.scala 626:50]
|
|
wire bus_ifu_wr_data_error = _T_2641 & miss_pending; // @[el2_ifu_mem_ctl.scala 626:68]
|
|
wire ic_miss_buff_data_error_in_0 = write_fill_data_0 ? bus_ifu_wr_data_error : _T_1359; // @[el2_ifu_mem_ctl.scala 410:72]
|
|
wire _T_1363 = ic_miss_buff_data_error[1] & _T_1325; // @[el2_ifu_mem_ctl.scala 411:32]
|
|
wire ic_miss_buff_data_error_in_1 = write_fill_data_1 ? bus_ifu_wr_data_error : _T_1363; // @[el2_ifu_mem_ctl.scala 410:72]
|
|
wire _T_1367 = ic_miss_buff_data_error[2] & _T_1325; // @[el2_ifu_mem_ctl.scala 411:32]
|
|
wire ic_miss_buff_data_error_in_2 = write_fill_data_2 ? bus_ifu_wr_data_error : _T_1367; // @[el2_ifu_mem_ctl.scala 410:72]
|
|
wire _T_1371 = ic_miss_buff_data_error[3] & _T_1325; // @[el2_ifu_mem_ctl.scala 411:32]
|
|
wire ic_miss_buff_data_error_in_3 = write_fill_data_3 ? bus_ifu_wr_data_error : _T_1371; // @[el2_ifu_mem_ctl.scala 410:72]
|
|
wire _T_1375 = ic_miss_buff_data_error[4] & _T_1325; // @[el2_ifu_mem_ctl.scala 411:32]
|
|
wire ic_miss_buff_data_error_in_4 = write_fill_data_4 ? bus_ifu_wr_data_error : _T_1375; // @[el2_ifu_mem_ctl.scala 410:72]
|
|
wire _T_1379 = ic_miss_buff_data_error[5] & _T_1325; // @[el2_ifu_mem_ctl.scala 411:32]
|
|
wire ic_miss_buff_data_error_in_5 = write_fill_data_5 ? bus_ifu_wr_data_error : _T_1379; // @[el2_ifu_mem_ctl.scala 410:72]
|
|
wire _T_1383 = ic_miss_buff_data_error[6] & _T_1325; // @[el2_ifu_mem_ctl.scala 411:32]
|
|
wire ic_miss_buff_data_error_in_6 = write_fill_data_6 ? bus_ifu_wr_data_error : _T_1383; // @[el2_ifu_mem_ctl.scala 410:72]
|
|
wire _T_1387 = ic_miss_buff_data_error[7] & _T_1325; // @[el2_ifu_mem_ctl.scala 411:32]
|
|
wire ic_miss_buff_data_error_in_7 = write_fill_data_7 ? bus_ifu_wr_data_error : _T_1387; // @[el2_ifu_mem_ctl.scala 410:72]
|
|
wire [6:0] _T_1393 = {ic_miss_buff_data_error_in_7,ic_miss_buff_data_error_in_6,ic_miss_buff_data_error_in_5,ic_miss_buff_data_error_in_4,ic_miss_buff_data_error_in_3,ic_miss_buff_data_error_in_2,ic_miss_buff_data_error_in_1}; // @[Cat.scala 29:58]
|
|
reg [6:0] perr_ic_index_ff; // @[Reg.scala 27:20]
|
|
wire _T_2451 = 3'h0 == perr_state; // @[Conditional.scala 37:30]
|
|
wire _T_2459 = _T_6 & _T_319; // @[el2_ifu_mem_ctl.scala 493:65]
|
|
wire _T_2460 = _T_2459 | io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 493:88]
|
|
wire _T_2462 = _T_2460 & _T_2573; // @[el2_ifu_mem_ctl.scala 493:112]
|
|
wire _T_2463 = 3'h1 == perr_state; // @[Conditional.scala 37:30]
|
|
wire _T_2464 = io_dec_tlu_flush_lower_wb | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 498:50]
|
|
wire _T_2466 = 3'h2 == perr_state; // @[Conditional.scala 37:30]
|
|
wire _T_2472 = 3'h4 == perr_state; // @[Conditional.scala 37:30]
|
|
wire _T_2474 = 3'h3 == perr_state; // @[Conditional.scala 37:30]
|
|
wire _GEN_22 = _T_2472 | _T_2474; // @[Conditional.scala 39:67]
|
|
wire _GEN_24 = _T_2466 ? _T_2464 : _GEN_22; // @[Conditional.scala 39:67]
|
|
wire _GEN_26 = _T_2463 ? _T_2464 : _GEN_24; // @[Conditional.scala 39:67]
|
|
wire perr_state_en = _T_2451 ? _T_2462 : _GEN_26; // @[Conditional.scala 40:58]
|
|
wire perr_sb_write_status = _T_2451 & perr_state_en; // @[Conditional.scala 40:58]
|
|
wire _T_2465 = io_dec_tlu_flush_lower_wb & io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 499:56]
|
|
wire _GEN_27 = _T_2463 & _T_2465; // @[Conditional.scala 39:67]
|
|
wire perr_sel_invalidate = _T_2451 ? 1'h0 : _GEN_27; // @[Conditional.scala 40:58]
|
|
wire [1:0] perr_err_inv_way = perr_sel_invalidate ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
reg dma_sb_err_state_ff; // @[el2_ifu_mem_ctl.scala 484:58]
|
|
wire _T_2448 = ~dma_sb_err_state_ff; // @[el2_ifu_mem_ctl.scala 483:49]
|
|
wire _T_2453 = io_ic_error_start & _T_319; // @[el2_ifu_mem_ctl.scala 492:87]
|
|
wire _T_2467 = io_dec_tlu_flush_err_wb & io_dec_tlu_flush_lower_wb; // @[el2_ifu_mem_ctl.scala 502:54]
|
|
wire _T_2468 = _T_2467 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 502:84]
|
|
wire _T_2477 = perr_state == 3'h2; // @[el2_ifu_mem_ctl.scala 523:66]
|
|
wire _T_2478 = io_dec_tlu_flush_err_wb & _T_2477; // @[el2_ifu_mem_ctl.scala 523:52]
|
|
wire _T_2480 = _T_2478 & _T_2573; // @[el2_ifu_mem_ctl.scala 523:81]
|
|
wire _T_2482 = io_dec_tlu_flush_lower_wb | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 526:59]
|
|
wire _T_2483 = _T_2482 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 526:86]
|
|
wire _T_2497 = _T_2482 | io_ifu_fetch_val[0]; // @[el2_ifu_mem_ctl.scala 529:81]
|
|
wire _T_2498 = _T_2497 | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 529:103]
|
|
wire _T_2499 = _T_2498 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 529:126]
|
|
wire _T_2519 = _T_2497 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 536:103]
|
|
wire _T_2526 = ~io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 541:62]
|
|
wire _T_2527 = io_dec_tlu_flush_lower_wb & _T_2526; // @[el2_ifu_mem_ctl.scala 541:60]
|
|
wire _T_2528 = _T_2527 | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 541:88]
|
|
wire _T_2529 = _T_2528 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 541:115]
|
|
wire _GEN_34 = _T_2525 & _T_2483; // @[Conditional.scala 39:67]
|
|
wire _GEN_37 = _T_2508 ? _T_2519 : _GEN_34; // @[Conditional.scala 39:67]
|
|
wire _GEN_39 = _T_2508 | _T_2525; // @[Conditional.scala 39:67]
|
|
wire _GEN_41 = _T_2481 ? _T_2499 : _GEN_37; // @[Conditional.scala 39:67]
|
|
wire _GEN_43 = _T_2481 | _GEN_39; // @[Conditional.scala 39:67]
|
|
wire err_stop_state_en = _T_2476 ? _T_2480 : _GEN_41; // @[Conditional.scala 40:58]
|
|
reg ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 561:55]
|
|
wire _T_2542 = ic_act_miss_f | ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 560:64]
|
|
wire _T_2544 = _T_2542 & _T_2573; // @[el2_ifu_mem_ctl.scala 560:85]
|
|
reg [2:0] bus_cmd_beat_count; // @[Reg.scala 27:20]
|
|
wire _T_2546 = bus_cmd_beat_count == 3'h7; // @[el2_ifu_mem_ctl.scala 560:133]
|
|
wire _T_2547 = _T_2546 & ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 560:164]
|
|
wire _T_2548 = _T_2547 & io_ifu_axi_arready; // @[el2_ifu_mem_ctl.scala 560:184]
|
|
wire _T_2549 = _T_2548 & miss_pending; // @[el2_ifu_mem_ctl.scala 560:204]
|
|
wire _T_2550 = ~_T_2549; // @[el2_ifu_mem_ctl.scala 560:112]
|
|
wire ifu_bus_arready = io_ifu_axi_arready & io_ifu_bus_clk_en; // @[el2_ifu_mem_ctl.scala 592:45]
|
|
wire _T_2567 = io_ifu_axi_arvalid & ifu_bus_arready; // @[el2_ifu_mem_ctl.scala 595:35]
|
|
wire _T_2568 = _T_2567 & miss_pending; // @[el2_ifu_mem_ctl.scala 595:53]
|
|
wire bus_cmd_sent = _T_2568 & _T_2573; // @[el2_ifu_mem_ctl.scala 595:68]
|
|
wire [2:0] _T_2558 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_2560 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2562 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
reg ifu_bus_arready_unq_ff; // @[el2_ifu_mem_ctl.scala 579:57]
|
|
reg ifu_bus_arvalid_ff; // @[el2_ifu_mem_ctl.scala 581:53]
|
|
wire ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 593:51]
|
|
wire _T_2588 = ~scnd_miss_req; // @[el2_ifu_mem_ctl.scala 603:73]
|
|
wire _T_2589 = _T_2574 & _T_2588; // @[el2_ifu_mem_ctl.scala 603:71]
|
|
wire _T_2591 = last_data_recieved_ff & _T_1325; // @[el2_ifu_mem_ctl.scala 603:114]
|
|
wire [2:0] _T_2597 = bus_rd_addr_count + 3'h1; // @[el2_ifu_mem_ctl.scala 608:45]
|
|
wire _T_2601 = ifu_bus_cmd_valid & io_ifu_axi_arready; // @[el2_ifu_mem_ctl.scala 611:48]
|
|
wire _T_2602 = _T_2601 & miss_pending; // @[el2_ifu_mem_ctl.scala 611:68]
|
|
wire bus_inc_cmd_beat_cnt = _T_2602 & _T_2573; // @[el2_ifu_mem_ctl.scala 611:83]
|
|
wire bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; // @[el2_ifu_mem_ctl.scala 613:57]
|
|
wire _T_2606 = ~bus_inc_cmd_beat_cnt; // @[el2_ifu_mem_ctl.scala 614:31]
|
|
wire _T_2607 = ic_act_miss_f | scnd_miss_req; // @[el2_ifu_mem_ctl.scala 614:71]
|
|
wire _T_2608 = _T_2607 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 614:87]
|
|
wire _T_2609 = ~_T_2608; // @[el2_ifu_mem_ctl.scala 614:55]
|
|
wire bus_hold_cmd_beat_cnt = _T_2606 & _T_2609; // @[el2_ifu_mem_ctl.scala 614:53]
|
|
wire _T_2610 = bus_inc_cmd_beat_cnt | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 615:46]
|
|
wire bus_cmd_beat_en = _T_2610 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 615:62]
|
|
wire [2:0] _T_2613 = bus_cmd_beat_count + 3'h1; // @[el2_ifu_mem_ctl.scala 617:46]
|
|
wire [2:0] _T_2615 = bus_reset_cmd_beat_cnt_secondlast ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_2616 = bus_inc_cmd_beat_cnt ? _T_2613 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_2617 = bus_hold_cmd_beat_cnt ? bus_cmd_beat_count : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_2619 = _T_2615 | _T_2616; // @[Mux.scala 27:72]
|
|
wire [2:0] bus_new_cmd_beat_count = _T_2619 | _T_2617; // @[Mux.scala 27:72]
|
|
reg ifc_dma_access_ok_prev; // @[el2_ifu_mem_ctl.scala 629:62]
|
|
wire _T_2648 = ~iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 634:50]
|
|
wire _T_2649 = io_ifc_dma_access_ok & _T_2648; // @[el2_ifu_mem_ctl.scala 634:47]
|
|
wire _T_2650 = ~io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 634:70]
|
|
wire _T_2654 = _T_2649 & ifc_dma_access_ok_prev; // @[el2_ifu_mem_ctl.scala 635:72]
|
|
wire _T_2655 = perr_state == 3'h0; // @[el2_ifu_mem_ctl.scala 635:111]
|
|
wire _T_2656 = _T_2654 & _T_2655; // @[el2_ifu_mem_ctl.scala 635:97]
|
|
wire ifc_dma_access_q_ok = _T_2656 & _T_2650; // @[el2_ifu_mem_ctl.scala 635:127]
|
|
wire _T_2659 = ifc_dma_access_q_ok & io_dma_iccm_req; // @[el2_ifu_mem_ctl.scala 638:40]
|
|
wire _T_2660 = _T_2659 & io_dma_mem_write; // @[el2_ifu_mem_ctl.scala 638:58]
|
|
wire _T_2663 = ~io_dma_mem_write; // @[el2_ifu_mem_ctl.scala 639:60]
|
|
wire _T_2664 = _T_2659 & _T_2663; // @[el2_ifu_mem_ctl.scala 639:58]
|
|
wire _T_2665 = io_ifc_iccm_access_bf & io_ifc_fetch_req_bf; // @[el2_ifu_mem_ctl.scala 639:104]
|
|
wire [2:0] _T_2670 = io_dma_iccm_req ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_2691 = io_dma_mem_wdata[32] ^ io_dma_mem_wdata[33]; // @[el2_lib.scala 259:74]
|
|
wire _T_2692 = _T_2691 ^ io_dma_mem_wdata[35]; // @[el2_lib.scala 259:74]
|
|
wire _T_2693 = _T_2692 ^ io_dma_mem_wdata[36]; // @[el2_lib.scala 259:74]
|
|
wire _T_2694 = _T_2693 ^ io_dma_mem_wdata[38]; // @[el2_lib.scala 259:74]
|
|
wire _T_2695 = _T_2694 ^ io_dma_mem_wdata[40]; // @[el2_lib.scala 259:74]
|
|
wire _T_2696 = _T_2695 ^ io_dma_mem_wdata[42]; // @[el2_lib.scala 259:74]
|
|
wire _T_2697 = _T_2696 ^ io_dma_mem_wdata[43]; // @[el2_lib.scala 259:74]
|
|
wire _T_2698 = _T_2697 ^ io_dma_mem_wdata[45]; // @[el2_lib.scala 259:74]
|
|
wire _T_2699 = _T_2698 ^ io_dma_mem_wdata[47]; // @[el2_lib.scala 259:74]
|
|
wire _T_2700 = _T_2699 ^ io_dma_mem_wdata[49]; // @[el2_lib.scala 259:74]
|
|
wire _T_2701 = _T_2700 ^ io_dma_mem_wdata[51]; // @[el2_lib.scala 259:74]
|
|
wire _T_2702 = _T_2701 ^ io_dma_mem_wdata[53]; // @[el2_lib.scala 259:74]
|
|
wire _T_2703 = _T_2702 ^ io_dma_mem_wdata[55]; // @[el2_lib.scala 259:74]
|
|
wire _T_2704 = _T_2703 ^ io_dma_mem_wdata[57]; // @[el2_lib.scala 259:74]
|
|
wire _T_2705 = _T_2704 ^ io_dma_mem_wdata[58]; // @[el2_lib.scala 259:74]
|
|
wire _T_2706 = _T_2705 ^ io_dma_mem_wdata[60]; // @[el2_lib.scala 259:74]
|
|
wire _T_2707 = _T_2706 ^ io_dma_mem_wdata[62]; // @[el2_lib.scala 259:74]
|
|
wire _T_2726 = io_dma_mem_wdata[32] ^ io_dma_mem_wdata[34]; // @[el2_lib.scala 259:74]
|
|
wire _T_2727 = _T_2726 ^ io_dma_mem_wdata[35]; // @[el2_lib.scala 259:74]
|
|
wire _T_2728 = _T_2727 ^ io_dma_mem_wdata[37]; // @[el2_lib.scala 259:74]
|
|
wire _T_2729 = _T_2728 ^ io_dma_mem_wdata[38]; // @[el2_lib.scala 259:74]
|
|
wire _T_2730 = _T_2729 ^ io_dma_mem_wdata[41]; // @[el2_lib.scala 259:74]
|
|
wire _T_2731 = _T_2730 ^ io_dma_mem_wdata[42]; // @[el2_lib.scala 259:74]
|
|
wire _T_2732 = _T_2731 ^ io_dma_mem_wdata[44]; // @[el2_lib.scala 259:74]
|
|
wire _T_2733 = _T_2732 ^ io_dma_mem_wdata[45]; // @[el2_lib.scala 259:74]
|
|
wire _T_2734 = _T_2733 ^ io_dma_mem_wdata[48]; // @[el2_lib.scala 259:74]
|
|
wire _T_2735 = _T_2734 ^ io_dma_mem_wdata[49]; // @[el2_lib.scala 259:74]
|
|
wire _T_2736 = _T_2735 ^ io_dma_mem_wdata[52]; // @[el2_lib.scala 259:74]
|
|
wire _T_2737 = _T_2736 ^ io_dma_mem_wdata[53]; // @[el2_lib.scala 259:74]
|
|
wire _T_2738 = _T_2737 ^ io_dma_mem_wdata[56]; // @[el2_lib.scala 259:74]
|
|
wire _T_2739 = _T_2738 ^ io_dma_mem_wdata[57]; // @[el2_lib.scala 259:74]
|
|
wire _T_2740 = _T_2739 ^ io_dma_mem_wdata[59]; // @[el2_lib.scala 259:74]
|
|
wire _T_2741 = _T_2740 ^ io_dma_mem_wdata[60]; // @[el2_lib.scala 259:74]
|
|
wire _T_2742 = _T_2741 ^ io_dma_mem_wdata[63]; // @[el2_lib.scala 259:74]
|
|
wire _T_2761 = io_dma_mem_wdata[33] ^ io_dma_mem_wdata[34]; // @[el2_lib.scala 259:74]
|
|
wire _T_2762 = _T_2761 ^ io_dma_mem_wdata[35]; // @[el2_lib.scala 259:74]
|
|
wire _T_2763 = _T_2762 ^ io_dma_mem_wdata[39]; // @[el2_lib.scala 259:74]
|
|
wire _T_2764 = _T_2763 ^ io_dma_mem_wdata[40]; // @[el2_lib.scala 259:74]
|
|
wire _T_2765 = _T_2764 ^ io_dma_mem_wdata[41]; // @[el2_lib.scala 259:74]
|
|
wire _T_2766 = _T_2765 ^ io_dma_mem_wdata[42]; // @[el2_lib.scala 259:74]
|
|
wire _T_2767 = _T_2766 ^ io_dma_mem_wdata[46]; // @[el2_lib.scala 259:74]
|
|
wire _T_2768 = _T_2767 ^ io_dma_mem_wdata[47]; // @[el2_lib.scala 259:74]
|
|
wire _T_2769 = _T_2768 ^ io_dma_mem_wdata[48]; // @[el2_lib.scala 259:74]
|
|
wire _T_2770 = _T_2769 ^ io_dma_mem_wdata[49]; // @[el2_lib.scala 259:74]
|
|
wire _T_2771 = _T_2770 ^ io_dma_mem_wdata[54]; // @[el2_lib.scala 259:74]
|
|
wire _T_2772 = _T_2771 ^ io_dma_mem_wdata[55]; // @[el2_lib.scala 259:74]
|
|
wire _T_2773 = _T_2772 ^ io_dma_mem_wdata[56]; // @[el2_lib.scala 259:74]
|
|
wire _T_2774 = _T_2773 ^ io_dma_mem_wdata[57]; // @[el2_lib.scala 259:74]
|
|
wire _T_2775 = _T_2774 ^ io_dma_mem_wdata[61]; // @[el2_lib.scala 259:74]
|
|
wire _T_2776 = _T_2775 ^ io_dma_mem_wdata[62]; // @[el2_lib.scala 259:74]
|
|
wire _T_2777 = _T_2776 ^ io_dma_mem_wdata[63]; // @[el2_lib.scala 259:74]
|
|
wire _T_2793 = io_dma_mem_wdata[36] ^ io_dma_mem_wdata[37]; // @[el2_lib.scala 259:74]
|
|
wire _T_2794 = _T_2793 ^ io_dma_mem_wdata[38]; // @[el2_lib.scala 259:74]
|
|
wire _T_2795 = _T_2794 ^ io_dma_mem_wdata[39]; // @[el2_lib.scala 259:74]
|
|
wire _T_2796 = _T_2795 ^ io_dma_mem_wdata[40]; // @[el2_lib.scala 259:74]
|
|
wire _T_2797 = _T_2796 ^ io_dma_mem_wdata[41]; // @[el2_lib.scala 259:74]
|
|
wire _T_2798 = _T_2797 ^ io_dma_mem_wdata[42]; // @[el2_lib.scala 259:74]
|
|
wire _T_2799 = _T_2798 ^ io_dma_mem_wdata[50]; // @[el2_lib.scala 259:74]
|
|
wire _T_2800 = _T_2799 ^ io_dma_mem_wdata[51]; // @[el2_lib.scala 259:74]
|
|
wire _T_2801 = _T_2800 ^ io_dma_mem_wdata[52]; // @[el2_lib.scala 259:74]
|
|
wire _T_2802 = _T_2801 ^ io_dma_mem_wdata[53]; // @[el2_lib.scala 259:74]
|
|
wire _T_2803 = _T_2802 ^ io_dma_mem_wdata[54]; // @[el2_lib.scala 259:74]
|
|
wire _T_2804 = _T_2803 ^ io_dma_mem_wdata[55]; // @[el2_lib.scala 259:74]
|
|
wire _T_2805 = _T_2804 ^ io_dma_mem_wdata[56]; // @[el2_lib.scala 259:74]
|
|
wire _T_2806 = _T_2805 ^ io_dma_mem_wdata[57]; // @[el2_lib.scala 259:74]
|
|
wire _T_2822 = io_dma_mem_wdata[43] ^ io_dma_mem_wdata[44]; // @[el2_lib.scala 259:74]
|
|
wire _T_2823 = _T_2822 ^ io_dma_mem_wdata[45]; // @[el2_lib.scala 259:74]
|
|
wire _T_2824 = _T_2823 ^ io_dma_mem_wdata[46]; // @[el2_lib.scala 259:74]
|
|
wire _T_2825 = _T_2824 ^ io_dma_mem_wdata[47]; // @[el2_lib.scala 259:74]
|
|
wire _T_2826 = _T_2825 ^ io_dma_mem_wdata[48]; // @[el2_lib.scala 259:74]
|
|
wire _T_2827 = _T_2826 ^ io_dma_mem_wdata[49]; // @[el2_lib.scala 259:74]
|
|
wire _T_2828 = _T_2827 ^ io_dma_mem_wdata[50]; // @[el2_lib.scala 259:74]
|
|
wire _T_2829 = _T_2828 ^ io_dma_mem_wdata[51]; // @[el2_lib.scala 259:74]
|
|
wire _T_2830 = _T_2829 ^ io_dma_mem_wdata[52]; // @[el2_lib.scala 259:74]
|
|
wire _T_2831 = _T_2830 ^ io_dma_mem_wdata[53]; // @[el2_lib.scala 259:74]
|
|
wire _T_2832 = _T_2831 ^ io_dma_mem_wdata[54]; // @[el2_lib.scala 259:74]
|
|
wire _T_2833 = _T_2832 ^ io_dma_mem_wdata[55]; // @[el2_lib.scala 259:74]
|
|
wire _T_2834 = _T_2833 ^ io_dma_mem_wdata[56]; // @[el2_lib.scala 259:74]
|
|
wire _T_2835 = _T_2834 ^ io_dma_mem_wdata[57]; // @[el2_lib.scala 259:74]
|
|
wire _T_2842 = io_dma_mem_wdata[58] ^ io_dma_mem_wdata[59]; // @[el2_lib.scala 259:74]
|
|
wire _T_2843 = _T_2842 ^ io_dma_mem_wdata[60]; // @[el2_lib.scala 259:74]
|
|
wire _T_2844 = _T_2843 ^ io_dma_mem_wdata[61]; // @[el2_lib.scala 259:74]
|
|
wire _T_2845 = _T_2844 ^ io_dma_mem_wdata[62]; // @[el2_lib.scala 259:74]
|
|
wire _T_2846 = _T_2845 ^ io_dma_mem_wdata[63]; // @[el2_lib.scala 259:74]
|
|
wire [5:0] _T_2851 = {_T_2846,_T_2835,_T_2806,_T_2777,_T_2742,_T_2707}; // @[Cat.scala 29:58]
|
|
wire _T_2852 = ^io_dma_mem_wdata[63:32]; // @[el2_lib.scala 267:13]
|
|
wire _T_2853 = ^_T_2851; // @[el2_lib.scala 267:23]
|
|
wire _T_2854 = _T_2852 ^ _T_2853; // @[el2_lib.scala 267:18]
|
|
wire _T_2875 = io_dma_mem_wdata[0] ^ io_dma_mem_wdata[1]; // @[el2_lib.scala 259:74]
|
|
wire _T_2876 = _T_2875 ^ io_dma_mem_wdata[3]; // @[el2_lib.scala 259:74]
|
|
wire _T_2877 = _T_2876 ^ io_dma_mem_wdata[4]; // @[el2_lib.scala 259:74]
|
|
wire _T_2878 = _T_2877 ^ io_dma_mem_wdata[6]; // @[el2_lib.scala 259:74]
|
|
wire _T_2879 = _T_2878 ^ io_dma_mem_wdata[8]; // @[el2_lib.scala 259:74]
|
|
wire _T_2880 = _T_2879 ^ io_dma_mem_wdata[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_2881 = _T_2880 ^ io_dma_mem_wdata[11]; // @[el2_lib.scala 259:74]
|
|
wire _T_2882 = _T_2881 ^ io_dma_mem_wdata[13]; // @[el2_lib.scala 259:74]
|
|
wire _T_2883 = _T_2882 ^ io_dma_mem_wdata[15]; // @[el2_lib.scala 259:74]
|
|
wire _T_2884 = _T_2883 ^ io_dma_mem_wdata[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_2885 = _T_2884 ^ io_dma_mem_wdata[19]; // @[el2_lib.scala 259:74]
|
|
wire _T_2886 = _T_2885 ^ io_dma_mem_wdata[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_2887 = _T_2886 ^ io_dma_mem_wdata[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_2888 = _T_2887 ^ io_dma_mem_wdata[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_2889 = _T_2888 ^ io_dma_mem_wdata[26]; // @[el2_lib.scala 259:74]
|
|
wire _T_2890 = _T_2889 ^ io_dma_mem_wdata[28]; // @[el2_lib.scala 259:74]
|
|
wire _T_2891 = _T_2890 ^ io_dma_mem_wdata[30]; // @[el2_lib.scala 259:74]
|
|
wire _T_2910 = io_dma_mem_wdata[0] ^ io_dma_mem_wdata[2]; // @[el2_lib.scala 259:74]
|
|
wire _T_2911 = _T_2910 ^ io_dma_mem_wdata[3]; // @[el2_lib.scala 259:74]
|
|
wire _T_2912 = _T_2911 ^ io_dma_mem_wdata[5]; // @[el2_lib.scala 259:74]
|
|
wire _T_2913 = _T_2912 ^ io_dma_mem_wdata[6]; // @[el2_lib.scala 259:74]
|
|
wire _T_2914 = _T_2913 ^ io_dma_mem_wdata[9]; // @[el2_lib.scala 259:74]
|
|
wire _T_2915 = _T_2914 ^ io_dma_mem_wdata[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_2916 = _T_2915 ^ io_dma_mem_wdata[12]; // @[el2_lib.scala 259:74]
|
|
wire _T_2917 = _T_2916 ^ io_dma_mem_wdata[13]; // @[el2_lib.scala 259:74]
|
|
wire _T_2918 = _T_2917 ^ io_dma_mem_wdata[16]; // @[el2_lib.scala 259:74]
|
|
wire _T_2919 = _T_2918 ^ io_dma_mem_wdata[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_2920 = _T_2919 ^ io_dma_mem_wdata[20]; // @[el2_lib.scala 259:74]
|
|
wire _T_2921 = _T_2920 ^ io_dma_mem_wdata[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_2922 = _T_2921 ^ io_dma_mem_wdata[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_2923 = _T_2922 ^ io_dma_mem_wdata[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_2924 = _T_2923 ^ io_dma_mem_wdata[27]; // @[el2_lib.scala 259:74]
|
|
wire _T_2925 = _T_2924 ^ io_dma_mem_wdata[28]; // @[el2_lib.scala 259:74]
|
|
wire _T_2926 = _T_2925 ^ io_dma_mem_wdata[31]; // @[el2_lib.scala 259:74]
|
|
wire _T_2945 = io_dma_mem_wdata[1] ^ io_dma_mem_wdata[2]; // @[el2_lib.scala 259:74]
|
|
wire _T_2946 = _T_2945 ^ io_dma_mem_wdata[3]; // @[el2_lib.scala 259:74]
|
|
wire _T_2947 = _T_2946 ^ io_dma_mem_wdata[7]; // @[el2_lib.scala 259:74]
|
|
wire _T_2948 = _T_2947 ^ io_dma_mem_wdata[8]; // @[el2_lib.scala 259:74]
|
|
wire _T_2949 = _T_2948 ^ io_dma_mem_wdata[9]; // @[el2_lib.scala 259:74]
|
|
wire _T_2950 = _T_2949 ^ io_dma_mem_wdata[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_2951 = _T_2950 ^ io_dma_mem_wdata[14]; // @[el2_lib.scala 259:74]
|
|
wire _T_2952 = _T_2951 ^ io_dma_mem_wdata[15]; // @[el2_lib.scala 259:74]
|
|
wire _T_2953 = _T_2952 ^ io_dma_mem_wdata[16]; // @[el2_lib.scala 259:74]
|
|
wire _T_2954 = _T_2953 ^ io_dma_mem_wdata[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_2955 = _T_2954 ^ io_dma_mem_wdata[22]; // @[el2_lib.scala 259:74]
|
|
wire _T_2956 = _T_2955 ^ io_dma_mem_wdata[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_2957 = _T_2956 ^ io_dma_mem_wdata[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_2958 = _T_2957 ^ io_dma_mem_wdata[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_2959 = _T_2958 ^ io_dma_mem_wdata[29]; // @[el2_lib.scala 259:74]
|
|
wire _T_2960 = _T_2959 ^ io_dma_mem_wdata[30]; // @[el2_lib.scala 259:74]
|
|
wire _T_2961 = _T_2960 ^ io_dma_mem_wdata[31]; // @[el2_lib.scala 259:74]
|
|
wire _T_2977 = io_dma_mem_wdata[4] ^ io_dma_mem_wdata[5]; // @[el2_lib.scala 259:74]
|
|
wire _T_2978 = _T_2977 ^ io_dma_mem_wdata[6]; // @[el2_lib.scala 259:74]
|
|
wire _T_2979 = _T_2978 ^ io_dma_mem_wdata[7]; // @[el2_lib.scala 259:74]
|
|
wire _T_2980 = _T_2979 ^ io_dma_mem_wdata[8]; // @[el2_lib.scala 259:74]
|
|
wire _T_2981 = _T_2980 ^ io_dma_mem_wdata[9]; // @[el2_lib.scala 259:74]
|
|
wire _T_2982 = _T_2981 ^ io_dma_mem_wdata[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_2983 = _T_2982 ^ io_dma_mem_wdata[18]; // @[el2_lib.scala 259:74]
|
|
wire _T_2984 = _T_2983 ^ io_dma_mem_wdata[19]; // @[el2_lib.scala 259:74]
|
|
wire _T_2985 = _T_2984 ^ io_dma_mem_wdata[20]; // @[el2_lib.scala 259:74]
|
|
wire _T_2986 = _T_2985 ^ io_dma_mem_wdata[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_2987 = _T_2986 ^ io_dma_mem_wdata[22]; // @[el2_lib.scala 259:74]
|
|
wire _T_2988 = _T_2987 ^ io_dma_mem_wdata[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_2989 = _T_2988 ^ io_dma_mem_wdata[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_2990 = _T_2989 ^ io_dma_mem_wdata[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_3006 = io_dma_mem_wdata[11] ^ io_dma_mem_wdata[12]; // @[el2_lib.scala 259:74]
|
|
wire _T_3007 = _T_3006 ^ io_dma_mem_wdata[13]; // @[el2_lib.scala 259:74]
|
|
wire _T_3008 = _T_3007 ^ io_dma_mem_wdata[14]; // @[el2_lib.scala 259:74]
|
|
wire _T_3009 = _T_3008 ^ io_dma_mem_wdata[15]; // @[el2_lib.scala 259:74]
|
|
wire _T_3010 = _T_3009 ^ io_dma_mem_wdata[16]; // @[el2_lib.scala 259:74]
|
|
wire _T_3011 = _T_3010 ^ io_dma_mem_wdata[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_3012 = _T_3011 ^ io_dma_mem_wdata[18]; // @[el2_lib.scala 259:74]
|
|
wire _T_3013 = _T_3012 ^ io_dma_mem_wdata[19]; // @[el2_lib.scala 259:74]
|
|
wire _T_3014 = _T_3013 ^ io_dma_mem_wdata[20]; // @[el2_lib.scala 259:74]
|
|
wire _T_3015 = _T_3014 ^ io_dma_mem_wdata[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_3016 = _T_3015 ^ io_dma_mem_wdata[22]; // @[el2_lib.scala 259:74]
|
|
wire _T_3017 = _T_3016 ^ io_dma_mem_wdata[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_3018 = _T_3017 ^ io_dma_mem_wdata[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_3019 = _T_3018 ^ io_dma_mem_wdata[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_3026 = io_dma_mem_wdata[26] ^ io_dma_mem_wdata[27]; // @[el2_lib.scala 259:74]
|
|
wire _T_3027 = _T_3026 ^ io_dma_mem_wdata[28]; // @[el2_lib.scala 259:74]
|
|
wire _T_3028 = _T_3027 ^ io_dma_mem_wdata[29]; // @[el2_lib.scala 259:74]
|
|
wire _T_3029 = _T_3028 ^ io_dma_mem_wdata[30]; // @[el2_lib.scala 259:74]
|
|
wire _T_3030 = _T_3029 ^ io_dma_mem_wdata[31]; // @[el2_lib.scala 259:74]
|
|
wire [5:0] _T_3035 = {_T_3030,_T_3019,_T_2990,_T_2961,_T_2926,_T_2891}; // @[Cat.scala 29:58]
|
|
wire _T_3036 = ^io_dma_mem_wdata[31:0]; // @[el2_lib.scala 267:13]
|
|
wire _T_3037 = ^_T_3035; // @[el2_lib.scala 267:23]
|
|
wire _T_3038 = _T_3036 ^ _T_3037; // @[el2_lib.scala 267:18]
|
|
wire [6:0] _T_3039 = {_T_3038,_T_3030,_T_3019,_T_2990,_T_2961,_T_2926,_T_2891}; // @[Cat.scala 29:58]
|
|
wire [13:0] dma_mem_ecc = {_T_2854,_T_2846,_T_2835,_T_2806,_T_2777,_T_2742,_T_2707,_T_3039}; // @[Cat.scala 29:58]
|
|
wire _T_3041 = ~_T_2659; // @[el2_ifu_mem_ctl.scala 645:45]
|
|
wire _T_3042 = iccm_correct_ecc & _T_3041; // @[el2_ifu_mem_ctl.scala 645:43]
|
|
reg [38:0] iccm_ecc_corr_data_ff; // @[Reg.scala 27:20]
|
|
wire [77:0] _T_3043 = {iccm_ecc_corr_data_ff,iccm_ecc_corr_data_ff}; // @[Cat.scala 29:58]
|
|
wire [77:0] _T_3050 = {dma_mem_ecc[13:7],io_dma_mem_wdata[63:32],dma_mem_ecc[6:0],io_dma_mem_wdata[31:0]}; // @[Cat.scala 29:58]
|
|
reg [1:0] dma_mem_addr_ff; // @[el2_ifu_mem_ctl.scala 659:53]
|
|
wire _T_3383 = _T_3295[5:0] == 6'h27; // @[el2_lib.scala 339:41]
|
|
wire _T_3381 = _T_3295[5:0] == 6'h26; // @[el2_lib.scala 339:41]
|
|
wire _T_3379 = _T_3295[5:0] == 6'h25; // @[el2_lib.scala 339:41]
|
|
wire _T_3377 = _T_3295[5:0] == 6'h24; // @[el2_lib.scala 339:41]
|
|
wire _T_3375 = _T_3295[5:0] == 6'h23; // @[el2_lib.scala 339:41]
|
|
wire _T_3373 = _T_3295[5:0] == 6'h22; // @[el2_lib.scala 339:41]
|
|
wire _T_3371 = _T_3295[5:0] == 6'h21; // @[el2_lib.scala 339:41]
|
|
wire _T_3369 = _T_3295[5:0] == 6'h20; // @[el2_lib.scala 339:41]
|
|
wire _T_3367 = _T_3295[5:0] == 6'h1f; // @[el2_lib.scala 339:41]
|
|
wire _T_3365 = _T_3295[5:0] == 6'h1e; // @[el2_lib.scala 339:41]
|
|
wire [9:0] _T_3441 = {_T_3383,_T_3381,_T_3379,_T_3377,_T_3375,_T_3373,_T_3371,_T_3369,_T_3367,_T_3365}; // @[el2_lib.scala 342:69]
|
|
wire _T_3363 = _T_3295[5:0] == 6'h1d; // @[el2_lib.scala 339:41]
|
|
wire _T_3361 = _T_3295[5:0] == 6'h1c; // @[el2_lib.scala 339:41]
|
|
wire _T_3359 = _T_3295[5:0] == 6'h1b; // @[el2_lib.scala 339:41]
|
|
wire _T_3357 = _T_3295[5:0] == 6'h1a; // @[el2_lib.scala 339:41]
|
|
wire _T_3355 = _T_3295[5:0] == 6'h19; // @[el2_lib.scala 339:41]
|
|
wire _T_3353 = _T_3295[5:0] == 6'h18; // @[el2_lib.scala 339:41]
|
|
wire _T_3351 = _T_3295[5:0] == 6'h17; // @[el2_lib.scala 339:41]
|
|
wire _T_3349 = _T_3295[5:0] == 6'h16; // @[el2_lib.scala 339:41]
|
|
wire _T_3347 = _T_3295[5:0] == 6'h15; // @[el2_lib.scala 339:41]
|
|
wire _T_3345 = _T_3295[5:0] == 6'h14; // @[el2_lib.scala 339:41]
|
|
wire [9:0] _T_3432 = {_T_3363,_T_3361,_T_3359,_T_3357,_T_3355,_T_3353,_T_3351,_T_3349,_T_3347,_T_3345}; // @[el2_lib.scala 342:69]
|
|
wire _T_3343 = _T_3295[5:0] == 6'h13; // @[el2_lib.scala 339:41]
|
|
wire _T_3341 = _T_3295[5:0] == 6'h12; // @[el2_lib.scala 339:41]
|
|
wire _T_3339 = _T_3295[5:0] == 6'h11; // @[el2_lib.scala 339:41]
|
|
wire _T_3337 = _T_3295[5:0] == 6'h10; // @[el2_lib.scala 339:41]
|
|
wire _T_3335 = _T_3295[5:0] == 6'hf; // @[el2_lib.scala 339:41]
|
|
wire _T_3333 = _T_3295[5:0] == 6'he; // @[el2_lib.scala 339:41]
|
|
wire _T_3331 = _T_3295[5:0] == 6'hd; // @[el2_lib.scala 339:41]
|
|
wire _T_3329 = _T_3295[5:0] == 6'hc; // @[el2_lib.scala 339:41]
|
|
wire _T_3327 = _T_3295[5:0] == 6'hb; // @[el2_lib.scala 339:41]
|
|
wire _T_3325 = _T_3295[5:0] == 6'ha; // @[el2_lib.scala 339:41]
|
|
wire [9:0] _T_3422 = {_T_3343,_T_3341,_T_3339,_T_3337,_T_3335,_T_3333,_T_3331,_T_3329,_T_3327,_T_3325}; // @[el2_lib.scala 342:69]
|
|
wire _T_3323 = _T_3295[5:0] == 6'h9; // @[el2_lib.scala 339:41]
|
|
wire _T_3321 = _T_3295[5:0] == 6'h8; // @[el2_lib.scala 339:41]
|
|
wire _T_3319 = _T_3295[5:0] == 6'h7; // @[el2_lib.scala 339:41]
|
|
wire _T_3317 = _T_3295[5:0] == 6'h6; // @[el2_lib.scala 339:41]
|
|
wire _T_3315 = _T_3295[5:0] == 6'h5; // @[el2_lib.scala 339:41]
|
|
wire _T_3313 = _T_3295[5:0] == 6'h4; // @[el2_lib.scala 339:41]
|
|
wire _T_3311 = _T_3295[5:0] == 6'h3; // @[el2_lib.scala 339:41]
|
|
wire _T_3309 = _T_3295[5:0] == 6'h2; // @[el2_lib.scala 339:41]
|
|
wire _T_3307 = _T_3295[5:0] == 6'h1; // @[el2_lib.scala 339:41]
|
|
wire [18:0] _T_3423 = {_T_3422,_T_3323,_T_3321,_T_3319,_T_3317,_T_3315,_T_3313,_T_3311,_T_3309,_T_3307}; // @[el2_lib.scala 342:69]
|
|
wire [38:0] _T_3443 = {_T_3441,_T_3432,_T_3423}; // @[el2_lib.scala 342:69]
|
|
wire [7:0] _T_3398 = {io_iccm_rd_data_ecc[35],io_iccm_rd_data_ecc[3:1],io_iccm_rd_data_ecc[34],io_iccm_rd_data_ecc[0],io_iccm_rd_data_ecc[33:32]}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_3404 = {io_iccm_rd_data_ecc[38],io_iccm_rd_data_ecc[31:26],io_iccm_rd_data_ecc[37],io_iccm_rd_data_ecc[25:11],io_iccm_rd_data_ecc[36],io_iccm_rd_data_ecc[10:4],_T_3398}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_3444 = _T_3443 ^ _T_3404; // @[el2_lib.scala 342:76]
|
|
wire [38:0] _T_3445 = _T_3299 ? _T_3444 : _T_3404; // @[el2_lib.scala 342:31]
|
|
wire [31:0] iccm_corrected_data_0 = {_T_3445[37:32],_T_3445[30:16],_T_3445[14:8],_T_3445[6:4],_T_3445[2]}; // @[Cat.scala 29:58]
|
|
wire _T_3768 = _T_3680[5:0] == 6'h27; // @[el2_lib.scala 339:41]
|
|
wire _T_3766 = _T_3680[5:0] == 6'h26; // @[el2_lib.scala 339:41]
|
|
wire _T_3764 = _T_3680[5:0] == 6'h25; // @[el2_lib.scala 339:41]
|
|
wire _T_3762 = _T_3680[5:0] == 6'h24; // @[el2_lib.scala 339:41]
|
|
wire _T_3760 = _T_3680[5:0] == 6'h23; // @[el2_lib.scala 339:41]
|
|
wire _T_3758 = _T_3680[5:0] == 6'h22; // @[el2_lib.scala 339:41]
|
|
wire _T_3756 = _T_3680[5:0] == 6'h21; // @[el2_lib.scala 339:41]
|
|
wire _T_3754 = _T_3680[5:0] == 6'h20; // @[el2_lib.scala 339:41]
|
|
wire _T_3752 = _T_3680[5:0] == 6'h1f; // @[el2_lib.scala 339:41]
|
|
wire _T_3750 = _T_3680[5:0] == 6'h1e; // @[el2_lib.scala 339:41]
|
|
wire [9:0] _T_3826 = {_T_3768,_T_3766,_T_3764,_T_3762,_T_3760,_T_3758,_T_3756,_T_3754,_T_3752,_T_3750}; // @[el2_lib.scala 342:69]
|
|
wire _T_3748 = _T_3680[5:0] == 6'h1d; // @[el2_lib.scala 339:41]
|
|
wire _T_3746 = _T_3680[5:0] == 6'h1c; // @[el2_lib.scala 339:41]
|
|
wire _T_3744 = _T_3680[5:0] == 6'h1b; // @[el2_lib.scala 339:41]
|
|
wire _T_3742 = _T_3680[5:0] == 6'h1a; // @[el2_lib.scala 339:41]
|
|
wire _T_3740 = _T_3680[5:0] == 6'h19; // @[el2_lib.scala 339:41]
|
|
wire _T_3738 = _T_3680[5:0] == 6'h18; // @[el2_lib.scala 339:41]
|
|
wire _T_3736 = _T_3680[5:0] == 6'h17; // @[el2_lib.scala 339:41]
|
|
wire _T_3734 = _T_3680[5:0] == 6'h16; // @[el2_lib.scala 339:41]
|
|
wire _T_3732 = _T_3680[5:0] == 6'h15; // @[el2_lib.scala 339:41]
|
|
wire _T_3730 = _T_3680[5:0] == 6'h14; // @[el2_lib.scala 339:41]
|
|
wire [9:0] _T_3817 = {_T_3748,_T_3746,_T_3744,_T_3742,_T_3740,_T_3738,_T_3736,_T_3734,_T_3732,_T_3730}; // @[el2_lib.scala 342:69]
|
|
wire _T_3728 = _T_3680[5:0] == 6'h13; // @[el2_lib.scala 339:41]
|
|
wire _T_3726 = _T_3680[5:0] == 6'h12; // @[el2_lib.scala 339:41]
|
|
wire _T_3724 = _T_3680[5:0] == 6'h11; // @[el2_lib.scala 339:41]
|
|
wire _T_3722 = _T_3680[5:0] == 6'h10; // @[el2_lib.scala 339:41]
|
|
wire _T_3720 = _T_3680[5:0] == 6'hf; // @[el2_lib.scala 339:41]
|
|
wire _T_3718 = _T_3680[5:0] == 6'he; // @[el2_lib.scala 339:41]
|
|
wire _T_3716 = _T_3680[5:0] == 6'hd; // @[el2_lib.scala 339:41]
|
|
wire _T_3714 = _T_3680[5:0] == 6'hc; // @[el2_lib.scala 339:41]
|
|
wire _T_3712 = _T_3680[5:0] == 6'hb; // @[el2_lib.scala 339:41]
|
|
wire _T_3710 = _T_3680[5:0] == 6'ha; // @[el2_lib.scala 339:41]
|
|
wire [9:0] _T_3807 = {_T_3728,_T_3726,_T_3724,_T_3722,_T_3720,_T_3718,_T_3716,_T_3714,_T_3712,_T_3710}; // @[el2_lib.scala 342:69]
|
|
wire _T_3708 = _T_3680[5:0] == 6'h9; // @[el2_lib.scala 339:41]
|
|
wire _T_3706 = _T_3680[5:0] == 6'h8; // @[el2_lib.scala 339:41]
|
|
wire _T_3704 = _T_3680[5:0] == 6'h7; // @[el2_lib.scala 339:41]
|
|
wire _T_3702 = _T_3680[5:0] == 6'h6; // @[el2_lib.scala 339:41]
|
|
wire _T_3700 = _T_3680[5:0] == 6'h5; // @[el2_lib.scala 339:41]
|
|
wire _T_3698 = _T_3680[5:0] == 6'h4; // @[el2_lib.scala 339:41]
|
|
wire _T_3696 = _T_3680[5:0] == 6'h3; // @[el2_lib.scala 339:41]
|
|
wire _T_3694 = _T_3680[5:0] == 6'h2; // @[el2_lib.scala 339:41]
|
|
wire _T_3692 = _T_3680[5:0] == 6'h1; // @[el2_lib.scala 339:41]
|
|
wire [18:0] _T_3808 = {_T_3807,_T_3708,_T_3706,_T_3704,_T_3702,_T_3700,_T_3698,_T_3696,_T_3694,_T_3692}; // @[el2_lib.scala 342:69]
|
|
wire [38:0] _T_3828 = {_T_3826,_T_3817,_T_3808}; // @[el2_lib.scala 342:69]
|
|
wire [7:0] _T_3783 = {io_iccm_rd_data_ecc[74],io_iccm_rd_data_ecc[42:40],io_iccm_rd_data_ecc[73],io_iccm_rd_data_ecc[39],io_iccm_rd_data_ecc[72:71]}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_3789 = {io_iccm_rd_data_ecc[77],io_iccm_rd_data_ecc[70:65],io_iccm_rd_data_ecc[76],io_iccm_rd_data_ecc[64:50],io_iccm_rd_data_ecc[75],io_iccm_rd_data_ecc[49:43],_T_3783}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_3829 = _T_3828 ^ _T_3789; // @[el2_lib.scala 342:76]
|
|
wire [38:0] _T_3830 = _T_3684 ? _T_3829 : _T_3789; // @[el2_lib.scala 342:31]
|
|
wire [31:0] iccm_corrected_data_1 = {_T_3830[37:32],_T_3830[30:16],_T_3830[14:8],_T_3830[6:4],_T_3830[2]}; // @[Cat.scala 29:58]
|
|
wire [31:0] iccm_dma_rdata_1_muxed = dma_mem_addr_ff[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[el2_ifu_mem_ctl.scala 651:35]
|
|
wire _T_3303 = ~_T_3295[6]; // @[el2_lib.scala 335:55]
|
|
wire _T_3304 = _T_3297 & _T_3303; // @[el2_lib.scala 335:53]
|
|
wire _T_3688 = ~_T_3680[6]; // @[el2_lib.scala 335:55]
|
|
wire _T_3689 = _T_3682 & _T_3688; // @[el2_lib.scala 335:53]
|
|
wire [1:0] iccm_double_ecc_error = {_T_3304,_T_3689}; // @[Cat.scala 29:58]
|
|
wire iccm_dma_ecc_error_in = |iccm_double_ecc_error; // @[el2_ifu_mem_ctl.scala 653:53]
|
|
wire [63:0] _T_3054 = {io_dma_mem_addr,io_dma_mem_addr}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_3055 = {iccm_dma_rdata_1_muxed,_T_3445[37:32],_T_3445[30:16],_T_3445[14:8],_T_3445[6:4],_T_3445[2]}; // @[Cat.scala 29:58]
|
|
reg [2:0] dma_mem_tag_ff; // @[el2_ifu_mem_ctl.scala 655:54]
|
|
reg [2:0] iccm_dma_rtag_temp; // @[el2_ifu_mem_ctl.scala 656:74]
|
|
reg iccm_dma_rvalid_temp; // @[el2_ifu_mem_ctl.scala 661:76]
|
|
reg [63:0] iccm_dma_rdata_temp; // @[el2_ifu_mem_ctl.scala 665:75]
|
|
wire _T_3060 = _T_2659 & _T_2648; // @[el2_ifu_mem_ctl.scala 668:65]
|
|
wire _T_3064 = _T_3041 & iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 669:50]
|
|
reg [13:0] iccm_ecc_corr_index_ff; // @[Reg.scala 27:20]
|
|
wire [14:0] _T_3065 = {iccm_ecc_corr_index_ff,1'h0}; // @[Cat.scala 29:58]
|
|
wire [14:0] _T_3067 = _T_3064 ? _T_3065 : io_ifc_fetch_addr_bf[14:0]; // @[el2_ifu_mem_ctl.scala 669:8]
|
|
wire _T_3457 = _T_3295 == 7'h40; // @[el2_lib.scala 345:62]
|
|
wire _T_3458 = _T_3445[38] ^ _T_3457; // @[el2_lib.scala 345:44]
|
|
wire [6:0] iccm_corrected_ecc_0 = {_T_3458,_T_3445[31],_T_3445[15],_T_3445[7],_T_3445[3],_T_3445[1:0]}; // @[Cat.scala 29:58]
|
|
wire _T_3842 = _T_3680 == 7'h40; // @[el2_lib.scala 345:62]
|
|
wire _T_3843 = _T_3830[38] ^ _T_3842; // @[el2_lib.scala 345:44]
|
|
wire [6:0] iccm_corrected_ecc_1 = {_T_3843,_T_3830[31],_T_3830[15],_T_3830[7],_T_3830[3],_T_3830[1:0]}; // @[Cat.scala 29:58]
|
|
wire _T_3859 = _T_3 & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 681:58]
|
|
wire [31:0] iccm_corrected_data_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[el2_ifu_mem_ctl.scala 683:38]
|
|
wire [6:0] iccm_corrected_ecc_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_ecc_0 : iccm_corrected_ecc_1; // @[el2_ifu_mem_ctl.scala 684:37]
|
|
reg iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 692:62]
|
|
wire _T_3867 = ~iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 686:76]
|
|
wire _T_3868 = io_iccm_rd_ecc_single_err & _T_3867; // @[el2_ifu_mem_ctl.scala 686:74]
|
|
wire _T_3870 = _T_3868 & _T_319; // @[el2_ifu_mem_ctl.scala 686:104]
|
|
wire iccm_ecc_write_status = _T_3870 | io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 686:127]
|
|
wire _T_3871 = io_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 687:67]
|
|
reg [13:0] iccm_rw_addr_f; // @[el2_ifu_mem_ctl.scala 691:51]
|
|
wire [13:0] _T_3876 = iccm_rw_addr_f + 14'h1; // @[el2_ifu_mem_ctl.scala 690:102]
|
|
wire [38:0] _T_3880 = {iccm_corrected_ecc_f_mux,iccm_corrected_data_f_mux}; // @[Cat.scala 29:58]
|
|
wire _T_3885 = ~io_ifc_fetch_uncacheable_bf; // @[el2_ifu_mem_ctl.scala 695:41]
|
|
wire _T_3886 = io_ifc_fetch_req_bf & _T_3885; // @[el2_ifu_mem_ctl.scala 695:39]
|
|
wire _T_3887 = ~io_ifc_iccm_access_bf; // @[el2_ifu_mem_ctl.scala 695:72]
|
|
wire _T_3888 = _T_3886 & _T_3887; // @[el2_ifu_mem_ctl.scala 695:70]
|
|
wire _T_3890 = ~miss_state_en; // @[el2_ifu_mem_ctl.scala 696:34]
|
|
wire _T_3891 = _T_2219 & _T_3890; // @[el2_ifu_mem_ctl.scala 696:32]
|
|
wire _T_3894 = _T_2235 & _T_3890; // @[el2_ifu_mem_ctl.scala 697:37]
|
|
wire _T_3895 = _T_3891 | _T_3894; // @[el2_ifu_mem_ctl.scala 696:88]
|
|
wire _T_3896 = miss_state == 3'h7; // @[el2_ifu_mem_ctl.scala 698:19]
|
|
wire _T_3898 = _T_3896 & _T_3890; // @[el2_ifu_mem_ctl.scala 698:41]
|
|
wire _T_3899 = _T_3895 | _T_3898; // @[el2_ifu_mem_ctl.scala 697:88]
|
|
wire _T_3900 = miss_state == 3'h3; // @[el2_ifu_mem_ctl.scala 699:19]
|
|
wire _T_3902 = _T_3900 & _T_3890; // @[el2_ifu_mem_ctl.scala 699:35]
|
|
wire _T_3903 = _T_3899 | _T_3902; // @[el2_ifu_mem_ctl.scala 698:88]
|
|
wire _T_3906 = _T_2234 & _T_3890; // @[el2_ifu_mem_ctl.scala 700:38]
|
|
wire _T_3907 = _T_3903 | _T_3906; // @[el2_ifu_mem_ctl.scala 699:88]
|
|
wire _T_3909 = _T_2235 & miss_state_en; // @[el2_ifu_mem_ctl.scala 701:37]
|
|
wire _T_3910 = miss_nxtstate == 3'h3; // @[el2_ifu_mem_ctl.scala 701:71]
|
|
wire _T_3911 = _T_3909 & _T_3910; // @[el2_ifu_mem_ctl.scala 701:54]
|
|
wire _T_3912 = _T_3907 | _T_3911; // @[el2_ifu_mem_ctl.scala 700:57]
|
|
wire _T_3913 = ~_T_3912; // @[el2_ifu_mem_ctl.scala 696:5]
|
|
wire _T_3914 = _T_3888 & _T_3913; // @[el2_ifu_mem_ctl.scala 695:96]
|
|
wire _T_3915 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 702:28]
|
|
wire _T_3917 = _T_3915 & _T_3885; // @[el2_ifu_mem_ctl.scala 702:50]
|
|
wire _T_3919 = _T_3917 & _T_3887; // @[el2_ifu_mem_ctl.scala 702:81]
|
|
wire [1:0] _T_3922 = write_ic_16_bytes ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_9728 = bus_ifu_wr_en_ff_q & replace_way_mb_any_1; // @[el2_ifu_mem_ctl.scala 797:74]
|
|
wire bus_wren_1 = _T_9728 & miss_pending; // @[el2_ifu_mem_ctl.scala 797:98]
|
|
wire _T_9727 = bus_ifu_wr_en_ff_q & replace_way_mb_any_0; // @[el2_ifu_mem_ctl.scala 797:74]
|
|
wire bus_wren_0 = _T_9727 & miss_pending; // @[el2_ifu_mem_ctl.scala 797:98]
|
|
wire [1:0] bus_ic_wr_en = {bus_wren_1,bus_wren_0}; // @[Cat.scala 29:58]
|
|
wire _T_3928 = ~_T_108; // @[el2_ifu_mem_ctl.scala 705:106]
|
|
wire _T_3929 = _T_2219 & _T_3928; // @[el2_ifu_mem_ctl.scala 705:104]
|
|
wire _T_3930 = _T_2235 | _T_3929; // @[el2_ifu_mem_ctl.scala 705:77]
|
|
wire _T_3934 = ~_T_51; // @[el2_ifu_mem_ctl.scala 705:172]
|
|
wire _T_3935 = _T_3930 & _T_3934; // @[el2_ifu_mem_ctl.scala 705:170]
|
|
wire _T_3936 = ~_T_3935; // @[el2_ifu_mem_ctl.scala 705:44]
|
|
wire _T_3940 = reset_ic_in | reset_ic_ff; // @[el2_ifu_mem_ctl.scala 708:64]
|
|
wire _T_3941 = ~_T_3940; // @[el2_ifu_mem_ctl.scala 708:50]
|
|
wire _T_3942 = _T_276 & _T_3941; // @[el2_ifu_mem_ctl.scala 708:48]
|
|
wire _T_3943 = ~reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 708:81]
|
|
wire ic_valid = _T_3942 & _T_3943; // @[el2_ifu_mem_ctl.scala 708:79]
|
|
wire _T_3945 = debug_c1_clken & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 709:82]
|
|
reg [6:0] ifu_status_wr_addr_ff; // @[el2_ifu_mem_ctl.scala 712:14]
|
|
wire _T_3948 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 715:74]
|
|
wire _T_9725 = bus_ifu_wr_en_ff_q & last_beat; // @[el2_ifu_mem_ctl.scala 796:45]
|
|
wire way_status_wr_en = _T_9725 | ic_act_hit_f; // @[el2_ifu_mem_ctl.scala 796:58]
|
|
reg way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 717:14]
|
|
wire way_status_hit_new = io_ic_rd_hit[0]; // @[el2_ifu_mem_ctl.scala 792:41]
|
|
reg way_status_new_ff; // @[el2_ifu_mem_ctl.scala 723:14]
|
|
wire _T_3968 = ifu_status_wr_addr_ff[2:0] == 3'h0; // @[el2_ifu_mem_ctl.scala 729:128]
|
|
wire _T_3969 = _T_3968 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 729:136]
|
|
wire _T_3972 = ifu_status_wr_addr_ff[2:0] == 3'h1; // @[el2_ifu_mem_ctl.scala 729:128]
|
|
wire _T_3973 = _T_3972 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 729:136]
|
|
wire _T_3976 = ifu_status_wr_addr_ff[2:0] == 3'h2; // @[el2_ifu_mem_ctl.scala 729:128]
|
|
wire _T_3977 = _T_3976 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 729:136]
|
|
wire _T_3980 = ifu_status_wr_addr_ff[2:0] == 3'h3; // @[el2_ifu_mem_ctl.scala 729:128]
|
|
wire _T_3981 = _T_3980 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 729:136]
|
|
wire _T_3984 = ifu_status_wr_addr_ff[2:0] == 3'h4; // @[el2_ifu_mem_ctl.scala 729:128]
|
|
wire _T_3985 = _T_3984 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 729:136]
|
|
wire _T_3988 = ifu_status_wr_addr_ff[2:0] == 3'h5; // @[el2_ifu_mem_ctl.scala 729:128]
|
|
wire _T_3989 = _T_3988 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 729:136]
|
|
wire _T_3992 = ifu_status_wr_addr_ff[2:0] == 3'h6; // @[el2_ifu_mem_ctl.scala 729:128]
|
|
wire _T_3993 = _T_3992 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 729:136]
|
|
wire _T_3996 = ifu_status_wr_addr_ff[2:0] == 3'h7; // @[el2_ifu_mem_ctl.scala 729:128]
|
|
wire _T_3997 = _T_3996 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 729:136]
|
|
wire _T_9731 = _T_100 & replace_way_mb_any_1; // @[el2_ifu_mem_ctl.scala 799:84]
|
|
wire _T_9732 = _T_9731 & miss_pending; // @[el2_ifu_mem_ctl.scala 799:108]
|
|
wire bus_wren_last_1 = _T_9732 & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 799:123]
|
|
wire wren_reset_miss_1 = replace_way_mb_any_1 & reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 800:84]
|
|
wire _T_9734 = bus_wren_last_1 | wren_reset_miss_1; // @[el2_ifu_mem_ctl.scala 801:73]
|
|
wire _T_9729 = _T_100 & replace_way_mb_any_0; // @[el2_ifu_mem_ctl.scala 799:84]
|
|
wire _T_9730 = _T_9729 & miss_pending; // @[el2_ifu_mem_ctl.scala 799:108]
|
|
wire bus_wren_last_0 = _T_9730 & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 799:123]
|
|
wire wren_reset_miss_0 = replace_way_mb_any_0 & reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 800:84]
|
|
wire _T_9733 = bus_wren_last_0 | wren_reset_miss_0; // @[el2_ifu_mem_ctl.scala 801:73]
|
|
wire [1:0] ifu_tag_wren = {_T_9734,_T_9733}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_9769 = _T_3948 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] ic_debug_tag_wr_en = _T_9769 & io_ic_debug_way; // @[el2_ifu_mem_ctl.scala 835:90]
|
|
reg [1:0] ifu_tag_wren_ff; // @[el2_ifu_mem_ctl.scala 744:14]
|
|
reg ic_valid_ff; // @[el2_ifu_mem_ctl.scala 748:14]
|
|
wire _T_5011 = ifu_ic_rw_int_addr_ff[6:5] == 2'h0; // @[el2_ifu_mem_ctl.scala 752:78]
|
|
wire _T_5013 = _T_5011 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 752:87]
|
|
wire _T_5015 = perr_ic_index_ff[6:5] == 2'h0; // @[el2_ifu_mem_ctl.scala 753:70]
|
|
wire _T_5017 = _T_5015 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 753:79]
|
|
wire _T_5018 = _T_5013 | _T_5017; // @[el2_ifu_mem_ctl.scala 752:109]
|
|
wire _T_5019 = _T_5018 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 753:102]
|
|
wire _T_5023 = _T_5011 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 752:87]
|
|
wire _T_5027 = _T_5015 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 753:79]
|
|
wire _T_5028 = _T_5023 | _T_5027; // @[el2_ifu_mem_ctl.scala 752:109]
|
|
wire _T_5029 = _T_5028 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 753:102]
|
|
wire [1:0] tag_valid_clken_0 = {_T_5029,_T_5019}; // @[Cat.scala 29:58]
|
|
wire _T_5031 = ifu_ic_rw_int_addr_ff[6:5] == 2'h1; // @[el2_ifu_mem_ctl.scala 752:78]
|
|
wire _T_5033 = _T_5031 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 752:87]
|
|
wire _T_5035 = perr_ic_index_ff[6:5] == 2'h1; // @[el2_ifu_mem_ctl.scala 753:70]
|
|
wire _T_5037 = _T_5035 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 753:79]
|
|
wire _T_5038 = _T_5033 | _T_5037; // @[el2_ifu_mem_ctl.scala 752:109]
|
|
wire _T_5039 = _T_5038 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 753:102]
|
|
wire _T_5043 = _T_5031 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 752:87]
|
|
wire _T_5047 = _T_5035 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 753:79]
|
|
wire _T_5048 = _T_5043 | _T_5047; // @[el2_ifu_mem_ctl.scala 752:109]
|
|
wire _T_5049 = _T_5048 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 753:102]
|
|
wire [1:0] tag_valid_clken_1 = {_T_5049,_T_5039}; // @[Cat.scala 29:58]
|
|
wire _T_5051 = ifu_ic_rw_int_addr_ff[6:5] == 2'h2; // @[el2_ifu_mem_ctl.scala 752:78]
|
|
wire _T_5053 = _T_5051 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 752:87]
|
|
wire _T_5055 = perr_ic_index_ff[6:5] == 2'h2; // @[el2_ifu_mem_ctl.scala 753:70]
|
|
wire _T_5057 = _T_5055 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 753:79]
|
|
wire _T_5058 = _T_5053 | _T_5057; // @[el2_ifu_mem_ctl.scala 752:109]
|
|
wire _T_5059 = _T_5058 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 753:102]
|
|
wire _T_5063 = _T_5051 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 752:87]
|
|
wire _T_5067 = _T_5055 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 753:79]
|
|
wire _T_5068 = _T_5063 | _T_5067; // @[el2_ifu_mem_ctl.scala 752:109]
|
|
wire _T_5069 = _T_5068 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 753:102]
|
|
wire [1:0] tag_valid_clken_2 = {_T_5069,_T_5059}; // @[Cat.scala 29:58]
|
|
wire _T_5071 = ifu_ic_rw_int_addr_ff[6:5] == 2'h3; // @[el2_ifu_mem_ctl.scala 752:78]
|
|
wire _T_5073 = _T_5071 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 752:87]
|
|
wire _T_5075 = perr_ic_index_ff[6:5] == 2'h3; // @[el2_ifu_mem_ctl.scala 753:70]
|
|
wire _T_5077 = _T_5075 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 753:79]
|
|
wire _T_5078 = _T_5073 | _T_5077; // @[el2_ifu_mem_ctl.scala 752:109]
|
|
wire _T_5079 = _T_5078 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 753:102]
|
|
wire _T_5083 = _T_5071 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 752:87]
|
|
wire _T_5087 = _T_5075 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 753:79]
|
|
wire _T_5088 = _T_5083 | _T_5087; // @[el2_ifu_mem_ctl.scala 752:109]
|
|
wire _T_5089 = _T_5088 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 753:102]
|
|
wire [1:0] tag_valid_clken_3 = {_T_5089,_T_5079}; // @[Cat.scala 29:58]
|
|
wire _T_5100 = ic_valid_ff & _T_195; // @[el2_ifu_mem_ctl.scala 761:97]
|
|
wire _T_5101 = ~perr_sel_invalidate; // @[el2_ifu_mem_ctl.scala 761:124]
|
|
wire _T_5102 = _T_5100 & _T_5101; // @[el2_ifu_mem_ctl.scala 761:122]
|
|
wire _T_5105 = _T_4619 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5106 = perr_ic_index_ff == 7'h0; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5108 = _T_5106 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5109 = _T_5105 | _T_5108; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5110 = _T_5109 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5120 = _T_4620 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5121 = perr_ic_index_ff == 7'h1; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5123 = _T_5121 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5124 = _T_5120 | _T_5123; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5125 = _T_5124 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5135 = _T_4621 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5136 = perr_ic_index_ff == 7'h2; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5138 = _T_5136 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5139 = _T_5135 | _T_5138; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5140 = _T_5139 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5150 = _T_4622 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5151 = perr_ic_index_ff == 7'h3; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5153 = _T_5151 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5154 = _T_5150 | _T_5153; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5155 = _T_5154 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5165 = _T_4623 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5166 = perr_ic_index_ff == 7'h4; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5168 = _T_5166 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5169 = _T_5165 | _T_5168; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5170 = _T_5169 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5180 = _T_4624 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5181 = perr_ic_index_ff == 7'h5; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5183 = _T_5181 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5184 = _T_5180 | _T_5183; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5185 = _T_5184 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5195 = _T_4625 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5196 = perr_ic_index_ff == 7'h6; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5198 = _T_5196 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5199 = _T_5195 | _T_5198; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5200 = _T_5199 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5210 = _T_4626 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5211 = perr_ic_index_ff == 7'h7; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5213 = _T_5211 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5214 = _T_5210 | _T_5213; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5215 = _T_5214 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5225 = _T_4627 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5226 = perr_ic_index_ff == 7'h8; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5228 = _T_5226 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5229 = _T_5225 | _T_5228; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5230 = _T_5229 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5240 = _T_4628 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5241 = perr_ic_index_ff == 7'h9; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5243 = _T_5241 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5244 = _T_5240 | _T_5243; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5245 = _T_5244 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5255 = _T_4629 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5256 = perr_ic_index_ff == 7'ha; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5258 = _T_5256 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5259 = _T_5255 | _T_5258; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5260 = _T_5259 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5270 = _T_4630 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5271 = perr_ic_index_ff == 7'hb; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5273 = _T_5271 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5274 = _T_5270 | _T_5273; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5275 = _T_5274 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5285 = _T_4631 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5286 = perr_ic_index_ff == 7'hc; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5288 = _T_5286 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5289 = _T_5285 | _T_5288; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5290 = _T_5289 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5300 = _T_4632 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5301 = perr_ic_index_ff == 7'hd; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5303 = _T_5301 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5304 = _T_5300 | _T_5303; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5305 = _T_5304 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5315 = _T_4633 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5316 = perr_ic_index_ff == 7'he; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5318 = _T_5316 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5319 = _T_5315 | _T_5318; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5320 = _T_5319 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5330 = _T_4634 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5331 = perr_ic_index_ff == 7'hf; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5333 = _T_5331 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5334 = _T_5330 | _T_5333; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5335 = _T_5334 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5345 = _T_4635 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5346 = perr_ic_index_ff == 7'h10; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5348 = _T_5346 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5349 = _T_5345 | _T_5348; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5350 = _T_5349 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5360 = _T_4636 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5361 = perr_ic_index_ff == 7'h11; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5363 = _T_5361 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5364 = _T_5360 | _T_5363; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5365 = _T_5364 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5375 = _T_4637 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5376 = perr_ic_index_ff == 7'h12; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5378 = _T_5376 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5379 = _T_5375 | _T_5378; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5380 = _T_5379 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5390 = _T_4638 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5391 = perr_ic_index_ff == 7'h13; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5393 = _T_5391 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5394 = _T_5390 | _T_5393; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5395 = _T_5394 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5405 = _T_4639 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5406 = perr_ic_index_ff == 7'h14; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5408 = _T_5406 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5409 = _T_5405 | _T_5408; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5410 = _T_5409 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5420 = _T_4640 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5421 = perr_ic_index_ff == 7'h15; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5423 = _T_5421 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5424 = _T_5420 | _T_5423; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5425 = _T_5424 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5435 = _T_4641 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5436 = perr_ic_index_ff == 7'h16; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5438 = _T_5436 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5439 = _T_5435 | _T_5438; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5440 = _T_5439 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5450 = _T_4642 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5451 = perr_ic_index_ff == 7'h17; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5453 = _T_5451 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5454 = _T_5450 | _T_5453; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5455 = _T_5454 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5465 = _T_4643 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5466 = perr_ic_index_ff == 7'h18; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5468 = _T_5466 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5469 = _T_5465 | _T_5468; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5470 = _T_5469 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5480 = _T_4644 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5481 = perr_ic_index_ff == 7'h19; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5483 = _T_5481 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5484 = _T_5480 | _T_5483; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5485 = _T_5484 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5495 = _T_4645 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5496 = perr_ic_index_ff == 7'h1a; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5498 = _T_5496 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5499 = _T_5495 | _T_5498; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5500 = _T_5499 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5510 = _T_4646 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5511 = perr_ic_index_ff == 7'h1b; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5513 = _T_5511 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5514 = _T_5510 | _T_5513; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5515 = _T_5514 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5525 = _T_4647 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5526 = perr_ic_index_ff == 7'h1c; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5528 = _T_5526 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5529 = _T_5525 | _T_5528; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5530 = _T_5529 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5540 = _T_4648 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5541 = perr_ic_index_ff == 7'h1d; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5543 = _T_5541 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5544 = _T_5540 | _T_5543; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5545 = _T_5544 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5555 = _T_4649 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5556 = perr_ic_index_ff == 7'h1e; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5558 = _T_5556 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5559 = _T_5555 | _T_5558; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5560 = _T_5559 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5570 = _T_4650 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5571 = perr_ic_index_ff == 7'h1f; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_5573 = _T_5571 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5574 = _T_5570 | _T_5573; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5575 = _T_5574 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5585 = _T_4619 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5588 = _T_5106 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5589 = _T_5585 | _T_5588; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5590 = _T_5589 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5600 = _T_4620 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5603 = _T_5121 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5604 = _T_5600 | _T_5603; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5605 = _T_5604 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5615 = _T_4621 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5618 = _T_5136 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5619 = _T_5615 | _T_5618; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5620 = _T_5619 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5630 = _T_4622 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5633 = _T_5151 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5634 = _T_5630 | _T_5633; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5635 = _T_5634 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5645 = _T_4623 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5648 = _T_5166 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5649 = _T_5645 | _T_5648; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5650 = _T_5649 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5660 = _T_4624 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5663 = _T_5181 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5664 = _T_5660 | _T_5663; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5665 = _T_5664 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5675 = _T_4625 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5678 = _T_5196 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5679 = _T_5675 | _T_5678; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5680 = _T_5679 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5690 = _T_4626 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5693 = _T_5211 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5694 = _T_5690 | _T_5693; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5695 = _T_5694 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5705 = _T_4627 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5708 = _T_5226 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5709 = _T_5705 | _T_5708; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5710 = _T_5709 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5720 = _T_4628 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5723 = _T_5241 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5724 = _T_5720 | _T_5723; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5725 = _T_5724 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5735 = _T_4629 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5738 = _T_5256 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5739 = _T_5735 | _T_5738; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5740 = _T_5739 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5750 = _T_4630 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5753 = _T_5271 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5754 = _T_5750 | _T_5753; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5755 = _T_5754 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5765 = _T_4631 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5768 = _T_5286 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5769 = _T_5765 | _T_5768; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5770 = _T_5769 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5780 = _T_4632 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5783 = _T_5301 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5784 = _T_5780 | _T_5783; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5785 = _T_5784 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5795 = _T_4633 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5798 = _T_5316 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5799 = _T_5795 | _T_5798; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5800 = _T_5799 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5810 = _T_4634 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5813 = _T_5331 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5814 = _T_5810 | _T_5813; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5815 = _T_5814 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5825 = _T_4635 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5828 = _T_5346 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5829 = _T_5825 | _T_5828; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5830 = _T_5829 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5840 = _T_4636 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5843 = _T_5361 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5844 = _T_5840 | _T_5843; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5845 = _T_5844 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5855 = _T_4637 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5858 = _T_5376 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5859 = _T_5855 | _T_5858; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5860 = _T_5859 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5870 = _T_4638 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5873 = _T_5391 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5874 = _T_5870 | _T_5873; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5875 = _T_5874 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5885 = _T_4639 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5888 = _T_5406 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5889 = _T_5885 | _T_5888; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5890 = _T_5889 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5900 = _T_4640 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5903 = _T_5421 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5904 = _T_5900 | _T_5903; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5905 = _T_5904 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5915 = _T_4641 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5918 = _T_5436 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5919 = _T_5915 | _T_5918; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5920 = _T_5919 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5930 = _T_4642 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5933 = _T_5451 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5934 = _T_5930 | _T_5933; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5935 = _T_5934 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5945 = _T_4643 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5948 = _T_5466 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5949 = _T_5945 | _T_5948; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5950 = _T_5949 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5960 = _T_4644 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5963 = _T_5481 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5964 = _T_5960 | _T_5963; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5965 = _T_5964 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5975 = _T_4645 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5978 = _T_5496 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5979 = _T_5975 | _T_5978; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5980 = _T_5979 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_5990 = _T_4646 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_5993 = _T_5511 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_5994 = _T_5990 | _T_5993; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_5995 = _T_5994 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6005 = _T_4647 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6008 = _T_5526 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6009 = _T_6005 | _T_6008; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6010 = _T_6009 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6020 = _T_4648 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6023 = _T_5541 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6024 = _T_6020 | _T_6023; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6025 = _T_6024 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6035 = _T_4649 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6038 = _T_5556 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6039 = _T_6035 | _T_6038; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6040 = _T_6039 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6050 = _T_4650 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6053 = _T_5571 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6054 = _T_6050 | _T_6053; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6055 = _T_6054 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6065 = _T_4651 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6066 = perr_ic_index_ff == 7'h20; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6068 = _T_6066 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6069 = _T_6065 | _T_6068; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6070 = _T_6069 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6080 = _T_4652 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6081 = perr_ic_index_ff == 7'h21; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6083 = _T_6081 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6084 = _T_6080 | _T_6083; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6085 = _T_6084 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6095 = _T_4653 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6096 = perr_ic_index_ff == 7'h22; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6098 = _T_6096 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6099 = _T_6095 | _T_6098; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6100 = _T_6099 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6110 = _T_4654 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6111 = perr_ic_index_ff == 7'h23; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6113 = _T_6111 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6114 = _T_6110 | _T_6113; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6115 = _T_6114 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6125 = _T_4655 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6126 = perr_ic_index_ff == 7'h24; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6128 = _T_6126 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6129 = _T_6125 | _T_6128; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6130 = _T_6129 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6140 = _T_4656 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6141 = perr_ic_index_ff == 7'h25; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6143 = _T_6141 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6144 = _T_6140 | _T_6143; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6145 = _T_6144 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6155 = _T_4657 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6156 = perr_ic_index_ff == 7'h26; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6158 = _T_6156 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6159 = _T_6155 | _T_6158; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6160 = _T_6159 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6170 = _T_4658 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6171 = perr_ic_index_ff == 7'h27; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6173 = _T_6171 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6174 = _T_6170 | _T_6173; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6175 = _T_6174 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6185 = _T_4659 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6186 = perr_ic_index_ff == 7'h28; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6188 = _T_6186 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6189 = _T_6185 | _T_6188; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6190 = _T_6189 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6200 = _T_4660 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6201 = perr_ic_index_ff == 7'h29; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6203 = _T_6201 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6204 = _T_6200 | _T_6203; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6205 = _T_6204 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6215 = _T_4661 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6216 = perr_ic_index_ff == 7'h2a; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6218 = _T_6216 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6219 = _T_6215 | _T_6218; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6220 = _T_6219 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6230 = _T_4662 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6231 = perr_ic_index_ff == 7'h2b; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6233 = _T_6231 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6234 = _T_6230 | _T_6233; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6235 = _T_6234 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6245 = _T_4663 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6246 = perr_ic_index_ff == 7'h2c; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6248 = _T_6246 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6249 = _T_6245 | _T_6248; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6250 = _T_6249 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6260 = _T_4664 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6261 = perr_ic_index_ff == 7'h2d; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6263 = _T_6261 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6264 = _T_6260 | _T_6263; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6265 = _T_6264 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6275 = _T_4665 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6276 = perr_ic_index_ff == 7'h2e; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6278 = _T_6276 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6279 = _T_6275 | _T_6278; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6280 = _T_6279 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6290 = _T_4666 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6291 = perr_ic_index_ff == 7'h2f; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6293 = _T_6291 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6294 = _T_6290 | _T_6293; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6295 = _T_6294 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6305 = _T_4667 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6306 = perr_ic_index_ff == 7'h30; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6308 = _T_6306 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6309 = _T_6305 | _T_6308; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6310 = _T_6309 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6320 = _T_4668 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6321 = perr_ic_index_ff == 7'h31; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6323 = _T_6321 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6324 = _T_6320 | _T_6323; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6325 = _T_6324 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6335 = _T_4669 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6336 = perr_ic_index_ff == 7'h32; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6338 = _T_6336 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6339 = _T_6335 | _T_6338; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6340 = _T_6339 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6350 = _T_4670 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6351 = perr_ic_index_ff == 7'h33; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6353 = _T_6351 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6354 = _T_6350 | _T_6353; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6355 = _T_6354 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6365 = _T_4671 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6366 = perr_ic_index_ff == 7'h34; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6368 = _T_6366 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6369 = _T_6365 | _T_6368; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6370 = _T_6369 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6380 = _T_4672 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6381 = perr_ic_index_ff == 7'h35; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6383 = _T_6381 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6384 = _T_6380 | _T_6383; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6385 = _T_6384 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6395 = _T_4673 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6396 = perr_ic_index_ff == 7'h36; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6398 = _T_6396 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6399 = _T_6395 | _T_6398; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6400 = _T_6399 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6410 = _T_4674 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6411 = perr_ic_index_ff == 7'h37; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6413 = _T_6411 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6414 = _T_6410 | _T_6413; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6415 = _T_6414 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6425 = _T_4675 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6426 = perr_ic_index_ff == 7'h38; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6428 = _T_6426 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6429 = _T_6425 | _T_6428; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6430 = _T_6429 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6440 = _T_4676 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6441 = perr_ic_index_ff == 7'h39; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6443 = _T_6441 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6444 = _T_6440 | _T_6443; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6445 = _T_6444 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6455 = _T_4677 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6456 = perr_ic_index_ff == 7'h3a; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6458 = _T_6456 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6459 = _T_6455 | _T_6458; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6460 = _T_6459 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6470 = _T_4678 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6471 = perr_ic_index_ff == 7'h3b; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6473 = _T_6471 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6474 = _T_6470 | _T_6473; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6475 = _T_6474 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6485 = _T_4679 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6486 = perr_ic_index_ff == 7'h3c; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6488 = _T_6486 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6489 = _T_6485 | _T_6488; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6490 = _T_6489 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6500 = _T_4680 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6501 = perr_ic_index_ff == 7'h3d; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6503 = _T_6501 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6504 = _T_6500 | _T_6503; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6505 = _T_6504 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6515 = _T_4681 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6516 = perr_ic_index_ff == 7'h3e; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6518 = _T_6516 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6519 = _T_6515 | _T_6518; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6520 = _T_6519 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6530 = _T_4682 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6531 = perr_ic_index_ff == 7'h3f; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_6533 = _T_6531 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6534 = _T_6530 | _T_6533; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6535 = _T_6534 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6545 = _T_4651 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6548 = _T_6066 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6549 = _T_6545 | _T_6548; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6550 = _T_6549 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6560 = _T_4652 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6563 = _T_6081 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6564 = _T_6560 | _T_6563; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6565 = _T_6564 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6575 = _T_4653 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6578 = _T_6096 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6579 = _T_6575 | _T_6578; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6580 = _T_6579 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6590 = _T_4654 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6593 = _T_6111 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6594 = _T_6590 | _T_6593; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6595 = _T_6594 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6605 = _T_4655 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6608 = _T_6126 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6609 = _T_6605 | _T_6608; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6610 = _T_6609 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6620 = _T_4656 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6623 = _T_6141 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6624 = _T_6620 | _T_6623; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6625 = _T_6624 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6635 = _T_4657 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6638 = _T_6156 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6639 = _T_6635 | _T_6638; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6640 = _T_6639 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6650 = _T_4658 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6653 = _T_6171 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6654 = _T_6650 | _T_6653; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6655 = _T_6654 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6665 = _T_4659 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6668 = _T_6186 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6669 = _T_6665 | _T_6668; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6670 = _T_6669 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6680 = _T_4660 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6683 = _T_6201 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6684 = _T_6680 | _T_6683; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6685 = _T_6684 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6695 = _T_4661 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6698 = _T_6216 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6699 = _T_6695 | _T_6698; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6700 = _T_6699 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6710 = _T_4662 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6713 = _T_6231 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6714 = _T_6710 | _T_6713; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6715 = _T_6714 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6725 = _T_4663 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6728 = _T_6246 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6729 = _T_6725 | _T_6728; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6730 = _T_6729 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6740 = _T_4664 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6743 = _T_6261 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6744 = _T_6740 | _T_6743; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6745 = _T_6744 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6755 = _T_4665 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6758 = _T_6276 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6759 = _T_6755 | _T_6758; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6760 = _T_6759 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6770 = _T_4666 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6773 = _T_6291 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6774 = _T_6770 | _T_6773; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6775 = _T_6774 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6785 = _T_4667 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6788 = _T_6306 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6789 = _T_6785 | _T_6788; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6790 = _T_6789 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6800 = _T_4668 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6803 = _T_6321 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6804 = _T_6800 | _T_6803; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6805 = _T_6804 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6815 = _T_4669 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6818 = _T_6336 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6819 = _T_6815 | _T_6818; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6820 = _T_6819 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6830 = _T_4670 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6833 = _T_6351 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6834 = _T_6830 | _T_6833; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6835 = _T_6834 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6845 = _T_4671 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6848 = _T_6366 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6849 = _T_6845 | _T_6848; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6850 = _T_6849 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6860 = _T_4672 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6863 = _T_6381 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6864 = _T_6860 | _T_6863; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6865 = _T_6864 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6875 = _T_4673 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6878 = _T_6396 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6879 = _T_6875 | _T_6878; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6880 = _T_6879 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6890 = _T_4674 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6893 = _T_6411 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6894 = _T_6890 | _T_6893; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6895 = _T_6894 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6905 = _T_4675 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6908 = _T_6426 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6909 = _T_6905 | _T_6908; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6910 = _T_6909 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6920 = _T_4676 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6923 = _T_6441 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6924 = _T_6920 | _T_6923; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6925 = _T_6924 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6935 = _T_4677 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6938 = _T_6456 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6939 = _T_6935 | _T_6938; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6940 = _T_6939 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6950 = _T_4678 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6953 = _T_6471 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6954 = _T_6950 | _T_6953; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6955 = _T_6954 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6965 = _T_4679 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6968 = _T_6486 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6969 = _T_6965 | _T_6968; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6970 = _T_6969 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6980 = _T_4680 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6983 = _T_6501 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6984 = _T_6980 | _T_6983; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_6985 = _T_6984 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_6995 = _T_4681 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_6998 = _T_6516 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_6999 = _T_6995 | _T_6998; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7000 = _T_6999 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7010 = _T_4682 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7013 = _T_6531 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7014 = _T_7010 | _T_7013; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7015 = _T_7014 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7025 = _T_4683 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7026 = perr_ic_index_ff == 7'h40; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7028 = _T_7026 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7029 = _T_7025 | _T_7028; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7030 = _T_7029 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7040 = _T_4684 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7041 = perr_ic_index_ff == 7'h41; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7043 = _T_7041 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7044 = _T_7040 | _T_7043; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7045 = _T_7044 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7055 = _T_4685 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7056 = perr_ic_index_ff == 7'h42; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7058 = _T_7056 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7059 = _T_7055 | _T_7058; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7060 = _T_7059 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7070 = _T_4686 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7071 = perr_ic_index_ff == 7'h43; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7073 = _T_7071 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7074 = _T_7070 | _T_7073; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7075 = _T_7074 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7085 = _T_4687 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7086 = perr_ic_index_ff == 7'h44; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7088 = _T_7086 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7089 = _T_7085 | _T_7088; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7090 = _T_7089 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7100 = _T_4688 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7101 = perr_ic_index_ff == 7'h45; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7103 = _T_7101 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7104 = _T_7100 | _T_7103; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7105 = _T_7104 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7115 = _T_4689 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7116 = perr_ic_index_ff == 7'h46; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7118 = _T_7116 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7119 = _T_7115 | _T_7118; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7120 = _T_7119 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7130 = _T_4690 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7131 = perr_ic_index_ff == 7'h47; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7133 = _T_7131 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7134 = _T_7130 | _T_7133; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7135 = _T_7134 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7145 = _T_4691 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7146 = perr_ic_index_ff == 7'h48; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7148 = _T_7146 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7149 = _T_7145 | _T_7148; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7150 = _T_7149 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7160 = _T_4692 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7161 = perr_ic_index_ff == 7'h49; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7163 = _T_7161 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7164 = _T_7160 | _T_7163; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7165 = _T_7164 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7175 = _T_4693 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7176 = perr_ic_index_ff == 7'h4a; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7178 = _T_7176 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7179 = _T_7175 | _T_7178; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7180 = _T_7179 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7190 = _T_4694 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7191 = perr_ic_index_ff == 7'h4b; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7193 = _T_7191 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7194 = _T_7190 | _T_7193; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7195 = _T_7194 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7205 = _T_4695 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7206 = perr_ic_index_ff == 7'h4c; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7208 = _T_7206 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7209 = _T_7205 | _T_7208; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7210 = _T_7209 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7220 = _T_4696 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7221 = perr_ic_index_ff == 7'h4d; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7223 = _T_7221 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7224 = _T_7220 | _T_7223; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7225 = _T_7224 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7235 = _T_4697 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7236 = perr_ic_index_ff == 7'h4e; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7238 = _T_7236 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7239 = _T_7235 | _T_7238; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7240 = _T_7239 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7250 = _T_4698 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7251 = perr_ic_index_ff == 7'h4f; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7253 = _T_7251 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7254 = _T_7250 | _T_7253; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7255 = _T_7254 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7265 = _T_4699 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7266 = perr_ic_index_ff == 7'h50; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7268 = _T_7266 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7269 = _T_7265 | _T_7268; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7270 = _T_7269 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7280 = _T_4700 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7281 = perr_ic_index_ff == 7'h51; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7283 = _T_7281 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7284 = _T_7280 | _T_7283; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7285 = _T_7284 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7295 = _T_4701 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7296 = perr_ic_index_ff == 7'h52; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7298 = _T_7296 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7299 = _T_7295 | _T_7298; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7300 = _T_7299 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7310 = _T_4702 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7311 = perr_ic_index_ff == 7'h53; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7313 = _T_7311 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7314 = _T_7310 | _T_7313; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7315 = _T_7314 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7325 = _T_4703 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7326 = perr_ic_index_ff == 7'h54; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7328 = _T_7326 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7329 = _T_7325 | _T_7328; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7330 = _T_7329 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7340 = _T_4704 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7341 = perr_ic_index_ff == 7'h55; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7343 = _T_7341 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7344 = _T_7340 | _T_7343; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7345 = _T_7344 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7355 = _T_4705 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7356 = perr_ic_index_ff == 7'h56; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7358 = _T_7356 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7359 = _T_7355 | _T_7358; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7360 = _T_7359 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7370 = _T_4706 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7371 = perr_ic_index_ff == 7'h57; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7373 = _T_7371 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7374 = _T_7370 | _T_7373; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7375 = _T_7374 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7385 = _T_4707 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7386 = perr_ic_index_ff == 7'h58; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7388 = _T_7386 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7389 = _T_7385 | _T_7388; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7390 = _T_7389 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7400 = _T_4708 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7401 = perr_ic_index_ff == 7'h59; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7403 = _T_7401 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7404 = _T_7400 | _T_7403; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7405 = _T_7404 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7415 = _T_4709 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7416 = perr_ic_index_ff == 7'h5a; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7418 = _T_7416 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7419 = _T_7415 | _T_7418; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7420 = _T_7419 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7430 = _T_4710 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7431 = perr_ic_index_ff == 7'h5b; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7433 = _T_7431 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7434 = _T_7430 | _T_7433; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7435 = _T_7434 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7445 = _T_4711 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7446 = perr_ic_index_ff == 7'h5c; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7448 = _T_7446 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7449 = _T_7445 | _T_7448; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7450 = _T_7449 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7460 = _T_4712 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7461 = perr_ic_index_ff == 7'h5d; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7463 = _T_7461 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7464 = _T_7460 | _T_7463; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7465 = _T_7464 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7475 = _T_4713 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7476 = perr_ic_index_ff == 7'h5e; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7478 = _T_7476 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7479 = _T_7475 | _T_7478; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7480 = _T_7479 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7490 = _T_4714 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7491 = perr_ic_index_ff == 7'h5f; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7493 = _T_7491 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7494 = _T_7490 | _T_7493; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7495 = _T_7494 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7505 = _T_4683 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7508 = _T_7026 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7509 = _T_7505 | _T_7508; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7510 = _T_7509 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7520 = _T_4684 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7523 = _T_7041 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7524 = _T_7520 | _T_7523; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7525 = _T_7524 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7535 = _T_4685 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7538 = _T_7056 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7539 = _T_7535 | _T_7538; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7540 = _T_7539 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7550 = _T_4686 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7553 = _T_7071 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7554 = _T_7550 | _T_7553; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7555 = _T_7554 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7565 = _T_4687 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7568 = _T_7086 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7569 = _T_7565 | _T_7568; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7570 = _T_7569 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7580 = _T_4688 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7583 = _T_7101 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7584 = _T_7580 | _T_7583; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7585 = _T_7584 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7595 = _T_4689 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7598 = _T_7116 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7599 = _T_7595 | _T_7598; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7600 = _T_7599 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7610 = _T_4690 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7613 = _T_7131 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7614 = _T_7610 | _T_7613; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7615 = _T_7614 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7625 = _T_4691 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7628 = _T_7146 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7629 = _T_7625 | _T_7628; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7630 = _T_7629 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7640 = _T_4692 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7643 = _T_7161 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7644 = _T_7640 | _T_7643; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7645 = _T_7644 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7655 = _T_4693 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7658 = _T_7176 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7659 = _T_7655 | _T_7658; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7660 = _T_7659 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7670 = _T_4694 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7673 = _T_7191 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7674 = _T_7670 | _T_7673; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7675 = _T_7674 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7685 = _T_4695 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7688 = _T_7206 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7689 = _T_7685 | _T_7688; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7690 = _T_7689 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7700 = _T_4696 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7703 = _T_7221 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7704 = _T_7700 | _T_7703; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7705 = _T_7704 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7715 = _T_4697 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7718 = _T_7236 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7719 = _T_7715 | _T_7718; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7720 = _T_7719 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7730 = _T_4698 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7733 = _T_7251 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7734 = _T_7730 | _T_7733; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7735 = _T_7734 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7745 = _T_4699 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7748 = _T_7266 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7749 = _T_7745 | _T_7748; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7750 = _T_7749 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7760 = _T_4700 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7763 = _T_7281 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7764 = _T_7760 | _T_7763; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7765 = _T_7764 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7775 = _T_4701 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7778 = _T_7296 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7779 = _T_7775 | _T_7778; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7780 = _T_7779 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7790 = _T_4702 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7793 = _T_7311 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7794 = _T_7790 | _T_7793; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7795 = _T_7794 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7805 = _T_4703 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7808 = _T_7326 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7809 = _T_7805 | _T_7808; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7810 = _T_7809 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7820 = _T_4704 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7823 = _T_7341 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7824 = _T_7820 | _T_7823; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7825 = _T_7824 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7835 = _T_4705 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7838 = _T_7356 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7839 = _T_7835 | _T_7838; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7840 = _T_7839 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7850 = _T_4706 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7853 = _T_7371 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7854 = _T_7850 | _T_7853; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7855 = _T_7854 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7865 = _T_4707 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7868 = _T_7386 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7869 = _T_7865 | _T_7868; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7870 = _T_7869 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7880 = _T_4708 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7883 = _T_7401 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7884 = _T_7880 | _T_7883; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7885 = _T_7884 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7895 = _T_4709 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7898 = _T_7416 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7899 = _T_7895 | _T_7898; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7900 = _T_7899 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7910 = _T_4710 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7913 = _T_7431 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7914 = _T_7910 | _T_7913; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7915 = _T_7914 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7925 = _T_4711 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7928 = _T_7446 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7929 = _T_7925 | _T_7928; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7930 = _T_7929 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7940 = _T_4712 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7943 = _T_7461 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7944 = _T_7940 | _T_7943; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7945 = _T_7944 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7955 = _T_4713 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7958 = _T_7476 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7959 = _T_7955 | _T_7958; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7960 = _T_7959 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7970 = _T_4714 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7973 = _T_7491 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7974 = _T_7970 | _T_7973; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7975 = _T_7974 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_7985 = _T_4715 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_7986 = perr_ic_index_ff == 7'h60; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_7988 = _T_7986 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_7989 = _T_7985 | _T_7988; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_7990 = _T_7989 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8000 = _T_4716 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8001 = perr_ic_index_ff == 7'h61; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8003 = _T_8001 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8004 = _T_8000 | _T_8003; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8005 = _T_8004 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8015 = _T_4717 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8016 = perr_ic_index_ff == 7'h62; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8018 = _T_8016 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8019 = _T_8015 | _T_8018; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8020 = _T_8019 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8030 = _T_4718 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8031 = perr_ic_index_ff == 7'h63; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8033 = _T_8031 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8034 = _T_8030 | _T_8033; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8035 = _T_8034 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8045 = _T_4719 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8046 = perr_ic_index_ff == 7'h64; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8048 = _T_8046 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8049 = _T_8045 | _T_8048; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8050 = _T_8049 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8060 = _T_4720 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8061 = perr_ic_index_ff == 7'h65; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8063 = _T_8061 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8064 = _T_8060 | _T_8063; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8065 = _T_8064 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8075 = _T_4721 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8076 = perr_ic_index_ff == 7'h66; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8078 = _T_8076 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8079 = _T_8075 | _T_8078; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8080 = _T_8079 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8090 = _T_4722 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8091 = perr_ic_index_ff == 7'h67; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8093 = _T_8091 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8094 = _T_8090 | _T_8093; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8095 = _T_8094 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8105 = _T_4723 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8106 = perr_ic_index_ff == 7'h68; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8108 = _T_8106 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8109 = _T_8105 | _T_8108; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8110 = _T_8109 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8120 = _T_4724 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8121 = perr_ic_index_ff == 7'h69; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8123 = _T_8121 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8124 = _T_8120 | _T_8123; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8125 = _T_8124 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8135 = _T_4725 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8136 = perr_ic_index_ff == 7'h6a; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8138 = _T_8136 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8139 = _T_8135 | _T_8138; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8140 = _T_8139 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8150 = _T_4726 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8151 = perr_ic_index_ff == 7'h6b; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8153 = _T_8151 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8154 = _T_8150 | _T_8153; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8155 = _T_8154 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8165 = _T_4727 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8166 = perr_ic_index_ff == 7'h6c; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8168 = _T_8166 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8169 = _T_8165 | _T_8168; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8170 = _T_8169 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8180 = _T_4728 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8181 = perr_ic_index_ff == 7'h6d; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8183 = _T_8181 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8184 = _T_8180 | _T_8183; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8185 = _T_8184 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8195 = _T_4729 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8196 = perr_ic_index_ff == 7'h6e; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8198 = _T_8196 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8199 = _T_8195 | _T_8198; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8200 = _T_8199 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8210 = _T_4730 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8211 = perr_ic_index_ff == 7'h6f; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8213 = _T_8211 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8214 = _T_8210 | _T_8213; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8215 = _T_8214 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8225 = _T_4731 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8226 = perr_ic_index_ff == 7'h70; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8228 = _T_8226 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8229 = _T_8225 | _T_8228; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8230 = _T_8229 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8240 = _T_4732 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8241 = perr_ic_index_ff == 7'h71; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8243 = _T_8241 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8244 = _T_8240 | _T_8243; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8245 = _T_8244 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8255 = _T_4733 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8256 = perr_ic_index_ff == 7'h72; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8258 = _T_8256 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8259 = _T_8255 | _T_8258; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8260 = _T_8259 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8270 = _T_4734 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8271 = perr_ic_index_ff == 7'h73; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8273 = _T_8271 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8274 = _T_8270 | _T_8273; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8275 = _T_8274 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8285 = _T_4735 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8286 = perr_ic_index_ff == 7'h74; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8288 = _T_8286 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8289 = _T_8285 | _T_8288; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8290 = _T_8289 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8300 = _T_4736 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8301 = perr_ic_index_ff == 7'h75; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8303 = _T_8301 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8304 = _T_8300 | _T_8303; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8305 = _T_8304 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8315 = _T_4737 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8316 = perr_ic_index_ff == 7'h76; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8318 = _T_8316 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8319 = _T_8315 | _T_8318; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8320 = _T_8319 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8330 = _T_4738 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8331 = perr_ic_index_ff == 7'h77; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8333 = _T_8331 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8334 = _T_8330 | _T_8333; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8335 = _T_8334 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8345 = _T_4739 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8346 = perr_ic_index_ff == 7'h78; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8348 = _T_8346 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8349 = _T_8345 | _T_8348; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8350 = _T_8349 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8360 = _T_4740 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8361 = perr_ic_index_ff == 7'h79; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8363 = _T_8361 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8364 = _T_8360 | _T_8363; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8365 = _T_8364 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8375 = _T_4741 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8376 = perr_ic_index_ff == 7'h7a; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8378 = _T_8376 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8379 = _T_8375 | _T_8378; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8380 = _T_8379 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8390 = _T_4742 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8391 = perr_ic_index_ff == 7'h7b; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8393 = _T_8391 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8394 = _T_8390 | _T_8393; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8395 = _T_8394 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8405 = _T_4743 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8406 = perr_ic_index_ff == 7'h7c; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8408 = _T_8406 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8409 = _T_8405 | _T_8408; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8410 = _T_8409 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8420 = _T_4744 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8421 = perr_ic_index_ff == 7'h7d; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8423 = _T_8421 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8424 = _T_8420 | _T_8423; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8425 = _T_8424 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8435 = _T_4745 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8436 = perr_ic_index_ff == 7'h7e; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8438 = _T_8436 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8439 = _T_8435 | _T_8438; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8440 = _T_8439 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8450 = _T_4746 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8451 = perr_ic_index_ff == 7'h7f; // @[el2_ifu_mem_ctl.scala 762:102]
|
|
wire _T_8453 = _T_8451 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8454 = _T_8450 | _T_8453; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8455 = _T_8454 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8465 = _T_4715 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8468 = _T_7986 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8469 = _T_8465 | _T_8468; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8470 = _T_8469 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8480 = _T_4716 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8483 = _T_8001 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8484 = _T_8480 | _T_8483; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8485 = _T_8484 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8495 = _T_4717 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8498 = _T_8016 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8499 = _T_8495 | _T_8498; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8500 = _T_8499 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8510 = _T_4718 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8513 = _T_8031 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8514 = _T_8510 | _T_8513; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8515 = _T_8514 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8525 = _T_4719 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8528 = _T_8046 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8529 = _T_8525 | _T_8528; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8530 = _T_8529 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8540 = _T_4720 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8543 = _T_8061 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8544 = _T_8540 | _T_8543; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8545 = _T_8544 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8555 = _T_4721 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8558 = _T_8076 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8559 = _T_8555 | _T_8558; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8560 = _T_8559 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8570 = _T_4722 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8573 = _T_8091 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8574 = _T_8570 | _T_8573; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8575 = _T_8574 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8585 = _T_4723 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8588 = _T_8106 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8589 = _T_8585 | _T_8588; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8590 = _T_8589 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8600 = _T_4724 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8603 = _T_8121 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8604 = _T_8600 | _T_8603; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8605 = _T_8604 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8615 = _T_4725 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8618 = _T_8136 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8619 = _T_8615 | _T_8618; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8620 = _T_8619 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8630 = _T_4726 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8633 = _T_8151 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8634 = _T_8630 | _T_8633; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8635 = _T_8634 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8645 = _T_4727 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8648 = _T_8166 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8649 = _T_8645 | _T_8648; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8650 = _T_8649 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8660 = _T_4728 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8663 = _T_8181 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8664 = _T_8660 | _T_8663; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8665 = _T_8664 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8675 = _T_4729 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8678 = _T_8196 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8679 = _T_8675 | _T_8678; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8680 = _T_8679 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8690 = _T_4730 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8693 = _T_8211 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8694 = _T_8690 | _T_8693; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8695 = _T_8694 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8705 = _T_4731 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8708 = _T_8226 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8709 = _T_8705 | _T_8708; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8710 = _T_8709 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8720 = _T_4732 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8723 = _T_8241 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8724 = _T_8720 | _T_8723; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8725 = _T_8724 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8735 = _T_4733 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8738 = _T_8256 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8739 = _T_8735 | _T_8738; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8740 = _T_8739 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8750 = _T_4734 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8753 = _T_8271 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8754 = _T_8750 | _T_8753; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8755 = _T_8754 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8765 = _T_4735 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8768 = _T_8286 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8769 = _T_8765 | _T_8768; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8770 = _T_8769 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8780 = _T_4736 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8783 = _T_8301 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8784 = _T_8780 | _T_8783; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8785 = _T_8784 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8795 = _T_4737 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8798 = _T_8316 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8799 = _T_8795 | _T_8798; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8800 = _T_8799 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8810 = _T_4738 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8813 = _T_8331 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8814 = _T_8810 | _T_8813; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8815 = _T_8814 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8825 = _T_4739 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8828 = _T_8346 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8829 = _T_8825 | _T_8828; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8830 = _T_8829 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8840 = _T_4740 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8843 = _T_8361 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8844 = _T_8840 | _T_8843; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8845 = _T_8844 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8855 = _T_4741 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8858 = _T_8376 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8859 = _T_8855 | _T_8858; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8860 = _T_8859 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8870 = _T_4742 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8873 = _T_8391 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8874 = _T_8870 | _T_8873; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8875 = _T_8874 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8885 = _T_4743 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8888 = _T_8406 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8889 = _T_8885 | _T_8888; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8890 = _T_8889 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8900 = _T_4744 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8903 = _T_8421 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8904 = _T_8900 | _T_8903; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8905 = _T_8904 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8915 = _T_4745 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8918 = _T_8436 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8919 = _T_8915 | _T_8918; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8920 = _T_8919 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_8930 = _T_4746 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 762:59]
|
|
wire _T_8933 = _T_8451 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 762:124]
|
|
wire _T_8934 = _T_8930 | _T_8933; // @[el2_ifu_mem_ctl.scala 762:81]
|
|
wire _T_8935 = _T_8934 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 762:147]
|
|
wire _T_9737 = ~fetch_uncacheable_ff; // @[el2_ifu_mem_ctl.scala 817:63]
|
|
wire _T_9738 = _T_9737 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 817:85]
|
|
wire [1:0] _T_9740 = _T_9738 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
reg _T_9747; // @[el2_ifu_mem_ctl.scala 822:57]
|
|
reg _T_9748; // @[el2_ifu_mem_ctl.scala 823:56]
|
|
reg _T_9749; // @[el2_ifu_mem_ctl.scala 824:59]
|
|
wire _T_9750 = ~ifu_bus_arready_ff; // @[el2_ifu_mem_ctl.scala 825:80]
|
|
wire _T_9751 = ifu_bus_arvalid_ff & _T_9750; // @[el2_ifu_mem_ctl.scala 825:78]
|
|
reg _T_9753; // @[el2_ifu_mem_ctl.scala 825:58]
|
|
reg _T_9754; // @[el2_ifu_mem_ctl.scala 826:58]
|
|
wire _T_9757 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[el2_ifu_mem_ctl.scala 833:71]
|
|
wire _T_9759 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[el2_ifu_mem_ctl.scala 833:124]
|
|
wire _T_9761 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[el2_ifu_mem_ctl.scala 834:50]
|
|
wire _T_9763 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[el2_ifu_mem_ctl.scala 834:103]
|
|
wire [3:0] _T_9766 = {_T_9757,_T_9759,_T_9761,_T_9763}; // @[Cat.scala 29:58]
|
|
reg _T_9775; // @[Reg.scala 27:20]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en),
|
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en),
|
|
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_8_io_l1clk),
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en),
|
|
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_9_io_l1clk),
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en),
|
|
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_10_io_l1clk),
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en),
|
|
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_11_io_l1clk),
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en),
|
|
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_12_io_l1clk),
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en),
|
|
.io_scan_mode(rvclkhdr_12_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_13_io_l1clk),
|
|
.io_clk(rvclkhdr_13_io_clk),
|
|
.io_en(rvclkhdr_13_io_en),
|
|
.io_scan_mode(rvclkhdr_13_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_14_io_l1clk),
|
|
.io_clk(rvclkhdr_14_io_clk),
|
|
.io_en(rvclkhdr_14_io_en),
|
|
.io_scan_mode(rvclkhdr_14_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_15_io_l1clk),
|
|
.io_clk(rvclkhdr_15_io_clk),
|
|
.io_en(rvclkhdr_15_io_en),
|
|
.io_scan_mode(rvclkhdr_15_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_16_io_l1clk),
|
|
.io_clk(rvclkhdr_16_io_clk),
|
|
.io_en(rvclkhdr_16_io_en),
|
|
.io_scan_mode(rvclkhdr_16_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_17_io_l1clk),
|
|
.io_clk(rvclkhdr_17_io_clk),
|
|
.io_en(rvclkhdr_17_io_en),
|
|
.io_scan_mode(rvclkhdr_17_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_18_io_l1clk),
|
|
.io_clk(rvclkhdr_18_io_clk),
|
|
.io_en(rvclkhdr_18_io_en),
|
|
.io_scan_mode(rvclkhdr_18_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_19_io_l1clk),
|
|
.io_clk(rvclkhdr_19_io_clk),
|
|
.io_en(rvclkhdr_19_io_en),
|
|
.io_scan_mode(rvclkhdr_19_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_20_io_l1clk),
|
|
.io_clk(rvclkhdr_20_io_clk),
|
|
.io_en(rvclkhdr_20_io_en),
|
|
.io_scan_mode(rvclkhdr_20_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_21_io_l1clk),
|
|
.io_clk(rvclkhdr_21_io_clk),
|
|
.io_en(rvclkhdr_21_io_en),
|
|
.io_scan_mode(rvclkhdr_21_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_22_io_l1clk),
|
|
.io_clk(rvclkhdr_22_io_clk),
|
|
.io_en(rvclkhdr_22_io_en),
|
|
.io_scan_mode(rvclkhdr_22_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_23_io_l1clk),
|
|
.io_clk(rvclkhdr_23_io_clk),
|
|
.io_en(rvclkhdr_23_io_en),
|
|
.io_scan_mode(rvclkhdr_23_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_24_io_l1clk),
|
|
.io_clk(rvclkhdr_24_io_clk),
|
|
.io_en(rvclkhdr_24_io_en),
|
|
.io_scan_mode(rvclkhdr_24_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_25_io_l1clk),
|
|
.io_clk(rvclkhdr_25_io_clk),
|
|
.io_en(rvclkhdr_25_io_en),
|
|
.io_scan_mode(rvclkhdr_25_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_26_io_l1clk),
|
|
.io_clk(rvclkhdr_26_io_clk),
|
|
.io_en(rvclkhdr_26_io_en),
|
|
.io_scan_mode(rvclkhdr_26_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_27_io_l1clk),
|
|
.io_clk(rvclkhdr_27_io_clk),
|
|
.io_en(rvclkhdr_27_io_en),
|
|
.io_scan_mode(rvclkhdr_27_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_28_io_l1clk),
|
|
.io_clk(rvclkhdr_28_io_clk),
|
|
.io_en(rvclkhdr_28_io_en),
|
|
.io_scan_mode(rvclkhdr_28_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_29_io_l1clk),
|
|
.io_clk(rvclkhdr_29_io_clk),
|
|
.io_en(rvclkhdr_29_io_en),
|
|
.io_scan_mode(rvclkhdr_29_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_30_io_l1clk),
|
|
.io_clk(rvclkhdr_30_io_clk),
|
|
.io_en(rvclkhdr_30_io_en),
|
|
.io_scan_mode(rvclkhdr_30_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_31 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_31_io_l1clk),
|
|
.io_clk(rvclkhdr_31_io_clk),
|
|
.io_en(rvclkhdr_31_io_en),
|
|
.io_scan_mode(rvclkhdr_31_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_32 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_32_io_l1clk),
|
|
.io_clk(rvclkhdr_32_io_clk),
|
|
.io_en(rvclkhdr_32_io_en),
|
|
.io_scan_mode(rvclkhdr_32_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_33 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_33_io_l1clk),
|
|
.io_clk(rvclkhdr_33_io_clk),
|
|
.io_en(rvclkhdr_33_io_en),
|
|
.io_scan_mode(rvclkhdr_33_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_34 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_34_io_l1clk),
|
|
.io_clk(rvclkhdr_34_io_clk),
|
|
.io_en(rvclkhdr_34_io_en),
|
|
.io_scan_mode(rvclkhdr_34_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_35 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_35_io_l1clk),
|
|
.io_clk(rvclkhdr_35_io_clk),
|
|
.io_en(rvclkhdr_35_io_en),
|
|
.io_scan_mode(rvclkhdr_35_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_36 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_36_io_l1clk),
|
|
.io_clk(rvclkhdr_36_io_clk),
|
|
.io_en(rvclkhdr_36_io_en),
|
|
.io_scan_mode(rvclkhdr_36_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_37 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_37_io_l1clk),
|
|
.io_clk(rvclkhdr_37_io_clk),
|
|
.io_en(rvclkhdr_37_io_en),
|
|
.io_scan_mode(rvclkhdr_37_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_38 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_38_io_l1clk),
|
|
.io_clk(rvclkhdr_38_io_clk),
|
|
.io_en(rvclkhdr_38_io_en),
|
|
.io_scan_mode(rvclkhdr_38_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_39 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_39_io_l1clk),
|
|
.io_clk(rvclkhdr_39_io_clk),
|
|
.io_en(rvclkhdr_39_io_en),
|
|
.io_scan_mode(rvclkhdr_39_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_40 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_40_io_l1clk),
|
|
.io_clk(rvclkhdr_40_io_clk),
|
|
.io_en(rvclkhdr_40_io_en),
|
|
.io_scan_mode(rvclkhdr_40_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_41 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_41_io_l1clk),
|
|
.io_clk(rvclkhdr_41_io_clk),
|
|
.io_en(rvclkhdr_41_io_en),
|
|
.io_scan_mode(rvclkhdr_41_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_42 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_42_io_l1clk),
|
|
.io_clk(rvclkhdr_42_io_clk),
|
|
.io_en(rvclkhdr_42_io_en),
|
|
.io_scan_mode(rvclkhdr_42_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_43 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_43_io_l1clk),
|
|
.io_clk(rvclkhdr_43_io_clk),
|
|
.io_en(rvclkhdr_43_io_en),
|
|
.io_scan_mode(rvclkhdr_43_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_44 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_44_io_l1clk),
|
|
.io_clk(rvclkhdr_44_io_clk),
|
|
.io_en(rvclkhdr_44_io_en),
|
|
.io_scan_mode(rvclkhdr_44_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_45 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_45_io_l1clk),
|
|
.io_clk(rvclkhdr_45_io_clk),
|
|
.io_en(rvclkhdr_45_io_en),
|
|
.io_scan_mode(rvclkhdr_45_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_46 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_46_io_l1clk),
|
|
.io_clk(rvclkhdr_46_io_clk),
|
|
.io_en(rvclkhdr_46_io_en),
|
|
.io_scan_mode(rvclkhdr_46_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_47 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_47_io_l1clk),
|
|
.io_clk(rvclkhdr_47_io_clk),
|
|
.io_en(rvclkhdr_47_io_en),
|
|
.io_scan_mode(rvclkhdr_47_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_48 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_48_io_l1clk),
|
|
.io_clk(rvclkhdr_48_io_clk),
|
|
.io_en(rvclkhdr_48_io_en),
|
|
.io_scan_mode(rvclkhdr_48_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_49 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_49_io_l1clk),
|
|
.io_clk(rvclkhdr_49_io_clk),
|
|
.io_en(rvclkhdr_49_io_en),
|
|
.io_scan_mode(rvclkhdr_49_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_50 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_50_io_l1clk),
|
|
.io_clk(rvclkhdr_50_io_clk),
|
|
.io_en(rvclkhdr_50_io_en),
|
|
.io_scan_mode(rvclkhdr_50_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_51 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_51_io_l1clk),
|
|
.io_clk(rvclkhdr_51_io_clk),
|
|
.io_en(rvclkhdr_51_io_en),
|
|
.io_scan_mode(rvclkhdr_51_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_52 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_52_io_l1clk),
|
|
.io_clk(rvclkhdr_52_io_clk),
|
|
.io_en(rvclkhdr_52_io_en),
|
|
.io_scan_mode(rvclkhdr_52_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_53 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_53_io_l1clk),
|
|
.io_clk(rvclkhdr_53_io_clk),
|
|
.io_en(rvclkhdr_53_io_en),
|
|
.io_scan_mode(rvclkhdr_53_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_54 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_54_io_l1clk),
|
|
.io_clk(rvclkhdr_54_io_clk),
|
|
.io_en(rvclkhdr_54_io_en),
|
|
.io_scan_mode(rvclkhdr_54_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_55 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_55_io_l1clk),
|
|
.io_clk(rvclkhdr_55_io_clk),
|
|
.io_en(rvclkhdr_55_io_en),
|
|
.io_scan_mode(rvclkhdr_55_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_56 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_56_io_l1clk),
|
|
.io_clk(rvclkhdr_56_io_clk),
|
|
.io_en(rvclkhdr_56_io_en),
|
|
.io_scan_mode(rvclkhdr_56_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_57 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_57_io_l1clk),
|
|
.io_clk(rvclkhdr_57_io_clk),
|
|
.io_en(rvclkhdr_57_io_en),
|
|
.io_scan_mode(rvclkhdr_57_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_58 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_58_io_l1clk),
|
|
.io_clk(rvclkhdr_58_io_clk),
|
|
.io_en(rvclkhdr_58_io_en),
|
|
.io_scan_mode(rvclkhdr_58_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_59 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_59_io_l1clk),
|
|
.io_clk(rvclkhdr_59_io_clk),
|
|
.io_en(rvclkhdr_59_io_en),
|
|
.io_scan_mode(rvclkhdr_59_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_60 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_60_io_l1clk),
|
|
.io_clk(rvclkhdr_60_io_clk),
|
|
.io_en(rvclkhdr_60_io_en),
|
|
.io_scan_mode(rvclkhdr_60_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_61 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_61_io_l1clk),
|
|
.io_clk(rvclkhdr_61_io_clk),
|
|
.io_en(rvclkhdr_61_io_en),
|
|
.io_scan_mode(rvclkhdr_61_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_62 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_62_io_l1clk),
|
|
.io_clk(rvclkhdr_62_io_clk),
|
|
.io_en(rvclkhdr_62_io_en),
|
|
.io_scan_mode(rvclkhdr_62_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_63 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_63_io_l1clk),
|
|
.io_clk(rvclkhdr_63_io_clk),
|
|
.io_en(rvclkhdr_63_io_en),
|
|
.io_scan_mode(rvclkhdr_63_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_64 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_64_io_l1clk),
|
|
.io_clk(rvclkhdr_64_io_clk),
|
|
.io_en(rvclkhdr_64_io_en),
|
|
.io_scan_mode(rvclkhdr_64_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_65 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_65_io_l1clk),
|
|
.io_clk(rvclkhdr_65_io_clk),
|
|
.io_en(rvclkhdr_65_io_en),
|
|
.io_scan_mode(rvclkhdr_65_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_66 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_66_io_l1clk),
|
|
.io_clk(rvclkhdr_66_io_clk),
|
|
.io_en(rvclkhdr_66_io_en),
|
|
.io_scan_mode(rvclkhdr_66_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_67 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_67_io_l1clk),
|
|
.io_clk(rvclkhdr_67_io_clk),
|
|
.io_en(rvclkhdr_67_io_en),
|
|
.io_scan_mode(rvclkhdr_67_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_68 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_68_io_l1clk),
|
|
.io_clk(rvclkhdr_68_io_clk),
|
|
.io_en(rvclkhdr_68_io_en),
|
|
.io_scan_mode(rvclkhdr_68_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_69 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_69_io_l1clk),
|
|
.io_clk(rvclkhdr_69_io_clk),
|
|
.io_en(rvclkhdr_69_io_en),
|
|
.io_scan_mode(rvclkhdr_69_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_70 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_70_io_l1clk),
|
|
.io_clk(rvclkhdr_70_io_clk),
|
|
.io_en(rvclkhdr_70_io_en),
|
|
.io_scan_mode(rvclkhdr_70_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_71 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_71_io_l1clk),
|
|
.io_clk(rvclkhdr_71_io_clk),
|
|
.io_en(rvclkhdr_71_io_en),
|
|
.io_scan_mode(rvclkhdr_71_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_72 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_72_io_l1clk),
|
|
.io_clk(rvclkhdr_72_io_clk),
|
|
.io_en(rvclkhdr_72_io_en),
|
|
.io_scan_mode(rvclkhdr_72_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_73 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_73_io_l1clk),
|
|
.io_clk(rvclkhdr_73_io_clk),
|
|
.io_en(rvclkhdr_73_io_en),
|
|
.io_scan_mode(rvclkhdr_73_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_74 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_74_io_l1clk),
|
|
.io_clk(rvclkhdr_74_io_clk),
|
|
.io_en(rvclkhdr_74_io_en),
|
|
.io_scan_mode(rvclkhdr_74_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_75 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_75_io_l1clk),
|
|
.io_clk(rvclkhdr_75_io_clk),
|
|
.io_en(rvclkhdr_75_io_en),
|
|
.io_scan_mode(rvclkhdr_75_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_76 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_76_io_l1clk),
|
|
.io_clk(rvclkhdr_76_io_clk),
|
|
.io_en(rvclkhdr_76_io_en),
|
|
.io_scan_mode(rvclkhdr_76_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_77 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_77_io_l1clk),
|
|
.io_clk(rvclkhdr_77_io_clk),
|
|
.io_en(rvclkhdr_77_io_en),
|
|
.io_scan_mode(rvclkhdr_77_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_78 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_78_io_l1clk),
|
|
.io_clk(rvclkhdr_78_io_clk),
|
|
.io_en(rvclkhdr_78_io_en),
|
|
.io_scan_mode(rvclkhdr_78_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_79 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_79_io_l1clk),
|
|
.io_clk(rvclkhdr_79_io_clk),
|
|
.io_en(rvclkhdr_79_io_en),
|
|
.io_scan_mode(rvclkhdr_79_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_80 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_80_io_l1clk),
|
|
.io_clk(rvclkhdr_80_io_clk),
|
|
.io_en(rvclkhdr_80_io_en),
|
|
.io_scan_mode(rvclkhdr_80_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_81 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_81_io_l1clk),
|
|
.io_clk(rvclkhdr_81_io_clk),
|
|
.io_en(rvclkhdr_81_io_en),
|
|
.io_scan_mode(rvclkhdr_81_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_82 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_82_io_l1clk),
|
|
.io_clk(rvclkhdr_82_io_clk),
|
|
.io_en(rvclkhdr_82_io_en),
|
|
.io_scan_mode(rvclkhdr_82_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_83 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_83_io_l1clk),
|
|
.io_clk(rvclkhdr_83_io_clk),
|
|
.io_en(rvclkhdr_83_io_en),
|
|
.io_scan_mode(rvclkhdr_83_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_84 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_84_io_l1clk),
|
|
.io_clk(rvclkhdr_84_io_clk),
|
|
.io_en(rvclkhdr_84_io_en),
|
|
.io_scan_mode(rvclkhdr_84_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_85 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_85_io_l1clk),
|
|
.io_clk(rvclkhdr_85_io_clk),
|
|
.io_en(rvclkhdr_85_io_en),
|
|
.io_scan_mode(rvclkhdr_85_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_86 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_86_io_l1clk),
|
|
.io_clk(rvclkhdr_86_io_clk),
|
|
.io_en(rvclkhdr_86_io_en),
|
|
.io_scan_mode(rvclkhdr_86_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_87 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_87_io_l1clk),
|
|
.io_clk(rvclkhdr_87_io_clk),
|
|
.io_en(rvclkhdr_87_io_en),
|
|
.io_scan_mode(rvclkhdr_87_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_88 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_88_io_l1clk),
|
|
.io_clk(rvclkhdr_88_io_clk),
|
|
.io_en(rvclkhdr_88_io_en),
|
|
.io_scan_mode(rvclkhdr_88_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_89 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_89_io_l1clk),
|
|
.io_clk(rvclkhdr_89_io_clk),
|
|
.io_en(rvclkhdr_89_io_en),
|
|
.io_scan_mode(rvclkhdr_89_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_90 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_90_io_l1clk),
|
|
.io_clk(rvclkhdr_90_io_clk),
|
|
.io_en(rvclkhdr_90_io_en),
|
|
.io_scan_mode(rvclkhdr_90_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_91 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_91_io_l1clk),
|
|
.io_clk(rvclkhdr_91_io_clk),
|
|
.io_en(rvclkhdr_91_io_en),
|
|
.io_scan_mode(rvclkhdr_91_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_92 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_92_io_l1clk),
|
|
.io_clk(rvclkhdr_92_io_clk),
|
|
.io_en(rvclkhdr_92_io_en),
|
|
.io_scan_mode(rvclkhdr_92_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_93 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_93_io_l1clk),
|
|
.io_clk(rvclkhdr_93_io_clk),
|
|
.io_en(rvclkhdr_93_io_en),
|
|
.io_scan_mode(rvclkhdr_93_io_scan_mode)
|
|
);
|
|
assign io_ifu_miss_state_idle = miss_state == 3'h0; // @[el2_ifu_mem_ctl.scala 331:26]
|
|
assign io_ifu_ic_mb_empty = _T_328 | _T_231; // @[el2_ifu_mem_ctl.scala 330:22]
|
|
assign io_ic_dma_active = _T_11 | io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 194:20]
|
|
assign io_ic_write_stall = write_ic_16_bytes & _T_3936; // @[el2_ifu_mem_ctl.scala 705:21]
|
|
assign io_ifu_pmu_ic_miss = _T_9747; // @[el2_ifu_mem_ctl.scala 822:22]
|
|
assign io_ifu_pmu_ic_hit = _T_9748; // @[el2_ifu_mem_ctl.scala 823:21]
|
|
assign io_ifu_pmu_bus_error = _T_9749; // @[el2_ifu_mem_ctl.scala 824:24]
|
|
assign io_ifu_pmu_bus_busy = _T_9753; // @[el2_ifu_mem_ctl.scala 825:23]
|
|
assign io_ifu_pmu_bus_trxn = _T_9754; // @[el2_ifu_mem_ctl.scala 826:23]
|
|
assign io_ifu_axi_arvalid = ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 566:22]
|
|
assign io_ifu_axi_arid = bus_rd_addr_count & _T_2558; // @[el2_ifu_mem_ctl.scala 567:19]
|
|
assign io_ifu_axi_araddr = _T_2560 & _T_2562; // @[el2_ifu_mem_ctl.scala 568:21]
|
|
assign io_ifu_axi_arregion = ifu_ic_req_addr_f[28:25]; // @[el2_ifu_mem_ctl.scala 571:23]
|
|
assign io_ifu_axi_rready = 1'h1; // @[el2_ifu_mem_ctl.scala 573:21]
|
|
assign io_iccm_dma_ecc_error = |iccm_double_ecc_error; // @[el2_ifu_mem_ctl.scala 664:25]
|
|
assign io_iccm_dma_rvalid = iccm_dma_rvalid_temp; // @[el2_ifu_mem_ctl.scala 662:22]
|
|
assign io_iccm_dma_rdata = iccm_dma_rdata_temp; // @[el2_ifu_mem_ctl.scala 666:21]
|
|
assign io_iccm_dma_rtag = iccm_dma_rtag_temp; // @[el2_ifu_mem_ctl.scala 657:20]
|
|
assign io_iccm_ready = _T_2656 & _T_2650; // @[el2_ifu_mem_ctl.scala 636:17]
|
|
assign io_ic_rw_addr = _T_340 | _T_341; // @[el2_ifu_mem_ctl.scala 340:17]
|
|
assign io_ic_wr_en = bus_ic_wr_en & _T_3922; // @[el2_ifu_mem_ctl.scala 704:15]
|
|
assign io_ic_rd_en = _T_3914 | _T_3919; // @[el2_ifu_mem_ctl.scala 695:15]
|
|
assign io_ic_wr_data_0 = ic_wr_16bytes_data[70:0]; // @[el2_ifu_mem_ctl.scala 347:17]
|
|
assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[el2_ifu_mem_ctl.scala 347:17]
|
|
assign io_ic_debug_wr_data = io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu_mem_ctl.scala 348:23]
|
|
assign io_ifu_ic_debug_rd_data = _T_1211; // @[el2_ifu_mem_ctl.scala 356:27]
|
|
assign io_ic_debug_addr = io_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[el2_ifu_mem_ctl.scala 829:20]
|
|
assign io_ic_debug_rd_en = io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_ifu_mem_ctl.scala 831:21]
|
|
assign io_ic_debug_wr_en = io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_ifu_mem_ctl.scala 832:21]
|
|
assign io_ic_debug_tag_array = io_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[el2_ifu_mem_ctl.scala 830:25]
|
|
assign io_ic_debug_way = _T_9766[1:0]; // @[el2_ifu_mem_ctl.scala 833:19]
|
|
assign io_ic_tag_valid = ic_tag_valid_unq & _T_9740; // @[el2_ifu_mem_ctl.scala 817:19]
|
|
assign io_iccm_rw_addr = _T_3060 ? io_dma_mem_addr[15:1] : _T_3067; // @[el2_ifu_mem_ctl.scala 668:19]
|
|
assign io_iccm_wren = _T_2660 | iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 638:16]
|
|
assign io_iccm_rden = _T_2664 | _T_2665; // @[el2_ifu_mem_ctl.scala 639:16]
|
|
assign io_iccm_wr_data = _T_3042 ? _T_3043 : _T_3050; // @[el2_ifu_mem_ctl.scala 645:19]
|
|
assign io_iccm_wr_size = _T_2670 & io_dma_mem_sz; // @[el2_ifu_mem_ctl.scala 641:19]
|
|
assign io_ic_hit_f = _T_263 | _T_264; // @[el2_ifu_mem_ctl.scala 291:15]
|
|
assign io_ic_access_fault_f = _T_2443 & _T_319; // @[el2_ifu_mem_ctl.scala 388:24]
|
|
assign io_ic_access_fault_type_f = io_iccm_rd_ecc_double_err ? 2'h1 : _T_1273; // @[el2_ifu_mem_ctl.scala 389:29]
|
|
assign io_iccm_rd_ecc_single_err = _T_3859 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 681:29]
|
|
assign io_iccm_rd_ecc_double_err = iccm_dma_ecc_error_in & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 682:29]
|
|
assign io_ic_error_start = _T_1199 | ic_rd_parity_final_err; // @[el2_ifu_mem_ctl.scala 350:21]
|
|
assign io_ifu_async_error_start = io_iccm_rd_ecc_single_err | io_ic_error_start; // @[el2_ifu_mem_ctl.scala 193:28]
|
|
assign io_iccm_dma_sb_error = _T_3 & dma_iccm_req_f; // @[el2_ifu_mem_ctl.scala 192:24]
|
|
assign io_ic_fetch_val_f = {_T_1281,fetch_req_f_qual}; // @[el2_ifu_mem_ctl.scala 392:21]
|
|
assign io_ic_data_f = io_ic_rd_data[31:0]; // @[el2_ifu_mem_ctl.scala 385:16]
|
|
assign io_ic_premux_data = ic_premux_data_temp[63:0]; // @[el2_ifu_mem_ctl.scala 382:21]
|
|
assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[el2_ifu_mem_ctl.scala 383:25]
|
|
assign io_ifu_ic_debug_rd_data_valid = _T_9775; // @[el2_ifu_mem_ctl.scala 840:33]
|
|
assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2448; // @[el2_ifu_mem_ctl.scala 483:27]
|
|
assign io_iccm_correction_state = _T_2476 ? 1'h0 : _GEN_43; // @[el2_ifu_mem_ctl.scala 518:28 el2_ifu_mem_ctl.scala 531:32 el2_ifu_mem_ctl.scala 538:32 el2_ifu_mem_ctl.scala 545:32]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_io_en = ic_debug_rd_en_ff; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_1_io_en = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_2_io_en = _T_2 | scnd_miss_req; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_3_io_en = _T_309 | io_dec_tlu_force_halt; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_4_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_5_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_6_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_7_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_8_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_9_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_10_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_11_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_12_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_13_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_14_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_15_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_16_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_17_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_18_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_19_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_20_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_21_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_22_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_23_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_24_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_25_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_26_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_27_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_28_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_29_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_30_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_31_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_31_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_32_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_32_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_33_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_33_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_34_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_34_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_35_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_35_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_35_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_36_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_36_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_36_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_37_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_37_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_37_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_38_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_38_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_38_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_39_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_39_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_39_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_40_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_40_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_40_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_41_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_41_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_41_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_42_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_42_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_42_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_43_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_43_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_43_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_44_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_44_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_44_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_45_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_45_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_45_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_46_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_46_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_46_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_47_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_47_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_47_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_48_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_48_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_48_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_49_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_49_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_49_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_50_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_50_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_50_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_51_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_51_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_51_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_52_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_52_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_52_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_53_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_53_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_53_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_54_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_54_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_54_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_55_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_55_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_55_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_56_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_56_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_56_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_57_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_57_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_57_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_58_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_58_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_58_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_59_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_59_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_59_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_60_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_60_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_60_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_61_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_61_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_61_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_62_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_62_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_62_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_63_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_63_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_63_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_64_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_64_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_64_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_65_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_65_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_65_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_66_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_66_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_66_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_67_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_67_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_67_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_68_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_68_io_en = io_ifu_bus_clk_en; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_68_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_69_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_69_io_en = io_ifu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_69_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_70_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_70_io_en = ifu_status_wr_addr_ff[6:3] == 4'h0; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_70_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_71_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_71_io_en = ifu_status_wr_addr_ff[6:3] == 4'h1; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_71_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_72_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_72_io_en = ifu_status_wr_addr_ff[6:3] == 4'h2; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_72_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_73_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_73_io_en = ifu_status_wr_addr_ff[6:3] == 4'h3; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_73_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_74_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_74_io_en = ifu_status_wr_addr_ff[6:3] == 4'h4; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_74_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_75_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_75_io_en = ifu_status_wr_addr_ff[6:3] == 4'h5; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_75_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_76_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_76_io_en = ifu_status_wr_addr_ff[6:3] == 4'h6; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_76_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_77_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_77_io_en = ifu_status_wr_addr_ff[6:3] == 4'h7; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_77_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_78_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_78_io_en = ifu_status_wr_addr_ff[6:3] == 4'h8; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_78_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_79_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_79_io_en = ifu_status_wr_addr_ff[6:3] == 4'h9; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_79_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_80_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_80_io_en = ifu_status_wr_addr_ff[6:3] == 4'ha; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_80_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_81_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_81_io_en = ifu_status_wr_addr_ff[6:3] == 4'hb; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_81_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_82_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_82_io_en = ifu_status_wr_addr_ff[6:3] == 4'hc; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_82_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_83_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_83_io_en = ifu_status_wr_addr_ff[6:3] == 4'hd; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_83_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_84_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_84_io_en = ifu_status_wr_addr_ff[6:3] == 4'he; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_84_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_85_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_85_io_en = ifu_status_wr_addr_ff[6:3] == 4'hf; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_85_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_86_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_86_io_en = tag_valid_clken_0[0]; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_86_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_87_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_87_io_en = tag_valid_clken_0[1]; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_87_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_88_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_88_io_en = tag_valid_clken_1[0]; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_88_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_89_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_89_io_en = tag_valid_clken_1[1]; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_89_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_90_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_90_io_en = tag_valid_clken_2[0]; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_90_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_91_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_91_io_en = tag_valid_clken_2[1]; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_91_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_92_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_92_io_en = tag_valid_clken_3[0]; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_92_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_93_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_93_io_en = tag_valid_clken_3[1]; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_93_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
flush_final_f = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
ifc_fetch_req_f_raw = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
miss_state = _RAND_2[2:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
scnd_miss_req_q = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
ifu_fetch_addr_int_f = _RAND_4[30:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
ifc_iccm_access_f = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
iccm_dma_rvalid_in = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
dma_iccm_req_f = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
perr_state = _RAND_8[2:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
err_stop_state = _RAND_9[1:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
reset_all_tags = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
ifc_region_acc_fault_final_f = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
ifu_bus_rvalid_unq_ff = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
bus_ifu_bus_clk_en_ff = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
uncacheable_miss_ff = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
bus_data_beat_count = _RAND_15[2:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
ic_miss_buff_data_valid = _RAND_16[7:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
imb_ff = _RAND_17[30:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
last_data_recieved_ff = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
sel_mb_addr_ff = _RAND_19[0:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
way_status_mb_scnd_ff = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
ifu_ic_rw_int_addr_ff = _RAND_21[6:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
way_status_out_0 = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
way_status_out_1 = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
way_status_out_2 = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
way_status_out_3 = _RAND_25[0:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
way_status_out_4 = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
way_status_out_5 = _RAND_27[0:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
way_status_out_6 = _RAND_28[0:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
way_status_out_7 = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
way_status_out_8 = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
way_status_out_9 = _RAND_31[0:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
way_status_out_10 = _RAND_32[0:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
way_status_out_11 = _RAND_33[0:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
way_status_out_12 = _RAND_34[0:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
way_status_out_13 = _RAND_35[0:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
way_status_out_14 = _RAND_36[0:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
way_status_out_15 = _RAND_37[0:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
way_status_out_16 = _RAND_38[0:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
way_status_out_17 = _RAND_39[0:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
way_status_out_18 = _RAND_40[0:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
way_status_out_19 = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
way_status_out_20 = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
way_status_out_21 = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
way_status_out_22 = _RAND_44[0:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
way_status_out_23 = _RAND_45[0:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
way_status_out_24 = _RAND_46[0:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
way_status_out_25 = _RAND_47[0:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
way_status_out_26 = _RAND_48[0:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
way_status_out_27 = _RAND_49[0:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
way_status_out_28 = _RAND_50[0:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
way_status_out_29 = _RAND_51[0:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
way_status_out_30 = _RAND_52[0:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
way_status_out_31 = _RAND_53[0:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
way_status_out_32 = _RAND_54[0:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
way_status_out_33 = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
way_status_out_34 = _RAND_56[0:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
way_status_out_35 = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
way_status_out_36 = _RAND_58[0:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
way_status_out_37 = _RAND_59[0:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
way_status_out_38 = _RAND_60[0:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
way_status_out_39 = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
way_status_out_40 = _RAND_62[0:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
way_status_out_41 = _RAND_63[0:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
way_status_out_42 = _RAND_64[0:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
way_status_out_43 = _RAND_65[0:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
way_status_out_44 = _RAND_66[0:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
way_status_out_45 = _RAND_67[0:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
way_status_out_46 = _RAND_68[0:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
way_status_out_47 = _RAND_69[0:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
way_status_out_48 = _RAND_70[0:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
way_status_out_49 = _RAND_71[0:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
way_status_out_50 = _RAND_72[0:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
way_status_out_51 = _RAND_73[0:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
way_status_out_52 = _RAND_74[0:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
way_status_out_53 = _RAND_75[0:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
way_status_out_54 = _RAND_76[0:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
way_status_out_55 = _RAND_77[0:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
way_status_out_56 = _RAND_78[0:0];
|
|
_RAND_79 = {1{`RANDOM}};
|
|
way_status_out_57 = _RAND_79[0:0];
|
|
_RAND_80 = {1{`RANDOM}};
|
|
way_status_out_58 = _RAND_80[0:0];
|
|
_RAND_81 = {1{`RANDOM}};
|
|
way_status_out_59 = _RAND_81[0:0];
|
|
_RAND_82 = {1{`RANDOM}};
|
|
way_status_out_60 = _RAND_82[0:0];
|
|
_RAND_83 = {1{`RANDOM}};
|
|
way_status_out_61 = _RAND_83[0:0];
|
|
_RAND_84 = {1{`RANDOM}};
|
|
way_status_out_62 = _RAND_84[0:0];
|
|
_RAND_85 = {1{`RANDOM}};
|
|
way_status_out_63 = _RAND_85[0:0];
|
|
_RAND_86 = {1{`RANDOM}};
|
|
way_status_out_64 = _RAND_86[0:0];
|
|
_RAND_87 = {1{`RANDOM}};
|
|
way_status_out_65 = _RAND_87[0:0];
|
|
_RAND_88 = {1{`RANDOM}};
|
|
way_status_out_66 = _RAND_88[0:0];
|
|
_RAND_89 = {1{`RANDOM}};
|
|
way_status_out_67 = _RAND_89[0:0];
|
|
_RAND_90 = {1{`RANDOM}};
|
|
way_status_out_68 = _RAND_90[0:0];
|
|
_RAND_91 = {1{`RANDOM}};
|
|
way_status_out_69 = _RAND_91[0:0];
|
|
_RAND_92 = {1{`RANDOM}};
|
|
way_status_out_70 = _RAND_92[0:0];
|
|
_RAND_93 = {1{`RANDOM}};
|
|
way_status_out_71 = _RAND_93[0:0];
|
|
_RAND_94 = {1{`RANDOM}};
|
|
way_status_out_72 = _RAND_94[0:0];
|
|
_RAND_95 = {1{`RANDOM}};
|
|
way_status_out_73 = _RAND_95[0:0];
|
|
_RAND_96 = {1{`RANDOM}};
|
|
way_status_out_74 = _RAND_96[0:0];
|
|
_RAND_97 = {1{`RANDOM}};
|
|
way_status_out_75 = _RAND_97[0:0];
|
|
_RAND_98 = {1{`RANDOM}};
|
|
way_status_out_76 = _RAND_98[0:0];
|
|
_RAND_99 = {1{`RANDOM}};
|
|
way_status_out_77 = _RAND_99[0:0];
|
|
_RAND_100 = {1{`RANDOM}};
|
|
way_status_out_78 = _RAND_100[0:0];
|
|
_RAND_101 = {1{`RANDOM}};
|
|
way_status_out_79 = _RAND_101[0:0];
|
|
_RAND_102 = {1{`RANDOM}};
|
|
way_status_out_80 = _RAND_102[0:0];
|
|
_RAND_103 = {1{`RANDOM}};
|
|
way_status_out_81 = _RAND_103[0:0];
|
|
_RAND_104 = {1{`RANDOM}};
|
|
way_status_out_82 = _RAND_104[0:0];
|
|
_RAND_105 = {1{`RANDOM}};
|
|
way_status_out_83 = _RAND_105[0:0];
|
|
_RAND_106 = {1{`RANDOM}};
|
|
way_status_out_84 = _RAND_106[0:0];
|
|
_RAND_107 = {1{`RANDOM}};
|
|
way_status_out_85 = _RAND_107[0:0];
|
|
_RAND_108 = {1{`RANDOM}};
|
|
way_status_out_86 = _RAND_108[0:0];
|
|
_RAND_109 = {1{`RANDOM}};
|
|
way_status_out_87 = _RAND_109[0:0];
|
|
_RAND_110 = {1{`RANDOM}};
|
|
way_status_out_88 = _RAND_110[0:0];
|
|
_RAND_111 = {1{`RANDOM}};
|
|
way_status_out_89 = _RAND_111[0:0];
|
|
_RAND_112 = {1{`RANDOM}};
|
|
way_status_out_90 = _RAND_112[0:0];
|
|
_RAND_113 = {1{`RANDOM}};
|
|
way_status_out_91 = _RAND_113[0:0];
|
|
_RAND_114 = {1{`RANDOM}};
|
|
way_status_out_92 = _RAND_114[0:0];
|
|
_RAND_115 = {1{`RANDOM}};
|
|
way_status_out_93 = _RAND_115[0:0];
|
|
_RAND_116 = {1{`RANDOM}};
|
|
way_status_out_94 = _RAND_116[0:0];
|
|
_RAND_117 = {1{`RANDOM}};
|
|
way_status_out_95 = _RAND_117[0:0];
|
|
_RAND_118 = {1{`RANDOM}};
|
|
way_status_out_96 = _RAND_118[0:0];
|
|
_RAND_119 = {1{`RANDOM}};
|
|
way_status_out_97 = _RAND_119[0:0];
|
|
_RAND_120 = {1{`RANDOM}};
|
|
way_status_out_98 = _RAND_120[0:0];
|
|
_RAND_121 = {1{`RANDOM}};
|
|
way_status_out_99 = _RAND_121[0:0];
|
|
_RAND_122 = {1{`RANDOM}};
|
|
way_status_out_100 = _RAND_122[0:0];
|
|
_RAND_123 = {1{`RANDOM}};
|
|
way_status_out_101 = _RAND_123[0:0];
|
|
_RAND_124 = {1{`RANDOM}};
|
|
way_status_out_102 = _RAND_124[0:0];
|
|
_RAND_125 = {1{`RANDOM}};
|
|
way_status_out_103 = _RAND_125[0:0];
|
|
_RAND_126 = {1{`RANDOM}};
|
|
way_status_out_104 = _RAND_126[0:0];
|
|
_RAND_127 = {1{`RANDOM}};
|
|
way_status_out_105 = _RAND_127[0:0];
|
|
_RAND_128 = {1{`RANDOM}};
|
|
way_status_out_106 = _RAND_128[0:0];
|
|
_RAND_129 = {1{`RANDOM}};
|
|
way_status_out_107 = _RAND_129[0:0];
|
|
_RAND_130 = {1{`RANDOM}};
|
|
way_status_out_108 = _RAND_130[0:0];
|
|
_RAND_131 = {1{`RANDOM}};
|
|
way_status_out_109 = _RAND_131[0:0];
|
|
_RAND_132 = {1{`RANDOM}};
|
|
way_status_out_110 = _RAND_132[0:0];
|
|
_RAND_133 = {1{`RANDOM}};
|
|
way_status_out_111 = _RAND_133[0:0];
|
|
_RAND_134 = {1{`RANDOM}};
|
|
way_status_out_112 = _RAND_134[0:0];
|
|
_RAND_135 = {1{`RANDOM}};
|
|
way_status_out_113 = _RAND_135[0:0];
|
|
_RAND_136 = {1{`RANDOM}};
|
|
way_status_out_114 = _RAND_136[0:0];
|
|
_RAND_137 = {1{`RANDOM}};
|
|
way_status_out_115 = _RAND_137[0:0];
|
|
_RAND_138 = {1{`RANDOM}};
|
|
way_status_out_116 = _RAND_138[0:0];
|
|
_RAND_139 = {1{`RANDOM}};
|
|
way_status_out_117 = _RAND_139[0:0];
|
|
_RAND_140 = {1{`RANDOM}};
|
|
way_status_out_118 = _RAND_140[0:0];
|
|
_RAND_141 = {1{`RANDOM}};
|
|
way_status_out_119 = _RAND_141[0:0];
|
|
_RAND_142 = {1{`RANDOM}};
|
|
way_status_out_120 = _RAND_142[0:0];
|
|
_RAND_143 = {1{`RANDOM}};
|
|
way_status_out_121 = _RAND_143[0:0];
|
|
_RAND_144 = {1{`RANDOM}};
|
|
way_status_out_122 = _RAND_144[0:0];
|
|
_RAND_145 = {1{`RANDOM}};
|
|
way_status_out_123 = _RAND_145[0:0];
|
|
_RAND_146 = {1{`RANDOM}};
|
|
way_status_out_124 = _RAND_146[0:0];
|
|
_RAND_147 = {1{`RANDOM}};
|
|
way_status_out_125 = _RAND_147[0:0];
|
|
_RAND_148 = {1{`RANDOM}};
|
|
way_status_out_126 = _RAND_148[0:0];
|
|
_RAND_149 = {1{`RANDOM}};
|
|
way_status_out_127 = _RAND_149[0:0];
|
|
_RAND_150 = {1{`RANDOM}};
|
|
tagv_mb_scnd_ff = _RAND_150[1:0];
|
|
_RAND_151 = {1{`RANDOM}};
|
|
uncacheable_miss_scnd_ff = _RAND_151[0:0];
|
|
_RAND_152 = {1{`RANDOM}};
|
|
imb_scnd_ff = _RAND_152[30:0];
|
|
_RAND_153 = {1{`RANDOM}};
|
|
ifu_bus_rid_ff = _RAND_153[2:0];
|
|
_RAND_154 = {1{`RANDOM}};
|
|
ifu_bus_rresp_ff = _RAND_154[1:0];
|
|
_RAND_155 = {1{`RANDOM}};
|
|
ifu_wr_data_comb_err_ff = _RAND_155[0:0];
|
|
_RAND_156 = {1{`RANDOM}};
|
|
way_status_mb_ff = _RAND_156[0:0];
|
|
_RAND_157 = {1{`RANDOM}};
|
|
tagv_mb_ff = _RAND_157[1:0];
|
|
_RAND_158 = {1{`RANDOM}};
|
|
reset_ic_ff = _RAND_158[0:0];
|
|
_RAND_159 = {1{`RANDOM}};
|
|
fetch_uncacheable_ff = _RAND_159[0:0];
|
|
_RAND_160 = {1{`RANDOM}};
|
|
miss_addr = _RAND_160[25:0];
|
|
_RAND_161 = {1{`RANDOM}};
|
|
ifc_region_acc_fault_f = _RAND_161[0:0];
|
|
_RAND_162 = {1{`RANDOM}};
|
|
bus_rd_addr_count = _RAND_162[2:0];
|
|
_RAND_163 = {1{`RANDOM}};
|
|
ic_act_miss_f_delayed = _RAND_163[0:0];
|
|
_RAND_164 = {2{`RANDOM}};
|
|
ifu_bus_rdata_ff = _RAND_164[63:0];
|
|
_RAND_165 = {1{`RANDOM}};
|
|
ic_miss_buff_data_0 = _RAND_165[31:0];
|
|
_RAND_166 = {1{`RANDOM}};
|
|
ic_miss_buff_data_1 = _RAND_166[31:0];
|
|
_RAND_167 = {1{`RANDOM}};
|
|
ic_miss_buff_data_2 = _RAND_167[31:0];
|
|
_RAND_168 = {1{`RANDOM}};
|
|
ic_miss_buff_data_3 = _RAND_168[31:0];
|
|
_RAND_169 = {1{`RANDOM}};
|
|
ic_miss_buff_data_4 = _RAND_169[31:0];
|
|
_RAND_170 = {1{`RANDOM}};
|
|
ic_miss_buff_data_5 = _RAND_170[31:0];
|
|
_RAND_171 = {1{`RANDOM}};
|
|
ic_miss_buff_data_6 = _RAND_171[31:0];
|
|
_RAND_172 = {1{`RANDOM}};
|
|
ic_miss_buff_data_7 = _RAND_172[31:0];
|
|
_RAND_173 = {1{`RANDOM}};
|
|
ic_miss_buff_data_8 = _RAND_173[31:0];
|
|
_RAND_174 = {1{`RANDOM}};
|
|
ic_miss_buff_data_9 = _RAND_174[31:0];
|
|
_RAND_175 = {1{`RANDOM}};
|
|
ic_miss_buff_data_10 = _RAND_175[31:0];
|
|
_RAND_176 = {1{`RANDOM}};
|
|
ic_miss_buff_data_11 = _RAND_176[31:0];
|
|
_RAND_177 = {1{`RANDOM}};
|
|
ic_miss_buff_data_12 = _RAND_177[31:0];
|
|
_RAND_178 = {1{`RANDOM}};
|
|
ic_miss_buff_data_13 = _RAND_178[31:0];
|
|
_RAND_179 = {1{`RANDOM}};
|
|
ic_miss_buff_data_14 = _RAND_179[31:0];
|
|
_RAND_180 = {1{`RANDOM}};
|
|
ic_miss_buff_data_15 = _RAND_180[31:0];
|
|
_RAND_181 = {1{`RANDOM}};
|
|
ic_crit_wd_rdy_new_ff = _RAND_181[0:0];
|
|
_RAND_182 = {1{`RANDOM}};
|
|
ic_miss_buff_data_error = _RAND_182[7:0];
|
|
_RAND_183 = {1{`RANDOM}};
|
|
ic_debug_ict_array_sel_ff = _RAND_183[0:0];
|
|
_RAND_184 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_0 = _RAND_184[0:0];
|
|
_RAND_185 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_1 = _RAND_185[0:0];
|
|
_RAND_186 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_2 = _RAND_186[0:0];
|
|
_RAND_187 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_3 = _RAND_187[0:0];
|
|
_RAND_188 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_4 = _RAND_188[0:0];
|
|
_RAND_189 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_5 = _RAND_189[0:0];
|
|
_RAND_190 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_6 = _RAND_190[0:0];
|
|
_RAND_191 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_7 = _RAND_191[0:0];
|
|
_RAND_192 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_8 = _RAND_192[0:0];
|
|
_RAND_193 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_9 = _RAND_193[0:0];
|
|
_RAND_194 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_10 = _RAND_194[0:0];
|
|
_RAND_195 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_11 = _RAND_195[0:0];
|
|
_RAND_196 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_12 = _RAND_196[0:0];
|
|
_RAND_197 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_13 = _RAND_197[0:0];
|
|
_RAND_198 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_14 = _RAND_198[0:0];
|
|
_RAND_199 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_15 = _RAND_199[0:0];
|
|
_RAND_200 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_16 = _RAND_200[0:0];
|
|
_RAND_201 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_17 = _RAND_201[0:0];
|
|
_RAND_202 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_18 = _RAND_202[0:0];
|
|
_RAND_203 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_19 = _RAND_203[0:0];
|
|
_RAND_204 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_20 = _RAND_204[0:0];
|
|
_RAND_205 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_21 = _RAND_205[0:0];
|
|
_RAND_206 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_22 = _RAND_206[0:0];
|
|
_RAND_207 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_23 = _RAND_207[0:0];
|
|
_RAND_208 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_24 = _RAND_208[0:0];
|
|
_RAND_209 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_25 = _RAND_209[0:0];
|
|
_RAND_210 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_26 = _RAND_210[0:0];
|
|
_RAND_211 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_27 = _RAND_211[0:0];
|
|
_RAND_212 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_28 = _RAND_212[0:0];
|
|
_RAND_213 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_29 = _RAND_213[0:0];
|
|
_RAND_214 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_30 = _RAND_214[0:0];
|
|
_RAND_215 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_31 = _RAND_215[0:0];
|
|
_RAND_216 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_32 = _RAND_216[0:0];
|
|
_RAND_217 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_33 = _RAND_217[0:0];
|
|
_RAND_218 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_34 = _RAND_218[0:0];
|
|
_RAND_219 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_35 = _RAND_219[0:0];
|
|
_RAND_220 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_36 = _RAND_220[0:0];
|
|
_RAND_221 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_37 = _RAND_221[0:0];
|
|
_RAND_222 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_38 = _RAND_222[0:0];
|
|
_RAND_223 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_39 = _RAND_223[0:0];
|
|
_RAND_224 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_40 = _RAND_224[0:0];
|
|
_RAND_225 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_41 = _RAND_225[0:0];
|
|
_RAND_226 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_42 = _RAND_226[0:0];
|
|
_RAND_227 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_43 = _RAND_227[0:0];
|
|
_RAND_228 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_44 = _RAND_228[0:0];
|
|
_RAND_229 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_45 = _RAND_229[0:0];
|
|
_RAND_230 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_46 = _RAND_230[0:0];
|
|
_RAND_231 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_47 = _RAND_231[0:0];
|
|
_RAND_232 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_48 = _RAND_232[0:0];
|
|
_RAND_233 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_49 = _RAND_233[0:0];
|
|
_RAND_234 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_50 = _RAND_234[0:0];
|
|
_RAND_235 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_51 = _RAND_235[0:0];
|
|
_RAND_236 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_52 = _RAND_236[0:0];
|
|
_RAND_237 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_53 = _RAND_237[0:0];
|
|
_RAND_238 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_54 = _RAND_238[0:0];
|
|
_RAND_239 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_55 = _RAND_239[0:0];
|
|
_RAND_240 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_56 = _RAND_240[0:0];
|
|
_RAND_241 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_57 = _RAND_241[0:0];
|
|
_RAND_242 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_58 = _RAND_242[0:0];
|
|
_RAND_243 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_59 = _RAND_243[0:0];
|
|
_RAND_244 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_60 = _RAND_244[0:0];
|
|
_RAND_245 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_61 = _RAND_245[0:0];
|
|
_RAND_246 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_62 = _RAND_246[0:0];
|
|
_RAND_247 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_63 = _RAND_247[0:0];
|
|
_RAND_248 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_64 = _RAND_248[0:0];
|
|
_RAND_249 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_65 = _RAND_249[0:0];
|
|
_RAND_250 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_66 = _RAND_250[0:0];
|
|
_RAND_251 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_67 = _RAND_251[0:0];
|
|
_RAND_252 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_68 = _RAND_252[0:0];
|
|
_RAND_253 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_69 = _RAND_253[0:0];
|
|
_RAND_254 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_70 = _RAND_254[0:0];
|
|
_RAND_255 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_71 = _RAND_255[0:0];
|
|
_RAND_256 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_72 = _RAND_256[0:0];
|
|
_RAND_257 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_73 = _RAND_257[0:0];
|
|
_RAND_258 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_74 = _RAND_258[0:0];
|
|
_RAND_259 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_75 = _RAND_259[0:0];
|
|
_RAND_260 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_76 = _RAND_260[0:0];
|
|
_RAND_261 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_77 = _RAND_261[0:0];
|
|
_RAND_262 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_78 = _RAND_262[0:0];
|
|
_RAND_263 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_79 = _RAND_263[0:0];
|
|
_RAND_264 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_80 = _RAND_264[0:0];
|
|
_RAND_265 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_81 = _RAND_265[0:0];
|
|
_RAND_266 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_82 = _RAND_266[0:0];
|
|
_RAND_267 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_83 = _RAND_267[0:0];
|
|
_RAND_268 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_84 = _RAND_268[0:0];
|
|
_RAND_269 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_85 = _RAND_269[0:0];
|
|
_RAND_270 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_86 = _RAND_270[0:0];
|
|
_RAND_271 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_87 = _RAND_271[0:0];
|
|
_RAND_272 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_88 = _RAND_272[0:0];
|
|
_RAND_273 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_89 = _RAND_273[0:0];
|
|
_RAND_274 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_90 = _RAND_274[0:0];
|
|
_RAND_275 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_91 = _RAND_275[0:0];
|
|
_RAND_276 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_92 = _RAND_276[0:0];
|
|
_RAND_277 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_93 = _RAND_277[0:0];
|
|
_RAND_278 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_94 = _RAND_278[0:0];
|
|
_RAND_279 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_95 = _RAND_279[0:0];
|
|
_RAND_280 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_96 = _RAND_280[0:0];
|
|
_RAND_281 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_97 = _RAND_281[0:0];
|
|
_RAND_282 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_98 = _RAND_282[0:0];
|
|
_RAND_283 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_99 = _RAND_283[0:0];
|
|
_RAND_284 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_100 = _RAND_284[0:0];
|
|
_RAND_285 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_101 = _RAND_285[0:0];
|
|
_RAND_286 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_102 = _RAND_286[0:0];
|
|
_RAND_287 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_103 = _RAND_287[0:0];
|
|
_RAND_288 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_104 = _RAND_288[0:0];
|
|
_RAND_289 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_105 = _RAND_289[0:0];
|
|
_RAND_290 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_106 = _RAND_290[0:0];
|
|
_RAND_291 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_107 = _RAND_291[0:0];
|
|
_RAND_292 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_108 = _RAND_292[0:0];
|
|
_RAND_293 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_109 = _RAND_293[0:0];
|
|
_RAND_294 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_110 = _RAND_294[0:0];
|
|
_RAND_295 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_111 = _RAND_295[0:0];
|
|
_RAND_296 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_112 = _RAND_296[0:0];
|
|
_RAND_297 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_113 = _RAND_297[0:0];
|
|
_RAND_298 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_114 = _RAND_298[0:0];
|
|
_RAND_299 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_115 = _RAND_299[0:0];
|
|
_RAND_300 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_116 = _RAND_300[0:0];
|
|
_RAND_301 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_117 = _RAND_301[0:0];
|
|
_RAND_302 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_118 = _RAND_302[0:0];
|
|
_RAND_303 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_119 = _RAND_303[0:0];
|
|
_RAND_304 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_120 = _RAND_304[0:0];
|
|
_RAND_305 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_121 = _RAND_305[0:0];
|
|
_RAND_306 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_122 = _RAND_306[0:0];
|
|
_RAND_307 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_123 = _RAND_307[0:0];
|
|
_RAND_308 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_124 = _RAND_308[0:0];
|
|
_RAND_309 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_125 = _RAND_309[0:0];
|
|
_RAND_310 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_126 = _RAND_310[0:0];
|
|
_RAND_311 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_127 = _RAND_311[0:0];
|
|
_RAND_312 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_0 = _RAND_312[0:0];
|
|
_RAND_313 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_1 = _RAND_313[0:0];
|
|
_RAND_314 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_2 = _RAND_314[0:0];
|
|
_RAND_315 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_3 = _RAND_315[0:0];
|
|
_RAND_316 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_4 = _RAND_316[0:0];
|
|
_RAND_317 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_5 = _RAND_317[0:0];
|
|
_RAND_318 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_6 = _RAND_318[0:0];
|
|
_RAND_319 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_7 = _RAND_319[0:0];
|
|
_RAND_320 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_8 = _RAND_320[0:0];
|
|
_RAND_321 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_9 = _RAND_321[0:0];
|
|
_RAND_322 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_10 = _RAND_322[0:0];
|
|
_RAND_323 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_11 = _RAND_323[0:0];
|
|
_RAND_324 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_12 = _RAND_324[0:0];
|
|
_RAND_325 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_13 = _RAND_325[0:0];
|
|
_RAND_326 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_14 = _RAND_326[0:0];
|
|
_RAND_327 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_15 = _RAND_327[0:0];
|
|
_RAND_328 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_16 = _RAND_328[0:0];
|
|
_RAND_329 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_17 = _RAND_329[0:0];
|
|
_RAND_330 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_18 = _RAND_330[0:0];
|
|
_RAND_331 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_19 = _RAND_331[0:0];
|
|
_RAND_332 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_20 = _RAND_332[0:0];
|
|
_RAND_333 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_21 = _RAND_333[0:0];
|
|
_RAND_334 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_22 = _RAND_334[0:0];
|
|
_RAND_335 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_23 = _RAND_335[0:0];
|
|
_RAND_336 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_24 = _RAND_336[0:0];
|
|
_RAND_337 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_25 = _RAND_337[0:0];
|
|
_RAND_338 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_26 = _RAND_338[0:0];
|
|
_RAND_339 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_27 = _RAND_339[0:0];
|
|
_RAND_340 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_28 = _RAND_340[0:0];
|
|
_RAND_341 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_29 = _RAND_341[0:0];
|
|
_RAND_342 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_30 = _RAND_342[0:0];
|
|
_RAND_343 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_31 = _RAND_343[0:0];
|
|
_RAND_344 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_32 = _RAND_344[0:0];
|
|
_RAND_345 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_33 = _RAND_345[0:0];
|
|
_RAND_346 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_34 = _RAND_346[0:0];
|
|
_RAND_347 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_35 = _RAND_347[0:0];
|
|
_RAND_348 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_36 = _RAND_348[0:0];
|
|
_RAND_349 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_37 = _RAND_349[0:0];
|
|
_RAND_350 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_38 = _RAND_350[0:0];
|
|
_RAND_351 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_39 = _RAND_351[0:0];
|
|
_RAND_352 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_40 = _RAND_352[0:0];
|
|
_RAND_353 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_41 = _RAND_353[0:0];
|
|
_RAND_354 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_42 = _RAND_354[0:0];
|
|
_RAND_355 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_43 = _RAND_355[0:0];
|
|
_RAND_356 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_44 = _RAND_356[0:0];
|
|
_RAND_357 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_45 = _RAND_357[0:0];
|
|
_RAND_358 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_46 = _RAND_358[0:0];
|
|
_RAND_359 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_47 = _RAND_359[0:0];
|
|
_RAND_360 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_48 = _RAND_360[0:0];
|
|
_RAND_361 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_49 = _RAND_361[0:0];
|
|
_RAND_362 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_50 = _RAND_362[0:0];
|
|
_RAND_363 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_51 = _RAND_363[0:0];
|
|
_RAND_364 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_52 = _RAND_364[0:0];
|
|
_RAND_365 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_53 = _RAND_365[0:0];
|
|
_RAND_366 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_54 = _RAND_366[0:0];
|
|
_RAND_367 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_55 = _RAND_367[0:0];
|
|
_RAND_368 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_56 = _RAND_368[0:0];
|
|
_RAND_369 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_57 = _RAND_369[0:0];
|
|
_RAND_370 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_58 = _RAND_370[0:0];
|
|
_RAND_371 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_59 = _RAND_371[0:0];
|
|
_RAND_372 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_60 = _RAND_372[0:0];
|
|
_RAND_373 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_61 = _RAND_373[0:0];
|
|
_RAND_374 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_62 = _RAND_374[0:0];
|
|
_RAND_375 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_63 = _RAND_375[0:0];
|
|
_RAND_376 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_64 = _RAND_376[0:0];
|
|
_RAND_377 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_65 = _RAND_377[0:0];
|
|
_RAND_378 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_66 = _RAND_378[0:0];
|
|
_RAND_379 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_67 = _RAND_379[0:0];
|
|
_RAND_380 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_68 = _RAND_380[0:0];
|
|
_RAND_381 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_69 = _RAND_381[0:0];
|
|
_RAND_382 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_70 = _RAND_382[0:0];
|
|
_RAND_383 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_71 = _RAND_383[0:0];
|
|
_RAND_384 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_72 = _RAND_384[0:0];
|
|
_RAND_385 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_73 = _RAND_385[0:0];
|
|
_RAND_386 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_74 = _RAND_386[0:0];
|
|
_RAND_387 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_75 = _RAND_387[0:0];
|
|
_RAND_388 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_76 = _RAND_388[0:0];
|
|
_RAND_389 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_77 = _RAND_389[0:0];
|
|
_RAND_390 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_78 = _RAND_390[0:0];
|
|
_RAND_391 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_79 = _RAND_391[0:0];
|
|
_RAND_392 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_80 = _RAND_392[0:0];
|
|
_RAND_393 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_81 = _RAND_393[0:0];
|
|
_RAND_394 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_82 = _RAND_394[0:0];
|
|
_RAND_395 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_83 = _RAND_395[0:0];
|
|
_RAND_396 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_84 = _RAND_396[0:0];
|
|
_RAND_397 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_85 = _RAND_397[0:0];
|
|
_RAND_398 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_86 = _RAND_398[0:0];
|
|
_RAND_399 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_87 = _RAND_399[0:0];
|
|
_RAND_400 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_88 = _RAND_400[0:0];
|
|
_RAND_401 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_89 = _RAND_401[0:0];
|
|
_RAND_402 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_90 = _RAND_402[0:0];
|
|
_RAND_403 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_91 = _RAND_403[0:0];
|
|
_RAND_404 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_92 = _RAND_404[0:0];
|
|
_RAND_405 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_93 = _RAND_405[0:0];
|
|
_RAND_406 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_94 = _RAND_406[0:0];
|
|
_RAND_407 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_95 = _RAND_407[0:0];
|
|
_RAND_408 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_96 = _RAND_408[0:0];
|
|
_RAND_409 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_97 = _RAND_409[0:0];
|
|
_RAND_410 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_98 = _RAND_410[0:0];
|
|
_RAND_411 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_99 = _RAND_411[0:0];
|
|
_RAND_412 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_100 = _RAND_412[0:0];
|
|
_RAND_413 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_101 = _RAND_413[0:0];
|
|
_RAND_414 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_102 = _RAND_414[0:0];
|
|
_RAND_415 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_103 = _RAND_415[0:0];
|
|
_RAND_416 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_104 = _RAND_416[0:0];
|
|
_RAND_417 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_105 = _RAND_417[0:0];
|
|
_RAND_418 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_106 = _RAND_418[0:0];
|
|
_RAND_419 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_107 = _RAND_419[0:0];
|
|
_RAND_420 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_108 = _RAND_420[0:0];
|
|
_RAND_421 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_109 = _RAND_421[0:0];
|
|
_RAND_422 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_110 = _RAND_422[0:0];
|
|
_RAND_423 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_111 = _RAND_423[0:0];
|
|
_RAND_424 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_112 = _RAND_424[0:0];
|
|
_RAND_425 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_113 = _RAND_425[0:0];
|
|
_RAND_426 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_114 = _RAND_426[0:0];
|
|
_RAND_427 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_115 = _RAND_427[0:0];
|
|
_RAND_428 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_116 = _RAND_428[0:0];
|
|
_RAND_429 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_117 = _RAND_429[0:0];
|
|
_RAND_430 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_118 = _RAND_430[0:0];
|
|
_RAND_431 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_119 = _RAND_431[0:0];
|
|
_RAND_432 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_120 = _RAND_432[0:0];
|
|
_RAND_433 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_121 = _RAND_433[0:0];
|
|
_RAND_434 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_122 = _RAND_434[0:0];
|
|
_RAND_435 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_123 = _RAND_435[0:0];
|
|
_RAND_436 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_124 = _RAND_436[0:0];
|
|
_RAND_437 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_125 = _RAND_437[0:0];
|
|
_RAND_438 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_126 = _RAND_438[0:0];
|
|
_RAND_439 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_127 = _RAND_439[0:0];
|
|
_RAND_440 = {1{`RANDOM}};
|
|
ic_debug_way_ff = _RAND_440[1:0];
|
|
_RAND_441 = {1{`RANDOM}};
|
|
ic_debug_rd_en_ff = _RAND_441[0:0];
|
|
_RAND_442 = {3{`RANDOM}};
|
|
_T_1211 = _RAND_442[70:0];
|
|
_RAND_443 = {1{`RANDOM}};
|
|
perr_ic_index_ff = _RAND_443[6:0];
|
|
_RAND_444 = {1{`RANDOM}};
|
|
dma_sb_err_state_ff = _RAND_444[0:0];
|
|
_RAND_445 = {1{`RANDOM}};
|
|
ifu_bus_cmd_valid = _RAND_445[0:0];
|
|
_RAND_446 = {1{`RANDOM}};
|
|
bus_cmd_beat_count = _RAND_446[2:0];
|
|
_RAND_447 = {1{`RANDOM}};
|
|
ifu_bus_arready_unq_ff = _RAND_447[0:0];
|
|
_RAND_448 = {1{`RANDOM}};
|
|
ifu_bus_arvalid_ff = _RAND_448[0:0];
|
|
_RAND_449 = {1{`RANDOM}};
|
|
ifc_dma_access_ok_prev = _RAND_449[0:0];
|
|
_RAND_450 = {2{`RANDOM}};
|
|
iccm_ecc_corr_data_ff = _RAND_450[38:0];
|
|
_RAND_451 = {1{`RANDOM}};
|
|
dma_mem_addr_ff = _RAND_451[1:0];
|
|
_RAND_452 = {1{`RANDOM}};
|
|
dma_mem_tag_ff = _RAND_452[2:0];
|
|
_RAND_453 = {1{`RANDOM}};
|
|
iccm_dma_rtag_temp = _RAND_453[2:0];
|
|
_RAND_454 = {1{`RANDOM}};
|
|
iccm_dma_rvalid_temp = _RAND_454[0:0];
|
|
_RAND_455 = {2{`RANDOM}};
|
|
iccm_dma_rdata_temp = _RAND_455[63:0];
|
|
_RAND_456 = {1{`RANDOM}};
|
|
iccm_ecc_corr_index_ff = _RAND_456[13:0];
|
|
_RAND_457 = {1{`RANDOM}};
|
|
iccm_rd_ecc_single_err_ff = _RAND_457[0:0];
|
|
_RAND_458 = {1{`RANDOM}};
|
|
iccm_rw_addr_f = _RAND_458[13:0];
|
|
_RAND_459 = {1{`RANDOM}};
|
|
ifu_status_wr_addr_ff = _RAND_459[6:0];
|
|
_RAND_460 = {1{`RANDOM}};
|
|
way_status_wr_en_ff = _RAND_460[0:0];
|
|
_RAND_461 = {1{`RANDOM}};
|
|
way_status_new_ff = _RAND_461[0:0];
|
|
_RAND_462 = {1{`RANDOM}};
|
|
ifu_tag_wren_ff = _RAND_462[1:0];
|
|
_RAND_463 = {1{`RANDOM}};
|
|
ic_valid_ff = _RAND_463[0:0];
|
|
_RAND_464 = {1{`RANDOM}};
|
|
_T_9747 = _RAND_464[0:0];
|
|
_RAND_465 = {1{`RANDOM}};
|
|
_T_9748 = _RAND_465[0:0];
|
|
_RAND_466 = {1{`RANDOM}};
|
|
_T_9749 = _RAND_466[0:0];
|
|
_RAND_467 = {1{`RANDOM}};
|
|
_T_9753 = _RAND_467[0:0];
|
|
_RAND_468 = {1{`RANDOM}};
|
|
_T_9754 = _RAND_468[0:0];
|
|
_RAND_469 = {1{`RANDOM}};
|
|
_T_9775 = _RAND_469[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
flush_final_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_fetch_req_f_raw = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
miss_state = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
scnd_miss_req_q = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_fetch_addr_int_f = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_iccm_access_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_dma_rvalid_in = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_iccm_req_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
perr_state = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
err_stop_state = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
reset_all_tags = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_region_acc_fault_final_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_rvalid_unq_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
bus_ifu_bus_clk_en_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
uncacheable_miss_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
bus_data_beat_count = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_valid = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
last_data_recieved_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
sel_mb_addr_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_mb_scnd_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_ic_rw_int_addr_ff = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_5 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_6 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_7 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_8 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_9 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_10 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_11 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_13 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_14 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_15 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_16 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_17 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_18 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_19 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_20 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_21 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_22 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_23 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_24 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_25 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_26 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_27 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_28 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_29 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_30 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_31 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_32 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_33 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_34 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_35 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_36 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_37 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_38 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_39 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_40 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_41 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_42 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_43 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_44 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_45 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_46 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_47 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_48 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_49 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_50 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_51 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_52 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_53 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_54 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_55 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_56 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_57 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_58 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_59 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_60 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_61 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_62 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_63 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_64 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_65 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_66 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_67 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_68 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_69 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_70 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_71 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_72 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_73 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_74 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_75 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_76 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_77 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_78 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_79 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_80 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_81 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_82 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_83 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_84 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_85 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_86 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_87 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_88 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_89 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_90 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_91 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_92 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_93 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_94 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_95 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_96 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_97 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_98 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_99 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_100 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_101 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_102 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_103 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_104 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_105 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_106 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_107 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_108 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_109 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_110 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_111 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_112 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_113 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_114 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_115 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_116 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_117 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_118 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_119 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_120 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_121 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_122 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_123 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_124 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_125 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_126 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_127 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
tagv_mb_scnd_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
uncacheable_miss_scnd_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
imb_scnd_ff = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_rid_ff = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_rresp_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_wr_data_comb_err_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_mb_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
tagv_mb_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fetch_uncacheable_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
miss_addr = 26'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_region_acc_fault_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
bus_rd_addr_count = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_act_miss_f_delayed = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_rdata_ff = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_4 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_5 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_6 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_7 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_8 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_9 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_10 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_11 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_12 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_13 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_14 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_15 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_crit_wd_rdy_new_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_error = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_debug_ict_array_sel_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_5 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_6 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_7 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_8 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_9 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_10 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_11 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_13 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_14 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_15 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_16 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_17 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_18 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_19 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_20 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_21 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_22 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_23 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_24 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_25 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_26 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_27 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_28 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_29 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_30 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_31 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_32 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_33 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_34 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_35 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_36 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_37 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_38 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_39 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_40 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_41 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_42 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_43 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_44 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_45 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_46 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_47 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_48 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_49 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_50 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_51 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_52 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_53 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_54 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_55 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_56 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_57 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_58 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_59 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_60 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_61 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_62 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_63 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_64 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_65 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_66 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_67 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_68 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_69 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_70 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_71 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_72 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_73 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_74 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_75 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_76 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_77 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_78 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_79 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_80 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_81 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_82 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_83 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_84 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_85 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_86 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_87 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_88 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_89 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_90 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_91 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_92 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_93 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_94 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_95 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_96 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_97 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_98 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_99 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_100 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_101 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_102 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_103 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_104 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_105 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_106 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_107 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_108 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_109 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_110 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_111 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_112 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_113 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_114 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_115 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_116 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_117 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_118 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_119 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_120 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_121 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_122 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_123 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_124 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_125 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_126 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_127 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_5 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_6 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_7 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_8 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_9 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_10 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_11 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_13 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_14 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_15 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_16 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_17 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_18 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_19 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_20 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_21 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_22 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_23 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_24 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_25 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_26 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_27 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_28 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_29 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_30 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_31 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_32 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_33 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_34 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_35 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_36 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_37 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_38 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_39 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_40 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_41 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_42 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_43 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_44 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_45 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_46 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_47 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_48 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_49 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_50 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_51 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_52 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_53 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_54 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_55 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_56 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_57 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_58 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_59 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_60 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_61 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_62 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_63 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_64 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_65 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_66 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_67 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_68 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_69 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_70 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_71 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_72 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_73 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_74 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_75 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_76 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_77 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_78 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_79 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_80 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_81 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_82 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_83 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_84 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_85 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_86 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_87 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_88 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_89 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_90 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_91 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_92 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_93 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_94 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_95 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_96 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_97 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_98 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_99 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_100 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_101 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_102 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_103 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_104 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_105 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_106 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_107 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_108 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_109 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_110 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_111 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_112 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_113 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_114 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_115 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_116 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_117 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_118 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_119 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_120 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_121 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_122 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_123 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_124 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_125 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_126 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_127 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_debug_way_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_debug_rd_en_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1211 = 71'h0;
|
|
end
|
|
if (reset) begin
|
|
perr_ic_index_ff = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_sb_err_state_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_cmd_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
bus_cmd_beat_count = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_arready_unq_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_arvalid_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_dma_access_ok_prev = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_ecc_corr_data_ff = 39'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_mem_addr_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_mem_tag_ff = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_dma_rtag_temp = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_dma_rvalid_temp = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_dma_rdata_temp = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_ecc_corr_index_ff = 14'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_rd_ecc_single_err_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_rw_addr_f = 14'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_status_wr_addr_ff = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_wr_en_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_new_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_tag_wren_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_valid_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9747 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9748 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9749 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9753 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9754 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9775 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge rvclkhdr_2_io_l1clk) begin
|
|
if (scnd_miss_req) begin
|
|
imb_ff <= imb_scnd_ff;
|
|
end else if (!(sel_hold_imb)) begin
|
|
imb_ff <= io_ifc_fetch_addr_bf;
|
|
end
|
|
end
|
|
always @(posedge clock) begin
|
|
reset_ic_ff <= _T_298 & _T_299;
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
flush_final_f <= 1'h0;
|
|
end else begin
|
|
flush_final_f <= io_exu_flush_final;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_fetch_req_f_raw <= 1'h0;
|
|
end else begin
|
|
ifc_fetch_req_f_raw <= _T_317 & _T_318;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
miss_state <= 3'h0;
|
|
end else if (miss_state_en) begin
|
|
if (_T_24) begin
|
|
if (_T_26) begin
|
|
miss_state <= 3'h1;
|
|
end else begin
|
|
miss_state <= 3'h2;
|
|
end
|
|
end else if (_T_31) begin
|
|
if (_T_36) begin
|
|
miss_state <= 3'h0;
|
|
end else if (_T_40) begin
|
|
miss_state <= 3'h3;
|
|
end else if (_T_47) begin
|
|
miss_state <= 3'h4;
|
|
end else if (_T_51) begin
|
|
miss_state <= 3'h0;
|
|
end else if (_T_61) begin
|
|
miss_state <= 3'h6;
|
|
end else if (_T_71) begin
|
|
miss_state <= 3'h6;
|
|
end else if (_T_79) begin
|
|
miss_state <= 3'h0;
|
|
end else if (_T_84) begin
|
|
miss_state <= 3'h2;
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end else if (_T_102) begin
|
|
miss_state <= 3'h0;
|
|
end else if (_T_106) begin
|
|
if (_T_113) begin
|
|
miss_state <= 3'h2;
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end else if (_T_121) begin
|
|
if (_T_126) begin
|
|
miss_state <= 3'h2;
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end else if (_T_132) begin
|
|
if (_T_137) begin
|
|
miss_state <= 3'h5;
|
|
end else if (_T_143) begin
|
|
miss_state <= 3'h7;
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end else if (_T_151) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
miss_state <= 3'h0;
|
|
end else if (io_exu_flush_final) begin
|
|
if (_T_32) begin
|
|
miss_state <= 3'h0;
|
|
end else begin
|
|
miss_state <= 3'h2;
|
|
end
|
|
end else begin
|
|
miss_state <= 3'h1;
|
|
end
|
|
end else if (_T_160) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
miss_state <= 3'h0;
|
|
end else if (io_exu_flush_final) begin
|
|
if (_T_32) begin
|
|
miss_state <= 3'h0;
|
|
end else begin
|
|
miss_state <= 3'h2;
|
|
end
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
scnd_miss_req_q <= 1'h0;
|
|
end else begin
|
|
scnd_miss_req_q <= _T_22 & _T_319;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_fetch_addr_int_f <= 31'h0;
|
|
end else begin
|
|
ifu_fetch_addr_int_f <= io_ifc_fetch_addr_bf;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_iccm_access_f <= 1'h0;
|
|
end else begin
|
|
ifc_iccm_access_f <= io_ifc_iccm_access_bf;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_dma_rvalid_in <= 1'h0;
|
|
end else begin
|
|
iccm_dma_rvalid_in <= _T_2659 & _T_2663;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_iccm_req_f <= 1'h0;
|
|
end else begin
|
|
dma_iccm_req_f <= io_dma_iccm_req;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
perr_state <= 3'h0;
|
|
end else if (perr_state_en) begin
|
|
if (_T_2451) begin
|
|
if (io_iccm_dma_sb_error) begin
|
|
perr_state <= 3'h4;
|
|
end else if (_T_2453) begin
|
|
perr_state <= 3'h1;
|
|
end else begin
|
|
perr_state <= 3'h2;
|
|
end
|
|
end else if (_T_2463) begin
|
|
perr_state <= 3'h0;
|
|
end else if (_T_2466) begin
|
|
if (_T_2468) begin
|
|
perr_state <= 3'h0;
|
|
end else begin
|
|
perr_state <= 3'h3;
|
|
end
|
|
end else if (_T_2472) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
perr_state <= 3'h0;
|
|
end else begin
|
|
perr_state <= 3'h3;
|
|
end
|
|
end else begin
|
|
perr_state <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
err_stop_state <= 2'h0;
|
|
end else if (err_stop_state_en) begin
|
|
if (_T_2476) begin
|
|
err_stop_state <= 2'h1;
|
|
end else if (_T_2481) begin
|
|
if (_T_2483) begin
|
|
err_stop_state <= 2'h0;
|
|
end else if (_T_2504) begin
|
|
err_stop_state <= 2'h3;
|
|
end else if (io_ifu_fetch_val[0]) begin
|
|
err_stop_state <= 2'h2;
|
|
end else begin
|
|
err_stop_state <= 2'h1;
|
|
end
|
|
end else if (_T_2508) begin
|
|
if (_T_2483) begin
|
|
err_stop_state <= 2'h0;
|
|
end else if (io_ifu_fetch_val[0]) begin
|
|
err_stop_state <= 2'h3;
|
|
end else begin
|
|
err_stop_state <= 2'h2;
|
|
end
|
|
end else if (_T_2525) begin
|
|
if (_T_2529) begin
|
|
err_stop_state <= 2'h0;
|
|
end else if (io_dec_tlu_flush_err_wb) begin
|
|
err_stop_state <= 2'h1;
|
|
end else begin
|
|
err_stop_state <= 2'h3;
|
|
end
|
|
end else begin
|
|
err_stop_state <= 2'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
reset_all_tags <= 1'h0;
|
|
end else begin
|
|
reset_all_tags <= io_dec_tlu_fence_i_wb;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_region_acc_fault_final_f <= 1'h0;
|
|
end else begin
|
|
ifc_region_acc_fault_final_f <= io_ifc_region_acc_fault_bf;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_rvalid_unq_ff <= 1'h0;
|
|
end else begin
|
|
ifu_bus_rvalid_unq_ff <= io_ifu_axi_rvalid;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
bus_ifu_bus_clk_en_ff <= 1'h0;
|
|
end else begin
|
|
bus_ifu_bus_clk_en_ff <= io_ifu_bus_clk_en;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
uncacheable_miss_ff <= 1'h0;
|
|
end else if (scnd_miss_req) begin
|
|
uncacheable_miss_ff <= uncacheable_miss_scnd_ff;
|
|
end else if (!(sel_hold_imb)) begin
|
|
uncacheable_miss_ff <= io_ifc_fetch_uncacheable_bf;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
bus_data_beat_count <= 3'h0;
|
|
end else begin
|
|
bus_data_beat_count <= _T_2581 | _T_2582;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_valid <= 8'h0;
|
|
end else begin
|
|
ic_miss_buff_data_valid <= {_T_1353,ic_miss_buff_data_valid_in_0};
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
last_data_recieved_ff <= 1'h0;
|
|
end else begin
|
|
last_data_recieved_ff <= _T_2589 | _T_2591;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
sel_mb_addr_ff <= 1'h0;
|
|
end else begin
|
|
sel_mb_addr_ff <= _T_334 | reset_tag_valid_for_miss;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_mb_scnd_ff <= 1'h0;
|
|
end else if (!(_T_19)) begin
|
|
way_status_mb_scnd_ff <= way_status;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_ic_rw_int_addr_ff <= 7'h0;
|
|
end else if (_T_3945) begin
|
|
ifu_ic_rw_int_addr_ff <= io_ic_debug_addr[9:3];
|
|
end else begin
|
|
ifu_ic_rw_int_addr_ff <= ifu_ic_rw_int_addr[11:5];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_0 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_0 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_1 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_1 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_2 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_2 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_3 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_3 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_4 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_4 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_5 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_5 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_6 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_6 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_7 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_7 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_8 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_8 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_9 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_9 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_10 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_10 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_11 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_11 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_12 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_12 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_13 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_13 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_14 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_14 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_15 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_15 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_16 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_16 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_17 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_17 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_18 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_18 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_19 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_19 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_20 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_20 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_21 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_21 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_22 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_22 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_23 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_23 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_24 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_24 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_25 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_25 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_26 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_26 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_27 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_27 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_28 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_28 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_29 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_29 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_30 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_30 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_31 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_31 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_32 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_32 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_33 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_33 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_34 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_34 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_35 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_35 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_36 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_36 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_37 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_37 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_38 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_38 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_39 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_39 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_40 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_40 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_41 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_41 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_42 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_42 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_43 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_43 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_44 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_44 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_45 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_45 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_46 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_46 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_47 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_47 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_48 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_48 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_49 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_49 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_50 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_50 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_51 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_51 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_52 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_52 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_53 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_53 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_54 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_54 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_55 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_55 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_56 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_56 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_57 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_57 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_58 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_58 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_59 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_59 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_60 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_60 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_61 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_61 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_62 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_62 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_63 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_63 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_64 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_64 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_65 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_65 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_66 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_66 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_67 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_67 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_68 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_68 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_69 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_69 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_70 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_70 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_71 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_71 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_72 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_72 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_73 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_73 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_74 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_74 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_75 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_75 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_76 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_76 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_77 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_77 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_78 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_78 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_79 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_79 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_80 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_80 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_81 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_81 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_82 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_82 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_83 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_83 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_84 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_84 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_85 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_85 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_86 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_86 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_87 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_87 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_88 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_88 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_89 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_89 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_90 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_90 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_91 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_91 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_92 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_92 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_93 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_93 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_94 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_94 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_95 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_95 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_96 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_96 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_97 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_97 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_98 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_98 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_99 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_99 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_100 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_100 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_101 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_101 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_102 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_102 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_103 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_103 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_104 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_104 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_105 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_105 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_106 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_106 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_107 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_107 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_108 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_108 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_109 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_109 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_110 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_110 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_111 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_111 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_112 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_112 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_113 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_113 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_114 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_114 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_115 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_115 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_116 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_116 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_117 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_117 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_118 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_118 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_119 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_119 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_120 <= 1'h0;
|
|
end else if (_T_3969) begin
|
|
way_status_out_120 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_121 <= 1'h0;
|
|
end else if (_T_3973) begin
|
|
way_status_out_121 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_122 <= 1'h0;
|
|
end else if (_T_3977) begin
|
|
way_status_out_122 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_123 <= 1'h0;
|
|
end else if (_T_3981) begin
|
|
way_status_out_123 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_124 <= 1'h0;
|
|
end else if (_T_3985) begin
|
|
way_status_out_124 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_125 <= 1'h0;
|
|
end else if (_T_3989) begin
|
|
way_status_out_125 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_126 <= 1'h0;
|
|
end else if (_T_3993) begin
|
|
way_status_out_126 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_127 <= 1'h0;
|
|
end else if (_T_3997) begin
|
|
way_status_out_127 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
tagv_mb_scnd_ff <= 2'h0;
|
|
end else if (!(_T_19)) begin
|
|
tagv_mb_scnd_ff <= _T_198;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
uncacheable_miss_scnd_ff <= 1'h0;
|
|
end else if (!(sel_hold_imb_scnd)) begin
|
|
uncacheable_miss_scnd_ff <= io_ifc_fetch_uncacheable_bf;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
imb_scnd_ff <= 31'h0;
|
|
end else if (!(sel_hold_imb_scnd)) begin
|
|
imb_scnd_ff <= io_ifc_fetch_addr_bf;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_rid_ff <= 3'h0;
|
|
end else begin
|
|
ifu_bus_rid_ff <= io_ifu_axi_rid;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_rresp_ff <= 2'h0;
|
|
end else begin
|
|
ifu_bus_rresp_ff <= io_ifu_axi_rresp;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_wr_data_comb_err_ff <= 1'h0;
|
|
end else begin
|
|
ifu_wr_data_comb_err_ff <= ifu_wr_cumulative_err_data & _T_2577;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_mb_ff <= 1'h0;
|
|
end else if (_T_278) begin
|
|
way_status_mb_ff <= way_status_mb_scnd_ff;
|
|
end else if (_T_280) begin
|
|
way_status_mb_ff <= replace_way_mb_any_0;
|
|
end else if (!(miss_pending)) begin
|
|
way_status_mb_ff <= way_status;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
tagv_mb_ff <= 2'h0;
|
|
end else if (scnd_miss_req) begin
|
|
tagv_mb_ff <= _T_290;
|
|
end else if (!(miss_pending)) begin
|
|
tagv_mb_ff <= _T_295;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fetch_uncacheable_ff <= 1'h0;
|
|
end else begin
|
|
fetch_uncacheable_ff <= io_ifc_fetch_uncacheable_bf;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
miss_addr <= 26'h0;
|
|
end else if (_T_231) begin
|
|
miss_addr <= imb_ff[30:5];
|
|
end else if (scnd_miss_req_q) begin
|
|
miss_addr <= imb_scnd_ff[30:5];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_region_acc_fault_f <= 1'h0;
|
|
end else begin
|
|
ifc_region_acc_fault_f <= io_ifc_region_acc_fault_bf;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bus_rd_addr_count <= 3'h0;
|
|
end else if (_T_231) begin
|
|
bus_rd_addr_count <= imb_ff[4:2];
|
|
end else if (scnd_miss_req_q) begin
|
|
bus_rd_addr_count <= imb_scnd_ff[4:2];
|
|
end else if (bus_cmd_sent) begin
|
|
bus_rd_addr_count <= _T_2597;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_act_miss_f_delayed <= 1'h0;
|
|
end else begin
|
|
ic_act_miss_f_delayed <= _T_233 & _T_209;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_rdata_ff <= 64'h0;
|
|
end else begin
|
|
ifu_bus_rdata_ff <= io_ifu_axi_rdata;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_0 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_0 <= io_ifu_axi_rdata[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_1 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_1 <= io_ifu_axi_rdata[63:32];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_2 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_2 <= io_ifu_axi_rdata[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_3 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_3 <= io_ifu_axi_rdata[63:32];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_4 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_4 <= io_ifu_axi_rdata[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_5 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_5 <= io_ifu_axi_rdata[63:32];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_6 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_6 <= io_ifu_axi_rdata[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_7 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_7 <= io_ifu_axi_rdata[63:32];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_40_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_8 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_8 <= io_ifu_axi_rdata[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_40_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_9 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_9 <= io_ifu_axi_rdata[63:32];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_49_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_10 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_10 <= io_ifu_axi_rdata[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_49_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_11 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_11 <= io_ifu_axi_rdata[63:32];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_58_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_12 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_12 <= io_ifu_axi_rdata[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_58_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_13 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_13 <= io_ifu_axi_rdata[63:32];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_67_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_14 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_14 <= io_ifu_axi_rdata[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_67_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_15 <= 32'h0;
|
|
end else begin
|
|
ic_miss_buff_data_15 <= io_ifu_axi_rdata[63:32];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_crit_wd_rdy_new_ff <= 1'h0;
|
|
end else begin
|
|
ic_crit_wd_rdy_new_ff <= _T_1509 | _T_1514;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_error <= 8'h0;
|
|
end else begin
|
|
ic_miss_buff_data_error <= {_T_1393,ic_miss_buff_data_error_in_0};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_debug_ict_array_sel_ff <= 1'h0;
|
|
end else begin
|
|
ic_debug_ict_array_sel_ff <= io_ic_debug_rd_en & io_ic_debug_tag_array;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_0 <= 1'h0;
|
|
end else if (_T_5590) begin
|
|
ic_tag_valid_out_1_0 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_1 <= 1'h0;
|
|
end else if (_T_5605) begin
|
|
ic_tag_valid_out_1_1 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_2 <= 1'h0;
|
|
end else if (_T_5620) begin
|
|
ic_tag_valid_out_1_2 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_3 <= 1'h0;
|
|
end else if (_T_5635) begin
|
|
ic_tag_valid_out_1_3 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_4 <= 1'h0;
|
|
end else if (_T_5650) begin
|
|
ic_tag_valid_out_1_4 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_5 <= 1'h0;
|
|
end else if (_T_5665) begin
|
|
ic_tag_valid_out_1_5 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_6 <= 1'h0;
|
|
end else if (_T_5680) begin
|
|
ic_tag_valid_out_1_6 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_7 <= 1'h0;
|
|
end else if (_T_5695) begin
|
|
ic_tag_valid_out_1_7 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_8 <= 1'h0;
|
|
end else if (_T_5710) begin
|
|
ic_tag_valid_out_1_8 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_9 <= 1'h0;
|
|
end else if (_T_5725) begin
|
|
ic_tag_valid_out_1_9 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_10 <= 1'h0;
|
|
end else if (_T_5740) begin
|
|
ic_tag_valid_out_1_10 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_11 <= 1'h0;
|
|
end else if (_T_5755) begin
|
|
ic_tag_valid_out_1_11 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_12 <= 1'h0;
|
|
end else if (_T_5770) begin
|
|
ic_tag_valid_out_1_12 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_13 <= 1'h0;
|
|
end else if (_T_5785) begin
|
|
ic_tag_valid_out_1_13 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_14 <= 1'h0;
|
|
end else if (_T_5800) begin
|
|
ic_tag_valid_out_1_14 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_15 <= 1'h0;
|
|
end else if (_T_5815) begin
|
|
ic_tag_valid_out_1_15 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_16 <= 1'h0;
|
|
end else if (_T_5830) begin
|
|
ic_tag_valid_out_1_16 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_17 <= 1'h0;
|
|
end else if (_T_5845) begin
|
|
ic_tag_valid_out_1_17 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_18 <= 1'h0;
|
|
end else if (_T_5860) begin
|
|
ic_tag_valid_out_1_18 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_19 <= 1'h0;
|
|
end else if (_T_5875) begin
|
|
ic_tag_valid_out_1_19 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_20 <= 1'h0;
|
|
end else if (_T_5890) begin
|
|
ic_tag_valid_out_1_20 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_21 <= 1'h0;
|
|
end else if (_T_5905) begin
|
|
ic_tag_valid_out_1_21 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_22 <= 1'h0;
|
|
end else if (_T_5920) begin
|
|
ic_tag_valid_out_1_22 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_23 <= 1'h0;
|
|
end else if (_T_5935) begin
|
|
ic_tag_valid_out_1_23 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_24 <= 1'h0;
|
|
end else if (_T_5950) begin
|
|
ic_tag_valid_out_1_24 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_25 <= 1'h0;
|
|
end else if (_T_5965) begin
|
|
ic_tag_valid_out_1_25 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_26 <= 1'h0;
|
|
end else if (_T_5980) begin
|
|
ic_tag_valid_out_1_26 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_27 <= 1'h0;
|
|
end else if (_T_5995) begin
|
|
ic_tag_valid_out_1_27 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_28 <= 1'h0;
|
|
end else if (_T_6010) begin
|
|
ic_tag_valid_out_1_28 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_29 <= 1'h0;
|
|
end else if (_T_6025) begin
|
|
ic_tag_valid_out_1_29 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_30 <= 1'h0;
|
|
end else if (_T_6040) begin
|
|
ic_tag_valid_out_1_30 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_31 <= 1'h0;
|
|
end else if (_T_6055) begin
|
|
ic_tag_valid_out_1_31 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_32 <= 1'h0;
|
|
end else if (_T_6550) begin
|
|
ic_tag_valid_out_1_32 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_33 <= 1'h0;
|
|
end else if (_T_6565) begin
|
|
ic_tag_valid_out_1_33 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_34 <= 1'h0;
|
|
end else if (_T_6580) begin
|
|
ic_tag_valid_out_1_34 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_35 <= 1'h0;
|
|
end else if (_T_6595) begin
|
|
ic_tag_valid_out_1_35 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_36 <= 1'h0;
|
|
end else if (_T_6610) begin
|
|
ic_tag_valid_out_1_36 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_37 <= 1'h0;
|
|
end else if (_T_6625) begin
|
|
ic_tag_valid_out_1_37 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_38 <= 1'h0;
|
|
end else if (_T_6640) begin
|
|
ic_tag_valid_out_1_38 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_39 <= 1'h0;
|
|
end else if (_T_6655) begin
|
|
ic_tag_valid_out_1_39 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_40 <= 1'h0;
|
|
end else if (_T_6670) begin
|
|
ic_tag_valid_out_1_40 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_41 <= 1'h0;
|
|
end else if (_T_6685) begin
|
|
ic_tag_valid_out_1_41 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_42 <= 1'h0;
|
|
end else if (_T_6700) begin
|
|
ic_tag_valid_out_1_42 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_43 <= 1'h0;
|
|
end else if (_T_6715) begin
|
|
ic_tag_valid_out_1_43 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_44 <= 1'h0;
|
|
end else if (_T_6730) begin
|
|
ic_tag_valid_out_1_44 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_45 <= 1'h0;
|
|
end else if (_T_6745) begin
|
|
ic_tag_valid_out_1_45 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_46 <= 1'h0;
|
|
end else if (_T_6760) begin
|
|
ic_tag_valid_out_1_46 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_47 <= 1'h0;
|
|
end else if (_T_6775) begin
|
|
ic_tag_valid_out_1_47 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_48 <= 1'h0;
|
|
end else if (_T_6790) begin
|
|
ic_tag_valid_out_1_48 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_49 <= 1'h0;
|
|
end else if (_T_6805) begin
|
|
ic_tag_valid_out_1_49 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_50 <= 1'h0;
|
|
end else if (_T_6820) begin
|
|
ic_tag_valid_out_1_50 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_51 <= 1'h0;
|
|
end else if (_T_6835) begin
|
|
ic_tag_valid_out_1_51 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_52 <= 1'h0;
|
|
end else if (_T_6850) begin
|
|
ic_tag_valid_out_1_52 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_53 <= 1'h0;
|
|
end else if (_T_6865) begin
|
|
ic_tag_valid_out_1_53 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_54 <= 1'h0;
|
|
end else if (_T_6880) begin
|
|
ic_tag_valid_out_1_54 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_55 <= 1'h0;
|
|
end else if (_T_6895) begin
|
|
ic_tag_valid_out_1_55 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_56 <= 1'h0;
|
|
end else if (_T_6910) begin
|
|
ic_tag_valid_out_1_56 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_57 <= 1'h0;
|
|
end else if (_T_6925) begin
|
|
ic_tag_valid_out_1_57 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_58 <= 1'h0;
|
|
end else if (_T_6940) begin
|
|
ic_tag_valid_out_1_58 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_59 <= 1'h0;
|
|
end else if (_T_6955) begin
|
|
ic_tag_valid_out_1_59 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_60 <= 1'h0;
|
|
end else if (_T_6970) begin
|
|
ic_tag_valid_out_1_60 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_61 <= 1'h0;
|
|
end else if (_T_6985) begin
|
|
ic_tag_valid_out_1_61 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_62 <= 1'h0;
|
|
end else if (_T_7000) begin
|
|
ic_tag_valid_out_1_62 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_63 <= 1'h0;
|
|
end else if (_T_7015) begin
|
|
ic_tag_valid_out_1_63 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_64 <= 1'h0;
|
|
end else if (_T_7510) begin
|
|
ic_tag_valid_out_1_64 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_65 <= 1'h0;
|
|
end else if (_T_7525) begin
|
|
ic_tag_valid_out_1_65 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_66 <= 1'h0;
|
|
end else if (_T_7540) begin
|
|
ic_tag_valid_out_1_66 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_67 <= 1'h0;
|
|
end else if (_T_7555) begin
|
|
ic_tag_valid_out_1_67 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_68 <= 1'h0;
|
|
end else if (_T_7570) begin
|
|
ic_tag_valid_out_1_68 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_69 <= 1'h0;
|
|
end else if (_T_7585) begin
|
|
ic_tag_valid_out_1_69 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_70 <= 1'h0;
|
|
end else if (_T_7600) begin
|
|
ic_tag_valid_out_1_70 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_71 <= 1'h0;
|
|
end else if (_T_7615) begin
|
|
ic_tag_valid_out_1_71 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_72 <= 1'h0;
|
|
end else if (_T_7630) begin
|
|
ic_tag_valid_out_1_72 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_73 <= 1'h0;
|
|
end else if (_T_7645) begin
|
|
ic_tag_valid_out_1_73 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_74 <= 1'h0;
|
|
end else if (_T_7660) begin
|
|
ic_tag_valid_out_1_74 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_75 <= 1'h0;
|
|
end else if (_T_7675) begin
|
|
ic_tag_valid_out_1_75 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_76 <= 1'h0;
|
|
end else if (_T_7690) begin
|
|
ic_tag_valid_out_1_76 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_77 <= 1'h0;
|
|
end else if (_T_7705) begin
|
|
ic_tag_valid_out_1_77 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_78 <= 1'h0;
|
|
end else if (_T_7720) begin
|
|
ic_tag_valid_out_1_78 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_79 <= 1'h0;
|
|
end else if (_T_7735) begin
|
|
ic_tag_valid_out_1_79 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_80 <= 1'h0;
|
|
end else if (_T_7750) begin
|
|
ic_tag_valid_out_1_80 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_81 <= 1'h0;
|
|
end else if (_T_7765) begin
|
|
ic_tag_valid_out_1_81 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_82 <= 1'h0;
|
|
end else if (_T_7780) begin
|
|
ic_tag_valid_out_1_82 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_83 <= 1'h0;
|
|
end else if (_T_7795) begin
|
|
ic_tag_valid_out_1_83 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_84 <= 1'h0;
|
|
end else if (_T_7810) begin
|
|
ic_tag_valid_out_1_84 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_85 <= 1'h0;
|
|
end else if (_T_7825) begin
|
|
ic_tag_valid_out_1_85 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_86 <= 1'h0;
|
|
end else if (_T_7840) begin
|
|
ic_tag_valid_out_1_86 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_87 <= 1'h0;
|
|
end else if (_T_7855) begin
|
|
ic_tag_valid_out_1_87 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_88 <= 1'h0;
|
|
end else if (_T_7870) begin
|
|
ic_tag_valid_out_1_88 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_89 <= 1'h0;
|
|
end else if (_T_7885) begin
|
|
ic_tag_valid_out_1_89 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_90 <= 1'h0;
|
|
end else if (_T_7900) begin
|
|
ic_tag_valid_out_1_90 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_91 <= 1'h0;
|
|
end else if (_T_7915) begin
|
|
ic_tag_valid_out_1_91 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_92 <= 1'h0;
|
|
end else if (_T_7930) begin
|
|
ic_tag_valid_out_1_92 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_93 <= 1'h0;
|
|
end else if (_T_7945) begin
|
|
ic_tag_valid_out_1_93 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_94 <= 1'h0;
|
|
end else if (_T_7960) begin
|
|
ic_tag_valid_out_1_94 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_95 <= 1'h0;
|
|
end else if (_T_7975) begin
|
|
ic_tag_valid_out_1_95 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_96 <= 1'h0;
|
|
end else if (_T_8470) begin
|
|
ic_tag_valid_out_1_96 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_97 <= 1'h0;
|
|
end else if (_T_8485) begin
|
|
ic_tag_valid_out_1_97 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_98 <= 1'h0;
|
|
end else if (_T_8500) begin
|
|
ic_tag_valid_out_1_98 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_99 <= 1'h0;
|
|
end else if (_T_8515) begin
|
|
ic_tag_valid_out_1_99 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_100 <= 1'h0;
|
|
end else if (_T_8530) begin
|
|
ic_tag_valid_out_1_100 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_101 <= 1'h0;
|
|
end else if (_T_8545) begin
|
|
ic_tag_valid_out_1_101 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_102 <= 1'h0;
|
|
end else if (_T_8560) begin
|
|
ic_tag_valid_out_1_102 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_103 <= 1'h0;
|
|
end else if (_T_8575) begin
|
|
ic_tag_valid_out_1_103 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_104 <= 1'h0;
|
|
end else if (_T_8590) begin
|
|
ic_tag_valid_out_1_104 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_105 <= 1'h0;
|
|
end else if (_T_8605) begin
|
|
ic_tag_valid_out_1_105 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_106 <= 1'h0;
|
|
end else if (_T_8620) begin
|
|
ic_tag_valid_out_1_106 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_107 <= 1'h0;
|
|
end else if (_T_8635) begin
|
|
ic_tag_valid_out_1_107 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_108 <= 1'h0;
|
|
end else if (_T_8650) begin
|
|
ic_tag_valid_out_1_108 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_109 <= 1'h0;
|
|
end else if (_T_8665) begin
|
|
ic_tag_valid_out_1_109 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_110 <= 1'h0;
|
|
end else if (_T_8680) begin
|
|
ic_tag_valid_out_1_110 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_111 <= 1'h0;
|
|
end else if (_T_8695) begin
|
|
ic_tag_valid_out_1_111 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_112 <= 1'h0;
|
|
end else if (_T_8710) begin
|
|
ic_tag_valid_out_1_112 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_113 <= 1'h0;
|
|
end else if (_T_8725) begin
|
|
ic_tag_valid_out_1_113 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_114 <= 1'h0;
|
|
end else if (_T_8740) begin
|
|
ic_tag_valid_out_1_114 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_115 <= 1'h0;
|
|
end else if (_T_8755) begin
|
|
ic_tag_valid_out_1_115 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_116 <= 1'h0;
|
|
end else if (_T_8770) begin
|
|
ic_tag_valid_out_1_116 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_117 <= 1'h0;
|
|
end else if (_T_8785) begin
|
|
ic_tag_valid_out_1_117 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_118 <= 1'h0;
|
|
end else if (_T_8800) begin
|
|
ic_tag_valid_out_1_118 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_119 <= 1'h0;
|
|
end else if (_T_8815) begin
|
|
ic_tag_valid_out_1_119 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_120 <= 1'h0;
|
|
end else if (_T_8830) begin
|
|
ic_tag_valid_out_1_120 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_121 <= 1'h0;
|
|
end else if (_T_8845) begin
|
|
ic_tag_valid_out_1_121 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_122 <= 1'h0;
|
|
end else if (_T_8860) begin
|
|
ic_tag_valid_out_1_122 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_123 <= 1'h0;
|
|
end else if (_T_8875) begin
|
|
ic_tag_valid_out_1_123 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_124 <= 1'h0;
|
|
end else if (_T_8890) begin
|
|
ic_tag_valid_out_1_124 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_125 <= 1'h0;
|
|
end else if (_T_8905) begin
|
|
ic_tag_valid_out_1_125 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_126 <= 1'h0;
|
|
end else if (_T_8920) begin
|
|
ic_tag_valid_out_1_126 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_127 <= 1'h0;
|
|
end else if (_T_8935) begin
|
|
ic_tag_valid_out_1_127 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_0 <= 1'h0;
|
|
end else if (_T_5110) begin
|
|
ic_tag_valid_out_0_0 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_1 <= 1'h0;
|
|
end else if (_T_5125) begin
|
|
ic_tag_valid_out_0_1 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_2 <= 1'h0;
|
|
end else if (_T_5140) begin
|
|
ic_tag_valid_out_0_2 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_3 <= 1'h0;
|
|
end else if (_T_5155) begin
|
|
ic_tag_valid_out_0_3 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_4 <= 1'h0;
|
|
end else if (_T_5170) begin
|
|
ic_tag_valid_out_0_4 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_5 <= 1'h0;
|
|
end else if (_T_5185) begin
|
|
ic_tag_valid_out_0_5 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_6 <= 1'h0;
|
|
end else if (_T_5200) begin
|
|
ic_tag_valid_out_0_6 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_7 <= 1'h0;
|
|
end else if (_T_5215) begin
|
|
ic_tag_valid_out_0_7 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_8 <= 1'h0;
|
|
end else if (_T_5230) begin
|
|
ic_tag_valid_out_0_8 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_9 <= 1'h0;
|
|
end else if (_T_5245) begin
|
|
ic_tag_valid_out_0_9 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_10 <= 1'h0;
|
|
end else if (_T_5260) begin
|
|
ic_tag_valid_out_0_10 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_11 <= 1'h0;
|
|
end else if (_T_5275) begin
|
|
ic_tag_valid_out_0_11 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_12 <= 1'h0;
|
|
end else if (_T_5290) begin
|
|
ic_tag_valid_out_0_12 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_13 <= 1'h0;
|
|
end else if (_T_5305) begin
|
|
ic_tag_valid_out_0_13 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_14 <= 1'h0;
|
|
end else if (_T_5320) begin
|
|
ic_tag_valid_out_0_14 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_15 <= 1'h0;
|
|
end else if (_T_5335) begin
|
|
ic_tag_valid_out_0_15 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_16 <= 1'h0;
|
|
end else if (_T_5350) begin
|
|
ic_tag_valid_out_0_16 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_17 <= 1'h0;
|
|
end else if (_T_5365) begin
|
|
ic_tag_valid_out_0_17 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_18 <= 1'h0;
|
|
end else if (_T_5380) begin
|
|
ic_tag_valid_out_0_18 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_19 <= 1'h0;
|
|
end else if (_T_5395) begin
|
|
ic_tag_valid_out_0_19 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_20 <= 1'h0;
|
|
end else if (_T_5410) begin
|
|
ic_tag_valid_out_0_20 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_21 <= 1'h0;
|
|
end else if (_T_5425) begin
|
|
ic_tag_valid_out_0_21 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_22 <= 1'h0;
|
|
end else if (_T_5440) begin
|
|
ic_tag_valid_out_0_22 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_23 <= 1'h0;
|
|
end else if (_T_5455) begin
|
|
ic_tag_valid_out_0_23 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_24 <= 1'h0;
|
|
end else if (_T_5470) begin
|
|
ic_tag_valid_out_0_24 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_25 <= 1'h0;
|
|
end else if (_T_5485) begin
|
|
ic_tag_valid_out_0_25 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_26 <= 1'h0;
|
|
end else if (_T_5500) begin
|
|
ic_tag_valid_out_0_26 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_27 <= 1'h0;
|
|
end else if (_T_5515) begin
|
|
ic_tag_valid_out_0_27 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_28 <= 1'h0;
|
|
end else if (_T_5530) begin
|
|
ic_tag_valid_out_0_28 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_29 <= 1'h0;
|
|
end else if (_T_5545) begin
|
|
ic_tag_valid_out_0_29 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_30 <= 1'h0;
|
|
end else if (_T_5560) begin
|
|
ic_tag_valid_out_0_30 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_31 <= 1'h0;
|
|
end else if (_T_5575) begin
|
|
ic_tag_valid_out_0_31 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_32 <= 1'h0;
|
|
end else if (_T_6070) begin
|
|
ic_tag_valid_out_0_32 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_33 <= 1'h0;
|
|
end else if (_T_6085) begin
|
|
ic_tag_valid_out_0_33 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_34 <= 1'h0;
|
|
end else if (_T_6100) begin
|
|
ic_tag_valid_out_0_34 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_35 <= 1'h0;
|
|
end else if (_T_6115) begin
|
|
ic_tag_valid_out_0_35 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_36 <= 1'h0;
|
|
end else if (_T_6130) begin
|
|
ic_tag_valid_out_0_36 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_37 <= 1'h0;
|
|
end else if (_T_6145) begin
|
|
ic_tag_valid_out_0_37 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_38 <= 1'h0;
|
|
end else if (_T_6160) begin
|
|
ic_tag_valid_out_0_38 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_39 <= 1'h0;
|
|
end else if (_T_6175) begin
|
|
ic_tag_valid_out_0_39 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_40 <= 1'h0;
|
|
end else if (_T_6190) begin
|
|
ic_tag_valid_out_0_40 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_41 <= 1'h0;
|
|
end else if (_T_6205) begin
|
|
ic_tag_valid_out_0_41 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_42 <= 1'h0;
|
|
end else if (_T_6220) begin
|
|
ic_tag_valid_out_0_42 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_43 <= 1'h0;
|
|
end else if (_T_6235) begin
|
|
ic_tag_valid_out_0_43 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_44 <= 1'h0;
|
|
end else if (_T_6250) begin
|
|
ic_tag_valid_out_0_44 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_45 <= 1'h0;
|
|
end else if (_T_6265) begin
|
|
ic_tag_valid_out_0_45 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_46 <= 1'h0;
|
|
end else if (_T_6280) begin
|
|
ic_tag_valid_out_0_46 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_47 <= 1'h0;
|
|
end else if (_T_6295) begin
|
|
ic_tag_valid_out_0_47 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_48 <= 1'h0;
|
|
end else if (_T_6310) begin
|
|
ic_tag_valid_out_0_48 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_49 <= 1'h0;
|
|
end else if (_T_6325) begin
|
|
ic_tag_valid_out_0_49 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_50 <= 1'h0;
|
|
end else if (_T_6340) begin
|
|
ic_tag_valid_out_0_50 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_51 <= 1'h0;
|
|
end else if (_T_6355) begin
|
|
ic_tag_valid_out_0_51 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_52 <= 1'h0;
|
|
end else if (_T_6370) begin
|
|
ic_tag_valid_out_0_52 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_53 <= 1'h0;
|
|
end else if (_T_6385) begin
|
|
ic_tag_valid_out_0_53 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_54 <= 1'h0;
|
|
end else if (_T_6400) begin
|
|
ic_tag_valid_out_0_54 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_55 <= 1'h0;
|
|
end else if (_T_6415) begin
|
|
ic_tag_valid_out_0_55 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_56 <= 1'h0;
|
|
end else if (_T_6430) begin
|
|
ic_tag_valid_out_0_56 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_57 <= 1'h0;
|
|
end else if (_T_6445) begin
|
|
ic_tag_valid_out_0_57 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_58 <= 1'h0;
|
|
end else if (_T_6460) begin
|
|
ic_tag_valid_out_0_58 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_59 <= 1'h0;
|
|
end else if (_T_6475) begin
|
|
ic_tag_valid_out_0_59 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_60 <= 1'h0;
|
|
end else if (_T_6490) begin
|
|
ic_tag_valid_out_0_60 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_61 <= 1'h0;
|
|
end else if (_T_6505) begin
|
|
ic_tag_valid_out_0_61 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_62 <= 1'h0;
|
|
end else if (_T_6520) begin
|
|
ic_tag_valid_out_0_62 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_63 <= 1'h0;
|
|
end else if (_T_6535) begin
|
|
ic_tag_valid_out_0_63 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_64 <= 1'h0;
|
|
end else if (_T_7030) begin
|
|
ic_tag_valid_out_0_64 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_65 <= 1'h0;
|
|
end else if (_T_7045) begin
|
|
ic_tag_valid_out_0_65 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_66 <= 1'h0;
|
|
end else if (_T_7060) begin
|
|
ic_tag_valid_out_0_66 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_67 <= 1'h0;
|
|
end else if (_T_7075) begin
|
|
ic_tag_valid_out_0_67 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_68 <= 1'h0;
|
|
end else if (_T_7090) begin
|
|
ic_tag_valid_out_0_68 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_69 <= 1'h0;
|
|
end else if (_T_7105) begin
|
|
ic_tag_valid_out_0_69 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_70 <= 1'h0;
|
|
end else if (_T_7120) begin
|
|
ic_tag_valid_out_0_70 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_71 <= 1'h0;
|
|
end else if (_T_7135) begin
|
|
ic_tag_valid_out_0_71 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_72 <= 1'h0;
|
|
end else if (_T_7150) begin
|
|
ic_tag_valid_out_0_72 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_73 <= 1'h0;
|
|
end else if (_T_7165) begin
|
|
ic_tag_valid_out_0_73 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_74 <= 1'h0;
|
|
end else if (_T_7180) begin
|
|
ic_tag_valid_out_0_74 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_75 <= 1'h0;
|
|
end else if (_T_7195) begin
|
|
ic_tag_valid_out_0_75 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_76 <= 1'h0;
|
|
end else if (_T_7210) begin
|
|
ic_tag_valid_out_0_76 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_77 <= 1'h0;
|
|
end else if (_T_7225) begin
|
|
ic_tag_valid_out_0_77 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_78 <= 1'h0;
|
|
end else if (_T_7240) begin
|
|
ic_tag_valid_out_0_78 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_79 <= 1'h0;
|
|
end else if (_T_7255) begin
|
|
ic_tag_valid_out_0_79 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_80 <= 1'h0;
|
|
end else if (_T_7270) begin
|
|
ic_tag_valid_out_0_80 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_81 <= 1'h0;
|
|
end else if (_T_7285) begin
|
|
ic_tag_valid_out_0_81 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_82 <= 1'h0;
|
|
end else if (_T_7300) begin
|
|
ic_tag_valid_out_0_82 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_83 <= 1'h0;
|
|
end else if (_T_7315) begin
|
|
ic_tag_valid_out_0_83 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_84 <= 1'h0;
|
|
end else if (_T_7330) begin
|
|
ic_tag_valid_out_0_84 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_85 <= 1'h0;
|
|
end else if (_T_7345) begin
|
|
ic_tag_valid_out_0_85 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_86 <= 1'h0;
|
|
end else if (_T_7360) begin
|
|
ic_tag_valid_out_0_86 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_87 <= 1'h0;
|
|
end else if (_T_7375) begin
|
|
ic_tag_valid_out_0_87 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_88 <= 1'h0;
|
|
end else if (_T_7390) begin
|
|
ic_tag_valid_out_0_88 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_89 <= 1'h0;
|
|
end else if (_T_7405) begin
|
|
ic_tag_valid_out_0_89 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_90 <= 1'h0;
|
|
end else if (_T_7420) begin
|
|
ic_tag_valid_out_0_90 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_91 <= 1'h0;
|
|
end else if (_T_7435) begin
|
|
ic_tag_valid_out_0_91 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_92 <= 1'h0;
|
|
end else if (_T_7450) begin
|
|
ic_tag_valid_out_0_92 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_93 <= 1'h0;
|
|
end else if (_T_7465) begin
|
|
ic_tag_valid_out_0_93 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_94 <= 1'h0;
|
|
end else if (_T_7480) begin
|
|
ic_tag_valid_out_0_94 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_95 <= 1'h0;
|
|
end else if (_T_7495) begin
|
|
ic_tag_valid_out_0_95 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_96 <= 1'h0;
|
|
end else if (_T_7990) begin
|
|
ic_tag_valid_out_0_96 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_97 <= 1'h0;
|
|
end else if (_T_8005) begin
|
|
ic_tag_valid_out_0_97 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_98 <= 1'h0;
|
|
end else if (_T_8020) begin
|
|
ic_tag_valid_out_0_98 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_99 <= 1'h0;
|
|
end else if (_T_8035) begin
|
|
ic_tag_valid_out_0_99 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_100 <= 1'h0;
|
|
end else if (_T_8050) begin
|
|
ic_tag_valid_out_0_100 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_101 <= 1'h0;
|
|
end else if (_T_8065) begin
|
|
ic_tag_valid_out_0_101 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_102 <= 1'h0;
|
|
end else if (_T_8080) begin
|
|
ic_tag_valid_out_0_102 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_103 <= 1'h0;
|
|
end else if (_T_8095) begin
|
|
ic_tag_valid_out_0_103 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_104 <= 1'h0;
|
|
end else if (_T_8110) begin
|
|
ic_tag_valid_out_0_104 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_105 <= 1'h0;
|
|
end else if (_T_8125) begin
|
|
ic_tag_valid_out_0_105 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_106 <= 1'h0;
|
|
end else if (_T_8140) begin
|
|
ic_tag_valid_out_0_106 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_107 <= 1'h0;
|
|
end else if (_T_8155) begin
|
|
ic_tag_valid_out_0_107 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_108 <= 1'h0;
|
|
end else if (_T_8170) begin
|
|
ic_tag_valid_out_0_108 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_109 <= 1'h0;
|
|
end else if (_T_8185) begin
|
|
ic_tag_valid_out_0_109 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_110 <= 1'h0;
|
|
end else if (_T_8200) begin
|
|
ic_tag_valid_out_0_110 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_111 <= 1'h0;
|
|
end else if (_T_8215) begin
|
|
ic_tag_valid_out_0_111 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_112 <= 1'h0;
|
|
end else if (_T_8230) begin
|
|
ic_tag_valid_out_0_112 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_113 <= 1'h0;
|
|
end else if (_T_8245) begin
|
|
ic_tag_valid_out_0_113 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_114 <= 1'h0;
|
|
end else if (_T_8260) begin
|
|
ic_tag_valid_out_0_114 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_115 <= 1'h0;
|
|
end else if (_T_8275) begin
|
|
ic_tag_valid_out_0_115 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_116 <= 1'h0;
|
|
end else if (_T_8290) begin
|
|
ic_tag_valid_out_0_116 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_117 <= 1'h0;
|
|
end else if (_T_8305) begin
|
|
ic_tag_valid_out_0_117 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_118 <= 1'h0;
|
|
end else if (_T_8320) begin
|
|
ic_tag_valid_out_0_118 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_119 <= 1'h0;
|
|
end else if (_T_8335) begin
|
|
ic_tag_valid_out_0_119 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_120 <= 1'h0;
|
|
end else if (_T_8350) begin
|
|
ic_tag_valid_out_0_120 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_121 <= 1'h0;
|
|
end else if (_T_8365) begin
|
|
ic_tag_valid_out_0_121 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_122 <= 1'h0;
|
|
end else if (_T_8380) begin
|
|
ic_tag_valid_out_0_122 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_123 <= 1'h0;
|
|
end else if (_T_8395) begin
|
|
ic_tag_valid_out_0_123 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_124 <= 1'h0;
|
|
end else if (_T_8410) begin
|
|
ic_tag_valid_out_0_124 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_125 <= 1'h0;
|
|
end else if (_T_8425) begin
|
|
ic_tag_valid_out_0_125 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_126 <= 1'h0;
|
|
end else if (_T_8440) begin
|
|
ic_tag_valid_out_0_126 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_127 <= 1'h0;
|
|
end else if (_T_8455) begin
|
|
ic_tag_valid_out_0_127 <= _T_5102;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_debug_way_ff <= 2'h0;
|
|
end else begin
|
|
ic_debug_way_ff <= io_ic_debug_way;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_debug_rd_en_ff <= 1'h0;
|
|
end else begin
|
|
ic_debug_rd_en_ff <= io_ic_debug_rd_en;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1211 <= 71'h0;
|
|
end else if (ic_debug_ict_array_sel_ff) begin
|
|
_T_1211 <= {{5'd0}, _T_1210};
|
|
end else begin
|
|
_T_1211 <= io_ic_debug_rd_data;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
perr_ic_index_ff <= 7'h0;
|
|
end else if (perr_sb_write_status) begin
|
|
perr_ic_index_ff <= ifu_ic_rw_int_addr_ff;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_sb_err_state_ff <= 1'h0;
|
|
end else begin
|
|
dma_sb_err_state_ff <= perr_state == 3'h4;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_69_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_cmd_valid <= 1'h0;
|
|
end else begin
|
|
ifu_bus_cmd_valid <= _T_2544 & _T_2550;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bus_cmd_beat_count <= 3'h0;
|
|
end else if (bus_cmd_beat_en) begin
|
|
bus_cmd_beat_count <= bus_new_cmd_beat_count;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_arready_unq_ff <= 1'h0;
|
|
end else begin
|
|
ifu_bus_arready_unq_ff <= io_ifu_axi_arready;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_arvalid_ff <= 1'h0;
|
|
end else begin
|
|
ifu_bus_arvalid_ff <= io_ifu_axi_arvalid;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_dma_access_ok_prev <= 1'h0;
|
|
end else begin
|
|
ifc_dma_access_ok_prev <= _T_2649 & _T_2650;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_ecc_corr_data_ff <= 39'h0;
|
|
end else if (iccm_ecc_write_status) begin
|
|
iccm_ecc_corr_data_ff <= _T_3880;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_mem_addr_ff <= 2'h0;
|
|
end else begin
|
|
dma_mem_addr_ff <= io_dma_mem_addr[3:2];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_mem_tag_ff <= 3'h0;
|
|
end else begin
|
|
dma_mem_tag_ff <= io_dma_mem_tag;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_dma_rtag_temp <= 3'h0;
|
|
end else begin
|
|
iccm_dma_rtag_temp <= dma_mem_tag_ff;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_dma_rvalid_temp <= 1'h0;
|
|
end else begin
|
|
iccm_dma_rvalid_temp <= iccm_dma_rvalid_in;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_dma_rdata_temp <= 64'h0;
|
|
end else if (iccm_dma_ecc_error_in) begin
|
|
iccm_dma_rdata_temp <= _T_3054;
|
|
end else begin
|
|
iccm_dma_rdata_temp <= _T_3055;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_ecc_corr_index_ff <= 14'h0;
|
|
end else if (iccm_ecc_write_status) begin
|
|
if (iccm_single_ecc_error[0]) begin
|
|
iccm_ecc_corr_index_ff <= iccm_rw_addr_f;
|
|
end else begin
|
|
iccm_ecc_corr_index_ff <= _T_3876;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_rd_ecc_single_err_ff <= 1'h0;
|
|
end else begin
|
|
iccm_rd_ecc_single_err_ff <= _T_3871 & _T_319;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_rw_addr_f <= 14'h0;
|
|
end else begin
|
|
iccm_rw_addr_f <= io_iccm_rw_addr[14:1];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_status_wr_addr_ff <= 7'h0;
|
|
end else if (_T_3945) begin
|
|
ifu_status_wr_addr_ff <= io_ic_debug_addr[9:3];
|
|
end else begin
|
|
ifu_status_wr_addr_ff <= ifu_status_wr_addr[11:5];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_wr_en_ff <= 1'h0;
|
|
end else begin
|
|
way_status_wr_en_ff <= way_status_wr_en | _T_3948;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_new_ff <= 1'h0;
|
|
end else if (_T_3948) begin
|
|
way_status_new_ff <= io_ic_debug_wr_data[4];
|
|
end else if (_T_9725) begin
|
|
way_status_new_ff <= replace_way_mb_any_0;
|
|
end else begin
|
|
way_status_new_ff <= way_status_hit_new;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_tag_wren_ff <= 2'h0;
|
|
end else begin
|
|
ifu_tag_wren_ff <= ifu_tag_wren | ic_debug_tag_wr_en;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_valid_ff <= 1'h0;
|
|
end else if (_T_3948) begin
|
|
ic_valid_ff <= io_ic_debug_wr_data[0];
|
|
end else begin
|
|
ic_valid_ff <= ic_valid;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9747 <= 1'h0;
|
|
end else begin
|
|
_T_9747 <= _T_233 & _T_209;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9748 <= 1'h0;
|
|
end else begin
|
|
_T_9748 <= _T_225 & _T_247;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9749 <= 1'h0;
|
|
end else begin
|
|
_T_9749 <= ic_byp_hit_f & ifu_byp_data_err_new;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9753 <= 1'h0;
|
|
end else begin
|
|
_T_9753 <= _T_9751 & miss_pending;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9754 <= 1'h0;
|
|
end else begin
|
|
_T_9754 <= _T_2568 & _T_2573;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9775 <= 1'h0;
|
|
end else if (ic_debug_rd_en_ff) begin
|
|
_T_9775 <= ic_debug_rd_en_ff;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_ifu_bp_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_active_clk,
|
|
input io_ic_hit_f,
|
|
input [30:0] io_ifc_fetch_addr_f,
|
|
input io_ifc_fetch_req_f,
|
|
input io_dec_tlu_br0_r_pkt_valid,
|
|
input [1:0] io_dec_tlu_br0_r_pkt_hist,
|
|
input io_dec_tlu_br0_r_pkt_br_error,
|
|
input io_dec_tlu_br0_r_pkt_br_start_error,
|
|
input io_dec_tlu_br0_r_pkt_way,
|
|
input io_dec_tlu_br0_r_pkt_middle,
|
|
input [7:0] io_exu_i0_br_fghr_r,
|
|
input [7:0] io_exu_i0_br_index_r,
|
|
input io_dec_tlu_flush_lower_wb,
|
|
input io_dec_tlu_flush_leak_one_wb,
|
|
input io_dec_tlu_bpred_disable,
|
|
input io_exu_mp_pkt_bits_misp,
|
|
input io_exu_mp_pkt_bits_ataken,
|
|
input io_exu_mp_pkt_bits_boffset,
|
|
input io_exu_mp_pkt_bits_pc4,
|
|
input [1:0] io_exu_mp_pkt_bits_hist,
|
|
input [11:0] io_exu_mp_pkt_bits_toffset,
|
|
input io_exu_mp_pkt_bits_pcall,
|
|
input io_exu_mp_pkt_bits_pret,
|
|
input io_exu_mp_pkt_bits_pja,
|
|
input io_exu_mp_pkt_bits_way,
|
|
input [7:0] io_exu_mp_eghr,
|
|
input [7:0] io_exu_mp_fghr,
|
|
input [7:0] io_exu_mp_index,
|
|
input [4:0] io_exu_mp_btag,
|
|
input io_exu_flush_final,
|
|
output io_ifu_bp_hit_taken_f,
|
|
output [30:0] io_ifu_bp_btb_target_f,
|
|
output io_ifu_bp_inst_mask_f,
|
|
output [7:0] io_ifu_bp_fghr_f,
|
|
output [1:0] io_ifu_bp_way_f,
|
|
output [1:0] io_ifu_bp_ret_f,
|
|
output [1:0] io_ifu_bp_hist1_f,
|
|
output [1:0] io_ifu_bp_hist0_f,
|
|
output [1:0] io_ifu_bp_pc4_f,
|
|
output [1:0] io_ifu_bp_valid_f,
|
|
output [11:0] io_ifu_bp_poffset_f,
|
|
input io_scan_mode
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
reg [31:0] _RAND_75;
|
|
reg [31:0] _RAND_76;
|
|
reg [31:0] _RAND_77;
|
|
reg [31:0] _RAND_78;
|
|
reg [31:0] _RAND_79;
|
|
reg [31:0] _RAND_80;
|
|
reg [31:0] _RAND_81;
|
|
reg [31:0] _RAND_82;
|
|
reg [31:0] _RAND_83;
|
|
reg [31:0] _RAND_84;
|
|
reg [31:0] _RAND_85;
|
|
reg [31:0] _RAND_86;
|
|
reg [31:0] _RAND_87;
|
|
reg [31:0] _RAND_88;
|
|
reg [31:0] _RAND_89;
|
|
reg [31:0] _RAND_90;
|
|
reg [31:0] _RAND_91;
|
|
reg [31:0] _RAND_92;
|
|
reg [31:0] _RAND_93;
|
|
reg [31:0] _RAND_94;
|
|
reg [31:0] _RAND_95;
|
|
reg [31:0] _RAND_96;
|
|
reg [31:0] _RAND_97;
|
|
reg [31:0] _RAND_98;
|
|
reg [31:0] _RAND_99;
|
|
reg [31:0] _RAND_100;
|
|
reg [31:0] _RAND_101;
|
|
reg [31:0] _RAND_102;
|
|
reg [31:0] _RAND_103;
|
|
reg [31:0] _RAND_104;
|
|
reg [31:0] _RAND_105;
|
|
reg [31:0] _RAND_106;
|
|
reg [31:0] _RAND_107;
|
|
reg [31:0] _RAND_108;
|
|
reg [31:0] _RAND_109;
|
|
reg [31:0] _RAND_110;
|
|
reg [31:0] _RAND_111;
|
|
reg [31:0] _RAND_112;
|
|
reg [31:0] _RAND_113;
|
|
reg [31:0] _RAND_114;
|
|
reg [31:0] _RAND_115;
|
|
reg [31:0] _RAND_116;
|
|
reg [31:0] _RAND_117;
|
|
reg [31:0] _RAND_118;
|
|
reg [31:0] _RAND_119;
|
|
reg [31:0] _RAND_120;
|
|
reg [31:0] _RAND_121;
|
|
reg [31:0] _RAND_122;
|
|
reg [31:0] _RAND_123;
|
|
reg [31:0] _RAND_124;
|
|
reg [31:0] _RAND_125;
|
|
reg [31:0] _RAND_126;
|
|
reg [31:0] _RAND_127;
|
|
reg [31:0] _RAND_128;
|
|
reg [31:0] _RAND_129;
|
|
reg [31:0] _RAND_130;
|
|
reg [31:0] _RAND_131;
|
|
reg [31:0] _RAND_132;
|
|
reg [31:0] _RAND_133;
|
|
reg [31:0] _RAND_134;
|
|
reg [31:0] _RAND_135;
|
|
reg [31:0] _RAND_136;
|
|
reg [31:0] _RAND_137;
|
|
reg [31:0] _RAND_138;
|
|
reg [31:0] _RAND_139;
|
|
reg [31:0] _RAND_140;
|
|
reg [31:0] _RAND_141;
|
|
reg [31:0] _RAND_142;
|
|
reg [31:0] _RAND_143;
|
|
reg [31:0] _RAND_144;
|
|
reg [31:0] _RAND_145;
|
|
reg [31:0] _RAND_146;
|
|
reg [31:0] _RAND_147;
|
|
reg [31:0] _RAND_148;
|
|
reg [31:0] _RAND_149;
|
|
reg [31:0] _RAND_150;
|
|
reg [31:0] _RAND_151;
|
|
reg [31:0] _RAND_152;
|
|
reg [31:0] _RAND_153;
|
|
reg [31:0] _RAND_154;
|
|
reg [31:0] _RAND_155;
|
|
reg [31:0] _RAND_156;
|
|
reg [31:0] _RAND_157;
|
|
reg [31:0] _RAND_158;
|
|
reg [31:0] _RAND_159;
|
|
reg [31:0] _RAND_160;
|
|
reg [31:0] _RAND_161;
|
|
reg [31:0] _RAND_162;
|
|
reg [31:0] _RAND_163;
|
|
reg [31:0] _RAND_164;
|
|
reg [31:0] _RAND_165;
|
|
reg [31:0] _RAND_166;
|
|
reg [31:0] _RAND_167;
|
|
reg [31:0] _RAND_168;
|
|
reg [31:0] _RAND_169;
|
|
reg [31:0] _RAND_170;
|
|
reg [31:0] _RAND_171;
|
|
reg [31:0] _RAND_172;
|
|
reg [31:0] _RAND_173;
|
|
reg [31:0] _RAND_174;
|
|
reg [31:0] _RAND_175;
|
|
reg [31:0] _RAND_176;
|
|
reg [31:0] _RAND_177;
|
|
reg [31:0] _RAND_178;
|
|
reg [31:0] _RAND_179;
|
|
reg [31:0] _RAND_180;
|
|
reg [31:0] _RAND_181;
|
|
reg [31:0] _RAND_182;
|
|
reg [31:0] _RAND_183;
|
|
reg [31:0] _RAND_184;
|
|
reg [31:0] _RAND_185;
|
|
reg [31:0] _RAND_186;
|
|
reg [31:0] _RAND_187;
|
|
reg [31:0] _RAND_188;
|
|
reg [31:0] _RAND_189;
|
|
reg [31:0] _RAND_190;
|
|
reg [31:0] _RAND_191;
|
|
reg [31:0] _RAND_192;
|
|
reg [31:0] _RAND_193;
|
|
reg [31:0] _RAND_194;
|
|
reg [31:0] _RAND_195;
|
|
reg [31:0] _RAND_196;
|
|
reg [31:0] _RAND_197;
|
|
reg [31:0] _RAND_198;
|
|
reg [31:0] _RAND_199;
|
|
reg [31:0] _RAND_200;
|
|
reg [31:0] _RAND_201;
|
|
reg [31:0] _RAND_202;
|
|
reg [31:0] _RAND_203;
|
|
reg [31:0] _RAND_204;
|
|
reg [31:0] _RAND_205;
|
|
reg [31:0] _RAND_206;
|
|
reg [31:0] _RAND_207;
|
|
reg [31:0] _RAND_208;
|
|
reg [31:0] _RAND_209;
|
|
reg [31:0] _RAND_210;
|
|
reg [31:0] _RAND_211;
|
|
reg [31:0] _RAND_212;
|
|
reg [31:0] _RAND_213;
|
|
reg [31:0] _RAND_214;
|
|
reg [31:0] _RAND_215;
|
|
reg [31:0] _RAND_216;
|
|
reg [31:0] _RAND_217;
|
|
reg [31:0] _RAND_218;
|
|
reg [31:0] _RAND_219;
|
|
reg [31:0] _RAND_220;
|
|
reg [31:0] _RAND_221;
|
|
reg [31:0] _RAND_222;
|
|
reg [31:0] _RAND_223;
|
|
reg [31:0] _RAND_224;
|
|
reg [31:0] _RAND_225;
|
|
reg [31:0] _RAND_226;
|
|
reg [31:0] _RAND_227;
|
|
reg [31:0] _RAND_228;
|
|
reg [31:0] _RAND_229;
|
|
reg [31:0] _RAND_230;
|
|
reg [31:0] _RAND_231;
|
|
reg [31:0] _RAND_232;
|
|
reg [31:0] _RAND_233;
|
|
reg [31:0] _RAND_234;
|
|
reg [31:0] _RAND_235;
|
|
reg [31:0] _RAND_236;
|
|
reg [31:0] _RAND_237;
|
|
reg [31:0] _RAND_238;
|
|
reg [31:0] _RAND_239;
|
|
reg [31:0] _RAND_240;
|
|
reg [31:0] _RAND_241;
|
|
reg [31:0] _RAND_242;
|
|
reg [31:0] _RAND_243;
|
|
reg [31:0] _RAND_244;
|
|
reg [31:0] _RAND_245;
|
|
reg [31:0] _RAND_246;
|
|
reg [31:0] _RAND_247;
|
|
reg [31:0] _RAND_248;
|
|
reg [31:0] _RAND_249;
|
|
reg [31:0] _RAND_250;
|
|
reg [31:0] _RAND_251;
|
|
reg [31:0] _RAND_252;
|
|
reg [31:0] _RAND_253;
|
|
reg [31:0] _RAND_254;
|
|
reg [31:0] _RAND_255;
|
|
reg [31:0] _RAND_256;
|
|
reg [31:0] _RAND_257;
|
|
reg [31:0] _RAND_258;
|
|
reg [31:0] _RAND_259;
|
|
reg [31:0] _RAND_260;
|
|
reg [31:0] _RAND_261;
|
|
reg [31:0] _RAND_262;
|
|
reg [31:0] _RAND_263;
|
|
reg [31:0] _RAND_264;
|
|
reg [31:0] _RAND_265;
|
|
reg [31:0] _RAND_266;
|
|
reg [31:0] _RAND_267;
|
|
reg [31:0] _RAND_268;
|
|
reg [31:0] _RAND_269;
|
|
reg [31:0] _RAND_270;
|
|
reg [31:0] _RAND_271;
|
|
reg [31:0] _RAND_272;
|
|
reg [31:0] _RAND_273;
|
|
reg [31:0] _RAND_274;
|
|
reg [31:0] _RAND_275;
|
|
reg [31:0] _RAND_276;
|
|
reg [31:0] _RAND_277;
|
|
reg [31:0] _RAND_278;
|
|
reg [31:0] _RAND_279;
|
|
reg [31:0] _RAND_280;
|
|
reg [31:0] _RAND_281;
|
|
reg [31:0] _RAND_282;
|
|
reg [31:0] _RAND_283;
|
|
reg [31:0] _RAND_284;
|
|
reg [31:0] _RAND_285;
|
|
reg [31:0] _RAND_286;
|
|
reg [31:0] _RAND_287;
|
|
reg [31:0] _RAND_288;
|
|
reg [31:0] _RAND_289;
|
|
reg [31:0] _RAND_290;
|
|
reg [31:0] _RAND_291;
|
|
reg [31:0] _RAND_292;
|
|
reg [31:0] _RAND_293;
|
|
reg [31:0] _RAND_294;
|
|
reg [31:0] _RAND_295;
|
|
reg [31:0] _RAND_296;
|
|
reg [31:0] _RAND_297;
|
|
reg [31:0] _RAND_298;
|
|
reg [31:0] _RAND_299;
|
|
reg [31:0] _RAND_300;
|
|
reg [31:0] _RAND_301;
|
|
reg [31:0] _RAND_302;
|
|
reg [31:0] _RAND_303;
|
|
reg [31:0] _RAND_304;
|
|
reg [31:0] _RAND_305;
|
|
reg [31:0] _RAND_306;
|
|
reg [31:0] _RAND_307;
|
|
reg [31:0] _RAND_308;
|
|
reg [31:0] _RAND_309;
|
|
reg [31:0] _RAND_310;
|
|
reg [31:0] _RAND_311;
|
|
reg [31:0] _RAND_312;
|
|
reg [31:0] _RAND_313;
|
|
reg [31:0] _RAND_314;
|
|
reg [31:0] _RAND_315;
|
|
reg [31:0] _RAND_316;
|
|
reg [31:0] _RAND_317;
|
|
reg [31:0] _RAND_318;
|
|
reg [31:0] _RAND_319;
|
|
reg [31:0] _RAND_320;
|
|
reg [31:0] _RAND_321;
|
|
reg [31:0] _RAND_322;
|
|
reg [31:0] _RAND_323;
|
|
reg [31:0] _RAND_324;
|
|
reg [31:0] _RAND_325;
|
|
reg [31:0] _RAND_326;
|
|
reg [31:0] _RAND_327;
|
|
reg [31:0] _RAND_328;
|
|
reg [31:0] _RAND_329;
|
|
reg [31:0] _RAND_330;
|
|
reg [31:0] _RAND_331;
|
|
reg [31:0] _RAND_332;
|
|
reg [31:0] _RAND_333;
|
|
reg [31:0] _RAND_334;
|
|
reg [31:0] _RAND_335;
|
|
reg [31:0] _RAND_336;
|
|
reg [31:0] _RAND_337;
|
|
reg [31:0] _RAND_338;
|
|
reg [31:0] _RAND_339;
|
|
reg [31:0] _RAND_340;
|
|
reg [31:0] _RAND_341;
|
|
reg [31:0] _RAND_342;
|
|
reg [31:0] _RAND_343;
|
|
reg [31:0] _RAND_344;
|
|
reg [31:0] _RAND_345;
|
|
reg [31:0] _RAND_346;
|
|
reg [31:0] _RAND_347;
|
|
reg [31:0] _RAND_348;
|
|
reg [31:0] _RAND_349;
|
|
reg [31:0] _RAND_350;
|
|
reg [31:0] _RAND_351;
|
|
reg [31:0] _RAND_352;
|
|
reg [31:0] _RAND_353;
|
|
reg [31:0] _RAND_354;
|
|
reg [31:0] _RAND_355;
|
|
reg [31:0] _RAND_356;
|
|
reg [31:0] _RAND_357;
|
|
reg [31:0] _RAND_358;
|
|
reg [31:0] _RAND_359;
|
|
reg [31:0] _RAND_360;
|
|
reg [31:0] _RAND_361;
|
|
reg [31:0] _RAND_362;
|
|
reg [31:0] _RAND_363;
|
|
reg [31:0] _RAND_364;
|
|
reg [31:0] _RAND_365;
|
|
reg [31:0] _RAND_366;
|
|
reg [31:0] _RAND_367;
|
|
reg [31:0] _RAND_368;
|
|
reg [31:0] _RAND_369;
|
|
reg [31:0] _RAND_370;
|
|
reg [31:0] _RAND_371;
|
|
reg [31:0] _RAND_372;
|
|
reg [31:0] _RAND_373;
|
|
reg [31:0] _RAND_374;
|
|
reg [31:0] _RAND_375;
|
|
reg [31:0] _RAND_376;
|
|
reg [31:0] _RAND_377;
|
|
reg [31:0] _RAND_378;
|
|
reg [31:0] _RAND_379;
|
|
reg [31:0] _RAND_380;
|
|
reg [31:0] _RAND_381;
|
|
reg [31:0] _RAND_382;
|
|
reg [31:0] _RAND_383;
|
|
reg [31:0] _RAND_384;
|
|
reg [31:0] _RAND_385;
|
|
reg [31:0] _RAND_386;
|
|
reg [31:0] _RAND_387;
|
|
reg [31:0] _RAND_388;
|
|
reg [31:0] _RAND_389;
|
|
reg [31:0] _RAND_390;
|
|
reg [31:0] _RAND_391;
|
|
reg [31:0] _RAND_392;
|
|
reg [31:0] _RAND_393;
|
|
reg [31:0] _RAND_394;
|
|
reg [31:0] _RAND_395;
|
|
reg [31:0] _RAND_396;
|
|
reg [31:0] _RAND_397;
|
|
reg [31:0] _RAND_398;
|
|
reg [31:0] _RAND_399;
|
|
reg [31:0] _RAND_400;
|
|
reg [31:0] _RAND_401;
|
|
reg [31:0] _RAND_402;
|
|
reg [31:0] _RAND_403;
|
|
reg [31:0] _RAND_404;
|
|
reg [31:0] _RAND_405;
|
|
reg [31:0] _RAND_406;
|
|
reg [31:0] _RAND_407;
|
|
reg [31:0] _RAND_408;
|
|
reg [31:0] _RAND_409;
|
|
reg [31:0] _RAND_410;
|
|
reg [31:0] _RAND_411;
|
|
reg [31:0] _RAND_412;
|
|
reg [31:0] _RAND_413;
|
|
reg [31:0] _RAND_414;
|
|
reg [31:0] _RAND_415;
|
|
reg [31:0] _RAND_416;
|
|
reg [31:0] _RAND_417;
|
|
reg [31:0] _RAND_418;
|
|
reg [31:0] _RAND_419;
|
|
reg [31:0] _RAND_420;
|
|
reg [31:0] _RAND_421;
|
|
reg [31:0] _RAND_422;
|
|
reg [31:0] _RAND_423;
|
|
reg [31:0] _RAND_424;
|
|
reg [31:0] _RAND_425;
|
|
reg [31:0] _RAND_426;
|
|
reg [31:0] _RAND_427;
|
|
reg [31:0] _RAND_428;
|
|
reg [31:0] _RAND_429;
|
|
reg [31:0] _RAND_430;
|
|
reg [31:0] _RAND_431;
|
|
reg [31:0] _RAND_432;
|
|
reg [31:0] _RAND_433;
|
|
reg [31:0] _RAND_434;
|
|
reg [31:0] _RAND_435;
|
|
reg [31:0] _RAND_436;
|
|
reg [31:0] _RAND_437;
|
|
reg [31:0] _RAND_438;
|
|
reg [31:0] _RAND_439;
|
|
reg [31:0] _RAND_440;
|
|
reg [31:0] _RAND_441;
|
|
reg [31:0] _RAND_442;
|
|
reg [31:0] _RAND_443;
|
|
reg [31:0] _RAND_444;
|
|
reg [31:0] _RAND_445;
|
|
reg [31:0] _RAND_446;
|
|
reg [31:0] _RAND_447;
|
|
reg [31:0] _RAND_448;
|
|
reg [31:0] _RAND_449;
|
|
reg [31:0] _RAND_450;
|
|
reg [31:0] _RAND_451;
|
|
reg [31:0] _RAND_452;
|
|
reg [31:0] _RAND_453;
|
|
reg [31:0] _RAND_454;
|
|
reg [31:0] _RAND_455;
|
|
reg [31:0] _RAND_456;
|
|
reg [31:0] _RAND_457;
|
|
reg [31:0] _RAND_458;
|
|
reg [31:0] _RAND_459;
|
|
reg [31:0] _RAND_460;
|
|
reg [31:0] _RAND_461;
|
|
reg [31:0] _RAND_462;
|
|
reg [31:0] _RAND_463;
|
|
reg [31:0] _RAND_464;
|
|
reg [31:0] _RAND_465;
|
|
reg [31:0] _RAND_466;
|
|
reg [31:0] _RAND_467;
|
|
reg [31:0] _RAND_468;
|
|
reg [31:0] _RAND_469;
|
|
reg [31:0] _RAND_470;
|
|
reg [31:0] _RAND_471;
|
|
reg [31:0] _RAND_472;
|
|
reg [31:0] _RAND_473;
|
|
reg [31:0] _RAND_474;
|
|
reg [31:0] _RAND_475;
|
|
reg [31:0] _RAND_476;
|
|
reg [31:0] _RAND_477;
|
|
reg [31:0] _RAND_478;
|
|
reg [31:0] _RAND_479;
|
|
reg [31:0] _RAND_480;
|
|
reg [31:0] _RAND_481;
|
|
reg [31:0] _RAND_482;
|
|
reg [31:0] _RAND_483;
|
|
reg [31:0] _RAND_484;
|
|
reg [31:0] _RAND_485;
|
|
reg [31:0] _RAND_486;
|
|
reg [31:0] _RAND_487;
|
|
reg [31:0] _RAND_488;
|
|
reg [31:0] _RAND_489;
|
|
reg [31:0] _RAND_490;
|
|
reg [31:0] _RAND_491;
|
|
reg [31:0] _RAND_492;
|
|
reg [31:0] _RAND_493;
|
|
reg [31:0] _RAND_494;
|
|
reg [31:0] _RAND_495;
|
|
reg [31:0] _RAND_496;
|
|
reg [31:0] _RAND_497;
|
|
reg [31:0] _RAND_498;
|
|
reg [31:0] _RAND_499;
|
|
reg [31:0] _RAND_500;
|
|
reg [31:0] _RAND_501;
|
|
reg [31:0] _RAND_502;
|
|
reg [31:0] _RAND_503;
|
|
reg [31:0] _RAND_504;
|
|
reg [31:0] _RAND_505;
|
|
reg [31:0] _RAND_506;
|
|
reg [31:0] _RAND_507;
|
|
reg [31:0] _RAND_508;
|
|
reg [31:0] _RAND_509;
|
|
reg [31:0] _RAND_510;
|
|
reg [31:0] _RAND_511;
|
|
reg [31:0] _RAND_512;
|
|
reg [31:0] _RAND_513;
|
|
reg [31:0] _RAND_514;
|
|
reg [31:0] _RAND_515;
|
|
reg [31:0] _RAND_516;
|
|
reg [31:0] _RAND_517;
|
|
reg [31:0] _RAND_518;
|
|
reg [31:0] _RAND_519;
|
|
reg [31:0] _RAND_520;
|
|
reg [31:0] _RAND_521;
|
|
reg [31:0] _RAND_522;
|
|
reg [31:0] _RAND_523;
|
|
reg [31:0] _RAND_524;
|
|
reg [31:0] _RAND_525;
|
|
reg [31:0] _RAND_526;
|
|
reg [31:0] _RAND_527;
|
|
reg [31:0] _RAND_528;
|
|
reg [31:0] _RAND_529;
|
|
reg [31:0] _RAND_530;
|
|
reg [31:0] _RAND_531;
|
|
reg [31:0] _RAND_532;
|
|
reg [31:0] _RAND_533;
|
|
reg [31:0] _RAND_534;
|
|
reg [31:0] _RAND_535;
|
|
reg [31:0] _RAND_536;
|
|
reg [31:0] _RAND_537;
|
|
reg [31:0] _RAND_538;
|
|
reg [31:0] _RAND_539;
|
|
reg [31:0] _RAND_540;
|
|
reg [31:0] _RAND_541;
|
|
reg [31:0] _RAND_542;
|
|
reg [31:0] _RAND_543;
|
|
reg [31:0] _RAND_544;
|
|
reg [31:0] _RAND_545;
|
|
reg [31:0] _RAND_546;
|
|
reg [31:0] _RAND_547;
|
|
reg [31:0] _RAND_548;
|
|
reg [31:0] _RAND_549;
|
|
reg [31:0] _RAND_550;
|
|
reg [31:0] _RAND_551;
|
|
reg [31:0] _RAND_552;
|
|
reg [31:0] _RAND_553;
|
|
reg [31:0] _RAND_554;
|
|
reg [31:0] _RAND_555;
|
|
reg [31:0] _RAND_556;
|
|
reg [31:0] _RAND_557;
|
|
reg [31:0] _RAND_558;
|
|
reg [31:0] _RAND_559;
|
|
reg [31:0] _RAND_560;
|
|
reg [31:0] _RAND_561;
|
|
reg [31:0] _RAND_562;
|
|
reg [31:0] _RAND_563;
|
|
reg [31:0] _RAND_564;
|
|
reg [31:0] _RAND_565;
|
|
reg [31:0] _RAND_566;
|
|
reg [31:0] _RAND_567;
|
|
reg [31:0] _RAND_568;
|
|
reg [31:0] _RAND_569;
|
|
reg [31:0] _RAND_570;
|
|
reg [31:0] _RAND_571;
|
|
reg [31:0] _RAND_572;
|
|
reg [31:0] _RAND_573;
|
|
reg [31:0] _RAND_574;
|
|
reg [31:0] _RAND_575;
|
|
reg [31:0] _RAND_576;
|
|
reg [31:0] _RAND_577;
|
|
reg [31:0] _RAND_578;
|
|
reg [31:0] _RAND_579;
|
|
reg [31:0] _RAND_580;
|
|
reg [31:0] _RAND_581;
|
|
reg [31:0] _RAND_582;
|
|
reg [31:0] _RAND_583;
|
|
reg [31:0] _RAND_584;
|
|
reg [31:0] _RAND_585;
|
|
reg [31:0] _RAND_586;
|
|
reg [31:0] _RAND_587;
|
|
reg [31:0] _RAND_588;
|
|
reg [31:0] _RAND_589;
|
|
reg [31:0] _RAND_590;
|
|
reg [31:0] _RAND_591;
|
|
reg [31:0] _RAND_592;
|
|
reg [31:0] _RAND_593;
|
|
reg [31:0] _RAND_594;
|
|
reg [31:0] _RAND_595;
|
|
reg [31:0] _RAND_596;
|
|
reg [31:0] _RAND_597;
|
|
reg [31:0] _RAND_598;
|
|
reg [31:0] _RAND_599;
|
|
reg [31:0] _RAND_600;
|
|
reg [31:0] _RAND_601;
|
|
reg [31:0] _RAND_602;
|
|
reg [31:0] _RAND_603;
|
|
reg [31:0] _RAND_604;
|
|
reg [31:0] _RAND_605;
|
|
reg [31:0] _RAND_606;
|
|
reg [31:0] _RAND_607;
|
|
reg [31:0] _RAND_608;
|
|
reg [31:0] _RAND_609;
|
|
reg [31:0] _RAND_610;
|
|
reg [31:0] _RAND_611;
|
|
reg [31:0] _RAND_612;
|
|
reg [31:0] _RAND_613;
|
|
reg [31:0] _RAND_614;
|
|
reg [31:0] _RAND_615;
|
|
reg [31:0] _RAND_616;
|
|
reg [31:0] _RAND_617;
|
|
reg [31:0] _RAND_618;
|
|
reg [31:0] _RAND_619;
|
|
reg [31:0] _RAND_620;
|
|
reg [31:0] _RAND_621;
|
|
reg [31:0] _RAND_622;
|
|
reg [31:0] _RAND_623;
|
|
reg [31:0] _RAND_624;
|
|
reg [31:0] _RAND_625;
|
|
reg [31:0] _RAND_626;
|
|
reg [31:0] _RAND_627;
|
|
reg [31:0] _RAND_628;
|
|
reg [31:0] _RAND_629;
|
|
reg [31:0] _RAND_630;
|
|
reg [31:0] _RAND_631;
|
|
reg [31:0] _RAND_632;
|
|
reg [31:0] _RAND_633;
|
|
reg [31:0] _RAND_634;
|
|
reg [31:0] _RAND_635;
|
|
reg [31:0] _RAND_636;
|
|
reg [31:0] _RAND_637;
|
|
reg [31:0] _RAND_638;
|
|
reg [31:0] _RAND_639;
|
|
reg [31:0] _RAND_640;
|
|
reg [31:0] _RAND_641;
|
|
reg [31:0] _RAND_642;
|
|
reg [31:0] _RAND_643;
|
|
reg [31:0] _RAND_644;
|
|
reg [31:0] _RAND_645;
|
|
reg [31:0] _RAND_646;
|
|
reg [31:0] _RAND_647;
|
|
reg [31:0] _RAND_648;
|
|
reg [31:0] _RAND_649;
|
|
reg [31:0] _RAND_650;
|
|
reg [31:0] _RAND_651;
|
|
reg [31:0] _RAND_652;
|
|
reg [31:0] _RAND_653;
|
|
reg [31:0] _RAND_654;
|
|
reg [31:0] _RAND_655;
|
|
reg [31:0] _RAND_656;
|
|
reg [31:0] _RAND_657;
|
|
reg [31:0] _RAND_658;
|
|
reg [31:0] _RAND_659;
|
|
reg [31:0] _RAND_660;
|
|
reg [31:0] _RAND_661;
|
|
reg [31:0] _RAND_662;
|
|
reg [31:0] _RAND_663;
|
|
reg [31:0] _RAND_664;
|
|
reg [31:0] _RAND_665;
|
|
reg [31:0] _RAND_666;
|
|
reg [31:0] _RAND_667;
|
|
reg [31:0] _RAND_668;
|
|
reg [31:0] _RAND_669;
|
|
reg [31:0] _RAND_670;
|
|
reg [31:0] _RAND_671;
|
|
reg [31:0] _RAND_672;
|
|
reg [31:0] _RAND_673;
|
|
reg [31:0] _RAND_674;
|
|
reg [31:0] _RAND_675;
|
|
reg [31:0] _RAND_676;
|
|
reg [31:0] _RAND_677;
|
|
reg [31:0] _RAND_678;
|
|
reg [31:0] _RAND_679;
|
|
reg [31:0] _RAND_680;
|
|
reg [31:0] _RAND_681;
|
|
reg [31:0] _RAND_682;
|
|
reg [31:0] _RAND_683;
|
|
reg [31:0] _RAND_684;
|
|
reg [31:0] _RAND_685;
|
|
reg [31:0] _RAND_686;
|
|
reg [31:0] _RAND_687;
|
|
reg [31:0] _RAND_688;
|
|
reg [31:0] _RAND_689;
|
|
reg [31:0] _RAND_690;
|
|
reg [31:0] _RAND_691;
|
|
reg [31:0] _RAND_692;
|
|
reg [31:0] _RAND_693;
|
|
reg [31:0] _RAND_694;
|
|
reg [31:0] _RAND_695;
|
|
reg [31:0] _RAND_696;
|
|
reg [31:0] _RAND_697;
|
|
reg [31:0] _RAND_698;
|
|
reg [31:0] _RAND_699;
|
|
reg [31:0] _RAND_700;
|
|
reg [31:0] _RAND_701;
|
|
reg [31:0] _RAND_702;
|
|
reg [31:0] _RAND_703;
|
|
reg [31:0] _RAND_704;
|
|
reg [31:0] _RAND_705;
|
|
reg [31:0] _RAND_706;
|
|
reg [31:0] _RAND_707;
|
|
reg [31:0] _RAND_708;
|
|
reg [31:0] _RAND_709;
|
|
reg [31:0] _RAND_710;
|
|
reg [31:0] _RAND_711;
|
|
reg [31:0] _RAND_712;
|
|
reg [31:0] _RAND_713;
|
|
reg [31:0] _RAND_714;
|
|
reg [31:0] _RAND_715;
|
|
reg [31:0] _RAND_716;
|
|
reg [31:0] _RAND_717;
|
|
reg [31:0] _RAND_718;
|
|
reg [31:0] _RAND_719;
|
|
reg [31:0] _RAND_720;
|
|
reg [31:0] _RAND_721;
|
|
reg [31:0] _RAND_722;
|
|
reg [31:0] _RAND_723;
|
|
reg [31:0] _RAND_724;
|
|
reg [31:0] _RAND_725;
|
|
reg [31:0] _RAND_726;
|
|
reg [31:0] _RAND_727;
|
|
reg [31:0] _RAND_728;
|
|
reg [31:0] _RAND_729;
|
|
reg [31:0] _RAND_730;
|
|
reg [31:0] _RAND_731;
|
|
reg [31:0] _RAND_732;
|
|
reg [31:0] _RAND_733;
|
|
reg [31:0] _RAND_734;
|
|
reg [31:0] _RAND_735;
|
|
reg [31:0] _RAND_736;
|
|
reg [31:0] _RAND_737;
|
|
reg [31:0] _RAND_738;
|
|
reg [31:0] _RAND_739;
|
|
reg [31:0] _RAND_740;
|
|
reg [31:0] _RAND_741;
|
|
reg [31:0] _RAND_742;
|
|
reg [31:0] _RAND_743;
|
|
reg [31:0] _RAND_744;
|
|
reg [31:0] _RAND_745;
|
|
reg [31:0] _RAND_746;
|
|
reg [31:0] _RAND_747;
|
|
reg [31:0] _RAND_748;
|
|
reg [31:0] _RAND_749;
|
|
reg [31:0] _RAND_750;
|
|
reg [31:0] _RAND_751;
|
|
reg [31:0] _RAND_752;
|
|
reg [31:0] _RAND_753;
|
|
reg [31:0] _RAND_754;
|
|
reg [31:0] _RAND_755;
|
|
reg [31:0] _RAND_756;
|
|
reg [31:0] _RAND_757;
|
|
reg [31:0] _RAND_758;
|
|
reg [31:0] _RAND_759;
|
|
reg [31:0] _RAND_760;
|
|
reg [31:0] _RAND_761;
|
|
reg [31:0] _RAND_762;
|
|
reg [31:0] _RAND_763;
|
|
reg [31:0] _RAND_764;
|
|
reg [31:0] _RAND_765;
|
|
reg [31:0] _RAND_766;
|
|
reg [31:0] _RAND_767;
|
|
reg [31:0] _RAND_768;
|
|
reg [31:0] _RAND_769;
|
|
reg [31:0] _RAND_770;
|
|
reg [31:0] _RAND_771;
|
|
reg [31:0] _RAND_772;
|
|
reg [31:0] _RAND_773;
|
|
reg [31:0] _RAND_774;
|
|
reg [31:0] _RAND_775;
|
|
reg [31:0] _RAND_776;
|
|
reg [31:0] _RAND_777;
|
|
reg [31:0] _RAND_778;
|
|
reg [31:0] _RAND_779;
|
|
reg [31:0] _RAND_780;
|
|
reg [31:0] _RAND_781;
|
|
reg [31:0] _RAND_782;
|
|
reg [31:0] _RAND_783;
|
|
reg [31:0] _RAND_784;
|
|
reg [31:0] _RAND_785;
|
|
reg [31:0] _RAND_786;
|
|
reg [31:0] _RAND_787;
|
|
reg [31:0] _RAND_788;
|
|
reg [31:0] _RAND_789;
|
|
reg [31:0] _RAND_790;
|
|
reg [31:0] _RAND_791;
|
|
reg [31:0] _RAND_792;
|
|
reg [31:0] _RAND_793;
|
|
reg [31:0] _RAND_794;
|
|
reg [31:0] _RAND_795;
|
|
reg [31:0] _RAND_796;
|
|
reg [31:0] _RAND_797;
|
|
reg [31:0] _RAND_798;
|
|
reg [31:0] _RAND_799;
|
|
reg [31:0] _RAND_800;
|
|
reg [31:0] _RAND_801;
|
|
reg [31:0] _RAND_802;
|
|
reg [31:0] _RAND_803;
|
|
reg [31:0] _RAND_804;
|
|
reg [31:0] _RAND_805;
|
|
reg [31:0] _RAND_806;
|
|
reg [31:0] _RAND_807;
|
|
reg [31:0] _RAND_808;
|
|
reg [31:0] _RAND_809;
|
|
reg [31:0] _RAND_810;
|
|
reg [31:0] _RAND_811;
|
|
reg [31:0] _RAND_812;
|
|
reg [31:0] _RAND_813;
|
|
reg [31:0] _RAND_814;
|
|
reg [31:0] _RAND_815;
|
|
reg [31:0] _RAND_816;
|
|
reg [31:0] _RAND_817;
|
|
reg [31:0] _RAND_818;
|
|
reg [31:0] _RAND_819;
|
|
reg [31:0] _RAND_820;
|
|
reg [31:0] _RAND_821;
|
|
reg [31:0] _RAND_822;
|
|
reg [31:0] _RAND_823;
|
|
reg [31:0] _RAND_824;
|
|
reg [31:0] _RAND_825;
|
|
reg [31:0] _RAND_826;
|
|
reg [31:0] _RAND_827;
|
|
reg [31:0] _RAND_828;
|
|
reg [31:0] _RAND_829;
|
|
reg [31:0] _RAND_830;
|
|
reg [31:0] _RAND_831;
|
|
reg [31:0] _RAND_832;
|
|
reg [31:0] _RAND_833;
|
|
reg [31:0] _RAND_834;
|
|
reg [31:0] _RAND_835;
|
|
reg [31:0] _RAND_836;
|
|
reg [31:0] _RAND_837;
|
|
reg [31:0] _RAND_838;
|
|
reg [31:0] _RAND_839;
|
|
reg [31:0] _RAND_840;
|
|
reg [31:0] _RAND_841;
|
|
reg [31:0] _RAND_842;
|
|
reg [31:0] _RAND_843;
|
|
reg [31:0] _RAND_844;
|
|
reg [31:0] _RAND_845;
|
|
reg [31:0] _RAND_846;
|
|
reg [31:0] _RAND_847;
|
|
reg [31:0] _RAND_848;
|
|
reg [31:0] _RAND_849;
|
|
reg [31:0] _RAND_850;
|
|
reg [31:0] _RAND_851;
|
|
reg [31:0] _RAND_852;
|
|
reg [31:0] _RAND_853;
|
|
reg [31:0] _RAND_854;
|
|
reg [31:0] _RAND_855;
|
|
reg [31:0] _RAND_856;
|
|
reg [31:0] _RAND_857;
|
|
reg [31:0] _RAND_858;
|
|
reg [31:0] _RAND_859;
|
|
reg [31:0] _RAND_860;
|
|
reg [31:0] _RAND_861;
|
|
reg [31:0] _RAND_862;
|
|
reg [31:0] _RAND_863;
|
|
reg [31:0] _RAND_864;
|
|
reg [31:0] _RAND_865;
|
|
reg [31:0] _RAND_866;
|
|
reg [31:0] _RAND_867;
|
|
reg [31:0] _RAND_868;
|
|
reg [31:0] _RAND_869;
|
|
reg [31:0] _RAND_870;
|
|
reg [31:0] _RAND_871;
|
|
reg [31:0] _RAND_872;
|
|
reg [31:0] _RAND_873;
|
|
reg [31:0] _RAND_874;
|
|
reg [31:0] _RAND_875;
|
|
reg [31:0] _RAND_876;
|
|
reg [31:0] _RAND_877;
|
|
reg [31:0] _RAND_878;
|
|
reg [31:0] _RAND_879;
|
|
reg [31:0] _RAND_880;
|
|
reg [31:0] _RAND_881;
|
|
reg [31:0] _RAND_882;
|
|
reg [31:0] _RAND_883;
|
|
reg [31:0] _RAND_884;
|
|
reg [31:0] _RAND_885;
|
|
reg [31:0] _RAND_886;
|
|
reg [31:0] _RAND_887;
|
|
reg [31:0] _RAND_888;
|
|
reg [31:0] _RAND_889;
|
|
reg [31:0] _RAND_890;
|
|
reg [31:0] _RAND_891;
|
|
reg [31:0] _RAND_892;
|
|
reg [31:0] _RAND_893;
|
|
reg [31:0] _RAND_894;
|
|
reg [31:0] _RAND_895;
|
|
reg [31:0] _RAND_896;
|
|
reg [31:0] _RAND_897;
|
|
reg [31:0] _RAND_898;
|
|
reg [31:0] _RAND_899;
|
|
reg [31:0] _RAND_900;
|
|
reg [31:0] _RAND_901;
|
|
reg [31:0] _RAND_902;
|
|
reg [31:0] _RAND_903;
|
|
reg [31:0] _RAND_904;
|
|
reg [31:0] _RAND_905;
|
|
reg [31:0] _RAND_906;
|
|
reg [31:0] _RAND_907;
|
|
reg [31:0] _RAND_908;
|
|
reg [31:0] _RAND_909;
|
|
reg [31:0] _RAND_910;
|
|
reg [31:0] _RAND_911;
|
|
reg [31:0] _RAND_912;
|
|
reg [31:0] _RAND_913;
|
|
reg [31:0] _RAND_914;
|
|
reg [31:0] _RAND_915;
|
|
reg [31:0] _RAND_916;
|
|
reg [31:0] _RAND_917;
|
|
reg [31:0] _RAND_918;
|
|
reg [31:0] _RAND_919;
|
|
reg [31:0] _RAND_920;
|
|
reg [31:0] _RAND_921;
|
|
reg [31:0] _RAND_922;
|
|
reg [31:0] _RAND_923;
|
|
reg [31:0] _RAND_924;
|
|
reg [31:0] _RAND_925;
|
|
reg [31:0] _RAND_926;
|
|
reg [31:0] _RAND_927;
|
|
reg [31:0] _RAND_928;
|
|
reg [31:0] _RAND_929;
|
|
reg [31:0] _RAND_930;
|
|
reg [31:0] _RAND_931;
|
|
reg [31:0] _RAND_932;
|
|
reg [31:0] _RAND_933;
|
|
reg [31:0] _RAND_934;
|
|
reg [31:0] _RAND_935;
|
|
reg [31:0] _RAND_936;
|
|
reg [31:0] _RAND_937;
|
|
reg [31:0] _RAND_938;
|
|
reg [31:0] _RAND_939;
|
|
reg [31:0] _RAND_940;
|
|
reg [31:0] _RAND_941;
|
|
reg [31:0] _RAND_942;
|
|
reg [31:0] _RAND_943;
|
|
reg [31:0] _RAND_944;
|
|
reg [31:0] _RAND_945;
|
|
reg [31:0] _RAND_946;
|
|
reg [31:0] _RAND_947;
|
|
reg [31:0] _RAND_948;
|
|
reg [31:0] _RAND_949;
|
|
reg [31:0] _RAND_950;
|
|
reg [31:0] _RAND_951;
|
|
reg [31:0] _RAND_952;
|
|
reg [31:0] _RAND_953;
|
|
reg [31:0] _RAND_954;
|
|
reg [31:0] _RAND_955;
|
|
reg [31:0] _RAND_956;
|
|
reg [31:0] _RAND_957;
|
|
reg [31:0] _RAND_958;
|
|
reg [31:0] _RAND_959;
|
|
reg [31:0] _RAND_960;
|
|
reg [31:0] _RAND_961;
|
|
reg [31:0] _RAND_962;
|
|
reg [31:0] _RAND_963;
|
|
reg [31:0] _RAND_964;
|
|
reg [31:0] _RAND_965;
|
|
reg [31:0] _RAND_966;
|
|
reg [31:0] _RAND_967;
|
|
reg [31:0] _RAND_968;
|
|
reg [31:0] _RAND_969;
|
|
reg [31:0] _RAND_970;
|
|
reg [31:0] _RAND_971;
|
|
reg [31:0] _RAND_972;
|
|
reg [31:0] _RAND_973;
|
|
reg [31:0] _RAND_974;
|
|
reg [31:0] _RAND_975;
|
|
reg [31:0] _RAND_976;
|
|
reg [31:0] _RAND_977;
|
|
reg [31:0] _RAND_978;
|
|
reg [31:0] _RAND_979;
|
|
reg [31:0] _RAND_980;
|
|
reg [31:0] _RAND_981;
|
|
reg [31:0] _RAND_982;
|
|
reg [31:0] _RAND_983;
|
|
reg [31:0] _RAND_984;
|
|
reg [31:0] _RAND_985;
|
|
reg [31:0] _RAND_986;
|
|
reg [31:0] _RAND_987;
|
|
reg [31:0] _RAND_988;
|
|
reg [31:0] _RAND_989;
|
|
reg [31:0] _RAND_990;
|
|
reg [31:0] _RAND_991;
|
|
reg [31:0] _RAND_992;
|
|
reg [31:0] _RAND_993;
|
|
reg [31:0] _RAND_994;
|
|
reg [31:0] _RAND_995;
|
|
reg [31:0] _RAND_996;
|
|
reg [31:0] _RAND_997;
|
|
reg [31:0] _RAND_998;
|
|
reg [31:0] _RAND_999;
|
|
reg [31:0] _RAND_1000;
|
|
reg [31:0] _RAND_1001;
|
|
reg [31:0] _RAND_1002;
|
|
reg [31:0] _RAND_1003;
|
|
reg [31:0] _RAND_1004;
|
|
reg [31:0] _RAND_1005;
|
|
reg [31:0] _RAND_1006;
|
|
reg [31:0] _RAND_1007;
|
|
reg [31:0] _RAND_1008;
|
|
reg [31:0] _RAND_1009;
|
|
reg [31:0] _RAND_1010;
|
|
reg [31:0] _RAND_1011;
|
|
reg [31:0] _RAND_1012;
|
|
reg [31:0] _RAND_1013;
|
|
reg [31:0] _RAND_1014;
|
|
reg [31:0] _RAND_1015;
|
|
reg [31:0] _RAND_1016;
|
|
reg [31:0] _RAND_1017;
|
|
reg [31:0] _RAND_1018;
|
|
reg [31:0] _RAND_1019;
|
|
reg [31:0] _RAND_1020;
|
|
reg [31:0] _RAND_1021;
|
|
reg [31:0] _RAND_1022;
|
|
reg [31:0] _RAND_1023;
|
|
reg [31:0] _RAND_1024;
|
|
reg [31:0] _RAND_1025;
|
|
reg [31:0] _RAND_1026;
|
|
reg [31:0] _RAND_1027;
|
|
reg [31:0] _RAND_1028;
|
|
reg [255:0] _RAND_1029;
|
|
reg [31:0] _RAND_1030;
|
|
reg [31:0] _RAND_1031;
|
|
reg [31:0] _RAND_1032;
|
|
reg [31:0] _RAND_1033;
|
|
reg [31:0] _RAND_1034;
|
|
reg [31:0] _RAND_1035;
|
|
reg [31:0] _RAND_1036;
|
|
reg [31:0] _RAND_1037;
|
|
reg [31:0] _RAND_1038;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_31_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_31_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_31_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_31_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_32_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_32_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_32_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_32_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_33_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_33_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_33_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_33_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_34_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_34_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_34_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_34_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_35_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_35_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_35_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_35_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_36_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_36_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_36_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_36_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_37_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_37_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_37_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_37_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_38_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_38_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_38_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_38_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_39_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_39_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_39_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_39_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_40_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_40_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_40_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_40_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_41_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_41_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_41_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_41_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_42_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_42_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_42_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_42_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_43_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_43_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_43_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_43_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_44_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_44_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_44_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_44_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_45_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_45_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_45_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_45_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_46_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_46_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_46_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_46_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_47_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_47_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_47_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_47_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_48_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_48_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_48_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_48_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_49_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_49_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_49_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_49_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_50_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_50_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_50_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_50_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_51_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_51_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_51_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_51_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_52_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_52_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_52_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_52_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_53_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_53_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_53_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_53_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_54_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_54_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_54_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_54_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_55_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_55_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_55_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_55_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_56_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_56_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_56_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_56_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_57_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_57_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_57_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_57_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_58_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_58_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_58_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_58_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_59_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_59_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_59_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_59_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_60_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_60_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_60_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_60_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_61_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_61_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_61_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_61_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_62_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_62_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_62_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_62_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_63_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_63_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_63_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_63_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_64_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_64_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_64_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_64_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_65_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_65_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_65_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_65_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_66_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_66_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_66_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_66_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_67_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_67_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_67_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_67_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_68_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_68_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_68_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_68_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_69_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_69_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_69_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_69_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_70_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_70_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_70_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_70_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_71_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_71_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_71_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_71_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_72_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_72_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_72_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_72_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_73_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_73_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_73_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_73_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_74_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_74_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_74_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_74_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_75_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_75_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_75_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_75_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_76_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_76_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_76_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_76_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_77_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_77_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_77_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_77_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_78_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_78_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_78_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_78_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_79_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_79_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_79_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_79_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_80_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_80_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_80_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_80_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_81_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_81_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_81_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_81_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_82_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_82_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_82_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_82_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_83_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_83_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_83_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_83_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_84_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_84_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_84_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_84_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_85_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_85_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_85_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_85_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_86_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_86_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_86_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_86_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_87_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_87_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_87_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_87_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_88_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_88_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_88_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_88_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_89_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_89_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_89_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_89_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_90_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_90_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_90_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_90_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_91_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_91_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_91_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_91_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_92_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_92_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_92_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_92_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_93_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_93_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_93_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_93_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_94_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_94_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_94_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_94_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_95_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_95_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_95_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_95_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_96_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_96_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_96_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_96_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_97_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_97_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_97_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_97_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_98_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_98_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_98_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_98_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_99_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_99_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_99_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_99_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_100_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_100_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_100_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_100_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_101_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_101_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_101_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_101_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_102_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_102_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_102_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_102_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_103_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_103_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_103_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_103_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_104_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_104_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_104_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_104_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_105_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_105_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_105_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_105_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_106_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_106_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_106_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_106_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_107_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_107_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_107_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_107_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_108_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_108_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_108_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_108_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_109_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_109_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_109_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_109_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_110_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_110_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_110_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_110_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_111_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_111_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_111_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_111_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_112_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_112_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_112_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_112_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_113_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_113_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_113_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_113_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_114_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_114_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_114_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_114_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_115_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_115_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_115_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_115_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_116_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_116_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_116_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_116_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_117_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_117_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_117_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_117_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_118_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_118_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_118_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_118_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_119_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_119_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_119_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_119_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_120_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_120_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_120_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_120_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_121_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_121_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_121_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_121_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_122_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_122_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_122_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_122_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_123_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_123_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_123_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_123_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_124_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_124_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_124_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_124_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_125_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_125_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_125_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_125_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_126_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_126_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_126_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_126_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_127_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_127_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_127_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_127_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_128_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_128_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_128_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_128_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_129_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_129_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_129_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_129_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_130_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_130_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_130_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_130_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_131_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_131_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_131_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_131_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_132_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_132_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_132_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_132_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_133_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_133_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_133_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_133_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_134_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_134_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_134_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_134_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_135_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_135_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_135_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_135_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_136_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_136_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_136_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_136_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_137_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_137_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_137_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_137_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_138_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_138_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_138_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_138_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_139_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_139_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_139_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_139_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_140_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_140_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_140_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_140_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_141_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_141_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_141_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_141_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_142_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_142_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_142_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_142_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_143_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_143_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_143_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_143_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_144_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_144_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_144_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_144_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_145_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_145_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_145_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_145_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_146_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_146_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_146_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_146_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_147_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_147_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_147_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_147_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_148_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_148_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_148_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_148_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_149_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_149_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_149_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_149_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_150_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_150_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_150_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_150_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_151_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_151_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_151_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_151_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_152_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_152_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_152_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_152_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_153_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_153_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_153_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_153_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_154_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_154_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_154_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_154_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_155_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_155_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_155_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_155_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_156_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_156_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_156_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_156_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_157_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_157_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_157_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_157_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_158_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_158_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_158_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_158_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_159_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_159_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_159_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_159_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_160_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_160_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_160_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_160_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_161_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_161_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_161_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_161_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_162_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_162_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_162_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_162_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_163_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_163_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_163_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_163_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_164_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_164_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_164_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_164_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_165_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_165_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_165_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_165_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_166_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_166_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_166_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_166_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_167_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_167_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_167_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_167_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_168_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_168_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_168_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_168_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_169_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_169_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_169_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_169_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_170_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_170_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_170_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_170_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_171_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_171_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_171_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_171_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_172_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_172_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_172_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_172_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_173_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_173_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_173_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_173_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_174_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_174_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_174_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_174_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_175_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_175_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_175_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_175_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_176_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_176_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_176_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_176_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_177_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_177_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_177_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_177_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_178_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_178_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_178_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_178_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_179_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_179_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_179_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_179_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_180_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_180_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_180_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_180_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_181_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_181_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_181_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_181_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_182_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_182_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_182_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_182_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_183_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_183_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_183_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_183_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_184_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_184_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_184_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_184_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_185_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_185_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_185_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_185_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_186_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_186_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_186_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_186_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_187_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_187_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_187_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_187_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_188_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_188_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_188_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_188_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_189_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_189_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_189_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_189_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_190_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_190_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_190_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_190_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_191_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_191_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_191_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_191_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_192_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_192_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_192_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_192_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_193_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_193_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_193_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_193_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_194_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_194_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_194_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_194_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_195_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_195_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_195_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_195_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_196_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_196_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_196_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_196_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_197_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_197_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_197_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_197_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_198_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_198_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_198_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_198_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_199_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_199_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_199_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_199_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_200_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_200_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_200_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_200_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_201_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_201_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_201_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_201_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_202_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_202_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_202_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_202_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_203_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_203_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_203_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_203_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_204_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_204_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_204_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_204_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_205_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_205_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_205_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_205_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_206_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_206_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_206_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_206_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_207_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_207_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_207_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_207_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_208_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_208_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_208_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_208_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_209_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_209_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_209_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_209_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_210_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_210_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_210_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_210_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_211_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_211_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_211_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_211_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_212_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_212_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_212_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_212_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_213_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_213_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_213_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_213_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_214_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_214_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_214_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_214_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_215_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_215_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_215_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_215_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_216_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_216_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_216_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_216_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_217_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_217_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_217_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_217_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_218_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_218_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_218_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_218_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_219_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_219_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_219_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_219_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_220_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_220_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_220_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_220_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_221_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_221_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_221_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_221_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_222_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_222_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_222_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_222_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_223_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_223_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_223_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_223_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_224_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_224_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_224_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_224_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_225_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_225_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_225_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_225_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_226_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_226_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_226_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_226_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_227_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_227_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_227_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_227_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_228_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_228_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_228_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_228_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_229_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_229_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_229_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_229_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_230_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_230_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_230_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_230_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_231_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_231_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_231_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_231_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_232_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_232_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_232_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_232_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_233_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_233_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_233_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_233_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_234_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_234_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_234_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_234_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_235_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_235_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_235_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_235_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_236_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_236_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_236_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_236_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_237_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_237_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_237_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_237_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_238_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_238_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_238_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_238_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_239_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_239_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_239_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_239_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_240_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_240_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_240_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_240_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_241_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_241_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_241_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_241_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_242_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_242_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_242_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_242_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_243_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_243_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_243_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_243_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_244_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_244_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_244_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_244_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_245_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_245_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_245_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_245_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_246_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_246_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_246_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_246_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_247_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_247_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_247_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_247_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_248_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_248_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_248_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_248_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_249_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_249_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_249_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_249_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_250_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_250_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_250_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_250_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_251_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_251_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_251_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_251_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_252_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_252_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_252_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_252_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_253_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_253_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_253_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_253_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_254_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_254_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_254_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_254_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_255_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_255_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_255_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_255_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_256_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_256_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_256_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_256_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_257_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_257_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_257_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_257_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_258_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_258_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_258_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_258_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_259_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_259_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_259_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_259_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_260_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_260_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_260_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_260_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_261_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_261_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_261_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_261_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_262_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_262_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_262_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_262_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_263_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_263_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_263_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_263_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_264_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_264_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_264_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_264_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_265_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_265_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_265_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_265_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_266_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_266_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_266_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_266_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_267_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_267_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_267_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_267_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_268_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_268_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_268_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_268_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_269_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_269_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_269_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_269_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_270_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_270_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_270_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_270_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_271_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_271_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_271_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_271_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_272_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_272_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_272_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_272_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_273_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_273_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_273_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_273_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_274_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_274_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_274_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_274_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_275_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_275_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_275_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_275_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_276_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_276_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_276_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_276_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_277_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_277_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_277_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_277_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_278_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_278_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_278_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_278_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_279_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_279_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_279_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_279_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_280_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_280_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_280_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_280_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_281_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_281_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_281_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_281_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_282_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_282_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_282_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_282_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_283_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_283_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_283_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_283_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_284_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_284_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_284_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_284_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_285_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_285_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_285_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_285_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_286_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_286_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_286_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_286_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_287_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_287_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_287_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_287_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_288_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_288_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_288_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_288_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_289_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_289_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_289_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_289_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_290_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_290_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_290_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_290_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_291_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_291_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_291_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_291_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_292_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_292_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_292_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_292_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_293_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_293_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_293_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_293_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_294_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_294_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_294_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_294_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_295_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_295_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_295_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_295_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_296_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_296_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_296_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_296_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_297_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_297_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_297_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_297_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_298_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_298_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_298_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_298_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_299_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_299_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_299_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_299_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_300_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_300_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_300_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_300_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_301_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_301_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_301_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_301_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_302_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_302_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_302_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_302_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_303_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_303_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_303_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_303_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_304_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_304_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_304_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_304_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_305_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_305_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_305_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_305_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_306_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_306_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_306_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_306_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_307_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_307_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_307_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_307_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_308_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_308_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_308_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_308_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_309_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_309_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_309_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_309_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_310_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_310_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_310_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_310_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_311_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_311_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_311_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_311_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_312_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_312_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_312_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_312_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_313_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_313_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_313_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_313_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_314_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_314_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_314_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_314_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_315_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_315_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_315_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_315_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_316_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_316_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_316_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_316_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_317_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_317_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_317_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_317_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_318_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_318_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_318_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_318_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_319_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_319_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_319_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_319_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_320_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_320_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_320_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_320_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_321_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_321_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_321_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_321_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_322_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_322_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_322_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_322_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_323_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_323_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_323_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_323_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_324_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_324_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_324_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_324_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_325_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_325_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_325_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_325_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_326_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_326_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_326_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_326_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_327_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_327_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_327_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_327_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_328_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_328_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_328_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_328_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_329_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_329_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_329_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_329_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_330_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_330_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_330_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_330_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_331_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_331_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_331_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_331_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_332_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_332_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_332_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_332_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_333_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_333_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_333_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_333_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_334_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_334_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_334_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_334_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_335_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_335_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_335_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_335_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_336_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_336_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_336_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_336_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_337_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_337_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_337_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_337_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_338_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_338_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_338_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_338_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_339_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_339_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_339_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_339_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_340_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_340_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_340_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_340_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_341_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_341_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_341_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_341_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_342_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_342_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_342_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_342_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_343_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_343_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_343_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_343_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_344_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_344_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_344_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_344_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_345_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_345_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_345_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_345_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_346_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_346_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_346_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_346_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_347_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_347_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_347_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_347_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_348_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_348_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_348_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_348_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_349_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_349_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_349_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_349_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_350_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_350_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_350_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_350_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_351_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_351_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_351_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_351_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_352_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_352_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_352_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_352_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_353_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_353_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_353_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_353_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_354_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_354_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_354_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_354_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_355_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_355_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_355_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_355_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_356_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_356_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_356_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_356_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_357_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_357_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_357_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_357_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_358_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_358_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_358_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_358_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_359_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_359_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_359_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_359_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_360_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_360_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_360_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_360_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_361_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_361_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_361_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_361_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_362_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_362_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_362_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_362_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_363_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_363_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_363_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_363_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_364_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_364_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_364_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_364_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_365_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_365_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_365_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_365_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_366_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_366_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_366_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_366_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_367_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_367_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_367_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_367_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_368_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_368_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_368_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_368_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_369_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_369_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_369_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_369_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_370_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_370_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_370_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_370_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_371_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_371_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_371_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_371_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_372_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_372_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_372_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_372_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_373_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_373_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_373_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_373_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_374_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_374_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_374_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_374_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_375_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_375_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_375_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_375_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_376_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_376_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_376_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_376_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_377_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_377_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_377_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_377_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_378_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_378_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_378_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_378_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_379_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_379_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_379_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_379_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_380_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_380_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_380_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_380_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_381_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_381_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_381_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_381_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_382_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_382_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_382_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_382_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_383_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_383_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_383_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_383_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_384_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_384_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_384_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_384_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_385_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_385_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_385_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_385_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_386_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_386_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_386_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_386_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_387_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_387_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_387_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_387_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_388_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_388_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_388_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_388_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_389_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_389_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_389_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_389_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_390_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_390_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_390_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_390_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_391_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_391_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_391_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_391_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_392_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_392_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_392_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_392_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_393_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_393_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_393_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_393_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_394_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_394_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_394_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_394_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_395_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_395_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_395_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_395_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_396_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_396_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_396_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_396_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_397_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_397_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_397_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_397_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_398_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_398_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_398_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_398_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_399_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_399_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_399_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_399_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_400_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_400_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_400_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_400_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_401_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_401_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_401_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_401_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_402_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_402_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_402_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_402_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_403_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_403_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_403_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_403_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_404_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_404_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_404_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_404_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_405_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_405_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_405_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_405_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_406_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_406_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_406_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_406_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_407_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_407_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_407_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_407_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_408_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_408_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_408_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_408_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_409_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_409_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_409_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_409_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_410_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_410_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_410_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_410_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_411_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_411_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_411_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_411_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_412_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_412_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_412_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_412_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_413_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_413_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_413_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_413_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_414_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_414_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_414_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_414_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_415_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_415_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_415_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_415_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_416_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_416_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_416_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_416_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_417_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_417_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_417_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_417_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_418_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_418_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_418_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_418_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_419_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_419_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_419_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_419_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_420_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_420_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_420_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_420_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_421_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_421_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_421_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_421_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_422_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_422_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_422_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_422_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_423_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_423_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_423_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_423_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_424_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_424_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_424_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_424_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_425_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_425_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_425_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_425_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_426_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_426_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_426_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_426_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_427_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_427_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_427_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_427_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_428_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_428_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_428_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_428_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_429_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_429_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_429_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_429_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_430_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_430_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_430_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_430_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_431_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_431_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_431_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_431_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_432_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_432_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_432_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_432_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_433_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_433_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_433_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_433_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_434_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_434_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_434_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_434_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_435_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_435_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_435_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_435_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_436_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_436_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_436_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_436_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_437_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_437_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_437_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_437_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_438_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_438_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_438_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_438_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_439_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_439_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_439_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_439_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_440_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_440_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_440_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_440_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_441_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_441_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_441_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_441_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_442_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_442_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_442_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_442_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_443_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_443_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_443_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_443_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_444_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_444_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_444_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_444_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_445_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_445_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_445_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_445_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_446_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_446_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_446_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_446_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_447_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_447_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_447_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_447_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_448_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_448_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_448_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_448_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_449_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_449_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_449_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_449_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_450_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_450_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_450_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_450_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_451_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_451_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_451_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_451_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_452_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_452_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_452_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_452_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_453_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_453_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_453_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_453_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_454_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_454_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_454_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_454_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_455_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_455_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_455_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_455_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_456_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_456_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_456_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_456_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_457_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_457_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_457_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_457_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_458_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_458_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_458_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_458_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_459_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_459_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_459_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_459_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_460_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_460_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_460_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_460_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_461_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_461_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_461_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_461_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_462_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_462_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_462_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_462_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_463_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_463_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_463_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_463_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_464_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_464_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_464_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_464_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_465_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_465_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_465_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_465_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_466_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_466_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_466_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_466_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_467_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_467_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_467_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_467_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_468_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_468_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_468_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_468_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_469_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_469_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_469_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_469_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_470_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_470_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_470_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_470_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_471_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_471_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_471_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_471_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_472_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_472_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_472_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_472_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_473_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_473_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_473_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_473_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_474_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_474_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_474_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_474_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_475_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_475_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_475_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_475_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_476_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_476_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_476_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_476_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_477_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_477_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_477_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_477_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_478_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_478_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_478_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_478_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_479_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_479_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_479_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_479_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_480_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_480_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_480_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_480_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_481_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_481_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_481_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_481_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_482_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_482_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_482_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_482_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_483_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_483_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_483_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_483_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_484_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_484_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_484_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_484_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_485_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_485_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_485_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_485_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_486_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_486_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_486_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_486_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_487_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_487_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_487_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_487_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_488_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_488_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_488_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_488_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_489_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_489_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_489_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_489_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_490_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_490_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_490_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_490_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_491_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_491_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_491_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_491_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_492_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_492_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_492_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_492_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_493_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_493_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_493_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_493_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_494_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_494_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_494_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_494_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_495_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_495_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_495_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_495_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_496_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_496_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_496_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_496_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_497_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_497_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_497_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_497_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_498_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_498_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_498_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_498_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_499_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_499_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_499_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_499_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_500_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_500_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_500_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_500_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_501_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_501_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_501_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_501_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_502_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_502_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_502_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_502_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_503_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_503_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_503_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_503_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_504_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_504_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_504_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_504_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_505_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_505_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_505_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_505_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_506_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_506_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_506_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_506_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_507_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_507_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_507_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_507_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_508_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_508_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_508_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_508_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_509_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_509_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_509_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_509_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_510_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_510_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_510_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_510_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_511_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_511_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_511_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_511_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_512_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_512_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_512_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_512_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_513_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_513_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_513_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_513_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_514_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_514_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_514_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_514_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_515_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_515_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_515_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_515_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_516_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_516_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_516_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_516_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_517_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_517_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_517_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_517_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_518_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_518_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_518_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_518_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_519_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_519_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_519_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_519_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_520_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_520_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_520_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_520_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_521_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_521_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_521_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_521_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_522_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_522_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_522_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_522_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_523_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_523_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_523_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_523_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_524_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_524_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_524_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_524_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_525_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_525_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_525_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_525_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_526_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_526_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_526_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_526_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_527_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_527_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_527_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_527_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_528_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_528_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_528_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_528_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_529_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_529_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_529_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_529_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_530_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_530_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_530_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_530_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_531_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_531_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_531_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_531_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_532_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_532_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_532_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_532_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_533_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_533_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_533_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_533_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_534_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_534_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_534_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_534_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_535_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_535_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_535_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_535_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_536_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_536_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_536_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_536_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_537_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_537_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_537_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_537_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_538_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_538_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_538_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_538_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_539_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_539_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_539_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_539_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_540_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_540_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_540_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_540_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_541_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_541_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_541_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_541_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_542_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_542_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_542_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_542_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_543_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_543_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_543_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_543_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_544_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_544_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_544_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_544_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_545_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_545_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_545_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_545_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_546_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_546_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_546_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_546_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_547_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_547_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_547_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_547_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_548_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_548_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_548_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_548_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_549_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_549_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_549_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_549_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_550_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_550_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_550_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_550_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_551_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_551_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_551_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_551_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_552_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_552_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_552_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_552_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_553_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_553_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_553_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_553_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire _T_40 = io_dec_tlu_flush_leak_one_wb & io_dec_tlu_flush_lower_wb; // @[el2_ifu_bp_ctl.scala 135:47]
|
|
reg leak_one_f_d1; // @[el2_ifu_bp_ctl.scala 129:56]
|
|
wire _T_41 = leak_one_f_d1 & io_dec_tlu_flush_lower_wb; // @[el2_ifu_bp_ctl.scala 135:93]
|
|
wire leak_one_f = _T_40 | _T_41; // @[el2_ifu_bp_ctl.scala 135:76]
|
|
wire _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 72:51]
|
|
wire exu_mp_valid = io_exu_mp_pkt_bits_misp & _T; // @[el2_ifu_bp_ctl.scala 72:49]
|
|
wire dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_br_start_error | io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu_bp_ctl.scala 94:50]
|
|
wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[el2_lib.scala 191:47]
|
|
wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[el2_lib.scala 191:85]
|
|
wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_bp_ctl.scala 102:51]
|
|
wire [30:0] _T_8 = {fetch_addr_p1_f,1'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_11 = _T_8[8:1] ^ _T_8[16:9]; // @[el2_lib.scala 191:47]
|
|
wire [7:0] btb_rd_addr_p1_f = _T_11 ^ _T_8[24:17]; // @[el2_lib.scala 191:85]
|
|
wire _T_143 = ~io_ifc_fetch_addr_f[0]; // @[el2_ifu_bp_ctl.scala 186:40]
|
|
wire _T_2111 = btb_rd_addr_f == 8'h0; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_0; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2623 = _T_2111 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72]
|
|
wire _T_2113 = btb_rd_addr_f == 8'h1; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_1; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2624 = _T_2113 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2879 = _T_2623 | _T_2624; // @[Mux.scala 27:72]
|
|
wire _T_2115 = btb_rd_addr_f == 8'h2; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_2; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2625 = _T_2115 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2880 = _T_2879 | _T_2625; // @[Mux.scala 27:72]
|
|
wire _T_2117 = btb_rd_addr_f == 8'h3; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_3; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2626 = _T_2117 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2881 = _T_2880 | _T_2626; // @[Mux.scala 27:72]
|
|
wire _T_2119 = btb_rd_addr_f == 8'h4; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_4; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2627 = _T_2119 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2882 = _T_2881 | _T_2627; // @[Mux.scala 27:72]
|
|
wire _T_2121 = btb_rd_addr_f == 8'h5; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_5; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2628 = _T_2121 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2883 = _T_2882 | _T_2628; // @[Mux.scala 27:72]
|
|
wire _T_2123 = btb_rd_addr_f == 8'h6; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_6; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2629 = _T_2123 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2884 = _T_2883 | _T_2629; // @[Mux.scala 27:72]
|
|
wire _T_2125 = btb_rd_addr_f == 8'h7; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_7; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2630 = _T_2125 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2885 = _T_2884 | _T_2630; // @[Mux.scala 27:72]
|
|
wire _T_2127 = btb_rd_addr_f == 8'h8; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_8; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2631 = _T_2127 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2886 = _T_2885 | _T_2631; // @[Mux.scala 27:72]
|
|
wire _T_2129 = btb_rd_addr_f == 8'h9; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_9; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2632 = _T_2129 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2887 = _T_2886 | _T_2632; // @[Mux.scala 27:72]
|
|
wire _T_2131 = btb_rd_addr_f == 8'ha; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_10; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2633 = _T_2131 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2888 = _T_2887 | _T_2633; // @[Mux.scala 27:72]
|
|
wire _T_2133 = btb_rd_addr_f == 8'hb; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_11; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2634 = _T_2133 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2889 = _T_2888 | _T_2634; // @[Mux.scala 27:72]
|
|
wire _T_2135 = btb_rd_addr_f == 8'hc; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_12; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2635 = _T_2135 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2890 = _T_2889 | _T_2635; // @[Mux.scala 27:72]
|
|
wire _T_2137 = btb_rd_addr_f == 8'hd; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_13; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2636 = _T_2137 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2891 = _T_2890 | _T_2636; // @[Mux.scala 27:72]
|
|
wire _T_2139 = btb_rd_addr_f == 8'he; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_14; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2637 = _T_2139 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2892 = _T_2891 | _T_2637; // @[Mux.scala 27:72]
|
|
wire _T_2141 = btb_rd_addr_f == 8'hf; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_15; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2638 = _T_2141 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2893 = _T_2892 | _T_2638; // @[Mux.scala 27:72]
|
|
wire _T_2143 = btb_rd_addr_f == 8'h10; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_16; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2639 = _T_2143 ? btb_bank0_rd_data_way0_out_16 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2894 = _T_2893 | _T_2639; // @[Mux.scala 27:72]
|
|
wire _T_2145 = btb_rd_addr_f == 8'h11; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_17; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2640 = _T_2145 ? btb_bank0_rd_data_way0_out_17 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2895 = _T_2894 | _T_2640; // @[Mux.scala 27:72]
|
|
wire _T_2147 = btb_rd_addr_f == 8'h12; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_18; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2641 = _T_2147 ? btb_bank0_rd_data_way0_out_18 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2896 = _T_2895 | _T_2641; // @[Mux.scala 27:72]
|
|
wire _T_2149 = btb_rd_addr_f == 8'h13; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_19; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2642 = _T_2149 ? btb_bank0_rd_data_way0_out_19 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2897 = _T_2896 | _T_2642; // @[Mux.scala 27:72]
|
|
wire _T_2151 = btb_rd_addr_f == 8'h14; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_20; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2643 = _T_2151 ? btb_bank0_rd_data_way0_out_20 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2898 = _T_2897 | _T_2643; // @[Mux.scala 27:72]
|
|
wire _T_2153 = btb_rd_addr_f == 8'h15; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_21; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2644 = _T_2153 ? btb_bank0_rd_data_way0_out_21 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2899 = _T_2898 | _T_2644; // @[Mux.scala 27:72]
|
|
wire _T_2155 = btb_rd_addr_f == 8'h16; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_22; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2645 = _T_2155 ? btb_bank0_rd_data_way0_out_22 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2900 = _T_2899 | _T_2645; // @[Mux.scala 27:72]
|
|
wire _T_2157 = btb_rd_addr_f == 8'h17; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_23; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2646 = _T_2157 ? btb_bank0_rd_data_way0_out_23 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2901 = _T_2900 | _T_2646; // @[Mux.scala 27:72]
|
|
wire _T_2159 = btb_rd_addr_f == 8'h18; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_24; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2647 = _T_2159 ? btb_bank0_rd_data_way0_out_24 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2902 = _T_2901 | _T_2647; // @[Mux.scala 27:72]
|
|
wire _T_2161 = btb_rd_addr_f == 8'h19; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_25; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2648 = _T_2161 ? btb_bank0_rd_data_way0_out_25 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2903 = _T_2902 | _T_2648; // @[Mux.scala 27:72]
|
|
wire _T_2163 = btb_rd_addr_f == 8'h1a; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_26; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2649 = _T_2163 ? btb_bank0_rd_data_way0_out_26 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2904 = _T_2903 | _T_2649; // @[Mux.scala 27:72]
|
|
wire _T_2165 = btb_rd_addr_f == 8'h1b; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_27; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2650 = _T_2165 ? btb_bank0_rd_data_way0_out_27 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2905 = _T_2904 | _T_2650; // @[Mux.scala 27:72]
|
|
wire _T_2167 = btb_rd_addr_f == 8'h1c; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_28; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2651 = _T_2167 ? btb_bank0_rd_data_way0_out_28 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2906 = _T_2905 | _T_2651; // @[Mux.scala 27:72]
|
|
wire _T_2169 = btb_rd_addr_f == 8'h1d; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_29; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2652 = _T_2169 ? btb_bank0_rd_data_way0_out_29 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2907 = _T_2906 | _T_2652; // @[Mux.scala 27:72]
|
|
wire _T_2171 = btb_rd_addr_f == 8'h1e; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_30; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2653 = _T_2171 ? btb_bank0_rd_data_way0_out_30 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2908 = _T_2907 | _T_2653; // @[Mux.scala 27:72]
|
|
wire _T_2173 = btb_rd_addr_f == 8'h1f; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_31; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2654 = _T_2173 ? btb_bank0_rd_data_way0_out_31 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2909 = _T_2908 | _T_2654; // @[Mux.scala 27:72]
|
|
wire _T_2175 = btb_rd_addr_f == 8'h20; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_32; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2655 = _T_2175 ? btb_bank0_rd_data_way0_out_32 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2910 = _T_2909 | _T_2655; // @[Mux.scala 27:72]
|
|
wire _T_2177 = btb_rd_addr_f == 8'h21; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_33; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2656 = _T_2177 ? btb_bank0_rd_data_way0_out_33 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2911 = _T_2910 | _T_2656; // @[Mux.scala 27:72]
|
|
wire _T_2179 = btb_rd_addr_f == 8'h22; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_34; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2657 = _T_2179 ? btb_bank0_rd_data_way0_out_34 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2912 = _T_2911 | _T_2657; // @[Mux.scala 27:72]
|
|
wire _T_2181 = btb_rd_addr_f == 8'h23; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_35; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2658 = _T_2181 ? btb_bank0_rd_data_way0_out_35 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2913 = _T_2912 | _T_2658; // @[Mux.scala 27:72]
|
|
wire _T_2183 = btb_rd_addr_f == 8'h24; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_36; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2659 = _T_2183 ? btb_bank0_rd_data_way0_out_36 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2914 = _T_2913 | _T_2659; // @[Mux.scala 27:72]
|
|
wire _T_2185 = btb_rd_addr_f == 8'h25; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_37; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2660 = _T_2185 ? btb_bank0_rd_data_way0_out_37 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2915 = _T_2914 | _T_2660; // @[Mux.scala 27:72]
|
|
wire _T_2187 = btb_rd_addr_f == 8'h26; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_38; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2661 = _T_2187 ? btb_bank0_rd_data_way0_out_38 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2916 = _T_2915 | _T_2661; // @[Mux.scala 27:72]
|
|
wire _T_2189 = btb_rd_addr_f == 8'h27; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_39; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2662 = _T_2189 ? btb_bank0_rd_data_way0_out_39 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2917 = _T_2916 | _T_2662; // @[Mux.scala 27:72]
|
|
wire _T_2191 = btb_rd_addr_f == 8'h28; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_40; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2663 = _T_2191 ? btb_bank0_rd_data_way0_out_40 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2918 = _T_2917 | _T_2663; // @[Mux.scala 27:72]
|
|
wire _T_2193 = btb_rd_addr_f == 8'h29; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_41; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2664 = _T_2193 ? btb_bank0_rd_data_way0_out_41 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2919 = _T_2918 | _T_2664; // @[Mux.scala 27:72]
|
|
wire _T_2195 = btb_rd_addr_f == 8'h2a; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_42; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2665 = _T_2195 ? btb_bank0_rd_data_way0_out_42 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2920 = _T_2919 | _T_2665; // @[Mux.scala 27:72]
|
|
wire _T_2197 = btb_rd_addr_f == 8'h2b; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_43; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2666 = _T_2197 ? btb_bank0_rd_data_way0_out_43 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2921 = _T_2920 | _T_2666; // @[Mux.scala 27:72]
|
|
wire _T_2199 = btb_rd_addr_f == 8'h2c; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_44; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2667 = _T_2199 ? btb_bank0_rd_data_way0_out_44 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2922 = _T_2921 | _T_2667; // @[Mux.scala 27:72]
|
|
wire _T_2201 = btb_rd_addr_f == 8'h2d; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_45; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2668 = _T_2201 ? btb_bank0_rd_data_way0_out_45 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2923 = _T_2922 | _T_2668; // @[Mux.scala 27:72]
|
|
wire _T_2203 = btb_rd_addr_f == 8'h2e; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_46; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2669 = _T_2203 ? btb_bank0_rd_data_way0_out_46 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2924 = _T_2923 | _T_2669; // @[Mux.scala 27:72]
|
|
wire _T_2205 = btb_rd_addr_f == 8'h2f; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_47; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2670 = _T_2205 ? btb_bank0_rd_data_way0_out_47 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2925 = _T_2924 | _T_2670; // @[Mux.scala 27:72]
|
|
wire _T_2207 = btb_rd_addr_f == 8'h30; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_48; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2671 = _T_2207 ? btb_bank0_rd_data_way0_out_48 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2926 = _T_2925 | _T_2671; // @[Mux.scala 27:72]
|
|
wire _T_2209 = btb_rd_addr_f == 8'h31; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_49; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2672 = _T_2209 ? btb_bank0_rd_data_way0_out_49 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2927 = _T_2926 | _T_2672; // @[Mux.scala 27:72]
|
|
wire _T_2211 = btb_rd_addr_f == 8'h32; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_50; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2673 = _T_2211 ? btb_bank0_rd_data_way0_out_50 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2928 = _T_2927 | _T_2673; // @[Mux.scala 27:72]
|
|
wire _T_2213 = btb_rd_addr_f == 8'h33; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_51; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2674 = _T_2213 ? btb_bank0_rd_data_way0_out_51 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2929 = _T_2928 | _T_2674; // @[Mux.scala 27:72]
|
|
wire _T_2215 = btb_rd_addr_f == 8'h34; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_52; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2675 = _T_2215 ? btb_bank0_rd_data_way0_out_52 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2930 = _T_2929 | _T_2675; // @[Mux.scala 27:72]
|
|
wire _T_2217 = btb_rd_addr_f == 8'h35; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_53; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2676 = _T_2217 ? btb_bank0_rd_data_way0_out_53 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2931 = _T_2930 | _T_2676; // @[Mux.scala 27:72]
|
|
wire _T_2219 = btb_rd_addr_f == 8'h36; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_54; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2677 = _T_2219 ? btb_bank0_rd_data_way0_out_54 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2932 = _T_2931 | _T_2677; // @[Mux.scala 27:72]
|
|
wire _T_2221 = btb_rd_addr_f == 8'h37; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_55; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2678 = _T_2221 ? btb_bank0_rd_data_way0_out_55 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2933 = _T_2932 | _T_2678; // @[Mux.scala 27:72]
|
|
wire _T_2223 = btb_rd_addr_f == 8'h38; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_56; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2679 = _T_2223 ? btb_bank0_rd_data_way0_out_56 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2934 = _T_2933 | _T_2679; // @[Mux.scala 27:72]
|
|
wire _T_2225 = btb_rd_addr_f == 8'h39; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_57; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2680 = _T_2225 ? btb_bank0_rd_data_way0_out_57 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2935 = _T_2934 | _T_2680; // @[Mux.scala 27:72]
|
|
wire _T_2227 = btb_rd_addr_f == 8'h3a; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_58; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2681 = _T_2227 ? btb_bank0_rd_data_way0_out_58 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2936 = _T_2935 | _T_2681; // @[Mux.scala 27:72]
|
|
wire _T_2229 = btb_rd_addr_f == 8'h3b; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_59; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2682 = _T_2229 ? btb_bank0_rd_data_way0_out_59 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2937 = _T_2936 | _T_2682; // @[Mux.scala 27:72]
|
|
wire _T_2231 = btb_rd_addr_f == 8'h3c; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_60; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2683 = _T_2231 ? btb_bank0_rd_data_way0_out_60 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2938 = _T_2937 | _T_2683; // @[Mux.scala 27:72]
|
|
wire _T_2233 = btb_rd_addr_f == 8'h3d; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_61; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2684 = _T_2233 ? btb_bank0_rd_data_way0_out_61 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2939 = _T_2938 | _T_2684; // @[Mux.scala 27:72]
|
|
wire _T_2235 = btb_rd_addr_f == 8'h3e; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_62; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2685 = _T_2235 ? btb_bank0_rd_data_way0_out_62 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2940 = _T_2939 | _T_2685; // @[Mux.scala 27:72]
|
|
wire _T_2237 = btb_rd_addr_f == 8'h3f; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_63; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2686 = _T_2237 ? btb_bank0_rd_data_way0_out_63 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2941 = _T_2940 | _T_2686; // @[Mux.scala 27:72]
|
|
wire _T_2239 = btb_rd_addr_f == 8'h40; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_64; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2687 = _T_2239 ? btb_bank0_rd_data_way0_out_64 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2942 = _T_2941 | _T_2687; // @[Mux.scala 27:72]
|
|
wire _T_2241 = btb_rd_addr_f == 8'h41; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_65; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2688 = _T_2241 ? btb_bank0_rd_data_way0_out_65 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2943 = _T_2942 | _T_2688; // @[Mux.scala 27:72]
|
|
wire _T_2243 = btb_rd_addr_f == 8'h42; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_66; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2689 = _T_2243 ? btb_bank0_rd_data_way0_out_66 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2944 = _T_2943 | _T_2689; // @[Mux.scala 27:72]
|
|
wire _T_2245 = btb_rd_addr_f == 8'h43; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_67; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2690 = _T_2245 ? btb_bank0_rd_data_way0_out_67 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2945 = _T_2944 | _T_2690; // @[Mux.scala 27:72]
|
|
wire _T_2247 = btb_rd_addr_f == 8'h44; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_68; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2691 = _T_2247 ? btb_bank0_rd_data_way0_out_68 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2946 = _T_2945 | _T_2691; // @[Mux.scala 27:72]
|
|
wire _T_2249 = btb_rd_addr_f == 8'h45; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_69; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2692 = _T_2249 ? btb_bank0_rd_data_way0_out_69 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2947 = _T_2946 | _T_2692; // @[Mux.scala 27:72]
|
|
wire _T_2251 = btb_rd_addr_f == 8'h46; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_70; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2693 = _T_2251 ? btb_bank0_rd_data_way0_out_70 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2948 = _T_2947 | _T_2693; // @[Mux.scala 27:72]
|
|
wire _T_2253 = btb_rd_addr_f == 8'h47; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_71; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2694 = _T_2253 ? btb_bank0_rd_data_way0_out_71 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2949 = _T_2948 | _T_2694; // @[Mux.scala 27:72]
|
|
wire _T_2255 = btb_rd_addr_f == 8'h48; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_72; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2695 = _T_2255 ? btb_bank0_rd_data_way0_out_72 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2950 = _T_2949 | _T_2695; // @[Mux.scala 27:72]
|
|
wire _T_2257 = btb_rd_addr_f == 8'h49; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_73; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2696 = _T_2257 ? btb_bank0_rd_data_way0_out_73 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2951 = _T_2950 | _T_2696; // @[Mux.scala 27:72]
|
|
wire _T_2259 = btb_rd_addr_f == 8'h4a; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_74; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2697 = _T_2259 ? btb_bank0_rd_data_way0_out_74 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2952 = _T_2951 | _T_2697; // @[Mux.scala 27:72]
|
|
wire _T_2261 = btb_rd_addr_f == 8'h4b; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_75; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2698 = _T_2261 ? btb_bank0_rd_data_way0_out_75 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2953 = _T_2952 | _T_2698; // @[Mux.scala 27:72]
|
|
wire _T_2263 = btb_rd_addr_f == 8'h4c; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_76; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2699 = _T_2263 ? btb_bank0_rd_data_way0_out_76 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2954 = _T_2953 | _T_2699; // @[Mux.scala 27:72]
|
|
wire _T_2265 = btb_rd_addr_f == 8'h4d; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_77; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2700 = _T_2265 ? btb_bank0_rd_data_way0_out_77 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2955 = _T_2954 | _T_2700; // @[Mux.scala 27:72]
|
|
wire _T_2267 = btb_rd_addr_f == 8'h4e; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_78; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2701 = _T_2267 ? btb_bank0_rd_data_way0_out_78 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2956 = _T_2955 | _T_2701; // @[Mux.scala 27:72]
|
|
wire _T_2269 = btb_rd_addr_f == 8'h4f; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_79; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2702 = _T_2269 ? btb_bank0_rd_data_way0_out_79 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2957 = _T_2956 | _T_2702; // @[Mux.scala 27:72]
|
|
wire _T_2271 = btb_rd_addr_f == 8'h50; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_80; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2703 = _T_2271 ? btb_bank0_rd_data_way0_out_80 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2958 = _T_2957 | _T_2703; // @[Mux.scala 27:72]
|
|
wire _T_2273 = btb_rd_addr_f == 8'h51; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_81; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2704 = _T_2273 ? btb_bank0_rd_data_way0_out_81 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2959 = _T_2958 | _T_2704; // @[Mux.scala 27:72]
|
|
wire _T_2275 = btb_rd_addr_f == 8'h52; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_82; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2705 = _T_2275 ? btb_bank0_rd_data_way0_out_82 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2960 = _T_2959 | _T_2705; // @[Mux.scala 27:72]
|
|
wire _T_2277 = btb_rd_addr_f == 8'h53; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_83; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2706 = _T_2277 ? btb_bank0_rd_data_way0_out_83 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2961 = _T_2960 | _T_2706; // @[Mux.scala 27:72]
|
|
wire _T_2279 = btb_rd_addr_f == 8'h54; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_84; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2707 = _T_2279 ? btb_bank0_rd_data_way0_out_84 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2962 = _T_2961 | _T_2707; // @[Mux.scala 27:72]
|
|
wire _T_2281 = btb_rd_addr_f == 8'h55; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_85; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2708 = _T_2281 ? btb_bank0_rd_data_way0_out_85 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2963 = _T_2962 | _T_2708; // @[Mux.scala 27:72]
|
|
wire _T_2283 = btb_rd_addr_f == 8'h56; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_86; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2709 = _T_2283 ? btb_bank0_rd_data_way0_out_86 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2964 = _T_2963 | _T_2709; // @[Mux.scala 27:72]
|
|
wire _T_2285 = btb_rd_addr_f == 8'h57; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_87; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2710 = _T_2285 ? btb_bank0_rd_data_way0_out_87 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2965 = _T_2964 | _T_2710; // @[Mux.scala 27:72]
|
|
wire _T_2287 = btb_rd_addr_f == 8'h58; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_88; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2711 = _T_2287 ? btb_bank0_rd_data_way0_out_88 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2966 = _T_2965 | _T_2711; // @[Mux.scala 27:72]
|
|
wire _T_2289 = btb_rd_addr_f == 8'h59; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_89; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2712 = _T_2289 ? btb_bank0_rd_data_way0_out_89 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2967 = _T_2966 | _T_2712; // @[Mux.scala 27:72]
|
|
wire _T_2291 = btb_rd_addr_f == 8'h5a; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_90; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2713 = _T_2291 ? btb_bank0_rd_data_way0_out_90 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2968 = _T_2967 | _T_2713; // @[Mux.scala 27:72]
|
|
wire _T_2293 = btb_rd_addr_f == 8'h5b; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_91; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2714 = _T_2293 ? btb_bank0_rd_data_way0_out_91 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2969 = _T_2968 | _T_2714; // @[Mux.scala 27:72]
|
|
wire _T_2295 = btb_rd_addr_f == 8'h5c; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_92; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2715 = _T_2295 ? btb_bank0_rd_data_way0_out_92 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2970 = _T_2969 | _T_2715; // @[Mux.scala 27:72]
|
|
wire _T_2297 = btb_rd_addr_f == 8'h5d; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_93; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2716 = _T_2297 ? btb_bank0_rd_data_way0_out_93 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2971 = _T_2970 | _T_2716; // @[Mux.scala 27:72]
|
|
wire _T_2299 = btb_rd_addr_f == 8'h5e; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_94; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2717 = _T_2299 ? btb_bank0_rd_data_way0_out_94 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2972 = _T_2971 | _T_2717; // @[Mux.scala 27:72]
|
|
wire _T_2301 = btb_rd_addr_f == 8'h5f; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_95; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2718 = _T_2301 ? btb_bank0_rd_data_way0_out_95 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2973 = _T_2972 | _T_2718; // @[Mux.scala 27:72]
|
|
wire _T_2303 = btb_rd_addr_f == 8'h60; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_96; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2719 = _T_2303 ? btb_bank0_rd_data_way0_out_96 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2974 = _T_2973 | _T_2719; // @[Mux.scala 27:72]
|
|
wire _T_2305 = btb_rd_addr_f == 8'h61; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_97; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2720 = _T_2305 ? btb_bank0_rd_data_way0_out_97 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2975 = _T_2974 | _T_2720; // @[Mux.scala 27:72]
|
|
wire _T_2307 = btb_rd_addr_f == 8'h62; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_98; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2721 = _T_2307 ? btb_bank0_rd_data_way0_out_98 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2976 = _T_2975 | _T_2721; // @[Mux.scala 27:72]
|
|
wire _T_2309 = btb_rd_addr_f == 8'h63; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_99; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2722 = _T_2309 ? btb_bank0_rd_data_way0_out_99 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2977 = _T_2976 | _T_2722; // @[Mux.scala 27:72]
|
|
wire _T_2311 = btb_rd_addr_f == 8'h64; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_100; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2723 = _T_2311 ? btb_bank0_rd_data_way0_out_100 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2978 = _T_2977 | _T_2723; // @[Mux.scala 27:72]
|
|
wire _T_2313 = btb_rd_addr_f == 8'h65; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_101; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2724 = _T_2313 ? btb_bank0_rd_data_way0_out_101 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2979 = _T_2978 | _T_2724; // @[Mux.scala 27:72]
|
|
wire _T_2315 = btb_rd_addr_f == 8'h66; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_102; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2725 = _T_2315 ? btb_bank0_rd_data_way0_out_102 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2980 = _T_2979 | _T_2725; // @[Mux.scala 27:72]
|
|
wire _T_2317 = btb_rd_addr_f == 8'h67; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_103; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2726 = _T_2317 ? btb_bank0_rd_data_way0_out_103 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2981 = _T_2980 | _T_2726; // @[Mux.scala 27:72]
|
|
wire _T_2319 = btb_rd_addr_f == 8'h68; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_104; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2727 = _T_2319 ? btb_bank0_rd_data_way0_out_104 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2982 = _T_2981 | _T_2727; // @[Mux.scala 27:72]
|
|
wire _T_2321 = btb_rd_addr_f == 8'h69; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_105; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2728 = _T_2321 ? btb_bank0_rd_data_way0_out_105 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2983 = _T_2982 | _T_2728; // @[Mux.scala 27:72]
|
|
wire _T_2323 = btb_rd_addr_f == 8'h6a; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_106; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2729 = _T_2323 ? btb_bank0_rd_data_way0_out_106 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2984 = _T_2983 | _T_2729; // @[Mux.scala 27:72]
|
|
wire _T_2325 = btb_rd_addr_f == 8'h6b; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_107; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2730 = _T_2325 ? btb_bank0_rd_data_way0_out_107 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2985 = _T_2984 | _T_2730; // @[Mux.scala 27:72]
|
|
wire _T_2327 = btb_rd_addr_f == 8'h6c; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_108; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2731 = _T_2327 ? btb_bank0_rd_data_way0_out_108 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2986 = _T_2985 | _T_2731; // @[Mux.scala 27:72]
|
|
wire _T_2329 = btb_rd_addr_f == 8'h6d; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_109; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2732 = _T_2329 ? btb_bank0_rd_data_way0_out_109 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2987 = _T_2986 | _T_2732; // @[Mux.scala 27:72]
|
|
wire _T_2331 = btb_rd_addr_f == 8'h6e; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_110; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2733 = _T_2331 ? btb_bank0_rd_data_way0_out_110 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2988 = _T_2987 | _T_2733; // @[Mux.scala 27:72]
|
|
wire _T_2333 = btb_rd_addr_f == 8'h6f; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_111; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2734 = _T_2333 ? btb_bank0_rd_data_way0_out_111 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2989 = _T_2988 | _T_2734; // @[Mux.scala 27:72]
|
|
wire _T_2335 = btb_rd_addr_f == 8'h70; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_112; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2735 = _T_2335 ? btb_bank0_rd_data_way0_out_112 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2990 = _T_2989 | _T_2735; // @[Mux.scala 27:72]
|
|
wire _T_2337 = btb_rd_addr_f == 8'h71; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_113; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2736 = _T_2337 ? btb_bank0_rd_data_way0_out_113 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2991 = _T_2990 | _T_2736; // @[Mux.scala 27:72]
|
|
wire _T_2339 = btb_rd_addr_f == 8'h72; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_114; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2737 = _T_2339 ? btb_bank0_rd_data_way0_out_114 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2992 = _T_2991 | _T_2737; // @[Mux.scala 27:72]
|
|
wire _T_2341 = btb_rd_addr_f == 8'h73; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_115; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2738 = _T_2341 ? btb_bank0_rd_data_way0_out_115 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2993 = _T_2992 | _T_2738; // @[Mux.scala 27:72]
|
|
wire _T_2343 = btb_rd_addr_f == 8'h74; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_116; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2739 = _T_2343 ? btb_bank0_rd_data_way0_out_116 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2994 = _T_2993 | _T_2739; // @[Mux.scala 27:72]
|
|
wire _T_2345 = btb_rd_addr_f == 8'h75; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_117; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2740 = _T_2345 ? btb_bank0_rd_data_way0_out_117 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2995 = _T_2994 | _T_2740; // @[Mux.scala 27:72]
|
|
wire _T_2347 = btb_rd_addr_f == 8'h76; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_118; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2741 = _T_2347 ? btb_bank0_rd_data_way0_out_118 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2996 = _T_2995 | _T_2741; // @[Mux.scala 27:72]
|
|
wire _T_2349 = btb_rd_addr_f == 8'h77; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_119; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2742 = _T_2349 ? btb_bank0_rd_data_way0_out_119 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2997 = _T_2996 | _T_2742; // @[Mux.scala 27:72]
|
|
wire _T_2351 = btb_rd_addr_f == 8'h78; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_120; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2743 = _T_2351 ? btb_bank0_rd_data_way0_out_120 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2998 = _T_2997 | _T_2743; // @[Mux.scala 27:72]
|
|
wire _T_2353 = btb_rd_addr_f == 8'h79; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_121; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2744 = _T_2353 ? btb_bank0_rd_data_way0_out_121 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_2999 = _T_2998 | _T_2744; // @[Mux.scala 27:72]
|
|
wire _T_2355 = btb_rd_addr_f == 8'h7a; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_122; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2745 = _T_2355 ? btb_bank0_rd_data_way0_out_122 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3000 = _T_2999 | _T_2745; // @[Mux.scala 27:72]
|
|
wire _T_2357 = btb_rd_addr_f == 8'h7b; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_123; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2746 = _T_2357 ? btb_bank0_rd_data_way0_out_123 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3001 = _T_3000 | _T_2746; // @[Mux.scala 27:72]
|
|
wire _T_2359 = btb_rd_addr_f == 8'h7c; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_124; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2747 = _T_2359 ? btb_bank0_rd_data_way0_out_124 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3002 = _T_3001 | _T_2747; // @[Mux.scala 27:72]
|
|
wire _T_2361 = btb_rd_addr_f == 8'h7d; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_125; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2748 = _T_2361 ? btb_bank0_rd_data_way0_out_125 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3003 = _T_3002 | _T_2748; // @[Mux.scala 27:72]
|
|
wire _T_2363 = btb_rd_addr_f == 8'h7e; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_126; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2749 = _T_2363 ? btb_bank0_rd_data_way0_out_126 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3004 = _T_3003 | _T_2749; // @[Mux.scala 27:72]
|
|
wire _T_2365 = btb_rd_addr_f == 8'h7f; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_127; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2750 = _T_2365 ? btb_bank0_rd_data_way0_out_127 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3005 = _T_3004 | _T_2750; // @[Mux.scala 27:72]
|
|
wire _T_2367 = btb_rd_addr_f == 8'h80; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_128; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2751 = _T_2367 ? btb_bank0_rd_data_way0_out_128 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3006 = _T_3005 | _T_2751; // @[Mux.scala 27:72]
|
|
wire _T_2369 = btb_rd_addr_f == 8'h81; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_129; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2752 = _T_2369 ? btb_bank0_rd_data_way0_out_129 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3007 = _T_3006 | _T_2752; // @[Mux.scala 27:72]
|
|
wire _T_2371 = btb_rd_addr_f == 8'h82; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_130; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2753 = _T_2371 ? btb_bank0_rd_data_way0_out_130 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3008 = _T_3007 | _T_2753; // @[Mux.scala 27:72]
|
|
wire _T_2373 = btb_rd_addr_f == 8'h83; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_131; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2754 = _T_2373 ? btb_bank0_rd_data_way0_out_131 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3009 = _T_3008 | _T_2754; // @[Mux.scala 27:72]
|
|
wire _T_2375 = btb_rd_addr_f == 8'h84; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_132; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2755 = _T_2375 ? btb_bank0_rd_data_way0_out_132 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3010 = _T_3009 | _T_2755; // @[Mux.scala 27:72]
|
|
wire _T_2377 = btb_rd_addr_f == 8'h85; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_133; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2756 = _T_2377 ? btb_bank0_rd_data_way0_out_133 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3011 = _T_3010 | _T_2756; // @[Mux.scala 27:72]
|
|
wire _T_2379 = btb_rd_addr_f == 8'h86; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_134; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2757 = _T_2379 ? btb_bank0_rd_data_way0_out_134 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3012 = _T_3011 | _T_2757; // @[Mux.scala 27:72]
|
|
wire _T_2381 = btb_rd_addr_f == 8'h87; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_135; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2758 = _T_2381 ? btb_bank0_rd_data_way0_out_135 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3013 = _T_3012 | _T_2758; // @[Mux.scala 27:72]
|
|
wire _T_2383 = btb_rd_addr_f == 8'h88; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_136; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2759 = _T_2383 ? btb_bank0_rd_data_way0_out_136 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3014 = _T_3013 | _T_2759; // @[Mux.scala 27:72]
|
|
wire _T_2385 = btb_rd_addr_f == 8'h89; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_137; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2760 = _T_2385 ? btb_bank0_rd_data_way0_out_137 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3015 = _T_3014 | _T_2760; // @[Mux.scala 27:72]
|
|
wire _T_2387 = btb_rd_addr_f == 8'h8a; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_138; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2761 = _T_2387 ? btb_bank0_rd_data_way0_out_138 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3016 = _T_3015 | _T_2761; // @[Mux.scala 27:72]
|
|
wire _T_2389 = btb_rd_addr_f == 8'h8b; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_139; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2762 = _T_2389 ? btb_bank0_rd_data_way0_out_139 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3017 = _T_3016 | _T_2762; // @[Mux.scala 27:72]
|
|
wire _T_2391 = btb_rd_addr_f == 8'h8c; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_140; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2763 = _T_2391 ? btb_bank0_rd_data_way0_out_140 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3018 = _T_3017 | _T_2763; // @[Mux.scala 27:72]
|
|
wire _T_2393 = btb_rd_addr_f == 8'h8d; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_141; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2764 = _T_2393 ? btb_bank0_rd_data_way0_out_141 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3019 = _T_3018 | _T_2764; // @[Mux.scala 27:72]
|
|
wire _T_2395 = btb_rd_addr_f == 8'h8e; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_142; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2765 = _T_2395 ? btb_bank0_rd_data_way0_out_142 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3020 = _T_3019 | _T_2765; // @[Mux.scala 27:72]
|
|
wire _T_2397 = btb_rd_addr_f == 8'h8f; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_143; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2766 = _T_2397 ? btb_bank0_rd_data_way0_out_143 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3021 = _T_3020 | _T_2766; // @[Mux.scala 27:72]
|
|
wire _T_2399 = btb_rd_addr_f == 8'h90; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_144; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2767 = _T_2399 ? btb_bank0_rd_data_way0_out_144 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3022 = _T_3021 | _T_2767; // @[Mux.scala 27:72]
|
|
wire _T_2401 = btb_rd_addr_f == 8'h91; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_145; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2768 = _T_2401 ? btb_bank0_rd_data_way0_out_145 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3023 = _T_3022 | _T_2768; // @[Mux.scala 27:72]
|
|
wire _T_2403 = btb_rd_addr_f == 8'h92; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_146; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2769 = _T_2403 ? btb_bank0_rd_data_way0_out_146 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3024 = _T_3023 | _T_2769; // @[Mux.scala 27:72]
|
|
wire _T_2405 = btb_rd_addr_f == 8'h93; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_147; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2770 = _T_2405 ? btb_bank0_rd_data_way0_out_147 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3025 = _T_3024 | _T_2770; // @[Mux.scala 27:72]
|
|
wire _T_2407 = btb_rd_addr_f == 8'h94; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_148; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2771 = _T_2407 ? btb_bank0_rd_data_way0_out_148 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3026 = _T_3025 | _T_2771; // @[Mux.scala 27:72]
|
|
wire _T_2409 = btb_rd_addr_f == 8'h95; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_149; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2772 = _T_2409 ? btb_bank0_rd_data_way0_out_149 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3027 = _T_3026 | _T_2772; // @[Mux.scala 27:72]
|
|
wire _T_2411 = btb_rd_addr_f == 8'h96; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_150; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2773 = _T_2411 ? btb_bank0_rd_data_way0_out_150 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3028 = _T_3027 | _T_2773; // @[Mux.scala 27:72]
|
|
wire _T_2413 = btb_rd_addr_f == 8'h97; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_151; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2774 = _T_2413 ? btb_bank0_rd_data_way0_out_151 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3029 = _T_3028 | _T_2774; // @[Mux.scala 27:72]
|
|
wire _T_2415 = btb_rd_addr_f == 8'h98; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_152; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2775 = _T_2415 ? btb_bank0_rd_data_way0_out_152 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3030 = _T_3029 | _T_2775; // @[Mux.scala 27:72]
|
|
wire _T_2417 = btb_rd_addr_f == 8'h99; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_153; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2776 = _T_2417 ? btb_bank0_rd_data_way0_out_153 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3031 = _T_3030 | _T_2776; // @[Mux.scala 27:72]
|
|
wire _T_2419 = btb_rd_addr_f == 8'h9a; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_154; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2777 = _T_2419 ? btb_bank0_rd_data_way0_out_154 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3032 = _T_3031 | _T_2777; // @[Mux.scala 27:72]
|
|
wire _T_2421 = btb_rd_addr_f == 8'h9b; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_155; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2778 = _T_2421 ? btb_bank0_rd_data_way0_out_155 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3033 = _T_3032 | _T_2778; // @[Mux.scala 27:72]
|
|
wire _T_2423 = btb_rd_addr_f == 8'h9c; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_156; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2779 = _T_2423 ? btb_bank0_rd_data_way0_out_156 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3034 = _T_3033 | _T_2779; // @[Mux.scala 27:72]
|
|
wire _T_2425 = btb_rd_addr_f == 8'h9d; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_157; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2780 = _T_2425 ? btb_bank0_rd_data_way0_out_157 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3035 = _T_3034 | _T_2780; // @[Mux.scala 27:72]
|
|
wire _T_2427 = btb_rd_addr_f == 8'h9e; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_158; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2781 = _T_2427 ? btb_bank0_rd_data_way0_out_158 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3036 = _T_3035 | _T_2781; // @[Mux.scala 27:72]
|
|
wire _T_2429 = btb_rd_addr_f == 8'h9f; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_159; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2782 = _T_2429 ? btb_bank0_rd_data_way0_out_159 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3037 = _T_3036 | _T_2782; // @[Mux.scala 27:72]
|
|
wire _T_2431 = btb_rd_addr_f == 8'ha0; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_160; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2783 = _T_2431 ? btb_bank0_rd_data_way0_out_160 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3038 = _T_3037 | _T_2783; // @[Mux.scala 27:72]
|
|
wire _T_2433 = btb_rd_addr_f == 8'ha1; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_161; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2784 = _T_2433 ? btb_bank0_rd_data_way0_out_161 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3039 = _T_3038 | _T_2784; // @[Mux.scala 27:72]
|
|
wire _T_2435 = btb_rd_addr_f == 8'ha2; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_162; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2785 = _T_2435 ? btb_bank0_rd_data_way0_out_162 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3040 = _T_3039 | _T_2785; // @[Mux.scala 27:72]
|
|
wire _T_2437 = btb_rd_addr_f == 8'ha3; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_163; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2786 = _T_2437 ? btb_bank0_rd_data_way0_out_163 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3041 = _T_3040 | _T_2786; // @[Mux.scala 27:72]
|
|
wire _T_2439 = btb_rd_addr_f == 8'ha4; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_164; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2787 = _T_2439 ? btb_bank0_rd_data_way0_out_164 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3042 = _T_3041 | _T_2787; // @[Mux.scala 27:72]
|
|
wire _T_2441 = btb_rd_addr_f == 8'ha5; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_165; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2788 = _T_2441 ? btb_bank0_rd_data_way0_out_165 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3043 = _T_3042 | _T_2788; // @[Mux.scala 27:72]
|
|
wire _T_2443 = btb_rd_addr_f == 8'ha6; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_166; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2789 = _T_2443 ? btb_bank0_rd_data_way0_out_166 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3044 = _T_3043 | _T_2789; // @[Mux.scala 27:72]
|
|
wire _T_2445 = btb_rd_addr_f == 8'ha7; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_167; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2790 = _T_2445 ? btb_bank0_rd_data_way0_out_167 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3045 = _T_3044 | _T_2790; // @[Mux.scala 27:72]
|
|
wire _T_2447 = btb_rd_addr_f == 8'ha8; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_168; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2791 = _T_2447 ? btb_bank0_rd_data_way0_out_168 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3046 = _T_3045 | _T_2791; // @[Mux.scala 27:72]
|
|
wire _T_2449 = btb_rd_addr_f == 8'ha9; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_169; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2792 = _T_2449 ? btb_bank0_rd_data_way0_out_169 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3047 = _T_3046 | _T_2792; // @[Mux.scala 27:72]
|
|
wire _T_2451 = btb_rd_addr_f == 8'haa; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_170; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2793 = _T_2451 ? btb_bank0_rd_data_way0_out_170 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3048 = _T_3047 | _T_2793; // @[Mux.scala 27:72]
|
|
wire _T_2453 = btb_rd_addr_f == 8'hab; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_171; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2794 = _T_2453 ? btb_bank0_rd_data_way0_out_171 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3049 = _T_3048 | _T_2794; // @[Mux.scala 27:72]
|
|
wire _T_2455 = btb_rd_addr_f == 8'hac; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_172; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2795 = _T_2455 ? btb_bank0_rd_data_way0_out_172 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3050 = _T_3049 | _T_2795; // @[Mux.scala 27:72]
|
|
wire _T_2457 = btb_rd_addr_f == 8'had; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_173; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2796 = _T_2457 ? btb_bank0_rd_data_way0_out_173 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3051 = _T_3050 | _T_2796; // @[Mux.scala 27:72]
|
|
wire _T_2459 = btb_rd_addr_f == 8'hae; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_174; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2797 = _T_2459 ? btb_bank0_rd_data_way0_out_174 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3052 = _T_3051 | _T_2797; // @[Mux.scala 27:72]
|
|
wire _T_2461 = btb_rd_addr_f == 8'haf; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_175; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2798 = _T_2461 ? btb_bank0_rd_data_way0_out_175 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3053 = _T_3052 | _T_2798; // @[Mux.scala 27:72]
|
|
wire _T_2463 = btb_rd_addr_f == 8'hb0; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_176; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2799 = _T_2463 ? btb_bank0_rd_data_way0_out_176 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3054 = _T_3053 | _T_2799; // @[Mux.scala 27:72]
|
|
wire _T_2465 = btb_rd_addr_f == 8'hb1; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_177; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2800 = _T_2465 ? btb_bank0_rd_data_way0_out_177 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3055 = _T_3054 | _T_2800; // @[Mux.scala 27:72]
|
|
wire _T_2467 = btb_rd_addr_f == 8'hb2; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_178; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2801 = _T_2467 ? btb_bank0_rd_data_way0_out_178 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3056 = _T_3055 | _T_2801; // @[Mux.scala 27:72]
|
|
wire _T_2469 = btb_rd_addr_f == 8'hb3; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_179; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2802 = _T_2469 ? btb_bank0_rd_data_way0_out_179 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3057 = _T_3056 | _T_2802; // @[Mux.scala 27:72]
|
|
wire _T_2471 = btb_rd_addr_f == 8'hb4; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_180; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2803 = _T_2471 ? btb_bank0_rd_data_way0_out_180 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3058 = _T_3057 | _T_2803; // @[Mux.scala 27:72]
|
|
wire _T_2473 = btb_rd_addr_f == 8'hb5; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_181; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2804 = _T_2473 ? btb_bank0_rd_data_way0_out_181 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3059 = _T_3058 | _T_2804; // @[Mux.scala 27:72]
|
|
wire _T_2475 = btb_rd_addr_f == 8'hb6; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_182; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2805 = _T_2475 ? btb_bank0_rd_data_way0_out_182 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3060 = _T_3059 | _T_2805; // @[Mux.scala 27:72]
|
|
wire _T_2477 = btb_rd_addr_f == 8'hb7; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_183; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2806 = _T_2477 ? btb_bank0_rd_data_way0_out_183 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3061 = _T_3060 | _T_2806; // @[Mux.scala 27:72]
|
|
wire _T_2479 = btb_rd_addr_f == 8'hb8; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_184; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2807 = _T_2479 ? btb_bank0_rd_data_way0_out_184 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3062 = _T_3061 | _T_2807; // @[Mux.scala 27:72]
|
|
wire _T_2481 = btb_rd_addr_f == 8'hb9; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_185; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2808 = _T_2481 ? btb_bank0_rd_data_way0_out_185 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3063 = _T_3062 | _T_2808; // @[Mux.scala 27:72]
|
|
wire _T_2483 = btb_rd_addr_f == 8'hba; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_186; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2809 = _T_2483 ? btb_bank0_rd_data_way0_out_186 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3064 = _T_3063 | _T_2809; // @[Mux.scala 27:72]
|
|
wire _T_2485 = btb_rd_addr_f == 8'hbb; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_187; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2810 = _T_2485 ? btb_bank0_rd_data_way0_out_187 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3065 = _T_3064 | _T_2810; // @[Mux.scala 27:72]
|
|
wire _T_2487 = btb_rd_addr_f == 8'hbc; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_188; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2811 = _T_2487 ? btb_bank0_rd_data_way0_out_188 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3066 = _T_3065 | _T_2811; // @[Mux.scala 27:72]
|
|
wire _T_2489 = btb_rd_addr_f == 8'hbd; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_189; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2812 = _T_2489 ? btb_bank0_rd_data_way0_out_189 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3067 = _T_3066 | _T_2812; // @[Mux.scala 27:72]
|
|
wire _T_2491 = btb_rd_addr_f == 8'hbe; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_190; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2813 = _T_2491 ? btb_bank0_rd_data_way0_out_190 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3068 = _T_3067 | _T_2813; // @[Mux.scala 27:72]
|
|
wire _T_2493 = btb_rd_addr_f == 8'hbf; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_191; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2814 = _T_2493 ? btb_bank0_rd_data_way0_out_191 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3069 = _T_3068 | _T_2814; // @[Mux.scala 27:72]
|
|
wire _T_2495 = btb_rd_addr_f == 8'hc0; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_192; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2815 = _T_2495 ? btb_bank0_rd_data_way0_out_192 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3070 = _T_3069 | _T_2815; // @[Mux.scala 27:72]
|
|
wire _T_2497 = btb_rd_addr_f == 8'hc1; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_193; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2816 = _T_2497 ? btb_bank0_rd_data_way0_out_193 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3071 = _T_3070 | _T_2816; // @[Mux.scala 27:72]
|
|
wire _T_2499 = btb_rd_addr_f == 8'hc2; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_194; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2817 = _T_2499 ? btb_bank0_rd_data_way0_out_194 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3072 = _T_3071 | _T_2817; // @[Mux.scala 27:72]
|
|
wire _T_2501 = btb_rd_addr_f == 8'hc3; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_195; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2818 = _T_2501 ? btb_bank0_rd_data_way0_out_195 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3073 = _T_3072 | _T_2818; // @[Mux.scala 27:72]
|
|
wire _T_2503 = btb_rd_addr_f == 8'hc4; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_196; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2819 = _T_2503 ? btb_bank0_rd_data_way0_out_196 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3074 = _T_3073 | _T_2819; // @[Mux.scala 27:72]
|
|
wire _T_2505 = btb_rd_addr_f == 8'hc5; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_197; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2820 = _T_2505 ? btb_bank0_rd_data_way0_out_197 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3075 = _T_3074 | _T_2820; // @[Mux.scala 27:72]
|
|
wire _T_2507 = btb_rd_addr_f == 8'hc6; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_198; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2821 = _T_2507 ? btb_bank0_rd_data_way0_out_198 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3076 = _T_3075 | _T_2821; // @[Mux.scala 27:72]
|
|
wire _T_2509 = btb_rd_addr_f == 8'hc7; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_199; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2822 = _T_2509 ? btb_bank0_rd_data_way0_out_199 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3077 = _T_3076 | _T_2822; // @[Mux.scala 27:72]
|
|
wire _T_2511 = btb_rd_addr_f == 8'hc8; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_200; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2823 = _T_2511 ? btb_bank0_rd_data_way0_out_200 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3078 = _T_3077 | _T_2823; // @[Mux.scala 27:72]
|
|
wire _T_2513 = btb_rd_addr_f == 8'hc9; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_201; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2824 = _T_2513 ? btb_bank0_rd_data_way0_out_201 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3079 = _T_3078 | _T_2824; // @[Mux.scala 27:72]
|
|
wire _T_2515 = btb_rd_addr_f == 8'hca; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_202; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2825 = _T_2515 ? btb_bank0_rd_data_way0_out_202 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3080 = _T_3079 | _T_2825; // @[Mux.scala 27:72]
|
|
wire _T_2517 = btb_rd_addr_f == 8'hcb; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_203; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2826 = _T_2517 ? btb_bank0_rd_data_way0_out_203 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3081 = _T_3080 | _T_2826; // @[Mux.scala 27:72]
|
|
wire _T_2519 = btb_rd_addr_f == 8'hcc; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_204; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2827 = _T_2519 ? btb_bank0_rd_data_way0_out_204 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3082 = _T_3081 | _T_2827; // @[Mux.scala 27:72]
|
|
wire _T_2521 = btb_rd_addr_f == 8'hcd; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_205; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2828 = _T_2521 ? btb_bank0_rd_data_way0_out_205 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3083 = _T_3082 | _T_2828; // @[Mux.scala 27:72]
|
|
wire _T_2523 = btb_rd_addr_f == 8'hce; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_206; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2829 = _T_2523 ? btb_bank0_rd_data_way0_out_206 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3084 = _T_3083 | _T_2829; // @[Mux.scala 27:72]
|
|
wire _T_2525 = btb_rd_addr_f == 8'hcf; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_207; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2830 = _T_2525 ? btb_bank0_rd_data_way0_out_207 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3085 = _T_3084 | _T_2830; // @[Mux.scala 27:72]
|
|
wire _T_2527 = btb_rd_addr_f == 8'hd0; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_208; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2831 = _T_2527 ? btb_bank0_rd_data_way0_out_208 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3086 = _T_3085 | _T_2831; // @[Mux.scala 27:72]
|
|
wire _T_2529 = btb_rd_addr_f == 8'hd1; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_209; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2832 = _T_2529 ? btb_bank0_rd_data_way0_out_209 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3087 = _T_3086 | _T_2832; // @[Mux.scala 27:72]
|
|
wire _T_2531 = btb_rd_addr_f == 8'hd2; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_210; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2833 = _T_2531 ? btb_bank0_rd_data_way0_out_210 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3088 = _T_3087 | _T_2833; // @[Mux.scala 27:72]
|
|
wire _T_2533 = btb_rd_addr_f == 8'hd3; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_211; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2834 = _T_2533 ? btb_bank0_rd_data_way0_out_211 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3089 = _T_3088 | _T_2834; // @[Mux.scala 27:72]
|
|
wire _T_2535 = btb_rd_addr_f == 8'hd4; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_212; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2835 = _T_2535 ? btb_bank0_rd_data_way0_out_212 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3090 = _T_3089 | _T_2835; // @[Mux.scala 27:72]
|
|
wire _T_2537 = btb_rd_addr_f == 8'hd5; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_213; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2836 = _T_2537 ? btb_bank0_rd_data_way0_out_213 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3091 = _T_3090 | _T_2836; // @[Mux.scala 27:72]
|
|
wire _T_2539 = btb_rd_addr_f == 8'hd6; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_214; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2837 = _T_2539 ? btb_bank0_rd_data_way0_out_214 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3092 = _T_3091 | _T_2837; // @[Mux.scala 27:72]
|
|
wire _T_2541 = btb_rd_addr_f == 8'hd7; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_215; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2838 = _T_2541 ? btb_bank0_rd_data_way0_out_215 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3093 = _T_3092 | _T_2838; // @[Mux.scala 27:72]
|
|
wire _T_2543 = btb_rd_addr_f == 8'hd8; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_216; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2839 = _T_2543 ? btb_bank0_rd_data_way0_out_216 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3094 = _T_3093 | _T_2839; // @[Mux.scala 27:72]
|
|
wire _T_2545 = btb_rd_addr_f == 8'hd9; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_217; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2840 = _T_2545 ? btb_bank0_rd_data_way0_out_217 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3095 = _T_3094 | _T_2840; // @[Mux.scala 27:72]
|
|
wire _T_2547 = btb_rd_addr_f == 8'hda; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_218; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2841 = _T_2547 ? btb_bank0_rd_data_way0_out_218 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3096 = _T_3095 | _T_2841; // @[Mux.scala 27:72]
|
|
wire _T_2549 = btb_rd_addr_f == 8'hdb; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_219; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2842 = _T_2549 ? btb_bank0_rd_data_way0_out_219 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3097 = _T_3096 | _T_2842; // @[Mux.scala 27:72]
|
|
wire _T_2551 = btb_rd_addr_f == 8'hdc; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_220; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2843 = _T_2551 ? btb_bank0_rd_data_way0_out_220 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3098 = _T_3097 | _T_2843; // @[Mux.scala 27:72]
|
|
wire _T_2553 = btb_rd_addr_f == 8'hdd; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_221; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2844 = _T_2553 ? btb_bank0_rd_data_way0_out_221 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3099 = _T_3098 | _T_2844; // @[Mux.scala 27:72]
|
|
wire _T_2555 = btb_rd_addr_f == 8'hde; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_222; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2845 = _T_2555 ? btb_bank0_rd_data_way0_out_222 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3100 = _T_3099 | _T_2845; // @[Mux.scala 27:72]
|
|
wire _T_2557 = btb_rd_addr_f == 8'hdf; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_223; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2846 = _T_2557 ? btb_bank0_rd_data_way0_out_223 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3101 = _T_3100 | _T_2846; // @[Mux.scala 27:72]
|
|
wire _T_2559 = btb_rd_addr_f == 8'he0; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_224; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2847 = _T_2559 ? btb_bank0_rd_data_way0_out_224 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3102 = _T_3101 | _T_2847; // @[Mux.scala 27:72]
|
|
wire _T_2561 = btb_rd_addr_f == 8'he1; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_225; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2848 = _T_2561 ? btb_bank0_rd_data_way0_out_225 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3103 = _T_3102 | _T_2848; // @[Mux.scala 27:72]
|
|
wire _T_2563 = btb_rd_addr_f == 8'he2; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_226; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2849 = _T_2563 ? btb_bank0_rd_data_way0_out_226 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3104 = _T_3103 | _T_2849; // @[Mux.scala 27:72]
|
|
wire _T_2565 = btb_rd_addr_f == 8'he3; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_227; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2850 = _T_2565 ? btb_bank0_rd_data_way0_out_227 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3105 = _T_3104 | _T_2850; // @[Mux.scala 27:72]
|
|
wire _T_2567 = btb_rd_addr_f == 8'he4; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_228; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2851 = _T_2567 ? btb_bank0_rd_data_way0_out_228 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3106 = _T_3105 | _T_2851; // @[Mux.scala 27:72]
|
|
wire _T_2569 = btb_rd_addr_f == 8'he5; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_229; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2852 = _T_2569 ? btb_bank0_rd_data_way0_out_229 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3107 = _T_3106 | _T_2852; // @[Mux.scala 27:72]
|
|
wire _T_2571 = btb_rd_addr_f == 8'he6; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_230; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2853 = _T_2571 ? btb_bank0_rd_data_way0_out_230 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3108 = _T_3107 | _T_2853; // @[Mux.scala 27:72]
|
|
wire _T_2573 = btb_rd_addr_f == 8'he7; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_231; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2854 = _T_2573 ? btb_bank0_rd_data_way0_out_231 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3109 = _T_3108 | _T_2854; // @[Mux.scala 27:72]
|
|
wire _T_2575 = btb_rd_addr_f == 8'he8; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_232; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2855 = _T_2575 ? btb_bank0_rd_data_way0_out_232 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3110 = _T_3109 | _T_2855; // @[Mux.scala 27:72]
|
|
wire _T_2577 = btb_rd_addr_f == 8'he9; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_233; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2856 = _T_2577 ? btb_bank0_rd_data_way0_out_233 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3111 = _T_3110 | _T_2856; // @[Mux.scala 27:72]
|
|
wire _T_2579 = btb_rd_addr_f == 8'hea; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_234; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2857 = _T_2579 ? btb_bank0_rd_data_way0_out_234 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3112 = _T_3111 | _T_2857; // @[Mux.scala 27:72]
|
|
wire _T_2581 = btb_rd_addr_f == 8'heb; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_235; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2858 = _T_2581 ? btb_bank0_rd_data_way0_out_235 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3113 = _T_3112 | _T_2858; // @[Mux.scala 27:72]
|
|
wire _T_2583 = btb_rd_addr_f == 8'hec; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_236; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2859 = _T_2583 ? btb_bank0_rd_data_way0_out_236 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3114 = _T_3113 | _T_2859; // @[Mux.scala 27:72]
|
|
wire _T_2585 = btb_rd_addr_f == 8'hed; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_237; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2860 = _T_2585 ? btb_bank0_rd_data_way0_out_237 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3115 = _T_3114 | _T_2860; // @[Mux.scala 27:72]
|
|
wire _T_2587 = btb_rd_addr_f == 8'hee; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_238; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2861 = _T_2587 ? btb_bank0_rd_data_way0_out_238 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3116 = _T_3115 | _T_2861; // @[Mux.scala 27:72]
|
|
wire _T_2589 = btb_rd_addr_f == 8'hef; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_239; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2862 = _T_2589 ? btb_bank0_rd_data_way0_out_239 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3117 = _T_3116 | _T_2862; // @[Mux.scala 27:72]
|
|
wire _T_2591 = btb_rd_addr_f == 8'hf0; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_240; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2863 = _T_2591 ? btb_bank0_rd_data_way0_out_240 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3118 = _T_3117 | _T_2863; // @[Mux.scala 27:72]
|
|
wire _T_2593 = btb_rd_addr_f == 8'hf1; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_241; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2864 = _T_2593 ? btb_bank0_rd_data_way0_out_241 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3119 = _T_3118 | _T_2864; // @[Mux.scala 27:72]
|
|
wire _T_2595 = btb_rd_addr_f == 8'hf2; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_242; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2865 = _T_2595 ? btb_bank0_rd_data_way0_out_242 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3120 = _T_3119 | _T_2865; // @[Mux.scala 27:72]
|
|
wire _T_2597 = btb_rd_addr_f == 8'hf3; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_243; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2866 = _T_2597 ? btb_bank0_rd_data_way0_out_243 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3121 = _T_3120 | _T_2866; // @[Mux.scala 27:72]
|
|
wire _T_2599 = btb_rd_addr_f == 8'hf4; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_244; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2867 = _T_2599 ? btb_bank0_rd_data_way0_out_244 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3122 = _T_3121 | _T_2867; // @[Mux.scala 27:72]
|
|
wire _T_2601 = btb_rd_addr_f == 8'hf5; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_245; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2868 = _T_2601 ? btb_bank0_rd_data_way0_out_245 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3123 = _T_3122 | _T_2868; // @[Mux.scala 27:72]
|
|
wire _T_2603 = btb_rd_addr_f == 8'hf6; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_246; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2869 = _T_2603 ? btb_bank0_rd_data_way0_out_246 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3124 = _T_3123 | _T_2869; // @[Mux.scala 27:72]
|
|
wire _T_2605 = btb_rd_addr_f == 8'hf7; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_247; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2870 = _T_2605 ? btb_bank0_rd_data_way0_out_247 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3125 = _T_3124 | _T_2870; // @[Mux.scala 27:72]
|
|
wire _T_2607 = btb_rd_addr_f == 8'hf8; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_248; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2871 = _T_2607 ? btb_bank0_rd_data_way0_out_248 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3126 = _T_3125 | _T_2871; // @[Mux.scala 27:72]
|
|
wire _T_2609 = btb_rd_addr_f == 8'hf9; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_249; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2872 = _T_2609 ? btb_bank0_rd_data_way0_out_249 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3127 = _T_3126 | _T_2872; // @[Mux.scala 27:72]
|
|
wire _T_2611 = btb_rd_addr_f == 8'hfa; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_250; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2873 = _T_2611 ? btb_bank0_rd_data_way0_out_250 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3128 = _T_3127 | _T_2873; // @[Mux.scala 27:72]
|
|
wire _T_2613 = btb_rd_addr_f == 8'hfb; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_251; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2874 = _T_2613 ? btb_bank0_rd_data_way0_out_251 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3129 = _T_3128 | _T_2874; // @[Mux.scala 27:72]
|
|
wire _T_2615 = btb_rd_addr_f == 8'hfc; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_252; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2875 = _T_2615 ? btb_bank0_rd_data_way0_out_252 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3130 = _T_3129 | _T_2875; // @[Mux.scala 27:72]
|
|
wire _T_2617 = btb_rd_addr_f == 8'hfd; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_253; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2876 = _T_2617 ? btb_bank0_rd_data_way0_out_253 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3131 = _T_3130 | _T_2876; // @[Mux.scala 27:72]
|
|
wire _T_2619 = btb_rd_addr_f == 8'hfe; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_254; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2877 = _T_2619 ? btb_bank0_rd_data_way0_out_254 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3132 = _T_3131 | _T_2877; // @[Mux.scala 27:72]
|
|
wire _T_2621 = btb_rd_addr_f == 8'hff; // @[el2_ifu_bp_ctl.scala 430:77]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_255; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_2878 = _T_2621 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_bank0_rd_data_way0_f = _T_3132 | _T_2878; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_25 = io_ifc_fetch_addr_f[13:9] ^ io_ifc_fetch_addr_f[18:14]; // @[el2_lib.scala 182:111]
|
|
wire [4:0] fetch_rd_tag_f = _T_25 ^ io_ifc_fetch_addr_f[23:19]; // @[el2_lib.scala 182:111]
|
|
wire _T_45 = btb_bank0_rd_data_way0_f[21:17] == fetch_rd_tag_f; // @[el2_ifu_bp_ctl.scala 139:97]
|
|
wire _T_46 = btb_bank0_rd_data_way0_f[0] & _T_45; // @[el2_ifu_bp_ctl.scala 139:55]
|
|
reg dec_tlu_way_wb_f; // @[el2_ifu_bp_ctl.scala 130:59]
|
|
wire _T_19 = io_exu_i0_br_index_r == btb_rd_addr_f; // @[el2_ifu_bp_ctl.scala 114:72]
|
|
wire branch_error_collision_f = dec_tlu_error_wb & _T_19; // @[el2_ifu_bp_ctl.scala 114:51]
|
|
wire branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 118:63]
|
|
wire _T_47 = dec_tlu_way_wb_f & branch_error_bank_conflict_f; // @[el2_ifu_bp_ctl.scala 140:44]
|
|
wire _T_48 = ~_T_47; // @[el2_ifu_bp_ctl.scala 140:25]
|
|
wire _T_49 = _T_46 & _T_48; // @[el2_ifu_bp_ctl.scala 139:117]
|
|
wire _T_50 = _T_49 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 140:76]
|
|
wire tag_match_way0_f = _T_50 & _T; // @[el2_ifu_bp_ctl.scala 140:97]
|
|
wire _T_81 = btb_bank0_rd_data_way0_f[3] ^ btb_bank0_rd_data_way0_f[4]; // @[el2_ifu_bp_ctl.scala 154:91]
|
|
wire _T_82 = tag_match_way0_f & _T_81; // @[el2_ifu_bp_ctl.scala 154:56]
|
|
wire _T_86 = ~_T_81; // @[el2_ifu_bp_ctl.scala 155:58]
|
|
wire _T_87 = tag_match_way0_f & _T_86; // @[el2_ifu_bp_ctl.scala 155:56]
|
|
wire [1:0] tag_match_way0_expanded_f = {_T_82,_T_87}; // @[Cat.scala 29:58]
|
|
wire [21:0] _T_126 = tag_match_way0_expanded_f[1] ? btb_bank0_rd_data_way0_f : 22'h0; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_0; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3647 = _T_2111 ? btb_bank0_rd_data_way1_out_0 : 22'h0; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_1; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3648 = _T_2113 ? btb_bank0_rd_data_way1_out_1 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3903 = _T_3647 | _T_3648; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_2; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3649 = _T_2115 ? btb_bank0_rd_data_way1_out_2 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3904 = _T_3903 | _T_3649; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_3; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3650 = _T_2117 ? btb_bank0_rd_data_way1_out_3 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3905 = _T_3904 | _T_3650; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_4; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3651 = _T_2119 ? btb_bank0_rd_data_way1_out_4 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3906 = _T_3905 | _T_3651; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_5; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3652 = _T_2121 ? btb_bank0_rd_data_way1_out_5 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3907 = _T_3906 | _T_3652; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_6; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3653 = _T_2123 ? btb_bank0_rd_data_way1_out_6 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3908 = _T_3907 | _T_3653; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_7; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3654 = _T_2125 ? btb_bank0_rd_data_way1_out_7 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3909 = _T_3908 | _T_3654; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_8; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3655 = _T_2127 ? btb_bank0_rd_data_way1_out_8 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3910 = _T_3909 | _T_3655; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_9; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3656 = _T_2129 ? btb_bank0_rd_data_way1_out_9 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3911 = _T_3910 | _T_3656; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_10; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3657 = _T_2131 ? btb_bank0_rd_data_way1_out_10 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3912 = _T_3911 | _T_3657; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_11; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3658 = _T_2133 ? btb_bank0_rd_data_way1_out_11 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3913 = _T_3912 | _T_3658; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_12; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3659 = _T_2135 ? btb_bank0_rd_data_way1_out_12 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3914 = _T_3913 | _T_3659; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_13; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3660 = _T_2137 ? btb_bank0_rd_data_way1_out_13 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3915 = _T_3914 | _T_3660; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_14; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3661 = _T_2139 ? btb_bank0_rd_data_way1_out_14 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3916 = _T_3915 | _T_3661; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_15; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3662 = _T_2141 ? btb_bank0_rd_data_way1_out_15 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3917 = _T_3916 | _T_3662; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_16; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3663 = _T_2143 ? btb_bank0_rd_data_way1_out_16 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3918 = _T_3917 | _T_3663; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_17; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3664 = _T_2145 ? btb_bank0_rd_data_way1_out_17 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3919 = _T_3918 | _T_3664; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_18; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3665 = _T_2147 ? btb_bank0_rd_data_way1_out_18 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3920 = _T_3919 | _T_3665; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_19; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3666 = _T_2149 ? btb_bank0_rd_data_way1_out_19 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3921 = _T_3920 | _T_3666; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_20; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3667 = _T_2151 ? btb_bank0_rd_data_way1_out_20 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3922 = _T_3921 | _T_3667; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_21; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3668 = _T_2153 ? btb_bank0_rd_data_way1_out_21 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3923 = _T_3922 | _T_3668; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_22; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3669 = _T_2155 ? btb_bank0_rd_data_way1_out_22 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3924 = _T_3923 | _T_3669; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_23; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3670 = _T_2157 ? btb_bank0_rd_data_way1_out_23 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3925 = _T_3924 | _T_3670; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_24; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3671 = _T_2159 ? btb_bank0_rd_data_way1_out_24 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3926 = _T_3925 | _T_3671; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_25; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3672 = _T_2161 ? btb_bank0_rd_data_way1_out_25 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3927 = _T_3926 | _T_3672; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_26; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3673 = _T_2163 ? btb_bank0_rd_data_way1_out_26 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3928 = _T_3927 | _T_3673; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_27; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3674 = _T_2165 ? btb_bank0_rd_data_way1_out_27 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3929 = _T_3928 | _T_3674; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_28; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3675 = _T_2167 ? btb_bank0_rd_data_way1_out_28 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3930 = _T_3929 | _T_3675; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_29; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3676 = _T_2169 ? btb_bank0_rd_data_way1_out_29 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3931 = _T_3930 | _T_3676; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_30; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3677 = _T_2171 ? btb_bank0_rd_data_way1_out_30 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3932 = _T_3931 | _T_3677; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_31; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3678 = _T_2173 ? btb_bank0_rd_data_way1_out_31 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3933 = _T_3932 | _T_3678; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_32; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3679 = _T_2175 ? btb_bank0_rd_data_way1_out_32 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3934 = _T_3933 | _T_3679; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_33; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3680 = _T_2177 ? btb_bank0_rd_data_way1_out_33 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3935 = _T_3934 | _T_3680; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_34; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3681 = _T_2179 ? btb_bank0_rd_data_way1_out_34 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3936 = _T_3935 | _T_3681; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_35; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3682 = _T_2181 ? btb_bank0_rd_data_way1_out_35 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3937 = _T_3936 | _T_3682; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_36; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3683 = _T_2183 ? btb_bank0_rd_data_way1_out_36 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3938 = _T_3937 | _T_3683; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_37; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3684 = _T_2185 ? btb_bank0_rd_data_way1_out_37 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3939 = _T_3938 | _T_3684; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_38; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3685 = _T_2187 ? btb_bank0_rd_data_way1_out_38 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3940 = _T_3939 | _T_3685; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_39; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3686 = _T_2189 ? btb_bank0_rd_data_way1_out_39 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3941 = _T_3940 | _T_3686; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_40; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3687 = _T_2191 ? btb_bank0_rd_data_way1_out_40 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3942 = _T_3941 | _T_3687; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_41; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3688 = _T_2193 ? btb_bank0_rd_data_way1_out_41 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3943 = _T_3942 | _T_3688; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_42; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3689 = _T_2195 ? btb_bank0_rd_data_way1_out_42 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3944 = _T_3943 | _T_3689; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_43; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3690 = _T_2197 ? btb_bank0_rd_data_way1_out_43 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3945 = _T_3944 | _T_3690; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_44; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3691 = _T_2199 ? btb_bank0_rd_data_way1_out_44 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3946 = _T_3945 | _T_3691; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_45; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3692 = _T_2201 ? btb_bank0_rd_data_way1_out_45 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3947 = _T_3946 | _T_3692; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_46; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3693 = _T_2203 ? btb_bank0_rd_data_way1_out_46 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3948 = _T_3947 | _T_3693; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_47; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3694 = _T_2205 ? btb_bank0_rd_data_way1_out_47 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3949 = _T_3948 | _T_3694; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_48; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3695 = _T_2207 ? btb_bank0_rd_data_way1_out_48 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3950 = _T_3949 | _T_3695; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_49; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3696 = _T_2209 ? btb_bank0_rd_data_way1_out_49 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3951 = _T_3950 | _T_3696; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_50; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3697 = _T_2211 ? btb_bank0_rd_data_way1_out_50 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3952 = _T_3951 | _T_3697; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_51; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3698 = _T_2213 ? btb_bank0_rd_data_way1_out_51 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3953 = _T_3952 | _T_3698; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_52; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3699 = _T_2215 ? btb_bank0_rd_data_way1_out_52 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3954 = _T_3953 | _T_3699; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_53; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3700 = _T_2217 ? btb_bank0_rd_data_way1_out_53 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3955 = _T_3954 | _T_3700; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_54; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3701 = _T_2219 ? btb_bank0_rd_data_way1_out_54 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3956 = _T_3955 | _T_3701; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_55; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3702 = _T_2221 ? btb_bank0_rd_data_way1_out_55 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3957 = _T_3956 | _T_3702; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_56; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3703 = _T_2223 ? btb_bank0_rd_data_way1_out_56 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3958 = _T_3957 | _T_3703; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_57; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3704 = _T_2225 ? btb_bank0_rd_data_way1_out_57 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3959 = _T_3958 | _T_3704; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_58; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3705 = _T_2227 ? btb_bank0_rd_data_way1_out_58 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3960 = _T_3959 | _T_3705; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_59; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3706 = _T_2229 ? btb_bank0_rd_data_way1_out_59 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3961 = _T_3960 | _T_3706; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_60; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3707 = _T_2231 ? btb_bank0_rd_data_way1_out_60 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3962 = _T_3961 | _T_3707; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_61; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3708 = _T_2233 ? btb_bank0_rd_data_way1_out_61 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3963 = _T_3962 | _T_3708; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_62; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3709 = _T_2235 ? btb_bank0_rd_data_way1_out_62 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3964 = _T_3963 | _T_3709; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_63; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3710 = _T_2237 ? btb_bank0_rd_data_way1_out_63 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3965 = _T_3964 | _T_3710; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_64; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3711 = _T_2239 ? btb_bank0_rd_data_way1_out_64 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3966 = _T_3965 | _T_3711; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_65; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3712 = _T_2241 ? btb_bank0_rd_data_way1_out_65 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3967 = _T_3966 | _T_3712; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_66; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3713 = _T_2243 ? btb_bank0_rd_data_way1_out_66 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3968 = _T_3967 | _T_3713; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_67; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3714 = _T_2245 ? btb_bank0_rd_data_way1_out_67 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3969 = _T_3968 | _T_3714; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_68; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3715 = _T_2247 ? btb_bank0_rd_data_way1_out_68 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3970 = _T_3969 | _T_3715; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_69; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3716 = _T_2249 ? btb_bank0_rd_data_way1_out_69 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3971 = _T_3970 | _T_3716; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_70; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3717 = _T_2251 ? btb_bank0_rd_data_way1_out_70 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3972 = _T_3971 | _T_3717; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_71; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3718 = _T_2253 ? btb_bank0_rd_data_way1_out_71 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3973 = _T_3972 | _T_3718; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_72; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3719 = _T_2255 ? btb_bank0_rd_data_way1_out_72 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3974 = _T_3973 | _T_3719; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_73; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3720 = _T_2257 ? btb_bank0_rd_data_way1_out_73 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3975 = _T_3974 | _T_3720; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_74; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3721 = _T_2259 ? btb_bank0_rd_data_way1_out_74 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3976 = _T_3975 | _T_3721; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_75; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3722 = _T_2261 ? btb_bank0_rd_data_way1_out_75 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3977 = _T_3976 | _T_3722; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_76; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3723 = _T_2263 ? btb_bank0_rd_data_way1_out_76 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3978 = _T_3977 | _T_3723; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_77; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3724 = _T_2265 ? btb_bank0_rd_data_way1_out_77 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3979 = _T_3978 | _T_3724; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_78; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3725 = _T_2267 ? btb_bank0_rd_data_way1_out_78 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3980 = _T_3979 | _T_3725; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_79; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3726 = _T_2269 ? btb_bank0_rd_data_way1_out_79 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3981 = _T_3980 | _T_3726; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_80; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3727 = _T_2271 ? btb_bank0_rd_data_way1_out_80 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3982 = _T_3981 | _T_3727; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_81; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3728 = _T_2273 ? btb_bank0_rd_data_way1_out_81 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3983 = _T_3982 | _T_3728; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_82; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3729 = _T_2275 ? btb_bank0_rd_data_way1_out_82 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3984 = _T_3983 | _T_3729; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_83; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3730 = _T_2277 ? btb_bank0_rd_data_way1_out_83 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3985 = _T_3984 | _T_3730; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_84; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3731 = _T_2279 ? btb_bank0_rd_data_way1_out_84 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3986 = _T_3985 | _T_3731; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_85; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3732 = _T_2281 ? btb_bank0_rd_data_way1_out_85 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3987 = _T_3986 | _T_3732; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_86; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3733 = _T_2283 ? btb_bank0_rd_data_way1_out_86 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3988 = _T_3987 | _T_3733; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_87; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3734 = _T_2285 ? btb_bank0_rd_data_way1_out_87 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3989 = _T_3988 | _T_3734; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_88; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3735 = _T_2287 ? btb_bank0_rd_data_way1_out_88 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3990 = _T_3989 | _T_3735; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_89; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3736 = _T_2289 ? btb_bank0_rd_data_way1_out_89 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3991 = _T_3990 | _T_3736; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_90; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3737 = _T_2291 ? btb_bank0_rd_data_way1_out_90 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3992 = _T_3991 | _T_3737; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_91; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3738 = _T_2293 ? btb_bank0_rd_data_way1_out_91 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3993 = _T_3992 | _T_3738; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_92; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3739 = _T_2295 ? btb_bank0_rd_data_way1_out_92 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3994 = _T_3993 | _T_3739; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_93; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3740 = _T_2297 ? btb_bank0_rd_data_way1_out_93 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3995 = _T_3994 | _T_3740; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_94; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3741 = _T_2299 ? btb_bank0_rd_data_way1_out_94 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3996 = _T_3995 | _T_3741; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_95; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3742 = _T_2301 ? btb_bank0_rd_data_way1_out_95 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3997 = _T_3996 | _T_3742; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_96; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3743 = _T_2303 ? btb_bank0_rd_data_way1_out_96 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3998 = _T_3997 | _T_3743; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_97; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3744 = _T_2305 ? btb_bank0_rd_data_way1_out_97 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3999 = _T_3998 | _T_3744; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_98; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3745 = _T_2307 ? btb_bank0_rd_data_way1_out_98 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4000 = _T_3999 | _T_3745; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_99; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3746 = _T_2309 ? btb_bank0_rd_data_way1_out_99 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4001 = _T_4000 | _T_3746; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_100; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3747 = _T_2311 ? btb_bank0_rd_data_way1_out_100 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4002 = _T_4001 | _T_3747; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_101; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3748 = _T_2313 ? btb_bank0_rd_data_way1_out_101 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4003 = _T_4002 | _T_3748; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_102; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3749 = _T_2315 ? btb_bank0_rd_data_way1_out_102 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4004 = _T_4003 | _T_3749; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_103; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3750 = _T_2317 ? btb_bank0_rd_data_way1_out_103 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4005 = _T_4004 | _T_3750; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_104; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3751 = _T_2319 ? btb_bank0_rd_data_way1_out_104 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4006 = _T_4005 | _T_3751; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_105; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3752 = _T_2321 ? btb_bank0_rd_data_way1_out_105 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4007 = _T_4006 | _T_3752; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_106; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3753 = _T_2323 ? btb_bank0_rd_data_way1_out_106 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4008 = _T_4007 | _T_3753; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_107; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3754 = _T_2325 ? btb_bank0_rd_data_way1_out_107 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4009 = _T_4008 | _T_3754; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_108; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3755 = _T_2327 ? btb_bank0_rd_data_way1_out_108 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4010 = _T_4009 | _T_3755; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_109; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3756 = _T_2329 ? btb_bank0_rd_data_way1_out_109 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4011 = _T_4010 | _T_3756; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_110; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3757 = _T_2331 ? btb_bank0_rd_data_way1_out_110 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4012 = _T_4011 | _T_3757; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_111; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3758 = _T_2333 ? btb_bank0_rd_data_way1_out_111 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4013 = _T_4012 | _T_3758; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_112; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3759 = _T_2335 ? btb_bank0_rd_data_way1_out_112 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4014 = _T_4013 | _T_3759; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_113; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3760 = _T_2337 ? btb_bank0_rd_data_way1_out_113 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4015 = _T_4014 | _T_3760; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_114; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3761 = _T_2339 ? btb_bank0_rd_data_way1_out_114 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4016 = _T_4015 | _T_3761; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_115; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3762 = _T_2341 ? btb_bank0_rd_data_way1_out_115 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4017 = _T_4016 | _T_3762; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_116; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3763 = _T_2343 ? btb_bank0_rd_data_way1_out_116 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4018 = _T_4017 | _T_3763; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_117; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3764 = _T_2345 ? btb_bank0_rd_data_way1_out_117 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4019 = _T_4018 | _T_3764; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_118; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3765 = _T_2347 ? btb_bank0_rd_data_way1_out_118 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4020 = _T_4019 | _T_3765; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_119; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3766 = _T_2349 ? btb_bank0_rd_data_way1_out_119 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4021 = _T_4020 | _T_3766; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_120; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3767 = _T_2351 ? btb_bank0_rd_data_way1_out_120 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4022 = _T_4021 | _T_3767; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_121; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3768 = _T_2353 ? btb_bank0_rd_data_way1_out_121 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4023 = _T_4022 | _T_3768; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_122; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3769 = _T_2355 ? btb_bank0_rd_data_way1_out_122 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4024 = _T_4023 | _T_3769; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_123; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3770 = _T_2357 ? btb_bank0_rd_data_way1_out_123 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4025 = _T_4024 | _T_3770; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_124; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3771 = _T_2359 ? btb_bank0_rd_data_way1_out_124 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4026 = _T_4025 | _T_3771; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_125; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3772 = _T_2361 ? btb_bank0_rd_data_way1_out_125 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4027 = _T_4026 | _T_3772; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_126; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3773 = _T_2363 ? btb_bank0_rd_data_way1_out_126 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4028 = _T_4027 | _T_3773; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_127; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3774 = _T_2365 ? btb_bank0_rd_data_way1_out_127 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4029 = _T_4028 | _T_3774; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_128; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3775 = _T_2367 ? btb_bank0_rd_data_way1_out_128 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4030 = _T_4029 | _T_3775; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_129; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3776 = _T_2369 ? btb_bank0_rd_data_way1_out_129 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4031 = _T_4030 | _T_3776; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_130; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3777 = _T_2371 ? btb_bank0_rd_data_way1_out_130 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4032 = _T_4031 | _T_3777; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_131; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3778 = _T_2373 ? btb_bank0_rd_data_way1_out_131 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4033 = _T_4032 | _T_3778; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_132; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3779 = _T_2375 ? btb_bank0_rd_data_way1_out_132 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4034 = _T_4033 | _T_3779; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_133; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3780 = _T_2377 ? btb_bank0_rd_data_way1_out_133 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4035 = _T_4034 | _T_3780; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_134; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3781 = _T_2379 ? btb_bank0_rd_data_way1_out_134 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4036 = _T_4035 | _T_3781; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_135; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3782 = _T_2381 ? btb_bank0_rd_data_way1_out_135 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4037 = _T_4036 | _T_3782; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_136; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3783 = _T_2383 ? btb_bank0_rd_data_way1_out_136 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4038 = _T_4037 | _T_3783; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_137; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3784 = _T_2385 ? btb_bank0_rd_data_way1_out_137 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4039 = _T_4038 | _T_3784; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_138; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3785 = _T_2387 ? btb_bank0_rd_data_way1_out_138 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4040 = _T_4039 | _T_3785; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_139; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3786 = _T_2389 ? btb_bank0_rd_data_way1_out_139 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4041 = _T_4040 | _T_3786; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_140; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3787 = _T_2391 ? btb_bank0_rd_data_way1_out_140 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4042 = _T_4041 | _T_3787; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_141; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3788 = _T_2393 ? btb_bank0_rd_data_way1_out_141 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4043 = _T_4042 | _T_3788; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_142; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3789 = _T_2395 ? btb_bank0_rd_data_way1_out_142 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4044 = _T_4043 | _T_3789; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_143; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3790 = _T_2397 ? btb_bank0_rd_data_way1_out_143 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4045 = _T_4044 | _T_3790; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_144; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3791 = _T_2399 ? btb_bank0_rd_data_way1_out_144 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4046 = _T_4045 | _T_3791; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_145; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3792 = _T_2401 ? btb_bank0_rd_data_way1_out_145 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4047 = _T_4046 | _T_3792; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_146; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3793 = _T_2403 ? btb_bank0_rd_data_way1_out_146 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4048 = _T_4047 | _T_3793; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_147; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3794 = _T_2405 ? btb_bank0_rd_data_way1_out_147 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4049 = _T_4048 | _T_3794; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_148; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3795 = _T_2407 ? btb_bank0_rd_data_way1_out_148 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4050 = _T_4049 | _T_3795; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_149; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3796 = _T_2409 ? btb_bank0_rd_data_way1_out_149 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4051 = _T_4050 | _T_3796; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_150; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3797 = _T_2411 ? btb_bank0_rd_data_way1_out_150 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4052 = _T_4051 | _T_3797; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_151; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3798 = _T_2413 ? btb_bank0_rd_data_way1_out_151 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4053 = _T_4052 | _T_3798; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_152; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3799 = _T_2415 ? btb_bank0_rd_data_way1_out_152 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4054 = _T_4053 | _T_3799; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_153; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3800 = _T_2417 ? btb_bank0_rd_data_way1_out_153 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4055 = _T_4054 | _T_3800; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_154; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3801 = _T_2419 ? btb_bank0_rd_data_way1_out_154 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4056 = _T_4055 | _T_3801; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_155; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3802 = _T_2421 ? btb_bank0_rd_data_way1_out_155 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4057 = _T_4056 | _T_3802; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_156; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3803 = _T_2423 ? btb_bank0_rd_data_way1_out_156 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4058 = _T_4057 | _T_3803; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_157; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3804 = _T_2425 ? btb_bank0_rd_data_way1_out_157 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4059 = _T_4058 | _T_3804; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_158; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3805 = _T_2427 ? btb_bank0_rd_data_way1_out_158 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4060 = _T_4059 | _T_3805; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_159; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3806 = _T_2429 ? btb_bank0_rd_data_way1_out_159 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4061 = _T_4060 | _T_3806; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_160; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3807 = _T_2431 ? btb_bank0_rd_data_way1_out_160 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4062 = _T_4061 | _T_3807; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_161; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3808 = _T_2433 ? btb_bank0_rd_data_way1_out_161 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4063 = _T_4062 | _T_3808; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_162; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3809 = _T_2435 ? btb_bank0_rd_data_way1_out_162 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4064 = _T_4063 | _T_3809; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_163; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3810 = _T_2437 ? btb_bank0_rd_data_way1_out_163 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4065 = _T_4064 | _T_3810; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_164; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3811 = _T_2439 ? btb_bank0_rd_data_way1_out_164 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4066 = _T_4065 | _T_3811; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_165; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3812 = _T_2441 ? btb_bank0_rd_data_way1_out_165 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4067 = _T_4066 | _T_3812; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_166; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3813 = _T_2443 ? btb_bank0_rd_data_way1_out_166 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4068 = _T_4067 | _T_3813; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_167; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3814 = _T_2445 ? btb_bank0_rd_data_way1_out_167 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4069 = _T_4068 | _T_3814; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_168; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3815 = _T_2447 ? btb_bank0_rd_data_way1_out_168 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4070 = _T_4069 | _T_3815; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_169; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3816 = _T_2449 ? btb_bank0_rd_data_way1_out_169 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4071 = _T_4070 | _T_3816; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_170; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3817 = _T_2451 ? btb_bank0_rd_data_way1_out_170 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4072 = _T_4071 | _T_3817; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_171; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3818 = _T_2453 ? btb_bank0_rd_data_way1_out_171 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4073 = _T_4072 | _T_3818; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_172; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3819 = _T_2455 ? btb_bank0_rd_data_way1_out_172 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4074 = _T_4073 | _T_3819; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_173; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3820 = _T_2457 ? btb_bank0_rd_data_way1_out_173 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4075 = _T_4074 | _T_3820; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_174; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3821 = _T_2459 ? btb_bank0_rd_data_way1_out_174 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4076 = _T_4075 | _T_3821; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_175; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3822 = _T_2461 ? btb_bank0_rd_data_way1_out_175 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4077 = _T_4076 | _T_3822; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_176; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3823 = _T_2463 ? btb_bank0_rd_data_way1_out_176 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4078 = _T_4077 | _T_3823; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_177; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3824 = _T_2465 ? btb_bank0_rd_data_way1_out_177 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4079 = _T_4078 | _T_3824; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_178; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3825 = _T_2467 ? btb_bank0_rd_data_way1_out_178 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4080 = _T_4079 | _T_3825; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_179; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3826 = _T_2469 ? btb_bank0_rd_data_way1_out_179 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4081 = _T_4080 | _T_3826; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_180; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3827 = _T_2471 ? btb_bank0_rd_data_way1_out_180 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4082 = _T_4081 | _T_3827; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_181; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3828 = _T_2473 ? btb_bank0_rd_data_way1_out_181 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4083 = _T_4082 | _T_3828; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_182; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3829 = _T_2475 ? btb_bank0_rd_data_way1_out_182 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4084 = _T_4083 | _T_3829; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_183; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3830 = _T_2477 ? btb_bank0_rd_data_way1_out_183 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4085 = _T_4084 | _T_3830; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_184; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3831 = _T_2479 ? btb_bank0_rd_data_way1_out_184 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4086 = _T_4085 | _T_3831; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_185; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3832 = _T_2481 ? btb_bank0_rd_data_way1_out_185 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4087 = _T_4086 | _T_3832; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_186; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3833 = _T_2483 ? btb_bank0_rd_data_way1_out_186 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4088 = _T_4087 | _T_3833; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_187; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3834 = _T_2485 ? btb_bank0_rd_data_way1_out_187 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4089 = _T_4088 | _T_3834; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_188; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3835 = _T_2487 ? btb_bank0_rd_data_way1_out_188 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4090 = _T_4089 | _T_3835; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_189; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3836 = _T_2489 ? btb_bank0_rd_data_way1_out_189 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4091 = _T_4090 | _T_3836; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_190; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3837 = _T_2491 ? btb_bank0_rd_data_way1_out_190 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4092 = _T_4091 | _T_3837; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_191; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3838 = _T_2493 ? btb_bank0_rd_data_way1_out_191 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4093 = _T_4092 | _T_3838; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_192; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3839 = _T_2495 ? btb_bank0_rd_data_way1_out_192 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4094 = _T_4093 | _T_3839; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_193; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3840 = _T_2497 ? btb_bank0_rd_data_way1_out_193 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4095 = _T_4094 | _T_3840; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_194; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3841 = _T_2499 ? btb_bank0_rd_data_way1_out_194 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4096 = _T_4095 | _T_3841; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_195; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3842 = _T_2501 ? btb_bank0_rd_data_way1_out_195 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4097 = _T_4096 | _T_3842; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_196; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3843 = _T_2503 ? btb_bank0_rd_data_way1_out_196 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4098 = _T_4097 | _T_3843; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_197; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3844 = _T_2505 ? btb_bank0_rd_data_way1_out_197 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4099 = _T_4098 | _T_3844; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_198; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3845 = _T_2507 ? btb_bank0_rd_data_way1_out_198 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4100 = _T_4099 | _T_3845; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_199; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3846 = _T_2509 ? btb_bank0_rd_data_way1_out_199 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4101 = _T_4100 | _T_3846; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_200; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3847 = _T_2511 ? btb_bank0_rd_data_way1_out_200 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4102 = _T_4101 | _T_3847; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_201; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3848 = _T_2513 ? btb_bank0_rd_data_way1_out_201 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4103 = _T_4102 | _T_3848; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_202; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3849 = _T_2515 ? btb_bank0_rd_data_way1_out_202 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4104 = _T_4103 | _T_3849; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_203; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3850 = _T_2517 ? btb_bank0_rd_data_way1_out_203 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4105 = _T_4104 | _T_3850; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_204; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3851 = _T_2519 ? btb_bank0_rd_data_way1_out_204 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4106 = _T_4105 | _T_3851; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_205; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3852 = _T_2521 ? btb_bank0_rd_data_way1_out_205 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4107 = _T_4106 | _T_3852; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_206; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3853 = _T_2523 ? btb_bank0_rd_data_way1_out_206 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4108 = _T_4107 | _T_3853; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_207; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3854 = _T_2525 ? btb_bank0_rd_data_way1_out_207 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4109 = _T_4108 | _T_3854; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_208; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3855 = _T_2527 ? btb_bank0_rd_data_way1_out_208 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4110 = _T_4109 | _T_3855; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_209; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3856 = _T_2529 ? btb_bank0_rd_data_way1_out_209 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4111 = _T_4110 | _T_3856; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_210; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3857 = _T_2531 ? btb_bank0_rd_data_way1_out_210 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4112 = _T_4111 | _T_3857; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_211; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3858 = _T_2533 ? btb_bank0_rd_data_way1_out_211 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4113 = _T_4112 | _T_3858; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_212; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3859 = _T_2535 ? btb_bank0_rd_data_way1_out_212 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4114 = _T_4113 | _T_3859; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_213; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3860 = _T_2537 ? btb_bank0_rd_data_way1_out_213 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4115 = _T_4114 | _T_3860; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_214; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3861 = _T_2539 ? btb_bank0_rd_data_way1_out_214 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4116 = _T_4115 | _T_3861; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_215; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3862 = _T_2541 ? btb_bank0_rd_data_way1_out_215 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4117 = _T_4116 | _T_3862; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_216; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3863 = _T_2543 ? btb_bank0_rd_data_way1_out_216 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4118 = _T_4117 | _T_3863; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_217; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3864 = _T_2545 ? btb_bank0_rd_data_way1_out_217 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4119 = _T_4118 | _T_3864; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_218; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3865 = _T_2547 ? btb_bank0_rd_data_way1_out_218 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4120 = _T_4119 | _T_3865; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_219; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3866 = _T_2549 ? btb_bank0_rd_data_way1_out_219 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4121 = _T_4120 | _T_3866; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_220; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3867 = _T_2551 ? btb_bank0_rd_data_way1_out_220 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4122 = _T_4121 | _T_3867; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_221; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3868 = _T_2553 ? btb_bank0_rd_data_way1_out_221 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4123 = _T_4122 | _T_3868; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_222; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3869 = _T_2555 ? btb_bank0_rd_data_way1_out_222 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4124 = _T_4123 | _T_3869; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_223; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3870 = _T_2557 ? btb_bank0_rd_data_way1_out_223 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4125 = _T_4124 | _T_3870; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_224; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3871 = _T_2559 ? btb_bank0_rd_data_way1_out_224 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4126 = _T_4125 | _T_3871; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_225; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3872 = _T_2561 ? btb_bank0_rd_data_way1_out_225 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4127 = _T_4126 | _T_3872; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_226; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3873 = _T_2563 ? btb_bank0_rd_data_way1_out_226 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4128 = _T_4127 | _T_3873; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_227; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3874 = _T_2565 ? btb_bank0_rd_data_way1_out_227 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4129 = _T_4128 | _T_3874; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_228; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3875 = _T_2567 ? btb_bank0_rd_data_way1_out_228 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4130 = _T_4129 | _T_3875; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_229; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3876 = _T_2569 ? btb_bank0_rd_data_way1_out_229 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4131 = _T_4130 | _T_3876; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_230; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3877 = _T_2571 ? btb_bank0_rd_data_way1_out_230 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4132 = _T_4131 | _T_3877; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_231; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3878 = _T_2573 ? btb_bank0_rd_data_way1_out_231 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4133 = _T_4132 | _T_3878; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_232; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3879 = _T_2575 ? btb_bank0_rd_data_way1_out_232 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4134 = _T_4133 | _T_3879; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_233; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3880 = _T_2577 ? btb_bank0_rd_data_way1_out_233 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4135 = _T_4134 | _T_3880; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_234; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3881 = _T_2579 ? btb_bank0_rd_data_way1_out_234 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4136 = _T_4135 | _T_3881; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_235; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3882 = _T_2581 ? btb_bank0_rd_data_way1_out_235 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4137 = _T_4136 | _T_3882; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_236; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3883 = _T_2583 ? btb_bank0_rd_data_way1_out_236 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4138 = _T_4137 | _T_3883; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_237; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3884 = _T_2585 ? btb_bank0_rd_data_way1_out_237 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4139 = _T_4138 | _T_3884; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_238; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3885 = _T_2587 ? btb_bank0_rd_data_way1_out_238 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4140 = _T_4139 | _T_3885; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_239; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3886 = _T_2589 ? btb_bank0_rd_data_way1_out_239 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4141 = _T_4140 | _T_3886; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_240; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3887 = _T_2591 ? btb_bank0_rd_data_way1_out_240 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4142 = _T_4141 | _T_3887; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_241; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3888 = _T_2593 ? btb_bank0_rd_data_way1_out_241 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4143 = _T_4142 | _T_3888; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_242; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3889 = _T_2595 ? btb_bank0_rd_data_way1_out_242 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4144 = _T_4143 | _T_3889; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_243; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3890 = _T_2597 ? btb_bank0_rd_data_way1_out_243 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4145 = _T_4144 | _T_3890; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_244; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3891 = _T_2599 ? btb_bank0_rd_data_way1_out_244 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4146 = _T_4145 | _T_3891; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_245; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3892 = _T_2601 ? btb_bank0_rd_data_way1_out_245 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4147 = _T_4146 | _T_3892; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_246; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3893 = _T_2603 ? btb_bank0_rd_data_way1_out_246 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4148 = _T_4147 | _T_3893; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_247; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3894 = _T_2605 ? btb_bank0_rd_data_way1_out_247 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4149 = _T_4148 | _T_3894; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_248; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3895 = _T_2607 ? btb_bank0_rd_data_way1_out_248 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4150 = _T_4149 | _T_3895; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_249; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3896 = _T_2609 ? btb_bank0_rd_data_way1_out_249 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4151 = _T_4150 | _T_3896; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_250; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3897 = _T_2611 ? btb_bank0_rd_data_way1_out_250 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4152 = _T_4151 | _T_3897; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_251; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3898 = _T_2613 ? btb_bank0_rd_data_way1_out_251 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4153 = _T_4152 | _T_3898; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_252; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3899 = _T_2615 ? btb_bank0_rd_data_way1_out_252 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4154 = _T_4153 | _T_3899; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_253; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3900 = _T_2617 ? btb_bank0_rd_data_way1_out_253 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4155 = _T_4154 | _T_3900; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_254; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3901 = _T_2619 ? btb_bank0_rd_data_way1_out_254 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4156 = _T_4155 | _T_3901; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_255; // @[el2_lib.scala 514:16]
|
|
wire [21:0] _T_3902 = _T_2621 ? btb_bank0_rd_data_way1_out_255 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_bank0_rd_data_way1_f = _T_4156 | _T_3902; // @[Mux.scala 27:72]
|
|
wire _T_54 = btb_bank0_rd_data_way1_f[21:17] == fetch_rd_tag_f; // @[el2_ifu_bp_ctl.scala 143:97]
|
|
wire _T_55 = btb_bank0_rd_data_way1_f[0] & _T_54; // @[el2_ifu_bp_ctl.scala 143:55]
|
|
wire _T_58 = _T_55 & _T_48; // @[el2_ifu_bp_ctl.scala 143:117]
|
|
wire _T_59 = _T_58 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 144:76]
|
|
wire tag_match_way1_f = _T_59 & _T; // @[el2_ifu_bp_ctl.scala 144:97]
|
|
wire _T_90 = btb_bank0_rd_data_way1_f[3] ^ btb_bank0_rd_data_way1_f[4]; // @[el2_ifu_bp_ctl.scala 157:91]
|
|
wire _T_91 = tag_match_way1_f & _T_90; // @[el2_ifu_bp_ctl.scala 157:56]
|
|
wire _T_95 = ~_T_90; // @[el2_ifu_bp_ctl.scala 158:58]
|
|
wire _T_96 = tag_match_way1_f & _T_95; // @[el2_ifu_bp_ctl.scala 158:56]
|
|
wire [1:0] tag_match_way1_expanded_f = {_T_91,_T_96}; // @[Cat.scala 29:58]
|
|
wire [21:0] _T_127 = tag_match_way1_expanded_f[1] ? btb_bank0_rd_data_way1_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_bank0o_rd_data_f = _T_126 | _T_127; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_145 = _T_143 ? btb_bank0o_rd_data_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire _T_4159 = btb_rd_addr_p1_f == 8'h0; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4671 = _T_4159 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72]
|
|
wire _T_4161 = btb_rd_addr_p1_f == 8'h1; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4672 = _T_4161 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4927 = _T_4671 | _T_4672; // @[Mux.scala 27:72]
|
|
wire _T_4163 = btb_rd_addr_p1_f == 8'h2; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4673 = _T_4163 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4928 = _T_4927 | _T_4673; // @[Mux.scala 27:72]
|
|
wire _T_4165 = btb_rd_addr_p1_f == 8'h3; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4674 = _T_4165 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4929 = _T_4928 | _T_4674; // @[Mux.scala 27:72]
|
|
wire _T_4167 = btb_rd_addr_p1_f == 8'h4; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4675 = _T_4167 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4930 = _T_4929 | _T_4675; // @[Mux.scala 27:72]
|
|
wire _T_4169 = btb_rd_addr_p1_f == 8'h5; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4676 = _T_4169 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4931 = _T_4930 | _T_4676; // @[Mux.scala 27:72]
|
|
wire _T_4171 = btb_rd_addr_p1_f == 8'h6; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4677 = _T_4171 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4932 = _T_4931 | _T_4677; // @[Mux.scala 27:72]
|
|
wire _T_4173 = btb_rd_addr_p1_f == 8'h7; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4678 = _T_4173 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4933 = _T_4932 | _T_4678; // @[Mux.scala 27:72]
|
|
wire _T_4175 = btb_rd_addr_p1_f == 8'h8; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4679 = _T_4175 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4934 = _T_4933 | _T_4679; // @[Mux.scala 27:72]
|
|
wire _T_4177 = btb_rd_addr_p1_f == 8'h9; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4680 = _T_4177 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4935 = _T_4934 | _T_4680; // @[Mux.scala 27:72]
|
|
wire _T_4179 = btb_rd_addr_p1_f == 8'ha; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4681 = _T_4179 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4936 = _T_4935 | _T_4681; // @[Mux.scala 27:72]
|
|
wire _T_4181 = btb_rd_addr_p1_f == 8'hb; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4682 = _T_4181 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4937 = _T_4936 | _T_4682; // @[Mux.scala 27:72]
|
|
wire _T_4183 = btb_rd_addr_p1_f == 8'hc; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4683 = _T_4183 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4938 = _T_4937 | _T_4683; // @[Mux.scala 27:72]
|
|
wire _T_4185 = btb_rd_addr_p1_f == 8'hd; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4684 = _T_4185 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4939 = _T_4938 | _T_4684; // @[Mux.scala 27:72]
|
|
wire _T_4187 = btb_rd_addr_p1_f == 8'he; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4685 = _T_4187 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4940 = _T_4939 | _T_4685; // @[Mux.scala 27:72]
|
|
wire _T_4189 = btb_rd_addr_p1_f == 8'hf; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4686 = _T_4189 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4941 = _T_4940 | _T_4686; // @[Mux.scala 27:72]
|
|
wire _T_4191 = btb_rd_addr_p1_f == 8'h10; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4687 = _T_4191 ? btb_bank0_rd_data_way0_out_16 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4942 = _T_4941 | _T_4687; // @[Mux.scala 27:72]
|
|
wire _T_4193 = btb_rd_addr_p1_f == 8'h11; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4688 = _T_4193 ? btb_bank0_rd_data_way0_out_17 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4943 = _T_4942 | _T_4688; // @[Mux.scala 27:72]
|
|
wire _T_4195 = btb_rd_addr_p1_f == 8'h12; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4689 = _T_4195 ? btb_bank0_rd_data_way0_out_18 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4944 = _T_4943 | _T_4689; // @[Mux.scala 27:72]
|
|
wire _T_4197 = btb_rd_addr_p1_f == 8'h13; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4690 = _T_4197 ? btb_bank0_rd_data_way0_out_19 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4945 = _T_4944 | _T_4690; // @[Mux.scala 27:72]
|
|
wire _T_4199 = btb_rd_addr_p1_f == 8'h14; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4691 = _T_4199 ? btb_bank0_rd_data_way0_out_20 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4946 = _T_4945 | _T_4691; // @[Mux.scala 27:72]
|
|
wire _T_4201 = btb_rd_addr_p1_f == 8'h15; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4692 = _T_4201 ? btb_bank0_rd_data_way0_out_21 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4947 = _T_4946 | _T_4692; // @[Mux.scala 27:72]
|
|
wire _T_4203 = btb_rd_addr_p1_f == 8'h16; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4693 = _T_4203 ? btb_bank0_rd_data_way0_out_22 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4948 = _T_4947 | _T_4693; // @[Mux.scala 27:72]
|
|
wire _T_4205 = btb_rd_addr_p1_f == 8'h17; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4694 = _T_4205 ? btb_bank0_rd_data_way0_out_23 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4949 = _T_4948 | _T_4694; // @[Mux.scala 27:72]
|
|
wire _T_4207 = btb_rd_addr_p1_f == 8'h18; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4695 = _T_4207 ? btb_bank0_rd_data_way0_out_24 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4950 = _T_4949 | _T_4695; // @[Mux.scala 27:72]
|
|
wire _T_4209 = btb_rd_addr_p1_f == 8'h19; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4696 = _T_4209 ? btb_bank0_rd_data_way0_out_25 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4951 = _T_4950 | _T_4696; // @[Mux.scala 27:72]
|
|
wire _T_4211 = btb_rd_addr_p1_f == 8'h1a; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4697 = _T_4211 ? btb_bank0_rd_data_way0_out_26 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4952 = _T_4951 | _T_4697; // @[Mux.scala 27:72]
|
|
wire _T_4213 = btb_rd_addr_p1_f == 8'h1b; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4698 = _T_4213 ? btb_bank0_rd_data_way0_out_27 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4953 = _T_4952 | _T_4698; // @[Mux.scala 27:72]
|
|
wire _T_4215 = btb_rd_addr_p1_f == 8'h1c; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4699 = _T_4215 ? btb_bank0_rd_data_way0_out_28 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4954 = _T_4953 | _T_4699; // @[Mux.scala 27:72]
|
|
wire _T_4217 = btb_rd_addr_p1_f == 8'h1d; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4700 = _T_4217 ? btb_bank0_rd_data_way0_out_29 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4955 = _T_4954 | _T_4700; // @[Mux.scala 27:72]
|
|
wire _T_4219 = btb_rd_addr_p1_f == 8'h1e; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4701 = _T_4219 ? btb_bank0_rd_data_way0_out_30 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4956 = _T_4955 | _T_4701; // @[Mux.scala 27:72]
|
|
wire _T_4221 = btb_rd_addr_p1_f == 8'h1f; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4702 = _T_4221 ? btb_bank0_rd_data_way0_out_31 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4957 = _T_4956 | _T_4702; // @[Mux.scala 27:72]
|
|
wire _T_4223 = btb_rd_addr_p1_f == 8'h20; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4703 = _T_4223 ? btb_bank0_rd_data_way0_out_32 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4958 = _T_4957 | _T_4703; // @[Mux.scala 27:72]
|
|
wire _T_4225 = btb_rd_addr_p1_f == 8'h21; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4704 = _T_4225 ? btb_bank0_rd_data_way0_out_33 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4959 = _T_4958 | _T_4704; // @[Mux.scala 27:72]
|
|
wire _T_4227 = btb_rd_addr_p1_f == 8'h22; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4705 = _T_4227 ? btb_bank0_rd_data_way0_out_34 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4960 = _T_4959 | _T_4705; // @[Mux.scala 27:72]
|
|
wire _T_4229 = btb_rd_addr_p1_f == 8'h23; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4706 = _T_4229 ? btb_bank0_rd_data_way0_out_35 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4961 = _T_4960 | _T_4706; // @[Mux.scala 27:72]
|
|
wire _T_4231 = btb_rd_addr_p1_f == 8'h24; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4707 = _T_4231 ? btb_bank0_rd_data_way0_out_36 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4962 = _T_4961 | _T_4707; // @[Mux.scala 27:72]
|
|
wire _T_4233 = btb_rd_addr_p1_f == 8'h25; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4708 = _T_4233 ? btb_bank0_rd_data_way0_out_37 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4963 = _T_4962 | _T_4708; // @[Mux.scala 27:72]
|
|
wire _T_4235 = btb_rd_addr_p1_f == 8'h26; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4709 = _T_4235 ? btb_bank0_rd_data_way0_out_38 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4964 = _T_4963 | _T_4709; // @[Mux.scala 27:72]
|
|
wire _T_4237 = btb_rd_addr_p1_f == 8'h27; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4710 = _T_4237 ? btb_bank0_rd_data_way0_out_39 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4965 = _T_4964 | _T_4710; // @[Mux.scala 27:72]
|
|
wire _T_4239 = btb_rd_addr_p1_f == 8'h28; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4711 = _T_4239 ? btb_bank0_rd_data_way0_out_40 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4966 = _T_4965 | _T_4711; // @[Mux.scala 27:72]
|
|
wire _T_4241 = btb_rd_addr_p1_f == 8'h29; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4712 = _T_4241 ? btb_bank0_rd_data_way0_out_41 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4967 = _T_4966 | _T_4712; // @[Mux.scala 27:72]
|
|
wire _T_4243 = btb_rd_addr_p1_f == 8'h2a; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4713 = _T_4243 ? btb_bank0_rd_data_way0_out_42 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4968 = _T_4967 | _T_4713; // @[Mux.scala 27:72]
|
|
wire _T_4245 = btb_rd_addr_p1_f == 8'h2b; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4714 = _T_4245 ? btb_bank0_rd_data_way0_out_43 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4969 = _T_4968 | _T_4714; // @[Mux.scala 27:72]
|
|
wire _T_4247 = btb_rd_addr_p1_f == 8'h2c; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4715 = _T_4247 ? btb_bank0_rd_data_way0_out_44 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4970 = _T_4969 | _T_4715; // @[Mux.scala 27:72]
|
|
wire _T_4249 = btb_rd_addr_p1_f == 8'h2d; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4716 = _T_4249 ? btb_bank0_rd_data_way0_out_45 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4971 = _T_4970 | _T_4716; // @[Mux.scala 27:72]
|
|
wire _T_4251 = btb_rd_addr_p1_f == 8'h2e; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4717 = _T_4251 ? btb_bank0_rd_data_way0_out_46 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4972 = _T_4971 | _T_4717; // @[Mux.scala 27:72]
|
|
wire _T_4253 = btb_rd_addr_p1_f == 8'h2f; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4718 = _T_4253 ? btb_bank0_rd_data_way0_out_47 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4973 = _T_4972 | _T_4718; // @[Mux.scala 27:72]
|
|
wire _T_4255 = btb_rd_addr_p1_f == 8'h30; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4719 = _T_4255 ? btb_bank0_rd_data_way0_out_48 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4974 = _T_4973 | _T_4719; // @[Mux.scala 27:72]
|
|
wire _T_4257 = btb_rd_addr_p1_f == 8'h31; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4720 = _T_4257 ? btb_bank0_rd_data_way0_out_49 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4975 = _T_4974 | _T_4720; // @[Mux.scala 27:72]
|
|
wire _T_4259 = btb_rd_addr_p1_f == 8'h32; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4721 = _T_4259 ? btb_bank0_rd_data_way0_out_50 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4976 = _T_4975 | _T_4721; // @[Mux.scala 27:72]
|
|
wire _T_4261 = btb_rd_addr_p1_f == 8'h33; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4722 = _T_4261 ? btb_bank0_rd_data_way0_out_51 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4977 = _T_4976 | _T_4722; // @[Mux.scala 27:72]
|
|
wire _T_4263 = btb_rd_addr_p1_f == 8'h34; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4723 = _T_4263 ? btb_bank0_rd_data_way0_out_52 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4978 = _T_4977 | _T_4723; // @[Mux.scala 27:72]
|
|
wire _T_4265 = btb_rd_addr_p1_f == 8'h35; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4724 = _T_4265 ? btb_bank0_rd_data_way0_out_53 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4979 = _T_4978 | _T_4724; // @[Mux.scala 27:72]
|
|
wire _T_4267 = btb_rd_addr_p1_f == 8'h36; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4725 = _T_4267 ? btb_bank0_rd_data_way0_out_54 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4980 = _T_4979 | _T_4725; // @[Mux.scala 27:72]
|
|
wire _T_4269 = btb_rd_addr_p1_f == 8'h37; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4726 = _T_4269 ? btb_bank0_rd_data_way0_out_55 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4981 = _T_4980 | _T_4726; // @[Mux.scala 27:72]
|
|
wire _T_4271 = btb_rd_addr_p1_f == 8'h38; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4727 = _T_4271 ? btb_bank0_rd_data_way0_out_56 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4982 = _T_4981 | _T_4727; // @[Mux.scala 27:72]
|
|
wire _T_4273 = btb_rd_addr_p1_f == 8'h39; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4728 = _T_4273 ? btb_bank0_rd_data_way0_out_57 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4983 = _T_4982 | _T_4728; // @[Mux.scala 27:72]
|
|
wire _T_4275 = btb_rd_addr_p1_f == 8'h3a; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4729 = _T_4275 ? btb_bank0_rd_data_way0_out_58 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4984 = _T_4983 | _T_4729; // @[Mux.scala 27:72]
|
|
wire _T_4277 = btb_rd_addr_p1_f == 8'h3b; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4730 = _T_4277 ? btb_bank0_rd_data_way0_out_59 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4985 = _T_4984 | _T_4730; // @[Mux.scala 27:72]
|
|
wire _T_4279 = btb_rd_addr_p1_f == 8'h3c; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4731 = _T_4279 ? btb_bank0_rd_data_way0_out_60 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4986 = _T_4985 | _T_4731; // @[Mux.scala 27:72]
|
|
wire _T_4281 = btb_rd_addr_p1_f == 8'h3d; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4732 = _T_4281 ? btb_bank0_rd_data_way0_out_61 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4987 = _T_4986 | _T_4732; // @[Mux.scala 27:72]
|
|
wire _T_4283 = btb_rd_addr_p1_f == 8'h3e; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4733 = _T_4283 ? btb_bank0_rd_data_way0_out_62 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4988 = _T_4987 | _T_4733; // @[Mux.scala 27:72]
|
|
wire _T_4285 = btb_rd_addr_p1_f == 8'h3f; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4734 = _T_4285 ? btb_bank0_rd_data_way0_out_63 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4989 = _T_4988 | _T_4734; // @[Mux.scala 27:72]
|
|
wire _T_4287 = btb_rd_addr_p1_f == 8'h40; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4735 = _T_4287 ? btb_bank0_rd_data_way0_out_64 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4990 = _T_4989 | _T_4735; // @[Mux.scala 27:72]
|
|
wire _T_4289 = btb_rd_addr_p1_f == 8'h41; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4736 = _T_4289 ? btb_bank0_rd_data_way0_out_65 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4991 = _T_4990 | _T_4736; // @[Mux.scala 27:72]
|
|
wire _T_4291 = btb_rd_addr_p1_f == 8'h42; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4737 = _T_4291 ? btb_bank0_rd_data_way0_out_66 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4992 = _T_4991 | _T_4737; // @[Mux.scala 27:72]
|
|
wire _T_4293 = btb_rd_addr_p1_f == 8'h43; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4738 = _T_4293 ? btb_bank0_rd_data_way0_out_67 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4993 = _T_4992 | _T_4738; // @[Mux.scala 27:72]
|
|
wire _T_4295 = btb_rd_addr_p1_f == 8'h44; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4739 = _T_4295 ? btb_bank0_rd_data_way0_out_68 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4994 = _T_4993 | _T_4739; // @[Mux.scala 27:72]
|
|
wire _T_4297 = btb_rd_addr_p1_f == 8'h45; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4740 = _T_4297 ? btb_bank0_rd_data_way0_out_69 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4995 = _T_4994 | _T_4740; // @[Mux.scala 27:72]
|
|
wire _T_4299 = btb_rd_addr_p1_f == 8'h46; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4741 = _T_4299 ? btb_bank0_rd_data_way0_out_70 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4996 = _T_4995 | _T_4741; // @[Mux.scala 27:72]
|
|
wire _T_4301 = btb_rd_addr_p1_f == 8'h47; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4742 = _T_4301 ? btb_bank0_rd_data_way0_out_71 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4997 = _T_4996 | _T_4742; // @[Mux.scala 27:72]
|
|
wire _T_4303 = btb_rd_addr_p1_f == 8'h48; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4743 = _T_4303 ? btb_bank0_rd_data_way0_out_72 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4998 = _T_4997 | _T_4743; // @[Mux.scala 27:72]
|
|
wire _T_4305 = btb_rd_addr_p1_f == 8'h49; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4744 = _T_4305 ? btb_bank0_rd_data_way0_out_73 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4999 = _T_4998 | _T_4744; // @[Mux.scala 27:72]
|
|
wire _T_4307 = btb_rd_addr_p1_f == 8'h4a; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4745 = _T_4307 ? btb_bank0_rd_data_way0_out_74 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5000 = _T_4999 | _T_4745; // @[Mux.scala 27:72]
|
|
wire _T_4309 = btb_rd_addr_p1_f == 8'h4b; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4746 = _T_4309 ? btb_bank0_rd_data_way0_out_75 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5001 = _T_5000 | _T_4746; // @[Mux.scala 27:72]
|
|
wire _T_4311 = btb_rd_addr_p1_f == 8'h4c; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4747 = _T_4311 ? btb_bank0_rd_data_way0_out_76 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5002 = _T_5001 | _T_4747; // @[Mux.scala 27:72]
|
|
wire _T_4313 = btb_rd_addr_p1_f == 8'h4d; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4748 = _T_4313 ? btb_bank0_rd_data_way0_out_77 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5003 = _T_5002 | _T_4748; // @[Mux.scala 27:72]
|
|
wire _T_4315 = btb_rd_addr_p1_f == 8'h4e; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4749 = _T_4315 ? btb_bank0_rd_data_way0_out_78 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5004 = _T_5003 | _T_4749; // @[Mux.scala 27:72]
|
|
wire _T_4317 = btb_rd_addr_p1_f == 8'h4f; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4750 = _T_4317 ? btb_bank0_rd_data_way0_out_79 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5005 = _T_5004 | _T_4750; // @[Mux.scala 27:72]
|
|
wire _T_4319 = btb_rd_addr_p1_f == 8'h50; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4751 = _T_4319 ? btb_bank0_rd_data_way0_out_80 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5006 = _T_5005 | _T_4751; // @[Mux.scala 27:72]
|
|
wire _T_4321 = btb_rd_addr_p1_f == 8'h51; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4752 = _T_4321 ? btb_bank0_rd_data_way0_out_81 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5007 = _T_5006 | _T_4752; // @[Mux.scala 27:72]
|
|
wire _T_4323 = btb_rd_addr_p1_f == 8'h52; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4753 = _T_4323 ? btb_bank0_rd_data_way0_out_82 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5008 = _T_5007 | _T_4753; // @[Mux.scala 27:72]
|
|
wire _T_4325 = btb_rd_addr_p1_f == 8'h53; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4754 = _T_4325 ? btb_bank0_rd_data_way0_out_83 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5009 = _T_5008 | _T_4754; // @[Mux.scala 27:72]
|
|
wire _T_4327 = btb_rd_addr_p1_f == 8'h54; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4755 = _T_4327 ? btb_bank0_rd_data_way0_out_84 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5010 = _T_5009 | _T_4755; // @[Mux.scala 27:72]
|
|
wire _T_4329 = btb_rd_addr_p1_f == 8'h55; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4756 = _T_4329 ? btb_bank0_rd_data_way0_out_85 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5011 = _T_5010 | _T_4756; // @[Mux.scala 27:72]
|
|
wire _T_4331 = btb_rd_addr_p1_f == 8'h56; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4757 = _T_4331 ? btb_bank0_rd_data_way0_out_86 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5012 = _T_5011 | _T_4757; // @[Mux.scala 27:72]
|
|
wire _T_4333 = btb_rd_addr_p1_f == 8'h57; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4758 = _T_4333 ? btb_bank0_rd_data_way0_out_87 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5013 = _T_5012 | _T_4758; // @[Mux.scala 27:72]
|
|
wire _T_4335 = btb_rd_addr_p1_f == 8'h58; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4759 = _T_4335 ? btb_bank0_rd_data_way0_out_88 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5014 = _T_5013 | _T_4759; // @[Mux.scala 27:72]
|
|
wire _T_4337 = btb_rd_addr_p1_f == 8'h59; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4760 = _T_4337 ? btb_bank0_rd_data_way0_out_89 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5015 = _T_5014 | _T_4760; // @[Mux.scala 27:72]
|
|
wire _T_4339 = btb_rd_addr_p1_f == 8'h5a; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4761 = _T_4339 ? btb_bank0_rd_data_way0_out_90 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5016 = _T_5015 | _T_4761; // @[Mux.scala 27:72]
|
|
wire _T_4341 = btb_rd_addr_p1_f == 8'h5b; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4762 = _T_4341 ? btb_bank0_rd_data_way0_out_91 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5017 = _T_5016 | _T_4762; // @[Mux.scala 27:72]
|
|
wire _T_4343 = btb_rd_addr_p1_f == 8'h5c; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4763 = _T_4343 ? btb_bank0_rd_data_way0_out_92 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5018 = _T_5017 | _T_4763; // @[Mux.scala 27:72]
|
|
wire _T_4345 = btb_rd_addr_p1_f == 8'h5d; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4764 = _T_4345 ? btb_bank0_rd_data_way0_out_93 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5019 = _T_5018 | _T_4764; // @[Mux.scala 27:72]
|
|
wire _T_4347 = btb_rd_addr_p1_f == 8'h5e; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4765 = _T_4347 ? btb_bank0_rd_data_way0_out_94 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5020 = _T_5019 | _T_4765; // @[Mux.scala 27:72]
|
|
wire _T_4349 = btb_rd_addr_p1_f == 8'h5f; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4766 = _T_4349 ? btb_bank0_rd_data_way0_out_95 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5021 = _T_5020 | _T_4766; // @[Mux.scala 27:72]
|
|
wire _T_4351 = btb_rd_addr_p1_f == 8'h60; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4767 = _T_4351 ? btb_bank0_rd_data_way0_out_96 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5022 = _T_5021 | _T_4767; // @[Mux.scala 27:72]
|
|
wire _T_4353 = btb_rd_addr_p1_f == 8'h61; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4768 = _T_4353 ? btb_bank0_rd_data_way0_out_97 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5023 = _T_5022 | _T_4768; // @[Mux.scala 27:72]
|
|
wire _T_4355 = btb_rd_addr_p1_f == 8'h62; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4769 = _T_4355 ? btb_bank0_rd_data_way0_out_98 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5024 = _T_5023 | _T_4769; // @[Mux.scala 27:72]
|
|
wire _T_4357 = btb_rd_addr_p1_f == 8'h63; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4770 = _T_4357 ? btb_bank0_rd_data_way0_out_99 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5025 = _T_5024 | _T_4770; // @[Mux.scala 27:72]
|
|
wire _T_4359 = btb_rd_addr_p1_f == 8'h64; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4771 = _T_4359 ? btb_bank0_rd_data_way0_out_100 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5026 = _T_5025 | _T_4771; // @[Mux.scala 27:72]
|
|
wire _T_4361 = btb_rd_addr_p1_f == 8'h65; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4772 = _T_4361 ? btb_bank0_rd_data_way0_out_101 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5027 = _T_5026 | _T_4772; // @[Mux.scala 27:72]
|
|
wire _T_4363 = btb_rd_addr_p1_f == 8'h66; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4773 = _T_4363 ? btb_bank0_rd_data_way0_out_102 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5028 = _T_5027 | _T_4773; // @[Mux.scala 27:72]
|
|
wire _T_4365 = btb_rd_addr_p1_f == 8'h67; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4774 = _T_4365 ? btb_bank0_rd_data_way0_out_103 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5029 = _T_5028 | _T_4774; // @[Mux.scala 27:72]
|
|
wire _T_4367 = btb_rd_addr_p1_f == 8'h68; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4775 = _T_4367 ? btb_bank0_rd_data_way0_out_104 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5030 = _T_5029 | _T_4775; // @[Mux.scala 27:72]
|
|
wire _T_4369 = btb_rd_addr_p1_f == 8'h69; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4776 = _T_4369 ? btb_bank0_rd_data_way0_out_105 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5031 = _T_5030 | _T_4776; // @[Mux.scala 27:72]
|
|
wire _T_4371 = btb_rd_addr_p1_f == 8'h6a; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4777 = _T_4371 ? btb_bank0_rd_data_way0_out_106 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5032 = _T_5031 | _T_4777; // @[Mux.scala 27:72]
|
|
wire _T_4373 = btb_rd_addr_p1_f == 8'h6b; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4778 = _T_4373 ? btb_bank0_rd_data_way0_out_107 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5033 = _T_5032 | _T_4778; // @[Mux.scala 27:72]
|
|
wire _T_4375 = btb_rd_addr_p1_f == 8'h6c; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4779 = _T_4375 ? btb_bank0_rd_data_way0_out_108 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5034 = _T_5033 | _T_4779; // @[Mux.scala 27:72]
|
|
wire _T_4377 = btb_rd_addr_p1_f == 8'h6d; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4780 = _T_4377 ? btb_bank0_rd_data_way0_out_109 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5035 = _T_5034 | _T_4780; // @[Mux.scala 27:72]
|
|
wire _T_4379 = btb_rd_addr_p1_f == 8'h6e; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4781 = _T_4379 ? btb_bank0_rd_data_way0_out_110 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5036 = _T_5035 | _T_4781; // @[Mux.scala 27:72]
|
|
wire _T_4381 = btb_rd_addr_p1_f == 8'h6f; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4782 = _T_4381 ? btb_bank0_rd_data_way0_out_111 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5037 = _T_5036 | _T_4782; // @[Mux.scala 27:72]
|
|
wire _T_4383 = btb_rd_addr_p1_f == 8'h70; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4783 = _T_4383 ? btb_bank0_rd_data_way0_out_112 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5038 = _T_5037 | _T_4783; // @[Mux.scala 27:72]
|
|
wire _T_4385 = btb_rd_addr_p1_f == 8'h71; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4784 = _T_4385 ? btb_bank0_rd_data_way0_out_113 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5039 = _T_5038 | _T_4784; // @[Mux.scala 27:72]
|
|
wire _T_4387 = btb_rd_addr_p1_f == 8'h72; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4785 = _T_4387 ? btb_bank0_rd_data_way0_out_114 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5040 = _T_5039 | _T_4785; // @[Mux.scala 27:72]
|
|
wire _T_4389 = btb_rd_addr_p1_f == 8'h73; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4786 = _T_4389 ? btb_bank0_rd_data_way0_out_115 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5041 = _T_5040 | _T_4786; // @[Mux.scala 27:72]
|
|
wire _T_4391 = btb_rd_addr_p1_f == 8'h74; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4787 = _T_4391 ? btb_bank0_rd_data_way0_out_116 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5042 = _T_5041 | _T_4787; // @[Mux.scala 27:72]
|
|
wire _T_4393 = btb_rd_addr_p1_f == 8'h75; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4788 = _T_4393 ? btb_bank0_rd_data_way0_out_117 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5043 = _T_5042 | _T_4788; // @[Mux.scala 27:72]
|
|
wire _T_4395 = btb_rd_addr_p1_f == 8'h76; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4789 = _T_4395 ? btb_bank0_rd_data_way0_out_118 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5044 = _T_5043 | _T_4789; // @[Mux.scala 27:72]
|
|
wire _T_4397 = btb_rd_addr_p1_f == 8'h77; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4790 = _T_4397 ? btb_bank0_rd_data_way0_out_119 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5045 = _T_5044 | _T_4790; // @[Mux.scala 27:72]
|
|
wire _T_4399 = btb_rd_addr_p1_f == 8'h78; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4791 = _T_4399 ? btb_bank0_rd_data_way0_out_120 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5046 = _T_5045 | _T_4791; // @[Mux.scala 27:72]
|
|
wire _T_4401 = btb_rd_addr_p1_f == 8'h79; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4792 = _T_4401 ? btb_bank0_rd_data_way0_out_121 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5047 = _T_5046 | _T_4792; // @[Mux.scala 27:72]
|
|
wire _T_4403 = btb_rd_addr_p1_f == 8'h7a; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4793 = _T_4403 ? btb_bank0_rd_data_way0_out_122 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5048 = _T_5047 | _T_4793; // @[Mux.scala 27:72]
|
|
wire _T_4405 = btb_rd_addr_p1_f == 8'h7b; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4794 = _T_4405 ? btb_bank0_rd_data_way0_out_123 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5049 = _T_5048 | _T_4794; // @[Mux.scala 27:72]
|
|
wire _T_4407 = btb_rd_addr_p1_f == 8'h7c; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4795 = _T_4407 ? btb_bank0_rd_data_way0_out_124 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5050 = _T_5049 | _T_4795; // @[Mux.scala 27:72]
|
|
wire _T_4409 = btb_rd_addr_p1_f == 8'h7d; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4796 = _T_4409 ? btb_bank0_rd_data_way0_out_125 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5051 = _T_5050 | _T_4796; // @[Mux.scala 27:72]
|
|
wire _T_4411 = btb_rd_addr_p1_f == 8'h7e; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4797 = _T_4411 ? btb_bank0_rd_data_way0_out_126 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5052 = _T_5051 | _T_4797; // @[Mux.scala 27:72]
|
|
wire _T_4413 = btb_rd_addr_p1_f == 8'h7f; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4798 = _T_4413 ? btb_bank0_rd_data_way0_out_127 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5053 = _T_5052 | _T_4798; // @[Mux.scala 27:72]
|
|
wire _T_4415 = btb_rd_addr_p1_f == 8'h80; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4799 = _T_4415 ? btb_bank0_rd_data_way0_out_128 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5054 = _T_5053 | _T_4799; // @[Mux.scala 27:72]
|
|
wire _T_4417 = btb_rd_addr_p1_f == 8'h81; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4800 = _T_4417 ? btb_bank0_rd_data_way0_out_129 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5055 = _T_5054 | _T_4800; // @[Mux.scala 27:72]
|
|
wire _T_4419 = btb_rd_addr_p1_f == 8'h82; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4801 = _T_4419 ? btb_bank0_rd_data_way0_out_130 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5056 = _T_5055 | _T_4801; // @[Mux.scala 27:72]
|
|
wire _T_4421 = btb_rd_addr_p1_f == 8'h83; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4802 = _T_4421 ? btb_bank0_rd_data_way0_out_131 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5057 = _T_5056 | _T_4802; // @[Mux.scala 27:72]
|
|
wire _T_4423 = btb_rd_addr_p1_f == 8'h84; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4803 = _T_4423 ? btb_bank0_rd_data_way0_out_132 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5058 = _T_5057 | _T_4803; // @[Mux.scala 27:72]
|
|
wire _T_4425 = btb_rd_addr_p1_f == 8'h85; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4804 = _T_4425 ? btb_bank0_rd_data_way0_out_133 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5059 = _T_5058 | _T_4804; // @[Mux.scala 27:72]
|
|
wire _T_4427 = btb_rd_addr_p1_f == 8'h86; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4805 = _T_4427 ? btb_bank0_rd_data_way0_out_134 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5060 = _T_5059 | _T_4805; // @[Mux.scala 27:72]
|
|
wire _T_4429 = btb_rd_addr_p1_f == 8'h87; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4806 = _T_4429 ? btb_bank0_rd_data_way0_out_135 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5061 = _T_5060 | _T_4806; // @[Mux.scala 27:72]
|
|
wire _T_4431 = btb_rd_addr_p1_f == 8'h88; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4807 = _T_4431 ? btb_bank0_rd_data_way0_out_136 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5062 = _T_5061 | _T_4807; // @[Mux.scala 27:72]
|
|
wire _T_4433 = btb_rd_addr_p1_f == 8'h89; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4808 = _T_4433 ? btb_bank0_rd_data_way0_out_137 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5063 = _T_5062 | _T_4808; // @[Mux.scala 27:72]
|
|
wire _T_4435 = btb_rd_addr_p1_f == 8'h8a; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4809 = _T_4435 ? btb_bank0_rd_data_way0_out_138 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5064 = _T_5063 | _T_4809; // @[Mux.scala 27:72]
|
|
wire _T_4437 = btb_rd_addr_p1_f == 8'h8b; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4810 = _T_4437 ? btb_bank0_rd_data_way0_out_139 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5065 = _T_5064 | _T_4810; // @[Mux.scala 27:72]
|
|
wire _T_4439 = btb_rd_addr_p1_f == 8'h8c; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4811 = _T_4439 ? btb_bank0_rd_data_way0_out_140 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5066 = _T_5065 | _T_4811; // @[Mux.scala 27:72]
|
|
wire _T_4441 = btb_rd_addr_p1_f == 8'h8d; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4812 = _T_4441 ? btb_bank0_rd_data_way0_out_141 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5067 = _T_5066 | _T_4812; // @[Mux.scala 27:72]
|
|
wire _T_4443 = btb_rd_addr_p1_f == 8'h8e; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4813 = _T_4443 ? btb_bank0_rd_data_way0_out_142 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5068 = _T_5067 | _T_4813; // @[Mux.scala 27:72]
|
|
wire _T_4445 = btb_rd_addr_p1_f == 8'h8f; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4814 = _T_4445 ? btb_bank0_rd_data_way0_out_143 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5069 = _T_5068 | _T_4814; // @[Mux.scala 27:72]
|
|
wire _T_4447 = btb_rd_addr_p1_f == 8'h90; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4815 = _T_4447 ? btb_bank0_rd_data_way0_out_144 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5070 = _T_5069 | _T_4815; // @[Mux.scala 27:72]
|
|
wire _T_4449 = btb_rd_addr_p1_f == 8'h91; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4816 = _T_4449 ? btb_bank0_rd_data_way0_out_145 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5071 = _T_5070 | _T_4816; // @[Mux.scala 27:72]
|
|
wire _T_4451 = btb_rd_addr_p1_f == 8'h92; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4817 = _T_4451 ? btb_bank0_rd_data_way0_out_146 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5072 = _T_5071 | _T_4817; // @[Mux.scala 27:72]
|
|
wire _T_4453 = btb_rd_addr_p1_f == 8'h93; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4818 = _T_4453 ? btb_bank0_rd_data_way0_out_147 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5073 = _T_5072 | _T_4818; // @[Mux.scala 27:72]
|
|
wire _T_4455 = btb_rd_addr_p1_f == 8'h94; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4819 = _T_4455 ? btb_bank0_rd_data_way0_out_148 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5074 = _T_5073 | _T_4819; // @[Mux.scala 27:72]
|
|
wire _T_4457 = btb_rd_addr_p1_f == 8'h95; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4820 = _T_4457 ? btb_bank0_rd_data_way0_out_149 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5075 = _T_5074 | _T_4820; // @[Mux.scala 27:72]
|
|
wire _T_4459 = btb_rd_addr_p1_f == 8'h96; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4821 = _T_4459 ? btb_bank0_rd_data_way0_out_150 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5076 = _T_5075 | _T_4821; // @[Mux.scala 27:72]
|
|
wire _T_4461 = btb_rd_addr_p1_f == 8'h97; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4822 = _T_4461 ? btb_bank0_rd_data_way0_out_151 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5077 = _T_5076 | _T_4822; // @[Mux.scala 27:72]
|
|
wire _T_4463 = btb_rd_addr_p1_f == 8'h98; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4823 = _T_4463 ? btb_bank0_rd_data_way0_out_152 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5078 = _T_5077 | _T_4823; // @[Mux.scala 27:72]
|
|
wire _T_4465 = btb_rd_addr_p1_f == 8'h99; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4824 = _T_4465 ? btb_bank0_rd_data_way0_out_153 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5079 = _T_5078 | _T_4824; // @[Mux.scala 27:72]
|
|
wire _T_4467 = btb_rd_addr_p1_f == 8'h9a; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4825 = _T_4467 ? btb_bank0_rd_data_way0_out_154 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5080 = _T_5079 | _T_4825; // @[Mux.scala 27:72]
|
|
wire _T_4469 = btb_rd_addr_p1_f == 8'h9b; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4826 = _T_4469 ? btb_bank0_rd_data_way0_out_155 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5081 = _T_5080 | _T_4826; // @[Mux.scala 27:72]
|
|
wire _T_4471 = btb_rd_addr_p1_f == 8'h9c; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4827 = _T_4471 ? btb_bank0_rd_data_way0_out_156 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5082 = _T_5081 | _T_4827; // @[Mux.scala 27:72]
|
|
wire _T_4473 = btb_rd_addr_p1_f == 8'h9d; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4828 = _T_4473 ? btb_bank0_rd_data_way0_out_157 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5083 = _T_5082 | _T_4828; // @[Mux.scala 27:72]
|
|
wire _T_4475 = btb_rd_addr_p1_f == 8'h9e; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4829 = _T_4475 ? btb_bank0_rd_data_way0_out_158 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5084 = _T_5083 | _T_4829; // @[Mux.scala 27:72]
|
|
wire _T_4477 = btb_rd_addr_p1_f == 8'h9f; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4830 = _T_4477 ? btb_bank0_rd_data_way0_out_159 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5085 = _T_5084 | _T_4830; // @[Mux.scala 27:72]
|
|
wire _T_4479 = btb_rd_addr_p1_f == 8'ha0; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4831 = _T_4479 ? btb_bank0_rd_data_way0_out_160 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5086 = _T_5085 | _T_4831; // @[Mux.scala 27:72]
|
|
wire _T_4481 = btb_rd_addr_p1_f == 8'ha1; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4832 = _T_4481 ? btb_bank0_rd_data_way0_out_161 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5087 = _T_5086 | _T_4832; // @[Mux.scala 27:72]
|
|
wire _T_4483 = btb_rd_addr_p1_f == 8'ha2; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4833 = _T_4483 ? btb_bank0_rd_data_way0_out_162 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5088 = _T_5087 | _T_4833; // @[Mux.scala 27:72]
|
|
wire _T_4485 = btb_rd_addr_p1_f == 8'ha3; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4834 = _T_4485 ? btb_bank0_rd_data_way0_out_163 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5089 = _T_5088 | _T_4834; // @[Mux.scala 27:72]
|
|
wire _T_4487 = btb_rd_addr_p1_f == 8'ha4; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4835 = _T_4487 ? btb_bank0_rd_data_way0_out_164 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5090 = _T_5089 | _T_4835; // @[Mux.scala 27:72]
|
|
wire _T_4489 = btb_rd_addr_p1_f == 8'ha5; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4836 = _T_4489 ? btb_bank0_rd_data_way0_out_165 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5091 = _T_5090 | _T_4836; // @[Mux.scala 27:72]
|
|
wire _T_4491 = btb_rd_addr_p1_f == 8'ha6; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4837 = _T_4491 ? btb_bank0_rd_data_way0_out_166 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5092 = _T_5091 | _T_4837; // @[Mux.scala 27:72]
|
|
wire _T_4493 = btb_rd_addr_p1_f == 8'ha7; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4838 = _T_4493 ? btb_bank0_rd_data_way0_out_167 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5093 = _T_5092 | _T_4838; // @[Mux.scala 27:72]
|
|
wire _T_4495 = btb_rd_addr_p1_f == 8'ha8; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4839 = _T_4495 ? btb_bank0_rd_data_way0_out_168 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5094 = _T_5093 | _T_4839; // @[Mux.scala 27:72]
|
|
wire _T_4497 = btb_rd_addr_p1_f == 8'ha9; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4840 = _T_4497 ? btb_bank0_rd_data_way0_out_169 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5095 = _T_5094 | _T_4840; // @[Mux.scala 27:72]
|
|
wire _T_4499 = btb_rd_addr_p1_f == 8'haa; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4841 = _T_4499 ? btb_bank0_rd_data_way0_out_170 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5096 = _T_5095 | _T_4841; // @[Mux.scala 27:72]
|
|
wire _T_4501 = btb_rd_addr_p1_f == 8'hab; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4842 = _T_4501 ? btb_bank0_rd_data_way0_out_171 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5097 = _T_5096 | _T_4842; // @[Mux.scala 27:72]
|
|
wire _T_4503 = btb_rd_addr_p1_f == 8'hac; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4843 = _T_4503 ? btb_bank0_rd_data_way0_out_172 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5098 = _T_5097 | _T_4843; // @[Mux.scala 27:72]
|
|
wire _T_4505 = btb_rd_addr_p1_f == 8'had; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4844 = _T_4505 ? btb_bank0_rd_data_way0_out_173 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5099 = _T_5098 | _T_4844; // @[Mux.scala 27:72]
|
|
wire _T_4507 = btb_rd_addr_p1_f == 8'hae; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4845 = _T_4507 ? btb_bank0_rd_data_way0_out_174 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5100 = _T_5099 | _T_4845; // @[Mux.scala 27:72]
|
|
wire _T_4509 = btb_rd_addr_p1_f == 8'haf; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4846 = _T_4509 ? btb_bank0_rd_data_way0_out_175 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5101 = _T_5100 | _T_4846; // @[Mux.scala 27:72]
|
|
wire _T_4511 = btb_rd_addr_p1_f == 8'hb0; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4847 = _T_4511 ? btb_bank0_rd_data_way0_out_176 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5102 = _T_5101 | _T_4847; // @[Mux.scala 27:72]
|
|
wire _T_4513 = btb_rd_addr_p1_f == 8'hb1; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4848 = _T_4513 ? btb_bank0_rd_data_way0_out_177 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5103 = _T_5102 | _T_4848; // @[Mux.scala 27:72]
|
|
wire _T_4515 = btb_rd_addr_p1_f == 8'hb2; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4849 = _T_4515 ? btb_bank0_rd_data_way0_out_178 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5104 = _T_5103 | _T_4849; // @[Mux.scala 27:72]
|
|
wire _T_4517 = btb_rd_addr_p1_f == 8'hb3; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4850 = _T_4517 ? btb_bank0_rd_data_way0_out_179 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5105 = _T_5104 | _T_4850; // @[Mux.scala 27:72]
|
|
wire _T_4519 = btb_rd_addr_p1_f == 8'hb4; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4851 = _T_4519 ? btb_bank0_rd_data_way0_out_180 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5106 = _T_5105 | _T_4851; // @[Mux.scala 27:72]
|
|
wire _T_4521 = btb_rd_addr_p1_f == 8'hb5; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4852 = _T_4521 ? btb_bank0_rd_data_way0_out_181 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5107 = _T_5106 | _T_4852; // @[Mux.scala 27:72]
|
|
wire _T_4523 = btb_rd_addr_p1_f == 8'hb6; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4853 = _T_4523 ? btb_bank0_rd_data_way0_out_182 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5108 = _T_5107 | _T_4853; // @[Mux.scala 27:72]
|
|
wire _T_4525 = btb_rd_addr_p1_f == 8'hb7; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4854 = _T_4525 ? btb_bank0_rd_data_way0_out_183 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5109 = _T_5108 | _T_4854; // @[Mux.scala 27:72]
|
|
wire _T_4527 = btb_rd_addr_p1_f == 8'hb8; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4855 = _T_4527 ? btb_bank0_rd_data_way0_out_184 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5110 = _T_5109 | _T_4855; // @[Mux.scala 27:72]
|
|
wire _T_4529 = btb_rd_addr_p1_f == 8'hb9; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4856 = _T_4529 ? btb_bank0_rd_data_way0_out_185 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5111 = _T_5110 | _T_4856; // @[Mux.scala 27:72]
|
|
wire _T_4531 = btb_rd_addr_p1_f == 8'hba; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4857 = _T_4531 ? btb_bank0_rd_data_way0_out_186 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5112 = _T_5111 | _T_4857; // @[Mux.scala 27:72]
|
|
wire _T_4533 = btb_rd_addr_p1_f == 8'hbb; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4858 = _T_4533 ? btb_bank0_rd_data_way0_out_187 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5113 = _T_5112 | _T_4858; // @[Mux.scala 27:72]
|
|
wire _T_4535 = btb_rd_addr_p1_f == 8'hbc; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4859 = _T_4535 ? btb_bank0_rd_data_way0_out_188 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5114 = _T_5113 | _T_4859; // @[Mux.scala 27:72]
|
|
wire _T_4537 = btb_rd_addr_p1_f == 8'hbd; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4860 = _T_4537 ? btb_bank0_rd_data_way0_out_189 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5115 = _T_5114 | _T_4860; // @[Mux.scala 27:72]
|
|
wire _T_4539 = btb_rd_addr_p1_f == 8'hbe; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4861 = _T_4539 ? btb_bank0_rd_data_way0_out_190 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5116 = _T_5115 | _T_4861; // @[Mux.scala 27:72]
|
|
wire _T_4541 = btb_rd_addr_p1_f == 8'hbf; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4862 = _T_4541 ? btb_bank0_rd_data_way0_out_191 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5117 = _T_5116 | _T_4862; // @[Mux.scala 27:72]
|
|
wire _T_4543 = btb_rd_addr_p1_f == 8'hc0; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4863 = _T_4543 ? btb_bank0_rd_data_way0_out_192 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5118 = _T_5117 | _T_4863; // @[Mux.scala 27:72]
|
|
wire _T_4545 = btb_rd_addr_p1_f == 8'hc1; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4864 = _T_4545 ? btb_bank0_rd_data_way0_out_193 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5119 = _T_5118 | _T_4864; // @[Mux.scala 27:72]
|
|
wire _T_4547 = btb_rd_addr_p1_f == 8'hc2; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4865 = _T_4547 ? btb_bank0_rd_data_way0_out_194 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5120 = _T_5119 | _T_4865; // @[Mux.scala 27:72]
|
|
wire _T_4549 = btb_rd_addr_p1_f == 8'hc3; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4866 = _T_4549 ? btb_bank0_rd_data_way0_out_195 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5121 = _T_5120 | _T_4866; // @[Mux.scala 27:72]
|
|
wire _T_4551 = btb_rd_addr_p1_f == 8'hc4; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4867 = _T_4551 ? btb_bank0_rd_data_way0_out_196 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5122 = _T_5121 | _T_4867; // @[Mux.scala 27:72]
|
|
wire _T_4553 = btb_rd_addr_p1_f == 8'hc5; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4868 = _T_4553 ? btb_bank0_rd_data_way0_out_197 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5123 = _T_5122 | _T_4868; // @[Mux.scala 27:72]
|
|
wire _T_4555 = btb_rd_addr_p1_f == 8'hc6; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4869 = _T_4555 ? btb_bank0_rd_data_way0_out_198 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5124 = _T_5123 | _T_4869; // @[Mux.scala 27:72]
|
|
wire _T_4557 = btb_rd_addr_p1_f == 8'hc7; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4870 = _T_4557 ? btb_bank0_rd_data_way0_out_199 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5125 = _T_5124 | _T_4870; // @[Mux.scala 27:72]
|
|
wire _T_4559 = btb_rd_addr_p1_f == 8'hc8; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4871 = _T_4559 ? btb_bank0_rd_data_way0_out_200 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5126 = _T_5125 | _T_4871; // @[Mux.scala 27:72]
|
|
wire _T_4561 = btb_rd_addr_p1_f == 8'hc9; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4872 = _T_4561 ? btb_bank0_rd_data_way0_out_201 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5127 = _T_5126 | _T_4872; // @[Mux.scala 27:72]
|
|
wire _T_4563 = btb_rd_addr_p1_f == 8'hca; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4873 = _T_4563 ? btb_bank0_rd_data_way0_out_202 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5128 = _T_5127 | _T_4873; // @[Mux.scala 27:72]
|
|
wire _T_4565 = btb_rd_addr_p1_f == 8'hcb; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4874 = _T_4565 ? btb_bank0_rd_data_way0_out_203 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5129 = _T_5128 | _T_4874; // @[Mux.scala 27:72]
|
|
wire _T_4567 = btb_rd_addr_p1_f == 8'hcc; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4875 = _T_4567 ? btb_bank0_rd_data_way0_out_204 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5130 = _T_5129 | _T_4875; // @[Mux.scala 27:72]
|
|
wire _T_4569 = btb_rd_addr_p1_f == 8'hcd; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4876 = _T_4569 ? btb_bank0_rd_data_way0_out_205 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5131 = _T_5130 | _T_4876; // @[Mux.scala 27:72]
|
|
wire _T_4571 = btb_rd_addr_p1_f == 8'hce; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4877 = _T_4571 ? btb_bank0_rd_data_way0_out_206 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5132 = _T_5131 | _T_4877; // @[Mux.scala 27:72]
|
|
wire _T_4573 = btb_rd_addr_p1_f == 8'hcf; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4878 = _T_4573 ? btb_bank0_rd_data_way0_out_207 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5133 = _T_5132 | _T_4878; // @[Mux.scala 27:72]
|
|
wire _T_4575 = btb_rd_addr_p1_f == 8'hd0; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4879 = _T_4575 ? btb_bank0_rd_data_way0_out_208 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5134 = _T_5133 | _T_4879; // @[Mux.scala 27:72]
|
|
wire _T_4577 = btb_rd_addr_p1_f == 8'hd1; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4880 = _T_4577 ? btb_bank0_rd_data_way0_out_209 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5135 = _T_5134 | _T_4880; // @[Mux.scala 27:72]
|
|
wire _T_4579 = btb_rd_addr_p1_f == 8'hd2; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4881 = _T_4579 ? btb_bank0_rd_data_way0_out_210 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5136 = _T_5135 | _T_4881; // @[Mux.scala 27:72]
|
|
wire _T_4581 = btb_rd_addr_p1_f == 8'hd3; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4882 = _T_4581 ? btb_bank0_rd_data_way0_out_211 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5137 = _T_5136 | _T_4882; // @[Mux.scala 27:72]
|
|
wire _T_4583 = btb_rd_addr_p1_f == 8'hd4; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4883 = _T_4583 ? btb_bank0_rd_data_way0_out_212 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5138 = _T_5137 | _T_4883; // @[Mux.scala 27:72]
|
|
wire _T_4585 = btb_rd_addr_p1_f == 8'hd5; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4884 = _T_4585 ? btb_bank0_rd_data_way0_out_213 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5139 = _T_5138 | _T_4884; // @[Mux.scala 27:72]
|
|
wire _T_4587 = btb_rd_addr_p1_f == 8'hd6; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4885 = _T_4587 ? btb_bank0_rd_data_way0_out_214 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5140 = _T_5139 | _T_4885; // @[Mux.scala 27:72]
|
|
wire _T_4589 = btb_rd_addr_p1_f == 8'hd7; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4886 = _T_4589 ? btb_bank0_rd_data_way0_out_215 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5141 = _T_5140 | _T_4886; // @[Mux.scala 27:72]
|
|
wire _T_4591 = btb_rd_addr_p1_f == 8'hd8; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4887 = _T_4591 ? btb_bank0_rd_data_way0_out_216 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5142 = _T_5141 | _T_4887; // @[Mux.scala 27:72]
|
|
wire _T_4593 = btb_rd_addr_p1_f == 8'hd9; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4888 = _T_4593 ? btb_bank0_rd_data_way0_out_217 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5143 = _T_5142 | _T_4888; // @[Mux.scala 27:72]
|
|
wire _T_4595 = btb_rd_addr_p1_f == 8'hda; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4889 = _T_4595 ? btb_bank0_rd_data_way0_out_218 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5144 = _T_5143 | _T_4889; // @[Mux.scala 27:72]
|
|
wire _T_4597 = btb_rd_addr_p1_f == 8'hdb; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4890 = _T_4597 ? btb_bank0_rd_data_way0_out_219 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5145 = _T_5144 | _T_4890; // @[Mux.scala 27:72]
|
|
wire _T_4599 = btb_rd_addr_p1_f == 8'hdc; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4891 = _T_4599 ? btb_bank0_rd_data_way0_out_220 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5146 = _T_5145 | _T_4891; // @[Mux.scala 27:72]
|
|
wire _T_4601 = btb_rd_addr_p1_f == 8'hdd; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4892 = _T_4601 ? btb_bank0_rd_data_way0_out_221 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5147 = _T_5146 | _T_4892; // @[Mux.scala 27:72]
|
|
wire _T_4603 = btb_rd_addr_p1_f == 8'hde; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4893 = _T_4603 ? btb_bank0_rd_data_way0_out_222 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5148 = _T_5147 | _T_4893; // @[Mux.scala 27:72]
|
|
wire _T_4605 = btb_rd_addr_p1_f == 8'hdf; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4894 = _T_4605 ? btb_bank0_rd_data_way0_out_223 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5149 = _T_5148 | _T_4894; // @[Mux.scala 27:72]
|
|
wire _T_4607 = btb_rd_addr_p1_f == 8'he0; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4895 = _T_4607 ? btb_bank0_rd_data_way0_out_224 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5150 = _T_5149 | _T_4895; // @[Mux.scala 27:72]
|
|
wire _T_4609 = btb_rd_addr_p1_f == 8'he1; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4896 = _T_4609 ? btb_bank0_rd_data_way0_out_225 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5151 = _T_5150 | _T_4896; // @[Mux.scala 27:72]
|
|
wire _T_4611 = btb_rd_addr_p1_f == 8'he2; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4897 = _T_4611 ? btb_bank0_rd_data_way0_out_226 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5152 = _T_5151 | _T_4897; // @[Mux.scala 27:72]
|
|
wire _T_4613 = btb_rd_addr_p1_f == 8'he3; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4898 = _T_4613 ? btb_bank0_rd_data_way0_out_227 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5153 = _T_5152 | _T_4898; // @[Mux.scala 27:72]
|
|
wire _T_4615 = btb_rd_addr_p1_f == 8'he4; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4899 = _T_4615 ? btb_bank0_rd_data_way0_out_228 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5154 = _T_5153 | _T_4899; // @[Mux.scala 27:72]
|
|
wire _T_4617 = btb_rd_addr_p1_f == 8'he5; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4900 = _T_4617 ? btb_bank0_rd_data_way0_out_229 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5155 = _T_5154 | _T_4900; // @[Mux.scala 27:72]
|
|
wire _T_4619 = btb_rd_addr_p1_f == 8'he6; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4901 = _T_4619 ? btb_bank0_rd_data_way0_out_230 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5156 = _T_5155 | _T_4901; // @[Mux.scala 27:72]
|
|
wire _T_4621 = btb_rd_addr_p1_f == 8'he7; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4902 = _T_4621 ? btb_bank0_rd_data_way0_out_231 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5157 = _T_5156 | _T_4902; // @[Mux.scala 27:72]
|
|
wire _T_4623 = btb_rd_addr_p1_f == 8'he8; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4903 = _T_4623 ? btb_bank0_rd_data_way0_out_232 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5158 = _T_5157 | _T_4903; // @[Mux.scala 27:72]
|
|
wire _T_4625 = btb_rd_addr_p1_f == 8'he9; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4904 = _T_4625 ? btb_bank0_rd_data_way0_out_233 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5159 = _T_5158 | _T_4904; // @[Mux.scala 27:72]
|
|
wire _T_4627 = btb_rd_addr_p1_f == 8'hea; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4905 = _T_4627 ? btb_bank0_rd_data_way0_out_234 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5160 = _T_5159 | _T_4905; // @[Mux.scala 27:72]
|
|
wire _T_4629 = btb_rd_addr_p1_f == 8'heb; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4906 = _T_4629 ? btb_bank0_rd_data_way0_out_235 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5161 = _T_5160 | _T_4906; // @[Mux.scala 27:72]
|
|
wire _T_4631 = btb_rd_addr_p1_f == 8'hec; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4907 = _T_4631 ? btb_bank0_rd_data_way0_out_236 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5162 = _T_5161 | _T_4907; // @[Mux.scala 27:72]
|
|
wire _T_4633 = btb_rd_addr_p1_f == 8'hed; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4908 = _T_4633 ? btb_bank0_rd_data_way0_out_237 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5163 = _T_5162 | _T_4908; // @[Mux.scala 27:72]
|
|
wire _T_4635 = btb_rd_addr_p1_f == 8'hee; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4909 = _T_4635 ? btb_bank0_rd_data_way0_out_238 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5164 = _T_5163 | _T_4909; // @[Mux.scala 27:72]
|
|
wire _T_4637 = btb_rd_addr_p1_f == 8'hef; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4910 = _T_4637 ? btb_bank0_rd_data_way0_out_239 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5165 = _T_5164 | _T_4910; // @[Mux.scala 27:72]
|
|
wire _T_4639 = btb_rd_addr_p1_f == 8'hf0; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4911 = _T_4639 ? btb_bank0_rd_data_way0_out_240 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5166 = _T_5165 | _T_4911; // @[Mux.scala 27:72]
|
|
wire _T_4641 = btb_rd_addr_p1_f == 8'hf1; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4912 = _T_4641 ? btb_bank0_rd_data_way0_out_241 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5167 = _T_5166 | _T_4912; // @[Mux.scala 27:72]
|
|
wire _T_4643 = btb_rd_addr_p1_f == 8'hf2; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4913 = _T_4643 ? btb_bank0_rd_data_way0_out_242 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5168 = _T_5167 | _T_4913; // @[Mux.scala 27:72]
|
|
wire _T_4645 = btb_rd_addr_p1_f == 8'hf3; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4914 = _T_4645 ? btb_bank0_rd_data_way0_out_243 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5169 = _T_5168 | _T_4914; // @[Mux.scala 27:72]
|
|
wire _T_4647 = btb_rd_addr_p1_f == 8'hf4; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4915 = _T_4647 ? btb_bank0_rd_data_way0_out_244 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5170 = _T_5169 | _T_4915; // @[Mux.scala 27:72]
|
|
wire _T_4649 = btb_rd_addr_p1_f == 8'hf5; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4916 = _T_4649 ? btb_bank0_rd_data_way0_out_245 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5171 = _T_5170 | _T_4916; // @[Mux.scala 27:72]
|
|
wire _T_4651 = btb_rd_addr_p1_f == 8'hf6; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4917 = _T_4651 ? btb_bank0_rd_data_way0_out_246 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5172 = _T_5171 | _T_4917; // @[Mux.scala 27:72]
|
|
wire _T_4653 = btb_rd_addr_p1_f == 8'hf7; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4918 = _T_4653 ? btb_bank0_rd_data_way0_out_247 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5173 = _T_5172 | _T_4918; // @[Mux.scala 27:72]
|
|
wire _T_4655 = btb_rd_addr_p1_f == 8'hf8; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4919 = _T_4655 ? btb_bank0_rd_data_way0_out_248 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5174 = _T_5173 | _T_4919; // @[Mux.scala 27:72]
|
|
wire _T_4657 = btb_rd_addr_p1_f == 8'hf9; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4920 = _T_4657 ? btb_bank0_rd_data_way0_out_249 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5175 = _T_5174 | _T_4920; // @[Mux.scala 27:72]
|
|
wire _T_4659 = btb_rd_addr_p1_f == 8'hfa; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4921 = _T_4659 ? btb_bank0_rd_data_way0_out_250 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5176 = _T_5175 | _T_4921; // @[Mux.scala 27:72]
|
|
wire _T_4661 = btb_rd_addr_p1_f == 8'hfb; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4922 = _T_4661 ? btb_bank0_rd_data_way0_out_251 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5177 = _T_5176 | _T_4922; // @[Mux.scala 27:72]
|
|
wire _T_4663 = btb_rd_addr_p1_f == 8'hfc; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4923 = _T_4663 ? btb_bank0_rd_data_way0_out_252 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5178 = _T_5177 | _T_4923; // @[Mux.scala 27:72]
|
|
wire _T_4665 = btb_rd_addr_p1_f == 8'hfd; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4924 = _T_4665 ? btb_bank0_rd_data_way0_out_253 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5179 = _T_5178 | _T_4924; // @[Mux.scala 27:72]
|
|
wire _T_4667 = btb_rd_addr_p1_f == 8'hfe; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4925 = _T_4667 ? btb_bank0_rd_data_way0_out_254 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5180 = _T_5179 | _T_4925; // @[Mux.scala 27:72]
|
|
wire _T_4669 = btb_rd_addr_p1_f == 8'hff; // @[el2_ifu_bp_ctl.scala 434:83]
|
|
wire [21:0] _T_4926 = _T_4669 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_5180 | _T_4926; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_31 = _T_8[13:9] ^ _T_8[18:14]; // @[el2_lib.scala 182:111]
|
|
wire [4:0] fetch_rd_tag_p1_f = _T_31 ^ _T_8[23:19]; // @[el2_lib.scala 182:111]
|
|
wire _T_63 = btb_bank0_rd_data_way0_p1_f[21:17] == fetch_rd_tag_p1_f; // @[el2_ifu_bp_ctl.scala 147:106]
|
|
wire _T_64 = btb_bank0_rd_data_way0_p1_f[0] & _T_63; // @[el2_ifu_bp_ctl.scala 147:61]
|
|
wire _T_67 = _T_64 & _T_48; // @[el2_ifu_bp_ctl.scala 147:129]
|
|
wire _T_68 = _T_67 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 148:56]
|
|
wire tag_match_way0_p1_f = _T_68 & _T; // @[el2_ifu_bp_ctl.scala 148:77]
|
|
wire _T_99 = btb_bank0_rd_data_way0_p1_f[3] ^ btb_bank0_rd_data_way0_p1_f[4]; // @[el2_ifu_bp_ctl.scala 160:100]
|
|
wire _T_100 = tag_match_way0_p1_f & _T_99; // @[el2_ifu_bp_ctl.scala 160:62]
|
|
wire _T_104 = ~_T_99; // @[el2_ifu_bp_ctl.scala 161:64]
|
|
wire _T_105 = tag_match_way0_p1_f & _T_104; // @[el2_ifu_bp_ctl.scala 161:62]
|
|
wire [1:0] tag_match_way0_expanded_p1_f = {_T_100,_T_105}; // @[Cat.scala 29:58]
|
|
wire [21:0] _T_133 = tag_match_way0_expanded_p1_f[0] ? btb_bank0_rd_data_way0_p1_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5695 = _T_4159 ? btb_bank0_rd_data_way1_out_0 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5696 = _T_4161 ? btb_bank0_rd_data_way1_out_1 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5951 = _T_5695 | _T_5696; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5697 = _T_4163 ? btb_bank0_rd_data_way1_out_2 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5952 = _T_5951 | _T_5697; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5698 = _T_4165 ? btb_bank0_rd_data_way1_out_3 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5953 = _T_5952 | _T_5698; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5699 = _T_4167 ? btb_bank0_rd_data_way1_out_4 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5954 = _T_5953 | _T_5699; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5700 = _T_4169 ? btb_bank0_rd_data_way1_out_5 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5955 = _T_5954 | _T_5700; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5701 = _T_4171 ? btb_bank0_rd_data_way1_out_6 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5956 = _T_5955 | _T_5701; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5702 = _T_4173 ? btb_bank0_rd_data_way1_out_7 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5957 = _T_5956 | _T_5702; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5703 = _T_4175 ? btb_bank0_rd_data_way1_out_8 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5958 = _T_5957 | _T_5703; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5704 = _T_4177 ? btb_bank0_rd_data_way1_out_9 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5959 = _T_5958 | _T_5704; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5705 = _T_4179 ? btb_bank0_rd_data_way1_out_10 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5960 = _T_5959 | _T_5705; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5706 = _T_4181 ? btb_bank0_rd_data_way1_out_11 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5961 = _T_5960 | _T_5706; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5707 = _T_4183 ? btb_bank0_rd_data_way1_out_12 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5962 = _T_5961 | _T_5707; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5708 = _T_4185 ? btb_bank0_rd_data_way1_out_13 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5963 = _T_5962 | _T_5708; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5709 = _T_4187 ? btb_bank0_rd_data_way1_out_14 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5964 = _T_5963 | _T_5709; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5710 = _T_4189 ? btb_bank0_rd_data_way1_out_15 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5965 = _T_5964 | _T_5710; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5711 = _T_4191 ? btb_bank0_rd_data_way1_out_16 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5966 = _T_5965 | _T_5711; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5712 = _T_4193 ? btb_bank0_rd_data_way1_out_17 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5967 = _T_5966 | _T_5712; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5713 = _T_4195 ? btb_bank0_rd_data_way1_out_18 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5968 = _T_5967 | _T_5713; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5714 = _T_4197 ? btb_bank0_rd_data_way1_out_19 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5969 = _T_5968 | _T_5714; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5715 = _T_4199 ? btb_bank0_rd_data_way1_out_20 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5970 = _T_5969 | _T_5715; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5716 = _T_4201 ? btb_bank0_rd_data_way1_out_21 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5971 = _T_5970 | _T_5716; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5717 = _T_4203 ? btb_bank0_rd_data_way1_out_22 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5972 = _T_5971 | _T_5717; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5718 = _T_4205 ? btb_bank0_rd_data_way1_out_23 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5973 = _T_5972 | _T_5718; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5719 = _T_4207 ? btb_bank0_rd_data_way1_out_24 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5974 = _T_5973 | _T_5719; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5720 = _T_4209 ? btb_bank0_rd_data_way1_out_25 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5975 = _T_5974 | _T_5720; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5721 = _T_4211 ? btb_bank0_rd_data_way1_out_26 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5976 = _T_5975 | _T_5721; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5722 = _T_4213 ? btb_bank0_rd_data_way1_out_27 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5977 = _T_5976 | _T_5722; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5723 = _T_4215 ? btb_bank0_rd_data_way1_out_28 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5978 = _T_5977 | _T_5723; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5724 = _T_4217 ? btb_bank0_rd_data_way1_out_29 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5979 = _T_5978 | _T_5724; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5725 = _T_4219 ? btb_bank0_rd_data_way1_out_30 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5980 = _T_5979 | _T_5725; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5726 = _T_4221 ? btb_bank0_rd_data_way1_out_31 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5981 = _T_5980 | _T_5726; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5727 = _T_4223 ? btb_bank0_rd_data_way1_out_32 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5982 = _T_5981 | _T_5727; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5728 = _T_4225 ? btb_bank0_rd_data_way1_out_33 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5983 = _T_5982 | _T_5728; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5729 = _T_4227 ? btb_bank0_rd_data_way1_out_34 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5984 = _T_5983 | _T_5729; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5730 = _T_4229 ? btb_bank0_rd_data_way1_out_35 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5985 = _T_5984 | _T_5730; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5731 = _T_4231 ? btb_bank0_rd_data_way1_out_36 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5986 = _T_5985 | _T_5731; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5732 = _T_4233 ? btb_bank0_rd_data_way1_out_37 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5987 = _T_5986 | _T_5732; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5733 = _T_4235 ? btb_bank0_rd_data_way1_out_38 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5988 = _T_5987 | _T_5733; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5734 = _T_4237 ? btb_bank0_rd_data_way1_out_39 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5989 = _T_5988 | _T_5734; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5735 = _T_4239 ? btb_bank0_rd_data_way1_out_40 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5990 = _T_5989 | _T_5735; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5736 = _T_4241 ? btb_bank0_rd_data_way1_out_41 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5991 = _T_5990 | _T_5736; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5737 = _T_4243 ? btb_bank0_rd_data_way1_out_42 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5992 = _T_5991 | _T_5737; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5738 = _T_4245 ? btb_bank0_rd_data_way1_out_43 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5993 = _T_5992 | _T_5738; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5739 = _T_4247 ? btb_bank0_rd_data_way1_out_44 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5994 = _T_5993 | _T_5739; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5740 = _T_4249 ? btb_bank0_rd_data_way1_out_45 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5995 = _T_5994 | _T_5740; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5741 = _T_4251 ? btb_bank0_rd_data_way1_out_46 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5996 = _T_5995 | _T_5741; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5742 = _T_4253 ? btb_bank0_rd_data_way1_out_47 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5997 = _T_5996 | _T_5742; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5743 = _T_4255 ? btb_bank0_rd_data_way1_out_48 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5998 = _T_5997 | _T_5743; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5744 = _T_4257 ? btb_bank0_rd_data_way1_out_49 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5999 = _T_5998 | _T_5744; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5745 = _T_4259 ? btb_bank0_rd_data_way1_out_50 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6000 = _T_5999 | _T_5745; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5746 = _T_4261 ? btb_bank0_rd_data_way1_out_51 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6001 = _T_6000 | _T_5746; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5747 = _T_4263 ? btb_bank0_rd_data_way1_out_52 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6002 = _T_6001 | _T_5747; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5748 = _T_4265 ? btb_bank0_rd_data_way1_out_53 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6003 = _T_6002 | _T_5748; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5749 = _T_4267 ? btb_bank0_rd_data_way1_out_54 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6004 = _T_6003 | _T_5749; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5750 = _T_4269 ? btb_bank0_rd_data_way1_out_55 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6005 = _T_6004 | _T_5750; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5751 = _T_4271 ? btb_bank0_rd_data_way1_out_56 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6006 = _T_6005 | _T_5751; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5752 = _T_4273 ? btb_bank0_rd_data_way1_out_57 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6007 = _T_6006 | _T_5752; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5753 = _T_4275 ? btb_bank0_rd_data_way1_out_58 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6008 = _T_6007 | _T_5753; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5754 = _T_4277 ? btb_bank0_rd_data_way1_out_59 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6009 = _T_6008 | _T_5754; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5755 = _T_4279 ? btb_bank0_rd_data_way1_out_60 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6010 = _T_6009 | _T_5755; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5756 = _T_4281 ? btb_bank0_rd_data_way1_out_61 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6011 = _T_6010 | _T_5756; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5757 = _T_4283 ? btb_bank0_rd_data_way1_out_62 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6012 = _T_6011 | _T_5757; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5758 = _T_4285 ? btb_bank0_rd_data_way1_out_63 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6013 = _T_6012 | _T_5758; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5759 = _T_4287 ? btb_bank0_rd_data_way1_out_64 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6014 = _T_6013 | _T_5759; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5760 = _T_4289 ? btb_bank0_rd_data_way1_out_65 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6015 = _T_6014 | _T_5760; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5761 = _T_4291 ? btb_bank0_rd_data_way1_out_66 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6016 = _T_6015 | _T_5761; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5762 = _T_4293 ? btb_bank0_rd_data_way1_out_67 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6017 = _T_6016 | _T_5762; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5763 = _T_4295 ? btb_bank0_rd_data_way1_out_68 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6018 = _T_6017 | _T_5763; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5764 = _T_4297 ? btb_bank0_rd_data_way1_out_69 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6019 = _T_6018 | _T_5764; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5765 = _T_4299 ? btb_bank0_rd_data_way1_out_70 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6020 = _T_6019 | _T_5765; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5766 = _T_4301 ? btb_bank0_rd_data_way1_out_71 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6021 = _T_6020 | _T_5766; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5767 = _T_4303 ? btb_bank0_rd_data_way1_out_72 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6022 = _T_6021 | _T_5767; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5768 = _T_4305 ? btb_bank0_rd_data_way1_out_73 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6023 = _T_6022 | _T_5768; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5769 = _T_4307 ? btb_bank0_rd_data_way1_out_74 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6024 = _T_6023 | _T_5769; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5770 = _T_4309 ? btb_bank0_rd_data_way1_out_75 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6025 = _T_6024 | _T_5770; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5771 = _T_4311 ? btb_bank0_rd_data_way1_out_76 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6026 = _T_6025 | _T_5771; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5772 = _T_4313 ? btb_bank0_rd_data_way1_out_77 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6027 = _T_6026 | _T_5772; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5773 = _T_4315 ? btb_bank0_rd_data_way1_out_78 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6028 = _T_6027 | _T_5773; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5774 = _T_4317 ? btb_bank0_rd_data_way1_out_79 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6029 = _T_6028 | _T_5774; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5775 = _T_4319 ? btb_bank0_rd_data_way1_out_80 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6030 = _T_6029 | _T_5775; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5776 = _T_4321 ? btb_bank0_rd_data_way1_out_81 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6031 = _T_6030 | _T_5776; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5777 = _T_4323 ? btb_bank0_rd_data_way1_out_82 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6032 = _T_6031 | _T_5777; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5778 = _T_4325 ? btb_bank0_rd_data_way1_out_83 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6033 = _T_6032 | _T_5778; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5779 = _T_4327 ? btb_bank0_rd_data_way1_out_84 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6034 = _T_6033 | _T_5779; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5780 = _T_4329 ? btb_bank0_rd_data_way1_out_85 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6035 = _T_6034 | _T_5780; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5781 = _T_4331 ? btb_bank0_rd_data_way1_out_86 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6036 = _T_6035 | _T_5781; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5782 = _T_4333 ? btb_bank0_rd_data_way1_out_87 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6037 = _T_6036 | _T_5782; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5783 = _T_4335 ? btb_bank0_rd_data_way1_out_88 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6038 = _T_6037 | _T_5783; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5784 = _T_4337 ? btb_bank0_rd_data_way1_out_89 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6039 = _T_6038 | _T_5784; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5785 = _T_4339 ? btb_bank0_rd_data_way1_out_90 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6040 = _T_6039 | _T_5785; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5786 = _T_4341 ? btb_bank0_rd_data_way1_out_91 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6041 = _T_6040 | _T_5786; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5787 = _T_4343 ? btb_bank0_rd_data_way1_out_92 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6042 = _T_6041 | _T_5787; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5788 = _T_4345 ? btb_bank0_rd_data_way1_out_93 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6043 = _T_6042 | _T_5788; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5789 = _T_4347 ? btb_bank0_rd_data_way1_out_94 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6044 = _T_6043 | _T_5789; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5790 = _T_4349 ? btb_bank0_rd_data_way1_out_95 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6045 = _T_6044 | _T_5790; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5791 = _T_4351 ? btb_bank0_rd_data_way1_out_96 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6046 = _T_6045 | _T_5791; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5792 = _T_4353 ? btb_bank0_rd_data_way1_out_97 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6047 = _T_6046 | _T_5792; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5793 = _T_4355 ? btb_bank0_rd_data_way1_out_98 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6048 = _T_6047 | _T_5793; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5794 = _T_4357 ? btb_bank0_rd_data_way1_out_99 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6049 = _T_6048 | _T_5794; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5795 = _T_4359 ? btb_bank0_rd_data_way1_out_100 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6050 = _T_6049 | _T_5795; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5796 = _T_4361 ? btb_bank0_rd_data_way1_out_101 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6051 = _T_6050 | _T_5796; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5797 = _T_4363 ? btb_bank0_rd_data_way1_out_102 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6052 = _T_6051 | _T_5797; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5798 = _T_4365 ? btb_bank0_rd_data_way1_out_103 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6053 = _T_6052 | _T_5798; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5799 = _T_4367 ? btb_bank0_rd_data_way1_out_104 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6054 = _T_6053 | _T_5799; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5800 = _T_4369 ? btb_bank0_rd_data_way1_out_105 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6055 = _T_6054 | _T_5800; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5801 = _T_4371 ? btb_bank0_rd_data_way1_out_106 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6056 = _T_6055 | _T_5801; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5802 = _T_4373 ? btb_bank0_rd_data_way1_out_107 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6057 = _T_6056 | _T_5802; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5803 = _T_4375 ? btb_bank0_rd_data_way1_out_108 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6058 = _T_6057 | _T_5803; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5804 = _T_4377 ? btb_bank0_rd_data_way1_out_109 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6059 = _T_6058 | _T_5804; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5805 = _T_4379 ? btb_bank0_rd_data_way1_out_110 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6060 = _T_6059 | _T_5805; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5806 = _T_4381 ? btb_bank0_rd_data_way1_out_111 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6061 = _T_6060 | _T_5806; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5807 = _T_4383 ? btb_bank0_rd_data_way1_out_112 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6062 = _T_6061 | _T_5807; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5808 = _T_4385 ? btb_bank0_rd_data_way1_out_113 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6063 = _T_6062 | _T_5808; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5809 = _T_4387 ? btb_bank0_rd_data_way1_out_114 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6064 = _T_6063 | _T_5809; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5810 = _T_4389 ? btb_bank0_rd_data_way1_out_115 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6065 = _T_6064 | _T_5810; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5811 = _T_4391 ? btb_bank0_rd_data_way1_out_116 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6066 = _T_6065 | _T_5811; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5812 = _T_4393 ? btb_bank0_rd_data_way1_out_117 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6067 = _T_6066 | _T_5812; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5813 = _T_4395 ? btb_bank0_rd_data_way1_out_118 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6068 = _T_6067 | _T_5813; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5814 = _T_4397 ? btb_bank0_rd_data_way1_out_119 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6069 = _T_6068 | _T_5814; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5815 = _T_4399 ? btb_bank0_rd_data_way1_out_120 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6070 = _T_6069 | _T_5815; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5816 = _T_4401 ? btb_bank0_rd_data_way1_out_121 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6071 = _T_6070 | _T_5816; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5817 = _T_4403 ? btb_bank0_rd_data_way1_out_122 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6072 = _T_6071 | _T_5817; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5818 = _T_4405 ? btb_bank0_rd_data_way1_out_123 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6073 = _T_6072 | _T_5818; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5819 = _T_4407 ? btb_bank0_rd_data_way1_out_124 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6074 = _T_6073 | _T_5819; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5820 = _T_4409 ? btb_bank0_rd_data_way1_out_125 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6075 = _T_6074 | _T_5820; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5821 = _T_4411 ? btb_bank0_rd_data_way1_out_126 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6076 = _T_6075 | _T_5821; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5822 = _T_4413 ? btb_bank0_rd_data_way1_out_127 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6077 = _T_6076 | _T_5822; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5823 = _T_4415 ? btb_bank0_rd_data_way1_out_128 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6078 = _T_6077 | _T_5823; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5824 = _T_4417 ? btb_bank0_rd_data_way1_out_129 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6079 = _T_6078 | _T_5824; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5825 = _T_4419 ? btb_bank0_rd_data_way1_out_130 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6080 = _T_6079 | _T_5825; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5826 = _T_4421 ? btb_bank0_rd_data_way1_out_131 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6081 = _T_6080 | _T_5826; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5827 = _T_4423 ? btb_bank0_rd_data_way1_out_132 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6082 = _T_6081 | _T_5827; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5828 = _T_4425 ? btb_bank0_rd_data_way1_out_133 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6083 = _T_6082 | _T_5828; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5829 = _T_4427 ? btb_bank0_rd_data_way1_out_134 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6084 = _T_6083 | _T_5829; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5830 = _T_4429 ? btb_bank0_rd_data_way1_out_135 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6085 = _T_6084 | _T_5830; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5831 = _T_4431 ? btb_bank0_rd_data_way1_out_136 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6086 = _T_6085 | _T_5831; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5832 = _T_4433 ? btb_bank0_rd_data_way1_out_137 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6087 = _T_6086 | _T_5832; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5833 = _T_4435 ? btb_bank0_rd_data_way1_out_138 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6088 = _T_6087 | _T_5833; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5834 = _T_4437 ? btb_bank0_rd_data_way1_out_139 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6089 = _T_6088 | _T_5834; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5835 = _T_4439 ? btb_bank0_rd_data_way1_out_140 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6090 = _T_6089 | _T_5835; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5836 = _T_4441 ? btb_bank0_rd_data_way1_out_141 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6091 = _T_6090 | _T_5836; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5837 = _T_4443 ? btb_bank0_rd_data_way1_out_142 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6092 = _T_6091 | _T_5837; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5838 = _T_4445 ? btb_bank0_rd_data_way1_out_143 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6093 = _T_6092 | _T_5838; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5839 = _T_4447 ? btb_bank0_rd_data_way1_out_144 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6094 = _T_6093 | _T_5839; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5840 = _T_4449 ? btb_bank0_rd_data_way1_out_145 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6095 = _T_6094 | _T_5840; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5841 = _T_4451 ? btb_bank0_rd_data_way1_out_146 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6096 = _T_6095 | _T_5841; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5842 = _T_4453 ? btb_bank0_rd_data_way1_out_147 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6097 = _T_6096 | _T_5842; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5843 = _T_4455 ? btb_bank0_rd_data_way1_out_148 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6098 = _T_6097 | _T_5843; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5844 = _T_4457 ? btb_bank0_rd_data_way1_out_149 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6099 = _T_6098 | _T_5844; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5845 = _T_4459 ? btb_bank0_rd_data_way1_out_150 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6100 = _T_6099 | _T_5845; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5846 = _T_4461 ? btb_bank0_rd_data_way1_out_151 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6101 = _T_6100 | _T_5846; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5847 = _T_4463 ? btb_bank0_rd_data_way1_out_152 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6102 = _T_6101 | _T_5847; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5848 = _T_4465 ? btb_bank0_rd_data_way1_out_153 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6103 = _T_6102 | _T_5848; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5849 = _T_4467 ? btb_bank0_rd_data_way1_out_154 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6104 = _T_6103 | _T_5849; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5850 = _T_4469 ? btb_bank0_rd_data_way1_out_155 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6105 = _T_6104 | _T_5850; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5851 = _T_4471 ? btb_bank0_rd_data_way1_out_156 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6106 = _T_6105 | _T_5851; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5852 = _T_4473 ? btb_bank0_rd_data_way1_out_157 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6107 = _T_6106 | _T_5852; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5853 = _T_4475 ? btb_bank0_rd_data_way1_out_158 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6108 = _T_6107 | _T_5853; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5854 = _T_4477 ? btb_bank0_rd_data_way1_out_159 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6109 = _T_6108 | _T_5854; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5855 = _T_4479 ? btb_bank0_rd_data_way1_out_160 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6110 = _T_6109 | _T_5855; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5856 = _T_4481 ? btb_bank0_rd_data_way1_out_161 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6111 = _T_6110 | _T_5856; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5857 = _T_4483 ? btb_bank0_rd_data_way1_out_162 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6112 = _T_6111 | _T_5857; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5858 = _T_4485 ? btb_bank0_rd_data_way1_out_163 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6113 = _T_6112 | _T_5858; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5859 = _T_4487 ? btb_bank0_rd_data_way1_out_164 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6114 = _T_6113 | _T_5859; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5860 = _T_4489 ? btb_bank0_rd_data_way1_out_165 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6115 = _T_6114 | _T_5860; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5861 = _T_4491 ? btb_bank0_rd_data_way1_out_166 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6116 = _T_6115 | _T_5861; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5862 = _T_4493 ? btb_bank0_rd_data_way1_out_167 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6117 = _T_6116 | _T_5862; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5863 = _T_4495 ? btb_bank0_rd_data_way1_out_168 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6118 = _T_6117 | _T_5863; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5864 = _T_4497 ? btb_bank0_rd_data_way1_out_169 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6119 = _T_6118 | _T_5864; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5865 = _T_4499 ? btb_bank0_rd_data_way1_out_170 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6120 = _T_6119 | _T_5865; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5866 = _T_4501 ? btb_bank0_rd_data_way1_out_171 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6121 = _T_6120 | _T_5866; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5867 = _T_4503 ? btb_bank0_rd_data_way1_out_172 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6122 = _T_6121 | _T_5867; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5868 = _T_4505 ? btb_bank0_rd_data_way1_out_173 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6123 = _T_6122 | _T_5868; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5869 = _T_4507 ? btb_bank0_rd_data_way1_out_174 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6124 = _T_6123 | _T_5869; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5870 = _T_4509 ? btb_bank0_rd_data_way1_out_175 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6125 = _T_6124 | _T_5870; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5871 = _T_4511 ? btb_bank0_rd_data_way1_out_176 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6126 = _T_6125 | _T_5871; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5872 = _T_4513 ? btb_bank0_rd_data_way1_out_177 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6127 = _T_6126 | _T_5872; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5873 = _T_4515 ? btb_bank0_rd_data_way1_out_178 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6128 = _T_6127 | _T_5873; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5874 = _T_4517 ? btb_bank0_rd_data_way1_out_179 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6129 = _T_6128 | _T_5874; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5875 = _T_4519 ? btb_bank0_rd_data_way1_out_180 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6130 = _T_6129 | _T_5875; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5876 = _T_4521 ? btb_bank0_rd_data_way1_out_181 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6131 = _T_6130 | _T_5876; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5877 = _T_4523 ? btb_bank0_rd_data_way1_out_182 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6132 = _T_6131 | _T_5877; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5878 = _T_4525 ? btb_bank0_rd_data_way1_out_183 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6133 = _T_6132 | _T_5878; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5879 = _T_4527 ? btb_bank0_rd_data_way1_out_184 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6134 = _T_6133 | _T_5879; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5880 = _T_4529 ? btb_bank0_rd_data_way1_out_185 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6135 = _T_6134 | _T_5880; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5881 = _T_4531 ? btb_bank0_rd_data_way1_out_186 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6136 = _T_6135 | _T_5881; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5882 = _T_4533 ? btb_bank0_rd_data_way1_out_187 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6137 = _T_6136 | _T_5882; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5883 = _T_4535 ? btb_bank0_rd_data_way1_out_188 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6138 = _T_6137 | _T_5883; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5884 = _T_4537 ? btb_bank0_rd_data_way1_out_189 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6139 = _T_6138 | _T_5884; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5885 = _T_4539 ? btb_bank0_rd_data_way1_out_190 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6140 = _T_6139 | _T_5885; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5886 = _T_4541 ? btb_bank0_rd_data_way1_out_191 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6141 = _T_6140 | _T_5886; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5887 = _T_4543 ? btb_bank0_rd_data_way1_out_192 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6142 = _T_6141 | _T_5887; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5888 = _T_4545 ? btb_bank0_rd_data_way1_out_193 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6143 = _T_6142 | _T_5888; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5889 = _T_4547 ? btb_bank0_rd_data_way1_out_194 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6144 = _T_6143 | _T_5889; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5890 = _T_4549 ? btb_bank0_rd_data_way1_out_195 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6145 = _T_6144 | _T_5890; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5891 = _T_4551 ? btb_bank0_rd_data_way1_out_196 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6146 = _T_6145 | _T_5891; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5892 = _T_4553 ? btb_bank0_rd_data_way1_out_197 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6147 = _T_6146 | _T_5892; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5893 = _T_4555 ? btb_bank0_rd_data_way1_out_198 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6148 = _T_6147 | _T_5893; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5894 = _T_4557 ? btb_bank0_rd_data_way1_out_199 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6149 = _T_6148 | _T_5894; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5895 = _T_4559 ? btb_bank0_rd_data_way1_out_200 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6150 = _T_6149 | _T_5895; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5896 = _T_4561 ? btb_bank0_rd_data_way1_out_201 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6151 = _T_6150 | _T_5896; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5897 = _T_4563 ? btb_bank0_rd_data_way1_out_202 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6152 = _T_6151 | _T_5897; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5898 = _T_4565 ? btb_bank0_rd_data_way1_out_203 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6153 = _T_6152 | _T_5898; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5899 = _T_4567 ? btb_bank0_rd_data_way1_out_204 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6154 = _T_6153 | _T_5899; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5900 = _T_4569 ? btb_bank0_rd_data_way1_out_205 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6155 = _T_6154 | _T_5900; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5901 = _T_4571 ? btb_bank0_rd_data_way1_out_206 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6156 = _T_6155 | _T_5901; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5902 = _T_4573 ? btb_bank0_rd_data_way1_out_207 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6157 = _T_6156 | _T_5902; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5903 = _T_4575 ? btb_bank0_rd_data_way1_out_208 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6158 = _T_6157 | _T_5903; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5904 = _T_4577 ? btb_bank0_rd_data_way1_out_209 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6159 = _T_6158 | _T_5904; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5905 = _T_4579 ? btb_bank0_rd_data_way1_out_210 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6160 = _T_6159 | _T_5905; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5906 = _T_4581 ? btb_bank0_rd_data_way1_out_211 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6161 = _T_6160 | _T_5906; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5907 = _T_4583 ? btb_bank0_rd_data_way1_out_212 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6162 = _T_6161 | _T_5907; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5908 = _T_4585 ? btb_bank0_rd_data_way1_out_213 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6163 = _T_6162 | _T_5908; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5909 = _T_4587 ? btb_bank0_rd_data_way1_out_214 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6164 = _T_6163 | _T_5909; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5910 = _T_4589 ? btb_bank0_rd_data_way1_out_215 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6165 = _T_6164 | _T_5910; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5911 = _T_4591 ? btb_bank0_rd_data_way1_out_216 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6166 = _T_6165 | _T_5911; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5912 = _T_4593 ? btb_bank0_rd_data_way1_out_217 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6167 = _T_6166 | _T_5912; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5913 = _T_4595 ? btb_bank0_rd_data_way1_out_218 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6168 = _T_6167 | _T_5913; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5914 = _T_4597 ? btb_bank0_rd_data_way1_out_219 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6169 = _T_6168 | _T_5914; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5915 = _T_4599 ? btb_bank0_rd_data_way1_out_220 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6170 = _T_6169 | _T_5915; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5916 = _T_4601 ? btb_bank0_rd_data_way1_out_221 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6171 = _T_6170 | _T_5916; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5917 = _T_4603 ? btb_bank0_rd_data_way1_out_222 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6172 = _T_6171 | _T_5917; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5918 = _T_4605 ? btb_bank0_rd_data_way1_out_223 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6173 = _T_6172 | _T_5918; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5919 = _T_4607 ? btb_bank0_rd_data_way1_out_224 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6174 = _T_6173 | _T_5919; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5920 = _T_4609 ? btb_bank0_rd_data_way1_out_225 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6175 = _T_6174 | _T_5920; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5921 = _T_4611 ? btb_bank0_rd_data_way1_out_226 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6176 = _T_6175 | _T_5921; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5922 = _T_4613 ? btb_bank0_rd_data_way1_out_227 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6177 = _T_6176 | _T_5922; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5923 = _T_4615 ? btb_bank0_rd_data_way1_out_228 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6178 = _T_6177 | _T_5923; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5924 = _T_4617 ? btb_bank0_rd_data_way1_out_229 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6179 = _T_6178 | _T_5924; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5925 = _T_4619 ? btb_bank0_rd_data_way1_out_230 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6180 = _T_6179 | _T_5925; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5926 = _T_4621 ? btb_bank0_rd_data_way1_out_231 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6181 = _T_6180 | _T_5926; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5927 = _T_4623 ? btb_bank0_rd_data_way1_out_232 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6182 = _T_6181 | _T_5927; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5928 = _T_4625 ? btb_bank0_rd_data_way1_out_233 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6183 = _T_6182 | _T_5928; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5929 = _T_4627 ? btb_bank0_rd_data_way1_out_234 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6184 = _T_6183 | _T_5929; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5930 = _T_4629 ? btb_bank0_rd_data_way1_out_235 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6185 = _T_6184 | _T_5930; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5931 = _T_4631 ? btb_bank0_rd_data_way1_out_236 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6186 = _T_6185 | _T_5931; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5932 = _T_4633 ? btb_bank0_rd_data_way1_out_237 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6187 = _T_6186 | _T_5932; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5933 = _T_4635 ? btb_bank0_rd_data_way1_out_238 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6188 = _T_6187 | _T_5933; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5934 = _T_4637 ? btb_bank0_rd_data_way1_out_239 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6189 = _T_6188 | _T_5934; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5935 = _T_4639 ? btb_bank0_rd_data_way1_out_240 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6190 = _T_6189 | _T_5935; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5936 = _T_4641 ? btb_bank0_rd_data_way1_out_241 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6191 = _T_6190 | _T_5936; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5937 = _T_4643 ? btb_bank0_rd_data_way1_out_242 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6192 = _T_6191 | _T_5937; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5938 = _T_4645 ? btb_bank0_rd_data_way1_out_243 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6193 = _T_6192 | _T_5938; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5939 = _T_4647 ? btb_bank0_rd_data_way1_out_244 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6194 = _T_6193 | _T_5939; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5940 = _T_4649 ? btb_bank0_rd_data_way1_out_245 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6195 = _T_6194 | _T_5940; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5941 = _T_4651 ? btb_bank0_rd_data_way1_out_246 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6196 = _T_6195 | _T_5941; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5942 = _T_4653 ? btb_bank0_rd_data_way1_out_247 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6197 = _T_6196 | _T_5942; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5943 = _T_4655 ? btb_bank0_rd_data_way1_out_248 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6198 = _T_6197 | _T_5943; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5944 = _T_4657 ? btb_bank0_rd_data_way1_out_249 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6199 = _T_6198 | _T_5944; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5945 = _T_4659 ? btb_bank0_rd_data_way1_out_250 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6200 = _T_6199 | _T_5945; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5946 = _T_4661 ? btb_bank0_rd_data_way1_out_251 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6201 = _T_6200 | _T_5946; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5947 = _T_4663 ? btb_bank0_rd_data_way1_out_252 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6202 = _T_6201 | _T_5947; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5948 = _T_4665 ? btb_bank0_rd_data_way1_out_253 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6203 = _T_6202 | _T_5948; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5949 = _T_4667 ? btb_bank0_rd_data_way1_out_254 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6204 = _T_6203 | _T_5949; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5950 = _T_4669 ? btb_bank0_rd_data_way1_out_255 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_bank0_rd_data_way1_p1_f = _T_6204 | _T_5950; // @[Mux.scala 27:72]
|
|
wire _T_72 = btb_bank0_rd_data_way1_p1_f[21:17] == fetch_rd_tag_p1_f; // @[el2_ifu_bp_ctl.scala 150:106]
|
|
wire _T_73 = btb_bank0_rd_data_way1_p1_f[0] & _T_72; // @[el2_ifu_bp_ctl.scala 150:61]
|
|
wire _T_76 = _T_73 & _T_48; // @[el2_ifu_bp_ctl.scala 150:129]
|
|
wire _T_77 = _T_76 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 151:56]
|
|
wire tag_match_way1_p1_f = _T_77 & _T; // @[el2_ifu_bp_ctl.scala 151:77]
|
|
wire _T_108 = btb_bank0_rd_data_way1_p1_f[3] ^ btb_bank0_rd_data_way1_p1_f[4]; // @[el2_ifu_bp_ctl.scala 163:100]
|
|
wire _T_109 = tag_match_way1_p1_f & _T_108; // @[el2_ifu_bp_ctl.scala 163:62]
|
|
wire _T_113 = ~_T_108; // @[el2_ifu_bp_ctl.scala 164:64]
|
|
wire _T_114 = tag_match_way1_p1_f & _T_113; // @[el2_ifu_bp_ctl.scala 164:62]
|
|
wire [1:0] tag_match_way1_expanded_p1_f = {_T_109,_T_114}; // @[Cat.scala 29:58]
|
|
wire [21:0] _T_134 = tag_match_way1_expanded_p1_f[0] ? btb_bank0_rd_data_way1_p1_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_bank0e_rd_data_p1_f = _T_133 | _T_134; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_146 = io_ifc_fetch_addr_f[0] ? btb_bank0e_rd_data_p1_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_vbank1_rd_data_f = _T_145 | _T_146; // @[Mux.scala 27:72]
|
|
wire _T_242 = btb_vbank1_rd_data_f[2] | btb_vbank1_rd_data_f[1]; // @[el2_ifu_bp_ctl.scala 276:59]
|
|
wire [21:0] _T_119 = tag_match_way0_expanded_f[0] ? btb_bank0_rd_data_way0_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_120 = tag_match_way1_expanded_f[0] ? btb_bank0_rd_data_way1_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_bank0e_rd_data_f = _T_119 | _T_120; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_139 = _T_143 ? btb_bank0e_rd_data_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_140 = io_ifc_fetch_addr_f[0] ? btb_bank0o_rd_data_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_vbank0_rd_data_f = _T_139 | _T_140; // @[Mux.scala 27:72]
|
|
wire _T_245 = btb_vbank0_rd_data_f[2] | btb_vbank0_rd_data_f[1]; // @[el2_ifu_bp_ctl.scala 277:59]
|
|
wire [1:0] bht_force_taken_f = {_T_242,_T_245}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_569 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58]
|
|
reg [7:0] fghr; // @[el2_ifu_bp_ctl.scala 335:44]
|
|
wire [7:0] bht_rd_addr_hashed_f = _T_569[9:2] ^ fghr; // @[el2_lib.scala 196:35]
|
|
wire _T_21407 = bht_rd_addr_hashed_f == 8'h0; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21919 = _T_21407 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72]
|
|
wire _T_21409 = bht_rd_addr_hashed_f == 8'h1; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_1; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21920 = _T_21409 ? bht_bank_rd_data_out_1_1 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22175 = _T_21919 | _T_21920; // @[Mux.scala 27:72]
|
|
wire _T_21411 = bht_rd_addr_hashed_f == 8'h2; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_2; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21921 = _T_21411 ? bht_bank_rd_data_out_1_2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22176 = _T_22175 | _T_21921; // @[Mux.scala 27:72]
|
|
wire _T_21413 = bht_rd_addr_hashed_f == 8'h3; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_3; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21922 = _T_21413 ? bht_bank_rd_data_out_1_3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22177 = _T_22176 | _T_21922; // @[Mux.scala 27:72]
|
|
wire _T_21415 = bht_rd_addr_hashed_f == 8'h4; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_4; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21923 = _T_21415 ? bht_bank_rd_data_out_1_4 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22178 = _T_22177 | _T_21923; // @[Mux.scala 27:72]
|
|
wire _T_21417 = bht_rd_addr_hashed_f == 8'h5; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_5; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21924 = _T_21417 ? bht_bank_rd_data_out_1_5 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22179 = _T_22178 | _T_21924; // @[Mux.scala 27:72]
|
|
wire _T_21419 = bht_rd_addr_hashed_f == 8'h6; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_6; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21925 = _T_21419 ? bht_bank_rd_data_out_1_6 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22180 = _T_22179 | _T_21925; // @[Mux.scala 27:72]
|
|
wire _T_21421 = bht_rd_addr_hashed_f == 8'h7; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_7; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21926 = _T_21421 ? bht_bank_rd_data_out_1_7 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22181 = _T_22180 | _T_21926; // @[Mux.scala 27:72]
|
|
wire _T_21423 = bht_rd_addr_hashed_f == 8'h8; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_8; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21927 = _T_21423 ? bht_bank_rd_data_out_1_8 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22182 = _T_22181 | _T_21927; // @[Mux.scala 27:72]
|
|
wire _T_21425 = bht_rd_addr_hashed_f == 8'h9; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_9; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21928 = _T_21425 ? bht_bank_rd_data_out_1_9 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22183 = _T_22182 | _T_21928; // @[Mux.scala 27:72]
|
|
wire _T_21427 = bht_rd_addr_hashed_f == 8'ha; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_10; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21929 = _T_21427 ? bht_bank_rd_data_out_1_10 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22184 = _T_22183 | _T_21929; // @[Mux.scala 27:72]
|
|
wire _T_21429 = bht_rd_addr_hashed_f == 8'hb; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_11; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21930 = _T_21429 ? bht_bank_rd_data_out_1_11 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22185 = _T_22184 | _T_21930; // @[Mux.scala 27:72]
|
|
wire _T_21431 = bht_rd_addr_hashed_f == 8'hc; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_12; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21931 = _T_21431 ? bht_bank_rd_data_out_1_12 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22186 = _T_22185 | _T_21931; // @[Mux.scala 27:72]
|
|
wire _T_21433 = bht_rd_addr_hashed_f == 8'hd; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_13; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21932 = _T_21433 ? bht_bank_rd_data_out_1_13 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22187 = _T_22186 | _T_21932; // @[Mux.scala 27:72]
|
|
wire _T_21435 = bht_rd_addr_hashed_f == 8'he; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_14; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21933 = _T_21435 ? bht_bank_rd_data_out_1_14 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22188 = _T_22187 | _T_21933; // @[Mux.scala 27:72]
|
|
wire _T_21437 = bht_rd_addr_hashed_f == 8'hf; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_15; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21934 = _T_21437 ? bht_bank_rd_data_out_1_15 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22189 = _T_22188 | _T_21934; // @[Mux.scala 27:72]
|
|
wire _T_21439 = bht_rd_addr_hashed_f == 8'h10; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_16; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21935 = _T_21439 ? bht_bank_rd_data_out_1_16 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22190 = _T_22189 | _T_21935; // @[Mux.scala 27:72]
|
|
wire _T_21441 = bht_rd_addr_hashed_f == 8'h11; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_17; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21936 = _T_21441 ? bht_bank_rd_data_out_1_17 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22191 = _T_22190 | _T_21936; // @[Mux.scala 27:72]
|
|
wire _T_21443 = bht_rd_addr_hashed_f == 8'h12; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_18; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21937 = _T_21443 ? bht_bank_rd_data_out_1_18 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22192 = _T_22191 | _T_21937; // @[Mux.scala 27:72]
|
|
wire _T_21445 = bht_rd_addr_hashed_f == 8'h13; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_19; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21938 = _T_21445 ? bht_bank_rd_data_out_1_19 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22193 = _T_22192 | _T_21938; // @[Mux.scala 27:72]
|
|
wire _T_21447 = bht_rd_addr_hashed_f == 8'h14; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_20; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21939 = _T_21447 ? bht_bank_rd_data_out_1_20 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22194 = _T_22193 | _T_21939; // @[Mux.scala 27:72]
|
|
wire _T_21449 = bht_rd_addr_hashed_f == 8'h15; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_21; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21940 = _T_21449 ? bht_bank_rd_data_out_1_21 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22195 = _T_22194 | _T_21940; // @[Mux.scala 27:72]
|
|
wire _T_21451 = bht_rd_addr_hashed_f == 8'h16; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_22; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21941 = _T_21451 ? bht_bank_rd_data_out_1_22 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22196 = _T_22195 | _T_21941; // @[Mux.scala 27:72]
|
|
wire _T_21453 = bht_rd_addr_hashed_f == 8'h17; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_23; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21942 = _T_21453 ? bht_bank_rd_data_out_1_23 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22197 = _T_22196 | _T_21942; // @[Mux.scala 27:72]
|
|
wire _T_21455 = bht_rd_addr_hashed_f == 8'h18; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_24; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21943 = _T_21455 ? bht_bank_rd_data_out_1_24 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22198 = _T_22197 | _T_21943; // @[Mux.scala 27:72]
|
|
wire _T_21457 = bht_rd_addr_hashed_f == 8'h19; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_25; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21944 = _T_21457 ? bht_bank_rd_data_out_1_25 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22199 = _T_22198 | _T_21944; // @[Mux.scala 27:72]
|
|
wire _T_21459 = bht_rd_addr_hashed_f == 8'h1a; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_26; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21945 = _T_21459 ? bht_bank_rd_data_out_1_26 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22200 = _T_22199 | _T_21945; // @[Mux.scala 27:72]
|
|
wire _T_21461 = bht_rd_addr_hashed_f == 8'h1b; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_27; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21946 = _T_21461 ? bht_bank_rd_data_out_1_27 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22201 = _T_22200 | _T_21946; // @[Mux.scala 27:72]
|
|
wire _T_21463 = bht_rd_addr_hashed_f == 8'h1c; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_28; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21947 = _T_21463 ? bht_bank_rd_data_out_1_28 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22202 = _T_22201 | _T_21947; // @[Mux.scala 27:72]
|
|
wire _T_21465 = bht_rd_addr_hashed_f == 8'h1d; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_29; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21948 = _T_21465 ? bht_bank_rd_data_out_1_29 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22203 = _T_22202 | _T_21948; // @[Mux.scala 27:72]
|
|
wire _T_21467 = bht_rd_addr_hashed_f == 8'h1e; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_30; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21949 = _T_21467 ? bht_bank_rd_data_out_1_30 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22204 = _T_22203 | _T_21949; // @[Mux.scala 27:72]
|
|
wire _T_21469 = bht_rd_addr_hashed_f == 8'h1f; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_31; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21950 = _T_21469 ? bht_bank_rd_data_out_1_31 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22205 = _T_22204 | _T_21950; // @[Mux.scala 27:72]
|
|
wire _T_21471 = bht_rd_addr_hashed_f == 8'h20; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_32; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21951 = _T_21471 ? bht_bank_rd_data_out_1_32 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22206 = _T_22205 | _T_21951; // @[Mux.scala 27:72]
|
|
wire _T_21473 = bht_rd_addr_hashed_f == 8'h21; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_33; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21952 = _T_21473 ? bht_bank_rd_data_out_1_33 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22207 = _T_22206 | _T_21952; // @[Mux.scala 27:72]
|
|
wire _T_21475 = bht_rd_addr_hashed_f == 8'h22; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_34; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21953 = _T_21475 ? bht_bank_rd_data_out_1_34 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22208 = _T_22207 | _T_21953; // @[Mux.scala 27:72]
|
|
wire _T_21477 = bht_rd_addr_hashed_f == 8'h23; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_35; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21954 = _T_21477 ? bht_bank_rd_data_out_1_35 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22209 = _T_22208 | _T_21954; // @[Mux.scala 27:72]
|
|
wire _T_21479 = bht_rd_addr_hashed_f == 8'h24; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_36; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21955 = _T_21479 ? bht_bank_rd_data_out_1_36 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22210 = _T_22209 | _T_21955; // @[Mux.scala 27:72]
|
|
wire _T_21481 = bht_rd_addr_hashed_f == 8'h25; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_37; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21956 = _T_21481 ? bht_bank_rd_data_out_1_37 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22211 = _T_22210 | _T_21956; // @[Mux.scala 27:72]
|
|
wire _T_21483 = bht_rd_addr_hashed_f == 8'h26; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_38; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21957 = _T_21483 ? bht_bank_rd_data_out_1_38 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22212 = _T_22211 | _T_21957; // @[Mux.scala 27:72]
|
|
wire _T_21485 = bht_rd_addr_hashed_f == 8'h27; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_39; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21958 = _T_21485 ? bht_bank_rd_data_out_1_39 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22213 = _T_22212 | _T_21958; // @[Mux.scala 27:72]
|
|
wire _T_21487 = bht_rd_addr_hashed_f == 8'h28; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_40; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21959 = _T_21487 ? bht_bank_rd_data_out_1_40 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22214 = _T_22213 | _T_21959; // @[Mux.scala 27:72]
|
|
wire _T_21489 = bht_rd_addr_hashed_f == 8'h29; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_41; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21960 = _T_21489 ? bht_bank_rd_data_out_1_41 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22215 = _T_22214 | _T_21960; // @[Mux.scala 27:72]
|
|
wire _T_21491 = bht_rd_addr_hashed_f == 8'h2a; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_42; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21961 = _T_21491 ? bht_bank_rd_data_out_1_42 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22216 = _T_22215 | _T_21961; // @[Mux.scala 27:72]
|
|
wire _T_21493 = bht_rd_addr_hashed_f == 8'h2b; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_43; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21962 = _T_21493 ? bht_bank_rd_data_out_1_43 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22217 = _T_22216 | _T_21962; // @[Mux.scala 27:72]
|
|
wire _T_21495 = bht_rd_addr_hashed_f == 8'h2c; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_44; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21963 = _T_21495 ? bht_bank_rd_data_out_1_44 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22218 = _T_22217 | _T_21963; // @[Mux.scala 27:72]
|
|
wire _T_21497 = bht_rd_addr_hashed_f == 8'h2d; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_45; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21964 = _T_21497 ? bht_bank_rd_data_out_1_45 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22219 = _T_22218 | _T_21964; // @[Mux.scala 27:72]
|
|
wire _T_21499 = bht_rd_addr_hashed_f == 8'h2e; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_46; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21965 = _T_21499 ? bht_bank_rd_data_out_1_46 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22220 = _T_22219 | _T_21965; // @[Mux.scala 27:72]
|
|
wire _T_21501 = bht_rd_addr_hashed_f == 8'h2f; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_47; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21966 = _T_21501 ? bht_bank_rd_data_out_1_47 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22221 = _T_22220 | _T_21966; // @[Mux.scala 27:72]
|
|
wire _T_21503 = bht_rd_addr_hashed_f == 8'h30; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_48; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21967 = _T_21503 ? bht_bank_rd_data_out_1_48 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22222 = _T_22221 | _T_21967; // @[Mux.scala 27:72]
|
|
wire _T_21505 = bht_rd_addr_hashed_f == 8'h31; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_49; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21968 = _T_21505 ? bht_bank_rd_data_out_1_49 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22223 = _T_22222 | _T_21968; // @[Mux.scala 27:72]
|
|
wire _T_21507 = bht_rd_addr_hashed_f == 8'h32; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_50; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21969 = _T_21507 ? bht_bank_rd_data_out_1_50 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22224 = _T_22223 | _T_21969; // @[Mux.scala 27:72]
|
|
wire _T_21509 = bht_rd_addr_hashed_f == 8'h33; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_51; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21970 = _T_21509 ? bht_bank_rd_data_out_1_51 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22225 = _T_22224 | _T_21970; // @[Mux.scala 27:72]
|
|
wire _T_21511 = bht_rd_addr_hashed_f == 8'h34; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_52; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21971 = _T_21511 ? bht_bank_rd_data_out_1_52 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22226 = _T_22225 | _T_21971; // @[Mux.scala 27:72]
|
|
wire _T_21513 = bht_rd_addr_hashed_f == 8'h35; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_53; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21972 = _T_21513 ? bht_bank_rd_data_out_1_53 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22227 = _T_22226 | _T_21972; // @[Mux.scala 27:72]
|
|
wire _T_21515 = bht_rd_addr_hashed_f == 8'h36; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_54; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21973 = _T_21515 ? bht_bank_rd_data_out_1_54 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22228 = _T_22227 | _T_21973; // @[Mux.scala 27:72]
|
|
wire _T_21517 = bht_rd_addr_hashed_f == 8'h37; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_55; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21974 = _T_21517 ? bht_bank_rd_data_out_1_55 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22229 = _T_22228 | _T_21974; // @[Mux.scala 27:72]
|
|
wire _T_21519 = bht_rd_addr_hashed_f == 8'h38; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_56; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21975 = _T_21519 ? bht_bank_rd_data_out_1_56 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22230 = _T_22229 | _T_21975; // @[Mux.scala 27:72]
|
|
wire _T_21521 = bht_rd_addr_hashed_f == 8'h39; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_57; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21976 = _T_21521 ? bht_bank_rd_data_out_1_57 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22231 = _T_22230 | _T_21976; // @[Mux.scala 27:72]
|
|
wire _T_21523 = bht_rd_addr_hashed_f == 8'h3a; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_58; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21977 = _T_21523 ? bht_bank_rd_data_out_1_58 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22232 = _T_22231 | _T_21977; // @[Mux.scala 27:72]
|
|
wire _T_21525 = bht_rd_addr_hashed_f == 8'h3b; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_59; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21978 = _T_21525 ? bht_bank_rd_data_out_1_59 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22233 = _T_22232 | _T_21978; // @[Mux.scala 27:72]
|
|
wire _T_21527 = bht_rd_addr_hashed_f == 8'h3c; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_60; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21979 = _T_21527 ? bht_bank_rd_data_out_1_60 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22234 = _T_22233 | _T_21979; // @[Mux.scala 27:72]
|
|
wire _T_21529 = bht_rd_addr_hashed_f == 8'h3d; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_61; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21980 = _T_21529 ? bht_bank_rd_data_out_1_61 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22235 = _T_22234 | _T_21980; // @[Mux.scala 27:72]
|
|
wire _T_21531 = bht_rd_addr_hashed_f == 8'h3e; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_62; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21981 = _T_21531 ? bht_bank_rd_data_out_1_62 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22236 = _T_22235 | _T_21981; // @[Mux.scala 27:72]
|
|
wire _T_21533 = bht_rd_addr_hashed_f == 8'h3f; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_63; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21982 = _T_21533 ? bht_bank_rd_data_out_1_63 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22237 = _T_22236 | _T_21982; // @[Mux.scala 27:72]
|
|
wire _T_21535 = bht_rd_addr_hashed_f == 8'h40; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_64; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21983 = _T_21535 ? bht_bank_rd_data_out_1_64 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22238 = _T_22237 | _T_21983; // @[Mux.scala 27:72]
|
|
wire _T_21537 = bht_rd_addr_hashed_f == 8'h41; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_65; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21984 = _T_21537 ? bht_bank_rd_data_out_1_65 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22239 = _T_22238 | _T_21984; // @[Mux.scala 27:72]
|
|
wire _T_21539 = bht_rd_addr_hashed_f == 8'h42; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_66; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21985 = _T_21539 ? bht_bank_rd_data_out_1_66 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22240 = _T_22239 | _T_21985; // @[Mux.scala 27:72]
|
|
wire _T_21541 = bht_rd_addr_hashed_f == 8'h43; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_67; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21986 = _T_21541 ? bht_bank_rd_data_out_1_67 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22241 = _T_22240 | _T_21986; // @[Mux.scala 27:72]
|
|
wire _T_21543 = bht_rd_addr_hashed_f == 8'h44; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_68; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21987 = _T_21543 ? bht_bank_rd_data_out_1_68 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22242 = _T_22241 | _T_21987; // @[Mux.scala 27:72]
|
|
wire _T_21545 = bht_rd_addr_hashed_f == 8'h45; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_69; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21988 = _T_21545 ? bht_bank_rd_data_out_1_69 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22243 = _T_22242 | _T_21988; // @[Mux.scala 27:72]
|
|
wire _T_21547 = bht_rd_addr_hashed_f == 8'h46; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_70; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21989 = _T_21547 ? bht_bank_rd_data_out_1_70 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22244 = _T_22243 | _T_21989; // @[Mux.scala 27:72]
|
|
wire _T_21549 = bht_rd_addr_hashed_f == 8'h47; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_71; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21990 = _T_21549 ? bht_bank_rd_data_out_1_71 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22245 = _T_22244 | _T_21990; // @[Mux.scala 27:72]
|
|
wire _T_21551 = bht_rd_addr_hashed_f == 8'h48; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_72; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21991 = _T_21551 ? bht_bank_rd_data_out_1_72 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22246 = _T_22245 | _T_21991; // @[Mux.scala 27:72]
|
|
wire _T_21553 = bht_rd_addr_hashed_f == 8'h49; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_73; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21992 = _T_21553 ? bht_bank_rd_data_out_1_73 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22247 = _T_22246 | _T_21992; // @[Mux.scala 27:72]
|
|
wire _T_21555 = bht_rd_addr_hashed_f == 8'h4a; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_74; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21993 = _T_21555 ? bht_bank_rd_data_out_1_74 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22248 = _T_22247 | _T_21993; // @[Mux.scala 27:72]
|
|
wire _T_21557 = bht_rd_addr_hashed_f == 8'h4b; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_75; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21994 = _T_21557 ? bht_bank_rd_data_out_1_75 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22249 = _T_22248 | _T_21994; // @[Mux.scala 27:72]
|
|
wire _T_21559 = bht_rd_addr_hashed_f == 8'h4c; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_76; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21995 = _T_21559 ? bht_bank_rd_data_out_1_76 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22250 = _T_22249 | _T_21995; // @[Mux.scala 27:72]
|
|
wire _T_21561 = bht_rd_addr_hashed_f == 8'h4d; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_77; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21996 = _T_21561 ? bht_bank_rd_data_out_1_77 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22251 = _T_22250 | _T_21996; // @[Mux.scala 27:72]
|
|
wire _T_21563 = bht_rd_addr_hashed_f == 8'h4e; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_78; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21997 = _T_21563 ? bht_bank_rd_data_out_1_78 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22252 = _T_22251 | _T_21997; // @[Mux.scala 27:72]
|
|
wire _T_21565 = bht_rd_addr_hashed_f == 8'h4f; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_79; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21998 = _T_21565 ? bht_bank_rd_data_out_1_79 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22253 = _T_22252 | _T_21998; // @[Mux.scala 27:72]
|
|
wire _T_21567 = bht_rd_addr_hashed_f == 8'h50; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_80; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_21999 = _T_21567 ? bht_bank_rd_data_out_1_80 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22254 = _T_22253 | _T_21999; // @[Mux.scala 27:72]
|
|
wire _T_21569 = bht_rd_addr_hashed_f == 8'h51; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_81; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22000 = _T_21569 ? bht_bank_rd_data_out_1_81 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22255 = _T_22254 | _T_22000; // @[Mux.scala 27:72]
|
|
wire _T_21571 = bht_rd_addr_hashed_f == 8'h52; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_82; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22001 = _T_21571 ? bht_bank_rd_data_out_1_82 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22256 = _T_22255 | _T_22001; // @[Mux.scala 27:72]
|
|
wire _T_21573 = bht_rd_addr_hashed_f == 8'h53; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_83; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22002 = _T_21573 ? bht_bank_rd_data_out_1_83 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22257 = _T_22256 | _T_22002; // @[Mux.scala 27:72]
|
|
wire _T_21575 = bht_rd_addr_hashed_f == 8'h54; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_84; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22003 = _T_21575 ? bht_bank_rd_data_out_1_84 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22258 = _T_22257 | _T_22003; // @[Mux.scala 27:72]
|
|
wire _T_21577 = bht_rd_addr_hashed_f == 8'h55; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_85; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22004 = _T_21577 ? bht_bank_rd_data_out_1_85 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22259 = _T_22258 | _T_22004; // @[Mux.scala 27:72]
|
|
wire _T_21579 = bht_rd_addr_hashed_f == 8'h56; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_86; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22005 = _T_21579 ? bht_bank_rd_data_out_1_86 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22260 = _T_22259 | _T_22005; // @[Mux.scala 27:72]
|
|
wire _T_21581 = bht_rd_addr_hashed_f == 8'h57; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_87; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22006 = _T_21581 ? bht_bank_rd_data_out_1_87 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22261 = _T_22260 | _T_22006; // @[Mux.scala 27:72]
|
|
wire _T_21583 = bht_rd_addr_hashed_f == 8'h58; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_88; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22007 = _T_21583 ? bht_bank_rd_data_out_1_88 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22262 = _T_22261 | _T_22007; // @[Mux.scala 27:72]
|
|
wire _T_21585 = bht_rd_addr_hashed_f == 8'h59; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_89; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22008 = _T_21585 ? bht_bank_rd_data_out_1_89 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22263 = _T_22262 | _T_22008; // @[Mux.scala 27:72]
|
|
wire _T_21587 = bht_rd_addr_hashed_f == 8'h5a; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_90; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22009 = _T_21587 ? bht_bank_rd_data_out_1_90 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22264 = _T_22263 | _T_22009; // @[Mux.scala 27:72]
|
|
wire _T_21589 = bht_rd_addr_hashed_f == 8'h5b; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_91; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22010 = _T_21589 ? bht_bank_rd_data_out_1_91 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22265 = _T_22264 | _T_22010; // @[Mux.scala 27:72]
|
|
wire _T_21591 = bht_rd_addr_hashed_f == 8'h5c; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_92; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22011 = _T_21591 ? bht_bank_rd_data_out_1_92 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22266 = _T_22265 | _T_22011; // @[Mux.scala 27:72]
|
|
wire _T_21593 = bht_rd_addr_hashed_f == 8'h5d; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_93; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22012 = _T_21593 ? bht_bank_rd_data_out_1_93 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22267 = _T_22266 | _T_22012; // @[Mux.scala 27:72]
|
|
wire _T_21595 = bht_rd_addr_hashed_f == 8'h5e; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_94; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22013 = _T_21595 ? bht_bank_rd_data_out_1_94 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22268 = _T_22267 | _T_22013; // @[Mux.scala 27:72]
|
|
wire _T_21597 = bht_rd_addr_hashed_f == 8'h5f; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_95; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22014 = _T_21597 ? bht_bank_rd_data_out_1_95 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22269 = _T_22268 | _T_22014; // @[Mux.scala 27:72]
|
|
wire _T_21599 = bht_rd_addr_hashed_f == 8'h60; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_96; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22015 = _T_21599 ? bht_bank_rd_data_out_1_96 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22270 = _T_22269 | _T_22015; // @[Mux.scala 27:72]
|
|
wire _T_21601 = bht_rd_addr_hashed_f == 8'h61; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_97; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22016 = _T_21601 ? bht_bank_rd_data_out_1_97 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22271 = _T_22270 | _T_22016; // @[Mux.scala 27:72]
|
|
wire _T_21603 = bht_rd_addr_hashed_f == 8'h62; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_98; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22017 = _T_21603 ? bht_bank_rd_data_out_1_98 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22272 = _T_22271 | _T_22017; // @[Mux.scala 27:72]
|
|
wire _T_21605 = bht_rd_addr_hashed_f == 8'h63; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_99; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22018 = _T_21605 ? bht_bank_rd_data_out_1_99 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22273 = _T_22272 | _T_22018; // @[Mux.scala 27:72]
|
|
wire _T_21607 = bht_rd_addr_hashed_f == 8'h64; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_100; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22019 = _T_21607 ? bht_bank_rd_data_out_1_100 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22274 = _T_22273 | _T_22019; // @[Mux.scala 27:72]
|
|
wire _T_21609 = bht_rd_addr_hashed_f == 8'h65; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_101; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22020 = _T_21609 ? bht_bank_rd_data_out_1_101 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22275 = _T_22274 | _T_22020; // @[Mux.scala 27:72]
|
|
wire _T_21611 = bht_rd_addr_hashed_f == 8'h66; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_102; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22021 = _T_21611 ? bht_bank_rd_data_out_1_102 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22276 = _T_22275 | _T_22021; // @[Mux.scala 27:72]
|
|
wire _T_21613 = bht_rd_addr_hashed_f == 8'h67; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_103; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22022 = _T_21613 ? bht_bank_rd_data_out_1_103 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22277 = _T_22276 | _T_22022; // @[Mux.scala 27:72]
|
|
wire _T_21615 = bht_rd_addr_hashed_f == 8'h68; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_104; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22023 = _T_21615 ? bht_bank_rd_data_out_1_104 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22278 = _T_22277 | _T_22023; // @[Mux.scala 27:72]
|
|
wire _T_21617 = bht_rd_addr_hashed_f == 8'h69; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_105; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22024 = _T_21617 ? bht_bank_rd_data_out_1_105 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22279 = _T_22278 | _T_22024; // @[Mux.scala 27:72]
|
|
wire _T_21619 = bht_rd_addr_hashed_f == 8'h6a; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_106; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22025 = _T_21619 ? bht_bank_rd_data_out_1_106 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22280 = _T_22279 | _T_22025; // @[Mux.scala 27:72]
|
|
wire _T_21621 = bht_rd_addr_hashed_f == 8'h6b; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_107; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22026 = _T_21621 ? bht_bank_rd_data_out_1_107 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22281 = _T_22280 | _T_22026; // @[Mux.scala 27:72]
|
|
wire _T_21623 = bht_rd_addr_hashed_f == 8'h6c; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_108; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22027 = _T_21623 ? bht_bank_rd_data_out_1_108 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22282 = _T_22281 | _T_22027; // @[Mux.scala 27:72]
|
|
wire _T_21625 = bht_rd_addr_hashed_f == 8'h6d; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_109; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22028 = _T_21625 ? bht_bank_rd_data_out_1_109 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22283 = _T_22282 | _T_22028; // @[Mux.scala 27:72]
|
|
wire _T_21627 = bht_rd_addr_hashed_f == 8'h6e; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_110; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22029 = _T_21627 ? bht_bank_rd_data_out_1_110 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22284 = _T_22283 | _T_22029; // @[Mux.scala 27:72]
|
|
wire _T_21629 = bht_rd_addr_hashed_f == 8'h6f; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_111; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22030 = _T_21629 ? bht_bank_rd_data_out_1_111 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22285 = _T_22284 | _T_22030; // @[Mux.scala 27:72]
|
|
wire _T_21631 = bht_rd_addr_hashed_f == 8'h70; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_112; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22031 = _T_21631 ? bht_bank_rd_data_out_1_112 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22286 = _T_22285 | _T_22031; // @[Mux.scala 27:72]
|
|
wire _T_21633 = bht_rd_addr_hashed_f == 8'h71; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_113; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22032 = _T_21633 ? bht_bank_rd_data_out_1_113 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22287 = _T_22286 | _T_22032; // @[Mux.scala 27:72]
|
|
wire _T_21635 = bht_rd_addr_hashed_f == 8'h72; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_114; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22033 = _T_21635 ? bht_bank_rd_data_out_1_114 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22288 = _T_22287 | _T_22033; // @[Mux.scala 27:72]
|
|
wire _T_21637 = bht_rd_addr_hashed_f == 8'h73; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_115; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22034 = _T_21637 ? bht_bank_rd_data_out_1_115 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22289 = _T_22288 | _T_22034; // @[Mux.scala 27:72]
|
|
wire _T_21639 = bht_rd_addr_hashed_f == 8'h74; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_116; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22035 = _T_21639 ? bht_bank_rd_data_out_1_116 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22290 = _T_22289 | _T_22035; // @[Mux.scala 27:72]
|
|
wire _T_21641 = bht_rd_addr_hashed_f == 8'h75; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_117; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22036 = _T_21641 ? bht_bank_rd_data_out_1_117 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22291 = _T_22290 | _T_22036; // @[Mux.scala 27:72]
|
|
wire _T_21643 = bht_rd_addr_hashed_f == 8'h76; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_118; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22037 = _T_21643 ? bht_bank_rd_data_out_1_118 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22292 = _T_22291 | _T_22037; // @[Mux.scala 27:72]
|
|
wire _T_21645 = bht_rd_addr_hashed_f == 8'h77; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_119; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22038 = _T_21645 ? bht_bank_rd_data_out_1_119 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22293 = _T_22292 | _T_22038; // @[Mux.scala 27:72]
|
|
wire _T_21647 = bht_rd_addr_hashed_f == 8'h78; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_120; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22039 = _T_21647 ? bht_bank_rd_data_out_1_120 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22294 = _T_22293 | _T_22039; // @[Mux.scala 27:72]
|
|
wire _T_21649 = bht_rd_addr_hashed_f == 8'h79; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_121; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22040 = _T_21649 ? bht_bank_rd_data_out_1_121 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22295 = _T_22294 | _T_22040; // @[Mux.scala 27:72]
|
|
wire _T_21651 = bht_rd_addr_hashed_f == 8'h7a; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_122; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22041 = _T_21651 ? bht_bank_rd_data_out_1_122 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22296 = _T_22295 | _T_22041; // @[Mux.scala 27:72]
|
|
wire _T_21653 = bht_rd_addr_hashed_f == 8'h7b; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_123; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22042 = _T_21653 ? bht_bank_rd_data_out_1_123 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22297 = _T_22296 | _T_22042; // @[Mux.scala 27:72]
|
|
wire _T_21655 = bht_rd_addr_hashed_f == 8'h7c; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_124; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22043 = _T_21655 ? bht_bank_rd_data_out_1_124 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22298 = _T_22297 | _T_22043; // @[Mux.scala 27:72]
|
|
wire _T_21657 = bht_rd_addr_hashed_f == 8'h7d; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_125; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22044 = _T_21657 ? bht_bank_rd_data_out_1_125 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22299 = _T_22298 | _T_22044; // @[Mux.scala 27:72]
|
|
wire _T_21659 = bht_rd_addr_hashed_f == 8'h7e; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_126; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22045 = _T_21659 ? bht_bank_rd_data_out_1_126 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22300 = _T_22299 | _T_22045; // @[Mux.scala 27:72]
|
|
wire _T_21661 = bht_rd_addr_hashed_f == 8'h7f; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_127; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22046 = _T_21661 ? bht_bank_rd_data_out_1_127 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22301 = _T_22300 | _T_22046; // @[Mux.scala 27:72]
|
|
wire _T_21663 = bht_rd_addr_hashed_f == 8'h80; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_128; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22047 = _T_21663 ? bht_bank_rd_data_out_1_128 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22302 = _T_22301 | _T_22047; // @[Mux.scala 27:72]
|
|
wire _T_21665 = bht_rd_addr_hashed_f == 8'h81; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_129; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22048 = _T_21665 ? bht_bank_rd_data_out_1_129 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22303 = _T_22302 | _T_22048; // @[Mux.scala 27:72]
|
|
wire _T_21667 = bht_rd_addr_hashed_f == 8'h82; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_130; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22049 = _T_21667 ? bht_bank_rd_data_out_1_130 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22304 = _T_22303 | _T_22049; // @[Mux.scala 27:72]
|
|
wire _T_21669 = bht_rd_addr_hashed_f == 8'h83; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_131; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22050 = _T_21669 ? bht_bank_rd_data_out_1_131 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22305 = _T_22304 | _T_22050; // @[Mux.scala 27:72]
|
|
wire _T_21671 = bht_rd_addr_hashed_f == 8'h84; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_132; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22051 = _T_21671 ? bht_bank_rd_data_out_1_132 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22306 = _T_22305 | _T_22051; // @[Mux.scala 27:72]
|
|
wire _T_21673 = bht_rd_addr_hashed_f == 8'h85; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_133; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22052 = _T_21673 ? bht_bank_rd_data_out_1_133 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22307 = _T_22306 | _T_22052; // @[Mux.scala 27:72]
|
|
wire _T_21675 = bht_rd_addr_hashed_f == 8'h86; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_134; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22053 = _T_21675 ? bht_bank_rd_data_out_1_134 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22308 = _T_22307 | _T_22053; // @[Mux.scala 27:72]
|
|
wire _T_21677 = bht_rd_addr_hashed_f == 8'h87; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_135; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22054 = _T_21677 ? bht_bank_rd_data_out_1_135 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22309 = _T_22308 | _T_22054; // @[Mux.scala 27:72]
|
|
wire _T_21679 = bht_rd_addr_hashed_f == 8'h88; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_136; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22055 = _T_21679 ? bht_bank_rd_data_out_1_136 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22310 = _T_22309 | _T_22055; // @[Mux.scala 27:72]
|
|
wire _T_21681 = bht_rd_addr_hashed_f == 8'h89; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_137; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22056 = _T_21681 ? bht_bank_rd_data_out_1_137 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22311 = _T_22310 | _T_22056; // @[Mux.scala 27:72]
|
|
wire _T_21683 = bht_rd_addr_hashed_f == 8'h8a; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_138; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22057 = _T_21683 ? bht_bank_rd_data_out_1_138 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22312 = _T_22311 | _T_22057; // @[Mux.scala 27:72]
|
|
wire _T_21685 = bht_rd_addr_hashed_f == 8'h8b; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_139; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22058 = _T_21685 ? bht_bank_rd_data_out_1_139 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22313 = _T_22312 | _T_22058; // @[Mux.scala 27:72]
|
|
wire _T_21687 = bht_rd_addr_hashed_f == 8'h8c; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_140; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22059 = _T_21687 ? bht_bank_rd_data_out_1_140 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22314 = _T_22313 | _T_22059; // @[Mux.scala 27:72]
|
|
wire _T_21689 = bht_rd_addr_hashed_f == 8'h8d; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_141; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22060 = _T_21689 ? bht_bank_rd_data_out_1_141 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22315 = _T_22314 | _T_22060; // @[Mux.scala 27:72]
|
|
wire _T_21691 = bht_rd_addr_hashed_f == 8'h8e; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_142; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22061 = _T_21691 ? bht_bank_rd_data_out_1_142 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22316 = _T_22315 | _T_22061; // @[Mux.scala 27:72]
|
|
wire _T_21693 = bht_rd_addr_hashed_f == 8'h8f; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_143; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22062 = _T_21693 ? bht_bank_rd_data_out_1_143 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22317 = _T_22316 | _T_22062; // @[Mux.scala 27:72]
|
|
wire _T_21695 = bht_rd_addr_hashed_f == 8'h90; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_144; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22063 = _T_21695 ? bht_bank_rd_data_out_1_144 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22318 = _T_22317 | _T_22063; // @[Mux.scala 27:72]
|
|
wire _T_21697 = bht_rd_addr_hashed_f == 8'h91; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_145; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22064 = _T_21697 ? bht_bank_rd_data_out_1_145 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22319 = _T_22318 | _T_22064; // @[Mux.scala 27:72]
|
|
wire _T_21699 = bht_rd_addr_hashed_f == 8'h92; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_146; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22065 = _T_21699 ? bht_bank_rd_data_out_1_146 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22320 = _T_22319 | _T_22065; // @[Mux.scala 27:72]
|
|
wire _T_21701 = bht_rd_addr_hashed_f == 8'h93; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_147; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22066 = _T_21701 ? bht_bank_rd_data_out_1_147 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22321 = _T_22320 | _T_22066; // @[Mux.scala 27:72]
|
|
wire _T_21703 = bht_rd_addr_hashed_f == 8'h94; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_148; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22067 = _T_21703 ? bht_bank_rd_data_out_1_148 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22322 = _T_22321 | _T_22067; // @[Mux.scala 27:72]
|
|
wire _T_21705 = bht_rd_addr_hashed_f == 8'h95; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_149; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22068 = _T_21705 ? bht_bank_rd_data_out_1_149 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22323 = _T_22322 | _T_22068; // @[Mux.scala 27:72]
|
|
wire _T_21707 = bht_rd_addr_hashed_f == 8'h96; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_150; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22069 = _T_21707 ? bht_bank_rd_data_out_1_150 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22324 = _T_22323 | _T_22069; // @[Mux.scala 27:72]
|
|
wire _T_21709 = bht_rd_addr_hashed_f == 8'h97; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_151; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22070 = _T_21709 ? bht_bank_rd_data_out_1_151 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22325 = _T_22324 | _T_22070; // @[Mux.scala 27:72]
|
|
wire _T_21711 = bht_rd_addr_hashed_f == 8'h98; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_152; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22071 = _T_21711 ? bht_bank_rd_data_out_1_152 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22326 = _T_22325 | _T_22071; // @[Mux.scala 27:72]
|
|
wire _T_21713 = bht_rd_addr_hashed_f == 8'h99; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_153; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22072 = _T_21713 ? bht_bank_rd_data_out_1_153 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22327 = _T_22326 | _T_22072; // @[Mux.scala 27:72]
|
|
wire _T_21715 = bht_rd_addr_hashed_f == 8'h9a; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_154; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22073 = _T_21715 ? bht_bank_rd_data_out_1_154 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22328 = _T_22327 | _T_22073; // @[Mux.scala 27:72]
|
|
wire _T_21717 = bht_rd_addr_hashed_f == 8'h9b; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_155; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22074 = _T_21717 ? bht_bank_rd_data_out_1_155 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22329 = _T_22328 | _T_22074; // @[Mux.scala 27:72]
|
|
wire _T_21719 = bht_rd_addr_hashed_f == 8'h9c; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_156; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22075 = _T_21719 ? bht_bank_rd_data_out_1_156 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22330 = _T_22329 | _T_22075; // @[Mux.scala 27:72]
|
|
wire _T_21721 = bht_rd_addr_hashed_f == 8'h9d; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_157; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22076 = _T_21721 ? bht_bank_rd_data_out_1_157 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22331 = _T_22330 | _T_22076; // @[Mux.scala 27:72]
|
|
wire _T_21723 = bht_rd_addr_hashed_f == 8'h9e; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_158; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22077 = _T_21723 ? bht_bank_rd_data_out_1_158 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22332 = _T_22331 | _T_22077; // @[Mux.scala 27:72]
|
|
wire _T_21725 = bht_rd_addr_hashed_f == 8'h9f; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_159; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22078 = _T_21725 ? bht_bank_rd_data_out_1_159 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22333 = _T_22332 | _T_22078; // @[Mux.scala 27:72]
|
|
wire _T_21727 = bht_rd_addr_hashed_f == 8'ha0; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_160; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22079 = _T_21727 ? bht_bank_rd_data_out_1_160 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22334 = _T_22333 | _T_22079; // @[Mux.scala 27:72]
|
|
wire _T_21729 = bht_rd_addr_hashed_f == 8'ha1; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_161; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22080 = _T_21729 ? bht_bank_rd_data_out_1_161 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22335 = _T_22334 | _T_22080; // @[Mux.scala 27:72]
|
|
wire _T_21731 = bht_rd_addr_hashed_f == 8'ha2; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_162; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22081 = _T_21731 ? bht_bank_rd_data_out_1_162 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22336 = _T_22335 | _T_22081; // @[Mux.scala 27:72]
|
|
wire _T_21733 = bht_rd_addr_hashed_f == 8'ha3; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_163; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22082 = _T_21733 ? bht_bank_rd_data_out_1_163 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22337 = _T_22336 | _T_22082; // @[Mux.scala 27:72]
|
|
wire _T_21735 = bht_rd_addr_hashed_f == 8'ha4; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_164; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22083 = _T_21735 ? bht_bank_rd_data_out_1_164 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22338 = _T_22337 | _T_22083; // @[Mux.scala 27:72]
|
|
wire _T_21737 = bht_rd_addr_hashed_f == 8'ha5; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_165; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22084 = _T_21737 ? bht_bank_rd_data_out_1_165 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22339 = _T_22338 | _T_22084; // @[Mux.scala 27:72]
|
|
wire _T_21739 = bht_rd_addr_hashed_f == 8'ha6; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_166; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22085 = _T_21739 ? bht_bank_rd_data_out_1_166 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22340 = _T_22339 | _T_22085; // @[Mux.scala 27:72]
|
|
wire _T_21741 = bht_rd_addr_hashed_f == 8'ha7; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_167; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22086 = _T_21741 ? bht_bank_rd_data_out_1_167 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22341 = _T_22340 | _T_22086; // @[Mux.scala 27:72]
|
|
wire _T_21743 = bht_rd_addr_hashed_f == 8'ha8; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_168; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22087 = _T_21743 ? bht_bank_rd_data_out_1_168 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22342 = _T_22341 | _T_22087; // @[Mux.scala 27:72]
|
|
wire _T_21745 = bht_rd_addr_hashed_f == 8'ha9; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_169; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22088 = _T_21745 ? bht_bank_rd_data_out_1_169 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22343 = _T_22342 | _T_22088; // @[Mux.scala 27:72]
|
|
wire _T_21747 = bht_rd_addr_hashed_f == 8'haa; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_170; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22089 = _T_21747 ? bht_bank_rd_data_out_1_170 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22344 = _T_22343 | _T_22089; // @[Mux.scala 27:72]
|
|
wire _T_21749 = bht_rd_addr_hashed_f == 8'hab; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_171; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22090 = _T_21749 ? bht_bank_rd_data_out_1_171 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22345 = _T_22344 | _T_22090; // @[Mux.scala 27:72]
|
|
wire _T_21751 = bht_rd_addr_hashed_f == 8'hac; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_172; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22091 = _T_21751 ? bht_bank_rd_data_out_1_172 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22346 = _T_22345 | _T_22091; // @[Mux.scala 27:72]
|
|
wire _T_21753 = bht_rd_addr_hashed_f == 8'had; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_173; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22092 = _T_21753 ? bht_bank_rd_data_out_1_173 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22347 = _T_22346 | _T_22092; // @[Mux.scala 27:72]
|
|
wire _T_21755 = bht_rd_addr_hashed_f == 8'hae; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_174; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22093 = _T_21755 ? bht_bank_rd_data_out_1_174 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22348 = _T_22347 | _T_22093; // @[Mux.scala 27:72]
|
|
wire _T_21757 = bht_rd_addr_hashed_f == 8'haf; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_175; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22094 = _T_21757 ? bht_bank_rd_data_out_1_175 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22349 = _T_22348 | _T_22094; // @[Mux.scala 27:72]
|
|
wire _T_21759 = bht_rd_addr_hashed_f == 8'hb0; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_176; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22095 = _T_21759 ? bht_bank_rd_data_out_1_176 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22350 = _T_22349 | _T_22095; // @[Mux.scala 27:72]
|
|
wire _T_21761 = bht_rd_addr_hashed_f == 8'hb1; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_177; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22096 = _T_21761 ? bht_bank_rd_data_out_1_177 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22351 = _T_22350 | _T_22096; // @[Mux.scala 27:72]
|
|
wire _T_21763 = bht_rd_addr_hashed_f == 8'hb2; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_178; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22097 = _T_21763 ? bht_bank_rd_data_out_1_178 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22352 = _T_22351 | _T_22097; // @[Mux.scala 27:72]
|
|
wire _T_21765 = bht_rd_addr_hashed_f == 8'hb3; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_179; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22098 = _T_21765 ? bht_bank_rd_data_out_1_179 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22353 = _T_22352 | _T_22098; // @[Mux.scala 27:72]
|
|
wire _T_21767 = bht_rd_addr_hashed_f == 8'hb4; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_180; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22099 = _T_21767 ? bht_bank_rd_data_out_1_180 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22354 = _T_22353 | _T_22099; // @[Mux.scala 27:72]
|
|
wire _T_21769 = bht_rd_addr_hashed_f == 8'hb5; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_181; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22100 = _T_21769 ? bht_bank_rd_data_out_1_181 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22355 = _T_22354 | _T_22100; // @[Mux.scala 27:72]
|
|
wire _T_21771 = bht_rd_addr_hashed_f == 8'hb6; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_182; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22101 = _T_21771 ? bht_bank_rd_data_out_1_182 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22356 = _T_22355 | _T_22101; // @[Mux.scala 27:72]
|
|
wire _T_21773 = bht_rd_addr_hashed_f == 8'hb7; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_183; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22102 = _T_21773 ? bht_bank_rd_data_out_1_183 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22357 = _T_22356 | _T_22102; // @[Mux.scala 27:72]
|
|
wire _T_21775 = bht_rd_addr_hashed_f == 8'hb8; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_184; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22103 = _T_21775 ? bht_bank_rd_data_out_1_184 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22358 = _T_22357 | _T_22103; // @[Mux.scala 27:72]
|
|
wire _T_21777 = bht_rd_addr_hashed_f == 8'hb9; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_185; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22104 = _T_21777 ? bht_bank_rd_data_out_1_185 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22359 = _T_22358 | _T_22104; // @[Mux.scala 27:72]
|
|
wire _T_21779 = bht_rd_addr_hashed_f == 8'hba; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_186; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22105 = _T_21779 ? bht_bank_rd_data_out_1_186 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22360 = _T_22359 | _T_22105; // @[Mux.scala 27:72]
|
|
wire _T_21781 = bht_rd_addr_hashed_f == 8'hbb; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_187; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22106 = _T_21781 ? bht_bank_rd_data_out_1_187 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22361 = _T_22360 | _T_22106; // @[Mux.scala 27:72]
|
|
wire _T_21783 = bht_rd_addr_hashed_f == 8'hbc; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_188; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22107 = _T_21783 ? bht_bank_rd_data_out_1_188 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22362 = _T_22361 | _T_22107; // @[Mux.scala 27:72]
|
|
wire _T_21785 = bht_rd_addr_hashed_f == 8'hbd; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_189; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22108 = _T_21785 ? bht_bank_rd_data_out_1_189 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22363 = _T_22362 | _T_22108; // @[Mux.scala 27:72]
|
|
wire _T_21787 = bht_rd_addr_hashed_f == 8'hbe; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_190; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22109 = _T_21787 ? bht_bank_rd_data_out_1_190 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22364 = _T_22363 | _T_22109; // @[Mux.scala 27:72]
|
|
wire _T_21789 = bht_rd_addr_hashed_f == 8'hbf; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_191; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22110 = _T_21789 ? bht_bank_rd_data_out_1_191 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22365 = _T_22364 | _T_22110; // @[Mux.scala 27:72]
|
|
wire _T_21791 = bht_rd_addr_hashed_f == 8'hc0; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_192; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22111 = _T_21791 ? bht_bank_rd_data_out_1_192 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22366 = _T_22365 | _T_22111; // @[Mux.scala 27:72]
|
|
wire _T_21793 = bht_rd_addr_hashed_f == 8'hc1; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_193; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22112 = _T_21793 ? bht_bank_rd_data_out_1_193 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22367 = _T_22366 | _T_22112; // @[Mux.scala 27:72]
|
|
wire _T_21795 = bht_rd_addr_hashed_f == 8'hc2; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_194; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22113 = _T_21795 ? bht_bank_rd_data_out_1_194 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22368 = _T_22367 | _T_22113; // @[Mux.scala 27:72]
|
|
wire _T_21797 = bht_rd_addr_hashed_f == 8'hc3; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_195; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22114 = _T_21797 ? bht_bank_rd_data_out_1_195 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22369 = _T_22368 | _T_22114; // @[Mux.scala 27:72]
|
|
wire _T_21799 = bht_rd_addr_hashed_f == 8'hc4; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_196; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22115 = _T_21799 ? bht_bank_rd_data_out_1_196 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22370 = _T_22369 | _T_22115; // @[Mux.scala 27:72]
|
|
wire _T_21801 = bht_rd_addr_hashed_f == 8'hc5; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_197; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22116 = _T_21801 ? bht_bank_rd_data_out_1_197 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22371 = _T_22370 | _T_22116; // @[Mux.scala 27:72]
|
|
wire _T_21803 = bht_rd_addr_hashed_f == 8'hc6; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_198; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22117 = _T_21803 ? bht_bank_rd_data_out_1_198 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22372 = _T_22371 | _T_22117; // @[Mux.scala 27:72]
|
|
wire _T_21805 = bht_rd_addr_hashed_f == 8'hc7; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_199; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22118 = _T_21805 ? bht_bank_rd_data_out_1_199 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22373 = _T_22372 | _T_22118; // @[Mux.scala 27:72]
|
|
wire _T_21807 = bht_rd_addr_hashed_f == 8'hc8; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_200; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22119 = _T_21807 ? bht_bank_rd_data_out_1_200 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22374 = _T_22373 | _T_22119; // @[Mux.scala 27:72]
|
|
wire _T_21809 = bht_rd_addr_hashed_f == 8'hc9; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_201; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22120 = _T_21809 ? bht_bank_rd_data_out_1_201 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22375 = _T_22374 | _T_22120; // @[Mux.scala 27:72]
|
|
wire _T_21811 = bht_rd_addr_hashed_f == 8'hca; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_202; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22121 = _T_21811 ? bht_bank_rd_data_out_1_202 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22376 = _T_22375 | _T_22121; // @[Mux.scala 27:72]
|
|
wire _T_21813 = bht_rd_addr_hashed_f == 8'hcb; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_203; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22122 = _T_21813 ? bht_bank_rd_data_out_1_203 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22377 = _T_22376 | _T_22122; // @[Mux.scala 27:72]
|
|
wire _T_21815 = bht_rd_addr_hashed_f == 8'hcc; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_204; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22123 = _T_21815 ? bht_bank_rd_data_out_1_204 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22378 = _T_22377 | _T_22123; // @[Mux.scala 27:72]
|
|
wire _T_21817 = bht_rd_addr_hashed_f == 8'hcd; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_205; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22124 = _T_21817 ? bht_bank_rd_data_out_1_205 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22379 = _T_22378 | _T_22124; // @[Mux.scala 27:72]
|
|
wire _T_21819 = bht_rd_addr_hashed_f == 8'hce; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_206; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22125 = _T_21819 ? bht_bank_rd_data_out_1_206 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22380 = _T_22379 | _T_22125; // @[Mux.scala 27:72]
|
|
wire _T_21821 = bht_rd_addr_hashed_f == 8'hcf; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_207; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22126 = _T_21821 ? bht_bank_rd_data_out_1_207 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22381 = _T_22380 | _T_22126; // @[Mux.scala 27:72]
|
|
wire _T_21823 = bht_rd_addr_hashed_f == 8'hd0; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_208; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22127 = _T_21823 ? bht_bank_rd_data_out_1_208 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22382 = _T_22381 | _T_22127; // @[Mux.scala 27:72]
|
|
wire _T_21825 = bht_rd_addr_hashed_f == 8'hd1; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_209; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22128 = _T_21825 ? bht_bank_rd_data_out_1_209 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22383 = _T_22382 | _T_22128; // @[Mux.scala 27:72]
|
|
wire _T_21827 = bht_rd_addr_hashed_f == 8'hd2; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_210; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22129 = _T_21827 ? bht_bank_rd_data_out_1_210 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22384 = _T_22383 | _T_22129; // @[Mux.scala 27:72]
|
|
wire _T_21829 = bht_rd_addr_hashed_f == 8'hd3; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_211; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22130 = _T_21829 ? bht_bank_rd_data_out_1_211 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22385 = _T_22384 | _T_22130; // @[Mux.scala 27:72]
|
|
wire _T_21831 = bht_rd_addr_hashed_f == 8'hd4; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_212; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22131 = _T_21831 ? bht_bank_rd_data_out_1_212 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22386 = _T_22385 | _T_22131; // @[Mux.scala 27:72]
|
|
wire _T_21833 = bht_rd_addr_hashed_f == 8'hd5; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_213; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22132 = _T_21833 ? bht_bank_rd_data_out_1_213 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22387 = _T_22386 | _T_22132; // @[Mux.scala 27:72]
|
|
wire _T_21835 = bht_rd_addr_hashed_f == 8'hd6; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_214; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22133 = _T_21835 ? bht_bank_rd_data_out_1_214 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22388 = _T_22387 | _T_22133; // @[Mux.scala 27:72]
|
|
wire _T_21837 = bht_rd_addr_hashed_f == 8'hd7; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_215; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22134 = _T_21837 ? bht_bank_rd_data_out_1_215 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22389 = _T_22388 | _T_22134; // @[Mux.scala 27:72]
|
|
wire _T_21839 = bht_rd_addr_hashed_f == 8'hd8; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_216; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22135 = _T_21839 ? bht_bank_rd_data_out_1_216 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22390 = _T_22389 | _T_22135; // @[Mux.scala 27:72]
|
|
wire _T_21841 = bht_rd_addr_hashed_f == 8'hd9; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_217; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22136 = _T_21841 ? bht_bank_rd_data_out_1_217 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22391 = _T_22390 | _T_22136; // @[Mux.scala 27:72]
|
|
wire _T_21843 = bht_rd_addr_hashed_f == 8'hda; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_218; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22137 = _T_21843 ? bht_bank_rd_data_out_1_218 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22392 = _T_22391 | _T_22137; // @[Mux.scala 27:72]
|
|
wire _T_21845 = bht_rd_addr_hashed_f == 8'hdb; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_219; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22138 = _T_21845 ? bht_bank_rd_data_out_1_219 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22393 = _T_22392 | _T_22138; // @[Mux.scala 27:72]
|
|
wire _T_21847 = bht_rd_addr_hashed_f == 8'hdc; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_220; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22139 = _T_21847 ? bht_bank_rd_data_out_1_220 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22394 = _T_22393 | _T_22139; // @[Mux.scala 27:72]
|
|
wire _T_21849 = bht_rd_addr_hashed_f == 8'hdd; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_221; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22140 = _T_21849 ? bht_bank_rd_data_out_1_221 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22395 = _T_22394 | _T_22140; // @[Mux.scala 27:72]
|
|
wire _T_21851 = bht_rd_addr_hashed_f == 8'hde; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_222; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22141 = _T_21851 ? bht_bank_rd_data_out_1_222 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22396 = _T_22395 | _T_22141; // @[Mux.scala 27:72]
|
|
wire _T_21853 = bht_rd_addr_hashed_f == 8'hdf; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_223; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22142 = _T_21853 ? bht_bank_rd_data_out_1_223 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22397 = _T_22396 | _T_22142; // @[Mux.scala 27:72]
|
|
wire _T_21855 = bht_rd_addr_hashed_f == 8'he0; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_224; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22143 = _T_21855 ? bht_bank_rd_data_out_1_224 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22398 = _T_22397 | _T_22143; // @[Mux.scala 27:72]
|
|
wire _T_21857 = bht_rd_addr_hashed_f == 8'he1; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_225; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22144 = _T_21857 ? bht_bank_rd_data_out_1_225 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22399 = _T_22398 | _T_22144; // @[Mux.scala 27:72]
|
|
wire _T_21859 = bht_rd_addr_hashed_f == 8'he2; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_226; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22145 = _T_21859 ? bht_bank_rd_data_out_1_226 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22400 = _T_22399 | _T_22145; // @[Mux.scala 27:72]
|
|
wire _T_21861 = bht_rd_addr_hashed_f == 8'he3; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_227; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22146 = _T_21861 ? bht_bank_rd_data_out_1_227 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22401 = _T_22400 | _T_22146; // @[Mux.scala 27:72]
|
|
wire _T_21863 = bht_rd_addr_hashed_f == 8'he4; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_228; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22147 = _T_21863 ? bht_bank_rd_data_out_1_228 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22402 = _T_22401 | _T_22147; // @[Mux.scala 27:72]
|
|
wire _T_21865 = bht_rd_addr_hashed_f == 8'he5; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_229; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22148 = _T_21865 ? bht_bank_rd_data_out_1_229 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22403 = _T_22402 | _T_22148; // @[Mux.scala 27:72]
|
|
wire _T_21867 = bht_rd_addr_hashed_f == 8'he6; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_230; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22149 = _T_21867 ? bht_bank_rd_data_out_1_230 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22404 = _T_22403 | _T_22149; // @[Mux.scala 27:72]
|
|
wire _T_21869 = bht_rd_addr_hashed_f == 8'he7; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_231; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22150 = _T_21869 ? bht_bank_rd_data_out_1_231 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22405 = _T_22404 | _T_22150; // @[Mux.scala 27:72]
|
|
wire _T_21871 = bht_rd_addr_hashed_f == 8'he8; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_232; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22151 = _T_21871 ? bht_bank_rd_data_out_1_232 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22406 = _T_22405 | _T_22151; // @[Mux.scala 27:72]
|
|
wire _T_21873 = bht_rd_addr_hashed_f == 8'he9; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_233; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22152 = _T_21873 ? bht_bank_rd_data_out_1_233 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22407 = _T_22406 | _T_22152; // @[Mux.scala 27:72]
|
|
wire _T_21875 = bht_rd_addr_hashed_f == 8'hea; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_234; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22153 = _T_21875 ? bht_bank_rd_data_out_1_234 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22408 = _T_22407 | _T_22153; // @[Mux.scala 27:72]
|
|
wire _T_21877 = bht_rd_addr_hashed_f == 8'heb; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_235; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22154 = _T_21877 ? bht_bank_rd_data_out_1_235 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22409 = _T_22408 | _T_22154; // @[Mux.scala 27:72]
|
|
wire _T_21879 = bht_rd_addr_hashed_f == 8'hec; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_236; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22155 = _T_21879 ? bht_bank_rd_data_out_1_236 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22410 = _T_22409 | _T_22155; // @[Mux.scala 27:72]
|
|
wire _T_21881 = bht_rd_addr_hashed_f == 8'hed; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_237; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22156 = _T_21881 ? bht_bank_rd_data_out_1_237 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22411 = _T_22410 | _T_22156; // @[Mux.scala 27:72]
|
|
wire _T_21883 = bht_rd_addr_hashed_f == 8'hee; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_238; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22157 = _T_21883 ? bht_bank_rd_data_out_1_238 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22412 = _T_22411 | _T_22157; // @[Mux.scala 27:72]
|
|
wire _T_21885 = bht_rd_addr_hashed_f == 8'hef; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_239; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22158 = _T_21885 ? bht_bank_rd_data_out_1_239 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22413 = _T_22412 | _T_22158; // @[Mux.scala 27:72]
|
|
wire _T_21887 = bht_rd_addr_hashed_f == 8'hf0; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_240; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22159 = _T_21887 ? bht_bank_rd_data_out_1_240 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22414 = _T_22413 | _T_22159; // @[Mux.scala 27:72]
|
|
wire _T_21889 = bht_rd_addr_hashed_f == 8'hf1; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_241; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22160 = _T_21889 ? bht_bank_rd_data_out_1_241 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22415 = _T_22414 | _T_22160; // @[Mux.scala 27:72]
|
|
wire _T_21891 = bht_rd_addr_hashed_f == 8'hf2; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_242; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22161 = _T_21891 ? bht_bank_rd_data_out_1_242 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22416 = _T_22415 | _T_22161; // @[Mux.scala 27:72]
|
|
wire _T_21893 = bht_rd_addr_hashed_f == 8'hf3; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_243; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22162 = _T_21893 ? bht_bank_rd_data_out_1_243 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22417 = _T_22416 | _T_22162; // @[Mux.scala 27:72]
|
|
wire _T_21895 = bht_rd_addr_hashed_f == 8'hf4; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_244; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22163 = _T_21895 ? bht_bank_rd_data_out_1_244 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22418 = _T_22417 | _T_22163; // @[Mux.scala 27:72]
|
|
wire _T_21897 = bht_rd_addr_hashed_f == 8'hf5; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_245; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22164 = _T_21897 ? bht_bank_rd_data_out_1_245 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22419 = _T_22418 | _T_22164; // @[Mux.scala 27:72]
|
|
wire _T_21899 = bht_rd_addr_hashed_f == 8'hf6; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_246; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22165 = _T_21899 ? bht_bank_rd_data_out_1_246 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22420 = _T_22419 | _T_22165; // @[Mux.scala 27:72]
|
|
wire _T_21901 = bht_rd_addr_hashed_f == 8'hf7; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_247; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22166 = _T_21901 ? bht_bank_rd_data_out_1_247 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22421 = _T_22420 | _T_22166; // @[Mux.scala 27:72]
|
|
wire _T_21903 = bht_rd_addr_hashed_f == 8'hf8; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_248; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22167 = _T_21903 ? bht_bank_rd_data_out_1_248 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22422 = _T_22421 | _T_22167; // @[Mux.scala 27:72]
|
|
wire _T_21905 = bht_rd_addr_hashed_f == 8'hf9; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_249; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22168 = _T_21905 ? bht_bank_rd_data_out_1_249 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22423 = _T_22422 | _T_22168; // @[Mux.scala 27:72]
|
|
wire _T_21907 = bht_rd_addr_hashed_f == 8'hfa; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_250; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22169 = _T_21907 ? bht_bank_rd_data_out_1_250 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22424 = _T_22423 | _T_22169; // @[Mux.scala 27:72]
|
|
wire _T_21909 = bht_rd_addr_hashed_f == 8'hfb; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_251; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22170 = _T_21909 ? bht_bank_rd_data_out_1_251 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22425 = _T_22424 | _T_22170; // @[Mux.scala 27:72]
|
|
wire _T_21911 = bht_rd_addr_hashed_f == 8'hfc; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_252; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22171 = _T_21911 ? bht_bank_rd_data_out_1_252 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22426 = _T_22425 | _T_22171; // @[Mux.scala 27:72]
|
|
wire _T_21913 = bht_rd_addr_hashed_f == 8'hfd; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_253; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22172 = _T_21913 ? bht_bank_rd_data_out_1_253 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22427 = _T_22426 | _T_22172; // @[Mux.scala 27:72]
|
|
wire _T_21915 = bht_rd_addr_hashed_f == 8'hfe; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_254; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22173 = _T_21915 ? bht_bank_rd_data_out_1_254 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22428 = _T_22427 | _T_22173; // @[Mux.scala 27:72]
|
|
wire _T_21917 = bht_rd_addr_hashed_f == 8'hff; // @[el2_ifu_bp_ctl.scala 467:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_255; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22174 = _T_21917 ? bht_bank_rd_data_out_1_255 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] bht_bank1_rd_data_f = _T_22428 | _T_22174; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_259 = _T_143 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72]
|
|
wire [9:0] _T_572 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] bht_rd_addr_hashed_p1_f = _T_572[9:2] ^ fghr; // @[el2_lib.scala 196:35]
|
|
wire _T_22431 = bht_rd_addr_hashed_p1_f == 8'h0; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_0; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22943 = _T_22431 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72]
|
|
wire _T_22433 = bht_rd_addr_hashed_p1_f == 8'h1; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_1; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22944 = _T_22433 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23199 = _T_22943 | _T_22944; // @[Mux.scala 27:72]
|
|
wire _T_22435 = bht_rd_addr_hashed_p1_f == 8'h2; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_2; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22945 = _T_22435 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23200 = _T_23199 | _T_22945; // @[Mux.scala 27:72]
|
|
wire _T_22437 = bht_rd_addr_hashed_p1_f == 8'h3; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_3; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22946 = _T_22437 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23201 = _T_23200 | _T_22946; // @[Mux.scala 27:72]
|
|
wire _T_22439 = bht_rd_addr_hashed_p1_f == 8'h4; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_4; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22947 = _T_22439 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23202 = _T_23201 | _T_22947; // @[Mux.scala 27:72]
|
|
wire _T_22441 = bht_rd_addr_hashed_p1_f == 8'h5; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_5; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22948 = _T_22441 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23203 = _T_23202 | _T_22948; // @[Mux.scala 27:72]
|
|
wire _T_22443 = bht_rd_addr_hashed_p1_f == 8'h6; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_6; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22949 = _T_22443 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23204 = _T_23203 | _T_22949; // @[Mux.scala 27:72]
|
|
wire _T_22445 = bht_rd_addr_hashed_p1_f == 8'h7; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_7; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22950 = _T_22445 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23205 = _T_23204 | _T_22950; // @[Mux.scala 27:72]
|
|
wire _T_22447 = bht_rd_addr_hashed_p1_f == 8'h8; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_8; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22951 = _T_22447 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23206 = _T_23205 | _T_22951; // @[Mux.scala 27:72]
|
|
wire _T_22449 = bht_rd_addr_hashed_p1_f == 8'h9; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_9; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22952 = _T_22449 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23207 = _T_23206 | _T_22952; // @[Mux.scala 27:72]
|
|
wire _T_22451 = bht_rd_addr_hashed_p1_f == 8'ha; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_10; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22953 = _T_22451 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23208 = _T_23207 | _T_22953; // @[Mux.scala 27:72]
|
|
wire _T_22453 = bht_rd_addr_hashed_p1_f == 8'hb; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_11; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22954 = _T_22453 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23209 = _T_23208 | _T_22954; // @[Mux.scala 27:72]
|
|
wire _T_22455 = bht_rd_addr_hashed_p1_f == 8'hc; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_12; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22955 = _T_22455 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23210 = _T_23209 | _T_22955; // @[Mux.scala 27:72]
|
|
wire _T_22457 = bht_rd_addr_hashed_p1_f == 8'hd; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_13; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22956 = _T_22457 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23211 = _T_23210 | _T_22956; // @[Mux.scala 27:72]
|
|
wire _T_22459 = bht_rd_addr_hashed_p1_f == 8'he; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_14; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22957 = _T_22459 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23212 = _T_23211 | _T_22957; // @[Mux.scala 27:72]
|
|
wire _T_22461 = bht_rd_addr_hashed_p1_f == 8'hf; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_15; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22958 = _T_22461 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23213 = _T_23212 | _T_22958; // @[Mux.scala 27:72]
|
|
wire _T_22463 = bht_rd_addr_hashed_p1_f == 8'h10; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_16; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22959 = _T_22463 ? bht_bank_rd_data_out_0_16 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23214 = _T_23213 | _T_22959; // @[Mux.scala 27:72]
|
|
wire _T_22465 = bht_rd_addr_hashed_p1_f == 8'h11; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_17; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22960 = _T_22465 ? bht_bank_rd_data_out_0_17 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23215 = _T_23214 | _T_22960; // @[Mux.scala 27:72]
|
|
wire _T_22467 = bht_rd_addr_hashed_p1_f == 8'h12; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_18; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22961 = _T_22467 ? bht_bank_rd_data_out_0_18 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23216 = _T_23215 | _T_22961; // @[Mux.scala 27:72]
|
|
wire _T_22469 = bht_rd_addr_hashed_p1_f == 8'h13; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_19; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22962 = _T_22469 ? bht_bank_rd_data_out_0_19 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23217 = _T_23216 | _T_22962; // @[Mux.scala 27:72]
|
|
wire _T_22471 = bht_rd_addr_hashed_p1_f == 8'h14; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_20; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22963 = _T_22471 ? bht_bank_rd_data_out_0_20 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23218 = _T_23217 | _T_22963; // @[Mux.scala 27:72]
|
|
wire _T_22473 = bht_rd_addr_hashed_p1_f == 8'h15; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_21; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22964 = _T_22473 ? bht_bank_rd_data_out_0_21 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23219 = _T_23218 | _T_22964; // @[Mux.scala 27:72]
|
|
wire _T_22475 = bht_rd_addr_hashed_p1_f == 8'h16; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_22; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22965 = _T_22475 ? bht_bank_rd_data_out_0_22 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23220 = _T_23219 | _T_22965; // @[Mux.scala 27:72]
|
|
wire _T_22477 = bht_rd_addr_hashed_p1_f == 8'h17; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_23; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22966 = _T_22477 ? bht_bank_rd_data_out_0_23 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23221 = _T_23220 | _T_22966; // @[Mux.scala 27:72]
|
|
wire _T_22479 = bht_rd_addr_hashed_p1_f == 8'h18; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_24; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22967 = _T_22479 ? bht_bank_rd_data_out_0_24 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23222 = _T_23221 | _T_22967; // @[Mux.scala 27:72]
|
|
wire _T_22481 = bht_rd_addr_hashed_p1_f == 8'h19; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_25; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22968 = _T_22481 ? bht_bank_rd_data_out_0_25 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23223 = _T_23222 | _T_22968; // @[Mux.scala 27:72]
|
|
wire _T_22483 = bht_rd_addr_hashed_p1_f == 8'h1a; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_26; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22969 = _T_22483 ? bht_bank_rd_data_out_0_26 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23224 = _T_23223 | _T_22969; // @[Mux.scala 27:72]
|
|
wire _T_22485 = bht_rd_addr_hashed_p1_f == 8'h1b; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_27; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22970 = _T_22485 ? bht_bank_rd_data_out_0_27 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23225 = _T_23224 | _T_22970; // @[Mux.scala 27:72]
|
|
wire _T_22487 = bht_rd_addr_hashed_p1_f == 8'h1c; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_28; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22971 = _T_22487 ? bht_bank_rd_data_out_0_28 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23226 = _T_23225 | _T_22971; // @[Mux.scala 27:72]
|
|
wire _T_22489 = bht_rd_addr_hashed_p1_f == 8'h1d; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_29; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22972 = _T_22489 ? bht_bank_rd_data_out_0_29 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23227 = _T_23226 | _T_22972; // @[Mux.scala 27:72]
|
|
wire _T_22491 = bht_rd_addr_hashed_p1_f == 8'h1e; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_30; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22973 = _T_22491 ? bht_bank_rd_data_out_0_30 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23228 = _T_23227 | _T_22973; // @[Mux.scala 27:72]
|
|
wire _T_22493 = bht_rd_addr_hashed_p1_f == 8'h1f; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_31; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22974 = _T_22493 ? bht_bank_rd_data_out_0_31 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23229 = _T_23228 | _T_22974; // @[Mux.scala 27:72]
|
|
wire _T_22495 = bht_rd_addr_hashed_p1_f == 8'h20; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_32; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22975 = _T_22495 ? bht_bank_rd_data_out_0_32 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23230 = _T_23229 | _T_22975; // @[Mux.scala 27:72]
|
|
wire _T_22497 = bht_rd_addr_hashed_p1_f == 8'h21; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_33; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22976 = _T_22497 ? bht_bank_rd_data_out_0_33 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23231 = _T_23230 | _T_22976; // @[Mux.scala 27:72]
|
|
wire _T_22499 = bht_rd_addr_hashed_p1_f == 8'h22; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_34; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22977 = _T_22499 ? bht_bank_rd_data_out_0_34 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23232 = _T_23231 | _T_22977; // @[Mux.scala 27:72]
|
|
wire _T_22501 = bht_rd_addr_hashed_p1_f == 8'h23; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_35; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22978 = _T_22501 ? bht_bank_rd_data_out_0_35 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23233 = _T_23232 | _T_22978; // @[Mux.scala 27:72]
|
|
wire _T_22503 = bht_rd_addr_hashed_p1_f == 8'h24; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_36; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22979 = _T_22503 ? bht_bank_rd_data_out_0_36 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23234 = _T_23233 | _T_22979; // @[Mux.scala 27:72]
|
|
wire _T_22505 = bht_rd_addr_hashed_p1_f == 8'h25; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_37; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22980 = _T_22505 ? bht_bank_rd_data_out_0_37 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23235 = _T_23234 | _T_22980; // @[Mux.scala 27:72]
|
|
wire _T_22507 = bht_rd_addr_hashed_p1_f == 8'h26; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_38; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22981 = _T_22507 ? bht_bank_rd_data_out_0_38 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23236 = _T_23235 | _T_22981; // @[Mux.scala 27:72]
|
|
wire _T_22509 = bht_rd_addr_hashed_p1_f == 8'h27; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_39; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22982 = _T_22509 ? bht_bank_rd_data_out_0_39 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23237 = _T_23236 | _T_22982; // @[Mux.scala 27:72]
|
|
wire _T_22511 = bht_rd_addr_hashed_p1_f == 8'h28; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_40; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22983 = _T_22511 ? bht_bank_rd_data_out_0_40 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23238 = _T_23237 | _T_22983; // @[Mux.scala 27:72]
|
|
wire _T_22513 = bht_rd_addr_hashed_p1_f == 8'h29; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_41; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22984 = _T_22513 ? bht_bank_rd_data_out_0_41 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23239 = _T_23238 | _T_22984; // @[Mux.scala 27:72]
|
|
wire _T_22515 = bht_rd_addr_hashed_p1_f == 8'h2a; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_42; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22985 = _T_22515 ? bht_bank_rd_data_out_0_42 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23240 = _T_23239 | _T_22985; // @[Mux.scala 27:72]
|
|
wire _T_22517 = bht_rd_addr_hashed_p1_f == 8'h2b; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_43; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22986 = _T_22517 ? bht_bank_rd_data_out_0_43 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23241 = _T_23240 | _T_22986; // @[Mux.scala 27:72]
|
|
wire _T_22519 = bht_rd_addr_hashed_p1_f == 8'h2c; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_44; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22987 = _T_22519 ? bht_bank_rd_data_out_0_44 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23242 = _T_23241 | _T_22987; // @[Mux.scala 27:72]
|
|
wire _T_22521 = bht_rd_addr_hashed_p1_f == 8'h2d; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_45; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22988 = _T_22521 ? bht_bank_rd_data_out_0_45 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23243 = _T_23242 | _T_22988; // @[Mux.scala 27:72]
|
|
wire _T_22523 = bht_rd_addr_hashed_p1_f == 8'h2e; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_46; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22989 = _T_22523 ? bht_bank_rd_data_out_0_46 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23244 = _T_23243 | _T_22989; // @[Mux.scala 27:72]
|
|
wire _T_22525 = bht_rd_addr_hashed_p1_f == 8'h2f; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_47; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22990 = _T_22525 ? bht_bank_rd_data_out_0_47 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23245 = _T_23244 | _T_22990; // @[Mux.scala 27:72]
|
|
wire _T_22527 = bht_rd_addr_hashed_p1_f == 8'h30; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_48; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22991 = _T_22527 ? bht_bank_rd_data_out_0_48 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23246 = _T_23245 | _T_22991; // @[Mux.scala 27:72]
|
|
wire _T_22529 = bht_rd_addr_hashed_p1_f == 8'h31; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_49; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22992 = _T_22529 ? bht_bank_rd_data_out_0_49 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23247 = _T_23246 | _T_22992; // @[Mux.scala 27:72]
|
|
wire _T_22531 = bht_rd_addr_hashed_p1_f == 8'h32; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_50; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22993 = _T_22531 ? bht_bank_rd_data_out_0_50 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23248 = _T_23247 | _T_22993; // @[Mux.scala 27:72]
|
|
wire _T_22533 = bht_rd_addr_hashed_p1_f == 8'h33; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_51; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22994 = _T_22533 ? bht_bank_rd_data_out_0_51 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23249 = _T_23248 | _T_22994; // @[Mux.scala 27:72]
|
|
wire _T_22535 = bht_rd_addr_hashed_p1_f == 8'h34; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_52; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22995 = _T_22535 ? bht_bank_rd_data_out_0_52 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23250 = _T_23249 | _T_22995; // @[Mux.scala 27:72]
|
|
wire _T_22537 = bht_rd_addr_hashed_p1_f == 8'h35; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_53; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22996 = _T_22537 ? bht_bank_rd_data_out_0_53 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23251 = _T_23250 | _T_22996; // @[Mux.scala 27:72]
|
|
wire _T_22539 = bht_rd_addr_hashed_p1_f == 8'h36; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_54; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22997 = _T_22539 ? bht_bank_rd_data_out_0_54 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23252 = _T_23251 | _T_22997; // @[Mux.scala 27:72]
|
|
wire _T_22541 = bht_rd_addr_hashed_p1_f == 8'h37; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_55; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22998 = _T_22541 ? bht_bank_rd_data_out_0_55 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23253 = _T_23252 | _T_22998; // @[Mux.scala 27:72]
|
|
wire _T_22543 = bht_rd_addr_hashed_p1_f == 8'h38; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_56; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_22999 = _T_22543 ? bht_bank_rd_data_out_0_56 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23254 = _T_23253 | _T_22999; // @[Mux.scala 27:72]
|
|
wire _T_22545 = bht_rd_addr_hashed_p1_f == 8'h39; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_57; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23000 = _T_22545 ? bht_bank_rd_data_out_0_57 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23255 = _T_23254 | _T_23000; // @[Mux.scala 27:72]
|
|
wire _T_22547 = bht_rd_addr_hashed_p1_f == 8'h3a; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_58; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23001 = _T_22547 ? bht_bank_rd_data_out_0_58 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23256 = _T_23255 | _T_23001; // @[Mux.scala 27:72]
|
|
wire _T_22549 = bht_rd_addr_hashed_p1_f == 8'h3b; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_59; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23002 = _T_22549 ? bht_bank_rd_data_out_0_59 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23257 = _T_23256 | _T_23002; // @[Mux.scala 27:72]
|
|
wire _T_22551 = bht_rd_addr_hashed_p1_f == 8'h3c; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_60; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23003 = _T_22551 ? bht_bank_rd_data_out_0_60 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23258 = _T_23257 | _T_23003; // @[Mux.scala 27:72]
|
|
wire _T_22553 = bht_rd_addr_hashed_p1_f == 8'h3d; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_61; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23004 = _T_22553 ? bht_bank_rd_data_out_0_61 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23259 = _T_23258 | _T_23004; // @[Mux.scala 27:72]
|
|
wire _T_22555 = bht_rd_addr_hashed_p1_f == 8'h3e; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_62; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23005 = _T_22555 ? bht_bank_rd_data_out_0_62 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23260 = _T_23259 | _T_23005; // @[Mux.scala 27:72]
|
|
wire _T_22557 = bht_rd_addr_hashed_p1_f == 8'h3f; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_63; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23006 = _T_22557 ? bht_bank_rd_data_out_0_63 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23261 = _T_23260 | _T_23006; // @[Mux.scala 27:72]
|
|
wire _T_22559 = bht_rd_addr_hashed_p1_f == 8'h40; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_64; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23007 = _T_22559 ? bht_bank_rd_data_out_0_64 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23262 = _T_23261 | _T_23007; // @[Mux.scala 27:72]
|
|
wire _T_22561 = bht_rd_addr_hashed_p1_f == 8'h41; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_65; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23008 = _T_22561 ? bht_bank_rd_data_out_0_65 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23263 = _T_23262 | _T_23008; // @[Mux.scala 27:72]
|
|
wire _T_22563 = bht_rd_addr_hashed_p1_f == 8'h42; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_66; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23009 = _T_22563 ? bht_bank_rd_data_out_0_66 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23264 = _T_23263 | _T_23009; // @[Mux.scala 27:72]
|
|
wire _T_22565 = bht_rd_addr_hashed_p1_f == 8'h43; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_67; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23010 = _T_22565 ? bht_bank_rd_data_out_0_67 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23265 = _T_23264 | _T_23010; // @[Mux.scala 27:72]
|
|
wire _T_22567 = bht_rd_addr_hashed_p1_f == 8'h44; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_68; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23011 = _T_22567 ? bht_bank_rd_data_out_0_68 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23266 = _T_23265 | _T_23011; // @[Mux.scala 27:72]
|
|
wire _T_22569 = bht_rd_addr_hashed_p1_f == 8'h45; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_69; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23012 = _T_22569 ? bht_bank_rd_data_out_0_69 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23267 = _T_23266 | _T_23012; // @[Mux.scala 27:72]
|
|
wire _T_22571 = bht_rd_addr_hashed_p1_f == 8'h46; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_70; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23013 = _T_22571 ? bht_bank_rd_data_out_0_70 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23268 = _T_23267 | _T_23013; // @[Mux.scala 27:72]
|
|
wire _T_22573 = bht_rd_addr_hashed_p1_f == 8'h47; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_71; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23014 = _T_22573 ? bht_bank_rd_data_out_0_71 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23269 = _T_23268 | _T_23014; // @[Mux.scala 27:72]
|
|
wire _T_22575 = bht_rd_addr_hashed_p1_f == 8'h48; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_72; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23015 = _T_22575 ? bht_bank_rd_data_out_0_72 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23270 = _T_23269 | _T_23015; // @[Mux.scala 27:72]
|
|
wire _T_22577 = bht_rd_addr_hashed_p1_f == 8'h49; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_73; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23016 = _T_22577 ? bht_bank_rd_data_out_0_73 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23271 = _T_23270 | _T_23016; // @[Mux.scala 27:72]
|
|
wire _T_22579 = bht_rd_addr_hashed_p1_f == 8'h4a; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_74; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23017 = _T_22579 ? bht_bank_rd_data_out_0_74 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23272 = _T_23271 | _T_23017; // @[Mux.scala 27:72]
|
|
wire _T_22581 = bht_rd_addr_hashed_p1_f == 8'h4b; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_75; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23018 = _T_22581 ? bht_bank_rd_data_out_0_75 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23273 = _T_23272 | _T_23018; // @[Mux.scala 27:72]
|
|
wire _T_22583 = bht_rd_addr_hashed_p1_f == 8'h4c; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_76; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23019 = _T_22583 ? bht_bank_rd_data_out_0_76 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23274 = _T_23273 | _T_23019; // @[Mux.scala 27:72]
|
|
wire _T_22585 = bht_rd_addr_hashed_p1_f == 8'h4d; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_77; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23020 = _T_22585 ? bht_bank_rd_data_out_0_77 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23275 = _T_23274 | _T_23020; // @[Mux.scala 27:72]
|
|
wire _T_22587 = bht_rd_addr_hashed_p1_f == 8'h4e; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_78; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23021 = _T_22587 ? bht_bank_rd_data_out_0_78 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23276 = _T_23275 | _T_23021; // @[Mux.scala 27:72]
|
|
wire _T_22589 = bht_rd_addr_hashed_p1_f == 8'h4f; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_79; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23022 = _T_22589 ? bht_bank_rd_data_out_0_79 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23277 = _T_23276 | _T_23022; // @[Mux.scala 27:72]
|
|
wire _T_22591 = bht_rd_addr_hashed_p1_f == 8'h50; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_80; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23023 = _T_22591 ? bht_bank_rd_data_out_0_80 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23278 = _T_23277 | _T_23023; // @[Mux.scala 27:72]
|
|
wire _T_22593 = bht_rd_addr_hashed_p1_f == 8'h51; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_81; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23024 = _T_22593 ? bht_bank_rd_data_out_0_81 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23279 = _T_23278 | _T_23024; // @[Mux.scala 27:72]
|
|
wire _T_22595 = bht_rd_addr_hashed_p1_f == 8'h52; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_82; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23025 = _T_22595 ? bht_bank_rd_data_out_0_82 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23280 = _T_23279 | _T_23025; // @[Mux.scala 27:72]
|
|
wire _T_22597 = bht_rd_addr_hashed_p1_f == 8'h53; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_83; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23026 = _T_22597 ? bht_bank_rd_data_out_0_83 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23281 = _T_23280 | _T_23026; // @[Mux.scala 27:72]
|
|
wire _T_22599 = bht_rd_addr_hashed_p1_f == 8'h54; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_84; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23027 = _T_22599 ? bht_bank_rd_data_out_0_84 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23282 = _T_23281 | _T_23027; // @[Mux.scala 27:72]
|
|
wire _T_22601 = bht_rd_addr_hashed_p1_f == 8'h55; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_85; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23028 = _T_22601 ? bht_bank_rd_data_out_0_85 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23283 = _T_23282 | _T_23028; // @[Mux.scala 27:72]
|
|
wire _T_22603 = bht_rd_addr_hashed_p1_f == 8'h56; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_86; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23029 = _T_22603 ? bht_bank_rd_data_out_0_86 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23284 = _T_23283 | _T_23029; // @[Mux.scala 27:72]
|
|
wire _T_22605 = bht_rd_addr_hashed_p1_f == 8'h57; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_87; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23030 = _T_22605 ? bht_bank_rd_data_out_0_87 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23285 = _T_23284 | _T_23030; // @[Mux.scala 27:72]
|
|
wire _T_22607 = bht_rd_addr_hashed_p1_f == 8'h58; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_88; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23031 = _T_22607 ? bht_bank_rd_data_out_0_88 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23286 = _T_23285 | _T_23031; // @[Mux.scala 27:72]
|
|
wire _T_22609 = bht_rd_addr_hashed_p1_f == 8'h59; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_89; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23032 = _T_22609 ? bht_bank_rd_data_out_0_89 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23287 = _T_23286 | _T_23032; // @[Mux.scala 27:72]
|
|
wire _T_22611 = bht_rd_addr_hashed_p1_f == 8'h5a; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_90; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23033 = _T_22611 ? bht_bank_rd_data_out_0_90 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23288 = _T_23287 | _T_23033; // @[Mux.scala 27:72]
|
|
wire _T_22613 = bht_rd_addr_hashed_p1_f == 8'h5b; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_91; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23034 = _T_22613 ? bht_bank_rd_data_out_0_91 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23289 = _T_23288 | _T_23034; // @[Mux.scala 27:72]
|
|
wire _T_22615 = bht_rd_addr_hashed_p1_f == 8'h5c; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_92; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23035 = _T_22615 ? bht_bank_rd_data_out_0_92 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23290 = _T_23289 | _T_23035; // @[Mux.scala 27:72]
|
|
wire _T_22617 = bht_rd_addr_hashed_p1_f == 8'h5d; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_93; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23036 = _T_22617 ? bht_bank_rd_data_out_0_93 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23291 = _T_23290 | _T_23036; // @[Mux.scala 27:72]
|
|
wire _T_22619 = bht_rd_addr_hashed_p1_f == 8'h5e; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_94; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23037 = _T_22619 ? bht_bank_rd_data_out_0_94 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23292 = _T_23291 | _T_23037; // @[Mux.scala 27:72]
|
|
wire _T_22621 = bht_rd_addr_hashed_p1_f == 8'h5f; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_95; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23038 = _T_22621 ? bht_bank_rd_data_out_0_95 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23293 = _T_23292 | _T_23038; // @[Mux.scala 27:72]
|
|
wire _T_22623 = bht_rd_addr_hashed_p1_f == 8'h60; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_96; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23039 = _T_22623 ? bht_bank_rd_data_out_0_96 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23294 = _T_23293 | _T_23039; // @[Mux.scala 27:72]
|
|
wire _T_22625 = bht_rd_addr_hashed_p1_f == 8'h61; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_97; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23040 = _T_22625 ? bht_bank_rd_data_out_0_97 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23295 = _T_23294 | _T_23040; // @[Mux.scala 27:72]
|
|
wire _T_22627 = bht_rd_addr_hashed_p1_f == 8'h62; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_98; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23041 = _T_22627 ? bht_bank_rd_data_out_0_98 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23296 = _T_23295 | _T_23041; // @[Mux.scala 27:72]
|
|
wire _T_22629 = bht_rd_addr_hashed_p1_f == 8'h63; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_99; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23042 = _T_22629 ? bht_bank_rd_data_out_0_99 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23297 = _T_23296 | _T_23042; // @[Mux.scala 27:72]
|
|
wire _T_22631 = bht_rd_addr_hashed_p1_f == 8'h64; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_100; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23043 = _T_22631 ? bht_bank_rd_data_out_0_100 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23298 = _T_23297 | _T_23043; // @[Mux.scala 27:72]
|
|
wire _T_22633 = bht_rd_addr_hashed_p1_f == 8'h65; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_101; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23044 = _T_22633 ? bht_bank_rd_data_out_0_101 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23299 = _T_23298 | _T_23044; // @[Mux.scala 27:72]
|
|
wire _T_22635 = bht_rd_addr_hashed_p1_f == 8'h66; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_102; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23045 = _T_22635 ? bht_bank_rd_data_out_0_102 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23300 = _T_23299 | _T_23045; // @[Mux.scala 27:72]
|
|
wire _T_22637 = bht_rd_addr_hashed_p1_f == 8'h67; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_103; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23046 = _T_22637 ? bht_bank_rd_data_out_0_103 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23301 = _T_23300 | _T_23046; // @[Mux.scala 27:72]
|
|
wire _T_22639 = bht_rd_addr_hashed_p1_f == 8'h68; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_104; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23047 = _T_22639 ? bht_bank_rd_data_out_0_104 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23302 = _T_23301 | _T_23047; // @[Mux.scala 27:72]
|
|
wire _T_22641 = bht_rd_addr_hashed_p1_f == 8'h69; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_105; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23048 = _T_22641 ? bht_bank_rd_data_out_0_105 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23303 = _T_23302 | _T_23048; // @[Mux.scala 27:72]
|
|
wire _T_22643 = bht_rd_addr_hashed_p1_f == 8'h6a; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_106; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23049 = _T_22643 ? bht_bank_rd_data_out_0_106 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23304 = _T_23303 | _T_23049; // @[Mux.scala 27:72]
|
|
wire _T_22645 = bht_rd_addr_hashed_p1_f == 8'h6b; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_107; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23050 = _T_22645 ? bht_bank_rd_data_out_0_107 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23305 = _T_23304 | _T_23050; // @[Mux.scala 27:72]
|
|
wire _T_22647 = bht_rd_addr_hashed_p1_f == 8'h6c; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_108; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23051 = _T_22647 ? bht_bank_rd_data_out_0_108 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23306 = _T_23305 | _T_23051; // @[Mux.scala 27:72]
|
|
wire _T_22649 = bht_rd_addr_hashed_p1_f == 8'h6d; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_109; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23052 = _T_22649 ? bht_bank_rd_data_out_0_109 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23307 = _T_23306 | _T_23052; // @[Mux.scala 27:72]
|
|
wire _T_22651 = bht_rd_addr_hashed_p1_f == 8'h6e; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_110; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23053 = _T_22651 ? bht_bank_rd_data_out_0_110 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23308 = _T_23307 | _T_23053; // @[Mux.scala 27:72]
|
|
wire _T_22653 = bht_rd_addr_hashed_p1_f == 8'h6f; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_111; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23054 = _T_22653 ? bht_bank_rd_data_out_0_111 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23309 = _T_23308 | _T_23054; // @[Mux.scala 27:72]
|
|
wire _T_22655 = bht_rd_addr_hashed_p1_f == 8'h70; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_112; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23055 = _T_22655 ? bht_bank_rd_data_out_0_112 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23310 = _T_23309 | _T_23055; // @[Mux.scala 27:72]
|
|
wire _T_22657 = bht_rd_addr_hashed_p1_f == 8'h71; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_113; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23056 = _T_22657 ? bht_bank_rd_data_out_0_113 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23311 = _T_23310 | _T_23056; // @[Mux.scala 27:72]
|
|
wire _T_22659 = bht_rd_addr_hashed_p1_f == 8'h72; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_114; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23057 = _T_22659 ? bht_bank_rd_data_out_0_114 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23312 = _T_23311 | _T_23057; // @[Mux.scala 27:72]
|
|
wire _T_22661 = bht_rd_addr_hashed_p1_f == 8'h73; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_115; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23058 = _T_22661 ? bht_bank_rd_data_out_0_115 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23313 = _T_23312 | _T_23058; // @[Mux.scala 27:72]
|
|
wire _T_22663 = bht_rd_addr_hashed_p1_f == 8'h74; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_116; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23059 = _T_22663 ? bht_bank_rd_data_out_0_116 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23314 = _T_23313 | _T_23059; // @[Mux.scala 27:72]
|
|
wire _T_22665 = bht_rd_addr_hashed_p1_f == 8'h75; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_117; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23060 = _T_22665 ? bht_bank_rd_data_out_0_117 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23315 = _T_23314 | _T_23060; // @[Mux.scala 27:72]
|
|
wire _T_22667 = bht_rd_addr_hashed_p1_f == 8'h76; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_118; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23061 = _T_22667 ? bht_bank_rd_data_out_0_118 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23316 = _T_23315 | _T_23061; // @[Mux.scala 27:72]
|
|
wire _T_22669 = bht_rd_addr_hashed_p1_f == 8'h77; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_119; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23062 = _T_22669 ? bht_bank_rd_data_out_0_119 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23317 = _T_23316 | _T_23062; // @[Mux.scala 27:72]
|
|
wire _T_22671 = bht_rd_addr_hashed_p1_f == 8'h78; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_120; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23063 = _T_22671 ? bht_bank_rd_data_out_0_120 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23318 = _T_23317 | _T_23063; // @[Mux.scala 27:72]
|
|
wire _T_22673 = bht_rd_addr_hashed_p1_f == 8'h79; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_121; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23064 = _T_22673 ? bht_bank_rd_data_out_0_121 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23319 = _T_23318 | _T_23064; // @[Mux.scala 27:72]
|
|
wire _T_22675 = bht_rd_addr_hashed_p1_f == 8'h7a; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_122; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23065 = _T_22675 ? bht_bank_rd_data_out_0_122 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23320 = _T_23319 | _T_23065; // @[Mux.scala 27:72]
|
|
wire _T_22677 = bht_rd_addr_hashed_p1_f == 8'h7b; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_123; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23066 = _T_22677 ? bht_bank_rd_data_out_0_123 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23321 = _T_23320 | _T_23066; // @[Mux.scala 27:72]
|
|
wire _T_22679 = bht_rd_addr_hashed_p1_f == 8'h7c; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_124; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23067 = _T_22679 ? bht_bank_rd_data_out_0_124 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23322 = _T_23321 | _T_23067; // @[Mux.scala 27:72]
|
|
wire _T_22681 = bht_rd_addr_hashed_p1_f == 8'h7d; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_125; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23068 = _T_22681 ? bht_bank_rd_data_out_0_125 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23323 = _T_23322 | _T_23068; // @[Mux.scala 27:72]
|
|
wire _T_22683 = bht_rd_addr_hashed_p1_f == 8'h7e; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_126; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23069 = _T_22683 ? bht_bank_rd_data_out_0_126 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23324 = _T_23323 | _T_23069; // @[Mux.scala 27:72]
|
|
wire _T_22685 = bht_rd_addr_hashed_p1_f == 8'h7f; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_127; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23070 = _T_22685 ? bht_bank_rd_data_out_0_127 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23325 = _T_23324 | _T_23070; // @[Mux.scala 27:72]
|
|
wire _T_22687 = bht_rd_addr_hashed_p1_f == 8'h80; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_128; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23071 = _T_22687 ? bht_bank_rd_data_out_0_128 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23326 = _T_23325 | _T_23071; // @[Mux.scala 27:72]
|
|
wire _T_22689 = bht_rd_addr_hashed_p1_f == 8'h81; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_129; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23072 = _T_22689 ? bht_bank_rd_data_out_0_129 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23327 = _T_23326 | _T_23072; // @[Mux.scala 27:72]
|
|
wire _T_22691 = bht_rd_addr_hashed_p1_f == 8'h82; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_130; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23073 = _T_22691 ? bht_bank_rd_data_out_0_130 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23328 = _T_23327 | _T_23073; // @[Mux.scala 27:72]
|
|
wire _T_22693 = bht_rd_addr_hashed_p1_f == 8'h83; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_131; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23074 = _T_22693 ? bht_bank_rd_data_out_0_131 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23329 = _T_23328 | _T_23074; // @[Mux.scala 27:72]
|
|
wire _T_22695 = bht_rd_addr_hashed_p1_f == 8'h84; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_132; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23075 = _T_22695 ? bht_bank_rd_data_out_0_132 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23330 = _T_23329 | _T_23075; // @[Mux.scala 27:72]
|
|
wire _T_22697 = bht_rd_addr_hashed_p1_f == 8'h85; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_133; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23076 = _T_22697 ? bht_bank_rd_data_out_0_133 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23331 = _T_23330 | _T_23076; // @[Mux.scala 27:72]
|
|
wire _T_22699 = bht_rd_addr_hashed_p1_f == 8'h86; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_134; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23077 = _T_22699 ? bht_bank_rd_data_out_0_134 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23332 = _T_23331 | _T_23077; // @[Mux.scala 27:72]
|
|
wire _T_22701 = bht_rd_addr_hashed_p1_f == 8'h87; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_135; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23078 = _T_22701 ? bht_bank_rd_data_out_0_135 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23333 = _T_23332 | _T_23078; // @[Mux.scala 27:72]
|
|
wire _T_22703 = bht_rd_addr_hashed_p1_f == 8'h88; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_136; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23079 = _T_22703 ? bht_bank_rd_data_out_0_136 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23334 = _T_23333 | _T_23079; // @[Mux.scala 27:72]
|
|
wire _T_22705 = bht_rd_addr_hashed_p1_f == 8'h89; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_137; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23080 = _T_22705 ? bht_bank_rd_data_out_0_137 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23335 = _T_23334 | _T_23080; // @[Mux.scala 27:72]
|
|
wire _T_22707 = bht_rd_addr_hashed_p1_f == 8'h8a; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_138; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23081 = _T_22707 ? bht_bank_rd_data_out_0_138 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23336 = _T_23335 | _T_23081; // @[Mux.scala 27:72]
|
|
wire _T_22709 = bht_rd_addr_hashed_p1_f == 8'h8b; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_139; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23082 = _T_22709 ? bht_bank_rd_data_out_0_139 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23337 = _T_23336 | _T_23082; // @[Mux.scala 27:72]
|
|
wire _T_22711 = bht_rd_addr_hashed_p1_f == 8'h8c; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_140; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23083 = _T_22711 ? bht_bank_rd_data_out_0_140 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23338 = _T_23337 | _T_23083; // @[Mux.scala 27:72]
|
|
wire _T_22713 = bht_rd_addr_hashed_p1_f == 8'h8d; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_141; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23084 = _T_22713 ? bht_bank_rd_data_out_0_141 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23339 = _T_23338 | _T_23084; // @[Mux.scala 27:72]
|
|
wire _T_22715 = bht_rd_addr_hashed_p1_f == 8'h8e; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_142; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23085 = _T_22715 ? bht_bank_rd_data_out_0_142 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23340 = _T_23339 | _T_23085; // @[Mux.scala 27:72]
|
|
wire _T_22717 = bht_rd_addr_hashed_p1_f == 8'h8f; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_143; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23086 = _T_22717 ? bht_bank_rd_data_out_0_143 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23341 = _T_23340 | _T_23086; // @[Mux.scala 27:72]
|
|
wire _T_22719 = bht_rd_addr_hashed_p1_f == 8'h90; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_144; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23087 = _T_22719 ? bht_bank_rd_data_out_0_144 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23342 = _T_23341 | _T_23087; // @[Mux.scala 27:72]
|
|
wire _T_22721 = bht_rd_addr_hashed_p1_f == 8'h91; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_145; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23088 = _T_22721 ? bht_bank_rd_data_out_0_145 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23343 = _T_23342 | _T_23088; // @[Mux.scala 27:72]
|
|
wire _T_22723 = bht_rd_addr_hashed_p1_f == 8'h92; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_146; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23089 = _T_22723 ? bht_bank_rd_data_out_0_146 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23344 = _T_23343 | _T_23089; // @[Mux.scala 27:72]
|
|
wire _T_22725 = bht_rd_addr_hashed_p1_f == 8'h93; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_147; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23090 = _T_22725 ? bht_bank_rd_data_out_0_147 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23345 = _T_23344 | _T_23090; // @[Mux.scala 27:72]
|
|
wire _T_22727 = bht_rd_addr_hashed_p1_f == 8'h94; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_148; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23091 = _T_22727 ? bht_bank_rd_data_out_0_148 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23346 = _T_23345 | _T_23091; // @[Mux.scala 27:72]
|
|
wire _T_22729 = bht_rd_addr_hashed_p1_f == 8'h95; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_149; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23092 = _T_22729 ? bht_bank_rd_data_out_0_149 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23347 = _T_23346 | _T_23092; // @[Mux.scala 27:72]
|
|
wire _T_22731 = bht_rd_addr_hashed_p1_f == 8'h96; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_150; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23093 = _T_22731 ? bht_bank_rd_data_out_0_150 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23348 = _T_23347 | _T_23093; // @[Mux.scala 27:72]
|
|
wire _T_22733 = bht_rd_addr_hashed_p1_f == 8'h97; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_151; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23094 = _T_22733 ? bht_bank_rd_data_out_0_151 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23349 = _T_23348 | _T_23094; // @[Mux.scala 27:72]
|
|
wire _T_22735 = bht_rd_addr_hashed_p1_f == 8'h98; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_152; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23095 = _T_22735 ? bht_bank_rd_data_out_0_152 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23350 = _T_23349 | _T_23095; // @[Mux.scala 27:72]
|
|
wire _T_22737 = bht_rd_addr_hashed_p1_f == 8'h99; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_153; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23096 = _T_22737 ? bht_bank_rd_data_out_0_153 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23351 = _T_23350 | _T_23096; // @[Mux.scala 27:72]
|
|
wire _T_22739 = bht_rd_addr_hashed_p1_f == 8'h9a; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_154; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23097 = _T_22739 ? bht_bank_rd_data_out_0_154 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23352 = _T_23351 | _T_23097; // @[Mux.scala 27:72]
|
|
wire _T_22741 = bht_rd_addr_hashed_p1_f == 8'h9b; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_155; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23098 = _T_22741 ? bht_bank_rd_data_out_0_155 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23353 = _T_23352 | _T_23098; // @[Mux.scala 27:72]
|
|
wire _T_22743 = bht_rd_addr_hashed_p1_f == 8'h9c; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_156; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23099 = _T_22743 ? bht_bank_rd_data_out_0_156 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23354 = _T_23353 | _T_23099; // @[Mux.scala 27:72]
|
|
wire _T_22745 = bht_rd_addr_hashed_p1_f == 8'h9d; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_157; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23100 = _T_22745 ? bht_bank_rd_data_out_0_157 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23355 = _T_23354 | _T_23100; // @[Mux.scala 27:72]
|
|
wire _T_22747 = bht_rd_addr_hashed_p1_f == 8'h9e; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_158; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23101 = _T_22747 ? bht_bank_rd_data_out_0_158 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23356 = _T_23355 | _T_23101; // @[Mux.scala 27:72]
|
|
wire _T_22749 = bht_rd_addr_hashed_p1_f == 8'h9f; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_159; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23102 = _T_22749 ? bht_bank_rd_data_out_0_159 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23357 = _T_23356 | _T_23102; // @[Mux.scala 27:72]
|
|
wire _T_22751 = bht_rd_addr_hashed_p1_f == 8'ha0; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_160; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23103 = _T_22751 ? bht_bank_rd_data_out_0_160 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23358 = _T_23357 | _T_23103; // @[Mux.scala 27:72]
|
|
wire _T_22753 = bht_rd_addr_hashed_p1_f == 8'ha1; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_161; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23104 = _T_22753 ? bht_bank_rd_data_out_0_161 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23359 = _T_23358 | _T_23104; // @[Mux.scala 27:72]
|
|
wire _T_22755 = bht_rd_addr_hashed_p1_f == 8'ha2; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_162; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23105 = _T_22755 ? bht_bank_rd_data_out_0_162 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23360 = _T_23359 | _T_23105; // @[Mux.scala 27:72]
|
|
wire _T_22757 = bht_rd_addr_hashed_p1_f == 8'ha3; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_163; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23106 = _T_22757 ? bht_bank_rd_data_out_0_163 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23361 = _T_23360 | _T_23106; // @[Mux.scala 27:72]
|
|
wire _T_22759 = bht_rd_addr_hashed_p1_f == 8'ha4; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_164; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23107 = _T_22759 ? bht_bank_rd_data_out_0_164 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23362 = _T_23361 | _T_23107; // @[Mux.scala 27:72]
|
|
wire _T_22761 = bht_rd_addr_hashed_p1_f == 8'ha5; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_165; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23108 = _T_22761 ? bht_bank_rd_data_out_0_165 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23363 = _T_23362 | _T_23108; // @[Mux.scala 27:72]
|
|
wire _T_22763 = bht_rd_addr_hashed_p1_f == 8'ha6; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_166; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23109 = _T_22763 ? bht_bank_rd_data_out_0_166 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23364 = _T_23363 | _T_23109; // @[Mux.scala 27:72]
|
|
wire _T_22765 = bht_rd_addr_hashed_p1_f == 8'ha7; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_167; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23110 = _T_22765 ? bht_bank_rd_data_out_0_167 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23365 = _T_23364 | _T_23110; // @[Mux.scala 27:72]
|
|
wire _T_22767 = bht_rd_addr_hashed_p1_f == 8'ha8; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_168; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23111 = _T_22767 ? bht_bank_rd_data_out_0_168 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23366 = _T_23365 | _T_23111; // @[Mux.scala 27:72]
|
|
wire _T_22769 = bht_rd_addr_hashed_p1_f == 8'ha9; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_169; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23112 = _T_22769 ? bht_bank_rd_data_out_0_169 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23367 = _T_23366 | _T_23112; // @[Mux.scala 27:72]
|
|
wire _T_22771 = bht_rd_addr_hashed_p1_f == 8'haa; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_170; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23113 = _T_22771 ? bht_bank_rd_data_out_0_170 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23368 = _T_23367 | _T_23113; // @[Mux.scala 27:72]
|
|
wire _T_22773 = bht_rd_addr_hashed_p1_f == 8'hab; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_171; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23114 = _T_22773 ? bht_bank_rd_data_out_0_171 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23369 = _T_23368 | _T_23114; // @[Mux.scala 27:72]
|
|
wire _T_22775 = bht_rd_addr_hashed_p1_f == 8'hac; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_172; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23115 = _T_22775 ? bht_bank_rd_data_out_0_172 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23370 = _T_23369 | _T_23115; // @[Mux.scala 27:72]
|
|
wire _T_22777 = bht_rd_addr_hashed_p1_f == 8'had; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_173; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23116 = _T_22777 ? bht_bank_rd_data_out_0_173 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23371 = _T_23370 | _T_23116; // @[Mux.scala 27:72]
|
|
wire _T_22779 = bht_rd_addr_hashed_p1_f == 8'hae; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_174; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23117 = _T_22779 ? bht_bank_rd_data_out_0_174 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23372 = _T_23371 | _T_23117; // @[Mux.scala 27:72]
|
|
wire _T_22781 = bht_rd_addr_hashed_p1_f == 8'haf; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_175; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23118 = _T_22781 ? bht_bank_rd_data_out_0_175 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23373 = _T_23372 | _T_23118; // @[Mux.scala 27:72]
|
|
wire _T_22783 = bht_rd_addr_hashed_p1_f == 8'hb0; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_176; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23119 = _T_22783 ? bht_bank_rd_data_out_0_176 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23374 = _T_23373 | _T_23119; // @[Mux.scala 27:72]
|
|
wire _T_22785 = bht_rd_addr_hashed_p1_f == 8'hb1; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_177; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23120 = _T_22785 ? bht_bank_rd_data_out_0_177 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23375 = _T_23374 | _T_23120; // @[Mux.scala 27:72]
|
|
wire _T_22787 = bht_rd_addr_hashed_p1_f == 8'hb2; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_178; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23121 = _T_22787 ? bht_bank_rd_data_out_0_178 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23376 = _T_23375 | _T_23121; // @[Mux.scala 27:72]
|
|
wire _T_22789 = bht_rd_addr_hashed_p1_f == 8'hb3; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_179; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23122 = _T_22789 ? bht_bank_rd_data_out_0_179 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23377 = _T_23376 | _T_23122; // @[Mux.scala 27:72]
|
|
wire _T_22791 = bht_rd_addr_hashed_p1_f == 8'hb4; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_180; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23123 = _T_22791 ? bht_bank_rd_data_out_0_180 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23378 = _T_23377 | _T_23123; // @[Mux.scala 27:72]
|
|
wire _T_22793 = bht_rd_addr_hashed_p1_f == 8'hb5; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_181; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23124 = _T_22793 ? bht_bank_rd_data_out_0_181 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23379 = _T_23378 | _T_23124; // @[Mux.scala 27:72]
|
|
wire _T_22795 = bht_rd_addr_hashed_p1_f == 8'hb6; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_182; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23125 = _T_22795 ? bht_bank_rd_data_out_0_182 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23380 = _T_23379 | _T_23125; // @[Mux.scala 27:72]
|
|
wire _T_22797 = bht_rd_addr_hashed_p1_f == 8'hb7; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_183; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23126 = _T_22797 ? bht_bank_rd_data_out_0_183 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23381 = _T_23380 | _T_23126; // @[Mux.scala 27:72]
|
|
wire _T_22799 = bht_rd_addr_hashed_p1_f == 8'hb8; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_184; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23127 = _T_22799 ? bht_bank_rd_data_out_0_184 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23382 = _T_23381 | _T_23127; // @[Mux.scala 27:72]
|
|
wire _T_22801 = bht_rd_addr_hashed_p1_f == 8'hb9; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_185; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23128 = _T_22801 ? bht_bank_rd_data_out_0_185 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23383 = _T_23382 | _T_23128; // @[Mux.scala 27:72]
|
|
wire _T_22803 = bht_rd_addr_hashed_p1_f == 8'hba; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_186; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23129 = _T_22803 ? bht_bank_rd_data_out_0_186 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23384 = _T_23383 | _T_23129; // @[Mux.scala 27:72]
|
|
wire _T_22805 = bht_rd_addr_hashed_p1_f == 8'hbb; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_187; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23130 = _T_22805 ? bht_bank_rd_data_out_0_187 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23385 = _T_23384 | _T_23130; // @[Mux.scala 27:72]
|
|
wire _T_22807 = bht_rd_addr_hashed_p1_f == 8'hbc; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_188; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23131 = _T_22807 ? bht_bank_rd_data_out_0_188 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23386 = _T_23385 | _T_23131; // @[Mux.scala 27:72]
|
|
wire _T_22809 = bht_rd_addr_hashed_p1_f == 8'hbd; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_189; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23132 = _T_22809 ? bht_bank_rd_data_out_0_189 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23387 = _T_23386 | _T_23132; // @[Mux.scala 27:72]
|
|
wire _T_22811 = bht_rd_addr_hashed_p1_f == 8'hbe; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_190; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23133 = _T_22811 ? bht_bank_rd_data_out_0_190 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23388 = _T_23387 | _T_23133; // @[Mux.scala 27:72]
|
|
wire _T_22813 = bht_rd_addr_hashed_p1_f == 8'hbf; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_191; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23134 = _T_22813 ? bht_bank_rd_data_out_0_191 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23389 = _T_23388 | _T_23134; // @[Mux.scala 27:72]
|
|
wire _T_22815 = bht_rd_addr_hashed_p1_f == 8'hc0; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_192; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23135 = _T_22815 ? bht_bank_rd_data_out_0_192 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23390 = _T_23389 | _T_23135; // @[Mux.scala 27:72]
|
|
wire _T_22817 = bht_rd_addr_hashed_p1_f == 8'hc1; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_193; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23136 = _T_22817 ? bht_bank_rd_data_out_0_193 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23391 = _T_23390 | _T_23136; // @[Mux.scala 27:72]
|
|
wire _T_22819 = bht_rd_addr_hashed_p1_f == 8'hc2; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_194; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23137 = _T_22819 ? bht_bank_rd_data_out_0_194 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23392 = _T_23391 | _T_23137; // @[Mux.scala 27:72]
|
|
wire _T_22821 = bht_rd_addr_hashed_p1_f == 8'hc3; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_195; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23138 = _T_22821 ? bht_bank_rd_data_out_0_195 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23393 = _T_23392 | _T_23138; // @[Mux.scala 27:72]
|
|
wire _T_22823 = bht_rd_addr_hashed_p1_f == 8'hc4; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_196; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23139 = _T_22823 ? bht_bank_rd_data_out_0_196 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23394 = _T_23393 | _T_23139; // @[Mux.scala 27:72]
|
|
wire _T_22825 = bht_rd_addr_hashed_p1_f == 8'hc5; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_197; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23140 = _T_22825 ? bht_bank_rd_data_out_0_197 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23395 = _T_23394 | _T_23140; // @[Mux.scala 27:72]
|
|
wire _T_22827 = bht_rd_addr_hashed_p1_f == 8'hc6; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_198; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23141 = _T_22827 ? bht_bank_rd_data_out_0_198 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23396 = _T_23395 | _T_23141; // @[Mux.scala 27:72]
|
|
wire _T_22829 = bht_rd_addr_hashed_p1_f == 8'hc7; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_199; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23142 = _T_22829 ? bht_bank_rd_data_out_0_199 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23397 = _T_23396 | _T_23142; // @[Mux.scala 27:72]
|
|
wire _T_22831 = bht_rd_addr_hashed_p1_f == 8'hc8; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_200; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23143 = _T_22831 ? bht_bank_rd_data_out_0_200 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23398 = _T_23397 | _T_23143; // @[Mux.scala 27:72]
|
|
wire _T_22833 = bht_rd_addr_hashed_p1_f == 8'hc9; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_201; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23144 = _T_22833 ? bht_bank_rd_data_out_0_201 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23399 = _T_23398 | _T_23144; // @[Mux.scala 27:72]
|
|
wire _T_22835 = bht_rd_addr_hashed_p1_f == 8'hca; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_202; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23145 = _T_22835 ? bht_bank_rd_data_out_0_202 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23400 = _T_23399 | _T_23145; // @[Mux.scala 27:72]
|
|
wire _T_22837 = bht_rd_addr_hashed_p1_f == 8'hcb; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_203; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23146 = _T_22837 ? bht_bank_rd_data_out_0_203 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23401 = _T_23400 | _T_23146; // @[Mux.scala 27:72]
|
|
wire _T_22839 = bht_rd_addr_hashed_p1_f == 8'hcc; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_204; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23147 = _T_22839 ? bht_bank_rd_data_out_0_204 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23402 = _T_23401 | _T_23147; // @[Mux.scala 27:72]
|
|
wire _T_22841 = bht_rd_addr_hashed_p1_f == 8'hcd; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_205; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23148 = _T_22841 ? bht_bank_rd_data_out_0_205 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23403 = _T_23402 | _T_23148; // @[Mux.scala 27:72]
|
|
wire _T_22843 = bht_rd_addr_hashed_p1_f == 8'hce; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_206; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23149 = _T_22843 ? bht_bank_rd_data_out_0_206 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23404 = _T_23403 | _T_23149; // @[Mux.scala 27:72]
|
|
wire _T_22845 = bht_rd_addr_hashed_p1_f == 8'hcf; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_207; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23150 = _T_22845 ? bht_bank_rd_data_out_0_207 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23405 = _T_23404 | _T_23150; // @[Mux.scala 27:72]
|
|
wire _T_22847 = bht_rd_addr_hashed_p1_f == 8'hd0; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_208; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23151 = _T_22847 ? bht_bank_rd_data_out_0_208 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23406 = _T_23405 | _T_23151; // @[Mux.scala 27:72]
|
|
wire _T_22849 = bht_rd_addr_hashed_p1_f == 8'hd1; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_209; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23152 = _T_22849 ? bht_bank_rd_data_out_0_209 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23407 = _T_23406 | _T_23152; // @[Mux.scala 27:72]
|
|
wire _T_22851 = bht_rd_addr_hashed_p1_f == 8'hd2; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_210; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23153 = _T_22851 ? bht_bank_rd_data_out_0_210 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23408 = _T_23407 | _T_23153; // @[Mux.scala 27:72]
|
|
wire _T_22853 = bht_rd_addr_hashed_p1_f == 8'hd3; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_211; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23154 = _T_22853 ? bht_bank_rd_data_out_0_211 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23409 = _T_23408 | _T_23154; // @[Mux.scala 27:72]
|
|
wire _T_22855 = bht_rd_addr_hashed_p1_f == 8'hd4; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_212; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23155 = _T_22855 ? bht_bank_rd_data_out_0_212 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23410 = _T_23409 | _T_23155; // @[Mux.scala 27:72]
|
|
wire _T_22857 = bht_rd_addr_hashed_p1_f == 8'hd5; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_213; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23156 = _T_22857 ? bht_bank_rd_data_out_0_213 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23411 = _T_23410 | _T_23156; // @[Mux.scala 27:72]
|
|
wire _T_22859 = bht_rd_addr_hashed_p1_f == 8'hd6; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_214; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23157 = _T_22859 ? bht_bank_rd_data_out_0_214 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23412 = _T_23411 | _T_23157; // @[Mux.scala 27:72]
|
|
wire _T_22861 = bht_rd_addr_hashed_p1_f == 8'hd7; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_215; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23158 = _T_22861 ? bht_bank_rd_data_out_0_215 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23413 = _T_23412 | _T_23158; // @[Mux.scala 27:72]
|
|
wire _T_22863 = bht_rd_addr_hashed_p1_f == 8'hd8; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_216; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23159 = _T_22863 ? bht_bank_rd_data_out_0_216 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23414 = _T_23413 | _T_23159; // @[Mux.scala 27:72]
|
|
wire _T_22865 = bht_rd_addr_hashed_p1_f == 8'hd9; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_217; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23160 = _T_22865 ? bht_bank_rd_data_out_0_217 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23415 = _T_23414 | _T_23160; // @[Mux.scala 27:72]
|
|
wire _T_22867 = bht_rd_addr_hashed_p1_f == 8'hda; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_218; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23161 = _T_22867 ? bht_bank_rd_data_out_0_218 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23416 = _T_23415 | _T_23161; // @[Mux.scala 27:72]
|
|
wire _T_22869 = bht_rd_addr_hashed_p1_f == 8'hdb; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_219; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23162 = _T_22869 ? bht_bank_rd_data_out_0_219 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23417 = _T_23416 | _T_23162; // @[Mux.scala 27:72]
|
|
wire _T_22871 = bht_rd_addr_hashed_p1_f == 8'hdc; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_220; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23163 = _T_22871 ? bht_bank_rd_data_out_0_220 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23418 = _T_23417 | _T_23163; // @[Mux.scala 27:72]
|
|
wire _T_22873 = bht_rd_addr_hashed_p1_f == 8'hdd; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_221; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23164 = _T_22873 ? bht_bank_rd_data_out_0_221 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23419 = _T_23418 | _T_23164; // @[Mux.scala 27:72]
|
|
wire _T_22875 = bht_rd_addr_hashed_p1_f == 8'hde; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_222; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23165 = _T_22875 ? bht_bank_rd_data_out_0_222 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23420 = _T_23419 | _T_23165; // @[Mux.scala 27:72]
|
|
wire _T_22877 = bht_rd_addr_hashed_p1_f == 8'hdf; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_223; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23166 = _T_22877 ? bht_bank_rd_data_out_0_223 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23421 = _T_23420 | _T_23166; // @[Mux.scala 27:72]
|
|
wire _T_22879 = bht_rd_addr_hashed_p1_f == 8'he0; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_224; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23167 = _T_22879 ? bht_bank_rd_data_out_0_224 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23422 = _T_23421 | _T_23167; // @[Mux.scala 27:72]
|
|
wire _T_22881 = bht_rd_addr_hashed_p1_f == 8'he1; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_225; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23168 = _T_22881 ? bht_bank_rd_data_out_0_225 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23423 = _T_23422 | _T_23168; // @[Mux.scala 27:72]
|
|
wire _T_22883 = bht_rd_addr_hashed_p1_f == 8'he2; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_226; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23169 = _T_22883 ? bht_bank_rd_data_out_0_226 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23424 = _T_23423 | _T_23169; // @[Mux.scala 27:72]
|
|
wire _T_22885 = bht_rd_addr_hashed_p1_f == 8'he3; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_227; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23170 = _T_22885 ? bht_bank_rd_data_out_0_227 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23425 = _T_23424 | _T_23170; // @[Mux.scala 27:72]
|
|
wire _T_22887 = bht_rd_addr_hashed_p1_f == 8'he4; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_228; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23171 = _T_22887 ? bht_bank_rd_data_out_0_228 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23426 = _T_23425 | _T_23171; // @[Mux.scala 27:72]
|
|
wire _T_22889 = bht_rd_addr_hashed_p1_f == 8'he5; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_229; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23172 = _T_22889 ? bht_bank_rd_data_out_0_229 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23427 = _T_23426 | _T_23172; // @[Mux.scala 27:72]
|
|
wire _T_22891 = bht_rd_addr_hashed_p1_f == 8'he6; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_230; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23173 = _T_22891 ? bht_bank_rd_data_out_0_230 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23428 = _T_23427 | _T_23173; // @[Mux.scala 27:72]
|
|
wire _T_22893 = bht_rd_addr_hashed_p1_f == 8'he7; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_231; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23174 = _T_22893 ? bht_bank_rd_data_out_0_231 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23429 = _T_23428 | _T_23174; // @[Mux.scala 27:72]
|
|
wire _T_22895 = bht_rd_addr_hashed_p1_f == 8'he8; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_232; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23175 = _T_22895 ? bht_bank_rd_data_out_0_232 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23430 = _T_23429 | _T_23175; // @[Mux.scala 27:72]
|
|
wire _T_22897 = bht_rd_addr_hashed_p1_f == 8'he9; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_233; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23176 = _T_22897 ? bht_bank_rd_data_out_0_233 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23431 = _T_23430 | _T_23176; // @[Mux.scala 27:72]
|
|
wire _T_22899 = bht_rd_addr_hashed_p1_f == 8'hea; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_234; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23177 = _T_22899 ? bht_bank_rd_data_out_0_234 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23432 = _T_23431 | _T_23177; // @[Mux.scala 27:72]
|
|
wire _T_22901 = bht_rd_addr_hashed_p1_f == 8'heb; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_235; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23178 = _T_22901 ? bht_bank_rd_data_out_0_235 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23433 = _T_23432 | _T_23178; // @[Mux.scala 27:72]
|
|
wire _T_22903 = bht_rd_addr_hashed_p1_f == 8'hec; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_236; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23179 = _T_22903 ? bht_bank_rd_data_out_0_236 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23434 = _T_23433 | _T_23179; // @[Mux.scala 27:72]
|
|
wire _T_22905 = bht_rd_addr_hashed_p1_f == 8'hed; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_237; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23180 = _T_22905 ? bht_bank_rd_data_out_0_237 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23435 = _T_23434 | _T_23180; // @[Mux.scala 27:72]
|
|
wire _T_22907 = bht_rd_addr_hashed_p1_f == 8'hee; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_238; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23181 = _T_22907 ? bht_bank_rd_data_out_0_238 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23436 = _T_23435 | _T_23181; // @[Mux.scala 27:72]
|
|
wire _T_22909 = bht_rd_addr_hashed_p1_f == 8'hef; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_239; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23182 = _T_22909 ? bht_bank_rd_data_out_0_239 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23437 = _T_23436 | _T_23182; // @[Mux.scala 27:72]
|
|
wire _T_22911 = bht_rd_addr_hashed_p1_f == 8'hf0; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_240; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23183 = _T_22911 ? bht_bank_rd_data_out_0_240 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23438 = _T_23437 | _T_23183; // @[Mux.scala 27:72]
|
|
wire _T_22913 = bht_rd_addr_hashed_p1_f == 8'hf1; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_241; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23184 = _T_22913 ? bht_bank_rd_data_out_0_241 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23439 = _T_23438 | _T_23184; // @[Mux.scala 27:72]
|
|
wire _T_22915 = bht_rd_addr_hashed_p1_f == 8'hf2; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_242; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23185 = _T_22915 ? bht_bank_rd_data_out_0_242 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23440 = _T_23439 | _T_23185; // @[Mux.scala 27:72]
|
|
wire _T_22917 = bht_rd_addr_hashed_p1_f == 8'hf3; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_243; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23186 = _T_22917 ? bht_bank_rd_data_out_0_243 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23441 = _T_23440 | _T_23186; // @[Mux.scala 27:72]
|
|
wire _T_22919 = bht_rd_addr_hashed_p1_f == 8'hf4; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_244; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23187 = _T_22919 ? bht_bank_rd_data_out_0_244 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23442 = _T_23441 | _T_23187; // @[Mux.scala 27:72]
|
|
wire _T_22921 = bht_rd_addr_hashed_p1_f == 8'hf5; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_245; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23188 = _T_22921 ? bht_bank_rd_data_out_0_245 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23443 = _T_23442 | _T_23188; // @[Mux.scala 27:72]
|
|
wire _T_22923 = bht_rd_addr_hashed_p1_f == 8'hf6; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_246; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23189 = _T_22923 ? bht_bank_rd_data_out_0_246 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23444 = _T_23443 | _T_23189; // @[Mux.scala 27:72]
|
|
wire _T_22925 = bht_rd_addr_hashed_p1_f == 8'hf7; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_247; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23190 = _T_22925 ? bht_bank_rd_data_out_0_247 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23445 = _T_23444 | _T_23190; // @[Mux.scala 27:72]
|
|
wire _T_22927 = bht_rd_addr_hashed_p1_f == 8'hf8; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_248; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23191 = _T_22927 ? bht_bank_rd_data_out_0_248 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23446 = _T_23445 | _T_23191; // @[Mux.scala 27:72]
|
|
wire _T_22929 = bht_rd_addr_hashed_p1_f == 8'hf9; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_249; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23192 = _T_22929 ? bht_bank_rd_data_out_0_249 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23447 = _T_23446 | _T_23192; // @[Mux.scala 27:72]
|
|
wire _T_22931 = bht_rd_addr_hashed_p1_f == 8'hfa; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_250; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23193 = _T_22931 ? bht_bank_rd_data_out_0_250 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23448 = _T_23447 | _T_23193; // @[Mux.scala 27:72]
|
|
wire _T_22933 = bht_rd_addr_hashed_p1_f == 8'hfb; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_251; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23194 = _T_22933 ? bht_bank_rd_data_out_0_251 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23449 = _T_23448 | _T_23194; // @[Mux.scala 27:72]
|
|
wire _T_22935 = bht_rd_addr_hashed_p1_f == 8'hfc; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_252; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23195 = _T_22935 ? bht_bank_rd_data_out_0_252 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23450 = _T_23449 | _T_23195; // @[Mux.scala 27:72]
|
|
wire _T_22937 = bht_rd_addr_hashed_p1_f == 8'hfd; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_253; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23196 = _T_22937 ? bht_bank_rd_data_out_0_253 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23451 = _T_23450 | _T_23196; // @[Mux.scala 27:72]
|
|
wire _T_22939 = bht_rd_addr_hashed_p1_f == 8'hfe; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_254; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23197 = _T_22939 ? bht_bank_rd_data_out_0_254 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23452 = _T_23451 | _T_23197; // @[Mux.scala 27:72]
|
|
wire _T_22941 = bht_rd_addr_hashed_p1_f == 8'hff; // @[el2_ifu_bp_ctl.scala 468:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_255; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23198 = _T_22941 ? bht_bank_rd_data_out_0_255 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] bht_bank0_rd_data_p1_f = _T_23452 | _T_23198; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_260 = io_ifc_fetch_addr_f[0] ? bht_bank0_rd_data_p1_f : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] bht_vbank1_rd_data_f = _T_259 | _T_260; // @[Mux.scala 27:72]
|
|
wire _T_264 = bht_force_taken_f[1] | bht_vbank1_rd_data_f[1]; // @[el2_ifu_bp_ctl.scala 293:42]
|
|
wire [1:0] wayhit_f = tag_match_way0_expanded_f | tag_match_way1_expanded_f; // @[el2_ifu_bp_ctl.scala 167:44]
|
|
wire [1:0] _T_158 = _T_143 ? wayhit_f : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] wayhit_p1_f = tag_match_way0_expanded_p1_f | tag_match_way1_expanded_p1_f; // @[el2_ifu_bp_ctl.scala 169:50]
|
|
wire [1:0] _T_157 = {wayhit_p1_f[0],wayhit_f[1]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_159 = io_ifc_fetch_addr_f[0] ? _T_157 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_160 = _T_158 | _T_159; // @[Mux.scala 27:72]
|
|
wire eoc_near = &io_ifc_fetch_addr_f[4:2]; // @[el2_ifu_bp_ctl.scala 253:64]
|
|
wire _T_218 = ~eoc_near; // @[el2_ifu_bp_ctl.scala 256:15]
|
|
wire [1:0] _T_220 = ~io_ifc_fetch_addr_f[1:0]; // @[el2_ifu_bp_ctl.scala 256:28]
|
|
wire _T_221 = |_T_220; // @[el2_ifu_bp_ctl.scala 256:58]
|
|
wire eoc_mask = _T_218 | _T_221; // @[el2_ifu_bp_ctl.scala 256:25]
|
|
wire [1:0] _T_162 = {eoc_mask,1'h1}; // @[Cat.scala 29:58]
|
|
wire [1:0] vwayhit_f = _T_160 & _T_162; // @[el2_ifu_bp_ctl.scala 215:71]
|
|
wire _T_266 = _T_264 & vwayhit_f[1]; // @[el2_ifu_bp_ctl.scala 293:69]
|
|
wire [1:0] _T_20895 = _T_21407 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20896 = _T_21409 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21151 = _T_20895 | _T_20896; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20897 = _T_21411 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21152 = _T_21151 | _T_20897; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20898 = _T_21413 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21153 = _T_21152 | _T_20898; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20899 = _T_21415 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21154 = _T_21153 | _T_20899; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20900 = _T_21417 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21155 = _T_21154 | _T_20900; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20901 = _T_21419 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21156 = _T_21155 | _T_20901; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20902 = _T_21421 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21157 = _T_21156 | _T_20902; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20903 = _T_21423 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21158 = _T_21157 | _T_20903; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20904 = _T_21425 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21159 = _T_21158 | _T_20904; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20905 = _T_21427 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21160 = _T_21159 | _T_20905; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20906 = _T_21429 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21161 = _T_21160 | _T_20906; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20907 = _T_21431 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21162 = _T_21161 | _T_20907; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20908 = _T_21433 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21163 = _T_21162 | _T_20908; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20909 = _T_21435 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21164 = _T_21163 | _T_20909; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20910 = _T_21437 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21165 = _T_21164 | _T_20910; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20911 = _T_21439 ? bht_bank_rd_data_out_0_16 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21166 = _T_21165 | _T_20911; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20912 = _T_21441 ? bht_bank_rd_data_out_0_17 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21167 = _T_21166 | _T_20912; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20913 = _T_21443 ? bht_bank_rd_data_out_0_18 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21168 = _T_21167 | _T_20913; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20914 = _T_21445 ? bht_bank_rd_data_out_0_19 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21169 = _T_21168 | _T_20914; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20915 = _T_21447 ? bht_bank_rd_data_out_0_20 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21170 = _T_21169 | _T_20915; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20916 = _T_21449 ? bht_bank_rd_data_out_0_21 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21171 = _T_21170 | _T_20916; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20917 = _T_21451 ? bht_bank_rd_data_out_0_22 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21172 = _T_21171 | _T_20917; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20918 = _T_21453 ? bht_bank_rd_data_out_0_23 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21173 = _T_21172 | _T_20918; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20919 = _T_21455 ? bht_bank_rd_data_out_0_24 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21174 = _T_21173 | _T_20919; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20920 = _T_21457 ? bht_bank_rd_data_out_0_25 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21175 = _T_21174 | _T_20920; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20921 = _T_21459 ? bht_bank_rd_data_out_0_26 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21176 = _T_21175 | _T_20921; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20922 = _T_21461 ? bht_bank_rd_data_out_0_27 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21177 = _T_21176 | _T_20922; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20923 = _T_21463 ? bht_bank_rd_data_out_0_28 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21178 = _T_21177 | _T_20923; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20924 = _T_21465 ? bht_bank_rd_data_out_0_29 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21179 = _T_21178 | _T_20924; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20925 = _T_21467 ? bht_bank_rd_data_out_0_30 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21180 = _T_21179 | _T_20925; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20926 = _T_21469 ? bht_bank_rd_data_out_0_31 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21181 = _T_21180 | _T_20926; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20927 = _T_21471 ? bht_bank_rd_data_out_0_32 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21182 = _T_21181 | _T_20927; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20928 = _T_21473 ? bht_bank_rd_data_out_0_33 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21183 = _T_21182 | _T_20928; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20929 = _T_21475 ? bht_bank_rd_data_out_0_34 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21184 = _T_21183 | _T_20929; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20930 = _T_21477 ? bht_bank_rd_data_out_0_35 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21185 = _T_21184 | _T_20930; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20931 = _T_21479 ? bht_bank_rd_data_out_0_36 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21186 = _T_21185 | _T_20931; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20932 = _T_21481 ? bht_bank_rd_data_out_0_37 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21187 = _T_21186 | _T_20932; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20933 = _T_21483 ? bht_bank_rd_data_out_0_38 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21188 = _T_21187 | _T_20933; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20934 = _T_21485 ? bht_bank_rd_data_out_0_39 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21189 = _T_21188 | _T_20934; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20935 = _T_21487 ? bht_bank_rd_data_out_0_40 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21190 = _T_21189 | _T_20935; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20936 = _T_21489 ? bht_bank_rd_data_out_0_41 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21191 = _T_21190 | _T_20936; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20937 = _T_21491 ? bht_bank_rd_data_out_0_42 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21192 = _T_21191 | _T_20937; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20938 = _T_21493 ? bht_bank_rd_data_out_0_43 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21193 = _T_21192 | _T_20938; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20939 = _T_21495 ? bht_bank_rd_data_out_0_44 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21194 = _T_21193 | _T_20939; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20940 = _T_21497 ? bht_bank_rd_data_out_0_45 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21195 = _T_21194 | _T_20940; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20941 = _T_21499 ? bht_bank_rd_data_out_0_46 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21196 = _T_21195 | _T_20941; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20942 = _T_21501 ? bht_bank_rd_data_out_0_47 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21197 = _T_21196 | _T_20942; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20943 = _T_21503 ? bht_bank_rd_data_out_0_48 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21198 = _T_21197 | _T_20943; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20944 = _T_21505 ? bht_bank_rd_data_out_0_49 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21199 = _T_21198 | _T_20944; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20945 = _T_21507 ? bht_bank_rd_data_out_0_50 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21200 = _T_21199 | _T_20945; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20946 = _T_21509 ? bht_bank_rd_data_out_0_51 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21201 = _T_21200 | _T_20946; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20947 = _T_21511 ? bht_bank_rd_data_out_0_52 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21202 = _T_21201 | _T_20947; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20948 = _T_21513 ? bht_bank_rd_data_out_0_53 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21203 = _T_21202 | _T_20948; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20949 = _T_21515 ? bht_bank_rd_data_out_0_54 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21204 = _T_21203 | _T_20949; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20950 = _T_21517 ? bht_bank_rd_data_out_0_55 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21205 = _T_21204 | _T_20950; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20951 = _T_21519 ? bht_bank_rd_data_out_0_56 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21206 = _T_21205 | _T_20951; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20952 = _T_21521 ? bht_bank_rd_data_out_0_57 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21207 = _T_21206 | _T_20952; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20953 = _T_21523 ? bht_bank_rd_data_out_0_58 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21208 = _T_21207 | _T_20953; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20954 = _T_21525 ? bht_bank_rd_data_out_0_59 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21209 = _T_21208 | _T_20954; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20955 = _T_21527 ? bht_bank_rd_data_out_0_60 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21210 = _T_21209 | _T_20955; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20956 = _T_21529 ? bht_bank_rd_data_out_0_61 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21211 = _T_21210 | _T_20956; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20957 = _T_21531 ? bht_bank_rd_data_out_0_62 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21212 = _T_21211 | _T_20957; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20958 = _T_21533 ? bht_bank_rd_data_out_0_63 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21213 = _T_21212 | _T_20958; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20959 = _T_21535 ? bht_bank_rd_data_out_0_64 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21214 = _T_21213 | _T_20959; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20960 = _T_21537 ? bht_bank_rd_data_out_0_65 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21215 = _T_21214 | _T_20960; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20961 = _T_21539 ? bht_bank_rd_data_out_0_66 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21216 = _T_21215 | _T_20961; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20962 = _T_21541 ? bht_bank_rd_data_out_0_67 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21217 = _T_21216 | _T_20962; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20963 = _T_21543 ? bht_bank_rd_data_out_0_68 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21218 = _T_21217 | _T_20963; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20964 = _T_21545 ? bht_bank_rd_data_out_0_69 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21219 = _T_21218 | _T_20964; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20965 = _T_21547 ? bht_bank_rd_data_out_0_70 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21220 = _T_21219 | _T_20965; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20966 = _T_21549 ? bht_bank_rd_data_out_0_71 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21221 = _T_21220 | _T_20966; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20967 = _T_21551 ? bht_bank_rd_data_out_0_72 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21222 = _T_21221 | _T_20967; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20968 = _T_21553 ? bht_bank_rd_data_out_0_73 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21223 = _T_21222 | _T_20968; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20969 = _T_21555 ? bht_bank_rd_data_out_0_74 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21224 = _T_21223 | _T_20969; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20970 = _T_21557 ? bht_bank_rd_data_out_0_75 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21225 = _T_21224 | _T_20970; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20971 = _T_21559 ? bht_bank_rd_data_out_0_76 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21226 = _T_21225 | _T_20971; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20972 = _T_21561 ? bht_bank_rd_data_out_0_77 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21227 = _T_21226 | _T_20972; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20973 = _T_21563 ? bht_bank_rd_data_out_0_78 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21228 = _T_21227 | _T_20973; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20974 = _T_21565 ? bht_bank_rd_data_out_0_79 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21229 = _T_21228 | _T_20974; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20975 = _T_21567 ? bht_bank_rd_data_out_0_80 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21230 = _T_21229 | _T_20975; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20976 = _T_21569 ? bht_bank_rd_data_out_0_81 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21231 = _T_21230 | _T_20976; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20977 = _T_21571 ? bht_bank_rd_data_out_0_82 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21232 = _T_21231 | _T_20977; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20978 = _T_21573 ? bht_bank_rd_data_out_0_83 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21233 = _T_21232 | _T_20978; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20979 = _T_21575 ? bht_bank_rd_data_out_0_84 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21234 = _T_21233 | _T_20979; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20980 = _T_21577 ? bht_bank_rd_data_out_0_85 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21235 = _T_21234 | _T_20980; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20981 = _T_21579 ? bht_bank_rd_data_out_0_86 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21236 = _T_21235 | _T_20981; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20982 = _T_21581 ? bht_bank_rd_data_out_0_87 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21237 = _T_21236 | _T_20982; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20983 = _T_21583 ? bht_bank_rd_data_out_0_88 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21238 = _T_21237 | _T_20983; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20984 = _T_21585 ? bht_bank_rd_data_out_0_89 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21239 = _T_21238 | _T_20984; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20985 = _T_21587 ? bht_bank_rd_data_out_0_90 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21240 = _T_21239 | _T_20985; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20986 = _T_21589 ? bht_bank_rd_data_out_0_91 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21241 = _T_21240 | _T_20986; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20987 = _T_21591 ? bht_bank_rd_data_out_0_92 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21242 = _T_21241 | _T_20987; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20988 = _T_21593 ? bht_bank_rd_data_out_0_93 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21243 = _T_21242 | _T_20988; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20989 = _T_21595 ? bht_bank_rd_data_out_0_94 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21244 = _T_21243 | _T_20989; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20990 = _T_21597 ? bht_bank_rd_data_out_0_95 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21245 = _T_21244 | _T_20990; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20991 = _T_21599 ? bht_bank_rd_data_out_0_96 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21246 = _T_21245 | _T_20991; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20992 = _T_21601 ? bht_bank_rd_data_out_0_97 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21247 = _T_21246 | _T_20992; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20993 = _T_21603 ? bht_bank_rd_data_out_0_98 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21248 = _T_21247 | _T_20993; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20994 = _T_21605 ? bht_bank_rd_data_out_0_99 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21249 = _T_21248 | _T_20994; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20995 = _T_21607 ? bht_bank_rd_data_out_0_100 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21250 = _T_21249 | _T_20995; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20996 = _T_21609 ? bht_bank_rd_data_out_0_101 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21251 = _T_21250 | _T_20996; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20997 = _T_21611 ? bht_bank_rd_data_out_0_102 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21252 = _T_21251 | _T_20997; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20998 = _T_21613 ? bht_bank_rd_data_out_0_103 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21253 = _T_21252 | _T_20998; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_20999 = _T_21615 ? bht_bank_rd_data_out_0_104 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21254 = _T_21253 | _T_20999; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21000 = _T_21617 ? bht_bank_rd_data_out_0_105 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21255 = _T_21254 | _T_21000; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21001 = _T_21619 ? bht_bank_rd_data_out_0_106 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21256 = _T_21255 | _T_21001; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21002 = _T_21621 ? bht_bank_rd_data_out_0_107 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21257 = _T_21256 | _T_21002; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21003 = _T_21623 ? bht_bank_rd_data_out_0_108 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21258 = _T_21257 | _T_21003; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21004 = _T_21625 ? bht_bank_rd_data_out_0_109 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21259 = _T_21258 | _T_21004; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21005 = _T_21627 ? bht_bank_rd_data_out_0_110 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21260 = _T_21259 | _T_21005; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21006 = _T_21629 ? bht_bank_rd_data_out_0_111 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21261 = _T_21260 | _T_21006; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21007 = _T_21631 ? bht_bank_rd_data_out_0_112 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21262 = _T_21261 | _T_21007; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21008 = _T_21633 ? bht_bank_rd_data_out_0_113 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21263 = _T_21262 | _T_21008; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21009 = _T_21635 ? bht_bank_rd_data_out_0_114 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21264 = _T_21263 | _T_21009; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21010 = _T_21637 ? bht_bank_rd_data_out_0_115 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21265 = _T_21264 | _T_21010; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21011 = _T_21639 ? bht_bank_rd_data_out_0_116 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21266 = _T_21265 | _T_21011; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21012 = _T_21641 ? bht_bank_rd_data_out_0_117 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21267 = _T_21266 | _T_21012; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21013 = _T_21643 ? bht_bank_rd_data_out_0_118 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21268 = _T_21267 | _T_21013; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21014 = _T_21645 ? bht_bank_rd_data_out_0_119 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21269 = _T_21268 | _T_21014; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21015 = _T_21647 ? bht_bank_rd_data_out_0_120 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21270 = _T_21269 | _T_21015; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21016 = _T_21649 ? bht_bank_rd_data_out_0_121 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21271 = _T_21270 | _T_21016; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21017 = _T_21651 ? bht_bank_rd_data_out_0_122 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21272 = _T_21271 | _T_21017; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21018 = _T_21653 ? bht_bank_rd_data_out_0_123 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21273 = _T_21272 | _T_21018; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21019 = _T_21655 ? bht_bank_rd_data_out_0_124 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21274 = _T_21273 | _T_21019; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21020 = _T_21657 ? bht_bank_rd_data_out_0_125 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21275 = _T_21274 | _T_21020; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21021 = _T_21659 ? bht_bank_rd_data_out_0_126 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21276 = _T_21275 | _T_21021; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21022 = _T_21661 ? bht_bank_rd_data_out_0_127 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21277 = _T_21276 | _T_21022; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21023 = _T_21663 ? bht_bank_rd_data_out_0_128 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21278 = _T_21277 | _T_21023; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21024 = _T_21665 ? bht_bank_rd_data_out_0_129 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21279 = _T_21278 | _T_21024; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21025 = _T_21667 ? bht_bank_rd_data_out_0_130 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21280 = _T_21279 | _T_21025; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21026 = _T_21669 ? bht_bank_rd_data_out_0_131 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21281 = _T_21280 | _T_21026; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21027 = _T_21671 ? bht_bank_rd_data_out_0_132 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21282 = _T_21281 | _T_21027; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21028 = _T_21673 ? bht_bank_rd_data_out_0_133 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21283 = _T_21282 | _T_21028; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21029 = _T_21675 ? bht_bank_rd_data_out_0_134 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21284 = _T_21283 | _T_21029; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21030 = _T_21677 ? bht_bank_rd_data_out_0_135 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21285 = _T_21284 | _T_21030; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21031 = _T_21679 ? bht_bank_rd_data_out_0_136 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21286 = _T_21285 | _T_21031; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21032 = _T_21681 ? bht_bank_rd_data_out_0_137 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21287 = _T_21286 | _T_21032; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21033 = _T_21683 ? bht_bank_rd_data_out_0_138 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21288 = _T_21287 | _T_21033; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21034 = _T_21685 ? bht_bank_rd_data_out_0_139 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21289 = _T_21288 | _T_21034; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21035 = _T_21687 ? bht_bank_rd_data_out_0_140 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21290 = _T_21289 | _T_21035; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21036 = _T_21689 ? bht_bank_rd_data_out_0_141 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21291 = _T_21290 | _T_21036; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21037 = _T_21691 ? bht_bank_rd_data_out_0_142 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21292 = _T_21291 | _T_21037; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21038 = _T_21693 ? bht_bank_rd_data_out_0_143 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21293 = _T_21292 | _T_21038; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21039 = _T_21695 ? bht_bank_rd_data_out_0_144 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21294 = _T_21293 | _T_21039; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21040 = _T_21697 ? bht_bank_rd_data_out_0_145 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21295 = _T_21294 | _T_21040; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21041 = _T_21699 ? bht_bank_rd_data_out_0_146 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21296 = _T_21295 | _T_21041; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21042 = _T_21701 ? bht_bank_rd_data_out_0_147 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21297 = _T_21296 | _T_21042; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21043 = _T_21703 ? bht_bank_rd_data_out_0_148 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21298 = _T_21297 | _T_21043; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21044 = _T_21705 ? bht_bank_rd_data_out_0_149 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21299 = _T_21298 | _T_21044; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21045 = _T_21707 ? bht_bank_rd_data_out_0_150 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21300 = _T_21299 | _T_21045; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21046 = _T_21709 ? bht_bank_rd_data_out_0_151 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21301 = _T_21300 | _T_21046; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21047 = _T_21711 ? bht_bank_rd_data_out_0_152 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21302 = _T_21301 | _T_21047; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21048 = _T_21713 ? bht_bank_rd_data_out_0_153 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21303 = _T_21302 | _T_21048; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21049 = _T_21715 ? bht_bank_rd_data_out_0_154 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21304 = _T_21303 | _T_21049; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21050 = _T_21717 ? bht_bank_rd_data_out_0_155 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21305 = _T_21304 | _T_21050; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21051 = _T_21719 ? bht_bank_rd_data_out_0_156 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21306 = _T_21305 | _T_21051; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21052 = _T_21721 ? bht_bank_rd_data_out_0_157 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21307 = _T_21306 | _T_21052; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21053 = _T_21723 ? bht_bank_rd_data_out_0_158 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21308 = _T_21307 | _T_21053; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21054 = _T_21725 ? bht_bank_rd_data_out_0_159 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21309 = _T_21308 | _T_21054; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21055 = _T_21727 ? bht_bank_rd_data_out_0_160 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21310 = _T_21309 | _T_21055; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21056 = _T_21729 ? bht_bank_rd_data_out_0_161 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21311 = _T_21310 | _T_21056; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21057 = _T_21731 ? bht_bank_rd_data_out_0_162 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21312 = _T_21311 | _T_21057; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21058 = _T_21733 ? bht_bank_rd_data_out_0_163 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21313 = _T_21312 | _T_21058; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21059 = _T_21735 ? bht_bank_rd_data_out_0_164 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21314 = _T_21313 | _T_21059; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21060 = _T_21737 ? bht_bank_rd_data_out_0_165 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21315 = _T_21314 | _T_21060; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21061 = _T_21739 ? bht_bank_rd_data_out_0_166 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21316 = _T_21315 | _T_21061; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21062 = _T_21741 ? bht_bank_rd_data_out_0_167 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21317 = _T_21316 | _T_21062; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21063 = _T_21743 ? bht_bank_rd_data_out_0_168 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21318 = _T_21317 | _T_21063; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21064 = _T_21745 ? bht_bank_rd_data_out_0_169 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21319 = _T_21318 | _T_21064; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21065 = _T_21747 ? bht_bank_rd_data_out_0_170 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21320 = _T_21319 | _T_21065; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21066 = _T_21749 ? bht_bank_rd_data_out_0_171 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21321 = _T_21320 | _T_21066; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21067 = _T_21751 ? bht_bank_rd_data_out_0_172 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21322 = _T_21321 | _T_21067; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21068 = _T_21753 ? bht_bank_rd_data_out_0_173 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21323 = _T_21322 | _T_21068; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21069 = _T_21755 ? bht_bank_rd_data_out_0_174 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21324 = _T_21323 | _T_21069; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21070 = _T_21757 ? bht_bank_rd_data_out_0_175 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21325 = _T_21324 | _T_21070; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21071 = _T_21759 ? bht_bank_rd_data_out_0_176 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21326 = _T_21325 | _T_21071; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21072 = _T_21761 ? bht_bank_rd_data_out_0_177 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21327 = _T_21326 | _T_21072; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21073 = _T_21763 ? bht_bank_rd_data_out_0_178 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21328 = _T_21327 | _T_21073; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21074 = _T_21765 ? bht_bank_rd_data_out_0_179 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21329 = _T_21328 | _T_21074; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21075 = _T_21767 ? bht_bank_rd_data_out_0_180 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21330 = _T_21329 | _T_21075; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21076 = _T_21769 ? bht_bank_rd_data_out_0_181 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21331 = _T_21330 | _T_21076; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21077 = _T_21771 ? bht_bank_rd_data_out_0_182 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21332 = _T_21331 | _T_21077; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21078 = _T_21773 ? bht_bank_rd_data_out_0_183 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21333 = _T_21332 | _T_21078; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21079 = _T_21775 ? bht_bank_rd_data_out_0_184 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21334 = _T_21333 | _T_21079; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21080 = _T_21777 ? bht_bank_rd_data_out_0_185 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21335 = _T_21334 | _T_21080; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21081 = _T_21779 ? bht_bank_rd_data_out_0_186 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21336 = _T_21335 | _T_21081; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21082 = _T_21781 ? bht_bank_rd_data_out_0_187 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21337 = _T_21336 | _T_21082; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21083 = _T_21783 ? bht_bank_rd_data_out_0_188 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21338 = _T_21337 | _T_21083; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21084 = _T_21785 ? bht_bank_rd_data_out_0_189 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21339 = _T_21338 | _T_21084; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21085 = _T_21787 ? bht_bank_rd_data_out_0_190 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21340 = _T_21339 | _T_21085; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21086 = _T_21789 ? bht_bank_rd_data_out_0_191 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21341 = _T_21340 | _T_21086; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21087 = _T_21791 ? bht_bank_rd_data_out_0_192 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21342 = _T_21341 | _T_21087; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21088 = _T_21793 ? bht_bank_rd_data_out_0_193 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21343 = _T_21342 | _T_21088; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21089 = _T_21795 ? bht_bank_rd_data_out_0_194 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21344 = _T_21343 | _T_21089; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21090 = _T_21797 ? bht_bank_rd_data_out_0_195 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21345 = _T_21344 | _T_21090; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21091 = _T_21799 ? bht_bank_rd_data_out_0_196 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21346 = _T_21345 | _T_21091; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21092 = _T_21801 ? bht_bank_rd_data_out_0_197 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21347 = _T_21346 | _T_21092; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21093 = _T_21803 ? bht_bank_rd_data_out_0_198 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21348 = _T_21347 | _T_21093; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21094 = _T_21805 ? bht_bank_rd_data_out_0_199 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21349 = _T_21348 | _T_21094; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21095 = _T_21807 ? bht_bank_rd_data_out_0_200 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21350 = _T_21349 | _T_21095; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21096 = _T_21809 ? bht_bank_rd_data_out_0_201 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21351 = _T_21350 | _T_21096; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21097 = _T_21811 ? bht_bank_rd_data_out_0_202 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21352 = _T_21351 | _T_21097; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21098 = _T_21813 ? bht_bank_rd_data_out_0_203 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21353 = _T_21352 | _T_21098; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21099 = _T_21815 ? bht_bank_rd_data_out_0_204 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21354 = _T_21353 | _T_21099; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21100 = _T_21817 ? bht_bank_rd_data_out_0_205 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21355 = _T_21354 | _T_21100; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21101 = _T_21819 ? bht_bank_rd_data_out_0_206 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21356 = _T_21355 | _T_21101; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21102 = _T_21821 ? bht_bank_rd_data_out_0_207 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21357 = _T_21356 | _T_21102; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21103 = _T_21823 ? bht_bank_rd_data_out_0_208 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21358 = _T_21357 | _T_21103; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21104 = _T_21825 ? bht_bank_rd_data_out_0_209 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21359 = _T_21358 | _T_21104; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21105 = _T_21827 ? bht_bank_rd_data_out_0_210 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21360 = _T_21359 | _T_21105; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21106 = _T_21829 ? bht_bank_rd_data_out_0_211 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21361 = _T_21360 | _T_21106; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21107 = _T_21831 ? bht_bank_rd_data_out_0_212 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21362 = _T_21361 | _T_21107; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21108 = _T_21833 ? bht_bank_rd_data_out_0_213 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21363 = _T_21362 | _T_21108; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21109 = _T_21835 ? bht_bank_rd_data_out_0_214 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21364 = _T_21363 | _T_21109; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21110 = _T_21837 ? bht_bank_rd_data_out_0_215 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21365 = _T_21364 | _T_21110; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21111 = _T_21839 ? bht_bank_rd_data_out_0_216 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21366 = _T_21365 | _T_21111; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21112 = _T_21841 ? bht_bank_rd_data_out_0_217 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21367 = _T_21366 | _T_21112; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21113 = _T_21843 ? bht_bank_rd_data_out_0_218 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21368 = _T_21367 | _T_21113; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21114 = _T_21845 ? bht_bank_rd_data_out_0_219 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21369 = _T_21368 | _T_21114; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21115 = _T_21847 ? bht_bank_rd_data_out_0_220 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21370 = _T_21369 | _T_21115; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21116 = _T_21849 ? bht_bank_rd_data_out_0_221 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21371 = _T_21370 | _T_21116; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21117 = _T_21851 ? bht_bank_rd_data_out_0_222 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21372 = _T_21371 | _T_21117; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21118 = _T_21853 ? bht_bank_rd_data_out_0_223 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21373 = _T_21372 | _T_21118; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21119 = _T_21855 ? bht_bank_rd_data_out_0_224 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21374 = _T_21373 | _T_21119; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21120 = _T_21857 ? bht_bank_rd_data_out_0_225 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21375 = _T_21374 | _T_21120; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21121 = _T_21859 ? bht_bank_rd_data_out_0_226 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21376 = _T_21375 | _T_21121; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21122 = _T_21861 ? bht_bank_rd_data_out_0_227 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21377 = _T_21376 | _T_21122; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21123 = _T_21863 ? bht_bank_rd_data_out_0_228 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21378 = _T_21377 | _T_21123; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21124 = _T_21865 ? bht_bank_rd_data_out_0_229 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21379 = _T_21378 | _T_21124; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21125 = _T_21867 ? bht_bank_rd_data_out_0_230 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21380 = _T_21379 | _T_21125; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21126 = _T_21869 ? bht_bank_rd_data_out_0_231 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21381 = _T_21380 | _T_21126; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21127 = _T_21871 ? bht_bank_rd_data_out_0_232 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21382 = _T_21381 | _T_21127; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21128 = _T_21873 ? bht_bank_rd_data_out_0_233 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21383 = _T_21382 | _T_21128; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21129 = _T_21875 ? bht_bank_rd_data_out_0_234 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21384 = _T_21383 | _T_21129; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21130 = _T_21877 ? bht_bank_rd_data_out_0_235 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21385 = _T_21384 | _T_21130; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21131 = _T_21879 ? bht_bank_rd_data_out_0_236 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21386 = _T_21385 | _T_21131; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21132 = _T_21881 ? bht_bank_rd_data_out_0_237 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21387 = _T_21386 | _T_21132; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21133 = _T_21883 ? bht_bank_rd_data_out_0_238 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21388 = _T_21387 | _T_21133; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21134 = _T_21885 ? bht_bank_rd_data_out_0_239 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21389 = _T_21388 | _T_21134; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21135 = _T_21887 ? bht_bank_rd_data_out_0_240 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21390 = _T_21389 | _T_21135; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21136 = _T_21889 ? bht_bank_rd_data_out_0_241 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21391 = _T_21390 | _T_21136; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21137 = _T_21891 ? bht_bank_rd_data_out_0_242 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21392 = _T_21391 | _T_21137; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21138 = _T_21893 ? bht_bank_rd_data_out_0_243 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21393 = _T_21392 | _T_21138; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21139 = _T_21895 ? bht_bank_rd_data_out_0_244 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21394 = _T_21393 | _T_21139; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21140 = _T_21897 ? bht_bank_rd_data_out_0_245 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21395 = _T_21394 | _T_21140; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21141 = _T_21899 ? bht_bank_rd_data_out_0_246 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21396 = _T_21395 | _T_21141; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21142 = _T_21901 ? bht_bank_rd_data_out_0_247 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21397 = _T_21396 | _T_21142; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21143 = _T_21903 ? bht_bank_rd_data_out_0_248 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21398 = _T_21397 | _T_21143; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21144 = _T_21905 ? bht_bank_rd_data_out_0_249 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21399 = _T_21398 | _T_21144; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21145 = _T_21907 ? bht_bank_rd_data_out_0_250 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21400 = _T_21399 | _T_21145; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21146 = _T_21909 ? bht_bank_rd_data_out_0_251 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21401 = _T_21400 | _T_21146; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21147 = _T_21911 ? bht_bank_rd_data_out_0_252 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21402 = _T_21401 | _T_21147; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21148 = _T_21913 ? bht_bank_rd_data_out_0_253 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21403 = _T_21402 | _T_21148; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21149 = _T_21915 ? bht_bank_rd_data_out_0_254 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21404 = _T_21403 | _T_21149; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21150 = _T_21917 ? bht_bank_rd_data_out_0_255 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] bht_bank0_rd_data_f = _T_21404 | _T_21150; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_251 = _T_143 ? bht_bank0_rd_data_f : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_252 = io_ifc_fetch_addr_f[0] ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] bht_vbank0_rd_data_f = _T_251 | _T_252; // @[Mux.scala 27:72]
|
|
wire _T_269 = bht_force_taken_f[0] | bht_vbank0_rd_data_f[1]; // @[el2_ifu_bp_ctl.scala 294:45]
|
|
wire _T_271 = _T_269 & vwayhit_f[0]; // @[el2_ifu_bp_ctl.scala 294:72]
|
|
wire [1:0] bht_dir_f = {_T_266,_T_271}; // @[Cat.scala 29:58]
|
|
wire _T_14 = ~bht_dir_f[0]; // @[el2_ifu_bp_ctl.scala 108:23]
|
|
wire [1:0] btb_sel_f = {_T_14,bht_dir_f[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] fetch_start_f = {io_ifc_fetch_addr_f[0],_T_143}; // @[Cat.scala 29:58]
|
|
wire _T_32 = io_exu_mp_btag == fetch_rd_tag_f; // @[el2_ifu_bp_ctl.scala 126:46]
|
|
wire _T_33 = _T_32 & exu_mp_valid; // @[el2_ifu_bp_ctl.scala 126:66]
|
|
wire _T_34 = _T_33 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 126:81]
|
|
wire _T_35 = io_exu_mp_index == btb_rd_addr_f; // @[el2_ifu_bp_ctl.scala 126:117]
|
|
wire fetch_mp_collision_f = _T_34 & _T_35; // @[el2_ifu_bp_ctl.scala 126:102]
|
|
wire _T_36 = io_exu_mp_btag == fetch_rd_tag_p1_f; // @[el2_ifu_bp_ctl.scala 127:49]
|
|
wire _T_37 = _T_36 & exu_mp_valid; // @[el2_ifu_bp_ctl.scala 127:72]
|
|
wire _T_38 = _T_37 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 127:87]
|
|
wire _T_39 = io_exu_mp_index == btb_rd_addr_p1_f; // @[el2_ifu_bp_ctl.scala 127:123]
|
|
wire fetch_mp_collision_p1_f = _T_38 & _T_39; // @[el2_ifu_bp_ctl.scala 127:108]
|
|
reg exu_mp_way_f; // @[el2_ifu_bp_ctl.scala 131:55]
|
|
reg exu_flush_final_d1; // @[el2_ifu_bp_ctl.scala 132:61]
|
|
wire [255:0] mp_wrindex_dec = 256'h1 << io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 203:28]
|
|
wire [255:0] fetch_wrindex_dec = 256'h1 << btb_rd_addr_f; // @[el2_ifu_bp_ctl.scala 206:31]
|
|
wire [255:0] fetch_wrindex_p1_dec = 256'h1 << btb_rd_addr_p1_f; // @[el2_ifu_bp_ctl.scala 209:34]
|
|
wire [255:0] _T_149 = exu_mp_valid ? 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff : 256'h0; // @[Bitwise.scala 72:12]
|
|
wire [255:0] mp_wrlru_b0 = mp_wrindex_dec & _T_149; // @[el2_ifu_bp_ctl.scala 212:36]
|
|
wire _T_165 = vwayhit_f[0] | vwayhit_f[1]; // @[el2_ifu_bp_ctl.scala 218:42]
|
|
wire _T_166 = _T_165 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 218:58]
|
|
wire lru_update_valid_f = _T_166 & _T; // @[el2_ifu_bp_ctl.scala 218:79]
|
|
wire [255:0] _T_169 = lru_update_valid_f ? 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff : 256'h0; // @[Bitwise.scala 72:12]
|
|
wire [255:0] fetch_wrlru_b0 = fetch_wrindex_dec & _T_169; // @[el2_ifu_bp_ctl.scala 220:42]
|
|
wire [255:0] fetch_wrlru_p1_b0 = fetch_wrindex_p1_dec & _T_169; // @[el2_ifu_bp_ctl.scala 221:48]
|
|
wire [255:0] _T_172 = ~mp_wrlru_b0; // @[el2_ifu_bp_ctl.scala 223:25]
|
|
wire [255:0] _T_173 = ~fetch_wrlru_b0; // @[el2_ifu_bp_ctl.scala 223:40]
|
|
wire [255:0] btb_lru_b0_hold = _T_172 & _T_173; // @[el2_ifu_bp_ctl.scala 223:38]
|
|
wire _T_175 = ~io_exu_mp_pkt_bits_way; // @[el2_ifu_bp_ctl.scala 230:40]
|
|
wire [255:0] _T_178 = _T_175 ? mp_wrlru_b0 : 256'h0; // @[Mux.scala 27:72]
|
|
wire [255:0] _T_179 = tag_match_way0_f ? fetch_wrlru_b0 : 256'h0; // @[Mux.scala 27:72]
|
|
wire [255:0] _T_180 = tag_match_way0_p1_f ? fetch_wrlru_p1_b0 : 256'h0; // @[Mux.scala 27:72]
|
|
wire [255:0] _T_181 = _T_178 | _T_179; // @[Mux.scala 27:72]
|
|
wire [255:0] _T_182 = _T_181 | _T_180; // @[Mux.scala 27:72]
|
|
reg [255:0] btb_lru_b0_f; // @[el2_lib.scala 514:16]
|
|
wire [255:0] _T_184 = btb_lru_b0_hold & btb_lru_b0_f; // @[el2_ifu_bp_ctl.scala 232:102]
|
|
wire [255:0] _T_186 = fetch_wrindex_dec & btb_lru_b0_f; // @[el2_ifu_bp_ctl.scala 235:78]
|
|
wire _T_187 = |_T_186; // @[el2_ifu_bp_ctl.scala 235:94]
|
|
wire btb_lru_rd_f = fetch_mp_collision_f ? exu_mp_way_f : _T_187; // @[el2_ifu_bp_ctl.scala 235:25]
|
|
wire [255:0] _T_189 = fetch_wrindex_p1_dec & btb_lru_b0_f; // @[el2_ifu_bp_ctl.scala 237:87]
|
|
wire _T_190 = |_T_189; // @[el2_ifu_bp_ctl.scala 237:103]
|
|
wire btb_lru_rd_p1_f = fetch_mp_collision_p1_f ? exu_mp_way_f : _T_190; // @[el2_ifu_bp_ctl.scala 237:28]
|
|
wire [1:0] _T_193 = {btb_lru_rd_f,btb_lru_rd_f}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_196 = {btb_lru_rd_p1_f,btb_lru_rd_f}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_197 = _T_143 ? _T_193 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_198 = io_ifc_fetch_addr_f[0] ? _T_196 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] btb_vlru_rd_f = _T_197 | _T_198; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_207 = {tag_match_way1_expanded_p1_f[0],tag_match_way1_expanded_f[1]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_208 = _T_143 ? tag_match_way1_expanded_f : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_209 = io_ifc_fetch_addr_f[0] ? _T_207 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] tag_match_vway1_expanded_f = _T_208 | _T_209; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_211 = ~vwayhit_f; // @[el2_ifu_bp_ctl.scala 247:52]
|
|
wire [1:0] _T_212 = _T_211 & btb_vlru_rd_f; // @[el2_ifu_bp_ctl.scala 247:63]
|
|
wire [15:0] _T_229 = btb_sel_f[1] ? btb_vbank1_rd_data_f[16:1] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_230 = btb_sel_f[0] ? btb_vbank0_rd_data_f[16:1] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] btb_sel_data_f = _T_229 | _T_230; // @[Mux.scala 27:72]
|
|
wire [11:0] btb_rd_tgt_f = btb_sel_data_f[15:4]; // @[el2_ifu_bp_ctl.scala 263:36]
|
|
wire btb_rd_pc4_f = btb_sel_data_f[3]; // @[el2_ifu_bp_ctl.scala 264:36]
|
|
wire btb_rd_call_f = btb_sel_data_f[1]; // @[el2_ifu_bp_ctl.scala 265:37]
|
|
wire btb_rd_ret_f = btb_sel_data_f[0]; // @[el2_ifu_bp_ctl.scala 266:36]
|
|
wire [1:0] _T_279 = {bht_vbank1_rd_data_f[1],bht_vbank0_rd_data_f[1]}; // @[Cat.scala 29:58]
|
|
wire [1:0] hist1_raw = bht_force_taken_f | _T_279; // @[el2_ifu_bp_ctl.scala 300:34]
|
|
wire [1:0] _T_233 = vwayhit_f & hist1_raw; // @[el2_ifu_bp_ctl.scala 273:39]
|
|
wire _T_234 = |_T_233; // @[el2_ifu_bp_ctl.scala 273:52]
|
|
wire _T_235 = _T_234 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 273:56]
|
|
wire _T_236 = ~leak_one_f_d1; // @[el2_ifu_bp_ctl.scala 273:79]
|
|
wire _T_237 = _T_235 & _T_236; // @[el2_ifu_bp_ctl.scala 273:77]
|
|
wire _T_238 = ~io_dec_tlu_bpred_disable; // @[el2_ifu_bp_ctl.scala 273:96]
|
|
wire _T_274 = io_ifu_bp_hit_taken_f & btb_sel_f[1]; // @[el2_ifu_bp_ctl.scala 297:51]
|
|
wire _T_275 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_bp_ctl.scala 297:69]
|
|
wire _T_285 = vwayhit_f[1] & btb_vbank1_rd_data_f[4]; // @[el2_ifu_bp_ctl.scala 306:34]
|
|
wire _T_288 = vwayhit_f[0] & btb_vbank0_rd_data_f[4]; // @[el2_ifu_bp_ctl.scala 307:34]
|
|
wire _T_291 = ~btb_vbank1_rd_data_f[2]; // @[el2_ifu_bp_ctl.scala 310:37]
|
|
wire _T_292 = vwayhit_f[1] & _T_291; // @[el2_ifu_bp_ctl.scala 310:35]
|
|
wire _T_294 = _T_292 & btb_vbank1_rd_data_f[1]; // @[el2_ifu_bp_ctl.scala 310:65]
|
|
wire _T_297 = ~btb_vbank0_rd_data_f[2]; // @[el2_ifu_bp_ctl.scala 311:37]
|
|
wire _T_298 = vwayhit_f[0] & _T_297; // @[el2_ifu_bp_ctl.scala 311:35]
|
|
wire _T_300 = _T_298 & btb_vbank0_rd_data_f[1]; // @[el2_ifu_bp_ctl.scala 311:65]
|
|
wire [1:0] num_valids = vwayhit_f[1] + vwayhit_f[0]; // @[el2_ifu_bp_ctl.scala 314:35]
|
|
wire [1:0] _T_303 = btb_sel_f & bht_dir_f; // @[el2_ifu_bp_ctl.scala 317:28]
|
|
wire final_h = |_T_303; // @[el2_ifu_bp_ctl.scala 317:41]
|
|
wire _T_304 = num_valids == 2'h2; // @[el2_ifu_bp_ctl.scala 321:41]
|
|
wire [7:0] _T_308 = {fghr[5:0],1'h0,final_h}; // @[Cat.scala 29:58]
|
|
wire _T_309 = num_valids == 2'h1; // @[el2_ifu_bp_ctl.scala 322:41]
|
|
wire [7:0] _T_312 = {fghr[6:0],final_h}; // @[Cat.scala 29:58]
|
|
wire _T_313 = num_valids == 2'h0; // @[el2_ifu_bp_ctl.scala 323:41]
|
|
wire [7:0] _T_316 = _T_304 ? _T_308 : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_317 = _T_309 ? _T_312 : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_318 = _T_313 ? fghr : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_319 = _T_316 | _T_317; // @[Mux.scala 27:72]
|
|
wire [7:0] merged_ghr = _T_319 | _T_318; // @[Mux.scala 27:72]
|
|
wire _T_322 = ~exu_flush_final_d1; // @[el2_ifu_bp_ctl.scala 332:27]
|
|
wire _T_323 = _T_322 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 332:47]
|
|
wire _T_324 = _T_323 & io_ic_hit_f; // @[el2_ifu_bp_ctl.scala 332:70]
|
|
wire _T_326 = _T_324 & _T_236; // @[el2_ifu_bp_ctl.scala 332:84]
|
|
wire _T_329 = io_ifc_fetch_req_f & io_ic_hit_f; // @[el2_ifu_bp_ctl.scala 333:70]
|
|
wire _T_331 = _T_329 & _T_236; // @[el2_ifu_bp_ctl.scala 333:84]
|
|
wire _T_332 = ~_T_331; // @[el2_ifu_bp_ctl.scala 333:49]
|
|
wire _T_333 = _T_322 & _T_332; // @[el2_ifu_bp_ctl.scala 333:47]
|
|
wire [7:0] _T_335 = exu_flush_final_d1 ? io_exu_mp_fghr : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_336 = _T_326 ? merged_ghr : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_337 = _T_333 ? fghr : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_338 = _T_335 | _T_336; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_343 = io_dec_tlu_bpred_disable ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_344 = ~_T_343; // @[el2_ifu_bp_ctl.scala 342:36]
|
|
wire _T_348 = ~fetch_start_f[0]; // @[el2_ifu_bp_ctl.scala 346:36]
|
|
wire _T_349 = bht_dir_f[0] & _T_348; // @[el2_ifu_bp_ctl.scala 346:34]
|
|
wire _T_353 = _T_14 & fetch_start_f[0]; // @[el2_ifu_bp_ctl.scala 346:72]
|
|
wire _T_354 = _T_349 | _T_353; // @[el2_ifu_bp_ctl.scala 346:55]
|
|
wire _T_357 = bht_dir_f[0] & fetch_start_f[0]; // @[el2_ifu_bp_ctl.scala 347:34]
|
|
wire _T_362 = _T_14 & _T_348; // @[el2_ifu_bp_ctl.scala 347:71]
|
|
wire _T_363 = _T_357 | _T_362; // @[el2_ifu_bp_ctl.scala 347:54]
|
|
wire [1:0] bloc_f = {_T_354,_T_363}; // @[Cat.scala 29:58]
|
|
wire _T_367 = _T_14 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_bp_ctl.scala 349:35]
|
|
wire _T_368 = ~btb_rd_pc4_f; // @[el2_ifu_bp_ctl.scala 349:62]
|
|
wire use_fa_plus = _T_367 & _T_368; // @[el2_ifu_bp_ctl.scala 349:60]
|
|
wire _T_371 = fetch_start_f[0] & btb_sel_f[0]; // @[el2_ifu_bp_ctl.scala 351:44]
|
|
wire btb_fg_crossing_f = _T_371 & btb_rd_pc4_f; // @[el2_ifu_bp_ctl.scala 351:59]
|
|
wire bp_total_branch_offset_f = bloc_f[1] ^ btb_rd_pc4_f; // @[el2_ifu_bp_ctl.scala 352:43]
|
|
wire _T_375 = io_ifc_fetch_req_f & _T_275; // @[el2_ifu_bp_ctl.scala 354:85]
|
|
reg [29:0] ifc_fetch_adder_prior; // @[el2_lib.scala 514:16]
|
|
wire _T_380 = ~btb_fg_crossing_f; // @[el2_ifu_bp_ctl.scala 360:32]
|
|
wire _T_381 = ~use_fa_plus; // @[el2_ifu_bp_ctl.scala 360:53]
|
|
wire _T_382 = _T_380 & _T_381; // @[el2_ifu_bp_ctl.scala 360:51]
|
|
wire [29:0] _T_385 = use_fa_plus ? fetch_addr_p1_f : 30'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_386 = btb_fg_crossing_f ? ifc_fetch_adder_prior : 30'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_387 = _T_382 ? io_ifc_fetch_addr_f[30:1] : 30'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_388 = _T_385 | _T_386; // @[Mux.scala 27:72]
|
|
wire [29:0] adder_pc_in_f = _T_388 | _T_387; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_392 = {adder_pc_in_f,bp_total_branch_offset_f,1'h0}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_393 = {btb_rd_tgt_f,1'h0}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_396 = _T_392[12:1] + _T_393[12:1]; // @[el2_lib.scala 208:31]
|
|
wire [18:0] _T_399 = _T_392[31:13] + 19'h1; // @[el2_lib.scala 209:27]
|
|
wire [18:0] _T_402 = _T_392[31:13] - 19'h1; // @[el2_lib.scala 210:27]
|
|
wire _T_405 = ~_T_396[12]; // @[el2_lib.scala 212:28]
|
|
wire _T_406 = _T_393[12] ^ _T_405; // @[el2_lib.scala 212:26]
|
|
wire _T_409 = ~_T_393[12]; // @[el2_lib.scala 213:20]
|
|
wire _T_411 = _T_409 & _T_396[12]; // @[el2_lib.scala 213:26]
|
|
wire _T_415 = _T_393[12] & _T_405; // @[el2_lib.scala 214:26]
|
|
wire [18:0] _T_417 = _T_406 ? _T_392[31:13] : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_418 = _T_411 ? _T_399 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_419 = _T_415 ? _T_402 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_420 = _T_417 | _T_418; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_421 = _T_420 | _T_419; // @[Mux.scala 27:72]
|
|
wire [31:0] bp_btb_target_adder_f = {_T_421,_T_396[11:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_425 = ~btb_rd_call_f; // @[el2_ifu_bp_ctl.scala 369:49]
|
|
wire _T_426 = btb_rd_ret_f & _T_425; // @[el2_ifu_bp_ctl.scala 369:47]
|
|
reg [31:0] rets_out_0; // @[el2_lib.scala 514:16]
|
|
wire _T_428 = _T_426 & rets_out_0[0]; // @[el2_ifu_bp_ctl.scala 369:64]
|
|
wire [12:0] _T_439 = {11'h0,_T_368,1'h0}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_442 = _T_392[12:1] + _T_439[12:1]; // @[el2_lib.scala 208:31]
|
|
wire _T_451 = ~_T_442[12]; // @[el2_lib.scala 212:28]
|
|
wire _T_452 = _T_439[12] ^ _T_451; // @[el2_lib.scala 212:26]
|
|
wire _T_455 = ~_T_439[12]; // @[el2_lib.scala 213:20]
|
|
wire _T_457 = _T_455 & _T_442[12]; // @[el2_lib.scala 213:26]
|
|
wire _T_461 = _T_439[12] & _T_451; // @[el2_lib.scala 214:26]
|
|
wire [18:0] _T_463 = _T_452 ? _T_392[31:13] : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_464 = _T_457 ? _T_399 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_465 = _T_461 ? _T_402 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_466 = _T_463 | _T_464; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_467 = _T_466 | _T_465; // @[Mux.scala 27:72]
|
|
wire [31:0] bp_rs_call_target_f = {_T_467,_T_442[11:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_471 = ~btb_rd_ret_f; // @[el2_ifu_bp_ctl.scala 375:33]
|
|
wire _T_472 = btb_rd_call_f & _T_471; // @[el2_ifu_bp_ctl.scala 375:31]
|
|
wire rs_push = _T_472 & io_ifu_bp_hit_taken_f; // @[el2_ifu_bp_ctl.scala 375:47]
|
|
wire rs_pop = _T_426 & io_ifu_bp_hit_taken_f; // @[el2_ifu_bp_ctl.scala 376:46]
|
|
wire _T_475 = ~rs_push; // @[el2_ifu_bp_ctl.scala 377:17]
|
|
wire _T_476 = ~rs_pop; // @[el2_ifu_bp_ctl.scala 377:28]
|
|
wire rs_hold = _T_475 & _T_476; // @[el2_ifu_bp_ctl.scala 377:26]
|
|
wire [31:0] _T_479 = {bp_rs_call_target_f[31:1],1'h1}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_481 = rs_push ? _T_479 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_1; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_482 = rs_pop ? rets_out_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_486 = rs_push ? rets_out_0 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_2; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_487 = rs_pop ? rets_out_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_491 = rs_push ? rets_out_1 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_3; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_492 = rs_pop ? rets_out_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_496 = rs_push ? rets_out_2 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_4; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_497 = rs_pop ? rets_out_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_501 = rs_push ? rets_out_3 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_5; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_502 = rs_pop ? rets_out_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_506 = rs_push ? rets_out_4 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_6; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_507 = rs_pop ? rets_out_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_511 = rs_push ? rets_out_5 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_7; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_512 = rs_pop ? rets_out_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_530 = ~dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 392:35]
|
|
wire btb_valid = exu_mp_valid & _T_530; // @[el2_ifu_bp_ctl.scala 392:32]
|
|
wire _T_531 = io_exu_mp_pkt_bits_pcall | io_exu_mp_pkt_bits_pja; // @[el2_ifu_bp_ctl.scala 396:89]
|
|
wire _T_532 = io_exu_mp_pkt_bits_pret | io_exu_mp_pkt_bits_pja; // @[el2_ifu_bp_ctl.scala 396:113]
|
|
wire [2:0] _T_534 = {_T_531,_T_532,btb_valid}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_537 = {io_exu_mp_btag,io_exu_mp_pkt_bits_toffset,io_exu_mp_pkt_bits_pc4,io_exu_mp_pkt_bits_boffset}; // @[Cat.scala 29:58]
|
|
wire exu_mp_valid_write = exu_mp_valid & io_exu_mp_pkt_bits_ataken; // @[el2_ifu_bp_ctl.scala 397:41]
|
|
wire _T_539 = _T_175 & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 400:39]
|
|
wire _T_541 = _T_539 & _T_530; // @[el2_ifu_bp_ctl.scala 400:60]
|
|
wire _T_542 = ~io_dec_tlu_br0_r_pkt_way; // @[el2_ifu_bp_ctl.scala 400:87]
|
|
wire _T_543 = _T_542 & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 400:104]
|
|
wire btb_wr_en_way0 = _T_541 | _T_543; // @[el2_ifu_bp_ctl.scala 400:83]
|
|
wire _T_544 = io_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 401:36]
|
|
wire _T_546 = _T_544 & _T_530; // @[el2_ifu_bp_ctl.scala 401:57]
|
|
wire _T_547 = io_dec_tlu_br0_r_pkt_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98]
|
|
wire btb_wr_en_way1 = _T_546 | _T_547; // @[el2_ifu_bp_ctl.scala 401:80]
|
|
wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_i0_br_index_r : io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 404:24]
|
|
wire middle_of_bank = io_exu_mp_pkt_bits_pc4 ^ io_exu_mp_pkt_bits_boffset; // @[el2_ifu_bp_ctl.scala 405:35]
|
|
wire _T_549 = ~io_exu_mp_pkt_bits_pcall; // @[el2_ifu_bp_ctl.scala 408:43]
|
|
wire _T_550 = exu_mp_valid & _T_549; // @[el2_ifu_bp_ctl.scala 408:41]
|
|
wire _T_551 = ~io_exu_mp_pkt_bits_pret; // @[el2_ifu_bp_ctl.scala 408:58]
|
|
wire _T_552 = _T_550 & _T_551; // @[el2_ifu_bp_ctl.scala 408:56]
|
|
wire _T_553 = ~io_exu_mp_pkt_bits_pja; // @[el2_ifu_bp_ctl.scala 408:72]
|
|
wire _T_554 = _T_552 & _T_553; // @[el2_ifu_bp_ctl.scala 408:70]
|
|
wire [1:0] _T_556 = _T_554 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_557 = ~middle_of_bank; // @[el2_ifu_bp_ctl.scala 408:106]
|
|
wire [1:0] _T_558 = {middle_of_bank,_T_557}; // @[Cat.scala 29:58]
|
|
wire [1:0] bht_wr_en0 = _T_556 & _T_558; // @[el2_ifu_bp_ctl.scala 408:84]
|
|
wire [1:0] _T_560 = io_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_561 = ~io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu_bp_ctl.scala 409:75]
|
|
wire [1:0] _T_562 = {io_dec_tlu_br0_r_pkt_middle,_T_561}; // @[Cat.scala 29:58]
|
|
wire [1:0] bht_wr_en2 = _T_560 & _T_562; // @[el2_ifu_bp_ctl.scala 409:46]
|
|
wire [9:0] _T_563 = {io_exu_mp_index,2'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] mp_hashed = _T_563[9:2] ^ io_exu_mp_eghr; // @[el2_lib.scala 196:35]
|
|
wire [9:0] _T_566 = {io_exu_i0_br_index_r,2'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] br0_hashed_wb = _T_566[9:2] ^ io_exu_i0_br_fghr_r; // @[el2_lib.scala 196:35]
|
|
wire _T_575 = btb_wr_addr == 8'h0; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_578 = btb_wr_addr == 8'h1; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_581 = btb_wr_addr == 8'h2; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_584 = btb_wr_addr == 8'h3; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_587 = btb_wr_addr == 8'h4; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_590 = btb_wr_addr == 8'h5; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_593 = btb_wr_addr == 8'h6; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_596 = btb_wr_addr == 8'h7; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_599 = btb_wr_addr == 8'h8; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_602 = btb_wr_addr == 8'h9; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_605 = btb_wr_addr == 8'ha; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_608 = btb_wr_addr == 8'hb; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_611 = btb_wr_addr == 8'hc; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_614 = btb_wr_addr == 8'hd; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_617 = btb_wr_addr == 8'he; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_620 = btb_wr_addr == 8'hf; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_623 = btb_wr_addr == 8'h10; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_626 = btb_wr_addr == 8'h11; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_629 = btb_wr_addr == 8'h12; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_632 = btb_wr_addr == 8'h13; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_635 = btb_wr_addr == 8'h14; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_638 = btb_wr_addr == 8'h15; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_641 = btb_wr_addr == 8'h16; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_644 = btb_wr_addr == 8'h17; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_647 = btb_wr_addr == 8'h18; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_650 = btb_wr_addr == 8'h19; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_653 = btb_wr_addr == 8'h1a; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_656 = btb_wr_addr == 8'h1b; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_659 = btb_wr_addr == 8'h1c; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_662 = btb_wr_addr == 8'h1d; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_665 = btb_wr_addr == 8'h1e; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_668 = btb_wr_addr == 8'h1f; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_671 = btb_wr_addr == 8'h20; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_674 = btb_wr_addr == 8'h21; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_677 = btb_wr_addr == 8'h22; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_680 = btb_wr_addr == 8'h23; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_683 = btb_wr_addr == 8'h24; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_686 = btb_wr_addr == 8'h25; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_689 = btb_wr_addr == 8'h26; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_692 = btb_wr_addr == 8'h27; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_695 = btb_wr_addr == 8'h28; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_698 = btb_wr_addr == 8'h29; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_701 = btb_wr_addr == 8'h2a; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_704 = btb_wr_addr == 8'h2b; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_707 = btb_wr_addr == 8'h2c; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_710 = btb_wr_addr == 8'h2d; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_713 = btb_wr_addr == 8'h2e; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_716 = btb_wr_addr == 8'h2f; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_719 = btb_wr_addr == 8'h30; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_722 = btb_wr_addr == 8'h31; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_725 = btb_wr_addr == 8'h32; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_728 = btb_wr_addr == 8'h33; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_731 = btb_wr_addr == 8'h34; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_734 = btb_wr_addr == 8'h35; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_737 = btb_wr_addr == 8'h36; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_740 = btb_wr_addr == 8'h37; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_743 = btb_wr_addr == 8'h38; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_746 = btb_wr_addr == 8'h39; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_749 = btb_wr_addr == 8'h3a; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_752 = btb_wr_addr == 8'h3b; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_755 = btb_wr_addr == 8'h3c; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_758 = btb_wr_addr == 8'h3d; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_761 = btb_wr_addr == 8'h3e; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_764 = btb_wr_addr == 8'h3f; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_767 = btb_wr_addr == 8'h40; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_770 = btb_wr_addr == 8'h41; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_773 = btb_wr_addr == 8'h42; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_776 = btb_wr_addr == 8'h43; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_779 = btb_wr_addr == 8'h44; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_782 = btb_wr_addr == 8'h45; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_785 = btb_wr_addr == 8'h46; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_788 = btb_wr_addr == 8'h47; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_791 = btb_wr_addr == 8'h48; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_794 = btb_wr_addr == 8'h49; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_797 = btb_wr_addr == 8'h4a; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_800 = btb_wr_addr == 8'h4b; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_803 = btb_wr_addr == 8'h4c; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_806 = btb_wr_addr == 8'h4d; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_809 = btb_wr_addr == 8'h4e; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_812 = btb_wr_addr == 8'h4f; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_815 = btb_wr_addr == 8'h50; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_818 = btb_wr_addr == 8'h51; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_821 = btb_wr_addr == 8'h52; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_824 = btb_wr_addr == 8'h53; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_827 = btb_wr_addr == 8'h54; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_830 = btb_wr_addr == 8'h55; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_833 = btb_wr_addr == 8'h56; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_836 = btb_wr_addr == 8'h57; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_839 = btb_wr_addr == 8'h58; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_842 = btb_wr_addr == 8'h59; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_845 = btb_wr_addr == 8'h5a; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_848 = btb_wr_addr == 8'h5b; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_851 = btb_wr_addr == 8'h5c; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_854 = btb_wr_addr == 8'h5d; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_857 = btb_wr_addr == 8'h5e; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_860 = btb_wr_addr == 8'h5f; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_863 = btb_wr_addr == 8'h60; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_866 = btb_wr_addr == 8'h61; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_869 = btb_wr_addr == 8'h62; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_872 = btb_wr_addr == 8'h63; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_875 = btb_wr_addr == 8'h64; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_878 = btb_wr_addr == 8'h65; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_881 = btb_wr_addr == 8'h66; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_884 = btb_wr_addr == 8'h67; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_887 = btb_wr_addr == 8'h68; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_890 = btb_wr_addr == 8'h69; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_893 = btb_wr_addr == 8'h6a; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_896 = btb_wr_addr == 8'h6b; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_899 = btb_wr_addr == 8'h6c; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_902 = btb_wr_addr == 8'h6d; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_905 = btb_wr_addr == 8'h6e; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_908 = btb_wr_addr == 8'h6f; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_911 = btb_wr_addr == 8'h70; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_914 = btb_wr_addr == 8'h71; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_917 = btb_wr_addr == 8'h72; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_920 = btb_wr_addr == 8'h73; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_923 = btb_wr_addr == 8'h74; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_926 = btb_wr_addr == 8'h75; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_929 = btb_wr_addr == 8'h76; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_932 = btb_wr_addr == 8'h77; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_935 = btb_wr_addr == 8'h78; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_938 = btb_wr_addr == 8'h79; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_941 = btb_wr_addr == 8'h7a; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_944 = btb_wr_addr == 8'h7b; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_947 = btb_wr_addr == 8'h7c; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_950 = btb_wr_addr == 8'h7d; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_953 = btb_wr_addr == 8'h7e; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_956 = btb_wr_addr == 8'h7f; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_959 = btb_wr_addr == 8'h80; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_962 = btb_wr_addr == 8'h81; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_965 = btb_wr_addr == 8'h82; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_968 = btb_wr_addr == 8'h83; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_971 = btb_wr_addr == 8'h84; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_974 = btb_wr_addr == 8'h85; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_977 = btb_wr_addr == 8'h86; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_980 = btb_wr_addr == 8'h87; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_983 = btb_wr_addr == 8'h88; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_986 = btb_wr_addr == 8'h89; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_989 = btb_wr_addr == 8'h8a; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_992 = btb_wr_addr == 8'h8b; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_995 = btb_wr_addr == 8'h8c; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_998 = btb_wr_addr == 8'h8d; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1001 = btb_wr_addr == 8'h8e; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1004 = btb_wr_addr == 8'h8f; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1007 = btb_wr_addr == 8'h90; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1010 = btb_wr_addr == 8'h91; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1013 = btb_wr_addr == 8'h92; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1016 = btb_wr_addr == 8'h93; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1019 = btb_wr_addr == 8'h94; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1022 = btb_wr_addr == 8'h95; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1025 = btb_wr_addr == 8'h96; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1028 = btb_wr_addr == 8'h97; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1031 = btb_wr_addr == 8'h98; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1034 = btb_wr_addr == 8'h99; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1037 = btb_wr_addr == 8'h9a; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1040 = btb_wr_addr == 8'h9b; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1043 = btb_wr_addr == 8'h9c; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1046 = btb_wr_addr == 8'h9d; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1049 = btb_wr_addr == 8'h9e; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1052 = btb_wr_addr == 8'h9f; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1055 = btb_wr_addr == 8'ha0; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1058 = btb_wr_addr == 8'ha1; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1061 = btb_wr_addr == 8'ha2; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1064 = btb_wr_addr == 8'ha3; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1067 = btb_wr_addr == 8'ha4; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1070 = btb_wr_addr == 8'ha5; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1073 = btb_wr_addr == 8'ha6; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1076 = btb_wr_addr == 8'ha7; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1079 = btb_wr_addr == 8'ha8; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1082 = btb_wr_addr == 8'ha9; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1085 = btb_wr_addr == 8'haa; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1088 = btb_wr_addr == 8'hab; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1091 = btb_wr_addr == 8'hac; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1094 = btb_wr_addr == 8'had; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1097 = btb_wr_addr == 8'hae; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1100 = btb_wr_addr == 8'haf; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1103 = btb_wr_addr == 8'hb0; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1106 = btb_wr_addr == 8'hb1; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1109 = btb_wr_addr == 8'hb2; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1112 = btb_wr_addr == 8'hb3; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1115 = btb_wr_addr == 8'hb4; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1118 = btb_wr_addr == 8'hb5; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1121 = btb_wr_addr == 8'hb6; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1124 = btb_wr_addr == 8'hb7; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1127 = btb_wr_addr == 8'hb8; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1130 = btb_wr_addr == 8'hb9; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1133 = btb_wr_addr == 8'hba; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1136 = btb_wr_addr == 8'hbb; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1139 = btb_wr_addr == 8'hbc; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1142 = btb_wr_addr == 8'hbd; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1145 = btb_wr_addr == 8'hbe; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1148 = btb_wr_addr == 8'hbf; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1151 = btb_wr_addr == 8'hc0; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1154 = btb_wr_addr == 8'hc1; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1157 = btb_wr_addr == 8'hc2; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1160 = btb_wr_addr == 8'hc3; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1163 = btb_wr_addr == 8'hc4; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1166 = btb_wr_addr == 8'hc5; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1169 = btb_wr_addr == 8'hc6; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1172 = btb_wr_addr == 8'hc7; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1175 = btb_wr_addr == 8'hc8; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1178 = btb_wr_addr == 8'hc9; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1181 = btb_wr_addr == 8'hca; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1184 = btb_wr_addr == 8'hcb; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1187 = btb_wr_addr == 8'hcc; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1190 = btb_wr_addr == 8'hcd; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1193 = btb_wr_addr == 8'hce; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1196 = btb_wr_addr == 8'hcf; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1199 = btb_wr_addr == 8'hd0; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1202 = btb_wr_addr == 8'hd1; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1205 = btb_wr_addr == 8'hd2; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1208 = btb_wr_addr == 8'hd3; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1211 = btb_wr_addr == 8'hd4; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1214 = btb_wr_addr == 8'hd5; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1217 = btb_wr_addr == 8'hd6; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1220 = btb_wr_addr == 8'hd7; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1223 = btb_wr_addr == 8'hd8; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1226 = btb_wr_addr == 8'hd9; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1229 = btb_wr_addr == 8'hda; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1232 = btb_wr_addr == 8'hdb; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1235 = btb_wr_addr == 8'hdc; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1238 = btb_wr_addr == 8'hdd; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1241 = btb_wr_addr == 8'hde; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1244 = btb_wr_addr == 8'hdf; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1247 = btb_wr_addr == 8'he0; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1250 = btb_wr_addr == 8'he1; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1253 = btb_wr_addr == 8'he2; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1256 = btb_wr_addr == 8'he3; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1259 = btb_wr_addr == 8'he4; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1262 = btb_wr_addr == 8'he5; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1265 = btb_wr_addr == 8'he6; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1268 = btb_wr_addr == 8'he7; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1271 = btb_wr_addr == 8'he8; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1274 = btb_wr_addr == 8'he9; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1277 = btb_wr_addr == 8'hea; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1280 = btb_wr_addr == 8'heb; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1283 = btb_wr_addr == 8'hec; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1286 = btb_wr_addr == 8'hed; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1289 = btb_wr_addr == 8'hee; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1292 = btb_wr_addr == 8'hef; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1295 = btb_wr_addr == 8'hf0; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1298 = btb_wr_addr == 8'hf1; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1301 = btb_wr_addr == 8'hf2; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1304 = btb_wr_addr == 8'hf3; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1307 = btb_wr_addr == 8'hf4; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1310 = btb_wr_addr == 8'hf5; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1313 = btb_wr_addr == 8'hf6; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1316 = btb_wr_addr == 8'hf7; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1319 = btb_wr_addr == 8'hf8; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1322 = btb_wr_addr == 8'hf9; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1325 = btb_wr_addr == 8'hfa; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1328 = btb_wr_addr == 8'hfb; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1331 = btb_wr_addr == 8'hfc; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1334 = btb_wr_addr == 8'hfd; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1337 = btb_wr_addr == 8'hfe; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_1340 = btb_wr_addr == 8'hff; // @[el2_ifu_bp_ctl.scala 427:95]
|
|
wire _T_6209 = mp_hashed[7:4] == 4'h0; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6211 = bht_wr_en0[0] & _T_6209; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6214 = br0_hashed_wb[7:4] == 4'h0; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6216 = bht_wr_en2[0] & _T_6214; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6220 = mp_hashed[7:4] == 4'h1; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6222 = bht_wr_en0[0] & _T_6220; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6225 = br0_hashed_wb[7:4] == 4'h1; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6227 = bht_wr_en2[0] & _T_6225; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6231 = mp_hashed[7:4] == 4'h2; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6233 = bht_wr_en0[0] & _T_6231; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6236 = br0_hashed_wb[7:4] == 4'h2; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6238 = bht_wr_en2[0] & _T_6236; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6242 = mp_hashed[7:4] == 4'h3; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6244 = bht_wr_en0[0] & _T_6242; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6247 = br0_hashed_wb[7:4] == 4'h3; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6249 = bht_wr_en2[0] & _T_6247; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6253 = mp_hashed[7:4] == 4'h4; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6255 = bht_wr_en0[0] & _T_6253; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6258 = br0_hashed_wb[7:4] == 4'h4; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6260 = bht_wr_en2[0] & _T_6258; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6264 = mp_hashed[7:4] == 4'h5; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6266 = bht_wr_en0[0] & _T_6264; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6269 = br0_hashed_wb[7:4] == 4'h5; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6271 = bht_wr_en2[0] & _T_6269; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6275 = mp_hashed[7:4] == 4'h6; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6277 = bht_wr_en0[0] & _T_6275; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6280 = br0_hashed_wb[7:4] == 4'h6; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6282 = bht_wr_en2[0] & _T_6280; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6286 = mp_hashed[7:4] == 4'h7; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6288 = bht_wr_en0[0] & _T_6286; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6291 = br0_hashed_wb[7:4] == 4'h7; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6293 = bht_wr_en2[0] & _T_6291; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6297 = mp_hashed[7:4] == 4'h8; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6299 = bht_wr_en0[0] & _T_6297; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6302 = br0_hashed_wb[7:4] == 4'h8; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6304 = bht_wr_en2[0] & _T_6302; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6308 = mp_hashed[7:4] == 4'h9; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6310 = bht_wr_en0[0] & _T_6308; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6313 = br0_hashed_wb[7:4] == 4'h9; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6315 = bht_wr_en2[0] & _T_6313; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6319 = mp_hashed[7:4] == 4'ha; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6321 = bht_wr_en0[0] & _T_6319; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6324 = br0_hashed_wb[7:4] == 4'ha; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6326 = bht_wr_en2[0] & _T_6324; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6330 = mp_hashed[7:4] == 4'hb; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6332 = bht_wr_en0[0] & _T_6330; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6335 = br0_hashed_wb[7:4] == 4'hb; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6337 = bht_wr_en2[0] & _T_6335; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6341 = mp_hashed[7:4] == 4'hc; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6343 = bht_wr_en0[0] & _T_6341; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6346 = br0_hashed_wb[7:4] == 4'hc; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6348 = bht_wr_en2[0] & _T_6346; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6352 = mp_hashed[7:4] == 4'hd; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6354 = bht_wr_en0[0] & _T_6352; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6357 = br0_hashed_wb[7:4] == 4'hd; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6359 = bht_wr_en2[0] & _T_6357; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6363 = mp_hashed[7:4] == 4'he; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6365 = bht_wr_en0[0] & _T_6363; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6368 = br0_hashed_wb[7:4] == 4'he; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6370 = bht_wr_en2[0] & _T_6368; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6374 = mp_hashed[7:4] == 4'hf; // @[el2_ifu_bp_ctl.scala 441:109]
|
|
wire _T_6376 = bht_wr_en0[0] & _T_6374; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6379 = br0_hashed_wb[7:4] == 4'hf; // @[el2_ifu_bp_ctl.scala 442:109]
|
|
wire _T_6381 = bht_wr_en2[0] & _T_6379; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6387 = bht_wr_en0[1] & _T_6209; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6392 = bht_wr_en2[1] & _T_6214; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6398 = bht_wr_en0[1] & _T_6220; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6403 = bht_wr_en2[1] & _T_6225; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6409 = bht_wr_en0[1] & _T_6231; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6414 = bht_wr_en2[1] & _T_6236; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6420 = bht_wr_en0[1] & _T_6242; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6425 = bht_wr_en2[1] & _T_6247; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6431 = bht_wr_en0[1] & _T_6253; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6436 = bht_wr_en2[1] & _T_6258; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6442 = bht_wr_en0[1] & _T_6264; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6447 = bht_wr_en2[1] & _T_6269; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6453 = bht_wr_en0[1] & _T_6275; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6458 = bht_wr_en2[1] & _T_6280; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6464 = bht_wr_en0[1] & _T_6286; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6469 = bht_wr_en2[1] & _T_6291; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6475 = bht_wr_en0[1] & _T_6297; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6480 = bht_wr_en2[1] & _T_6302; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6486 = bht_wr_en0[1] & _T_6308; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6491 = bht_wr_en2[1] & _T_6313; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6497 = bht_wr_en0[1] & _T_6319; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6502 = bht_wr_en2[1] & _T_6324; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6508 = bht_wr_en0[1] & _T_6330; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6513 = bht_wr_en2[1] & _T_6335; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6519 = bht_wr_en0[1] & _T_6341; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6524 = bht_wr_en2[1] & _T_6346; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6530 = bht_wr_en0[1] & _T_6352; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6535 = bht_wr_en2[1] & _T_6357; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6541 = bht_wr_en0[1] & _T_6363; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6546 = bht_wr_en2[1] & _T_6368; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6552 = bht_wr_en0[1] & _T_6374; // @[el2_ifu_bp_ctl.scala 441:44]
|
|
wire _T_6557 = bht_wr_en2[1] & _T_6379; // @[el2_ifu_bp_ctl.scala 442:44]
|
|
wire _T_6561 = br0_hashed_wb[3:0] == 4'h0; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6562 = bht_wr_en2[0] & _T_6561; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6565 = _T_6562 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6570 = br0_hashed_wb[3:0] == 4'h1; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6571 = bht_wr_en2[0] & _T_6570; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6574 = _T_6571 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6579 = br0_hashed_wb[3:0] == 4'h2; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6580 = bht_wr_en2[0] & _T_6579; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6583 = _T_6580 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6588 = br0_hashed_wb[3:0] == 4'h3; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6589 = bht_wr_en2[0] & _T_6588; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6592 = _T_6589 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6597 = br0_hashed_wb[3:0] == 4'h4; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6598 = bht_wr_en2[0] & _T_6597; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6601 = _T_6598 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6606 = br0_hashed_wb[3:0] == 4'h5; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6607 = bht_wr_en2[0] & _T_6606; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6610 = _T_6607 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6615 = br0_hashed_wb[3:0] == 4'h6; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6616 = bht_wr_en2[0] & _T_6615; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6619 = _T_6616 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6624 = br0_hashed_wb[3:0] == 4'h7; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6625 = bht_wr_en2[0] & _T_6624; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6628 = _T_6625 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6633 = br0_hashed_wb[3:0] == 4'h8; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6634 = bht_wr_en2[0] & _T_6633; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6637 = _T_6634 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6642 = br0_hashed_wb[3:0] == 4'h9; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6643 = bht_wr_en2[0] & _T_6642; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6646 = _T_6643 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6651 = br0_hashed_wb[3:0] == 4'ha; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6652 = bht_wr_en2[0] & _T_6651; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6655 = _T_6652 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6660 = br0_hashed_wb[3:0] == 4'hb; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6661 = bht_wr_en2[0] & _T_6660; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6664 = _T_6661 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6669 = br0_hashed_wb[3:0] == 4'hc; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6670 = bht_wr_en2[0] & _T_6669; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6673 = _T_6670 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6678 = br0_hashed_wb[3:0] == 4'hd; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6679 = bht_wr_en2[0] & _T_6678; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6682 = _T_6679 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6687 = br0_hashed_wb[3:0] == 4'he; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6688 = bht_wr_en2[0] & _T_6687; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6691 = _T_6688 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6696 = br0_hashed_wb[3:0] == 4'hf; // @[el2_ifu_bp_ctl.scala 447:74]
|
|
wire _T_6697 = bht_wr_en2[0] & _T_6696; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_6700 = _T_6697 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6709 = _T_6562 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6718 = _T_6571 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6727 = _T_6580 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6736 = _T_6589 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6745 = _T_6598 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6754 = _T_6607 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6763 = _T_6616 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6772 = _T_6625 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6781 = _T_6634 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6790 = _T_6643 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6799 = _T_6652 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6808 = _T_6661 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6817 = _T_6670 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6826 = _T_6679 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6835 = _T_6688 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6844 = _T_6697 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6853 = _T_6562 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6862 = _T_6571 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6871 = _T_6580 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6880 = _T_6589 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6889 = _T_6598 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6898 = _T_6607 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6907 = _T_6616 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6916 = _T_6625 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6925 = _T_6634 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6934 = _T_6643 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6943 = _T_6652 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6952 = _T_6661 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6961 = _T_6670 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6970 = _T_6679 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6979 = _T_6688 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6988 = _T_6697 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_6997 = _T_6562 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7006 = _T_6571 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7015 = _T_6580 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7024 = _T_6589 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7033 = _T_6598 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7042 = _T_6607 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7051 = _T_6616 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7060 = _T_6625 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7069 = _T_6634 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7078 = _T_6643 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7087 = _T_6652 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7096 = _T_6661 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7105 = _T_6670 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7114 = _T_6679 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7123 = _T_6688 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7132 = _T_6697 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7141 = _T_6562 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7150 = _T_6571 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7159 = _T_6580 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7168 = _T_6589 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7177 = _T_6598 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7186 = _T_6607 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7195 = _T_6616 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7204 = _T_6625 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7213 = _T_6634 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7222 = _T_6643 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7231 = _T_6652 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7240 = _T_6661 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7249 = _T_6670 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7258 = _T_6679 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7267 = _T_6688 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7276 = _T_6697 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7285 = _T_6562 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7294 = _T_6571 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7303 = _T_6580 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7312 = _T_6589 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7321 = _T_6598 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7330 = _T_6607 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7339 = _T_6616 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7348 = _T_6625 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7357 = _T_6634 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7366 = _T_6643 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7375 = _T_6652 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7384 = _T_6661 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7393 = _T_6670 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7402 = _T_6679 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7411 = _T_6688 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7420 = _T_6697 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7429 = _T_6562 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7438 = _T_6571 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7447 = _T_6580 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7456 = _T_6589 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7465 = _T_6598 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7474 = _T_6607 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7483 = _T_6616 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7492 = _T_6625 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7501 = _T_6634 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7510 = _T_6643 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7519 = _T_6652 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7528 = _T_6661 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7537 = _T_6670 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7546 = _T_6679 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7555 = _T_6688 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7564 = _T_6697 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7573 = _T_6562 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7582 = _T_6571 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7591 = _T_6580 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7600 = _T_6589 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7609 = _T_6598 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7618 = _T_6607 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7627 = _T_6616 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7636 = _T_6625 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7645 = _T_6634 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7654 = _T_6643 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7663 = _T_6652 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7672 = _T_6661 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7681 = _T_6670 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7690 = _T_6679 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7699 = _T_6688 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7708 = _T_6697 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7717 = _T_6562 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7726 = _T_6571 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7735 = _T_6580 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7744 = _T_6589 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7753 = _T_6598 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7762 = _T_6607 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7771 = _T_6616 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7780 = _T_6625 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7789 = _T_6634 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7798 = _T_6643 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7807 = _T_6652 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7816 = _T_6661 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7825 = _T_6670 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7834 = _T_6679 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7843 = _T_6688 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7852 = _T_6697 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7861 = _T_6562 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7870 = _T_6571 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7879 = _T_6580 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7888 = _T_6589 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7897 = _T_6598 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7906 = _T_6607 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7915 = _T_6616 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7924 = _T_6625 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7933 = _T_6634 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7942 = _T_6643 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7951 = _T_6652 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7960 = _T_6661 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7969 = _T_6670 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7978 = _T_6679 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7987 = _T_6688 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_7996 = _T_6697 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8005 = _T_6562 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8014 = _T_6571 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8023 = _T_6580 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8032 = _T_6589 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8041 = _T_6598 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8050 = _T_6607 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8059 = _T_6616 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8068 = _T_6625 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8077 = _T_6634 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8086 = _T_6643 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8095 = _T_6652 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8104 = _T_6661 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8113 = _T_6670 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8122 = _T_6679 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8131 = _T_6688 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8140 = _T_6697 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8149 = _T_6562 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8158 = _T_6571 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8167 = _T_6580 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8176 = _T_6589 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8185 = _T_6598 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8194 = _T_6607 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8203 = _T_6616 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8212 = _T_6625 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8221 = _T_6634 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8230 = _T_6643 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8239 = _T_6652 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8248 = _T_6661 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8257 = _T_6670 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8266 = _T_6679 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8275 = _T_6688 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8284 = _T_6697 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8293 = _T_6562 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8302 = _T_6571 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8311 = _T_6580 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8320 = _T_6589 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8329 = _T_6598 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8338 = _T_6607 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8347 = _T_6616 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8356 = _T_6625 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8365 = _T_6634 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8374 = _T_6643 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8383 = _T_6652 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8392 = _T_6661 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8401 = _T_6670 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8410 = _T_6679 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8419 = _T_6688 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8428 = _T_6697 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8437 = _T_6562 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8446 = _T_6571 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8455 = _T_6580 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8464 = _T_6589 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8473 = _T_6598 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8482 = _T_6607 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8491 = _T_6616 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8500 = _T_6625 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8509 = _T_6634 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8518 = _T_6643 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8527 = _T_6652 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8536 = _T_6661 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8545 = _T_6670 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8554 = _T_6679 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8563 = _T_6688 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8572 = _T_6697 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8581 = _T_6562 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8590 = _T_6571 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8599 = _T_6580 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8608 = _T_6589 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8617 = _T_6598 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8626 = _T_6607 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8635 = _T_6616 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8644 = _T_6625 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8653 = _T_6634 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8662 = _T_6643 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8671 = _T_6652 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8680 = _T_6661 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8689 = _T_6670 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8698 = _T_6679 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8707 = _T_6688 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8716 = _T_6697 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8725 = _T_6562 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8734 = _T_6571 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8743 = _T_6580 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8752 = _T_6589 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8761 = _T_6598 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8770 = _T_6607 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8779 = _T_6616 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8788 = _T_6625 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8797 = _T_6634 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8806 = _T_6643 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8815 = _T_6652 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8824 = _T_6661 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8833 = _T_6670 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8842 = _T_6679 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8851 = _T_6688 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8860 = _T_6697 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8866 = bht_wr_en2[1] & _T_6561; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8869 = _T_8866 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8875 = bht_wr_en2[1] & _T_6570; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8878 = _T_8875 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8884 = bht_wr_en2[1] & _T_6579; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8887 = _T_8884 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8893 = bht_wr_en2[1] & _T_6588; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8896 = _T_8893 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8902 = bht_wr_en2[1] & _T_6597; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8905 = _T_8902 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8911 = bht_wr_en2[1] & _T_6606; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8914 = _T_8911 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8920 = bht_wr_en2[1] & _T_6615; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8923 = _T_8920 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8929 = bht_wr_en2[1] & _T_6624; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8932 = _T_8929 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8938 = bht_wr_en2[1] & _T_6633; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8941 = _T_8938 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8947 = bht_wr_en2[1] & _T_6642; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8950 = _T_8947 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8956 = bht_wr_en2[1] & _T_6651; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8959 = _T_8956 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8965 = bht_wr_en2[1] & _T_6660; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8968 = _T_8965 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8974 = bht_wr_en2[1] & _T_6669; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8977 = _T_8974 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8983 = bht_wr_en2[1] & _T_6678; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8986 = _T_8983 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_8992 = bht_wr_en2[1] & _T_6687; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_8995 = _T_8992 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9001 = bht_wr_en2[1] & _T_6696; // @[el2_ifu_bp_ctl.scala 447:23]
|
|
wire _T_9004 = _T_9001 & _T_6214; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9013 = _T_8866 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9022 = _T_8875 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9031 = _T_8884 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9040 = _T_8893 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9049 = _T_8902 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9058 = _T_8911 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9067 = _T_8920 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9076 = _T_8929 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9085 = _T_8938 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9094 = _T_8947 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9103 = _T_8956 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9112 = _T_8965 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9121 = _T_8974 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9130 = _T_8983 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9139 = _T_8992 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9148 = _T_9001 & _T_6225; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9157 = _T_8866 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9166 = _T_8875 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9175 = _T_8884 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9184 = _T_8893 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9193 = _T_8902 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9202 = _T_8911 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9211 = _T_8920 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9220 = _T_8929 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9229 = _T_8938 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9238 = _T_8947 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9247 = _T_8956 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9256 = _T_8965 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9265 = _T_8974 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9274 = _T_8983 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9283 = _T_8992 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9292 = _T_9001 & _T_6236; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9301 = _T_8866 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9310 = _T_8875 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9319 = _T_8884 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9328 = _T_8893 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9337 = _T_8902 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9346 = _T_8911 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9355 = _T_8920 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9364 = _T_8929 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9373 = _T_8938 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9382 = _T_8947 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9391 = _T_8956 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9400 = _T_8965 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9409 = _T_8974 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9418 = _T_8983 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9427 = _T_8992 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9436 = _T_9001 & _T_6247; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9445 = _T_8866 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9454 = _T_8875 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9463 = _T_8884 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9472 = _T_8893 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9481 = _T_8902 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9490 = _T_8911 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9499 = _T_8920 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9508 = _T_8929 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9517 = _T_8938 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9526 = _T_8947 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9535 = _T_8956 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9544 = _T_8965 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9553 = _T_8974 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9562 = _T_8983 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9571 = _T_8992 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9580 = _T_9001 & _T_6258; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9589 = _T_8866 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9598 = _T_8875 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9607 = _T_8884 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9616 = _T_8893 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9625 = _T_8902 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9634 = _T_8911 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9643 = _T_8920 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9652 = _T_8929 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9661 = _T_8938 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9670 = _T_8947 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9679 = _T_8956 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9688 = _T_8965 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9697 = _T_8974 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9706 = _T_8983 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9715 = _T_8992 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9724 = _T_9001 & _T_6269; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9733 = _T_8866 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9742 = _T_8875 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9751 = _T_8884 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9760 = _T_8893 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9769 = _T_8902 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9778 = _T_8911 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9787 = _T_8920 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9796 = _T_8929 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9805 = _T_8938 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9814 = _T_8947 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9823 = _T_8956 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9832 = _T_8965 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9841 = _T_8974 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9850 = _T_8983 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9859 = _T_8992 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9868 = _T_9001 & _T_6280; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9877 = _T_8866 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9886 = _T_8875 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9895 = _T_8884 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9904 = _T_8893 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9913 = _T_8902 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9922 = _T_8911 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9931 = _T_8920 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9940 = _T_8929 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9949 = _T_8938 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9958 = _T_8947 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9967 = _T_8956 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9976 = _T_8965 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9985 = _T_8974 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_9994 = _T_8983 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10003 = _T_8992 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10012 = _T_9001 & _T_6291; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10021 = _T_8866 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10030 = _T_8875 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10039 = _T_8884 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10048 = _T_8893 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10057 = _T_8902 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10066 = _T_8911 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10075 = _T_8920 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10084 = _T_8929 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10093 = _T_8938 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10102 = _T_8947 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10111 = _T_8956 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10120 = _T_8965 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10129 = _T_8974 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10138 = _T_8983 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10147 = _T_8992 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10156 = _T_9001 & _T_6302; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10165 = _T_8866 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10174 = _T_8875 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10183 = _T_8884 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10192 = _T_8893 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10201 = _T_8902 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10210 = _T_8911 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10219 = _T_8920 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10228 = _T_8929 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10237 = _T_8938 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10246 = _T_8947 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10255 = _T_8956 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10264 = _T_8965 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10273 = _T_8974 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10282 = _T_8983 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10291 = _T_8992 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10300 = _T_9001 & _T_6313; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10309 = _T_8866 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10318 = _T_8875 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10327 = _T_8884 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10336 = _T_8893 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10345 = _T_8902 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10354 = _T_8911 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10363 = _T_8920 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10372 = _T_8929 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10381 = _T_8938 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10390 = _T_8947 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10399 = _T_8956 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10408 = _T_8965 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10417 = _T_8974 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10426 = _T_8983 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10435 = _T_8992 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10444 = _T_9001 & _T_6324; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10453 = _T_8866 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10462 = _T_8875 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10471 = _T_8884 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10480 = _T_8893 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10489 = _T_8902 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10498 = _T_8911 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10507 = _T_8920 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10516 = _T_8929 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10525 = _T_8938 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10534 = _T_8947 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10543 = _T_8956 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10552 = _T_8965 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10561 = _T_8974 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10570 = _T_8983 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10579 = _T_8992 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10588 = _T_9001 & _T_6335; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10597 = _T_8866 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10606 = _T_8875 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10615 = _T_8884 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10624 = _T_8893 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10633 = _T_8902 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10642 = _T_8911 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10651 = _T_8920 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10660 = _T_8929 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10669 = _T_8938 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10678 = _T_8947 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10687 = _T_8956 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10696 = _T_8965 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10705 = _T_8974 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10714 = _T_8983 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10723 = _T_8992 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10732 = _T_9001 & _T_6346; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10741 = _T_8866 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10750 = _T_8875 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10759 = _T_8884 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10768 = _T_8893 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10777 = _T_8902 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10786 = _T_8911 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10795 = _T_8920 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10804 = _T_8929 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10813 = _T_8938 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10822 = _T_8947 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10831 = _T_8956 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10840 = _T_8965 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10849 = _T_8974 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10858 = _T_8983 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10867 = _T_8992 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10876 = _T_9001 & _T_6357; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10885 = _T_8866 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10894 = _T_8875 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10903 = _T_8884 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10912 = _T_8893 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10921 = _T_8902 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10930 = _T_8911 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10939 = _T_8920 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10948 = _T_8929 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10957 = _T_8938 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10966 = _T_8947 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10975 = _T_8956 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10984 = _T_8965 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_10993 = _T_8974 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11002 = _T_8983 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11011 = _T_8992 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11020 = _T_9001 & _T_6368; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11029 = _T_8866 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11038 = _T_8875 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11047 = _T_8884 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11056 = _T_8893 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11065 = _T_8902 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11074 = _T_8911 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11083 = _T_8920 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11092 = _T_8929 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11101 = _T_8938 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11110 = _T_8947 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11119 = _T_8956 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11128 = _T_8965 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11137 = _T_8974 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11146 = _T_8983 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11155 = _T_8992 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11164 = _T_9001 & _T_6379; // @[el2_ifu_bp_ctl.scala 447:81]
|
|
wire _T_11169 = mp_hashed[3:0] == 4'h0; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11170 = bht_wr_en0[0] & _T_11169; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11174 = _T_11170 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_0 = _T_11174 | _T_6565; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11186 = mp_hashed[3:0] == 4'h1; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11187 = bht_wr_en0[0] & _T_11186; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11191 = _T_11187 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_1 = _T_11191 | _T_6574; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11203 = mp_hashed[3:0] == 4'h2; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11204 = bht_wr_en0[0] & _T_11203; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11208 = _T_11204 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_2 = _T_11208 | _T_6583; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11220 = mp_hashed[3:0] == 4'h3; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11221 = bht_wr_en0[0] & _T_11220; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11225 = _T_11221 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_3 = _T_11225 | _T_6592; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11237 = mp_hashed[3:0] == 4'h4; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11238 = bht_wr_en0[0] & _T_11237; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11242 = _T_11238 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_4 = _T_11242 | _T_6601; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11254 = mp_hashed[3:0] == 4'h5; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11255 = bht_wr_en0[0] & _T_11254; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11259 = _T_11255 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_5 = _T_11259 | _T_6610; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11271 = mp_hashed[3:0] == 4'h6; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11272 = bht_wr_en0[0] & _T_11271; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11276 = _T_11272 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_6 = _T_11276 | _T_6619; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11288 = mp_hashed[3:0] == 4'h7; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11289 = bht_wr_en0[0] & _T_11288; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11293 = _T_11289 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_7 = _T_11293 | _T_6628; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11305 = mp_hashed[3:0] == 4'h8; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11306 = bht_wr_en0[0] & _T_11305; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11310 = _T_11306 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_8 = _T_11310 | _T_6637; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11322 = mp_hashed[3:0] == 4'h9; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11323 = bht_wr_en0[0] & _T_11322; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11327 = _T_11323 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_9 = _T_11327 | _T_6646; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11339 = mp_hashed[3:0] == 4'ha; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11340 = bht_wr_en0[0] & _T_11339; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11344 = _T_11340 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_10 = _T_11344 | _T_6655; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11356 = mp_hashed[3:0] == 4'hb; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11357 = bht_wr_en0[0] & _T_11356; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11361 = _T_11357 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_11 = _T_11361 | _T_6664; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11373 = mp_hashed[3:0] == 4'hc; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11374 = bht_wr_en0[0] & _T_11373; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11378 = _T_11374 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_12 = _T_11378 | _T_6673; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11390 = mp_hashed[3:0] == 4'hd; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11391 = bht_wr_en0[0] & _T_11390; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11395 = _T_11391 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_13 = _T_11395 | _T_6682; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11407 = mp_hashed[3:0] == 4'he; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11408 = bht_wr_en0[0] & _T_11407; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11412 = _T_11408 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_14 = _T_11412 | _T_6691; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11424 = mp_hashed[3:0] == 4'hf; // @[el2_ifu_bp_ctl.scala 455:97]
|
|
wire _T_11425 = bht_wr_en0[0] & _T_11424; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_11429 = _T_11425 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_0_15 = _T_11429 | _T_6700; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11446 = _T_11170 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_0 = _T_11446 | _T_6709; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11463 = _T_11187 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_1 = _T_11463 | _T_6718; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11480 = _T_11204 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_2 = _T_11480 | _T_6727; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11497 = _T_11221 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_3 = _T_11497 | _T_6736; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11514 = _T_11238 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_4 = _T_11514 | _T_6745; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11531 = _T_11255 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_5 = _T_11531 | _T_6754; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11548 = _T_11272 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_6 = _T_11548 | _T_6763; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11565 = _T_11289 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_7 = _T_11565 | _T_6772; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11582 = _T_11306 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_8 = _T_11582 | _T_6781; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11599 = _T_11323 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_9 = _T_11599 | _T_6790; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11616 = _T_11340 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_10 = _T_11616 | _T_6799; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11633 = _T_11357 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_11 = _T_11633 | _T_6808; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11650 = _T_11374 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_12 = _T_11650 | _T_6817; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11667 = _T_11391 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_13 = _T_11667 | _T_6826; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11684 = _T_11408 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_14 = _T_11684 | _T_6835; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11701 = _T_11425 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_1_15 = _T_11701 | _T_6844; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11718 = _T_11170 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_0 = _T_11718 | _T_6853; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11735 = _T_11187 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_1 = _T_11735 | _T_6862; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11752 = _T_11204 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_2 = _T_11752 | _T_6871; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11769 = _T_11221 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_3 = _T_11769 | _T_6880; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11786 = _T_11238 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_4 = _T_11786 | _T_6889; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11803 = _T_11255 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_5 = _T_11803 | _T_6898; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11820 = _T_11272 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_6 = _T_11820 | _T_6907; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11837 = _T_11289 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_7 = _T_11837 | _T_6916; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11854 = _T_11306 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_8 = _T_11854 | _T_6925; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11871 = _T_11323 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_9 = _T_11871 | _T_6934; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11888 = _T_11340 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_10 = _T_11888 | _T_6943; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11905 = _T_11357 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_11 = _T_11905 | _T_6952; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11922 = _T_11374 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_12 = _T_11922 | _T_6961; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11939 = _T_11391 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_13 = _T_11939 | _T_6970; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11956 = _T_11408 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_14 = _T_11956 | _T_6979; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11973 = _T_11425 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_2_15 = _T_11973 | _T_6988; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_11990 = _T_11170 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_0 = _T_11990 | _T_6997; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12007 = _T_11187 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_1 = _T_12007 | _T_7006; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12024 = _T_11204 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_2 = _T_12024 | _T_7015; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12041 = _T_11221 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_3 = _T_12041 | _T_7024; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12058 = _T_11238 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_4 = _T_12058 | _T_7033; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12075 = _T_11255 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_5 = _T_12075 | _T_7042; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12092 = _T_11272 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_6 = _T_12092 | _T_7051; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12109 = _T_11289 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_7 = _T_12109 | _T_7060; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12126 = _T_11306 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_8 = _T_12126 | _T_7069; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12143 = _T_11323 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_9 = _T_12143 | _T_7078; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12160 = _T_11340 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_10 = _T_12160 | _T_7087; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12177 = _T_11357 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_11 = _T_12177 | _T_7096; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12194 = _T_11374 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_12 = _T_12194 | _T_7105; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12211 = _T_11391 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_13 = _T_12211 | _T_7114; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12228 = _T_11408 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_14 = _T_12228 | _T_7123; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12245 = _T_11425 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_3_15 = _T_12245 | _T_7132; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12262 = _T_11170 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_0 = _T_12262 | _T_7141; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12279 = _T_11187 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_1 = _T_12279 | _T_7150; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12296 = _T_11204 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_2 = _T_12296 | _T_7159; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12313 = _T_11221 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_3 = _T_12313 | _T_7168; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12330 = _T_11238 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_4 = _T_12330 | _T_7177; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12347 = _T_11255 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_5 = _T_12347 | _T_7186; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12364 = _T_11272 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_6 = _T_12364 | _T_7195; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12381 = _T_11289 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_7 = _T_12381 | _T_7204; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12398 = _T_11306 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_8 = _T_12398 | _T_7213; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12415 = _T_11323 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_9 = _T_12415 | _T_7222; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12432 = _T_11340 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_10 = _T_12432 | _T_7231; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12449 = _T_11357 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_11 = _T_12449 | _T_7240; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12466 = _T_11374 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_12 = _T_12466 | _T_7249; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12483 = _T_11391 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_13 = _T_12483 | _T_7258; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12500 = _T_11408 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_14 = _T_12500 | _T_7267; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12517 = _T_11425 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_4_15 = _T_12517 | _T_7276; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12534 = _T_11170 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_0 = _T_12534 | _T_7285; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12551 = _T_11187 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_1 = _T_12551 | _T_7294; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12568 = _T_11204 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_2 = _T_12568 | _T_7303; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12585 = _T_11221 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_3 = _T_12585 | _T_7312; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12602 = _T_11238 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_4 = _T_12602 | _T_7321; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12619 = _T_11255 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_5 = _T_12619 | _T_7330; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12636 = _T_11272 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_6 = _T_12636 | _T_7339; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12653 = _T_11289 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_7 = _T_12653 | _T_7348; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12670 = _T_11306 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_8 = _T_12670 | _T_7357; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12687 = _T_11323 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_9 = _T_12687 | _T_7366; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12704 = _T_11340 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_10 = _T_12704 | _T_7375; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12721 = _T_11357 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_11 = _T_12721 | _T_7384; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12738 = _T_11374 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_12 = _T_12738 | _T_7393; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12755 = _T_11391 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_13 = _T_12755 | _T_7402; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12772 = _T_11408 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_14 = _T_12772 | _T_7411; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12789 = _T_11425 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_5_15 = _T_12789 | _T_7420; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12806 = _T_11170 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_0 = _T_12806 | _T_7429; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12823 = _T_11187 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_1 = _T_12823 | _T_7438; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12840 = _T_11204 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_2 = _T_12840 | _T_7447; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12857 = _T_11221 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_3 = _T_12857 | _T_7456; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12874 = _T_11238 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_4 = _T_12874 | _T_7465; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12891 = _T_11255 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_5 = _T_12891 | _T_7474; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12908 = _T_11272 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_6 = _T_12908 | _T_7483; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12925 = _T_11289 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_7 = _T_12925 | _T_7492; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12942 = _T_11306 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_8 = _T_12942 | _T_7501; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12959 = _T_11323 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_9 = _T_12959 | _T_7510; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12976 = _T_11340 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_10 = _T_12976 | _T_7519; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_12993 = _T_11357 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_11 = _T_12993 | _T_7528; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13010 = _T_11374 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_12 = _T_13010 | _T_7537; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13027 = _T_11391 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_13 = _T_13027 | _T_7546; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13044 = _T_11408 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_14 = _T_13044 | _T_7555; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13061 = _T_11425 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_6_15 = _T_13061 | _T_7564; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13078 = _T_11170 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_0 = _T_13078 | _T_7573; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13095 = _T_11187 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_1 = _T_13095 | _T_7582; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13112 = _T_11204 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_2 = _T_13112 | _T_7591; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13129 = _T_11221 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_3 = _T_13129 | _T_7600; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13146 = _T_11238 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_4 = _T_13146 | _T_7609; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13163 = _T_11255 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_5 = _T_13163 | _T_7618; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13180 = _T_11272 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_6 = _T_13180 | _T_7627; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13197 = _T_11289 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_7 = _T_13197 | _T_7636; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13214 = _T_11306 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_8 = _T_13214 | _T_7645; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13231 = _T_11323 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_9 = _T_13231 | _T_7654; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13248 = _T_11340 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_10 = _T_13248 | _T_7663; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13265 = _T_11357 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_11 = _T_13265 | _T_7672; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13282 = _T_11374 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_12 = _T_13282 | _T_7681; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13299 = _T_11391 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_13 = _T_13299 | _T_7690; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13316 = _T_11408 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_14 = _T_13316 | _T_7699; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13333 = _T_11425 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_7_15 = _T_13333 | _T_7708; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13350 = _T_11170 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_0 = _T_13350 | _T_7717; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13367 = _T_11187 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_1 = _T_13367 | _T_7726; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13384 = _T_11204 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_2 = _T_13384 | _T_7735; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13401 = _T_11221 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_3 = _T_13401 | _T_7744; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13418 = _T_11238 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_4 = _T_13418 | _T_7753; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13435 = _T_11255 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_5 = _T_13435 | _T_7762; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13452 = _T_11272 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_6 = _T_13452 | _T_7771; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13469 = _T_11289 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_7 = _T_13469 | _T_7780; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13486 = _T_11306 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_8 = _T_13486 | _T_7789; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13503 = _T_11323 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_9 = _T_13503 | _T_7798; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13520 = _T_11340 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_10 = _T_13520 | _T_7807; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13537 = _T_11357 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_11 = _T_13537 | _T_7816; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13554 = _T_11374 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_12 = _T_13554 | _T_7825; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13571 = _T_11391 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_13 = _T_13571 | _T_7834; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13588 = _T_11408 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_14 = _T_13588 | _T_7843; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13605 = _T_11425 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_8_15 = _T_13605 | _T_7852; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13622 = _T_11170 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_0 = _T_13622 | _T_7861; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13639 = _T_11187 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_1 = _T_13639 | _T_7870; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13656 = _T_11204 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_2 = _T_13656 | _T_7879; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13673 = _T_11221 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_3 = _T_13673 | _T_7888; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13690 = _T_11238 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_4 = _T_13690 | _T_7897; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13707 = _T_11255 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_5 = _T_13707 | _T_7906; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13724 = _T_11272 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_6 = _T_13724 | _T_7915; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13741 = _T_11289 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_7 = _T_13741 | _T_7924; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13758 = _T_11306 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_8 = _T_13758 | _T_7933; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13775 = _T_11323 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_9 = _T_13775 | _T_7942; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13792 = _T_11340 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_10 = _T_13792 | _T_7951; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13809 = _T_11357 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_11 = _T_13809 | _T_7960; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13826 = _T_11374 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_12 = _T_13826 | _T_7969; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13843 = _T_11391 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_13 = _T_13843 | _T_7978; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13860 = _T_11408 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_14 = _T_13860 | _T_7987; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13877 = _T_11425 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_9_15 = _T_13877 | _T_7996; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13894 = _T_11170 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_0 = _T_13894 | _T_8005; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13911 = _T_11187 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_1 = _T_13911 | _T_8014; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13928 = _T_11204 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_2 = _T_13928 | _T_8023; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13945 = _T_11221 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_3 = _T_13945 | _T_8032; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13962 = _T_11238 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_4 = _T_13962 | _T_8041; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13979 = _T_11255 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_5 = _T_13979 | _T_8050; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_13996 = _T_11272 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_6 = _T_13996 | _T_8059; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14013 = _T_11289 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_7 = _T_14013 | _T_8068; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14030 = _T_11306 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_8 = _T_14030 | _T_8077; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14047 = _T_11323 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_9 = _T_14047 | _T_8086; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14064 = _T_11340 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_10 = _T_14064 | _T_8095; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14081 = _T_11357 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_11 = _T_14081 | _T_8104; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14098 = _T_11374 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_12 = _T_14098 | _T_8113; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14115 = _T_11391 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_13 = _T_14115 | _T_8122; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14132 = _T_11408 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_14 = _T_14132 | _T_8131; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14149 = _T_11425 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_10_15 = _T_14149 | _T_8140; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14166 = _T_11170 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_0 = _T_14166 | _T_8149; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14183 = _T_11187 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_1 = _T_14183 | _T_8158; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14200 = _T_11204 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_2 = _T_14200 | _T_8167; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14217 = _T_11221 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_3 = _T_14217 | _T_8176; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14234 = _T_11238 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_4 = _T_14234 | _T_8185; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14251 = _T_11255 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_5 = _T_14251 | _T_8194; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14268 = _T_11272 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_6 = _T_14268 | _T_8203; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14285 = _T_11289 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_7 = _T_14285 | _T_8212; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14302 = _T_11306 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_8 = _T_14302 | _T_8221; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14319 = _T_11323 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_9 = _T_14319 | _T_8230; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14336 = _T_11340 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_10 = _T_14336 | _T_8239; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14353 = _T_11357 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_11 = _T_14353 | _T_8248; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14370 = _T_11374 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_12 = _T_14370 | _T_8257; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14387 = _T_11391 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_13 = _T_14387 | _T_8266; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14404 = _T_11408 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_14 = _T_14404 | _T_8275; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14421 = _T_11425 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_11_15 = _T_14421 | _T_8284; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14438 = _T_11170 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_0 = _T_14438 | _T_8293; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14455 = _T_11187 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_1 = _T_14455 | _T_8302; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14472 = _T_11204 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_2 = _T_14472 | _T_8311; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14489 = _T_11221 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_3 = _T_14489 | _T_8320; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14506 = _T_11238 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_4 = _T_14506 | _T_8329; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14523 = _T_11255 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_5 = _T_14523 | _T_8338; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14540 = _T_11272 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_6 = _T_14540 | _T_8347; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14557 = _T_11289 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_7 = _T_14557 | _T_8356; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14574 = _T_11306 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_8 = _T_14574 | _T_8365; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14591 = _T_11323 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_9 = _T_14591 | _T_8374; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14608 = _T_11340 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_10 = _T_14608 | _T_8383; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14625 = _T_11357 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_11 = _T_14625 | _T_8392; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14642 = _T_11374 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_12 = _T_14642 | _T_8401; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14659 = _T_11391 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_13 = _T_14659 | _T_8410; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14676 = _T_11408 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_14 = _T_14676 | _T_8419; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14693 = _T_11425 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_12_15 = _T_14693 | _T_8428; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14710 = _T_11170 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_0 = _T_14710 | _T_8437; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14727 = _T_11187 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_1 = _T_14727 | _T_8446; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14744 = _T_11204 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_2 = _T_14744 | _T_8455; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14761 = _T_11221 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_3 = _T_14761 | _T_8464; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14778 = _T_11238 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_4 = _T_14778 | _T_8473; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14795 = _T_11255 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_5 = _T_14795 | _T_8482; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14812 = _T_11272 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_6 = _T_14812 | _T_8491; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14829 = _T_11289 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_7 = _T_14829 | _T_8500; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14846 = _T_11306 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_8 = _T_14846 | _T_8509; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14863 = _T_11323 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_9 = _T_14863 | _T_8518; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14880 = _T_11340 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_10 = _T_14880 | _T_8527; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14897 = _T_11357 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_11 = _T_14897 | _T_8536; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14914 = _T_11374 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_12 = _T_14914 | _T_8545; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14931 = _T_11391 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_13 = _T_14931 | _T_8554; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14948 = _T_11408 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_14 = _T_14948 | _T_8563; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14965 = _T_11425 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_13_15 = _T_14965 | _T_8572; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14982 = _T_11170 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_0 = _T_14982 | _T_8581; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_14999 = _T_11187 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_1 = _T_14999 | _T_8590; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15016 = _T_11204 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_2 = _T_15016 | _T_8599; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15033 = _T_11221 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_3 = _T_15033 | _T_8608; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15050 = _T_11238 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_4 = _T_15050 | _T_8617; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15067 = _T_11255 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_5 = _T_15067 | _T_8626; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15084 = _T_11272 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_6 = _T_15084 | _T_8635; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15101 = _T_11289 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_7 = _T_15101 | _T_8644; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15118 = _T_11306 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_8 = _T_15118 | _T_8653; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15135 = _T_11323 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_9 = _T_15135 | _T_8662; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15152 = _T_11340 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_10 = _T_15152 | _T_8671; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15169 = _T_11357 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_11 = _T_15169 | _T_8680; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15186 = _T_11374 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_12 = _T_15186 | _T_8689; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15203 = _T_11391 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_13 = _T_15203 | _T_8698; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15220 = _T_11408 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_14 = _T_15220 | _T_8707; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15237 = _T_11425 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_14_15 = _T_15237 | _T_8716; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15254 = _T_11170 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_0 = _T_15254 | _T_8725; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15271 = _T_11187 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_1 = _T_15271 | _T_8734; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15288 = _T_11204 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_2 = _T_15288 | _T_8743; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15305 = _T_11221 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_3 = _T_15305 | _T_8752; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15322 = _T_11238 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_4 = _T_15322 | _T_8761; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15339 = _T_11255 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_5 = _T_15339 | _T_8770; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15356 = _T_11272 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_6 = _T_15356 | _T_8779; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15373 = _T_11289 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_7 = _T_15373 | _T_8788; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15390 = _T_11306 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_8 = _T_15390 | _T_8797; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15407 = _T_11323 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_9 = _T_15407 | _T_8806; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15424 = _T_11340 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_10 = _T_15424 | _T_8815; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15441 = _T_11357 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_11 = _T_15441 | _T_8824; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15458 = _T_11374 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_12 = _T_15458 | _T_8833; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15475 = _T_11391 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_13 = _T_15475 | _T_8842; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15492 = _T_11408 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_14 = _T_15492 | _T_8851; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15509 = _T_11425 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_0_15_15 = _T_15509 | _T_8860; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15522 = bht_wr_en0[1] & _T_11169; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15526 = _T_15522 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_0 = _T_15526 | _T_8869; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15539 = bht_wr_en0[1] & _T_11186; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15543 = _T_15539 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_1 = _T_15543 | _T_8878; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15556 = bht_wr_en0[1] & _T_11203; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15560 = _T_15556 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_2 = _T_15560 | _T_8887; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15573 = bht_wr_en0[1] & _T_11220; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15577 = _T_15573 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_3 = _T_15577 | _T_8896; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15590 = bht_wr_en0[1] & _T_11237; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15594 = _T_15590 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_4 = _T_15594 | _T_8905; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15607 = bht_wr_en0[1] & _T_11254; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15611 = _T_15607 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_5 = _T_15611 | _T_8914; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15624 = bht_wr_en0[1] & _T_11271; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15628 = _T_15624 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_6 = _T_15628 | _T_8923; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15641 = bht_wr_en0[1] & _T_11288; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15645 = _T_15641 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_7 = _T_15645 | _T_8932; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15658 = bht_wr_en0[1] & _T_11305; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15662 = _T_15658 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_8 = _T_15662 | _T_8941; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15675 = bht_wr_en0[1] & _T_11322; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15679 = _T_15675 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_9 = _T_15679 | _T_8950; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15692 = bht_wr_en0[1] & _T_11339; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15696 = _T_15692 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_10 = _T_15696 | _T_8959; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15709 = bht_wr_en0[1] & _T_11356; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15713 = _T_15709 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_11 = _T_15713 | _T_8968; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15726 = bht_wr_en0[1] & _T_11373; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15730 = _T_15726 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_12 = _T_15730 | _T_8977; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15743 = bht_wr_en0[1] & _T_11390; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15747 = _T_15743 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_13 = _T_15747 | _T_8986; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15760 = bht_wr_en0[1] & _T_11407; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15764 = _T_15760 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_14 = _T_15764 | _T_8995; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15777 = bht_wr_en0[1] & _T_11424; // @[el2_ifu_bp_ctl.scala 455:45]
|
|
wire _T_15781 = _T_15777 & _T_6209; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_0_15 = _T_15781 | _T_9004; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15798 = _T_15522 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_0 = _T_15798 | _T_9013; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15815 = _T_15539 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_1 = _T_15815 | _T_9022; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15832 = _T_15556 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_2 = _T_15832 | _T_9031; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15849 = _T_15573 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_3 = _T_15849 | _T_9040; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15866 = _T_15590 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_4 = _T_15866 | _T_9049; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15883 = _T_15607 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_5 = _T_15883 | _T_9058; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15900 = _T_15624 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_6 = _T_15900 | _T_9067; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15917 = _T_15641 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_7 = _T_15917 | _T_9076; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15934 = _T_15658 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_8 = _T_15934 | _T_9085; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15951 = _T_15675 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_9 = _T_15951 | _T_9094; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15968 = _T_15692 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_10 = _T_15968 | _T_9103; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_15985 = _T_15709 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_11 = _T_15985 | _T_9112; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16002 = _T_15726 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_12 = _T_16002 | _T_9121; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16019 = _T_15743 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_13 = _T_16019 | _T_9130; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16036 = _T_15760 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_14 = _T_16036 | _T_9139; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16053 = _T_15777 & _T_6220; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_1_15 = _T_16053 | _T_9148; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16070 = _T_15522 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_0 = _T_16070 | _T_9157; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16087 = _T_15539 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_1 = _T_16087 | _T_9166; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16104 = _T_15556 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_2 = _T_16104 | _T_9175; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16121 = _T_15573 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_3 = _T_16121 | _T_9184; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16138 = _T_15590 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_4 = _T_16138 | _T_9193; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16155 = _T_15607 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_5 = _T_16155 | _T_9202; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16172 = _T_15624 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_6 = _T_16172 | _T_9211; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16189 = _T_15641 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_7 = _T_16189 | _T_9220; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16206 = _T_15658 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_8 = _T_16206 | _T_9229; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16223 = _T_15675 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_9 = _T_16223 | _T_9238; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16240 = _T_15692 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_10 = _T_16240 | _T_9247; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16257 = _T_15709 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_11 = _T_16257 | _T_9256; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16274 = _T_15726 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_12 = _T_16274 | _T_9265; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16291 = _T_15743 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_13 = _T_16291 | _T_9274; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16308 = _T_15760 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_14 = _T_16308 | _T_9283; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16325 = _T_15777 & _T_6231; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_2_15 = _T_16325 | _T_9292; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16342 = _T_15522 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_0 = _T_16342 | _T_9301; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16359 = _T_15539 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_1 = _T_16359 | _T_9310; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16376 = _T_15556 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_2 = _T_16376 | _T_9319; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16393 = _T_15573 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_3 = _T_16393 | _T_9328; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16410 = _T_15590 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_4 = _T_16410 | _T_9337; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16427 = _T_15607 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_5 = _T_16427 | _T_9346; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16444 = _T_15624 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_6 = _T_16444 | _T_9355; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16461 = _T_15641 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_7 = _T_16461 | _T_9364; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16478 = _T_15658 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_8 = _T_16478 | _T_9373; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16495 = _T_15675 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_9 = _T_16495 | _T_9382; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16512 = _T_15692 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_10 = _T_16512 | _T_9391; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16529 = _T_15709 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_11 = _T_16529 | _T_9400; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16546 = _T_15726 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_12 = _T_16546 | _T_9409; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16563 = _T_15743 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_13 = _T_16563 | _T_9418; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16580 = _T_15760 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_14 = _T_16580 | _T_9427; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16597 = _T_15777 & _T_6242; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_3_15 = _T_16597 | _T_9436; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16614 = _T_15522 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_0 = _T_16614 | _T_9445; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16631 = _T_15539 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_1 = _T_16631 | _T_9454; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16648 = _T_15556 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_2 = _T_16648 | _T_9463; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16665 = _T_15573 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_3 = _T_16665 | _T_9472; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16682 = _T_15590 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_4 = _T_16682 | _T_9481; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16699 = _T_15607 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_5 = _T_16699 | _T_9490; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16716 = _T_15624 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_6 = _T_16716 | _T_9499; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16733 = _T_15641 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_7 = _T_16733 | _T_9508; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16750 = _T_15658 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_8 = _T_16750 | _T_9517; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16767 = _T_15675 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_9 = _T_16767 | _T_9526; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16784 = _T_15692 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_10 = _T_16784 | _T_9535; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16801 = _T_15709 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_11 = _T_16801 | _T_9544; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16818 = _T_15726 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_12 = _T_16818 | _T_9553; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16835 = _T_15743 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_13 = _T_16835 | _T_9562; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16852 = _T_15760 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_14 = _T_16852 | _T_9571; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16869 = _T_15777 & _T_6253; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_4_15 = _T_16869 | _T_9580; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16886 = _T_15522 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_0 = _T_16886 | _T_9589; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16903 = _T_15539 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_1 = _T_16903 | _T_9598; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16920 = _T_15556 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_2 = _T_16920 | _T_9607; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16937 = _T_15573 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_3 = _T_16937 | _T_9616; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16954 = _T_15590 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_4 = _T_16954 | _T_9625; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16971 = _T_15607 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_5 = _T_16971 | _T_9634; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_16988 = _T_15624 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_6 = _T_16988 | _T_9643; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17005 = _T_15641 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_7 = _T_17005 | _T_9652; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17022 = _T_15658 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_8 = _T_17022 | _T_9661; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17039 = _T_15675 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_9 = _T_17039 | _T_9670; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17056 = _T_15692 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_10 = _T_17056 | _T_9679; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17073 = _T_15709 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_11 = _T_17073 | _T_9688; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17090 = _T_15726 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_12 = _T_17090 | _T_9697; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17107 = _T_15743 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_13 = _T_17107 | _T_9706; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17124 = _T_15760 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_14 = _T_17124 | _T_9715; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17141 = _T_15777 & _T_6264; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_5_15 = _T_17141 | _T_9724; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17158 = _T_15522 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_0 = _T_17158 | _T_9733; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17175 = _T_15539 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_1 = _T_17175 | _T_9742; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17192 = _T_15556 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_2 = _T_17192 | _T_9751; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17209 = _T_15573 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_3 = _T_17209 | _T_9760; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17226 = _T_15590 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_4 = _T_17226 | _T_9769; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17243 = _T_15607 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_5 = _T_17243 | _T_9778; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17260 = _T_15624 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_6 = _T_17260 | _T_9787; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17277 = _T_15641 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_7 = _T_17277 | _T_9796; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17294 = _T_15658 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_8 = _T_17294 | _T_9805; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17311 = _T_15675 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_9 = _T_17311 | _T_9814; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17328 = _T_15692 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_10 = _T_17328 | _T_9823; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17345 = _T_15709 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_11 = _T_17345 | _T_9832; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17362 = _T_15726 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_12 = _T_17362 | _T_9841; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17379 = _T_15743 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_13 = _T_17379 | _T_9850; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17396 = _T_15760 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_14 = _T_17396 | _T_9859; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17413 = _T_15777 & _T_6275; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_6_15 = _T_17413 | _T_9868; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17430 = _T_15522 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_0 = _T_17430 | _T_9877; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17447 = _T_15539 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_1 = _T_17447 | _T_9886; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17464 = _T_15556 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_2 = _T_17464 | _T_9895; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17481 = _T_15573 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_3 = _T_17481 | _T_9904; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17498 = _T_15590 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_4 = _T_17498 | _T_9913; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17515 = _T_15607 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_5 = _T_17515 | _T_9922; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17532 = _T_15624 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_6 = _T_17532 | _T_9931; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17549 = _T_15641 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_7 = _T_17549 | _T_9940; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17566 = _T_15658 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_8 = _T_17566 | _T_9949; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17583 = _T_15675 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_9 = _T_17583 | _T_9958; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17600 = _T_15692 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_10 = _T_17600 | _T_9967; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17617 = _T_15709 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_11 = _T_17617 | _T_9976; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17634 = _T_15726 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_12 = _T_17634 | _T_9985; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17651 = _T_15743 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_13 = _T_17651 | _T_9994; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17668 = _T_15760 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_14 = _T_17668 | _T_10003; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17685 = _T_15777 & _T_6286; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_7_15 = _T_17685 | _T_10012; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17702 = _T_15522 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_0 = _T_17702 | _T_10021; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17719 = _T_15539 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_1 = _T_17719 | _T_10030; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17736 = _T_15556 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_2 = _T_17736 | _T_10039; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17753 = _T_15573 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_3 = _T_17753 | _T_10048; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17770 = _T_15590 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_4 = _T_17770 | _T_10057; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17787 = _T_15607 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_5 = _T_17787 | _T_10066; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17804 = _T_15624 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_6 = _T_17804 | _T_10075; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17821 = _T_15641 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_7 = _T_17821 | _T_10084; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17838 = _T_15658 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_8 = _T_17838 | _T_10093; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17855 = _T_15675 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_9 = _T_17855 | _T_10102; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17872 = _T_15692 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_10 = _T_17872 | _T_10111; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17889 = _T_15709 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_11 = _T_17889 | _T_10120; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17906 = _T_15726 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_12 = _T_17906 | _T_10129; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17923 = _T_15743 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_13 = _T_17923 | _T_10138; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17940 = _T_15760 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_14 = _T_17940 | _T_10147; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17957 = _T_15777 & _T_6297; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_8_15 = _T_17957 | _T_10156; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17974 = _T_15522 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_0 = _T_17974 | _T_10165; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_17991 = _T_15539 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_1 = _T_17991 | _T_10174; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18008 = _T_15556 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_2 = _T_18008 | _T_10183; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18025 = _T_15573 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_3 = _T_18025 | _T_10192; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18042 = _T_15590 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_4 = _T_18042 | _T_10201; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18059 = _T_15607 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_5 = _T_18059 | _T_10210; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18076 = _T_15624 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_6 = _T_18076 | _T_10219; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18093 = _T_15641 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_7 = _T_18093 | _T_10228; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18110 = _T_15658 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_8 = _T_18110 | _T_10237; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18127 = _T_15675 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_9 = _T_18127 | _T_10246; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18144 = _T_15692 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_10 = _T_18144 | _T_10255; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18161 = _T_15709 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_11 = _T_18161 | _T_10264; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18178 = _T_15726 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_12 = _T_18178 | _T_10273; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18195 = _T_15743 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_13 = _T_18195 | _T_10282; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18212 = _T_15760 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_14 = _T_18212 | _T_10291; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18229 = _T_15777 & _T_6308; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_9_15 = _T_18229 | _T_10300; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18246 = _T_15522 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_0 = _T_18246 | _T_10309; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18263 = _T_15539 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_1 = _T_18263 | _T_10318; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18280 = _T_15556 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_2 = _T_18280 | _T_10327; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18297 = _T_15573 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_3 = _T_18297 | _T_10336; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18314 = _T_15590 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_4 = _T_18314 | _T_10345; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18331 = _T_15607 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_5 = _T_18331 | _T_10354; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18348 = _T_15624 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_6 = _T_18348 | _T_10363; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18365 = _T_15641 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_7 = _T_18365 | _T_10372; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18382 = _T_15658 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_8 = _T_18382 | _T_10381; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18399 = _T_15675 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_9 = _T_18399 | _T_10390; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18416 = _T_15692 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_10 = _T_18416 | _T_10399; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18433 = _T_15709 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_11 = _T_18433 | _T_10408; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18450 = _T_15726 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_12 = _T_18450 | _T_10417; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18467 = _T_15743 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_13 = _T_18467 | _T_10426; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18484 = _T_15760 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_14 = _T_18484 | _T_10435; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18501 = _T_15777 & _T_6319; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_10_15 = _T_18501 | _T_10444; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18518 = _T_15522 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_0 = _T_18518 | _T_10453; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18535 = _T_15539 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_1 = _T_18535 | _T_10462; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18552 = _T_15556 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_2 = _T_18552 | _T_10471; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18569 = _T_15573 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_3 = _T_18569 | _T_10480; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18586 = _T_15590 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_4 = _T_18586 | _T_10489; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18603 = _T_15607 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_5 = _T_18603 | _T_10498; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18620 = _T_15624 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_6 = _T_18620 | _T_10507; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18637 = _T_15641 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_7 = _T_18637 | _T_10516; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18654 = _T_15658 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_8 = _T_18654 | _T_10525; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18671 = _T_15675 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_9 = _T_18671 | _T_10534; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18688 = _T_15692 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_10 = _T_18688 | _T_10543; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18705 = _T_15709 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_11 = _T_18705 | _T_10552; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18722 = _T_15726 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_12 = _T_18722 | _T_10561; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18739 = _T_15743 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_13 = _T_18739 | _T_10570; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18756 = _T_15760 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_14 = _T_18756 | _T_10579; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18773 = _T_15777 & _T_6330; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_11_15 = _T_18773 | _T_10588; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18790 = _T_15522 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_0 = _T_18790 | _T_10597; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18807 = _T_15539 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_1 = _T_18807 | _T_10606; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18824 = _T_15556 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_2 = _T_18824 | _T_10615; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18841 = _T_15573 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_3 = _T_18841 | _T_10624; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18858 = _T_15590 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_4 = _T_18858 | _T_10633; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18875 = _T_15607 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_5 = _T_18875 | _T_10642; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18892 = _T_15624 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_6 = _T_18892 | _T_10651; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18909 = _T_15641 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_7 = _T_18909 | _T_10660; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18926 = _T_15658 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_8 = _T_18926 | _T_10669; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18943 = _T_15675 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_9 = _T_18943 | _T_10678; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18960 = _T_15692 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_10 = _T_18960 | _T_10687; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18977 = _T_15709 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_11 = _T_18977 | _T_10696; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_18994 = _T_15726 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_12 = _T_18994 | _T_10705; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19011 = _T_15743 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_13 = _T_19011 | _T_10714; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19028 = _T_15760 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_14 = _T_19028 | _T_10723; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19045 = _T_15777 & _T_6341; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_12_15 = _T_19045 | _T_10732; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19062 = _T_15522 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_0 = _T_19062 | _T_10741; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19079 = _T_15539 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_1 = _T_19079 | _T_10750; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19096 = _T_15556 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_2 = _T_19096 | _T_10759; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19113 = _T_15573 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_3 = _T_19113 | _T_10768; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19130 = _T_15590 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_4 = _T_19130 | _T_10777; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19147 = _T_15607 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_5 = _T_19147 | _T_10786; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19164 = _T_15624 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_6 = _T_19164 | _T_10795; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19181 = _T_15641 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_7 = _T_19181 | _T_10804; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19198 = _T_15658 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_8 = _T_19198 | _T_10813; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19215 = _T_15675 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_9 = _T_19215 | _T_10822; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19232 = _T_15692 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_10 = _T_19232 | _T_10831; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19249 = _T_15709 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_11 = _T_19249 | _T_10840; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19266 = _T_15726 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_12 = _T_19266 | _T_10849; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19283 = _T_15743 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_13 = _T_19283 | _T_10858; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19300 = _T_15760 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_14 = _T_19300 | _T_10867; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19317 = _T_15777 & _T_6352; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_13_15 = _T_19317 | _T_10876; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19334 = _T_15522 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_0 = _T_19334 | _T_10885; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19351 = _T_15539 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_1 = _T_19351 | _T_10894; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19368 = _T_15556 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_2 = _T_19368 | _T_10903; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19385 = _T_15573 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_3 = _T_19385 | _T_10912; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19402 = _T_15590 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_4 = _T_19402 | _T_10921; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19419 = _T_15607 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_5 = _T_19419 | _T_10930; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19436 = _T_15624 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_6 = _T_19436 | _T_10939; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19453 = _T_15641 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_7 = _T_19453 | _T_10948; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19470 = _T_15658 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_8 = _T_19470 | _T_10957; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19487 = _T_15675 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_9 = _T_19487 | _T_10966; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19504 = _T_15692 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_10 = _T_19504 | _T_10975; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19521 = _T_15709 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_11 = _T_19521 | _T_10984; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19538 = _T_15726 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_12 = _T_19538 | _T_10993; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19555 = _T_15743 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_13 = _T_19555 | _T_11002; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19572 = _T_15760 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_14 = _T_19572 | _T_11011; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19589 = _T_15777 & _T_6363; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_14_15 = _T_19589 | _T_11020; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19606 = _T_15522 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_0 = _T_19606 | _T_11029; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19623 = _T_15539 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_1 = _T_19623 | _T_11038; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19640 = _T_15556 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_2 = _T_19640 | _T_11047; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19657 = _T_15573 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_3 = _T_19657 | _T_11056; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19674 = _T_15590 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_4 = _T_19674 | _T_11065; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19691 = _T_15607 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_5 = _T_19691 | _T_11074; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19708 = _T_15624 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_6 = _T_19708 | _T_11083; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19725 = _T_15641 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_7 = _T_19725 | _T_11092; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19742 = _T_15658 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_8 = _T_19742 | _T_11101; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19759 = _T_15675 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_9 = _T_19759 | _T_11110; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19776 = _T_15692 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_10 = _T_19776 | _T_11119; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19793 = _T_15709 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_11 = _T_19793 | _T_11128; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19810 = _T_15726 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_12 = _T_19810 | _T_11137; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19827 = _T_15743 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_13 = _T_19827 | _T_11146; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19844 = _T_15760 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_14 = _T_19844 | _T_11155; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
wire _T_19861 = _T_15777 & _T_6374; // @[el2_ifu_bp_ctl.scala 455:110]
|
|
wire bht_bank_sel_1_15_15 = _T_19861 | _T_11164; // @[el2_ifu_bp_ctl.scala 455:223]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en),
|
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en),
|
|
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_8_io_l1clk),
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en),
|
|
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_9_io_l1clk),
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en),
|
|
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_10_io_l1clk),
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en),
|
|
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_11_io_l1clk),
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en),
|
|
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_12_io_l1clk),
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en),
|
|
.io_scan_mode(rvclkhdr_12_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_13_io_l1clk),
|
|
.io_clk(rvclkhdr_13_io_clk),
|
|
.io_en(rvclkhdr_13_io_en),
|
|
.io_scan_mode(rvclkhdr_13_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_14_io_l1clk),
|
|
.io_clk(rvclkhdr_14_io_clk),
|
|
.io_en(rvclkhdr_14_io_en),
|
|
.io_scan_mode(rvclkhdr_14_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_15_io_l1clk),
|
|
.io_clk(rvclkhdr_15_io_clk),
|
|
.io_en(rvclkhdr_15_io_en),
|
|
.io_scan_mode(rvclkhdr_15_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_16_io_l1clk),
|
|
.io_clk(rvclkhdr_16_io_clk),
|
|
.io_en(rvclkhdr_16_io_en),
|
|
.io_scan_mode(rvclkhdr_16_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_17_io_l1clk),
|
|
.io_clk(rvclkhdr_17_io_clk),
|
|
.io_en(rvclkhdr_17_io_en),
|
|
.io_scan_mode(rvclkhdr_17_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_18_io_l1clk),
|
|
.io_clk(rvclkhdr_18_io_clk),
|
|
.io_en(rvclkhdr_18_io_en),
|
|
.io_scan_mode(rvclkhdr_18_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_19_io_l1clk),
|
|
.io_clk(rvclkhdr_19_io_clk),
|
|
.io_en(rvclkhdr_19_io_en),
|
|
.io_scan_mode(rvclkhdr_19_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_20_io_l1clk),
|
|
.io_clk(rvclkhdr_20_io_clk),
|
|
.io_en(rvclkhdr_20_io_en),
|
|
.io_scan_mode(rvclkhdr_20_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_21_io_l1clk),
|
|
.io_clk(rvclkhdr_21_io_clk),
|
|
.io_en(rvclkhdr_21_io_en),
|
|
.io_scan_mode(rvclkhdr_21_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_22_io_l1clk),
|
|
.io_clk(rvclkhdr_22_io_clk),
|
|
.io_en(rvclkhdr_22_io_en),
|
|
.io_scan_mode(rvclkhdr_22_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_23_io_l1clk),
|
|
.io_clk(rvclkhdr_23_io_clk),
|
|
.io_en(rvclkhdr_23_io_en),
|
|
.io_scan_mode(rvclkhdr_23_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_24_io_l1clk),
|
|
.io_clk(rvclkhdr_24_io_clk),
|
|
.io_en(rvclkhdr_24_io_en),
|
|
.io_scan_mode(rvclkhdr_24_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_25_io_l1clk),
|
|
.io_clk(rvclkhdr_25_io_clk),
|
|
.io_en(rvclkhdr_25_io_en),
|
|
.io_scan_mode(rvclkhdr_25_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_26_io_l1clk),
|
|
.io_clk(rvclkhdr_26_io_clk),
|
|
.io_en(rvclkhdr_26_io_en),
|
|
.io_scan_mode(rvclkhdr_26_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_27_io_l1clk),
|
|
.io_clk(rvclkhdr_27_io_clk),
|
|
.io_en(rvclkhdr_27_io_en),
|
|
.io_scan_mode(rvclkhdr_27_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_28_io_l1clk),
|
|
.io_clk(rvclkhdr_28_io_clk),
|
|
.io_en(rvclkhdr_28_io_en),
|
|
.io_scan_mode(rvclkhdr_28_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_29_io_l1clk),
|
|
.io_clk(rvclkhdr_29_io_clk),
|
|
.io_en(rvclkhdr_29_io_en),
|
|
.io_scan_mode(rvclkhdr_29_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_30_io_l1clk),
|
|
.io_clk(rvclkhdr_30_io_clk),
|
|
.io_en(rvclkhdr_30_io_en),
|
|
.io_scan_mode(rvclkhdr_30_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_31 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_31_io_l1clk),
|
|
.io_clk(rvclkhdr_31_io_clk),
|
|
.io_en(rvclkhdr_31_io_en),
|
|
.io_scan_mode(rvclkhdr_31_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_32 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_32_io_l1clk),
|
|
.io_clk(rvclkhdr_32_io_clk),
|
|
.io_en(rvclkhdr_32_io_en),
|
|
.io_scan_mode(rvclkhdr_32_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_33 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_33_io_l1clk),
|
|
.io_clk(rvclkhdr_33_io_clk),
|
|
.io_en(rvclkhdr_33_io_en),
|
|
.io_scan_mode(rvclkhdr_33_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_34 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_34_io_l1clk),
|
|
.io_clk(rvclkhdr_34_io_clk),
|
|
.io_en(rvclkhdr_34_io_en),
|
|
.io_scan_mode(rvclkhdr_34_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_35 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_35_io_l1clk),
|
|
.io_clk(rvclkhdr_35_io_clk),
|
|
.io_en(rvclkhdr_35_io_en),
|
|
.io_scan_mode(rvclkhdr_35_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_36 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_36_io_l1clk),
|
|
.io_clk(rvclkhdr_36_io_clk),
|
|
.io_en(rvclkhdr_36_io_en),
|
|
.io_scan_mode(rvclkhdr_36_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_37 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_37_io_l1clk),
|
|
.io_clk(rvclkhdr_37_io_clk),
|
|
.io_en(rvclkhdr_37_io_en),
|
|
.io_scan_mode(rvclkhdr_37_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_38 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_38_io_l1clk),
|
|
.io_clk(rvclkhdr_38_io_clk),
|
|
.io_en(rvclkhdr_38_io_en),
|
|
.io_scan_mode(rvclkhdr_38_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_39 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_39_io_l1clk),
|
|
.io_clk(rvclkhdr_39_io_clk),
|
|
.io_en(rvclkhdr_39_io_en),
|
|
.io_scan_mode(rvclkhdr_39_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_40 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_40_io_l1clk),
|
|
.io_clk(rvclkhdr_40_io_clk),
|
|
.io_en(rvclkhdr_40_io_en),
|
|
.io_scan_mode(rvclkhdr_40_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_41 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_41_io_l1clk),
|
|
.io_clk(rvclkhdr_41_io_clk),
|
|
.io_en(rvclkhdr_41_io_en),
|
|
.io_scan_mode(rvclkhdr_41_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_42 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_42_io_l1clk),
|
|
.io_clk(rvclkhdr_42_io_clk),
|
|
.io_en(rvclkhdr_42_io_en),
|
|
.io_scan_mode(rvclkhdr_42_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_43 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_43_io_l1clk),
|
|
.io_clk(rvclkhdr_43_io_clk),
|
|
.io_en(rvclkhdr_43_io_en),
|
|
.io_scan_mode(rvclkhdr_43_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_44 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_44_io_l1clk),
|
|
.io_clk(rvclkhdr_44_io_clk),
|
|
.io_en(rvclkhdr_44_io_en),
|
|
.io_scan_mode(rvclkhdr_44_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_45 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_45_io_l1clk),
|
|
.io_clk(rvclkhdr_45_io_clk),
|
|
.io_en(rvclkhdr_45_io_en),
|
|
.io_scan_mode(rvclkhdr_45_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_46 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_46_io_l1clk),
|
|
.io_clk(rvclkhdr_46_io_clk),
|
|
.io_en(rvclkhdr_46_io_en),
|
|
.io_scan_mode(rvclkhdr_46_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_47 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_47_io_l1clk),
|
|
.io_clk(rvclkhdr_47_io_clk),
|
|
.io_en(rvclkhdr_47_io_en),
|
|
.io_scan_mode(rvclkhdr_47_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_48 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_48_io_l1clk),
|
|
.io_clk(rvclkhdr_48_io_clk),
|
|
.io_en(rvclkhdr_48_io_en),
|
|
.io_scan_mode(rvclkhdr_48_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_49 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_49_io_l1clk),
|
|
.io_clk(rvclkhdr_49_io_clk),
|
|
.io_en(rvclkhdr_49_io_en),
|
|
.io_scan_mode(rvclkhdr_49_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_50 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_50_io_l1clk),
|
|
.io_clk(rvclkhdr_50_io_clk),
|
|
.io_en(rvclkhdr_50_io_en),
|
|
.io_scan_mode(rvclkhdr_50_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_51 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_51_io_l1clk),
|
|
.io_clk(rvclkhdr_51_io_clk),
|
|
.io_en(rvclkhdr_51_io_en),
|
|
.io_scan_mode(rvclkhdr_51_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_52 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_52_io_l1clk),
|
|
.io_clk(rvclkhdr_52_io_clk),
|
|
.io_en(rvclkhdr_52_io_en),
|
|
.io_scan_mode(rvclkhdr_52_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_53 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_53_io_l1clk),
|
|
.io_clk(rvclkhdr_53_io_clk),
|
|
.io_en(rvclkhdr_53_io_en),
|
|
.io_scan_mode(rvclkhdr_53_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_54 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_54_io_l1clk),
|
|
.io_clk(rvclkhdr_54_io_clk),
|
|
.io_en(rvclkhdr_54_io_en),
|
|
.io_scan_mode(rvclkhdr_54_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_55 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_55_io_l1clk),
|
|
.io_clk(rvclkhdr_55_io_clk),
|
|
.io_en(rvclkhdr_55_io_en),
|
|
.io_scan_mode(rvclkhdr_55_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_56 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_56_io_l1clk),
|
|
.io_clk(rvclkhdr_56_io_clk),
|
|
.io_en(rvclkhdr_56_io_en),
|
|
.io_scan_mode(rvclkhdr_56_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_57 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_57_io_l1clk),
|
|
.io_clk(rvclkhdr_57_io_clk),
|
|
.io_en(rvclkhdr_57_io_en),
|
|
.io_scan_mode(rvclkhdr_57_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_58 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_58_io_l1clk),
|
|
.io_clk(rvclkhdr_58_io_clk),
|
|
.io_en(rvclkhdr_58_io_en),
|
|
.io_scan_mode(rvclkhdr_58_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_59 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_59_io_l1clk),
|
|
.io_clk(rvclkhdr_59_io_clk),
|
|
.io_en(rvclkhdr_59_io_en),
|
|
.io_scan_mode(rvclkhdr_59_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_60 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_60_io_l1clk),
|
|
.io_clk(rvclkhdr_60_io_clk),
|
|
.io_en(rvclkhdr_60_io_en),
|
|
.io_scan_mode(rvclkhdr_60_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_61 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_61_io_l1clk),
|
|
.io_clk(rvclkhdr_61_io_clk),
|
|
.io_en(rvclkhdr_61_io_en),
|
|
.io_scan_mode(rvclkhdr_61_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_62 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_62_io_l1clk),
|
|
.io_clk(rvclkhdr_62_io_clk),
|
|
.io_en(rvclkhdr_62_io_en),
|
|
.io_scan_mode(rvclkhdr_62_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_63 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_63_io_l1clk),
|
|
.io_clk(rvclkhdr_63_io_clk),
|
|
.io_en(rvclkhdr_63_io_en),
|
|
.io_scan_mode(rvclkhdr_63_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_64 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_64_io_l1clk),
|
|
.io_clk(rvclkhdr_64_io_clk),
|
|
.io_en(rvclkhdr_64_io_en),
|
|
.io_scan_mode(rvclkhdr_64_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_65 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_65_io_l1clk),
|
|
.io_clk(rvclkhdr_65_io_clk),
|
|
.io_en(rvclkhdr_65_io_en),
|
|
.io_scan_mode(rvclkhdr_65_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_66 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_66_io_l1clk),
|
|
.io_clk(rvclkhdr_66_io_clk),
|
|
.io_en(rvclkhdr_66_io_en),
|
|
.io_scan_mode(rvclkhdr_66_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_67 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_67_io_l1clk),
|
|
.io_clk(rvclkhdr_67_io_clk),
|
|
.io_en(rvclkhdr_67_io_en),
|
|
.io_scan_mode(rvclkhdr_67_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_68 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_68_io_l1clk),
|
|
.io_clk(rvclkhdr_68_io_clk),
|
|
.io_en(rvclkhdr_68_io_en),
|
|
.io_scan_mode(rvclkhdr_68_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_69 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_69_io_l1clk),
|
|
.io_clk(rvclkhdr_69_io_clk),
|
|
.io_en(rvclkhdr_69_io_en),
|
|
.io_scan_mode(rvclkhdr_69_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_70 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_70_io_l1clk),
|
|
.io_clk(rvclkhdr_70_io_clk),
|
|
.io_en(rvclkhdr_70_io_en),
|
|
.io_scan_mode(rvclkhdr_70_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_71 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_71_io_l1clk),
|
|
.io_clk(rvclkhdr_71_io_clk),
|
|
.io_en(rvclkhdr_71_io_en),
|
|
.io_scan_mode(rvclkhdr_71_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_72 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_72_io_l1clk),
|
|
.io_clk(rvclkhdr_72_io_clk),
|
|
.io_en(rvclkhdr_72_io_en),
|
|
.io_scan_mode(rvclkhdr_72_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_73 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_73_io_l1clk),
|
|
.io_clk(rvclkhdr_73_io_clk),
|
|
.io_en(rvclkhdr_73_io_en),
|
|
.io_scan_mode(rvclkhdr_73_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_74 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_74_io_l1clk),
|
|
.io_clk(rvclkhdr_74_io_clk),
|
|
.io_en(rvclkhdr_74_io_en),
|
|
.io_scan_mode(rvclkhdr_74_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_75 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_75_io_l1clk),
|
|
.io_clk(rvclkhdr_75_io_clk),
|
|
.io_en(rvclkhdr_75_io_en),
|
|
.io_scan_mode(rvclkhdr_75_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_76 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_76_io_l1clk),
|
|
.io_clk(rvclkhdr_76_io_clk),
|
|
.io_en(rvclkhdr_76_io_en),
|
|
.io_scan_mode(rvclkhdr_76_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_77 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_77_io_l1clk),
|
|
.io_clk(rvclkhdr_77_io_clk),
|
|
.io_en(rvclkhdr_77_io_en),
|
|
.io_scan_mode(rvclkhdr_77_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_78 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_78_io_l1clk),
|
|
.io_clk(rvclkhdr_78_io_clk),
|
|
.io_en(rvclkhdr_78_io_en),
|
|
.io_scan_mode(rvclkhdr_78_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_79 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_79_io_l1clk),
|
|
.io_clk(rvclkhdr_79_io_clk),
|
|
.io_en(rvclkhdr_79_io_en),
|
|
.io_scan_mode(rvclkhdr_79_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_80 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_80_io_l1clk),
|
|
.io_clk(rvclkhdr_80_io_clk),
|
|
.io_en(rvclkhdr_80_io_en),
|
|
.io_scan_mode(rvclkhdr_80_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_81 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_81_io_l1clk),
|
|
.io_clk(rvclkhdr_81_io_clk),
|
|
.io_en(rvclkhdr_81_io_en),
|
|
.io_scan_mode(rvclkhdr_81_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_82 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_82_io_l1clk),
|
|
.io_clk(rvclkhdr_82_io_clk),
|
|
.io_en(rvclkhdr_82_io_en),
|
|
.io_scan_mode(rvclkhdr_82_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_83 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_83_io_l1clk),
|
|
.io_clk(rvclkhdr_83_io_clk),
|
|
.io_en(rvclkhdr_83_io_en),
|
|
.io_scan_mode(rvclkhdr_83_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_84 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_84_io_l1clk),
|
|
.io_clk(rvclkhdr_84_io_clk),
|
|
.io_en(rvclkhdr_84_io_en),
|
|
.io_scan_mode(rvclkhdr_84_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_85 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_85_io_l1clk),
|
|
.io_clk(rvclkhdr_85_io_clk),
|
|
.io_en(rvclkhdr_85_io_en),
|
|
.io_scan_mode(rvclkhdr_85_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_86 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_86_io_l1clk),
|
|
.io_clk(rvclkhdr_86_io_clk),
|
|
.io_en(rvclkhdr_86_io_en),
|
|
.io_scan_mode(rvclkhdr_86_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_87 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_87_io_l1clk),
|
|
.io_clk(rvclkhdr_87_io_clk),
|
|
.io_en(rvclkhdr_87_io_en),
|
|
.io_scan_mode(rvclkhdr_87_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_88 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_88_io_l1clk),
|
|
.io_clk(rvclkhdr_88_io_clk),
|
|
.io_en(rvclkhdr_88_io_en),
|
|
.io_scan_mode(rvclkhdr_88_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_89 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_89_io_l1clk),
|
|
.io_clk(rvclkhdr_89_io_clk),
|
|
.io_en(rvclkhdr_89_io_en),
|
|
.io_scan_mode(rvclkhdr_89_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_90 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_90_io_l1clk),
|
|
.io_clk(rvclkhdr_90_io_clk),
|
|
.io_en(rvclkhdr_90_io_en),
|
|
.io_scan_mode(rvclkhdr_90_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_91 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_91_io_l1clk),
|
|
.io_clk(rvclkhdr_91_io_clk),
|
|
.io_en(rvclkhdr_91_io_en),
|
|
.io_scan_mode(rvclkhdr_91_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_92 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_92_io_l1clk),
|
|
.io_clk(rvclkhdr_92_io_clk),
|
|
.io_en(rvclkhdr_92_io_en),
|
|
.io_scan_mode(rvclkhdr_92_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_93 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_93_io_l1clk),
|
|
.io_clk(rvclkhdr_93_io_clk),
|
|
.io_en(rvclkhdr_93_io_en),
|
|
.io_scan_mode(rvclkhdr_93_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_94 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_94_io_l1clk),
|
|
.io_clk(rvclkhdr_94_io_clk),
|
|
.io_en(rvclkhdr_94_io_en),
|
|
.io_scan_mode(rvclkhdr_94_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_95 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_95_io_l1clk),
|
|
.io_clk(rvclkhdr_95_io_clk),
|
|
.io_en(rvclkhdr_95_io_en),
|
|
.io_scan_mode(rvclkhdr_95_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_96 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_96_io_l1clk),
|
|
.io_clk(rvclkhdr_96_io_clk),
|
|
.io_en(rvclkhdr_96_io_en),
|
|
.io_scan_mode(rvclkhdr_96_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_97 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_97_io_l1clk),
|
|
.io_clk(rvclkhdr_97_io_clk),
|
|
.io_en(rvclkhdr_97_io_en),
|
|
.io_scan_mode(rvclkhdr_97_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_98 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_98_io_l1clk),
|
|
.io_clk(rvclkhdr_98_io_clk),
|
|
.io_en(rvclkhdr_98_io_en),
|
|
.io_scan_mode(rvclkhdr_98_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_99 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_99_io_l1clk),
|
|
.io_clk(rvclkhdr_99_io_clk),
|
|
.io_en(rvclkhdr_99_io_en),
|
|
.io_scan_mode(rvclkhdr_99_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_100 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_100_io_l1clk),
|
|
.io_clk(rvclkhdr_100_io_clk),
|
|
.io_en(rvclkhdr_100_io_en),
|
|
.io_scan_mode(rvclkhdr_100_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_101 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_101_io_l1clk),
|
|
.io_clk(rvclkhdr_101_io_clk),
|
|
.io_en(rvclkhdr_101_io_en),
|
|
.io_scan_mode(rvclkhdr_101_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_102 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_102_io_l1clk),
|
|
.io_clk(rvclkhdr_102_io_clk),
|
|
.io_en(rvclkhdr_102_io_en),
|
|
.io_scan_mode(rvclkhdr_102_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_103 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_103_io_l1clk),
|
|
.io_clk(rvclkhdr_103_io_clk),
|
|
.io_en(rvclkhdr_103_io_en),
|
|
.io_scan_mode(rvclkhdr_103_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_104 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_104_io_l1clk),
|
|
.io_clk(rvclkhdr_104_io_clk),
|
|
.io_en(rvclkhdr_104_io_en),
|
|
.io_scan_mode(rvclkhdr_104_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_105 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_105_io_l1clk),
|
|
.io_clk(rvclkhdr_105_io_clk),
|
|
.io_en(rvclkhdr_105_io_en),
|
|
.io_scan_mode(rvclkhdr_105_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_106 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_106_io_l1clk),
|
|
.io_clk(rvclkhdr_106_io_clk),
|
|
.io_en(rvclkhdr_106_io_en),
|
|
.io_scan_mode(rvclkhdr_106_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_107 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_107_io_l1clk),
|
|
.io_clk(rvclkhdr_107_io_clk),
|
|
.io_en(rvclkhdr_107_io_en),
|
|
.io_scan_mode(rvclkhdr_107_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_108 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_108_io_l1clk),
|
|
.io_clk(rvclkhdr_108_io_clk),
|
|
.io_en(rvclkhdr_108_io_en),
|
|
.io_scan_mode(rvclkhdr_108_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_109 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_109_io_l1clk),
|
|
.io_clk(rvclkhdr_109_io_clk),
|
|
.io_en(rvclkhdr_109_io_en),
|
|
.io_scan_mode(rvclkhdr_109_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_110 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_110_io_l1clk),
|
|
.io_clk(rvclkhdr_110_io_clk),
|
|
.io_en(rvclkhdr_110_io_en),
|
|
.io_scan_mode(rvclkhdr_110_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_111 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_111_io_l1clk),
|
|
.io_clk(rvclkhdr_111_io_clk),
|
|
.io_en(rvclkhdr_111_io_en),
|
|
.io_scan_mode(rvclkhdr_111_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_112 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_112_io_l1clk),
|
|
.io_clk(rvclkhdr_112_io_clk),
|
|
.io_en(rvclkhdr_112_io_en),
|
|
.io_scan_mode(rvclkhdr_112_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_113 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_113_io_l1clk),
|
|
.io_clk(rvclkhdr_113_io_clk),
|
|
.io_en(rvclkhdr_113_io_en),
|
|
.io_scan_mode(rvclkhdr_113_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_114 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_114_io_l1clk),
|
|
.io_clk(rvclkhdr_114_io_clk),
|
|
.io_en(rvclkhdr_114_io_en),
|
|
.io_scan_mode(rvclkhdr_114_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_115 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_115_io_l1clk),
|
|
.io_clk(rvclkhdr_115_io_clk),
|
|
.io_en(rvclkhdr_115_io_en),
|
|
.io_scan_mode(rvclkhdr_115_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_116 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_116_io_l1clk),
|
|
.io_clk(rvclkhdr_116_io_clk),
|
|
.io_en(rvclkhdr_116_io_en),
|
|
.io_scan_mode(rvclkhdr_116_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_117 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_117_io_l1clk),
|
|
.io_clk(rvclkhdr_117_io_clk),
|
|
.io_en(rvclkhdr_117_io_en),
|
|
.io_scan_mode(rvclkhdr_117_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_118 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_118_io_l1clk),
|
|
.io_clk(rvclkhdr_118_io_clk),
|
|
.io_en(rvclkhdr_118_io_en),
|
|
.io_scan_mode(rvclkhdr_118_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_119 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_119_io_l1clk),
|
|
.io_clk(rvclkhdr_119_io_clk),
|
|
.io_en(rvclkhdr_119_io_en),
|
|
.io_scan_mode(rvclkhdr_119_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_120 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_120_io_l1clk),
|
|
.io_clk(rvclkhdr_120_io_clk),
|
|
.io_en(rvclkhdr_120_io_en),
|
|
.io_scan_mode(rvclkhdr_120_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_121 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_121_io_l1clk),
|
|
.io_clk(rvclkhdr_121_io_clk),
|
|
.io_en(rvclkhdr_121_io_en),
|
|
.io_scan_mode(rvclkhdr_121_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_122 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_122_io_l1clk),
|
|
.io_clk(rvclkhdr_122_io_clk),
|
|
.io_en(rvclkhdr_122_io_en),
|
|
.io_scan_mode(rvclkhdr_122_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_123 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_123_io_l1clk),
|
|
.io_clk(rvclkhdr_123_io_clk),
|
|
.io_en(rvclkhdr_123_io_en),
|
|
.io_scan_mode(rvclkhdr_123_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_124 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_124_io_l1clk),
|
|
.io_clk(rvclkhdr_124_io_clk),
|
|
.io_en(rvclkhdr_124_io_en),
|
|
.io_scan_mode(rvclkhdr_124_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_125 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_125_io_l1clk),
|
|
.io_clk(rvclkhdr_125_io_clk),
|
|
.io_en(rvclkhdr_125_io_en),
|
|
.io_scan_mode(rvclkhdr_125_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_126 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_126_io_l1clk),
|
|
.io_clk(rvclkhdr_126_io_clk),
|
|
.io_en(rvclkhdr_126_io_en),
|
|
.io_scan_mode(rvclkhdr_126_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_127 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_127_io_l1clk),
|
|
.io_clk(rvclkhdr_127_io_clk),
|
|
.io_en(rvclkhdr_127_io_en),
|
|
.io_scan_mode(rvclkhdr_127_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_128 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_128_io_l1clk),
|
|
.io_clk(rvclkhdr_128_io_clk),
|
|
.io_en(rvclkhdr_128_io_en),
|
|
.io_scan_mode(rvclkhdr_128_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_129 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_129_io_l1clk),
|
|
.io_clk(rvclkhdr_129_io_clk),
|
|
.io_en(rvclkhdr_129_io_en),
|
|
.io_scan_mode(rvclkhdr_129_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_130 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_130_io_l1clk),
|
|
.io_clk(rvclkhdr_130_io_clk),
|
|
.io_en(rvclkhdr_130_io_en),
|
|
.io_scan_mode(rvclkhdr_130_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_131 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_131_io_l1clk),
|
|
.io_clk(rvclkhdr_131_io_clk),
|
|
.io_en(rvclkhdr_131_io_en),
|
|
.io_scan_mode(rvclkhdr_131_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_132 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_132_io_l1clk),
|
|
.io_clk(rvclkhdr_132_io_clk),
|
|
.io_en(rvclkhdr_132_io_en),
|
|
.io_scan_mode(rvclkhdr_132_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_133 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_133_io_l1clk),
|
|
.io_clk(rvclkhdr_133_io_clk),
|
|
.io_en(rvclkhdr_133_io_en),
|
|
.io_scan_mode(rvclkhdr_133_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_134 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_134_io_l1clk),
|
|
.io_clk(rvclkhdr_134_io_clk),
|
|
.io_en(rvclkhdr_134_io_en),
|
|
.io_scan_mode(rvclkhdr_134_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_135 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_135_io_l1clk),
|
|
.io_clk(rvclkhdr_135_io_clk),
|
|
.io_en(rvclkhdr_135_io_en),
|
|
.io_scan_mode(rvclkhdr_135_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_136 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_136_io_l1clk),
|
|
.io_clk(rvclkhdr_136_io_clk),
|
|
.io_en(rvclkhdr_136_io_en),
|
|
.io_scan_mode(rvclkhdr_136_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_137 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_137_io_l1clk),
|
|
.io_clk(rvclkhdr_137_io_clk),
|
|
.io_en(rvclkhdr_137_io_en),
|
|
.io_scan_mode(rvclkhdr_137_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_138 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_138_io_l1clk),
|
|
.io_clk(rvclkhdr_138_io_clk),
|
|
.io_en(rvclkhdr_138_io_en),
|
|
.io_scan_mode(rvclkhdr_138_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_139 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_139_io_l1clk),
|
|
.io_clk(rvclkhdr_139_io_clk),
|
|
.io_en(rvclkhdr_139_io_en),
|
|
.io_scan_mode(rvclkhdr_139_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_140 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_140_io_l1clk),
|
|
.io_clk(rvclkhdr_140_io_clk),
|
|
.io_en(rvclkhdr_140_io_en),
|
|
.io_scan_mode(rvclkhdr_140_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_141 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_141_io_l1clk),
|
|
.io_clk(rvclkhdr_141_io_clk),
|
|
.io_en(rvclkhdr_141_io_en),
|
|
.io_scan_mode(rvclkhdr_141_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_142 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_142_io_l1clk),
|
|
.io_clk(rvclkhdr_142_io_clk),
|
|
.io_en(rvclkhdr_142_io_en),
|
|
.io_scan_mode(rvclkhdr_142_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_143 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_143_io_l1clk),
|
|
.io_clk(rvclkhdr_143_io_clk),
|
|
.io_en(rvclkhdr_143_io_en),
|
|
.io_scan_mode(rvclkhdr_143_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_144 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_144_io_l1clk),
|
|
.io_clk(rvclkhdr_144_io_clk),
|
|
.io_en(rvclkhdr_144_io_en),
|
|
.io_scan_mode(rvclkhdr_144_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_145 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_145_io_l1clk),
|
|
.io_clk(rvclkhdr_145_io_clk),
|
|
.io_en(rvclkhdr_145_io_en),
|
|
.io_scan_mode(rvclkhdr_145_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_146 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_146_io_l1clk),
|
|
.io_clk(rvclkhdr_146_io_clk),
|
|
.io_en(rvclkhdr_146_io_en),
|
|
.io_scan_mode(rvclkhdr_146_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_147 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_147_io_l1clk),
|
|
.io_clk(rvclkhdr_147_io_clk),
|
|
.io_en(rvclkhdr_147_io_en),
|
|
.io_scan_mode(rvclkhdr_147_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_148 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_148_io_l1clk),
|
|
.io_clk(rvclkhdr_148_io_clk),
|
|
.io_en(rvclkhdr_148_io_en),
|
|
.io_scan_mode(rvclkhdr_148_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_149 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_149_io_l1clk),
|
|
.io_clk(rvclkhdr_149_io_clk),
|
|
.io_en(rvclkhdr_149_io_en),
|
|
.io_scan_mode(rvclkhdr_149_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_150 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_150_io_l1clk),
|
|
.io_clk(rvclkhdr_150_io_clk),
|
|
.io_en(rvclkhdr_150_io_en),
|
|
.io_scan_mode(rvclkhdr_150_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_151 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_151_io_l1clk),
|
|
.io_clk(rvclkhdr_151_io_clk),
|
|
.io_en(rvclkhdr_151_io_en),
|
|
.io_scan_mode(rvclkhdr_151_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_152 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_152_io_l1clk),
|
|
.io_clk(rvclkhdr_152_io_clk),
|
|
.io_en(rvclkhdr_152_io_en),
|
|
.io_scan_mode(rvclkhdr_152_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_153 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_153_io_l1clk),
|
|
.io_clk(rvclkhdr_153_io_clk),
|
|
.io_en(rvclkhdr_153_io_en),
|
|
.io_scan_mode(rvclkhdr_153_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_154 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_154_io_l1clk),
|
|
.io_clk(rvclkhdr_154_io_clk),
|
|
.io_en(rvclkhdr_154_io_en),
|
|
.io_scan_mode(rvclkhdr_154_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_155 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_155_io_l1clk),
|
|
.io_clk(rvclkhdr_155_io_clk),
|
|
.io_en(rvclkhdr_155_io_en),
|
|
.io_scan_mode(rvclkhdr_155_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_156 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_156_io_l1clk),
|
|
.io_clk(rvclkhdr_156_io_clk),
|
|
.io_en(rvclkhdr_156_io_en),
|
|
.io_scan_mode(rvclkhdr_156_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_157 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_157_io_l1clk),
|
|
.io_clk(rvclkhdr_157_io_clk),
|
|
.io_en(rvclkhdr_157_io_en),
|
|
.io_scan_mode(rvclkhdr_157_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_158 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_158_io_l1clk),
|
|
.io_clk(rvclkhdr_158_io_clk),
|
|
.io_en(rvclkhdr_158_io_en),
|
|
.io_scan_mode(rvclkhdr_158_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_159 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_159_io_l1clk),
|
|
.io_clk(rvclkhdr_159_io_clk),
|
|
.io_en(rvclkhdr_159_io_en),
|
|
.io_scan_mode(rvclkhdr_159_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_160 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_160_io_l1clk),
|
|
.io_clk(rvclkhdr_160_io_clk),
|
|
.io_en(rvclkhdr_160_io_en),
|
|
.io_scan_mode(rvclkhdr_160_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_161 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_161_io_l1clk),
|
|
.io_clk(rvclkhdr_161_io_clk),
|
|
.io_en(rvclkhdr_161_io_en),
|
|
.io_scan_mode(rvclkhdr_161_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_162 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_162_io_l1clk),
|
|
.io_clk(rvclkhdr_162_io_clk),
|
|
.io_en(rvclkhdr_162_io_en),
|
|
.io_scan_mode(rvclkhdr_162_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_163 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_163_io_l1clk),
|
|
.io_clk(rvclkhdr_163_io_clk),
|
|
.io_en(rvclkhdr_163_io_en),
|
|
.io_scan_mode(rvclkhdr_163_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_164 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_164_io_l1clk),
|
|
.io_clk(rvclkhdr_164_io_clk),
|
|
.io_en(rvclkhdr_164_io_en),
|
|
.io_scan_mode(rvclkhdr_164_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_165 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_165_io_l1clk),
|
|
.io_clk(rvclkhdr_165_io_clk),
|
|
.io_en(rvclkhdr_165_io_en),
|
|
.io_scan_mode(rvclkhdr_165_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_166 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_166_io_l1clk),
|
|
.io_clk(rvclkhdr_166_io_clk),
|
|
.io_en(rvclkhdr_166_io_en),
|
|
.io_scan_mode(rvclkhdr_166_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_167 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_167_io_l1clk),
|
|
.io_clk(rvclkhdr_167_io_clk),
|
|
.io_en(rvclkhdr_167_io_en),
|
|
.io_scan_mode(rvclkhdr_167_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_168 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_168_io_l1clk),
|
|
.io_clk(rvclkhdr_168_io_clk),
|
|
.io_en(rvclkhdr_168_io_en),
|
|
.io_scan_mode(rvclkhdr_168_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_169 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_169_io_l1clk),
|
|
.io_clk(rvclkhdr_169_io_clk),
|
|
.io_en(rvclkhdr_169_io_en),
|
|
.io_scan_mode(rvclkhdr_169_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_170 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_170_io_l1clk),
|
|
.io_clk(rvclkhdr_170_io_clk),
|
|
.io_en(rvclkhdr_170_io_en),
|
|
.io_scan_mode(rvclkhdr_170_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_171 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_171_io_l1clk),
|
|
.io_clk(rvclkhdr_171_io_clk),
|
|
.io_en(rvclkhdr_171_io_en),
|
|
.io_scan_mode(rvclkhdr_171_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_172 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_172_io_l1clk),
|
|
.io_clk(rvclkhdr_172_io_clk),
|
|
.io_en(rvclkhdr_172_io_en),
|
|
.io_scan_mode(rvclkhdr_172_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_173 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_173_io_l1clk),
|
|
.io_clk(rvclkhdr_173_io_clk),
|
|
.io_en(rvclkhdr_173_io_en),
|
|
.io_scan_mode(rvclkhdr_173_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_174 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_174_io_l1clk),
|
|
.io_clk(rvclkhdr_174_io_clk),
|
|
.io_en(rvclkhdr_174_io_en),
|
|
.io_scan_mode(rvclkhdr_174_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_175 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_175_io_l1clk),
|
|
.io_clk(rvclkhdr_175_io_clk),
|
|
.io_en(rvclkhdr_175_io_en),
|
|
.io_scan_mode(rvclkhdr_175_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_176 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_176_io_l1clk),
|
|
.io_clk(rvclkhdr_176_io_clk),
|
|
.io_en(rvclkhdr_176_io_en),
|
|
.io_scan_mode(rvclkhdr_176_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_177 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_177_io_l1clk),
|
|
.io_clk(rvclkhdr_177_io_clk),
|
|
.io_en(rvclkhdr_177_io_en),
|
|
.io_scan_mode(rvclkhdr_177_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_178 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_178_io_l1clk),
|
|
.io_clk(rvclkhdr_178_io_clk),
|
|
.io_en(rvclkhdr_178_io_en),
|
|
.io_scan_mode(rvclkhdr_178_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_179 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_179_io_l1clk),
|
|
.io_clk(rvclkhdr_179_io_clk),
|
|
.io_en(rvclkhdr_179_io_en),
|
|
.io_scan_mode(rvclkhdr_179_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_180 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_180_io_l1clk),
|
|
.io_clk(rvclkhdr_180_io_clk),
|
|
.io_en(rvclkhdr_180_io_en),
|
|
.io_scan_mode(rvclkhdr_180_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_181 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_181_io_l1clk),
|
|
.io_clk(rvclkhdr_181_io_clk),
|
|
.io_en(rvclkhdr_181_io_en),
|
|
.io_scan_mode(rvclkhdr_181_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_182 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_182_io_l1clk),
|
|
.io_clk(rvclkhdr_182_io_clk),
|
|
.io_en(rvclkhdr_182_io_en),
|
|
.io_scan_mode(rvclkhdr_182_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_183 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_183_io_l1clk),
|
|
.io_clk(rvclkhdr_183_io_clk),
|
|
.io_en(rvclkhdr_183_io_en),
|
|
.io_scan_mode(rvclkhdr_183_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_184 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_184_io_l1clk),
|
|
.io_clk(rvclkhdr_184_io_clk),
|
|
.io_en(rvclkhdr_184_io_en),
|
|
.io_scan_mode(rvclkhdr_184_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_185 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_185_io_l1clk),
|
|
.io_clk(rvclkhdr_185_io_clk),
|
|
.io_en(rvclkhdr_185_io_en),
|
|
.io_scan_mode(rvclkhdr_185_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_186 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_186_io_l1clk),
|
|
.io_clk(rvclkhdr_186_io_clk),
|
|
.io_en(rvclkhdr_186_io_en),
|
|
.io_scan_mode(rvclkhdr_186_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_187 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_187_io_l1clk),
|
|
.io_clk(rvclkhdr_187_io_clk),
|
|
.io_en(rvclkhdr_187_io_en),
|
|
.io_scan_mode(rvclkhdr_187_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_188 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_188_io_l1clk),
|
|
.io_clk(rvclkhdr_188_io_clk),
|
|
.io_en(rvclkhdr_188_io_en),
|
|
.io_scan_mode(rvclkhdr_188_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_189 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_189_io_l1clk),
|
|
.io_clk(rvclkhdr_189_io_clk),
|
|
.io_en(rvclkhdr_189_io_en),
|
|
.io_scan_mode(rvclkhdr_189_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_190 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_190_io_l1clk),
|
|
.io_clk(rvclkhdr_190_io_clk),
|
|
.io_en(rvclkhdr_190_io_en),
|
|
.io_scan_mode(rvclkhdr_190_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_191 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_191_io_l1clk),
|
|
.io_clk(rvclkhdr_191_io_clk),
|
|
.io_en(rvclkhdr_191_io_en),
|
|
.io_scan_mode(rvclkhdr_191_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_192 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_192_io_l1clk),
|
|
.io_clk(rvclkhdr_192_io_clk),
|
|
.io_en(rvclkhdr_192_io_en),
|
|
.io_scan_mode(rvclkhdr_192_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_193 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_193_io_l1clk),
|
|
.io_clk(rvclkhdr_193_io_clk),
|
|
.io_en(rvclkhdr_193_io_en),
|
|
.io_scan_mode(rvclkhdr_193_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_194 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_194_io_l1clk),
|
|
.io_clk(rvclkhdr_194_io_clk),
|
|
.io_en(rvclkhdr_194_io_en),
|
|
.io_scan_mode(rvclkhdr_194_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_195 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_195_io_l1clk),
|
|
.io_clk(rvclkhdr_195_io_clk),
|
|
.io_en(rvclkhdr_195_io_en),
|
|
.io_scan_mode(rvclkhdr_195_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_196 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_196_io_l1clk),
|
|
.io_clk(rvclkhdr_196_io_clk),
|
|
.io_en(rvclkhdr_196_io_en),
|
|
.io_scan_mode(rvclkhdr_196_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_197 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_197_io_l1clk),
|
|
.io_clk(rvclkhdr_197_io_clk),
|
|
.io_en(rvclkhdr_197_io_en),
|
|
.io_scan_mode(rvclkhdr_197_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_198 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_198_io_l1clk),
|
|
.io_clk(rvclkhdr_198_io_clk),
|
|
.io_en(rvclkhdr_198_io_en),
|
|
.io_scan_mode(rvclkhdr_198_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_199 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_199_io_l1clk),
|
|
.io_clk(rvclkhdr_199_io_clk),
|
|
.io_en(rvclkhdr_199_io_en),
|
|
.io_scan_mode(rvclkhdr_199_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_200 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_200_io_l1clk),
|
|
.io_clk(rvclkhdr_200_io_clk),
|
|
.io_en(rvclkhdr_200_io_en),
|
|
.io_scan_mode(rvclkhdr_200_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_201 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_201_io_l1clk),
|
|
.io_clk(rvclkhdr_201_io_clk),
|
|
.io_en(rvclkhdr_201_io_en),
|
|
.io_scan_mode(rvclkhdr_201_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_202 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_202_io_l1clk),
|
|
.io_clk(rvclkhdr_202_io_clk),
|
|
.io_en(rvclkhdr_202_io_en),
|
|
.io_scan_mode(rvclkhdr_202_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_203 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_203_io_l1clk),
|
|
.io_clk(rvclkhdr_203_io_clk),
|
|
.io_en(rvclkhdr_203_io_en),
|
|
.io_scan_mode(rvclkhdr_203_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_204 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_204_io_l1clk),
|
|
.io_clk(rvclkhdr_204_io_clk),
|
|
.io_en(rvclkhdr_204_io_en),
|
|
.io_scan_mode(rvclkhdr_204_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_205 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_205_io_l1clk),
|
|
.io_clk(rvclkhdr_205_io_clk),
|
|
.io_en(rvclkhdr_205_io_en),
|
|
.io_scan_mode(rvclkhdr_205_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_206 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_206_io_l1clk),
|
|
.io_clk(rvclkhdr_206_io_clk),
|
|
.io_en(rvclkhdr_206_io_en),
|
|
.io_scan_mode(rvclkhdr_206_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_207 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_207_io_l1clk),
|
|
.io_clk(rvclkhdr_207_io_clk),
|
|
.io_en(rvclkhdr_207_io_en),
|
|
.io_scan_mode(rvclkhdr_207_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_208 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_208_io_l1clk),
|
|
.io_clk(rvclkhdr_208_io_clk),
|
|
.io_en(rvclkhdr_208_io_en),
|
|
.io_scan_mode(rvclkhdr_208_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_209 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_209_io_l1clk),
|
|
.io_clk(rvclkhdr_209_io_clk),
|
|
.io_en(rvclkhdr_209_io_en),
|
|
.io_scan_mode(rvclkhdr_209_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_210 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_210_io_l1clk),
|
|
.io_clk(rvclkhdr_210_io_clk),
|
|
.io_en(rvclkhdr_210_io_en),
|
|
.io_scan_mode(rvclkhdr_210_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_211 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_211_io_l1clk),
|
|
.io_clk(rvclkhdr_211_io_clk),
|
|
.io_en(rvclkhdr_211_io_en),
|
|
.io_scan_mode(rvclkhdr_211_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_212 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_212_io_l1clk),
|
|
.io_clk(rvclkhdr_212_io_clk),
|
|
.io_en(rvclkhdr_212_io_en),
|
|
.io_scan_mode(rvclkhdr_212_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_213 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_213_io_l1clk),
|
|
.io_clk(rvclkhdr_213_io_clk),
|
|
.io_en(rvclkhdr_213_io_en),
|
|
.io_scan_mode(rvclkhdr_213_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_214 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_214_io_l1clk),
|
|
.io_clk(rvclkhdr_214_io_clk),
|
|
.io_en(rvclkhdr_214_io_en),
|
|
.io_scan_mode(rvclkhdr_214_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_215 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_215_io_l1clk),
|
|
.io_clk(rvclkhdr_215_io_clk),
|
|
.io_en(rvclkhdr_215_io_en),
|
|
.io_scan_mode(rvclkhdr_215_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_216 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_216_io_l1clk),
|
|
.io_clk(rvclkhdr_216_io_clk),
|
|
.io_en(rvclkhdr_216_io_en),
|
|
.io_scan_mode(rvclkhdr_216_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_217 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_217_io_l1clk),
|
|
.io_clk(rvclkhdr_217_io_clk),
|
|
.io_en(rvclkhdr_217_io_en),
|
|
.io_scan_mode(rvclkhdr_217_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_218 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_218_io_l1clk),
|
|
.io_clk(rvclkhdr_218_io_clk),
|
|
.io_en(rvclkhdr_218_io_en),
|
|
.io_scan_mode(rvclkhdr_218_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_219 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_219_io_l1clk),
|
|
.io_clk(rvclkhdr_219_io_clk),
|
|
.io_en(rvclkhdr_219_io_en),
|
|
.io_scan_mode(rvclkhdr_219_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_220 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_220_io_l1clk),
|
|
.io_clk(rvclkhdr_220_io_clk),
|
|
.io_en(rvclkhdr_220_io_en),
|
|
.io_scan_mode(rvclkhdr_220_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_221 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_221_io_l1clk),
|
|
.io_clk(rvclkhdr_221_io_clk),
|
|
.io_en(rvclkhdr_221_io_en),
|
|
.io_scan_mode(rvclkhdr_221_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_222 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_222_io_l1clk),
|
|
.io_clk(rvclkhdr_222_io_clk),
|
|
.io_en(rvclkhdr_222_io_en),
|
|
.io_scan_mode(rvclkhdr_222_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_223 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_223_io_l1clk),
|
|
.io_clk(rvclkhdr_223_io_clk),
|
|
.io_en(rvclkhdr_223_io_en),
|
|
.io_scan_mode(rvclkhdr_223_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_224 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_224_io_l1clk),
|
|
.io_clk(rvclkhdr_224_io_clk),
|
|
.io_en(rvclkhdr_224_io_en),
|
|
.io_scan_mode(rvclkhdr_224_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_225 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_225_io_l1clk),
|
|
.io_clk(rvclkhdr_225_io_clk),
|
|
.io_en(rvclkhdr_225_io_en),
|
|
.io_scan_mode(rvclkhdr_225_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_226 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_226_io_l1clk),
|
|
.io_clk(rvclkhdr_226_io_clk),
|
|
.io_en(rvclkhdr_226_io_en),
|
|
.io_scan_mode(rvclkhdr_226_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_227 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_227_io_l1clk),
|
|
.io_clk(rvclkhdr_227_io_clk),
|
|
.io_en(rvclkhdr_227_io_en),
|
|
.io_scan_mode(rvclkhdr_227_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_228 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_228_io_l1clk),
|
|
.io_clk(rvclkhdr_228_io_clk),
|
|
.io_en(rvclkhdr_228_io_en),
|
|
.io_scan_mode(rvclkhdr_228_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_229 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_229_io_l1clk),
|
|
.io_clk(rvclkhdr_229_io_clk),
|
|
.io_en(rvclkhdr_229_io_en),
|
|
.io_scan_mode(rvclkhdr_229_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_230 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_230_io_l1clk),
|
|
.io_clk(rvclkhdr_230_io_clk),
|
|
.io_en(rvclkhdr_230_io_en),
|
|
.io_scan_mode(rvclkhdr_230_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_231 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_231_io_l1clk),
|
|
.io_clk(rvclkhdr_231_io_clk),
|
|
.io_en(rvclkhdr_231_io_en),
|
|
.io_scan_mode(rvclkhdr_231_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_232 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_232_io_l1clk),
|
|
.io_clk(rvclkhdr_232_io_clk),
|
|
.io_en(rvclkhdr_232_io_en),
|
|
.io_scan_mode(rvclkhdr_232_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_233 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_233_io_l1clk),
|
|
.io_clk(rvclkhdr_233_io_clk),
|
|
.io_en(rvclkhdr_233_io_en),
|
|
.io_scan_mode(rvclkhdr_233_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_234 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_234_io_l1clk),
|
|
.io_clk(rvclkhdr_234_io_clk),
|
|
.io_en(rvclkhdr_234_io_en),
|
|
.io_scan_mode(rvclkhdr_234_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_235 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_235_io_l1clk),
|
|
.io_clk(rvclkhdr_235_io_clk),
|
|
.io_en(rvclkhdr_235_io_en),
|
|
.io_scan_mode(rvclkhdr_235_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_236 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_236_io_l1clk),
|
|
.io_clk(rvclkhdr_236_io_clk),
|
|
.io_en(rvclkhdr_236_io_en),
|
|
.io_scan_mode(rvclkhdr_236_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_237 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_237_io_l1clk),
|
|
.io_clk(rvclkhdr_237_io_clk),
|
|
.io_en(rvclkhdr_237_io_en),
|
|
.io_scan_mode(rvclkhdr_237_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_238 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_238_io_l1clk),
|
|
.io_clk(rvclkhdr_238_io_clk),
|
|
.io_en(rvclkhdr_238_io_en),
|
|
.io_scan_mode(rvclkhdr_238_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_239 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_239_io_l1clk),
|
|
.io_clk(rvclkhdr_239_io_clk),
|
|
.io_en(rvclkhdr_239_io_en),
|
|
.io_scan_mode(rvclkhdr_239_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_240 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_240_io_l1clk),
|
|
.io_clk(rvclkhdr_240_io_clk),
|
|
.io_en(rvclkhdr_240_io_en),
|
|
.io_scan_mode(rvclkhdr_240_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_241 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_241_io_l1clk),
|
|
.io_clk(rvclkhdr_241_io_clk),
|
|
.io_en(rvclkhdr_241_io_en),
|
|
.io_scan_mode(rvclkhdr_241_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_242 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_242_io_l1clk),
|
|
.io_clk(rvclkhdr_242_io_clk),
|
|
.io_en(rvclkhdr_242_io_en),
|
|
.io_scan_mode(rvclkhdr_242_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_243 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_243_io_l1clk),
|
|
.io_clk(rvclkhdr_243_io_clk),
|
|
.io_en(rvclkhdr_243_io_en),
|
|
.io_scan_mode(rvclkhdr_243_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_244 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_244_io_l1clk),
|
|
.io_clk(rvclkhdr_244_io_clk),
|
|
.io_en(rvclkhdr_244_io_en),
|
|
.io_scan_mode(rvclkhdr_244_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_245 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_245_io_l1clk),
|
|
.io_clk(rvclkhdr_245_io_clk),
|
|
.io_en(rvclkhdr_245_io_en),
|
|
.io_scan_mode(rvclkhdr_245_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_246 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_246_io_l1clk),
|
|
.io_clk(rvclkhdr_246_io_clk),
|
|
.io_en(rvclkhdr_246_io_en),
|
|
.io_scan_mode(rvclkhdr_246_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_247 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_247_io_l1clk),
|
|
.io_clk(rvclkhdr_247_io_clk),
|
|
.io_en(rvclkhdr_247_io_en),
|
|
.io_scan_mode(rvclkhdr_247_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_248 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_248_io_l1clk),
|
|
.io_clk(rvclkhdr_248_io_clk),
|
|
.io_en(rvclkhdr_248_io_en),
|
|
.io_scan_mode(rvclkhdr_248_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_249 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_249_io_l1clk),
|
|
.io_clk(rvclkhdr_249_io_clk),
|
|
.io_en(rvclkhdr_249_io_en),
|
|
.io_scan_mode(rvclkhdr_249_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_250 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_250_io_l1clk),
|
|
.io_clk(rvclkhdr_250_io_clk),
|
|
.io_en(rvclkhdr_250_io_en),
|
|
.io_scan_mode(rvclkhdr_250_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_251 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_251_io_l1clk),
|
|
.io_clk(rvclkhdr_251_io_clk),
|
|
.io_en(rvclkhdr_251_io_en),
|
|
.io_scan_mode(rvclkhdr_251_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_252 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_252_io_l1clk),
|
|
.io_clk(rvclkhdr_252_io_clk),
|
|
.io_en(rvclkhdr_252_io_en),
|
|
.io_scan_mode(rvclkhdr_252_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_253 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_253_io_l1clk),
|
|
.io_clk(rvclkhdr_253_io_clk),
|
|
.io_en(rvclkhdr_253_io_en),
|
|
.io_scan_mode(rvclkhdr_253_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_254 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_254_io_l1clk),
|
|
.io_clk(rvclkhdr_254_io_clk),
|
|
.io_en(rvclkhdr_254_io_en),
|
|
.io_scan_mode(rvclkhdr_254_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_255 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_255_io_l1clk),
|
|
.io_clk(rvclkhdr_255_io_clk),
|
|
.io_en(rvclkhdr_255_io_en),
|
|
.io_scan_mode(rvclkhdr_255_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_256 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_256_io_l1clk),
|
|
.io_clk(rvclkhdr_256_io_clk),
|
|
.io_en(rvclkhdr_256_io_en),
|
|
.io_scan_mode(rvclkhdr_256_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_257 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_257_io_l1clk),
|
|
.io_clk(rvclkhdr_257_io_clk),
|
|
.io_en(rvclkhdr_257_io_en),
|
|
.io_scan_mode(rvclkhdr_257_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_258 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_258_io_l1clk),
|
|
.io_clk(rvclkhdr_258_io_clk),
|
|
.io_en(rvclkhdr_258_io_en),
|
|
.io_scan_mode(rvclkhdr_258_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_259 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_259_io_l1clk),
|
|
.io_clk(rvclkhdr_259_io_clk),
|
|
.io_en(rvclkhdr_259_io_en),
|
|
.io_scan_mode(rvclkhdr_259_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_260 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_260_io_l1clk),
|
|
.io_clk(rvclkhdr_260_io_clk),
|
|
.io_en(rvclkhdr_260_io_en),
|
|
.io_scan_mode(rvclkhdr_260_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_261 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_261_io_l1clk),
|
|
.io_clk(rvclkhdr_261_io_clk),
|
|
.io_en(rvclkhdr_261_io_en),
|
|
.io_scan_mode(rvclkhdr_261_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_262 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_262_io_l1clk),
|
|
.io_clk(rvclkhdr_262_io_clk),
|
|
.io_en(rvclkhdr_262_io_en),
|
|
.io_scan_mode(rvclkhdr_262_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_263 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_263_io_l1clk),
|
|
.io_clk(rvclkhdr_263_io_clk),
|
|
.io_en(rvclkhdr_263_io_en),
|
|
.io_scan_mode(rvclkhdr_263_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_264 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_264_io_l1clk),
|
|
.io_clk(rvclkhdr_264_io_clk),
|
|
.io_en(rvclkhdr_264_io_en),
|
|
.io_scan_mode(rvclkhdr_264_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_265 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_265_io_l1clk),
|
|
.io_clk(rvclkhdr_265_io_clk),
|
|
.io_en(rvclkhdr_265_io_en),
|
|
.io_scan_mode(rvclkhdr_265_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_266 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_266_io_l1clk),
|
|
.io_clk(rvclkhdr_266_io_clk),
|
|
.io_en(rvclkhdr_266_io_en),
|
|
.io_scan_mode(rvclkhdr_266_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_267 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_267_io_l1clk),
|
|
.io_clk(rvclkhdr_267_io_clk),
|
|
.io_en(rvclkhdr_267_io_en),
|
|
.io_scan_mode(rvclkhdr_267_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_268 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_268_io_l1clk),
|
|
.io_clk(rvclkhdr_268_io_clk),
|
|
.io_en(rvclkhdr_268_io_en),
|
|
.io_scan_mode(rvclkhdr_268_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_269 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_269_io_l1clk),
|
|
.io_clk(rvclkhdr_269_io_clk),
|
|
.io_en(rvclkhdr_269_io_en),
|
|
.io_scan_mode(rvclkhdr_269_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_270 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_270_io_l1clk),
|
|
.io_clk(rvclkhdr_270_io_clk),
|
|
.io_en(rvclkhdr_270_io_en),
|
|
.io_scan_mode(rvclkhdr_270_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_271 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_271_io_l1clk),
|
|
.io_clk(rvclkhdr_271_io_clk),
|
|
.io_en(rvclkhdr_271_io_en),
|
|
.io_scan_mode(rvclkhdr_271_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_272 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_272_io_l1clk),
|
|
.io_clk(rvclkhdr_272_io_clk),
|
|
.io_en(rvclkhdr_272_io_en),
|
|
.io_scan_mode(rvclkhdr_272_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_273 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_273_io_l1clk),
|
|
.io_clk(rvclkhdr_273_io_clk),
|
|
.io_en(rvclkhdr_273_io_en),
|
|
.io_scan_mode(rvclkhdr_273_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_274 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_274_io_l1clk),
|
|
.io_clk(rvclkhdr_274_io_clk),
|
|
.io_en(rvclkhdr_274_io_en),
|
|
.io_scan_mode(rvclkhdr_274_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_275 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_275_io_l1clk),
|
|
.io_clk(rvclkhdr_275_io_clk),
|
|
.io_en(rvclkhdr_275_io_en),
|
|
.io_scan_mode(rvclkhdr_275_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_276 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_276_io_l1clk),
|
|
.io_clk(rvclkhdr_276_io_clk),
|
|
.io_en(rvclkhdr_276_io_en),
|
|
.io_scan_mode(rvclkhdr_276_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_277 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_277_io_l1clk),
|
|
.io_clk(rvclkhdr_277_io_clk),
|
|
.io_en(rvclkhdr_277_io_en),
|
|
.io_scan_mode(rvclkhdr_277_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_278 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_278_io_l1clk),
|
|
.io_clk(rvclkhdr_278_io_clk),
|
|
.io_en(rvclkhdr_278_io_en),
|
|
.io_scan_mode(rvclkhdr_278_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_279 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_279_io_l1clk),
|
|
.io_clk(rvclkhdr_279_io_clk),
|
|
.io_en(rvclkhdr_279_io_en),
|
|
.io_scan_mode(rvclkhdr_279_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_280 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_280_io_l1clk),
|
|
.io_clk(rvclkhdr_280_io_clk),
|
|
.io_en(rvclkhdr_280_io_en),
|
|
.io_scan_mode(rvclkhdr_280_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_281 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_281_io_l1clk),
|
|
.io_clk(rvclkhdr_281_io_clk),
|
|
.io_en(rvclkhdr_281_io_en),
|
|
.io_scan_mode(rvclkhdr_281_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_282 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_282_io_l1clk),
|
|
.io_clk(rvclkhdr_282_io_clk),
|
|
.io_en(rvclkhdr_282_io_en),
|
|
.io_scan_mode(rvclkhdr_282_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_283 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_283_io_l1clk),
|
|
.io_clk(rvclkhdr_283_io_clk),
|
|
.io_en(rvclkhdr_283_io_en),
|
|
.io_scan_mode(rvclkhdr_283_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_284 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_284_io_l1clk),
|
|
.io_clk(rvclkhdr_284_io_clk),
|
|
.io_en(rvclkhdr_284_io_en),
|
|
.io_scan_mode(rvclkhdr_284_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_285 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_285_io_l1clk),
|
|
.io_clk(rvclkhdr_285_io_clk),
|
|
.io_en(rvclkhdr_285_io_en),
|
|
.io_scan_mode(rvclkhdr_285_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_286 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_286_io_l1clk),
|
|
.io_clk(rvclkhdr_286_io_clk),
|
|
.io_en(rvclkhdr_286_io_en),
|
|
.io_scan_mode(rvclkhdr_286_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_287 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_287_io_l1clk),
|
|
.io_clk(rvclkhdr_287_io_clk),
|
|
.io_en(rvclkhdr_287_io_en),
|
|
.io_scan_mode(rvclkhdr_287_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_288 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_288_io_l1clk),
|
|
.io_clk(rvclkhdr_288_io_clk),
|
|
.io_en(rvclkhdr_288_io_en),
|
|
.io_scan_mode(rvclkhdr_288_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_289 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_289_io_l1clk),
|
|
.io_clk(rvclkhdr_289_io_clk),
|
|
.io_en(rvclkhdr_289_io_en),
|
|
.io_scan_mode(rvclkhdr_289_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_290 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_290_io_l1clk),
|
|
.io_clk(rvclkhdr_290_io_clk),
|
|
.io_en(rvclkhdr_290_io_en),
|
|
.io_scan_mode(rvclkhdr_290_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_291 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_291_io_l1clk),
|
|
.io_clk(rvclkhdr_291_io_clk),
|
|
.io_en(rvclkhdr_291_io_en),
|
|
.io_scan_mode(rvclkhdr_291_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_292 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_292_io_l1clk),
|
|
.io_clk(rvclkhdr_292_io_clk),
|
|
.io_en(rvclkhdr_292_io_en),
|
|
.io_scan_mode(rvclkhdr_292_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_293 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_293_io_l1clk),
|
|
.io_clk(rvclkhdr_293_io_clk),
|
|
.io_en(rvclkhdr_293_io_en),
|
|
.io_scan_mode(rvclkhdr_293_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_294 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_294_io_l1clk),
|
|
.io_clk(rvclkhdr_294_io_clk),
|
|
.io_en(rvclkhdr_294_io_en),
|
|
.io_scan_mode(rvclkhdr_294_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_295 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_295_io_l1clk),
|
|
.io_clk(rvclkhdr_295_io_clk),
|
|
.io_en(rvclkhdr_295_io_en),
|
|
.io_scan_mode(rvclkhdr_295_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_296 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_296_io_l1clk),
|
|
.io_clk(rvclkhdr_296_io_clk),
|
|
.io_en(rvclkhdr_296_io_en),
|
|
.io_scan_mode(rvclkhdr_296_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_297 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_297_io_l1clk),
|
|
.io_clk(rvclkhdr_297_io_clk),
|
|
.io_en(rvclkhdr_297_io_en),
|
|
.io_scan_mode(rvclkhdr_297_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_298 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_298_io_l1clk),
|
|
.io_clk(rvclkhdr_298_io_clk),
|
|
.io_en(rvclkhdr_298_io_en),
|
|
.io_scan_mode(rvclkhdr_298_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_299 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_299_io_l1clk),
|
|
.io_clk(rvclkhdr_299_io_clk),
|
|
.io_en(rvclkhdr_299_io_en),
|
|
.io_scan_mode(rvclkhdr_299_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_300 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_300_io_l1clk),
|
|
.io_clk(rvclkhdr_300_io_clk),
|
|
.io_en(rvclkhdr_300_io_en),
|
|
.io_scan_mode(rvclkhdr_300_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_301 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_301_io_l1clk),
|
|
.io_clk(rvclkhdr_301_io_clk),
|
|
.io_en(rvclkhdr_301_io_en),
|
|
.io_scan_mode(rvclkhdr_301_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_302 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_302_io_l1clk),
|
|
.io_clk(rvclkhdr_302_io_clk),
|
|
.io_en(rvclkhdr_302_io_en),
|
|
.io_scan_mode(rvclkhdr_302_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_303 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_303_io_l1clk),
|
|
.io_clk(rvclkhdr_303_io_clk),
|
|
.io_en(rvclkhdr_303_io_en),
|
|
.io_scan_mode(rvclkhdr_303_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_304 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_304_io_l1clk),
|
|
.io_clk(rvclkhdr_304_io_clk),
|
|
.io_en(rvclkhdr_304_io_en),
|
|
.io_scan_mode(rvclkhdr_304_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_305 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_305_io_l1clk),
|
|
.io_clk(rvclkhdr_305_io_clk),
|
|
.io_en(rvclkhdr_305_io_en),
|
|
.io_scan_mode(rvclkhdr_305_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_306 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_306_io_l1clk),
|
|
.io_clk(rvclkhdr_306_io_clk),
|
|
.io_en(rvclkhdr_306_io_en),
|
|
.io_scan_mode(rvclkhdr_306_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_307 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_307_io_l1clk),
|
|
.io_clk(rvclkhdr_307_io_clk),
|
|
.io_en(rvclkhdr_307_io_en),
|
|
.io_scan_mode(rvclkhdr_307_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_308 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_308_io_l1clk),
|
|
.io_clk(rvclkhdr_308_io_clk),
|
|
.io_en(rvclkhdr_308_io_en),
|
|
.io_scan_mode(rvclkhdr_308_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_309 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_309_io_l1clk),
|
|
.io_clk(rvclkhdr_309_io_clk),
|
|
.io_en(rvclkhdr_309_io_en),
|
|
.io_scan_mode(rvclkhdr_309_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_310 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_310_io_l1clk),
|
|
.io_clk(rvclkhdr_310_io_clk),
|
|
.io_en(rvclkhdr_310_io_en),
|
|
.io_scan_mode(rvclkhdr_310_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_311 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_311_io_l1clk),
|
|
.io_clk(rvclkhdr_311_io_clk),
|
|
.io_en(rvclkhdr_311_io_en),
|
|
.io_scan_mode(rvclkhdr_311_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_312 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_312_io_l1clk),
|
|
.io_clk(rvclkhdr_312_io_clk),
|
|
.io_en(rvclkhdr_312_io_en),
|
|
.io_scan_mode(rvclkhdr_312_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_313 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_313_io_l1clk),
|
|
.io_clk(rvclkhdr_313_io_clk),
|
|
.io_en(rvclkhdr_313_io_en),
|
|
.io_scan_mode(rvclkhdr_313_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_314 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_314_io_l1clk),
|
|
.io_clk(rvclkhdr_314_io_clk),
|
|
.io_en(rvclkhdr_314_io_en),
|
|
.io_scan_mode(rvclkhdr_314_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_315 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_315_io_l1clk),
|
|
.io_clk(rvclkhdr_315_io_clk),
|
|
.io_en(rvclkhdr_315_io_en),
|
|
.io_scan_mode(rvclkhdr_315_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_316 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_316_io_l1clk),
|
|
.io_clk(rvclkhdr_316_io_clk),
|
|
.io_en(rvclkhdr_316_io_en),
|
|
.io_scan_mode(rvclkhdr_316_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_317 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_317_io_l1clk),
|
|
.io_clk(rvclkhdr_317_io_clk),
|
|
.io_en(rvclkhdr_317_io_en),
|
|
.io_scan_mode(rvclkhdr_317_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_318 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_318_io_l1clk),
|
|
.io_clk(rvclkhdr_318_io_clk),
|
|
.io_en(rvclkhdr_318_io_en),
|
|
.io_scan_mode(rvclkhdr_318_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_319 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_319_io_l1clk),
|
|
.io_clk(rvclkhdr_319_io_clk),
|
|
.io_en(rvclkhdr_319_io_en),
|
|
.io_scan_mode(rvclkhdr_319_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_320 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_320_io_l1clk),
|
|
.io_clk(rvclkhdr_320_io_clk),
|
|
.io_en(rvclkhdr_320_io_en),
|
|
.io_scan_mode(rvclkhdr_320_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_321 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_321_io_l1clk),
|
|
.io_clk(rvclkhdr_321_io_clk),
|
|
.io_en(rvclkhdr_321_io_en),
|
|
.io_scan_mode(rvclkhdr_321_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_322 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_322_io_l1clk),
|
|
.io_clk(rvclkhdr_322_io_clk),
|
|
.io_en(rvclkhdr_322_io_en),
|
|
.io_scan_mode(rvclkhdr_322_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_323 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_323_io_l1clk),
|
|
.io_clk(rvclkhdr_323_io_clk),
|
|
.io_en(rvclkhdr_323_io_en),
|
|
.io_scan_mode(rvclkhdr_323_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_324 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_324_io_l1clk),
|
|
.io_clk(rvclkhdr_324_io_clk),
|
|
.io_en(rvclkhdr_324_io_en),
|
|
.io_scan_mode(rvclkhdr_324_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_325 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_325_io_l1clk),
|
|
.io_clk(rvclkhdr_325_io_clk),
|
|
.io_en(rvclkhdr_325_io_en),
|
|
.io_scan_mode(rvclkhdr_325_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_326 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_326_io_l1clk),
|
|
.io_clk(rvclkhdr_326_io_clk),
|
|
.io_en(rvclkhdr_326_io_en),
|
|
.io_scan_mode(rvclkhdr_326_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_327 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_327_io_l1clk),
|
|
.io_clk(rvclkhdr_327_io_clk),
|
|
.io_en(rvclkhdr_327_io_en),
|
|
.io_scan_mode(rvclkhdr_327_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_328 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_328_io_l1clk),
|
|
.io_clk(rvclkhdr_328_io_clk),
|
|
.io_en(rvclkhdr_328_io_en),
|
|
.io_scan_mode(rvclkhdr_328_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_329 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_329_io_l1clk),
|
|
.io_clk(rvclkhdr_329_io_clk),
|
|
.io_en(rvclkhdr_329_io_en),
|
|
.io_scan_mode(rvclkhdr_329_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_330 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_330_io_l1clk),
|
|
.io_clk(rvclkhdr_330_io_clk),
|
|
.io_en(rvclkhdr_330_io_en),
|
|
.io_scan_mode(rvclkhdr_330_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_331 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_331_io_l1clk),
|
|
.io_clk(rvclkhdr_331_io_clk),
|
|
.io_en(rvclkhdr_331_io_en),
|
|
.io_scan_mode(rvclkhdr_331_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_332 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_332_io_l1clk),
|
|
.io_clk(rvclkhdr_332_io_clk),
|
|
.io_en(rvclkhdr_332_io_en),
|
|
.io_scan_mode(rvclkhdr_332_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_333 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_333_io_l1clk),
|
|
.io_clk(rvclkhdr_333_io_clk),
|
|
.io_en(rvclkhdr_333_io_en),
|
|
.io_scan_mode(rvclkhdr_333_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_334 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_334_io_l1clk),
|
|
.io_clk(rvclkhdr_334_io_clk),
|
|
.io_en(rvclkhdr_334_io_en),
|
|
.io_scan_mode(rvclkhdr_334_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_335 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_335_io_l1clk),
|
|
.io_clk(rvclkhdr_335_io_clk),
|
|
.io_en(rvclkhdr_335_io_en),
|
|
.io_scan_mode(rvclkhdr_335_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_336 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_336_io_l1clk),
|
|
.io_clk(rvclkhdr_336_io_clk),
|
|
.io_en(rvclkhdr_336_io_en),
|
|
.io_scan_mode(rvclkhdr_336_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_337 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_337_io_l1clk),
|
|
.io_clk(rvclkhdr_337_io_clk),
|
|
.io_en(rvclkhdr_337_io_en),
|
|
.io_scan_mode(rvclkhdr_337_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_338 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_338_io_l1clk),
|
|
.io_clk(rvclkhdr_338_io_clk),
|
|
.io_en(rvclkhdr_338_io_en),
|
|
.io_scan_mode(rvclkhdr_338_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_339 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_339_io_l1clk),
|
|
.io_clk(rvclkhdr_339_io_clk),
|
|
.io_en(rvclkhdr_339_io_en),
|
|
.io_scan_mode(rvclkhdr_339_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_340 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_340_io_l1clk),
|
|
.io_clk(rvclkhdr_340_io_clk),
|
|
.io_en(rvclkhdr_340_io_en),
|
|
.io_scan_mode(rvclkhdr_340_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_341 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_341_io_l1clk),
|
|
.io_clk(rvclkhdr_341_io_clk),
|
|
.io_en(rvclkhdr_341_io_en),
|
|
.io_scan_mode(rvclkhdr_341_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_342 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_342_io_l1clk),
|
|
.io_clk(rvclkhdr_342_io_clk),
|
|
.io_en(rvclkhdr_342_io_en),
|
|
.io_scan_mode(rvclkhdr_342_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_343 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_343_io_l1clk),
|
|
.io_clk(rvclkhdr_343_io_clk),
|
|
.io_en(rvclkhdr_343_io_en),
|
|
.io_scan_mode(rvclkhdr_343_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_344 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_344_io_l1clk),
|
|
.io_clk(rvclkhdr_344_io_clk),
|
|
.io_en(rvclkhdr_344_io_en),
|
|
.io_scan_mode(rvclkhdr_344_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_345 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_345_io_l1clk),
|
|
.io_clk(rvclkhdr_345_io_clk),
|
|
.io_en(rvclkhdr_345_io_en),
|
|
.io_scan_mode(rvclkhdr_345_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_346 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_346_io_l1clk),
|
|
.io_clk(rvclkhdr_346_io_clk),
|
|
.io_en(rvclkhdr_346_io_en),
|
|
.io_scan_mode(rvclkhdr_346_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_347 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_347_io_l1clk),
|
|
.io_clk(rvclkhdr_347_io_clk),
|
|
.io_en(rvclkhdr_347_io_en),
|
|
.io_scan_mode(rvclkhdr_347_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_348 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_348_io_l1clk),
|
|
.io_clk(rvclkhdr_348_io_clk),
|
|
.io_en(rvclkhdr_348_io_en),
|
|
.io_scan_mode(rvclkhdr_348_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_349 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_349_io_l1clk),
|
|
.io_clk(rvclkhdr_349_io_clk),
|
|
.io_en(rvclkhdr_349_io_en),
|
|
.io_scan_mode(rvclkhdr_349_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_350 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_350_io_l1clk),
|
|
.io_clk(rvclkhdr_350_io_clk),
|
|
.io_en(rvclkhdr_350_io_en),
|
|
.io_scan_mode(rvclkhdr_350_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_351 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_351_io_l1clk),
|
|
.io_clk(rvclkhdr_351_io_clk),
|
|
.io_en(rvclkhdr_351_io_en),
|
|
.io_scan_mode(rvclkhdr_351_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_352 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_352_io_l1clk),
|
|
.io_clk(rvclkhdr_352_io_clk),
|
|
.io_en(rvclkhdr_352_io_en),
|
|
.io_scan_mode(rvclkhdr_352_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_353 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_353_io_l1clk),
|
|
.io_clk(rvclkhdr_353_io_clk),
|
|
.io_en(rvclkhdr_353_io_en),
|
|
.io_scan_mode(rvclkhdr_353_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_354 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_354_io_l1clk),
|
|
.io_clk(rvclkhdr_354_io_clk),
|
|
.io_en(rvclkhdr_354_io_en),
|
|
.io_scan_mode(rvclkhdr_354_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_355 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_355_io_l1clk),
|
|
.io_clk(rvclkhdr_355_io_clk),
|
|
.io_en(rvclkhdr_355_io_en),
|
|
.io_scan_mode(rvclkhdr_355_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_356 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_356_io_l1clk),
|
|
.io_clk(rvclkhdr_356_io_clk),
|
|
.io_en(rvclkhdr_356_io_en),
|
|
.io_scan_mode(rvclkhdr_356_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_357 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_357_io_l1clk),
|
|
.io_clk(rvclkhdr_357_io_clk),
|
|
.io_en(rvclkhdr_357_io_en),
|
|
.io_scan_mode(rvclkhdr_357_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_358 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_358_io_l1clk),
|
|
.io_clk(rvclkhdr_358_io_clk),
|
|
.io_en(rvclkhdr_358_io_en),
|
|
.io_scan_mode(rvclkhdr_358_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_359 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_359_io_l1clk),
|
|
.io_clk(rvclkhdr_359_io_clk),
|
|
.io_en(rvclkhdr_359_io_en),
|
|
.io_scan_mode(rvclkhdr_359_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_360 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_360_io_l1clk),
|
|
.io_clk(rvclkhdr_360_io_clk),
|
|
.io_en(rvclkhdr_360_io_en),
|
|
.io_scan_mode(rvclkhdr_360_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_361 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_361_io_l1clk),
|
|
.io_clk(rvclkhdr_361_io_clk),
|
|
.io_en(rvclkhdr_361_io_en),
|
|
.io_scan_mode(rvclkhdr_361_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_362 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_362_io_l1clk),
|
|
.io_clk(rvclkhdr_362_io_clk),
|
|
.io_en(rvclkhdr_362_io_en),
|
|
.io_scan_mode(rvclkhdr_362_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_363 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_363_io_l1clk),
|
|
.io_clk(rvclkhdr_363_io_clk),
|
|
.io_en(rvclkhdr_363_io_en),
|
|
.io_scan_mode(rvclkhdr_363_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_364 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_364_io_l1clk),
|
|
.io_clk(rvclkhdr_364_io_clk),
|
|
.io_en(rvclkhdr_364_io_en),
|
|
.io_scan_mode(rvclkhdr_364_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_365 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_365_io_l1clk),
|
|
.io_clk(rvclkhdr_365_io_clk),
|
|
.io_en(rvclkhdr_365_io_en),
|
|
.io_scan_mode(rvclkhdr_365_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_366 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_366_io_l1clk),
|
|
.io_clk(rvclkhdr_366_io_clk),
|
|
.io_en(rvclkhdr_366_io_en),
|
|
.io_scan_mode(rvclkhdr_366_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_367 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_367_io_l1clk),
|
|
.io_clk(rvclkhdr_367_io_clk),
|
|
.io_en(rvclkhdr_367_io_en),
|
|
.io_scan_mode(rvclkhdr_367_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_368 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_368_io_l1clk),
|
|
.io_clk(rvclkhdr_368_io_clk),
|
|
.io_en(rvclkhdr_368_io_en),
|
|
.io_scan_mode(rvclkhdr_368_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_369 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_369_io_l1clk),
|
|
.io_clk(rvclkhdr_369_io_clk),
|
|
.io_en(rvclkhdr_369_io_en),
|
|
.io_scan_mode(rvclkhdr_369_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_370 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_370_io_l1clk),
|
|
.io_clk(rvclkhdr_370_io_clk),
|
|
.io_en(rvclkhdr_370_io_en),
|
|
.io_scan_mode(rvclkhdr_370_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_371 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_371_io_l1clk),
|
|
.io_clk(rvclkhdr_371_io_clk),
|
|
.io_en(rvclkhdr_371_io_en),
|
|
.io_scan_mode(rvclkhdr_371_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_372 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_372_io_l1clk),
|
|
.io_clk(rvclkhdr_372_io_clk),
|
|
.io_en(rvclkhdr_372_io_en),
|
|
.io_scan_mode(rvclkhdr_372_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_373 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_373_io_l1clk),
|
|
.io_clk(rvclkhdr_373_io_clk),
|
|
.io_en(rvclkhdr_373_io_en),
|
|
.io_scan_mode(rvclkhdr_373_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_374 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_374_io_l1clk),
|
|
.io_clk(rvclkhdr_374_io_clk),
|
|
.io_en(rvclkhdr_374_io_en),
|
|
.io_scan_mode(rvclkhdr_374_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_375 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_375_io_l1clk),
|
|
.io_clk(rvclkhdr_375_io_clk),
|
|
.io_en(rvclkhdr_375_io_en),
|
|
.io_scan_mode(rvclkhdr_375_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_376 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_376_io_l1clk),
|
|
.io_clk(rvclkhdr_376_io_clk),
|
|
.io_en(rvclkhdr_376_io_en),
|
|
.io_scan_mode(rvclkhdr_376_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_377 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_377_io_l1clk),
|
|
.io_clk(rvclkhdr_377_io_clk),
|
|
.io_en(rvclkhdr_377_io_en),
|
|
.io_scan_mode(rvclkhdr_377_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_378 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_378_io_l1clk),
|
|
.io_clk(rvclkhdr_378_io_clk),
|
|
.io_en(rvclkhdr_378_io_en),
|
|
.io_scan_mode(rvclkhdr_378_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_379 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_379_io_l1clk),
|
|
.io_clk(rvclkhdr_379_io_clk),
|
|
.io_en(rvclkhdr_379_io_en),
|
|
.io_scan_mode(rvclkhdr_379_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_380 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_380_io_l1clk),
|
|
.io_clk(rvclkhdr_380_io_clk),
|
|
.io_en(rvclkhdr_380_io_en),
|
|
.io_scan_mode(rvclkhdr_380_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_381 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_381_io_l1clk),
|
|
.io_clk(rvclkhdr_381_io_clk),
|
|
.io_en(rvclkhdr_381_io_en),
|
|
.io_scan_mode(rvclkhdr_381_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_382 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_382_io_l1clk),
|
|
.io_clk(rvclkhdr_382_io_clk),
|
|
.io_en(rvclkhdr_382_io_en),
|
|
.io_scan_mode(rvclkhdr_382_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_383 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_383_io_l1clk),
|
|
.io_clk(rvclkhdr_383_io_clk),
|
|
.io_en(rvclkhdr_383_io_en),
|
|
.io_scan_mode(rvclkhdr_383_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_384 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_384_io_l1clk),
|
|
.io_clk(rvclkhdr_384_io_clk),
|
|
.io_en(rvclkhdr_384_io_en),
|
|
.io_scan_mode(rvclkhdr_384_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_385 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_385_io_l1clk),
|
|
.io_clk(rvclkhdr_385_io_clk),
|
|
.io_en(rvclkhdr_385_io_en),
|
|
.io_scan_mode(rvclkhdr_385_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_386 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_386_io_l1clk),
|
|
.io_clk(rvclkhdr_386_io_clk),
|
|
.io_en(rvclkhdr_386_io_en),
|
|
.io_scan_mode(rvclkhdr_386_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_387 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_387_io_l1clk),
|
|
.io_clk(rvclkhdr_387_io_clk),
|
|
.io_en(rvclkhdr_387_io_en),
|
|
.io_scan_mode(rvclkhdr_387_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_388 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_388_io_l1clk),
|
|
.io_clk(rvclkhdr_388_io_clk),
|
|
.io_en(rvclkhdr_388_io_en),
|
|
.io_scan_mode(rvclkhdr_388_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_389 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_389_io_l1clk),
|
|
.io_clk(rvclkhdr_389_io_clk),
|
|
.io_en(rvclkhdr_389_io_en),
|
|
.io_scan_mode(rvclkhdr_389_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_390 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_390_io_l1clk),
|
|
.io_clk(rvclkhdr_390_io_clk),
|
|
.io_en(rvclkhdr_390_io_en),
|
|
.io_scan_mode(rvclkhdr_390_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_391 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_391_io_l1clk),
|
|
.io_clk(rvclkhdr_391_io_clk),
|
|
.io_en(rvclkhdr_391_io_en),
|
|
.io_scan_mode(rvclkhdr_391_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_392 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_392_io_l1clk),
|
|
.io_clk(rvclkhdr_392_io_clk),
|
|
.io_en(rvclkhdr_392_io_en),
|
|
.io_scan_mode(rvclkhdr_392_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_393 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_393_io_l1clk),
|
|
.io_clk(rvclkhdr_393_io_clk),
|
|
.io_en(rvclkhdr_393_io_en),
|
|
.io_scan_mode(rvclkhdr_393_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_394 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_394_io_l1clk),
|
|
.io_clk(rvclkhdr_394_io_clk),
|
|
.io_en(rvclkhdr_394_io_en),
|
|
.io_scan_mode(rvclkhdr_394_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_395 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_395_io_l1clk),
|
|
.io_clk(rvclkhdr_395_io_clk),
|
|
.io_en(rvclkhdr_395_io_en),
|
|
.io_scan_mode(rvclkhdr_395_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_396 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_396_io_l1clk),
|
|
.io_clk(rvclkhdr_396_io_clk),
|
|
.io_en(rvclkhdr_396_io_en),
|
|
.io_scan_mode(rvclkhdr_396_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_397 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_397_io_l1clk),
|
|
.io_clk(rvclkhdr_397_io_clk),
|
|
.io_en(rvclkhdr_397_io_en),
|
|
.io_scan_mode(rvclkhdr_397_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_398 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_398_io_l1clk),
|
|
.io_clk(rvclkhdr_398_io_clk),
|
|
.io_en(rvclkhdr_398_io_en),
|
|
.io_scan_mode(rvclkhdr_398_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_399 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_399_io_l1clk),
|
|
.io_clk(rvclkhdr_399_io_clk),
|
|
.io_en(rvclkhdr_399_io_en),
|
|
.io_scan_mode(rvclkhdr_399_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_400 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_400_io_l1clk),
|
|
.io_clk(rvclkhdr_400_io_clk),
|
|
.io_en(rvclkhdr_400_io_en),
|
|
.io_scan_mode(rvclkhdr_400_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_401 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_401_io_l1clk),
|
|
.io_clk(rvclkhdr_401_io_clk),
|
|
.io_en(rvclkhdr_401_io_en),
|
|
.io_scan_mode(rvclkhdr_401_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_402 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_402_io_l1clk),
|
|
.io_clk(rvclkhdr_402_io_clk),
|
|
.io_en(rvclkhdr_402_io_en),
|
|
.io_scan_mode(rvclkhdr_402_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_403 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_403_io_l1clk),
|
|
.io_clk(rvclkhdr_403_io_clk),
|
|
.io_en(rvclkhdr_403_io_en),
|
|
.io_scan_mode(rvclkhdr_403_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_404 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_404_io_l1clk),
|
|
.io_clk(rvclkhdr_404_io_clk),
|
|
.io_en(rvclkhdr_404_io_en),
|
|
.io_scan_mode(rvclkhdr_404_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_405 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_405_io_l1clk),
|
|
.io_clk(rvclkhdr_405_io_clk),
|
|
.io_en(rvclkhdr_405_io_en),
|
|
.io_scan_mode(rvclkhdr_405_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_406 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_406_io_l1clk),
|
|
.io_clk(rvclkhdr_406_io_clk),
|
|
.io_en(rvclkhdr_406_io_en),
|
|
.io_scan_mode(rvclkhdr_406_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_407 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_407_io_l1clk),
|
|
.io_clk(rvclkhdr_407_io_clk),
|
|
.io_en(rvclkhdr_407_io_en),
|
|
.io_scan_mode(rvclkhdr_407_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_408 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_408_io_l1clk),
|
|
.io_clk(rvclkhdr_408_io_clk),
|
|
.io_en(rvclkhdr_408_io_en),
|
|
.io_scan_mode(rvclkhdr_408_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_409 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_409_io_l1clk),
|
|
.io_clk(rvclkhdr_409_io_clk),
|
|
.io_en(rvclkhdr_409_io_en),
|
|
.io_scan_mode(rvclkhdr_409_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_410 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_410_io_l1clk),
|
|
.io_clk(rvclkhdr_410_io_clk),
|
|
.io_en(rvclkhdr_410_io_en),
|
|
.io_scan_mode(rvclkhdr_410_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_411 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_411_io_l1clk),
|
|
.io_clk(rvclkhdr_411_io_clk),
|
|
.io_en(rvclkhdr_411_io_en),
|
|
.io_scan_mode(rvclkhdr_411_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_412 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_412_io_l1clk),
|
|
.io_clk(rvclkhdr_412_io_clk),
|
|
.io_en(rvclkhdr_412_io_en),
|
|
.io_scan_mode(rvclkhdr_412_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_413 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_413_io_l1clk),
|
|
.io_clk(rvclkhdr_413_io_clk),
|
|
.io_en(rvclkhdr_413_io_en),
|
|
.io_scan_mode(rvclkhdr_413_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_414 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_414_io_l1clk),
|
|
.io_clk(rvclkhdr_414_io_clk),
|
|
.io_en(rvclkhdr_414_io_en),
|
|
.io_scan_mode(rvclkhdr_414_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_415 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_415_io_l1clk),
|
|
.io_clk(rvclkhdr_415_io_clk),
|
|
.io_en(rvclkhdr_415_io_en),
|
|
.io_scan_mode(rvclkhdr_415_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_416 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_416_io_l1clk),
|
|
.io_clk(rvclkhdr_416_io_clk),
|
|
.io_en(rvclkhdr_416_io_en),
|
|
.io_scan_mode(rvclkhdr_416_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_417 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_417_io_l1clk),
|
|
.io_clk(rvclkhdr_417_io_clk),
|
|
.io_en(rvclkhdr_417_io_en),
|
|
.io_scan_mode(rvclkhdr_417_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_418 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_418_io_l1clk),
|
|
.io_clk(rvclkhdr_418_io_clk),
|
|
.io_en(rvclkhdr_418_io_en),
|
|
.io_scan_mode(rvclkhdr_418_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_419 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_419_io_l1clk),
|
|
.io_clk(rvclkhdr_419_io_clk),
|
|
.io_en(rvclkhdr_419_io_en),
|
|
.io_scan_mode(rvclkhdr_419_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_420 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_420_io_l1clk),
|
|
.io_clk(rvclkhdr_420_io_clk),
|
|
.io_en(rvclkhdr_420_io_en),
|
|
.io_scan_mode(rvclkhdr_420_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_421 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_421_io_l1clk),
|
|
.io_clk(rvclkhdr_421_io_clk),
|
|
.io_en(rvclkhdr_421_io_en),
|
|
.io_scan_mode(rvclkhdr_421_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_422 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_422_io_l1clk),
|
|
.io_clk(rvclkhdr_422_io_clk),
|
|
.io_en(rvclkhdr_422_io_en),
|
|
.io_scan_mode(rvclkhdr_422_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_423 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_423_io_l1clk),
|
|
.io_clk(rvclkhdr_423_io_clk),
|
|
.io_en(rvclkhdr_423_io_en),
|
|
.io_scan_mode(rvclkhdr_423_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_424 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_424_io_l1clk),
|
|
.io_clk(rvclkhdr_424_io_clk),
|
|
.io_en(rvclkhdr_424_io_en),
|
|
.io_scan_mode(rvclkhdr_424_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_425 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_425_io_l1clk),
|
|
.io_clk(rvclkhdr_425_io_clk),
|
|
.io_en(rvclkhdr_425_io_en),
|
|
.io_scan_mode(rvclkhdr_425_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_426 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_426_io_l1clk),
|
|
.io_clk(rvclkhdr_426_io_clk),
|
|
.io_en(rvclkhdr_426_io_en),
|
|
.io_scan_mode(rvclkhdr_426_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_427 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_427_io_l1clk),
|
|
.io_clk(rvclkhdr_427_io_clk),
|
|
.io_en(rvclkhdr_427_io_en),
|
|
.io_scan_mode(rvclkhdr_427_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_428 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_428_io_l1clk),
|
|
.io_clk(rvclkhdr_428_io_clk),
|
|
.io_en(rvclkhdr_428_io_en),
|
|
.io_scan_mode(rvclkhdr_428_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_429 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_429_io_l1clk),
|
|
.io_clk(rvclkhdr_429_io_clk),
|
|
.io_en(rvclkhdr_429_io_en),
|
|
.io_scan_mode(rvclkhdr_429_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_430 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_430_io_l1clk),
|
|
.io_clk(rvclkhdr_430_io_clk),
|
|
.io_en(rvclkhdr_430_io_en),
|
|
.io_scan_mode(rvclkhdr_430_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_431 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_431_io_l1clk),
|
|
.io_clk(rvclkhdr_431_io_clk),
|
|
.io_en(rvclkhdr_431_io_en),
|
|
.io_scan_mode(rvclkhdr_431_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_432 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_432_io_l1clk),
|
|
.io_clk(rvclkhdr_432_io_clk),
|
|
.io_en(rvclkhdr_432_io_en),
|
|
.io_scan_mode(rvclkhdr_432_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_433 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_433_io_l1clk),
|
|
.io_clk(rvclkhdr_433_io_clk),
|
|
.io_en(rvclkhdr_433_io_en),
|
|
.io_scan_mode(rvclkhdr_433_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_434 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_434_io_l1clk),
|
|
.io_clk(rvclkhdr_434_io_clk),
|
|
.io_en(rvclkhdr_434_io_en),
|
|
.io_scan_mode(rvclkhdr_434_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_435 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_435_io_l1clk),
|
|
.io_clk(rvclkhdr_435_io_clk),
|
|
.io_en(rvclkhdr_435_io_en),
|
|
.io_scan_mode(rvclkhdr_435_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_436 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_436_io_l1clk),
|
|
.io_clk(rvclkhdr_436_io_clk),
|
|
.io_en(rvclkhdr_436_io_en),
|
|
.io_scan_mode(rvclkhdr_436_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_437 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_437_io_l1clk),
|
|
.io_clk(rvclkhdr_437_io_clk),
|
|
.io_en(rvclkhdr_437_io_en),
|
|
.io_scan_mode(rvclkhdr_437_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_438 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_438_io_l1clk),
|
|
.io_clk(rvclkhdr_438_io_clk),
|
|
.io_en(rvclkhdr_438_io_en),
|
|
.io_scan_mode(rvclkhdr_438_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_439 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_439_io_l1clk),
|
|
.io_clk(rvclkhdr_439_io_clk),
|
|
.io_en(rvclkhdr_439_io_en),
|
|
.io_scan_mode(rvclkhdr_439_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_440 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_440_io_l1clk),
|
|
.io_clk(rvclkhdr_440_io_clk),
|
|
.io_en(rvclkhdr_440_io_en),
|
|
.io_scan_mode(rvclkhdr_440_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_441 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_441_io_l1clk),
|
|
.io_clk(rvclkhdr_441_io_clk),
|
|
.io_en(rvclkhdr_441_io_en),
|
|
.io_scan_mode(rvclkhdr_441_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_442 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_442_io_l1clk),
|
|
.io_clk(rvclkhdr_442_io_clk),
|
|
.io_en(rvclkhdr_442_io_en),
|
|
.io_scan_mode(rvclkhdr_442_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_443 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_443_io_l1clk),
|
|
.io_clk(rvclkhdr_443_io_clk),
|
|
.io_en(rvclkhdr_443_io_en),
|
|
.io_scan_mode(rvclkhdr_443_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_444 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_444_io_l1clk),
|
|
.io_clk(rvclkhdr_444_io_clk),
|
|
.io_en(rvclkhdr_444_io_en),
|
|
.io_scan_mode(rvclkhdr_444_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_445 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_445_io_l1clk),
|
|
.io_clk(rvclkhdr_445_io_clk),
|
|
.io_en(rvclkhdr_445_io_en),
|
|
.io_scan_mode(rvclkhdr_445_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_446 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_446_io_l1clk),
|
|
.io_clk(rvclkhdr_446_io_clk),
|
|
.io_en(rvclkhdr_446_io_en),
|
|
.io_scan_mode(rvclkhdr_446_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_447 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_447_io_l1clk),
|
|
.io_clk(rvclkhdr_447_io_clk),
|
|
.io_en(rvclkhdr_447_io_en),
|
|
.io_scan_mode(rvclkhdr_447_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_448 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_448_io_l1clk),
|
|
.io_clk(rvclkhdr_448_io_clk),
|
|
.io_en(rvclkhdr_448_io_en),
|
|
.io_scan_mode(rvclkhdr_448_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_449 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_449_io_l1clk),
|
|
.io_clk(rvclkhdr_449_io_clk),
|
|
.io_en(rvclkhdr_449_io_en),
|
|
.io_scan_mode(rvclkhdr_449_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_450 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_450_io_l1clk),
|
|
.io_clk(rvclkhdr_450_io_clk),
|
|
.io_en(rvclkhdr_450_io_en),
|
|
.io_scan_mode(rvclkhdr_450_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_451 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_451_io_l1clk),
|
|
.io_clk(rvclkhdr_451_io_clk),
|
|
.io_en(rvclkhdr_451_io_en),
|
|
.io_scan_mode(rvclkhdr_451_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_452 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_452_io_l1clk),
|
|
.io_clk(rvclkhdr_452_io_clk),
|
|
.io_en(rvclkhdr_452_io_en),
|
|
.io_scan_mode(rvclkhdr_452_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_453 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_453_io_l1clk),
|
|
.io_clk(rvclkhdr_453_io_clk),
|
|
.io_en(rvclkhdr_453_io_en),
|
|
.io_scan_mode(rvclkhdr_453_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_454 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_454_io_l1clk),
|
|
.io_clk(rvclkhdr_454_io_clk),
|
|
.io_en(rvclkhdr_454_io_en),
|
|
.io_scan_mode(rvclkhdr_454_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_455 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_455_io_l1clk),
|
|
.io_clk(rvclkhdr_455_io_clk),
|
|
.io_en(rvclkhdr_455_io_en),
|
|
.io_scan_mode(rvclkhdr_455_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_456 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_456_io_l1clk),
|
|
.io_clk(rvclkhdr_456_io_clk),
|
|
.io_en(rvclkhdr_456_io_en),
|
|
.io_scan_mode(rvclkhdr_456_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_457 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_457_io_l1clk),
|
|
.io_clk(rvclkhdr_457_io_clk),
|
|
.io_en(rvclkhdr_457_io_en),
|
|
.io_scan_mode(rvclkhdr_457_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_458 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_458_io_l1clk),
|
|
.io_clk(rvclkhdr_458_io_clk),
|
|
.io_en(rvclkhdr_458_io_en),
|
|
.io_scan_mode(rvclkhdr_458_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_459 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_459_io_l1clk),
|
|
.io_clk(rvclkhdr_459_io_clk),
|
|
.io_en(rvclkhdr_459_io_en),
|
|
.io_scan_mode(rvclkhdr_459_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_460 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_460_io_l1clk),
|
|
.io_clk(rvclkhdr_460_io_clk),
|
|
.io_en(rvclkhdr_460_io_en),
|
|
.io_scan_mode(rvclkhdr_460_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_461 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_461_io_l1clk),
|
|
.io_clk(rvclkhdr_461_io_clk),
|
|
.io_en(rvclkhdr_461_io_en),
|
|
.io_scan_mode(rvclkhdr_461_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_462 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_462_io_l1clk),
|
|
.io_clk(rvclkhdr_462_io_clk),
|
|
.io_en(rvclkhdr_462_io_en),
|
|
.io_scan_mode(rvclkhdr_462_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_463 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_463_io_l1clk),
|
|
.io_clk(rvclkhdr_463_io_clk),
|
|
.io_en(rvclkhdr_463_io_en),
|
|
.io_scan_mode(rvclkhdr_463_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_464 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_464_io_l1clk),
|
|
.io_clk(rvclkhdr_464_io_clk),
|
|
.io_en(rvclkhdr_464_io_en),
|
|
.io_scan_mode(rvclkhdr_464_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_465 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_465_io_l1clk),
|
|
.io_clk(rvclkhdr_465_io_clk),
|
|
.io_en(rvclkhdr_465_io_en),
|
|
.io_scan_mode(rvclkhdr_465_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_466 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_466_io_l1clk),
|
|
.io_clk(rvclkhdr_466_io_clk),
|
|
.io_en(rvclkhdr_466_io_en),
|
|
.io_scan_mode(rvclkhdr_466_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_467 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_467_io_l1clk),
|
|
.io_clk(rvclkhdr_467_io_clk),
|
|
.io_en(rvclkhdr_467_io_en),
|
|
.io_scan_mode(rvclkhdr_467_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_468 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_468_io_l1clk),
|
|
.io_clk(rvclkhdr_468_io_clk),
|
|
.io_en(rvclkhdr_468_io_en),
|
|
.io_scan_mode(rvclkhdr_468_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_469 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_469_io_l1clk),
|
|
.io_clk(rvclkhdr_469_io_clk),
|
|
.io_en(rvclkhdr_469_io_en),
|
|
.io_scan_mode(rvclkhdr_469_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_470 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_470_io_l1clk),
|
|
.io_clk(rvclkhdr_470_io_clk),
|
|
.io_en(rvclkhdr_470_io_en),
|
|
.io_scan_mode(rvclkhdr_470_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_471 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_471_io_l1clk),
|
|
.io_clk(rvclkhdr_471_io_clk),
|
|
.io_en(rvclkhdr_471_io_en),
|
|
.io_scan_mode(rvclkhdr_471_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_472 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_472_io_l1clk),
|
|
.io_clk(rvclkhdr_472_io_clk),
|
|
.io_en(rvclkhdr_472_io_en),
|
|
.io_scan_mode(rvclkhdr_472_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_473 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_473_io_l1clk),
|
|
.io_clk(rvclkhdr_473_io_clk),
|
|
.io_en(rvclkhdr_473_io_en),
|
|
.io_scan_mode(rvclkhdr_473_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_474 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_474_io_l1clk),
|
|
.io_clk(rvclkhdr_474_io_clk),
|
|
.io_en(rvclkhdr_474_io_en),
|
|
.io_scan_mode(rvclkhdr_474_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_475 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_475_io_l1clk),
|
|
.io_clk(rvclkhdr_475_io_clk),
|
|
.io_en(rvclkhdr_475_io_en),
|
|
.io_scan_mode(rvclkhdr_475_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_476 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_476_io_l1clk),
|
|
.io_clk(rvclkhdr_476_io_clk),
|
|
.io_en(rvclkhdr_476_io_en),
|
|
.io_scan_mode(rvclkhdr_476_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_477 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_477_io_l1clk),
|
|
.io_clk(rvclkhdr_477_io_clk),
|
|
.io_en(rvclkhdr_477_io_en),
|
|
.io_scan_mode(rvclkhdr_477_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_478 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_478_io_l1clk),
|
|
.io_clk(rvclkhdr_478_io_clk),
|
|
.io_en(rvclkhdr_478_io_en),
|
|
.io_scan_mode(rvclkhdr_478_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_479 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_479_io_l1clk),
|
|
.io_clk(rvclkhdr_479_io_clk),
|
|
.io_en(rvclkhdr_479_io_en),
|
|
.io_scan_mode(rvclkhdr_479_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_480 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_480_io_l1clk),
|
|
.io_clk(rvclkhdr_480_io_clk),
|
|
.io_en(rvclkhdr_480_io_en),
|
|
.io_scan_mode(rvclkhdr_480_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_481 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_481_io_l1clk),
|
|
.io_clk(rvclkhdr_481_io_clk),
|
|
.io_en(rvclkhdr_481_io_en),
|
|
.io_scan_mode(rvclkhdr_481_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_482 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_482_io_l1clk),
|
|
.io_clk(rvclkhdr_482_io_clk),
|
|
.io_en(rvclkhdr_482_io_en),
|
|
.io_scan_mode(rvclkhdr_482_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_483 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_483_io_l1clk),
|
|
.io_clk(rvclkhdr_483_io_clk),
|
|
.io_en(rvclkhdr_483_io_en),
|
|
.io_scan_mode(rvclkhdr_483_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_484 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_484_io_l1clk),
|
|
.io_clk(rvclkhdr_484_io_clk),
|
|
.io_en(rvclkhdr_484_io_en),
|
|
.io_scan_mode(rvclkhdr_484_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_485 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_485_io_l1clk),
|
|
.io_clk(rvclkhdr_485_io_clk),
|
|
.io_en(rvclkhdr_485_io_en),
|
|
.io_scan_mode(rvclkhdr_485_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_486 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_486_io_l1clk),
|
|
.io_clk(rvclkhdr_486_io_clk),
|
|
.io_en(rvclkhdr_486_io_en),
|
|
.io_scan_mode(rvclkhdr_486_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_487 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_487_io_l1clk),
|
|
.io_clk(rvclkhdr_487_io_clk),
|
|
.io_en(rvclkhdr_487_io_en),
|
|
.io_scan_mode(rvclkhdr_487_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_488 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_488_io_l1clk),
|
|
.io_clk(rvclkhdr_488_io_clk),
|
|
.io_en(rvclkhdr_488_io_en),
|
|
.io_scan_mode(rvclkhdr_488_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_489 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_489_io_l1clk),
|
|
.io_clk(rvclkhdr_489_io_clk),
|
|
.io_en(rvclkhdr_489_io_en),
|
|
.io_scan_mode(rvclkhdr_489_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_490 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_490_io_l1clk),
|
|
.io_clk(rvclkhdr_490_io_clk),
|
|
.io_en(rvclkhdr_490_io_en),
|
|
.io_scan_mode(rvclkhdr_490_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_491 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_491_io_l1clk),
|
|
.io_clk(rvclkhdr_491_io_clk),
|
|
.io_en(rvclkhdr_491_io_en),
|
|
.io_scan_mode(rvclkhdr_491_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_492 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_492_io_l1clk),
|
|
.io_clk(rvclkhdr_492_io_clk),
|
|
.io_en(rvclkhdr_492_io_en),
|
|
.io_scan_mode(rvclkhdr_492_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_493 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_493_io_l1clk),
|
|
.io_clk(rvclkhdr_493_io_clk),
|
|
.io_en(rvclkhdr_493_io_en),
|
|
.io_scan_mode(rvclkhdr_493_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_494 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_494_io_l1clk),
|
|
.io_clk(rvclkhdr_494_io_clk),
|
|
.io_en(rvclkhdr_494_io_en),
|
|
.io_scan_mode(rvclkhdr_494_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_495 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_495_io_l1clk),
|
|
.io_clk(rvclkhdr_495_io_clk),
|
|
.io_en(rvclkhdr_495_io_en),
|
|
.io_scan_mode(rvclkhdr_495_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_496 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_496_io_l1clk),
|
|
.io_clk(rvclkhdr_496_io_clk),
|
|
.io_en(rvclkhdr_496_io_en),
|
|
.io_scan_mode(rvclkhdr_496_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_497 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_497_io_l1clk),
|
|
.io_clk(rvclkhdr_497_io_clk),
|
|
.io_en(rvclkhdr_497_io_en),
|
|
.io_scan_mode(rvclkhdr_497_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_498 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_498_io_l1clk),
|
|
.io_clk(rvclkhdr_498_io_clk),
|
|
.io_en(rvclkhdr_498_io_en),
|
|
.io_scan_mode(rvclkhdr_498_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_499 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_499_io_l1clk),
|
|
.io_clk(rvclkhdr_499_io_clk),
|
|
.io_en(rvclkhdr_499_io_en),
|
|
.io_scan_mode(rvclkhdr_499_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_500 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_500_io_l1clk),
|
|
.io_clk(rvclkhdr_500_io_clk),
|
|
.io_en(rvclkhdr_500_io_en),
|
|
.io_scan_mode(rvclkhdr_500_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_501 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_501_io_l1clk),
|
|
.io_clk(rvclkhdr_501_io_clk),
|
|
.io_en(rvclkhdr_501_io_en),
|
|
.io_scan_mode(rvclkhdr_501_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_502 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_502_io_l1clk),
|
|
.io_clk(rvclkhdr_502_io_clk),
|
|
.io_en(rvclkhdr_502_io_en),
|
|
.io_scan_mode(rvclkhdr_502_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_503 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_503_io_l1clk),
|
|
.io_clk(rvclkhdr_503_io_clk),
|
|
.io_en(rvclkhdr_503_io_en),
|
|
.io_scan_mode(rvclkhdr_503_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_504 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_504_io_l1clk),
|
|
.io_clk(rvclkhdr_504_io_clk),
|
|
.io_en(rvclkhdr_504_io_en),
|
|
.io_scan_mode(rvclkhdr_504_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_505 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_505_io_l1clk),
|
|
.io_clk(rvclkhdr_505_io_clk),
|
|
.io_en(rvclkhdr_505_io_en),
|
|
.io_scan_mode(rvclkhdr_505_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_506 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_506_io_l1clk),
|
|
.io_clk(rvclkhdr_506_io_clk),
|
|
.io_en(rvclkhdr_506_io_en),
|
|
.io_scan_mode(rvclkhdr_506_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_507 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_507_io_l1clk),
|
|
.io_clk(rvclkhdr_507_io_clk),
|
|
.io_en(rvclkhdr_507_io_en),
|
|
.io_scan_mode(rvclkhdr_507_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_508 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_508_io_l1clk),
|
|
.io_clk(rvclkhdr_508_io_clk),
|
|
.io_en(rvclkhdr_508_io_en),
|
|
.io_scan_mode(rvclkhdr_508_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_509 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_509_io_l1clk),
|
|
.io_clk(rvclkhdr_509_io_clk),
|
|
.io_en(rvclkhdr_509_io_en),
|
|
.io_scan_mode(rvclkhdr_509_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_510 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_510_io_l1clk),
|
|
.io_clk(rvclkhdr_510_io_clk),
|
|
.io_en(rvclkhdr_510_io_en),
|
|
.io_scan_mode(rvclkhdr_510_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_511 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_511_io_l1clk),
|
|
.io_clk(rvclkhdr_511_io_clk),
|
|
.io_en(rvclkhdr_511_io_en),
|
|
.io_scan_mode(rvclkhdr_511_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_512 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_512_io_l1clk),
|
|
.io_clk(rvclkhdr_512_io_clk),
|
|
.io_en(rvclkhdr_512_io_en),
|
|
.io_scan_mode(rvclkhdr_512_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_513 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_513_io_l1clk),
|
|
.io_clk(rvclkhdr_513_io_clk),
|
|
.io_en(rvclkhdr_513_io_en),
|
|
.io_scan_mode(rvclkhdr_513_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_514 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_514_io_l1clk),
|
|
.io_clk(rvclkhdr_514_io_clk),
|
|
.io_en(rvclkhdr_514_io_en),
|
|
.io_scan_mode(rvclkhdr_514_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_515 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_515_io_l1clk),
|
|
.io_clk(rvclkhdr_515_io_clk),
|
|
.io_en(rvclkhdr_515_io_en),
|
|
.io_scan_mode(rvclkhdr_515_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_516 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_516_io_l1clk),
|
|
.io_clk(rvclkhdr_516_io_clk),
|
|
.io_en(rvclkhdr_516_io_en),
|
|
.io_scan_mode(rvclkhdr_516_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_517 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_517_io_l1clk),
|
|
.io_clk(rvclkhdr_517_io_clk),
|
|
.io_en(rvclkhdr_517_io_en),
|
|
.io_scan_mode(rvclkhdr_517_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_518 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_518_io_l1clk),
|
|
.io_clk(rvclkhdr_518_io_clk),
|
|
.io_en(rvclkhdr_518_io_en),
|
|
.io_scan_mode(rvclkhdr_518_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_519 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_519_io_l1clk),
|
|
.io_clk(rvclkhdr_519_io_clk),
|
|
.io_en(rvclkhdr_519_io_en),
|
|
.io_scan_mode(rvclkhdr_519_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_520 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_520_io_l1clk),
|
|
.io_clk(rvclkhdr_520_io_clk),
|
|
.io_en(rvclkhdr_520_io_en),
|
|
.io_scan_mode(rvclkhdr_520_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_521 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_521_io_l1clk),
|
|
.io_clk(rvclkhdr_521_io_clk),
|
|
.io_en(rvclkhdr_521_io_en),
|
|
.io_scan_mode(rvclkhdr_521_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_522 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_522_io_l1clk),
|
|
.io_clk(rvclkhdr_522_io_clk),
|
|
.io_en(rvclkhdr_522_io_en),
|
|
.io_scan_mode(rvclkhdr_522_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_523 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_523_io_l1clk),
|
|
.io_clk(rvclkhdr_523_io_clk),
|
|
.io_en(rvclkhdr_523_io_en),
|
|
.io_scan_mode(rvclkhdr_523_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_524 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_524_io_l1clk),
|
|
.io_clk(rvclkhdr_524_io_clk),
|
|
.io_en(rvclkhdr_524_io_en),
|
|
.io_scan_mode(rvclkhdr_524_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_525 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_525_io_l1clk),
|
|
.io_clk(rvclkhdr_525_io_clk),
|
|
.io_en(rvclkhdr_525_io_en),
|
|
.io_scan_mode(rvclkhdr_525_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_526 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_526_io_l1clk),
|
|
.io_clk(rvclkhdr_526_io_clk),
|
|
.io_en(rvclkhdr_526_io_en),
|
|
.io_scan_mode(rvclkhdr_526_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_527 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_527_io_l1clk),
|
|
.io_clk(rvclkhdr_527_io_clk),
|
|
.io_en(rvclkhdr_527_io_en),
|
|
.io_scan_mode(rvclkhdr_527_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_528 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_528_io_l1clk),
|
|
.io_clk(rvclkhdr_528_io_clk),
|
|
.io_en(rvclkhdr_528_io_en),
|
|
.io_scan_mode(rvclkhdr_528_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_529 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_529_io_l1clk),
|
|
.io_clk(rvclkhdr_529_io_clk),
|
|
.io_en(rvclkhdr_529_io_en),
|
|
.io_scan_mode(rvclkhdr_529_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_530 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_530_io_l1clk),
|
|
.io_clk(rvclkhdr_530_io_clk),
|
|
.io_en(rvclkhdr_530_io_en),
|
|
.io_scan_mode(rvclkhdr_530_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_531 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_531_io_l1clk),
|
|
.io_clk(rvclkhdr_531_io_clk),
|
|
.io_en(rvclkhdr_531_io_en),
|
|
.io_scan_mode(rvclkhdr_531_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_532 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_532_io_l1clk),
|
|
.io_clk(rvclkhdr_532_io_clk),
|
|
.io_en(rvclkhdr_532_io_en),
|
|
.io_scan_mode(rvclkhdr_532_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_533 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_533_io_l1clk),
|
|
.io_clk(rvclkhdr_533_io_clk),
|
|
.io_en(rvclkhdr_533_io_en),
|
|
.io_scan_mode(rvclkhdr_533_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_534 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_534_io_l1clk),
|
|
.io_clk(rvclkhdr_534_io_clk),
|
|
.io_en(rvclkhdr_534_io_en),
|
|
.io_scan_mode(rvclkhdr_534_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_535 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_535_io_l1clk),
|
|
.io_clk(rvclkhdr_535_io_clk),
|
|
.io_en(rvclkhdr_535_io_en),
|
|
.io_scan_mode(rvclkhdr_535_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_536 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_536_io_l1clk),
|
|
.io_clk(rvclkhdr_536_io_clk),
|
|
.io_en(rvclkhdr_536_io_en),
|
|
.io_scan_mode(rvclkhdr_536_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_537 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_537_io_l1clk),
|
|
.io_clk(rvclkhdr_537_io_clk),
|
|
.io_en(rvclkhdr_537_io_en),
|
|
.io_scan_mode(rvclkhdr_537_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_538 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_538_io_l1clk),
|
|
.io_clk(rvclkhdr_538_io_clk),
|
|
.io_en(rvclkhdr_538_io_en),
|
|
.io_scan_mode(rvclkhdr_538_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_539 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_539_io_l1clk),
|
|
.io_clk(rvclkhdr_539_io_clk),
|
|
.io_en(rvclkhdr_539_io_en),
|
|
.io_scan_mode(rvclkhdr_539_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_540 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_540_io_l1clk),
|
|
.io_clk(rvclkhdr_540_io_clk),
|
|
.io_en(rvclkhdr_540_io_en),
|
|
.io_scan_mode(rvclkhdr_540_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_541 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_541_io_l1clk),
|
|
.io_clk(rvclkhdr_541_io_clk),
|
|
.io_en(rvclkhdr_541_io_en),
|
|
.io_scan_mode(rvclkhdr_541_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_542 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_542_io_l1clk),
|
|
.io_clk(rvclkhdr_542_io_clk),
|
|
.io_en(rvclkhdr_542_io_en),
|
|
.io_scan_mode(rvclkhdr_542_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_543 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_543_io_l1clk),
|
|
.io_clk(rvclkhdr_543_io_clk),
|
|
.io_en(rvclkhdr_543_io_en),
|
|
.io_scan_mode(rvclkhdr_543_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_544 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_544_io_l1clk),
|
|
.io_clk(rvclkhdr_544_io_clk),
|
|
.io_en(rvclkhdr_544_io_en),
|
|
.io_scan_mode(rvclkhdr_544_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_545 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_545_io_l1clk),
|
|
.io_clk(rvclkhdr_545_io_clk),
|
|
.io_en(rvclkhdr_545_io_en),
|
|
.io_scan_mode(rvclkhdr_545_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_546 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_546_io_l1clk),
|
|
.io_clk(rvclkhdr_546_io_clk),
|
|
.io_en(rvclkhdr_546_io_en),
|
|
.io_scan_mode(rvclkhdr_546_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_547 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_547_io_l1clk),
|
|
.io_clk(rvclkhdr_547_io_clk),
|
|
.io_en(rvclkhdr_547_io_en),
|
|
.io_scan_mode(rvclkhdr_547_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_548 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_548_io_l1clk),
|
|
.io_clk(rvclkhdr_548_io_clk),
|
|
.io_en(rvclkhdr_548_io_en),
|
|
.io_scan_mode(rvclkhdr_548_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_549 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_549_io_l1clk),
|
|
.io_clk(rvclkhdr_549_io_clk),
|
|
.io_en(rvclkhdr_549_io_en),
|
|
.io_scan_mode(rvclkhdr_549_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_550 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_550_io_l1clk),
|
|
.io_clk(rvclkhdr_550_io_clk),
|
|
.io_en(rvclkhdr_550_io_en),
|
|
.io_scan_mode(rvclkhdr_550_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_551 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_551_io_l1clk),
|
|
.io_clk(rvclkhdr_551_io_clk),
|
|
.io_en(rvclkhdr_551_io_en),
|
|
.io_scan_mode(rvclkhdr_551_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_552 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_552_io_l1clk),
|
|
.io_clk(rvclkhdr_552_io_clk),
|
|
.io_en(rvclkhdr_552_io_en),
|
|
.io_scan_mode(rvclkhdr_552_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_553 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_553_io_l1clk),
|
|
.io_clk(rvclkhdr_553_io_clk),
|
|
.io_en(rvclkhdr_553_io_en),
|
|
.io_scan_mode(rvclkhdr_553_io_scan_mode)
|
|
);
|
|
assign io_ifu_bp_hit_taken_f = _T_237 & _T_238; // @[el2_ifu_bp_ctl.scala 273:25]
|
|
assign io_ifu_bp_btb_target_f = _T_428 ? rets_out_0[31:1] : bp_btb_target_adder_f[31:1]; // @[el2_ifu_bp_ctl.scala 369:26]
|
|
assign io_ifu_bp_inst_mask_f = _T_274 | _T_275; // @[el2_ifu_bp_ctl.scala 297:25]
|
|
assign io_ifu_bp_fghr_f = fghr; // @[el2_ifu_bp_ctl.scala 337:20]
|
|
assign io_ifu_bp_way_f = tag_match_vway1_expanded_f | _T_212; // @[el2_ifu_bp_ctl.scala 247:19]
|
|
assign io_ifu_bp_ret_f = {_T_294,_T_300}; // @[el2_ifu_bp_ctl.scala 343:19]
|
|
assign io_ifu_bp_hist1_f = bht_force_taken_f | _T_279; // @[el2_ifu_bp_ctl.scala 338:21]
|
|
assign io_ifu_bp_hist0_f = {bht_vbank1_rd_data_f[0],bht_vbank0_rd_data_f[0]}; // @[el2_ifu_bp_ctl.scala 339:21]
|
|
assign io_ifu_bp_pc4_f = {_T_285,_T_288}; // @[el2_ifu_bp_ctl.scala 340:19]
|
|
assign io_ifu_bp_valid_f = vwayhit_f & _T_344; // @[el2_ifu_bp_ctl.scala 342:21]
|
|
assign io_ifu_bp_poffset_f = btb_sel_data_f[15:4]; // @[el2_ifu_bp_ctl.scala 356:23]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = io_ifc_fetch_req_f | exu_mp_valid; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = _T_375 & io_ic_hit_f; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_2_io_en = ~rs_hold; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_4_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_5_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_6_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_7_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_8_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_9_io_en = _T_472 & io_ifu_bp_hit_taken_f; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_10_io_en = _T_575 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_11_io_en = _T_578 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_12_io_en = _T_581 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_13_io_en = _T_584 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_14_io_en = _T_587 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_15_io_en = _T_590 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_16_io_en = _T_593 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_17_io_en = _T_596 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_18_io_en = _T_599 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_19_io_en = _T_602 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_20_io_en = _T_605 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_21_io_en = _T_608 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_22_io_en = _T_611 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_23_io_en = _T_614 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_24_io_en = _T_617 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_25_io_en = _T_620 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_26_io_en = _T_623 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_27_io_en = _T_626 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_28_io_en = _T_629 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_29_io_en = _T_632 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_30_io_en = _T_635 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_31_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_31_io_en = _T_638 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_32_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_32_io_en = _T_641 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_33_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_33_io_en = _T_644 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_34_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_34_io_en = _T_647 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_35_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_35_io_en = _T_650 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_35_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_36_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_36_io_en = _T_653 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_36_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_37_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_37_io_en = _T_656 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_37_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_38_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_38_io_en = _T_659 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_38_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_39_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_39_io_en = _T_662 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_39_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_40_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_40_io_en = _T_665 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_40_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_41_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_41_io_en = _T_668 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_41_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_42_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_42_io_en = _T_671 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_42_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_43_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_43_io_en = _T_674 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_43_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_44_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_44_io_en = _T_677 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_44_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_45_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_45_io_en = _T_680 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_45_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_46_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_46_io_en = _T_683 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_46_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_47_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_47_io_en = _T_686 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_47_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_48_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_48_io_en = _T_689 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_48_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_49_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_49_io_en = _T_692 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_49_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_50_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_50_io_en = _T_695 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_50_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_51_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_51_io_en = _T_698 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_51_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_52_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_52_io_en = _T_701 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_52_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_53_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_53_io_en = _T_704 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_53_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_54_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_54_io_en = _T_707 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_54_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_55_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_55_io_en = _T_710 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_55_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_56_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_56_io_en = _T_713 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_56_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_57_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_57_io_en = _T_716 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_57_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_58_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_58_io_en = _T_719 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_58_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_59_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_59_io_en = _T_722 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_59_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_60_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_60_io_en = _T_725 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_60_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_61_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_61_io_en = _T_728 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_61_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_62_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_62_io_en = _T_731 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_62_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_63_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_63_io_en = _T_734 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_63_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_64_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_64_io_en = _T_737 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_64_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_65_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_65_io_en = _T_740 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_65_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_66_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_66_io_en = _T_743 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_66_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_67_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_67_io_en = _T_746 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_67_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_68_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_68_io_en = _T_749 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_68_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_69_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_69_io_en = _T_752 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_69_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_70_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_70_io_en = _T_755 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_70_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_71_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_71_io_en = _T_758 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_71_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_72_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_72_io_en = _T_761 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_72_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_73_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_73_io_en = _T_764 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_73_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_74_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_74_io_en = _T_767 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_74_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_75_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_75_io_en = _T_770 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_75_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_76_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_76_io_en = _T_773 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_76_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_77_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_77_io_en = _T_776 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_77_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_78_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_78_io_en = _T_779 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_78_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_79_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_79_io_en = _T_782 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_79_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_80_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_80_io_en = _T_785 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_80_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_81_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_81_io_en = _T_788 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_81_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_82_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_82_io_en = _T_791 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_82_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_83_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_83_io_en = _T_794 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_83_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_84_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_84_io_en = _T_797 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_84_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_85_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_85_io_en = _T_800 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_85_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_86_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_86_io_en = _T_803 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_86_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_87_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_87_io_en = _T_806 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_87_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_88_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_88_io_en = _T_809 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_88_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_89_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_89_io_en = _T_812 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_89_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_90_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_90_io_en = _T_815 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_90_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_91_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_91_io_en = _T_818 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_91_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_92_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_92_io_en = _T_821 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_92_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_93_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_93_io_en = _T_824 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_93_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_94_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_94_io_en = _T_827 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_94_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_95_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_95_io_en = _T_830 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_95_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_96_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_96_io_en = _T_833 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_96_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_97_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_97_io_en = _T_836 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_97_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_98_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_98_io_en = _T_839 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_98_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_99_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_99_io_en = _T_842 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_99_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_100_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_100_io_en = _T_845 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_100_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_101_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_101_io_en = _T_848 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_101_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_102_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_102_io_en = _T_851 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_102_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_103_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_103_io_en = _T_854 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_103_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_104_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_104_io_en = _T_857 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_104_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_105_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_105_io_en = _T_860 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_105_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_106_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_106_io_en = _T_863 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_106_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_107_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_107_io_en = _T_866 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_107_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_108_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_108_io_en = _T_869 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_108_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_109_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_109_io_en = _T_872 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_109_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_110_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_110_io_en = _T_875 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_110_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_111_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_111_io_en = _T_878 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_111_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_112_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_112_io_en = _T_881 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_112_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_113_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_113_io_en = _T_884 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_113_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_114_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_114_io_en = _T_887 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_114_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_115_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_115_io_en = _T_890 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_115_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_116_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_116_io_en = _T_893 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_116_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_117_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_117_io_en = _T_896 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_117_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_118_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_118_io_en = _T_899 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_118_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_119_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_119_io_en = _T_902 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_119_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_120_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_120_io_en = _T_905 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_120_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_121_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_121_io_en = _T_908 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_121_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_122_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_122_io_en = _T_911 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_122_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_123_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_123_io_en = _T_914 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_123_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_124_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_124_io_en = _T_917 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_124_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_125_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_125_io_en = _T_920 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_125_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_126_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_126_io_en = _T_923 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_126_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_127_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_127_io_en = _T_926 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_127_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_128_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_128_io_en = _T_929 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_128_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_129_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_129_io_en = _T_932 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_129_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_130_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_130_io_en = _T_935 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_130_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_131_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_131_io_en = _T_938 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_131_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_132_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_132_io_en = _T_941 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_132_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_133_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_133_io_en = _T_944 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_133_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_134_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_134_io_en = _T_947 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_134_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_135_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_135_io_en = _T_950 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_135_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_136_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_136_io_en = _T_953 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_136_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_137_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_137_io_en = _T_956 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_137_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_138_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_138_io_en = _T_959 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_138_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_139_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_139_io_en = _T_962 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_139_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_140_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_140_io_en = _T_965 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_140_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_141_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_141_io_en = _T_968 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_141_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_142_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_142_io_en = _T_971 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_142_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_143_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_143_io_en = _T_974 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_143_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_144_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_144_io_en = _T_977 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_144_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_145_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_145_io_en = _T_980 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_145_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_146_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_146_io_en = _T_983 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_146_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_147_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_147_io_en = _T_986 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_147_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_148_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_148_io_en = _T_989 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_148_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_149_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_149_io_en = _T_992 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_149_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_150_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_150_io_en = _T_995 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_150_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_151_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_151_io_en = _T_998 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_151_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_152_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_152_io_en = _T_1001 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_152_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_153_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_153_io_en = _T_1004 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_153_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_154_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_154_io_en = _T_1007 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_154_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_155_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_155_io_en = _T_1010 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_155_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_156_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_156_io_en = _T_1013 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_156_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_157_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_157_io_en = _T_1016 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_157_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_158_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_158_io_en = _T_1019 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_158_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_159_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_159_io_en = _T_1022 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_159_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_160_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_160_io_en = _T_1025 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_160_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_161_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_161_io_en = _T_1028 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_161_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_162_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_162_io_en = _T_1031 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_162_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_163_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_163_io_en = _T_1034 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_163_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_164_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_164_io_en = _T_1037 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_164_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_165_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_165_io_en = _T_1040 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_165_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_166_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_166_io_en = _T_1043 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_166_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_167_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_167_io_en = _T_1046 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_167_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_168_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_168_io_en = _T_1049 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_168_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_169_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_169_io_en = _T_1052 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_169_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_170_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_170_io_en = _T_1055 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_170_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_171_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_171_io_en = _T_1058 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_171_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_172_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_172_io_en = _T_1061 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_172_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_173_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_173_io_en = _T_1064 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_173_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_174_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_174_io_en = _T_1067 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_174_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_175_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_175_io_en = _T_1070 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_175_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_176_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_176_io_en = _T_1073 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_176_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_177_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_177_io_en = _T_1076 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_177_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_178_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_178_io_en = _T_1079 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_178_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_179_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_179_io_en = _T_1082 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_179_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_180_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_180_io_en = _T_1085 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_180_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_181_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_181_io_en = _T_1088 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_181_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_182_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_182_io_en = _T_1091 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_182_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_183_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_183_io_en = _T_1094 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_183_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_184_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_184_io_en = _T_1097 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_184_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_185_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_185_io_en = _T_1100 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_185_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_186_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_186_io_en = _T_1103 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_186_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_187_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_187_io_en = _T_1106 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_187_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_188_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_188_io_en = _T_1109 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_188_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_189_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_189_io_en = _T_1112 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_189_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_190_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_190_io_en = _T_1115 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_190_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_191_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_191_io_en = _T_1118 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_191_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_192_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_192_io_en = _T_1121 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_192_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_193_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_193_io_en = _T_1124 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_193_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_194_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_194_io_en = _T_1127 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_194_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_195_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_195_io_en = _T_1130 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_195_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_196_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_196_io_en = _T_1133 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_196_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_197_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_197_io_en = _T_1136 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_197_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_198_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_198_io_en = _T_1139 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_198_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_199_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_199_io_en = _T_1142 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_199_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_200_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_200_io_en = _T_1145 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_200_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_201_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_201_io_en = _T_1148 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_201_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_202_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_202_io_en = _T_1151 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_202_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_203_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_203_io_en = _T_1154 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_203_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_204_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_204_io_en = _T_1157 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_204_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_205_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_205_io_en = _T_1160 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_205_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_206_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_206_io_en = _T_1163 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_206_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_207_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_207_io_en = _T_1166 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_207_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_208_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_208_io_en = _T_1169 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_208_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_209_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_209_io_en = _T_1172 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_209_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_210_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_210_io_en = _T_1175 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_210_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_211_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_211_io_en = _T_1178 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_211_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_212_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_212_io_en = _T_1181 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_212_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_213_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_213_io_en = _T_1184 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_213_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_214_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_214_io_en = _T_1187 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_214_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_215_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_215_io_en = _T_1190 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_215_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_216_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_216_io_en = _T_1193 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_216_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_217_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_217_io_en = _T_1196 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_217_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_218_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_218_io_en = _T_1199 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_218_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_219_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_219_io_en = _T_1202 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_219_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_220_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_220_io_en = _T_1205 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_220_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_221_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_221_io_en = _T_1208 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_221_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_222_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_222_io_en = _T_1211 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_222_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_223_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_223_io_en = _T_1214 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_223_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_224_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_224_io_en = _T_1217 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_224_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_225_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_225_io_en = _T_1220 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_225_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_226_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_226_io_en = _T_1223 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_226_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_227_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_227_io_en = _T_1226 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_227_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_228_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_228_io_en = _T_1229 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_228_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_229_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_229_io_en = _T_1232 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_229_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_230_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_230_io_en = _T_1235 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_230_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_231_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_231_io_en = _T_1238 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_231_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_232_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_232_io_en = _T_1241 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_232_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_233_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_233_io_en = _T_1244 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_233_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_234_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_234_io_en = _T_1247 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_234_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_235_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_235_io_en = _T_1250 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_235_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_236_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_236_io_en = _T_1253 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_236_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_237_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_237_io_en = _T_1256 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_237_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_238_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_238_io_en = _T_1259 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_238_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_239_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_239_io_en = _T_1262 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_239_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_240_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_240_io_en = _T_1265 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_240_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_241_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_241_io_en = _T_1268 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_241_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_242_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_242_io_en = _T_1271 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_242_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_243_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_243_io_en = _T_1274 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_243_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_244_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_244_io_en = _T_1277 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_244_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_245_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_245_io_en = _T_1280 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_245_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_246_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_246_io_en = _T_1283 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_246_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_247_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_247_io_en = _T_1286 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_247_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_248_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_248_io_en = _T_1289 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_248_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_249_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_249_io_en = _T_1292 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_249_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_250_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_250_io_en = _T_1295 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_250_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_251_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_251_io_en = _T_1298 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_251_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_252_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_252_io_en = _T_1301 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_252_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_253_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_253_io_en = _T_1304 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_253_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_254_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_254_io_en = _T_1307 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_254_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_255_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_255_io_en = _T_1310 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_255_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_256_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_256_io_en = _T_1313 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_256_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_257_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_257_io_en = _T_1316 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_257_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_258_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_258_io_en = _T_1319 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_258_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_259_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_259_io_en = _T_1322 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_259_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_260_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_260_io_en = _T_1325 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_260_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_261_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_261_io_en = _T_1328 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_261_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_262_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_262_io_en = _T_1331 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_262_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_263_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_263_io_en = _T_1334 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_263_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_264_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_264_io_en = _T_1337 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_264_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_265_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_265_io_en = _T_1340 & btb_wr_en_way0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_265_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_266_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_266_io_en = _T_575 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_266_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_267_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_267_io_en = _T_578 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_267_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_268_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_268_io_en = _T_581 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_268_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_269_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_269_io_en = _T_584 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_269_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_270_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_270_io_en = _T_587 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_270_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_271_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_271_io_en = _T_590 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_271_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_272_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_272_io_en = _T_593 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_272_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_273_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_273_io_en = _T_596 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_273_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_274_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_274_io_en = _T_599 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_274_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_275_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_275_io_en = _T_602 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_275_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_276_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_276_io_en = _T_605 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_276_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_277_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_277_io_en = _T_608 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_277_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_278_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_278_io_en = _T_611 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_278_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_279_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_279_io_en = _T_614 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_279_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_280_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_280_io_en = _T_617 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_280_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_281_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_281_io_en = _T_620 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_281_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_282_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_282_io_en = _T_623 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_282_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_283_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_283_io_en = _T_626 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_283_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_284_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_284_io_en = _T_629 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_284_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_285_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_285_io_en = _T_632 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_285_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_286_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_286_io_en = _T_635 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_286_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_287_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_287_io_en = _T_638 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_287_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_288_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_288_io_en = _T_641 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_288_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_289_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_289_io_en = _T_644 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_289_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_290_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_290_io_en = _T_647 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_290_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_291_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_291_io_en = _T_650 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_291_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_292_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_292_io_en = _T_653 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_292_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_293_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_293_io_en = _T_656 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_293_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_294_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_294_io_en = _T_659 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_294_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_295_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_295_io_en = _T_662 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_295_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_296_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_296_io_en = _T_665 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_296_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_297_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_297_io_en = _T_668 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_297_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_298_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_298_io_en = _T_671 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_298_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_299_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_299_io_en = _T_674 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_299_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_300_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_300_io_en = _T_677 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_300_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_301_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_301_io_en = _T_680 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_301_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_302_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_302_io_en = _T_683 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_302_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_303_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_303_io_en = _T_686 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_303_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_304_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_304_io_en = _T_689 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_304_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_305_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_305_io_en = _T_692 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_305_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_306_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_306_io_en = _T_695 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_306_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_307_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_307_io_en = _T_698 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_307_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_308_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_308_io_en = _T_701 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_308_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_309_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_309_io_en = _T_704 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_309_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_310_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_310_io_en = _T_707 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_310_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_311_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_311_io_en = _T_710 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_311_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_312_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_312_io_en = _T_713 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_312_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_313_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_313_io_en = _T_716 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_313_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_314_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_314_io_en = _T_719 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_314_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_315_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_315_io_en = _T_722 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_315_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_316_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_316_io_en = _T_725 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_316_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_317_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_317_io_en = _T_728 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_317_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_318_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_318_io_en = _T_731 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_318_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_319_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_319_io_en = _T_734 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_319_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_320_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_320_io_en = _T_737 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_320_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_321_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_321_io_en = _T_740 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_321_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_322_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_322_io_en = _T_743 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_322_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_323_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_323_io_en = _T_746 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_323_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_324_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_324_io_en = _T_749 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_324_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_325_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_325_io_en = _T_752 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_325_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_326_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_326_io_en = _T_755 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_326_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_327_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_327_io_en = _T_758 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_327_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_328_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_328_io_en = _T_761 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_328_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_329_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_329_io_en = _T_764 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_329_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_330_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_330_io_en = _T_767 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_330_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_331_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_331_io_en = _T_770 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_331_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_332_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_332_io_en = _T_773 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_332_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_333_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_333_io_en = _T_776 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_333_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_334_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_334_io_en = _T_779 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_334_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_335_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_335_io_en = _T_782 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_335_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_336_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_336_io_en = _T_785 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_336_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_337_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_337_io_en = _T_788 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_337_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_338_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_338_io_en = _T_791 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_338_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_339_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_339_io_en = _T_794 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_339_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_340_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_340_io_en = _T_797 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_340_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_341_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_341_io_en = _T_800 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_341_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_342_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_342_io_en = _T_803 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_342_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_343_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_343_io_en = _T_806 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_343_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_344_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_344_io_en = _T_809 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_344_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_345_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_345_io_en = _T_812 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_345_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_346_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_346_io_en = _T_815 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_346_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_347_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_347_io_en = _T_818 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_347_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_348_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_348_io_en = _T_821 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_348_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_349_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_349_io_en = _T_824 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_349_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_350_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_350_io_en = _T_827 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_350_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_351_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_351_io_en = _T_830 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_351_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_352_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_352_io_en = _T_833 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_352_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_353_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_353_io_en = _T_836 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_353_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_354_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_354_io_en = _T_839 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_354_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_355_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_355_io_en = _T_842 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_355_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_356_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_356_io_en = _T_845 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_356_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_357_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_357_io_en = _T_848 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_357_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_358_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_358_io_en = _T_851 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_358_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_359_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_359_io_en = _T_854 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_359_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_360_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_360_io_en = _T_857 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_360_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_361_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_361_io_en = _T_860 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_361_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_362_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_362_io_en = _T_863 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_362_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_363_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_363_io_en = _T_866 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_363_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_364_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_364_io_en = _T_869 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_364_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_365_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_365_io_en = _T_872 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_365_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_366_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_366_io_en = _T_875 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_366_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_367_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_367_io_en = _T_878 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_367_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_368_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_368_io_en = _T_881 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_368_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_369_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_369_io_en = _T_884 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_369_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_370_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_370_io_en = _T_887 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_370_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_371_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_371_io_en = _T_890 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_371_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_372_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_372_io_en = _T_893 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_372_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_373_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_373_io_en = _T_896 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_373_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_374_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_374_io_en = _T_899 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_374_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_375_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_375_io_en = _T_902 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_375_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_376_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_376_io_en = _T_905 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_376_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_377_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_377_io_en = _T_908 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_377_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_378_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_378_io_en = _T_911 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_378_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_379_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_379_io_en = _T_914 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_379_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_380_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_380_io_en = _T_917 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_380_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_381_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_381_io_en = _T_920 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_381_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_382_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_382_io_en = _T_923 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_382_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_383_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_383_io_en = _T_926 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_383_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_384_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_384_io_en = _T_929 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_384_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_385_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_385_io_en = _T_932 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_385_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_386_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_386_io_en = _T_935 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_386_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_387_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_387_io_en = _T_938 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_387_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_388_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_388_io_en = _T_941 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_388_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_389_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_389_io_en = _T_944 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_389_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_390_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_390_io_en = _T_947 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_390_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_391_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_391_io_en = _T_950 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_391_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_392_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_392_io_en = _T_953 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_392_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_393_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_393_io_en = _T_956 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_393_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_394_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_394_io_en = _T_959 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_394_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_395_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_395_io_en = _T_962 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_395_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_396_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_396_io_en = _T_965 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_396_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_397_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_397_io_en = _T_968 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_397_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_398_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_398_io_en = _T_971 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_398_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_399_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_399_io_en = _T_974 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_399_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_400_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_400_io_en = _T_977 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_400_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_401_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_401_io_en = _T_980 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_401_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_402_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_402_io_en = _T_983 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_402_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_403_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_403_io_en = _T_986 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_403_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_404_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_404_io_en = _T_989 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_404_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_405_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_405_io_en = _T_992 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_405_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_406_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_406_io_en = _T_995 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_406_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_407_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_407_io_en = _T_998 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_407_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_408_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_408_io_en = _T_1001 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_408_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_409_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_409_io_en = _T_1004 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_409_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_410_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_410_io_en = _T_1007 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_410_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_411_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_411_io_en = _T_1010 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_411_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_412_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_412_io_en = _T_1013 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_412_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_413_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_413_io_en = _T_1016 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_413_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_414_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_414_io_en = _T_1019 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_414_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_415_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_415_io_en = _T_1022 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_415_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_416_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_416_io_en = _T_1025 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_416_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_417_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_417_io_en = _T_1028 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_417_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_418_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_418_io_en = _T_1031 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_418_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_419_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_419_io_en = _T_1034 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_419_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_420_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_420_io_en = _T_1037 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_420_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_421_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_421_io_en = _T_1040 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_421_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_422_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_422_io_en = _T_1043 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_422_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_423_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_423_io_en = _T_1046 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_423_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_424_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_424_io_en = _T_1049 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_424_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_425_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_425_io_en = _T_1052 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_425_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_426_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_426_io_en = _T_1055 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_426_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_427_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_427_io_en = _T_1058 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_427_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_428_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_428_io_en = _T_1061 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_428_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_429_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_429_io_en = _T_1064 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_429_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_430_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_430_io_en = _T_1067 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_430_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_431_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_431_io_en = _T_1070 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_431_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_432_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_432_io_en = _T_1073 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_432_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_433_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_433_io_en = _T_1076 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_433_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_434_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_434_io_en = _T_1079 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_434_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_435_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_435_io_en = _T_1082 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_435_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_436_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_436_io_en = _T_1085 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_436_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_437_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_437_io_en = _T_1088 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_437_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_438_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_438_io_en = _T_1091 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_438_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_439_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_439_io_en = _T_1094 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_439_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_440_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_440_io_en = _T_1097 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_440_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_441_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_441_io_en = _T_1100 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_441_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_442_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_442_io_en = _T_1103 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_442_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_443_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_443_io_en = _T_1106 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_443_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_444_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_444_io_en = _T_1109 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_444_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_445_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_445_io_en = _T_1112 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_445_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_446_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_446_io_en = _T_1115 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_446_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_447_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_447_io_en = _T_1118 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_447_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_448_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_448_io_en = _T_1121 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_448_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_449_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_449_io_en = _T_1124 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_449_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_450_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_450_io_en = _T_1127 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_450_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_451_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_451_io_en = _T_1130 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_451_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_452_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_452_io_en = _T_1133 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_452_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_453_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_453_io_en = _T_1136 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_453_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_454_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_454_io_en = _T_1139 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_454_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_455_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_455_io_en = _T_1142 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_455_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_456_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_456_io_en = _T_1145 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_456_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_457_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_457_io_en = _T_1148 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_457_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_458_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_458_io_en = _T_1151 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_458_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_459_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_459_io_en = _T_1154 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_459_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_460_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_460_io_en = _T_1157 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_460_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_461_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_461_io_en = _T_1160 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_461_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_462_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_462_io_en = _T_1163 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_462_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_463_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_463_io_en = _T_1166 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_463_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_464_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_464_io_en = _T_1169 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_464_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_465_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_465_io_en = _T_1172 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_465_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_466_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_466_io_en = _T_1175 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_466_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_467_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_467_io_en = _T_1178 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_467_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_468_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_468_io_en = _T_1181 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_468_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_469_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_469_io_en = _T_1184 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_469_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_470_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_470_io_en = _T_1187 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_470_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_471_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_471_io_en = _T_1190 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_471_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_472_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_472_io_en = _T_1193 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_472_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_473_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_473_io_en = _T_1196 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_473_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_474_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_474_io_en = _T_1199 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_474_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_475_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_475_io_en = _T_1202 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_475_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_476_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_476_io_en = _T_1205 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_476_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_477_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_477_io_en = _T_1208 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_477_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_478_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_478_io_en = _T_1211 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_478_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_479_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_479_io_en = _T_1214 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_479_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_480_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_480_io_en = _T_1217 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_480_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_481_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_481_io_en = _T_1220 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_481_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_482_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_482_io_en = _T_1223 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_482_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_483_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_483_io_en = _T_1226 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_483_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_484_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_484_io_en = _T_1229 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_484_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_485_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_485_io_en = _T_1232 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_485_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_486_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_486_io_en = _T_1235 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_486_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_487_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_487_io_en = _T_1238 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_487_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_488_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_488_io_en = _T_1241 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_488_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_489_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_489_io_en = _T_1244 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_489_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_490_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_490_io_en = _T_1247 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_490_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_491_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_491_io_en = _T_1250 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_491_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_492_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_492_io_en = _T_1253 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_492_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_493_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_493_io_en = _T_1256 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_493_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_494_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_494_io_en = _T_1259 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_494_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_495_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_495_io_en = _T_1262 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_495_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_496_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_496_io_en = _T_1265 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_496_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_497_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_497_io_en = _T_1268 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_497_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_498_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_498_io_en = _T_1271 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_498_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_499_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_499_io_en = _T_1274 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_499_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_500_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_500_io_en = _T_1277 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_500_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_501_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_501_io_en = _T_1280 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_501_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_502_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_502_io_en = _T_1283 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_502_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_503_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_503_io_en = _T_1286 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_503_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_504_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_504_io_en = _T_1289 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_504_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_505_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_505_io_en = _T_1292 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_505_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_506_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_506_io_en = _T_1295 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_506_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_507_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_507_io_en = _T_1298 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_507_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_508_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_508_io_en = _T_1301 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_508_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_509_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_509_io_en = _T_1304 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_509_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_510_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_510_io_en = _T_1307 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_510_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_511_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_511_io_en = _T_1310 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_511_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_512_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_512_io_en = _T_1313 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_512_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_513_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_513_io_en = _T_1316 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_513_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_514_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_514_io_en = _T_1319 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_514_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_515_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_515_io_en = _T_1322 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_515_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_516_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_516_io_en = _T_1325 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_516_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_517_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_517_io_en = _T_1328 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_517_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_518_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_518_io_en = _T_1331 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_518_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_519_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_519_io_en = _T_1334 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_519_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_520_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_520_io_en = _T_1337 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_520_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_521_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_521_io_en = _T_1340 & btb_wr_en_way1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_521_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_522_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_522_io_en = _T_6211 | _T_6216; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_522_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_523_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_523_io_en = _T_6222 | _T_6227; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_523_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_524_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_524_io_en = _T_6233 | _T_6238; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_524_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_525_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_525_io_en = _T_6244 | _T_6249; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_525_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_526_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_526_io_en = _T_6255 | _T_6260; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_526_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_527_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_527_io_en = _T_6266 | _T_6271; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_527_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_528_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_528_io_en = _T_6277 | _T_6282; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_528_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_529_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_529_io_en = _T_6288 | _T_6293; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_529_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_530_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_530_io_en = _T_6299 | _T_6304; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_530_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_531_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_531_io_en = _T_6310 | _T_6315; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_531_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_532_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_532_io_en = _T_6321 | _T_6326; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_532_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_533_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_533_io_en = _T_6332 | _T_6337; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_533_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_534_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_534_io_en = _T_6343 | _T_6348; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_534_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_535_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_535_io_en = _T_6354 | _T_6359; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_535_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_536_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_536_io_en = _T_6365 | _T_6370; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_536_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_537_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_537_io_en = _T_6376 | _T_6381; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_537_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_538_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_538_io_en = _T_6387 | _T_6392; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_538_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_539_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_539_io_en = _T_6398 | _T_6403; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_539_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_540_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_540_io_en = _T_6409 | _T_6414; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_540_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_541_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_541_io_en = _T_6420 | _T_6425; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_541_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_542_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_542_io_en = _T_6431 | _T_6436; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_542_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_543_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_543_io_en = _T_6442 | _T_6447; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_543_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_544_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_544_io_en = _T_6453 | _T_6458; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_544_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_545_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_545_io_en = _T_6464 | _T_6469; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_545_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_546_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_546_io_en = _T_6475 | _T_6480; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_546_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_547_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_547_io_en = _T_6486 | _T_6491; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_547_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_548_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_548_io_en = _T_6497 | _T_6502; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_548_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_549_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_549_io_en = _T_6508 | _T_6513; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_549_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_550_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_550_io_en = _T_6519 | _T_6524; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_550_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_551_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_551_io_en = _T_6530 | _T_6535; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_551_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_552_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_552_io_en = _T_6541 | _T_6546; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_552_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_553_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_553_io_en = _T_6552 | _T_6557; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_553_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
leak_one_f_d1 = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_0 = _RAND_1[21:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_1 = _RAND_2[21:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_2 = _RAND_3[21:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_3 = _RAND_4[21:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_4 = _RAND_5[21:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_5 = _RAND_6[21:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_6 = _RAND_7[21:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_7 = _RAND_8[21:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_8 = _RAND_9[21:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_9 = _RAND_10[21:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_10 = _RAND_11[21:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_11 = _RAND_12[21:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_12 = _RAND_13[21:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_13 = _RAND_14[21:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_14 = _RAND_15[21:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_15 = _RAND_16[21:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_16 = _RAND_17[21:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_17 = _RAND_18[21:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_18 = _RAND_19[21:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_19 = _RAND_20[21:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_20 = _RAND_21[21:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_21 = _RAND_22[21:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_22 = _RAND_23[21:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_23 = _RAND_24[21:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_24 = _RAND_25[21:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_25 = _RAND_26[21:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_26 = _RAND_27[21:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_27 = _RAND_28[21:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_28 = _RAND_29[21:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_29 = _RAND_30[21:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_30 = _RAND_31[21:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_31 = _RAND_32[21:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_32 = _RAND_33[21:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_33 = _RAND_34[21:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_34 = _RAND_35[21:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_35 = _RAND_36[21:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_36 = _RAND_37[21:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_37 = _RAND_38[21:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_38 = _RAND_39[21:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_39 = _RAND_40[21:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_40 = _RAND_41[21:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_41 = _RAND_42[21:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_42 = _RAND_43[21:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_43 = _RAND_44[21:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_44 = _RAND_45[21:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_45 = _RAND_46[21:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_46 = _RAND_47[21:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_47 = _RAND_48[21:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_48 = _RAND_49[21:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_49 = _RAND_50[21:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_50 = _RAND_51[21:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_51 = _RAND_52[21:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_52 = _RAND_53[21:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_53 = _RAND_54[21:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_54 = _RAND_55[21:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_55 = _RAND_56[21:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_56 = _RAND_57[21:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_57 = _RAND_58[21:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_58 = _RAND_59[21:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_59 = _RAND_60[21:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_60 = _RAND_61[21:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_61 = _RAND_62[21:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_62 = _RAND_63[21:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_63 = _RAND_64[21:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_64 = _RAND_65[21:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_65 = _RAND_66[21:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_66 = _RAND_67[21:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_67 = _RAND_68[21:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_68 = _RAND_69[21:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_69 = _RAND_70[21:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_70 = _RAND_71[21:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_71 = _RAND_72[21:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_72 = _RAND_73[21:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_73 = _RAND_74[21:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_74 = _RAND_75[21:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_75 = _RAND_76[21:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_76 = _RAND_77[21:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_77 = _RAND_78[21:0];
|
|
_RAND_79 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_78 = _RAND_79[21:0];
|
|
_RAND_80 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_79 = _RAND_80[21:0];
|
|
_RAND_81 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_80 = _RAND_81[21:0];
|
|
_RAND_82 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_81 = _RAND_82[21:0];
|
|
_RAND_83 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_82 = _RAND_83[21:0];
|
|
_RAND_84 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_83 = _RAND_84[21:0];
|
|
_RAND_85 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_84 = _RAND_85[21:0];
|
|
_RAND_86 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_85 = _RAND_86[21:0];
|
|
_RAND_87 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_86 = _RAND_87[21:0];
|
|
_RAND_88 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_87 = _RAND_88[21:0];
|
|
_RAND_89 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_88 = _RAND_89[21:0];
|
|
_RAND_90 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_89 = _RAND_90[21:0];
|
|
_RAND_91 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_90 = _RAND_91[21:0];
|
|
_RAND_92 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_91 = _RAND_92[21:0];
|
|
_RAND_93 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_92 = _RAND_93[21:0];
|
|
_RAND_94 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_93 = _RAND_94[21:0];
|
|
_RAND_95 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_94 = _RAND_95[21:0];
|
|
_RAND_96 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_95 = _RAND_96[21:0];
|
|
_RAND_97 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_96 = _RAND_97[21:0];
|
|
_RAND_98 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_97 = _RAND_98[21:0];
|
|
_RAND_99 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_98 = _RAND_99[21:0];
|
|
_RAND_100 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_99 = _RAND_100[21:0];
|
|
_RAND_101 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_100 = _RAND_101[21:0];
|
|
_RAND_102 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_101 = _RAND_102[21:0];
|
|
_RAND_103 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_102 = _RAND_103[21:0];
|
|
_RAND_104 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_103 = _RAND_104[21:0];
|
|
_RAND_105 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_104 = _RAND_105[21:0];
|
|
_RAND_106 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_105 = _RAND_106[21:0];
|
|
_RAND_107 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_106 = _RAND_107[21:0];
|
|
_RAND_108 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_107 = _RAND_108[21:0];
|
|
_RAND_109 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_108 = _RAND_109[21:0];
|
|
_RAND_110 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_109 = _RAND_110[21:0];
|
|
_RAND_111 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_110 = _RAND_111[21:0];
|
|
_RAND_112 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_111 = _RAND_112[21:0];
|
|
_RAND_113 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_112 = _RAND_113[21:0];
|
|
_RAND_114 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_113 = _RAND_114[21:0];
|
|
_RAND_115 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_114 = _RAND_115[21:0];
|
|
_RAND_116 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_115 = _RAND_116[21:0];
|
|
_RAND_117 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_116 = _RAND_117[21:0];
|
|
_RAND_118 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_117 = _RAND_118[21:0];
|
|
_RAND_119 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_118 = _RAND_119[21:0];
|
|
_RAND_120 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_119 = _RAND_120[21:0];
|
|
_RAND_121 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_120 = _RAND_121[21:0];
|
|
_RAND_122 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_121 = _RAND_122[21:0];
|
|
_RAND_123 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_122 = _RAND_123[21:0];
|
|
_RAND_124 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_123 = _RAND_124[21:0];
|
|
_RAND_125 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_124 = _RAND_125[21:0];
|
|
_RAND_126 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_125 = _RAND_126[21:0];
|
|
_RAND_127 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_126 = _RAND_127[21:0];
|
|
_RAND_128 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_127 = _RAND_128[21:0];
|
|
_RAND_129 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_128 = _RAND_129[21:0];
|
|
_RAND_130 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_129 = _RAND_130[21:0];
|
|
_RAND_131 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_130 = _RAND_131[21:0];
|
|
_RAND_132 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_131 = _RAND_132[21:0];
|
|
_RAND_133 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_132 = _RAND_133[21:0];
|
|
_RAND_134 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_133 = _RAND_134[21:0];
|
|
_RAND_135 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_134 = _RAND_135[21:0];
|
|
_RAND_136 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_135 = _RAND_136[21:0];
|
|
_RAND_137 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_136 = _RAND_137[21:0];
|
|
_RAND_138 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_137 = _RAND_138[21:0];
|
|
_RAND_139 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_138 = _RAND_139[21:0];
|
|
_RAND_140 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_139 = _RAND_140[21:0];
|
|
_RAND_141 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_140 = _RAND_141[21:0];
|
|
_RAND_142 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_141 = _RAND_142[21:0];
|
|
_RAND_143 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_142 = _RAND_143[21:0];
|
|
_RAND_144 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_143 = _RAND_144[21:0];
|
|
_RAND_145 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_144 = _RAND_145[21:0];
|
|
_RAND_146 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_145 = _RAND_146[21:0];
|
|
_RAND_147 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_146 = _RAND_147[21:0];
|
|
_RAND_148 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_147 = _RAND_148[21:0];
|
|
_RAND_149 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_148 = _RAND_149[21:0];
|
|
_RAND_150 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_149 = _RAND_150[21:0];
|
|
_RAND_151 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_150 = _RAND_151[21:0];
|
|
_RAND_152 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_151 = _RAND_152[21:0];
|
|
_RAND_153 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_152 = _RAND_153[21:0];
|
|
_RAND_154 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_153 = _RAND_154[21:0];
|
|
_RAND_155 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_154 = _RAND_155[21:0];
|
|
_RAND_156 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_155 = _RAND_156[21:0];
|
|
_RAND_157 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_156 = _RAND_157[21:0];
|
|
_RAND_158 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_157 = _RAND_158[21:0];
|
|
_RAND_159 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_158 = _RAND_159[21:0];
|
|
_RAND_160 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_159 = _RAND_160[21:0];
|
|
_RAND_161 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_160 = _RAND_161[21:0];
|
|
_RAND_162 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_161 = _RAND_162[21:0];
|
|
_RAND_163 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_162 = _RAND_163[21:0];
|
|
_RAND_164 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_163 = _RAND_164[21:0];
|
|
_RAND_165 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_164 = _RAND_165[21:0];
|
|
_RAND_166 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_165 = _RAND_166[21:0];
|
|
_RAND_167 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_166 = _RAND_167[21:0];
|
|
_RAND_168 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_167 = _RAND_168[21:0];
|
|
_RAND_169 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_168 = _RAND_169[21:0];
|
|
_RAND_170 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_169 = _RAND_170[21:0];
|
|
_RAND_171 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_170 = _RAND_171[21:0];
|
|
_RAND_172 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_171 = _RAND_172[21:0];
|
|
_RAND_173 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_172 = _RAND_173[21:0];
|
|
_RAND_174 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_173 = _RAND_174[21:0];
|
|
_RAND_175 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_174 = _RAND_175[21:0];
|
|
_RAND_176 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_175 = _RAND_176[21:0];
|
|
_RAND_177 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_176 = _RAND_177[21:0];
|
|
_RAND_178 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_177 = _RAND_178[21:0];
|
|
_RAND_179 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_178 = _RAND_179[21:0];
|
|
_RAND_180 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_179 = _RAND_180[21:0];
|
|
_RAND_181 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_180 = _RAND_181[21:0];
|
|
_RAND_182 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_181 = _RAND_182[21:0];
|
|
_RAND_183 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_182 = _RAND_183[21:0];
|
|
_RAND_184 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_183 = _RAND_184[21:0];
|
|
_RAND_185 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_184 = _RAND_185[21:0];
|
|
_RAND_186 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_185 = _RAND_186[21:0];
|
|
_RAND_187 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_186 = _RAND_187[21:0];
|
|
_RAND_188 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_187 = _RAND_188[21:0];
|
|
_RAND_189 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_188 = _RAND_189[21:0];
|
|
_RAND_190 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_189 = _RAND_190[21:0];
|
|
_RAND_191 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_190 = _RAND_191[21:0];
|
|
_RAND_192 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_191 = _RAND_192[21:0];
|
|
_RAND_193 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_192 = _RAND_193[21:0];
|
|
_RAND_194 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_193 = _RAND_194[21:0];
|
|
_RAND_195 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_194 = _RAND_195[21:0];
|
|
_RAND_196 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_195 = _RAND_196[21:0];
|
|
_RAND_197 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_196 = _RAND_197[21:0];
|
|
_RAND_198 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_197 = _RAND_198[21:0];
|
|
_RAND_199 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_198 = _RAND_199[21:0];
|
|
_RAND_200 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_199 = _RAND_200[21:0];
|
|
_RAND_201 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_200 = _RAND_201[21:0];
|
|
_RAND_202 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_201 = _RAND_202[21:0];
|
|
_RAND_203 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_202 = _RAND_203[21:0];
|
|
_RAND_204 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_203 = _RAND_204[21:0];
|
|
_RAND_205 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_204 = _RAND_205[21:0];
|
|
_RAND_206 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_205 = _RAND_206[21:0];
|
|
_RAND_207 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_206 = _RAND_207[21:0];
|
|
_RAND_208 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_207 = _RAND_208[21:0];
|
|
_RAND_209 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_208 = _RAND_209[21:0];
|
|
_RAND_210 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_209 = _RAND_210[21:0];
|
|
_RAND_211 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_210 = _RAND_211[21:0];
|
|
_RAND_212 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_211 = _RAND_212[21:0];
|
|
_RAND_213 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_212 = _RAND_213[21:0];
|
|
_RAND_214 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_213 = _RAND_214[21:0];
|
|
_RAND_215 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_214 = _RAND_215[21:0];
|
|
_RAND_216 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_215 = _RAND_216[21:0];
|
|
_RAND_217 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_216 = _RAND_217[21:0];
|
|
_RAND_218 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_217 = _RAND_218[21:0];
|
|
_RAND_219 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_218 = _RAND_219[21:0];
|
|
_RAND_220 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_219 = _RAND_220[21:0];
|
|
_RAND_221 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_220 = _RAND_221[21:0];
|
|
_RAND_222 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_221 = _RAND_222[21:0];
|
|
_RAND_223 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_222 = _RAND_223[21:0];
|
|
_RAND_224 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_223 = _RAND_224[21:0];
|
|
_RAND_225 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_224 = _RAND_225[21:0];
|
|
_RAND_226 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_225 = _RAND_226[21:0];
|
|
_RAND_227 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_226 = _RAND_227[21:0];
|
|
_RAND_228 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_227 = _RAND_228[21:0];
|
|
_RAND_229 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_228 = _RAND_229[21:0];
|
|
_RAND_230 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_229 = _RAND_230[21:0];
|
|
_RAND_231 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_230 = _RAND_231[21:0];
|
|
_RAND_232 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_231 = _RAND_232[21:0];
|
|
_RAND_233 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_232 = _RAND_233[21:0];
|
|
_RAND_234 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_233 = _RAND_234[21:0];
|
|
_RAND_235 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_234 = _RAND_235[21:0];
|
|
_RAND_236 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_235 = _RAND_236[21:0];
|
|
_RAND_237 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_236 = _RAND_237[21:0];
|
|
_RAND_238 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_237 = _RAND_238[21:0];
|
|
_RAND_239 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_238 = _RAND_239[21:0];
|
|
_RAND_240 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_239 = _RAND_240[21:0];
|
|
_RAND_241 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_240 = _RAND_241[21:0];
|
|
_RAND_242 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_241 = _RAND_242[21:0];
|
|
_RAND_243 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_242 = _RAND_243[21:0];
|
|
_RAND_244 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_243 = _RAND_244[21:0];
|
|
_RAND_245 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_244 = _RAND_245[21:0];
|
|
_RAND_246 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_245 = _RAND_246[21:0];
|
|
_RAND_247 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_246 = _RAND_247[21:0];
|
|
_RAND_248 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_247 = _RAND_248[21:0];
|
|
_RAND_249 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_248 = _RAND_249[21:0];
|
|
_RAND_250 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_249 = _RAND_250[21:0];
|
|
_RAND_251 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_250 = _RAND_251[21:0];
|
|
_RAND_252 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_251 = _RAND_252[21:0];
|
|
_RAND_253 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_252 = _RAND_253[21:0];
|
|
_RAND_254 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_253 = _RAND_254[21:0];
|
|
_RAND_255 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_254 = _RAND_255[21:0];
|
|
_RAND_256 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_255 = _RAND_256[21:0];
|
|
_RAND_257 = {1{`RANDOM}};
|
|
dec_tlu_way_wb_f = _RAND_257[0:0];
|
|
_RAND_258 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_0 = _RAND_258[21:0];
|
|
_RAND_259 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_1 = _RAND_259[21:0];
|
|
_RAND_260 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_2 = _RAND_260[21:0];
|
|
_RAND_261 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_3 = _RAND_261[21:0];
|
|
_RAND_262 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_4 = _RAND_262[21:0];
|
|
_RAND_263 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_5 = _RAND_263[21:0];
|
|
_RAND_264 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_6 = _RAND_264[21:0];
|
|
_RAND_265 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_7 = _RAND_265[21:0];
|
|
_RAND_266 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_8 = _RAND_266[21:0];
|
|
_RAND_267 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_9 = _RAND_267[21:0];
|
|
_RAND_268 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_10 = _RAND_268[21:0];
|
|
_RAND_269 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_11 = _RAND_269[21:0];
|
|
_RAND_270 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_12 = _RAND_270[21:0];
|
|
_RAND_271 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_13 = _RAND_271[21:0];
|
|
_RAND_272 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_14 = _RAND_272[21:0];
|
|
_RAND_273 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_15 = _RAND_273[21:0];
|
|
_RAND_274 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_16 = _RAND_274[21:0];
|
|
_RAND_275 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_17 = _RAND_275[21:0];
|
|
_RAND_276 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_18 = _RAND_276[21:0];
|
|
_RAND_277 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_19 = _RAND_277[21:0];
|
|
_RAND_278 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_20 = _RAND_278[21:0];
|
|
_RAND_279 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_21 = _RAND_279[21:0];
|
|
_RAND_280 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_22 = _RAND_280[21:0];
|
|
_RAND_281 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_23 = _RAND_281[21:0];
|
|
_RAND_282 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_24 = _RAND_282[21:0];
|
|
_RAND_283 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_25 = _RAND_283[21:0];
|
|
_RAND_284 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_26 = _RAND_284[21:0];
|
|
_RAND_285 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_27 = _RAND_285[21:0];
|
|
_RAND_286 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_28 = _RAND_286[21:0];
|
|
_RAND_287 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_29 = _RAND_287[21:0];
|
|
_RAND_288 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_30 = _RAND_288[21:0];
|
|
_RAND_289 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_31 = _RAND_289[21:0];
|
|
_RAND_290 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_32 = _RAND_290[21:0];
|
|
_RAND_291 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_33 = _RAND_291[21:0];
|
|
_RAND_292 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_34 = _RAND_292[21:0];
|
|
_RAND_293 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_35 = _RAND_293[21:0];
|
|
_RAND_294 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_36 = _RAND_294[21:0];
|
|
_RAND_295 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_37 = _RAND_295[21:0];
|
|
_RAND_296 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_38 = _RAND_296[21:0];
|
|
_RAND_297 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_39 = _RAND_297[21:0];
|
|
_RAND_298 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_40 = _RAND_298[21:0];
|
|
_RAND_299 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_41 = _RAND_299[21:0];
|
|
_RAND_300 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_42 = _RAND_300[21:0];
|
|
_RAND_301 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_43 = _RAND_301[21:0];
|
|
_RAND_302 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_44 = _RAND_302[21:0];
|
|
_RAND_303 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_45 = _RAND_303[21:0];
|
|
_RAND_304 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_46 = _RAND_304[21:0];
|
|
_RAND_305 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_47 = _RAND_305[21:0];
|
|
_RAND_306 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_48 = _RAND_306[21:0];
|
|
_RAND_307 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_49 = _RAND_307[21:0];
|
|
_RAND_308 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_50 = _RAND_308[21:0];
|
|
_RAND_309 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_51 = _RAND_309[21:0];
|
|
_RAND_310 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_52 = _RAND_310[21:0];
|
|
_RAND_311 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_53 = _RAND_311[21:0];
|
|
_RAND_312 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_54 = _RAND_312[21:0];
|
|
_RAND_313 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_55 = _RAND_313[21:0];
|
|
_RAND_314 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_56 = _RAND_314[21:0];
|
|
_RAND_315 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_57 = _RAND_315[21:0];
|
|
_RAND_316 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_58 = _RAND_316[21:0];
|
|
_RAND_317 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_59 = _RAND_317[21:0];
|
|
_RAND_318 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_60 = _RAND_318[21:0];
|
|
_RAND_319 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_61 = _RAND_319[21:0];
|
|
_RAND_320 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_62 = _RAND_320[21:0];
|
|
_RAND_321 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_63 = _RAND_321[21:0];
|
|
_RAND_322 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_64 = _RAND_322[21:0];
|
|
_RAND_323 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_65 = _RAND_323[21:0];
|
|
_RAND_324 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_66 = _RAND_324[21:0];
|
|
_RAND_325 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_67 = _RAND_325[21:0];
|
|
_RAND_326 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_68 = _RAND_326[21:0];
|
|
_RAND_327 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_69 = _RAND_327[21:0];
|
|
_RAND_328 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_70 = _RAND_328[21:0];
|
|
_RAND_329 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_71 = _RAND_329[21:0];
|
|
_RAND_330 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_72 = _RAND_330[21:0];
|
|
_RAND_331 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_73 = _RAND_331[21:0];
|
|
_RAND_332 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_74 = _RAND_332[21:0];
|
|
_RAND_333 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_75 = _RAND_333[21:0];
|
|
_RAND_334 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_76 = _RAND_334[21:0];
|
|
_RAND_335 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_77 = _RAND_335[21:0];
|
|
_RAND_336 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_78 = _RAND_336[21:0];
|
|
_RAND_337 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_79 = _RAND_337[21:0];
|
|
_RAND_338 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_80 = _RAND_338[21:0];
|
|
_RAND_339 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_81 = _RAND_339[21:0];
|
|
_RAND_340 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_82 = _RAND_340[21:0];
|
|
_RAND_341 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_83 = _RAND_341[21:0];
|
|
_RAND_342 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_84 = _RAND_342[21:0];
|
|
_RAND_343 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_85 = _RAND_343[21:0];
|
|
_RAND_344 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_86 = _RAND_344[21:0];
|
|
_RAND_345 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_87 = _RAND_345[21:0];
|
|
_RAND_346 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_88 = _RAND_346[21:0];
|
|
_RAND_347 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_89 = _RAND_347[21:0];
|
|
_RAND_348 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_90 = _RAND_348[21:0];
|
|
_RAND_349 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_91 = _RAND_349[21:0];
|
|
_RAND_350 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_92 = _RAND_350[21:0];
|
|
_RAND_351 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_93 = _RAND_351[21:0];
|
|
_RAND_352 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_94 = _RAND_352[21:0];
|
|
_RAND_353 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_95 = _RAND_353[21:0];
|
|
_RAND_354 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_96 = _RAND_354[21:0];
|
|
_RAND_355 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_97 = _RAND_355[21:0];
|
|
_RAND_356 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_98 = _RAND_356[21:0];
|
|
_RAND_357 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_99 = _RAND_357[21:0];
|
|
_RAND_358 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_100 = _RAND_358[21:0];
|
|
_RAND_359 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_101 = _RAND_359[21:0];
|
|
_RAND_360 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_102 = _RAND_360[21:0];
|
|
_RAND_361 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_103 = _RAND_361[21:0];
|
|
_RAND_362 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_104 = _RAND_362[21:0];
|
|
_RAND_363 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_105 = _RAND_363[21:0];
|
|
_RAND_364 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_106 = _RAND_364[21:0];
|
|
_RAND_365 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_107 = _RAND_365[21:0];
|
|
_RAND_366 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_108 = _RAND_366[21:0];
|
|
_RAND_367 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_109 = _RAND_367[21:0];
|
|
_RAND_368 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_110 = _RAND_368[21:0];
|
|
_RAND_369 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_111 = _RAND_369[21:0];
|
|
_RAND_370 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_112 = _RAND_370[21:0];
|
|
_RAND_371 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_113 = _RAND_371[21:0];
|
|
_RAND_372 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_114 = _RAND_372[21:0];
|
|
_RAND_373 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_115 = _RAND_373[21:0];
|
|
_RAND_374 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_116 = _RAND_374[21:0];
|
|
_RAND_375 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_117 = _RAND_375[21:0];
|
|
_RAND_376 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_118 = _RAND_376[21:0];
|
|
_RAND_377 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_119 = _RAND_377[21:0];
|
|
_RAND_378 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_120 = _RAND_378[21:0];
|
|
_RAND_379 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_121 = _RAND_379[21:0];
|
|
_RAND_380 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_122 = _RAND_380[21:0];
|
|
_RAND_381 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_123 = _RAND_381[21:0];
|
|
_RAND_382 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_124 = _RAND_382[21:0];
|
|
_RAND_383 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_125 = _RAND_383[21:0];
|
|
_RAND_384 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_126 = _RAND_384[21:0];
|
|
_RAND_385 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_127 = _RAND_385[21:0];
|
|
_RAND_386 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_128 = _RAND_386[21:0];
|
|
_RAND_387 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_129 = _RAND_387[21:0];
|
|
_RAND_388 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_130 = _RAND_388[21:0];
|
|
_RAND_389 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_131 = _RAND_389[21:0];
|
|
_RAND_390 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_132 = _RAND_390[21:0];
|
|
_RAND_391 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_133 = _RAND_391[21:0];
|
|
_RAND_392 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_134 = _RAND_392[21:0];
|
|
_RAND_393 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_135 = _RAND_393[21:0];
|
|
_RAND_394 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_136 = _RAND_394[21:0];
|
|
_RAND_395 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_137 = _RAND_395[21:0];
|
|
_RAND_396 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_138 = _RAND_396[21:0];
|
|
_RAND_397 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_139 = _RAND_397[21:0];
|
|
_RAND_398 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_140 = _RAND_398[21:0];
|
|
_RAND_399 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_141 = _RAND_399[21:0];
|
|
_RAND_400 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_142 = _RAND_400[21:0];
|
|
_RAND_401 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_143 = _RAND_401[21:0];
|
|
_RAND_402 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_144 = _RAND_402[21:0];
|
|
_RAND_403 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_145 = _RAND_403[21:0];
|
|
_RAND_404 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_146 = _RAND_404[21:0];
|
|
_RAND_405 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_147 = _RAND_405[21:0];
|
|
_RAND_406 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_148 = _RAND_406[21:0];
|
|
_RAND_407 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_149 = _RAND_407[21:0];
|
|
_RAND_408 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_150 = _RAND_408[21:0];
|
|
_RAND_409 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_151 = _RAND_409[21:0];
|
|
_RAND_410 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_152 = _RAND_410[21:0];
|
|
_RAND_411 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_153 = _RAND_411[21:0];
|
|
_RAND_412 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_154 = _RAND_412[21:0];
|
|
_RAND_413 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_155 = _RAND_413[21:0];
|
|
_RAND_414 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_156 = _RAND_414[21:0];
|
|
_RAND_415 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_157 = _RAND_415[21:0];
|
|
_RAND_416 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_158 = _RAND_416[21:0];
|
|
_RAND_417 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_159 = _RAND_417[21:0];
|
|
_RAND_418 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_160 = _RAND_418[21:0];
|
|
_RAND_419 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_161 = _RAND_419[21:0];
|
|
_RAND_420 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_162 = _RAND_420[21:0];
|
|
_RAND_421 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_163 = _RAND_421[21:0];
|
|
_RAND_422 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_164 = _RAND_422[21:0];
|
|
_RAND_423 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_165 = _RAND_423[21:0];
|
|
_RAND_424 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_166 = _RAND_424[21:0];
|
|
_RAND_425 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_167 = _RAND_425[21:0];
|
|
_RAND_426 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_168 = _RAND_426[21:0];
|
|
_RAND_427 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_169 = _RAND_427[21:0];
|
|
_RAND_428 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_170 = _RAND_428[21:0];
|
|
_RAND_429 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_171 = _RAND_429[21:0];
|
|
_RAND_430 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_172 = _RAND_430[21:0];
|
|
_RAND_431 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_173 = _RAND_431[21:0];
|
|
_RAND_432 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_174 = _RAND_432[21:0];
|
|
_RAND_433 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_175 = _RAND_433[21:0];
|
|
_RAND_434 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_176 = _RAND_434[21:0];
|
|
_RAND_435 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_177 = _RAND_435[21:0];
|
|
_RAND_436 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_178 = _RAND_436[21:0];
|
|
_RAND_437 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_179 = _RAND_437[21:0];
|
|
_RAND_438 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_180 = _RAND_438[21:0];
|
|
_RAND_439 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_181 = _RAND_439[21:0];
|
|
_RAND_440 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_182 = _RAND_440[21:0];
|
|
_RAND_441 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_183 = _RAND_441[21:0];
|
|
_RAND_442 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_184 = _RAND_442[21:0];
|
|
_RAND_443 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_185 = _RAND_443[21:0];
|
|
_RAND_444 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_186 = _RAND_444[21:0];
|
|
_RAND_445 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_187 = _RAND_445[21:0];
|
|
_RAND_446 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_188 = _RAND_446[21:0];
|
|
_RAND_447 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_189 = _RAND_447[21:0];
|
|
_RAND_448 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_190 = _RAND_448[21:0];
|
|
_RAND_449 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_191 = _RAND_449[21:0];
|
|
_RAND_450 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_192 = _RAND_450[21:0];
|
|
_RAND_451 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_193 = _RAND_451[21:0];
|
|
_RAND_452 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_194 = _RAND_452[21:0];
|
|
_RAND_453 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_195 = _RAND_453[21:0];
|
|
_RAND_454 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_196 = _RAND_454[21:0];
|
|
_RAND_455 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_197 = _RAND_455[21:0];
|
|
_RAND_456 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_198 = _RAND_456[21:0];
|
|
_RAND_457 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_199 = _RAND_457[21:0];
|
|
_RAND_458 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_200 = _RAND_458[21:0];
|
|
_RAND_459 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_201 = _RAND_459[21:0];
|
|
_RAND_460 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_202 = _RAND_460[21:0];
|
|
_RAND_461 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_203 = _RAND_461[21:0];
|
|
_RAND_462 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_204 = _RAND_462[21:0];
|
|
_RAND_463 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_205 = _RAND_463[21:0];
|
|
_RAND_464 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_206 = _RAND_464[21:0];
|
|
_RAND_465 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_207 = _RAND_465[21:0];
|
|
_RAND_466 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_208 = _RAND_466[21:0];
|
|
_RAND_467 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_209 = _RAND_467[21:0];
|
|
_RAND_468 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_210 = _RAND_468[21:0];
|
|
_RAND_469 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_211 = _RAND_469[21:0];
|
|
_RAND_470 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_212 = _RAND_470[21:0];
|
|
_RAND_471 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_213 = _RAND_471[21:0];
|
|
_RAND_472 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_214 = _RAND_472[21:0];
|
|
_RAND_473 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_215 = _RAND_473[21:0];
|
|
_RAND_474 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_216 = _RAND_474[21:0];
|
|
_RAND_475 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_217 = _RAND_475[21:0];
|
|
_RAND_476 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_218 = _RAND_476[21:0];
|
|
_RAND_477 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_219 = _RAND_477[21:0];
|
|
_RAND_478 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_220 = _RAND_478[21:0];
|
|
_RAND_479 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_221 = _RAND_479[21:0];
|
|
_RAND_480 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_222 = _RAND_480[21:0];
|
|
_RAND_481 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_223 = _RAND_481[21:0];
|
|
_RAND_482 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_224 = _RAND_482[21:0];
|
|
_RAND_483 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_225 = _RAND_483[21:0];
|
|
_RAND_484 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_226 = _RAND_484[21:0];
|
|
_RAND_485 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_227 = _RAND_485[21:0];
|
|
_RAND_486 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_228 = _RAND_486[21:0];
|
|
_RAND_487 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_229 = _RAND_487[21:0];
|
|
_RAND_488 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_230 = _RAND_488[21:0];
|
|
_RAND_489 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_231 = _RAND_489[21:0];
|
|
_RAND_490 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_232 = _RAND_490[21:0];
|
|
_RAND_491 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_233 = _RAND_491[21:0];
|
|
_RAND_492 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_234 = _RAND_492[21:0];
|
|
_RAND_493 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_235 = _RAND_493[21:0];
|
|
_RAND_494 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_236 = _RAND_494[21:0];
|
|
_RAND_495 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_237 = _RAND_495[21:0];
|
|
_RAND_496 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_238 = _RAND_496[21:0];
|
|
_RAND_497 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_239 = _RAND_497[21:0];
|
|
_RAND_498 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_240 = _RAND_498[21:0];
|
|
_RAND_499 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_241 = _RAND_499[21:0];
|
|
_RAND_500 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_242 = _RAND_500[21:0];
|
|
_RAND_501 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_243 = _RAND_501[21:0];
|
|
_RAND_502 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_244 = _RAND_502[21:0];
|
|
_RAND_503 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_245 = _RAND_503[21:0];
|
|
_RAND_504 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_246 = _RAND_504[21:0];
|
|
_RAND_505 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_247 = _RAND_505[21:0];
|
|
_RAND_506 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_248 = _RAND_506[21:0];
|
|
_RAND_507 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_249 = _RAND_507[21:0];
|
|
_RAND_508 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_250 = _RAND_508[21:0];
|
|
_RAND_509 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_251 = _RAND_509[21:0];
|
|
_RAND_510 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_252 = _RAND_510[21:0];
|
|
_RAND_511 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_253 = _RAND_511[21:0];
|
|
_RAND_512 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_254 = _RAND_512[21:0];
|
|
_RAND_513 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_255 = _RAND_513[21:0];
|
|
_RAND_514 = {1{`RANDOM}};
|
|
fghr = _RAND_514[7:0];
|
|
_RAND_515 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_0 = _RAND_515[1:0];
|
|
_RAND_516 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_1 = _RAND_516[1:0];
|
|
_RAND_517 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_2 = _RAND_517[1:0];
|
|
_RAND_518 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_3 = _RAND_518[1:0];
|
|
_RAND_519 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_4 = _RAND_519[1:0];
|
|
_RAND_520 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_5 = _RAND_520[1:0];
|
|
_RAND_521 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_6 = _RAND_521[1:0];
|
|
_RAND_522 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_7 = _RAND_522[1:0];
|
|
_RAND_523 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_8 = _RAND_523[1:0];
|
|
_RAND_524 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_9 = _RAND_524[1:0];
|
|
_RAND_525 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_10 = _RAND_525[1:0];
|
|
_RAND_526 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_11 = _RAND_526[1:0];
|
|
_RAND_527 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_12 = _RAND_527[1:0];
|
|
_RAND_528 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_13 = _RAND_528[1:0];
|
|
_RAND_529 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_14 = _RAND_529[1:0];
|
|
_RAND_530 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_15 = _RAND_530[1:0];
|
|
_RAND_531 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_16 = _RAND_531[1:0];
|
|
_RAND_532 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_17 = _RAND_532[1:0];
|
|
_RAND_533 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_18 = _RAND_533[1:0];
|
|
_RAND_534 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_19 = _RAND_534[1:0];
|
|
_RAND_535 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_20 = _RAND_535[1:0];
|
|
_RAND_536 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_21 = _RAND_536[1:0];
|
|
_RAND_537 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_22 = _RAND_537[1:0];
|
|
_RAND_538 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_23 = _RAND_538[1:0];
|
|
_RAND_539 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_24 = _RAND_539[1:0];
|
|
_RAND_540 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_25 = _RAND_540[1:0];
|
|
_RAND_541 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_26 = _RAND_541[1:0];
|
|
_RAND_542 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_27 = _RAND_542[1:0];
|
|
_RAND_543 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_28 = _RAND_543[1:0];
|
|
_RAND_544 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_29 = _RAND_544[1:0];
|
|
_RAND_545 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_30 = _RAND_545[1:0];
|
|
_RAND_546 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_31 = _RAND_546[1:0];
|
|
_RAND_547 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_32 = _RAND_547[1:0];
|
|
_RAND_548 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_33 = _RAND_548[1:0];
|
|
_RAND_549 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_34 = _RAND_549[1:0];
|
|
_RAND_550 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_35 = _RAND_550[1:0];
|
|
_RAND_551 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_36 = _RAND_551[1:0];
|
|
_RAND_552 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_37 = _RAND_552[1:0];
|
|
_RAND_553 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_38 = _RAND_553[1:0];
|
|
_RAND_554 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_39 = _RAND_554[1:0];
|
|
_RAND_555 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_40 = _RAND_555[1:0];
|
|
_RAND_556 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_41 = _RAND_556[1:0];
|
|
_RAND_557 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_42 = _RAND_557[1:0];
|
|
_RAND_558 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_43 = _RAND_558[1:0];
|
|
_RAND_559 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_44 = _RAND_559[1:0];
|
|
_RAND_560 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_45 = _RAND_560[1:0];
|
|
_RAND_561 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_46 = _RAND_561[1:0];
|
|
_RAND_562 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_47 = _RAND_562[1:0];
|
|
_RAND_563 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_48 = _RAND_563[1:0];
|
|
_RAND_564 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_49 = _RAND_564[1:0];
|
|
_RAND_565 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_50 = _RAND_565[1:0];
|
|
_RAND_566 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_51 = _RAND_566[1:0];
|
|
_RAND_567 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_52 = _RAND_567[1:0];
|
|
_RAND_568 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_53 = _RAND_568[1:0];
|
|
_RAND_569 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_54 = _RAND_569[1:0];
|
|
_RAND_570 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_55 = _RAND_570[1:0];
|
|
_RAND_571 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_56 = _RAND_571[1:0];
|
|
_RAND_572 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_57 = _RAND_572[1:0];
|
|
_RAND_573 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_58 = _RAND_573[1:0];
|
|
_RAND_574 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_59 = _RAND_574[1:0];
|
|
_RAND_575 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_60 = _RAND_575[1:0];
|
|
_RAND_576 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_61 = _RAND_576[1:0];
|
|
_RAND_577 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_62 = _RAND_577[1:0];
|
|
_RAND_578 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_63 = _RAND_578[1:0];
|
|
_RAND_579 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_64 = _RAND_579[1:0];
|
|
_RAND_580 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_65 = _RAND_580[1:0];
|
|
_RAND_581 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_66 = _RAND_581[1:0];
|
|
_RAND_582 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_67 = _RAND_582[1:0];
|
|
_RAND_583 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_68 = _RAND_583[1:0];
|
|
_RAND_584 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_69 = _RAND_584[1:0];
|
|
_RAND_585 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_70 = _RAND_585[1:0];
|
|
_RAND_586 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_71 = _RAND_586[1:0];
|
|
_RAND_587 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_72 = _RAND_587[1:0];
|
|
_RAND_588 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_73 = _RAND_588[1:0];
|
|
_RAND_589 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_74 = _RAND_589[1:0];
|
|
_RAND_590 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_75 = _RAND_590[1:0];
|
|
_RAND_591 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_76 = _RAND_591[1:0];
|
|
_RAND_592 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_77 = _RAND_592[1:0];
|
|
_RAND_593 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_78 = _RAND_593[1:0];
|
|
_RAND_594 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_79 = _RAND_594[1:0];
|
|
_RAND_595 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_80 = _RAND_595[1:0];
|
|
_RAND_596 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_81 = _RAND_596[1:0];
|
|
_RAND_597 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_82 = _RAND_597[1:0];
|
|
_RAND_598 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_83 = _RAND_598[1:0];
|
|
_RAND_599 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_84 = _RAND_599[1:0];
|
|
_RAND_600 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_85 = _RAND_600[1:0];
|
|
_RAND_601 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_86 = _RAND_601[1:0];
|
|
_RAND_602 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_87 = _RAND_602[1:0];
|
|
_RAND_603 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_88 = _RAND_603[1:0];
|
|
_RAND_604 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_89 = _RAND_604[1:0];
|
|
_RAND_605 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_90 = _RAND_605[1:0];
|
|
_RAND_606 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_91 = _RAND_606[1:0];
|
|
_RAND_607 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_92 = _RAND_607[1:0];
|
|
_RAND_608 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_93 = _RAND_608[1:0];
|
|
_RAND_609 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_94 = _RAND_609[1:0];
|
|
_RAND_610 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_95 = _RAND_610[1:0];
|
|
_RAND_611 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_96 = _RAND_611[1:0];
|
|
_RAND_612 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_97 = _RAND_612[1:0];
|
|
_RAND_613 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_98 = _RAND_613[1:0];
|
|
_RAND_614 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_99 = _RAND_614[1:0];
|
|
_RAND_615 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_100 = _RAND_615[1:0];
|
|
_RAND_616 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_101 = _RAND_616[1:0];
|
|
_RAND_617 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_102 = _RAND_617[1:0];
|
|
_RAND_618 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_103 = _RAND_618[1:0];
|
|
_RAND_619 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_104 = _RAND_619[1:0];
|
|
_RAND_620 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_105 = _RAND_620[1:0];
|
|
_RAND_621 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_106 = _RAND_621[1:0];
|
|
_RAND_622 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_107 = _RAND_622[1:0];
|
|
_RAND_623 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_108 = _RAND_623[1:0];
|
|
_RAND_624 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_109 = _RAND_624[1:0];
|
|
_RAND_625 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_110 = _RAND_625[1:0];
|
|
_RAND_626 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_111 = _RAND_626[1:0];
|
|
_RAND_627 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_112 = _RAND_627[1:0];
|
|
_RAND_628 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_113 = _RAND_628[1:0];
|
|
_RAND_629 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_114 = _RAND_629[1:0];
|
|
_RAND_630 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_115 = _RAND_630[1:0];
|
|
_RAND_631 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_116 = _RAND_631[1:0];
|
|
_RAND_632 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_117 = _RAND_632[1:0];
|
|
_RAND_633 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_118 = _RAND_633[1:0];
|
|
_RAND_634 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_119 = _RAND_634[1:0];
|
|
_RAND_635 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_120 = _RAND_635[1:0];
|
|
_RAND_636 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_121 = _RAND_636[1:0];
|
|
_RAND_637 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_122 = _RAND_637[1:0];
|
|
_RAND_638 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_123 = _RAND_638[1:0];
|
|
_RAND_639 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_124 = _RAND_639[1:0];
|
|
_RAND_640 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_125 = _RAND_640[1:0];
|
|
_RAND_641 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_126 = _RAND_641[1:0];
|
|
_RAND_642 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_127 = _RAND_642[1:0];
|
|
_RAND_643 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_128 = _RAND_643[1:0];
|
|
_RAND_644 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_129 = _RAND_644[1:0];
|
|
_RAND_645 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_130 = _RAND_645[1:0];
|
|
_RAND_646 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_131 = _RAND_646[1:0];
|
|
_RAND_647 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_132 = _RAND_647[1:0];
|
|
_RAND_648 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_133 = _RAND_648[1:0];
|
|
_RAND_649 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_134 = _RAND_649[1:0];
|
|
_RAND_650 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_135 = _RAND_650[1:0];
|
|
_RAND_651 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_136 = _RAND_651[1:0];
|
|
_RAND_652 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_137 = _RAND_652[1:0];
|
|
_RAND_653 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_138 = _RAND_653[1:0];
|
|
_RAND_654 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_139 = _RAND_654[1:0];
|
|
_RAND_655 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_140 = _RAND_655[1:0];
|
|
_RAND_656 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_141 = _RAND_656[1:0];
|
|
_RAND_657 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_142 = _RAND_657[1:0];
|
|
_RAND_658 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_143 = _RAND_658[1:0];
|
|
_RAND_659 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_144 = _RAND_659[1:0];
|
|
_RAND_660 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_145 = _RAND_660[1:0];
|
|
_RAND_661 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_146 = _RAND_661[1:0];
|
|
_RAND_662 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_147 = _RAND_662[1:0];
|
|
_RAND_663 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_148 = _RAND_663[1:0];
|
|
_RAND_664 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_149 = _RAND_664[1:0];
|
|
_RAND_665 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_150 = _RAND_665[1:0];
|
|
_RAND_666 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_151 = _RAND_666[1:0];
|
|
_RAND_667 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_152 = _RAND_667[1:0];
|
|
_RAND_668 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_153 = _RAND_668[1:0];
|
|
_RAND_669 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_154 = _RAND_669[1:0];
|
|
_RAND_670 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_155 = _RAND_670[1:0];
|
|
_RAND_671 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_156 = _RAND_671[1:0];
|
|
_RAND_672 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_157 = _RAND_672[1:0];
|
|
_RAND_673 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_158 = _RAND_673[1:0];
|
|
_RAND_674 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_159 = _RAND_674[1:0];
|
|
_RAND_675 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_160 = _RAND_675[1:0];
|
|
_RAND_676 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_161 = _RAND_676[1:0];
|
|
_RAND_677 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_162 = _RAND_677[1:0];
|
|
_RAND_678 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_163 = _RAND_678[1:0];
|
|
_RAND_679 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_164 = _RAND_679[1:0];
|
|
_RAND_680 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_165 = _RAND_680[1:0];
|
|
_RAND_681 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_166 = _RAND_681[1:0];
|
|
_RAND_682 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_167 = _RAND_682[1:0];
|
|
_RAND_683 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_168 = _RAND_683[1:0];
|
|
_RAND_684 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_169 = _RAND_684[1:0];
|
|
_RAND_685 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_170 = _RAND_685[1:0];
|
|
_RAND_686 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_171 = _RAND_686[1:0];
|
|
_RAND_687 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_172 = _RAND_687[1:0];
|
|
_RAND_688 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_173 = _RAND_688[1:0];
|
|
_RAND_689 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_174 = _RAND_689[1:0];
|
|
_RAND_690 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_175 = _RAND_690[1:0];
|
|
_RAND_691 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_176 = _RAND_691[1:0];
|
|
_RAND_692 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_177 = _RAND_692[1:0];
|
|
_RAND_693 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_178 = _RAND_693[1:0];
|
|
_RAND_694 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_179 = _RAND_694[1:0];
|
|
_RAND_695 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_180 = _RAND_695[1:0];
|
|
_RAND_696 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_181 = _RAND_696[1:0];
|
|
_RAND_697 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_182 = _RAND_697[1:0];
|
|
_RAND_698 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_183 = _RAND_698[1:0];
|
|
_RAND_699 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_184 = _RAND_699[1:0];
|
|
_RAND_700 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_185 = _RAND_700[1:0];
|
|
_RAND_701 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_186 = _RAND_701[1:0];
|
|
_RAND_702 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_187 = _RAND_702[1:0];
|
|
_RAND_703 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_188 = _RAND_703[1:0];
|
|
_RAND_704 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_189 = _RAND_704[1:0];
|
|
_RAND_705 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_190 = _RAND_705[1:0];
|
|
_RAND_706 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_191 = _RAND_706[1:0];
|
|
_RAND_707 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_192 = _RAND_707[1:0];
|
|
_RAND_708 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_193 = _RAND_708[1:0];
|
|
_RAND_709 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_194 = _RAND_709[1:0];
|
|
_RAND_710 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_195 = _RAND_710[1:0];
|
|
_RAND_711 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_196 = _RAND_711[1:0];
|
|
_RAND_712 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_197 = _RAND_712[1:0];
|
|
_RAND_713 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_198 = _RAND_713[1:0];
|
|
_RAND_714 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_199 = _RAND_714[1:0];
|
|
_RAND_715 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_200 = _RAND_715[1:0];
|
|
_RAND_716 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_201 = _RAND_716[1:0];
|
|
_RAND_717 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_202 = _RAND_717[1:0];
|
|
_RAND_718 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_203 = _RAND_718[1:0];
|
|
_RAND_719 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_204 = _RAND_719[1:0];
|
|
_RAND_720 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_205 = _RAND_720[1:0];
|
|
_RAND_721 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_206 = _RAND_721[1:0];
|
|
_RAND_722 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_207 = _RAND_722[1:0];
|
|
_RAND_723 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_208 = _RAND_723[1:0];
|
|
_RAND_724 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_209 = _RAND_724[1:0];
|
|
_RAND_725 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_210 = _RAND_725[1:0];
|
|
_RAND_726 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_211 = _RAND_726[1:0];
|
|
_RAND_727 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_212 = _RAND_727[1:0];
|
|
_RAND_728 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_213 = _RAND_728[1:0];
|
|
_RAND_729 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_214 = _RAND_729[1:0];
|
|
_RAND_730 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_215 = _RAND_730[1:0];
|
|
_RAND_731 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_216 = _RAND_731[1:0];
|
|
_RAND_732 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_217 = _RAND_732[1:0];
|
|
_RAND_733 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_218 = _RAND_733[1:0];
|
|
_RAND_734 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_219 = _RAND_734[1:0];
|
|
_RAND_735 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_220 = _RAND_735[1:0];
|
|
_RAND_736 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_221 = _RAND_736[1:0];
|
|
_RAND_737 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_222 = _RAND_737[1:0];
|
|
_RAND_738 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_223 = _RAND_738[1:0];
|
|
_RAND_739 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_224 = _RAND_739[1:0];
|
|
_RAND_740 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_225 = _RAND_740[1:0];
|
|
_RAND_741 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_226 = _RAND_741[1:0];
|
|
_RAND_742 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_227 = _RAND_742[1:0];
|
|
_RAND_743 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_228 = _RAND_743[1:0];
|
|
_RAND_744 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_229 = _RAND_744[1:0];
|
|
_RAND_745 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_230 = _RAND_745[1:0];
|
|
_RAND_746 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_231 = _RAND_746[1:0];
|
|
_RAND_747 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_232 = _RAND_747[1:0];
|
|
_RAND_748 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_233 = _RAND_748[1:0];
|
|
_RAND_749 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_234 = _RAND_749[1:0];
|
|
_RAND_750 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_235 = _RAND_750[1:0];
|
|
_RAND_751 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_236 = _RAND_751[1:0];
|
|
_RAND_752 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_237 = _RAND_752[1:0];
|
|
_RAND_753 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_238 = _RAND_753[1:0];
|
|
_RAND_754 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_239 = _RAND_754[1:0];
|
|
_RAND_755 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_240 = _RAND_755[1:0];
|
|
_RAND_756 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_241 = _RAND_756[1:0];
|
|
_RAND_757 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_242 = _RAND_757[1:0];
|
|
_RAND_758 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_243 = _RAND_758[1:0];
|
|
_RAND_759 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_244 = _RAND_759[1:0];
|
|
_RAND_760 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_245 = _RAND_760[1:0];
|
|
_RAND_761 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_246 = _RAND_761[1:0];
|
|
_RAND_762 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_247 = _RAND_762[1:0];
|
|
_RAND_763 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_248 = _RAND_763[1:0];
|
|
_RAND_764 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_249 = _RAND_764[1:0];
|
|
_RAND_765 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_250 = _RAND_765[1:0];
|
|
_RAND_766 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_251 = _RAND_766[1:0];
|
|
_RAND_767 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_252 = _RAND_767[1:0];
|
|
_RAND_768 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_253 = _RAND_768[1:0];
|
|
_RAND_769 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_254 = _RAND_769[1:0];
|
|
_RAND_770 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_255 = _RAND_770[1:0];
|
|
_RAND_771 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_0 = _RAND_771[1:0];
|
|
_RAND_772 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_1 = _RAND_772[1:0];
|
|
_RAND_773 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_2 = _RAND_773[1:0];
|
|
_RAND_774 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_3 = _RAND_774[1:0];
|
|
_RAND_775 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_4 = _RAND_775[1:0];
|
|
_RAND_776 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_5 = _RAND_776[1:0];
|
|
_RAND_777 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_6 = _RAND_777[1:0];
|
|
_RAND_778 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_7 = _RAND_778[1:0];
|
|
_RAND_779 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_8 = _RAND_779[1:0];
|
|
_RAND_780 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_9 = _RAND_780[1:0];
|
|
_RAND_781 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_10 = _RAND_781[1:0];
|
|
_RAND_782 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_11 = _RAND_782[1:0];
|
|
_RAND_783 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_12 = _RAND_783[1:0];
|
|
_RAND_784 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_13 = _RAND_784[1:0];
|
|
_RAND_785 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_14 = _RAND_785[1:0];
|
|
_RAND_786 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_15 = _RAND_786[1:0];
|
|
_RAND_787 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_16 = _RAND_787[1:0];
|
|
_RAND_788 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_17 = _RAND_788[1:0];
|
|
_RAND_789 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_18 = _RAND_789[1:0];
|
|
_RAND_790 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_19 = _RAND_790[1:0];
|
|
_RAND_791 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_20 = _RAND_791[1:0];
|
|
_RAND_792 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_21 = _RAND_792[1:0];
|
|
_RAND_793 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_22 = _RAND_793[1:0];
|
|
_RAND_794 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_23 = _RAND_794[1:0];
|
|
_RAND_795 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_24 = _RAND_795[1:0];
|
|
_RAND_796 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_25 = _RAND_796[1:0];
|
|
_RAND_797 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_26 = _RAND_797[1:0];
|
|
_RAND_798 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_27 = _RAND_798[1:0];
|
|
_RAND_799 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_28 = _RAND_799[1:0];
|
|
_RAND_800 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_29 = _RAND_800[1:0];
|
|
_RAND_801 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_30 = _RAND_801[1:0];
|
|
_RAND_802 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_31 = _RAND_802[1:0];
|
|
_RAND_803 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_32 = _RAND_803[1:0];
|
|
_RAND_804 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_33 = _RAND_804[1:0];
|
|
_RAND_805 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_34 = _RAND_805[1:0];
|
|
_RAND_806 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_35 = _RAND_806[1:0];
|
|
_RAND_807 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_36 = _RAND_807[1:0];
|
|
_RAND_808 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_37 = _RAND_808[1:0];
|
|
_RAND_809 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_38 = _RAND_809[1:0];
|
|
_RAND_810 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_39 = _RAND_810[1:0];
|
|
_RAND_811 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_40 = _RAND_811[1:0];
|
|
_RAND_812 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_41 = _RAND_812[1:0];
|
|
_RAND_813 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_42 = _RAND_813[1:0];
|
|
_RAND_814 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_43 = _RAND_814[1:0];
|
|
_RAND_815 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_44 = _RAND_815[1:0];
|
|
_RAND_816 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_45 = _RAND_816[1:0];
|
|
_RAND_817 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_46 = _RAND_817[1:0];
|
|
_RAND_818 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_47 = _RAND_818[1:0];
|
|
_RAND_819 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_48 = _RAND_819[1:0];
|
|
_RAND_820 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_49 = _RAND_820[1:0];
|
|
_RAND_821 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_50 = _RAND_821[1:0];
|
|
_RAND_822 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_51 = _RAND_822[1:0];
|
|
_RAND_823 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_52 = _RAND_823[1:0];
|
|
_RAND_824 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_53 = _RAND_824[1:0];
|
|
_RAND_825 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_54 = _RAND_825[1:0];
|
|
_RAND_826 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_55 = _RAND_826[1:0];
|
|
_RAND_827 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_56 = _RAND_827[1:0];
|
|
_RAND_828 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_57 = _RAND_828[1:0];
|
|
_RAND_829 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_58 = _RAND_829[1:0];
|
|
_RAND_830 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_59 = _RAND_830[1:0];
|
|
_RAND_831 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_60 = _RAND_831[1:0];
|
|
_RAND_832 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_61 = _RAND_832[1:0];
|
|
_RAND_833 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_62 = _RAND_833[1:0];
|
|
_RAND_834 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_63 = _RAND_834[1:0];
|
|
_RAND_835 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_64 = _RAND_835[1:0];
|
|
_RAND_836 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_65 = _RAND_836[1:0];
|
|
_RAND_837 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_66 = _RAND_837[1:0];
|
|
_RAND_838 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_67 = _RAND_838[1:0];
|
|
_RAND_839 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_68 = _RAND_839[1:0];
|
|
_RAND_840 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_69 = _RAND_840[1:0];
|
|
_RAND_841 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_70 = _RAND_841[1:0];
|
|
_RAND_842 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_71 = _RAND_842[1:0];
|
|
_RAND_843 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_72 = _RAND_843[1:0];
|
|
_RAND_844 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_73 = _RAND_844[1:0];
|
|
_RAND_845 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_74 = _RAND_845[1:0];
|
|
_RAND_846 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_75 = _RAND_846[1:0];
|
|
_RAND_847 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_76 = _RAND_847[1:0];
|
|
_RAND_848 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_77 = _RAND_848[1:0];
|
|
_RAND_849 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_78 = _RAND_849[1:0];
|
|
_RAND_850 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_79 = _RAND_850[1:0];
|
|
_RAND_851 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_80 = _RAND_851[1:0];
|
|
_RAND_852 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_81 = _RAND_852[1:0];
|
|
_RAND_853 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_82 = _RAND_853[1:0];
|
|
_RAND_854 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_83 = _RAND_854[1:0];
|
|
_RAND_855 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_84 = _RAND_855[1:0];
|
|
_RAND_856 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_85 = _RAND_856[1:0];
|
|
_RAND_857 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_86 = _RAND_857[1:0];
|
|
_RAND_858 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_87 = _RAND_858[1:0];
|
|
_RAND_859 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_88 = _RAND_859[1:0];
|
|
_RAND_860 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_89 = _RAND_860[1:0];
|
|
_RAND_861 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_90 = _RAND_861[1:0];
|
|
_RAND_862 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_91 = _RAND_862[1:0];
|
|
_RAND_863 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_92 = _RAND_863[1:0];
|
|
_RAND_864 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_93 = _RAND_864[1:0];
|
|
_RAND_865 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_94 = _RAND_865[1:0];
|
|
_RAND_866 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_95 = _RAND_866[1:0];
|
|
_RAND_867 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_96 = _RAND_867[1:0];
|
|
_RAND_868 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_97 = _RAND_868[1:0];
|
|
_RAND_869 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_98 = _RAND_869[1:0];
|
|
_RAND_870 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_99 = _RAND_870[1:0];
|
|
_RAND_871 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_100 = _RAND_871[1:0];
|
|
_RAND_872 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_101 = _RAND_872[1:0];
|
|
_RAND_873 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_102 = _RAND_873[1:0];
|
|
_RAND_874 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_103 = _RAND_874[1:0];
|
|
_RAND_875 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_104 = _RAND_875[1:0];
|
|
_RAND_876 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_105 = _RAND_876[1:0];
|
|
_RAND_877 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_106 = _RAND_877[1:0];
|
|
_RAND_878 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_107 = _RAND_878[1:0];
|
|
_RAND_879 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_108 = _RAND_879[1:0];
|
|
_RAND_880 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_109 = _RAND_880[1:0];
|
|
_RAND_881 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_110 = _RAND_881[1:0];
|
|
_RAND_882 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_111 = _RAND_882[1:0];
|
|
_RAND_883 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_112 = _RAND_883[1:0];
|
|
_RAND_884 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_113 = _RAND_884[1:0];
|
|
_RAND_885 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_114 = _RAND_885[1:0];
|
|
_RAND_886 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_115 = _RAND_886[1:0];
|
|
_RAND_887 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_116 = _RAND_887[1:0];
|
|
_RAND_888 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_117 = _RAND_888[1:0];
|
|
_RAND_889 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_118 = _RAND_889[1:0];
|
|
_RAND_890 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_119 = _RAND_890[1:0];
|
|
_RAND_891 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_120 = _RAND_891[1:0];
|
|
_RAND_892 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_121 = _RAND_892[1:0];
|
|
_RAND_893 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_122 = _RAND_893[1:0];
|
|
_RAND_894 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_123 = _RAND_894[1:0];
|
|
_RAND_895 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_124 = _RAND_895[1:0];
|
|
_RAND_896 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_125 = _RAND_896[1:0];
|
|
_RAND_897 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_126 = _RAND_897[1:0];
|
|
_RAND_898 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_127 = _RAND_898[1:0];
|
|
_RAND_899 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_128 = _RAND_899[1:0];
|
|
_RAND_900 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_129 = _RAND_900[1:0];
|
|
_RAND_901 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_130 = _RAND_901[1:0];
|
|
_RAND_902 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_131 = _RAND_902[1:0];
|
|
_RAND_903 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_132 = _RAND_903[1:0];
|
|
_RAND_904 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_133 = _RAND_904[1:0];
|
|
_RAND_905 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_134 = _RAND_905[1:0];
|
|
_RAND_906 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_135 = _RAND_906[1:0];
|
|
_RAND_907 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_136 = _RAND_907[1:0];
|
|
_RAND_908 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_137 = _RAND_908[1:0];
|
|
_RAND_909 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_138 = _RAND_909[1:0];
|
|
_RAND_910 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_139 = _RAND_910[1:0];
|
|
_RAND_911 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_140 = _RAND_911[1:0];
|
|
_RAND_912 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_141 = _RAND_912[1:0];
|
|
_RAND_913 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_142 = _RAND_913[1:0];
|
|
_RAND_914 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_143 = _RAND_914[1:0];
|
|
_RAND_915 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_144 = _RAND_915[1:0];
|
|
_RAND_916 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_145 = _RAND_916[1:0];
|
|
_RAND_917 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_146 = _RAND_917[1:0];
|
|
_RAND_918 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_147 = _RAND_918[1:0];
|
|
_RAND_919 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_148 = _RAND_919[1:0];
|
|
_RAND_920 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_149 = _RAND_920[1:0];
|
|
_RAND_921 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_150 = _RAND_921[1:0];
|
|
_RAND_922 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_151 = _RAND_922[1:0];
|
|
_RAND_923 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_152 = _RAND_923[1:0];
|
|
_RAND_924 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_153 = _RAND_924[1:0];
|
|
_RAND_925 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_154 = _RAND_925[1:0];
|
|
_RAND_926 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_155 = _RAND_926[1:0];
|
|
_RAND_927 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_156 = _RAND_927[1:0];
|
|
_RAND_928 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_157 = _RAND_928[1:0];
|
|
_RAND_929 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_158 = _RAND_929[1:0];
|
|
_RAND_930 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_159 = _RAND_930[1:0];
|
|
_RAND_931 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_160 = _RAND_931[1:0];
|
|
_RAND_932 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_161 = _RAND_932[1:0];
|
|
_RAND_933 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_162 = _RAND_933[1:0];
|
|
_RAND_934 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_163 = _RAND_934[1:0];
|
|
_RAND_935 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_164 = _RAND_935[1:0];
|
|
_RAND_936 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_165 = _RAND_936[1:0];
|
|
_RAND_937 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_166 = _RAND_937[1:0];
|
|
_RAND_938 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_167 = _RAND_938[1:0];
|
|
_RAND_939 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_168 = _RAND_939[1:0];
|
|
_RAND_940 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_169 = _RAND_940[1:0];
|
|
_RAND_941 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_170 = _RAND_941[1:0];
|
|
_RAND_942 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_171 = _RAND_942[1:0];
|
|
_RAND_943 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_172 = _RAND_943[1:0];
|
|
_RAND_944 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_173 = _RAND_944[1:0];
|
|
_RAND_945 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_174 = _RAND_945[1:0];
|
|
_RAND_946 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_175 = _RAND_946[1:0];
|
|
_RAND_947 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_176 = _RAND_947[1:0];
|
|
_RAND_948 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_177 = _RAND_948[1:0];
|
|
_RAND_949 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_178 = _RAND_949[1:0];
|
|
_RAND_950 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_179 = _RAND_950[1:0];
|
|
_RAND_951 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_180 = _RAND_951[1:0];
|
|
_RAND_952 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_181 = _RAND_952[1:0];
|
|
_RAND_953 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_182 = _RAND_953[1:0];
|
|
_RAND_954 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_183 = _RAND_954[1:0];
|
|
_RAND_955 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_184 = _RAND_955[1:0];
|
|
_RAND_956 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_185 = _RAND_956[1:0];
|
|
_RAND_957 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_186 = _RAND_957[1:0];
|
|
_RAND_958 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_187 = _RAND_958[1:0];
|
|
_RAND_959 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_188 = _RAND_959[1:0];
|
|
_RAND_960 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_189 = _RAND_960[1:0];
|
|
_RAND_961 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_190 = _RAND_961[1:0];
|
|
_RAND_962 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_191 = _RAND_962[1:0];
|
|
_RAND_963 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_192 = _RAND_963[1:0];
|
|
_RAND_964 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_193 = _RAND_964[1:0];
|
|
_RAND_965 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_194 = _RAND_965[1:0];
|
|
_RAND_966 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_195 = _RAND_966[1:0];
|
|
_RAND_967 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_196 = _RAND_967[1:0];
|
|
_RAND_968 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_197 = _RAND_968[1:0];
|
|
_RAND_969 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_198 = _RAND_969[1:0];
|
|
_RAND_970 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_199 = _RAND_970[1:0];
|
|
_RAND_971 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_200 = _RAND_971[1:0];
|
|
_RAND_972 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_201 = _RAND_972[1:0];
|
|
_RAND_973 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_202 = _RAND_973[1:0];
|
|
_RAND_974 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_203 = _RAND_974[1:0];
|
|
_RAND_975 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_204 = _RAND_975[1:0];
|
|
_RAND_976 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_205 = _RAND_976[1:0];
|
|
_RAND_977 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_206 = _RAND_977[1:0];
|
|
_RAND_978 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_207 = _RAND_978[1:0];
|
|
_RAND_979 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_208 = _RAND_979[1:0];
|
|
_RAND_980 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_209 = _RAND_980[1:0];
|
|
_RAND_981 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_210 = _RAND_981[1:0];
|
|
_RAND_982 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_211 = _RAND_982[1:0];
|
|
_RAND_983 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_212 = _RAND_983[1:0];
|
|
_RAND_984 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_213 = _RAND_984[1:0];
|
|
_RAND_985 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_214 = _RAND_985[1:0];
|
|
_RAND_986 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_215 = _RAND_986[1:0];
|
|
_RAND_987 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_216 = _RAND_987[1:0];
|
|
_RAND_988 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_217 = _RAND_988[1:0];
|
|
_RAND_989 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_218 = _RAND_989[1:0];
|
|
_RAND_990 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_219 = _RAND_990[1:0];
|
|
_RAND_991 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_220 = _RAND_991[1:0];
|
|
_RAND_992 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_221 = _RAND_992[1:0];
|
|
_RAND_993 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_222 = _RAND_993[1:0];
|
|
_RAND_994 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_223 = _RAND_994[1:0];
|
|
_RAND_995 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_224 = _RAND_995[1:0];
|
|
_RAND_996 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_225 = _RAND_996[1:0];
|
|
_RAND_997 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_226 = _RAND_997[1:0];
|
|
_RAND_998 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_227 = _RAND_998[1:0];
|
|
_RAND_999 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_228 = _RAND_999[1:0];
|
|
_RAND_1000 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_229 = _RAND_1000[1:0];
|
|
_RAND_1001 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_230 = _RAND_1001[1:0];
|
|
_RAND_1002 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_231 = _RAND_1002[1:0];
|
|
_RAND_1003 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_232 = _RAND_1003[1:0];
|
|
_RAND_1004 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_233 = _RAND_1004[1:0];
|
|
_RAND_1005 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_234 = _RAND_1005[1:0];
|
|
_RAND_1006 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_235 = _RAND_1006[1:0];
|
|
_RAND_1007 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_236 = _RAND_1007[1:0];
|
|
_RAND_1008 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_237 = _RAND_1008[1:0];
|
|
_RAND_1009 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_238 = _RAND_1009[1:0];
|
|
_RAND_1010 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_239 = _RAND_1010[1:0];
|
|
_RAND_1011 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_240 = _RAND_1011[1:0];
|
|
_RAND_1012 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_241 = _RAND_1012[1:0];
|
|
_RAND_1013 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_242 = _RAND_1013[1:0];
|
|
_RAND_1014 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_243 = _RAND_1014[1:0];
|
|
_RAND_1015 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_244 = _RAND_1015[1:0];
|
|
_RAND_1016 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_245 = _RAND_1016[1:0];
|
|
_RAND_1017 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_246 = _RAND_1017[1:0];
|
|
_RAND_1018 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_247 = _RAND_1018[1:0];
|
|
_RAND_1019 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_248 = _RAND_1019[1:0];
|
|
_RAND_1020 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_249 = _RAND_1020[1:0];
|
|
_RAND_1021 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_250 = _RAND_1021[1:0];
|
|
_RAND_1022 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_251 = _RAND_1022[1:0];
|
|
_RAND_1023 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_252 = _RAND_1023[1:0];
|
|
_RAND_1024 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_253 = _RAND_1024[1:0];
|
|
_RAND_1025 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_254 = _RAND_1025[1:0];
|
|
_RAND_1026 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_255 = _RAND_1026[1:0];
|
|
_RAND_1027 = {1{`RANDOM}};
|
|
exu_mp_way_f = _RAND_1027[0:0];
|
|
_RAND_1028 = {1{`RANDOM}};
|
|
exu_flush_final_d1 = _RAND_1028[0:0];
|
|
_RAND_1029 = {8{`RANDOM}};
|
|
btb_lru_b0_f = _RAND_1029[255:0];
|
|
_RAND_1030 = {1{`RANDOM}};
|
|
ifc_fetch_adder_prior = _RAND_1030[29:0];
|
|
_RAND_1031 = {1{`RANDOM}};
|
|
rets_out_0 = _RAND_1031[31:0];
|
|
_RAND_1032 = {1{`RANDOM}};
|
|
rets_out_1 = _RAND_1032[31:0];
|
|
_RAND_1033 = {1{`RANDOM}};
|
|
rets_out_2 = _RAND_1033[31:0];
|
|
_RAND_1034 = {1{`RANDOM}};
|
|
rets_out_3 = _RAND_1034[31:0];
|
|
_RAND_1035 = {1{`RANDOM}};
|
|
rets_out_4 = _RAND_1035[31:0];
|
|
_RAND_1036 = {1{`RANDOM}};
|
|
rets_out_5 = _RAND_1036[31:0];
|
|
_RAND_1037 = {1{`RANDOM}};
|
|
rets_out_6 = _RAND_1037[31:0];
|
|
_RAND_1038 = {1{`RANDOM}};
|
|
rets_out_7 = _RAND_1038[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
leak_one_f_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_0 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_1 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_2 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_3 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_4 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_5 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_6 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_7 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_8 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_9 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_10 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_11 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_12 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_13 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_14 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_15 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_16 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_17 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_18 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_19 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_20 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_21 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_22 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_23 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_24 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_25 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_26 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_27 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_28 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_29 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_30 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_31 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_32 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_33 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_34 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_35 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_36 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_37 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_38 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_39 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_40 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_41 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_42 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_43 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_44 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_45 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_46 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_47 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_48 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_49 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_50 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_51 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_52 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_53 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_54 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_55 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_56 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_57 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_58 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_59 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_60 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_61 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_62 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_63 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_64 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_65 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_66 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_67 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_68 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_69 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_70 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_71 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_72 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_73 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_74 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_75 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_76 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_77 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_78 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_79 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_80 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_81 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_82 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_83 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_84 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_85 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_86 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_87 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_88 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_89 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_90 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_91 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_92 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_93 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_94 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_95 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_96 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_97 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_98 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_99 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_100 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_101 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_102 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_103 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_104 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_105 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_106 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_107 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_108 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_109 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_110 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_111 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_112 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_113 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_114 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_115 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_116 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_117 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_118 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_119 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_120 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_121 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_122 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_123 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_124 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_125 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_126 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_127 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_128 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_129 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_130 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_131 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_132 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_133 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_134 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_135 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_136 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_137 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_138 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_139 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_140 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_141 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_142 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_143 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_144 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_145 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_146 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_147 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_148 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_149 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_150 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_151 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_152 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_153 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_154 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_155 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_156 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_157 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_158 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_159 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_160 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_161 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_162 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_163 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_164 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_165 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_166 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_167 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_168 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_169 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_170 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_171 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_172 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_173 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_174 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_175 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_176 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_177 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_178 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_179 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_180 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_181 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_182 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_183 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_184 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_185 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_186 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_187 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_188 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_189 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_190 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_191 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_192 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_193 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_194 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_195 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_196 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_197 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_198 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_199 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_200 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_201 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_202 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_203 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_204 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_205 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_206 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_207 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_208 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_209 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_210 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_211 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_212 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_213 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_214 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_215 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_216 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_217 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_218 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_219 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_220 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_221 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_222 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_223 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_224 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_225 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_226 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_227 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_228 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_229 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_230 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_231 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_232 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_233 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_234 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_235 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_236 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_237 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_238 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_239 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_240 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_241 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_242 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_243 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_244 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_245 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_246 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_247 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_248 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_249 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_250 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_251 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_252 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_253 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_254 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_255 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_tlu_way_wb_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_0 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_1 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_2 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_3 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_4 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_5 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_6 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_7 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_8 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_9 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_10 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_11 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_12 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_13 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_14 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_15 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_16 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_17 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_18 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_19 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_20 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_21 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_22 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_23 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_24 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_25 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_26 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_27 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_28 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_29 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_30 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_31 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_32 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_33 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_34 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_35 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_36 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_37 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_38 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_39 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_40 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_41 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_42 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_43 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_44 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_45 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_46 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_47 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_48 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_49 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_50 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_51 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_52 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_53 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_54 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_55 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_56 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_57 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_58 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_59 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_60 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_61 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_62 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_63 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_64 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_65 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_66 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_67 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_68 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_69 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_70 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_71 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_72 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_73 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_74 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_75 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_76 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_77 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_78 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_79 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_80 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_81 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_82 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_83 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_84 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_85 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_86 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_87 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_88 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_89 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_90 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_91 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_92 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_93 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_94 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_95 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_96 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_97 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_98 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_99 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_100 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_101 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_102 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_103 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_104 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_105 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_106 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_107 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_108 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_109 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_110 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_111 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_112 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_113 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_114 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_115 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_116 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_117 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_118 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_119 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_120 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_121 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_122 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_123 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_124 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_125 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_126 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_127 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_128 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_129 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_130 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_131 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_132 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_133 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_134 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_135 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_136 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_137 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_138 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_139 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_140 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_141 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_142 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_143 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_144 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_145 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_146 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_147 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_148 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_149 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_150 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_151 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_152 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_153 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_154 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_155 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_156 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_157 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_158 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_159 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_160 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_161 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_162 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_163 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_164 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_165 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_166 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_167 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_168 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_169 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_170 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_171 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_172 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_173 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_174 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_175 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_176 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_177 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_178 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_179 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_180 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_181 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_182 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_183 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_184 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_185 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_186 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_187 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_188 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_189 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_190 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_191 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_192 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_193 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_194 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_195 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_196 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_197 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_198 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_199 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_200 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_201 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_202 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_203 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_204 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_205 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_206 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_207 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_208 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_209 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_210 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_211 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_212 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_213 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_214 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_215 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_216 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_217 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_218 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_219 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_220 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_221 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_222 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_223 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_224 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_225 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_226 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_227 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_228 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_229 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_230 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_231 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_232 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_233 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_234 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_235 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_236 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_237 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_238 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_239 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_240 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_241 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_242 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_243 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_244 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_245 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_246 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_247 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_248 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_249 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_250 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_251 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_252 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_253 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_254 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_255 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
fghr = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_4 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_5 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_6 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_7 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_8 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_9 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_10 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_11 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_12 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_13 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_14 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_15 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_16 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_17 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_18 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_19 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_20 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_21 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_22 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_23 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_24 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_25 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_26 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_27 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_28 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_29 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_30 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_31 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_32 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_33 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_34 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_35 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_36 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_37 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_38 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_39 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_40 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_41 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_42 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_43 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_44 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_45 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_46 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_47 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_48 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_49 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_50 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_51 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_52 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_53 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_54 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_55 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_56 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_57 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_58 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_59 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_60 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_61 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_62 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_63 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_64 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_65 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_66 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_67 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_68 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_69 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_70 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_71 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_72 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_73 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_74 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_75 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_76 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_77 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_78 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_79 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_80 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_81 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_82 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_83 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_84 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_85 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_86 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_87 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_88 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_89 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_90 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_91 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_92 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_93 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_94 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_95 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_96 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_97 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_98 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_99 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_100 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_101 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_102 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_103 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_104 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_105 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_106 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_107 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_108 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_109 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_110 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_111 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_112 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_113 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_114 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_115 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_116 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_117 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_118 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_119 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_120 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_121 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_122 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_123 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_124 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_125 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_126 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_127 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_128 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_129 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_130 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_131 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_132 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_133 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_134 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_135 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_136 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_137 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_138 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_139 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_140 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_141 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_142 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_143 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_144 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_145 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_146 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_147 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_148 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_149 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_150 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_151 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_152 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_153 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_154 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_155 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_156 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_157 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_158 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_159 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_160 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_161 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_162 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_163 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_164 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_165 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_166 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_167 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_168 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_169 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_170 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_171 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_172 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_173 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_174 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_175 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_176 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_177 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_178 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_179 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_180 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_181 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_182 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_183 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_184 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_185 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_186 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_187 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_188 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_189 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_190 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_191 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_192 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_193 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_194 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_195 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_196 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_197 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_198 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_199 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_200 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_201 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_202 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_203 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_204 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_205 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_206 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_207 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_208 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_209 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_210 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_211 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_212 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_213 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_214 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_215 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_216 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_217 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_218 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_219 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_220 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_221 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_222 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_223 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_224 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_225 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_226 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_227 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_228 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_229 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_230 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_231 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_232 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_233 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_234 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_235 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_236 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_237 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_238 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_239 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_240 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_241 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_242 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_243 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_244 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_245 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_246 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_247 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_248 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_249 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_250 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_251 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_252 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_253 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_254 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_255 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_4 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_5 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_6 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_7 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_8 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_9 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_10 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_11 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_12 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_13 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_14 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_15 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_16 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_17 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_18 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_19 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_20 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_21 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_22 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_23 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_24 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_25 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_26 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_27 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_28 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_29 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_30 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_31 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_32 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_33 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_34 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_35 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_36 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_37 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_38 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_39 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_40 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_41 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_42 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_43 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_44 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_45 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_46 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_47 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_48 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_49 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_50 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_51 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_52 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_53 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_54 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_55 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_56 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_57 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_58 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_59 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_60 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_61 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_62 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_63 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_64 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_65 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_66 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_67 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_68 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_69 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_70 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_71 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_72 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_73 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_74 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_75 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_76 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_77 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_78 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_79 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_80 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_81 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_82 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_83 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_84 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_85 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_86 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_87 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_88 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_89 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_90 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_91 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_92 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_93 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_94 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_95 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_96 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_97 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_98 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_99 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_100 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_101 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_102 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_103 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_104 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_105 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_106 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_107 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_108 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_109 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_110 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_111 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_112 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_113 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_114 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_115 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_116 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_117 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_118 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_119 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_120 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_121 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_122 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_123 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_124 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_125 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_126 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_127 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_128 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_129 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_130 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_131 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_132 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_133 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_134 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_135 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_136 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_137 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_138 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_139 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_140 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_141 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_142 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_143 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_144 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_145 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_146 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_147 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_148 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_149 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_150 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_151 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_152 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_153 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_154 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_155 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_156 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_157 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_158 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_159 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_160 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_161 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_162 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_163 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_164 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_165 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_166 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_167 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_168 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_169 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_170 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_171 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_172 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_173 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_174 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_175 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_176 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_177 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_178 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_179 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_180 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_181 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_182 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_183 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_184 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_185 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_186 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_187 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_188 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_189 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_190 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_191 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_192 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_193 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_194 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_195 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_196 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_197 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_198 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_199 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_200 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_201 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_202 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_203 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_204 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_205 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_206 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_207 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_208 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_209 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_210 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_211 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_212 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_213 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_214 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_215 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_216 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_217 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_218 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_219 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_220 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_221 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_222 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_223 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_224 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_225 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_226 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_227 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_228 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_229 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_230 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_231 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_232 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_233 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_234 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_235 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_236 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_237 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_238 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_239 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_240 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_241 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_242 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_243 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_244 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_245 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_246 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_247 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_248 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_249 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_250 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_251 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_252 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_253 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_254 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_255 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
exu_mp_way_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
exu_flush_final_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_lru_b0_f = 256'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_fetch_adder_prior = 30'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_4 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_5 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_6 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_7 = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
leak_one_f_d1 <= 1'h0;
|
|
end else begin
|
|
leak_one_f_d1 <= _T_40 | _T_41;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_0 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_0 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_1 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_1 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_2 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_2 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_3 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_3 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_4 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_4 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_5 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_5 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_6 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_6 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_7 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_7 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_8 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_8 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_9 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_9 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_10 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_10 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_11 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_11 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_12 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_12 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_13 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_13 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_14 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_14 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_15 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_15 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_16 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_16 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_17 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_17 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_18 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_18 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_19 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_19 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_20 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_20 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_21 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_21 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_32_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_22 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_22 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_33_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_23 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_23 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_24 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_24 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_35_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_25 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_25 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_36_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_26 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_26 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_37_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_27 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_27 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_38_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_28 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_28 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_39_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_29 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_29 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_40_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_30 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_30 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_41_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_31 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_31 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_42_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_32 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_32 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_43_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_33 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_33 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_44_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_34 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_34 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_45_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_35 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_35 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_46_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_36 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_36 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_47_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_37 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_37 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_48_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_38 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_38 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_49_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_39 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_39 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_50_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_40 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_40 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_51_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_41 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_41 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_52_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_42 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_42 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_53_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_43 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_43 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_54_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_44 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_44 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_55_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_45 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_45 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_56_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_46 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_46 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_57_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_47 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_47 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_58_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_48 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_48 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_59_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_49 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_49 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_60_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_50 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_50 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_61_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_51 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_51 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_62_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_52 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_52 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_63_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_53 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_53 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_64_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_54 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_54 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_65_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_55 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_55 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_66_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_56 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_56 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_67_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_57 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_57 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_58 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_58 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_69_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_59 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_59 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_60 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_60 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_61 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_61 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_62 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_62 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_63 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_63 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_64 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_64 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_65 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_65 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_66 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_66 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_67 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_67 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_68 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_68 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_69 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_69 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_70 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_70 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_71 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_71 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_72 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_72 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_73 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_73 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_74 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_74 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_75 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_75 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_76 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_76 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_77 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_77 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_78 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_78 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_79 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_79 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_80 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_80 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_81 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_81 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_82 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_82 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_83 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_83 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_94_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_84 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_84 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_95_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_85 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_85 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_96_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_86 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_86 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_97_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_87 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_87 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_98_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_88 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_88 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_99_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_89 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_89 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_100_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_90 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_90 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_101_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_91 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_91 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_102_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_92 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_92 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_103_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_93 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_93 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_104_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_94 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_94 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_105_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_95 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_95 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_106_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_96 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_96 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_107_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_97 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_97 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_108_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_98 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_98 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_109_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_99 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_99 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_110_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_100 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_100 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_111_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_101 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_101 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_112_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_102 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_102 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_113_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_103 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_103 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_114_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_104 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_104 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_115_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_105 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_105 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_116_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_106 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_106 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_117_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_107 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_107 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_118_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_108 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_108 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_119_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_109 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_109 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_120_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_110 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_110 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_121_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_111 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_111 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_122_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_112 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_112 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_123_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_113 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_113 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_124_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_114 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_114 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_125_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_115 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_115 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_126_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_116 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_116 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_127_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_117 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_117 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_128_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_118 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_118 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_129_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_119 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_119 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_130_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_120 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_120 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_131_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_121 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_121 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_132_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_122 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_122 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_133_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_123 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_123 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_134_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_124 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_124 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_135_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_125 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_125 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_136_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_126 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_126 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_137_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_127 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_127 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_138_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_128 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_128 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_139_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_129 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_129 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_140_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_130 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_130 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_141_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_131 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_131 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_142_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_132 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_132 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_143_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_133 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_133 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_144_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_134 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_134 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_145_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_135 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_135 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_146_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_136 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_136 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_147_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_137 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_137 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_148_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_138 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_138 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_149_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_139 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_139 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_150_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_140 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_140 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_151_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_141 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_141 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_152_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_142 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_142 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_153_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_143 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_143 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_154_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_144 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_144 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_155_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_145 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_145 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_156_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_146 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_146 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_157_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_147 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_147 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_158_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_148 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_148 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_159_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_149 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_149 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_160_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_150 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_150 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_161_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_151 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_151 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_162_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_152 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_152 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_163_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_153 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_153 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_164_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_154 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_154 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_165_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_155 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_155 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_166_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_156 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_156 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_167_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_157 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_157 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_168_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_158 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_158 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_169_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_159 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_159 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_170_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_160 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_160 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_171_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_161 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_161 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_172_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_162 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_162 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_173_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_163 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_163 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_174_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_164 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_164 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_175_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_165 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_165 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_176_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_166 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_166 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_177_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_167 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_167 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_178_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_168 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_168 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_179_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_169 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_169 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_180_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_170 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_170 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_181_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_171 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_171 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_182_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_172 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_172 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_183_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_173 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_173 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_184_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_174 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_174 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_185_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_175 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_175 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_186_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_176 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_176 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_187_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_177 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_177 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_188_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_178 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_178 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_189_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_179 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_179 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_190_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_180 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_180 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_191_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_181 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_181 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_192_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_182 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_182 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_193_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_183 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_183 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_194_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_184 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_184 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_195_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_185 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_185 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_196_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_186 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_186 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_197_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_187 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_187 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_198_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_188 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_188 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_199_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_189 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_189 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_200_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_190 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_190 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_201_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_191 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_191 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_202_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_192 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_192 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_203_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_193 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_193 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_204_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_194 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_194 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_205_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_195 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_195 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_206_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_196 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_196 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_207_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_197 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_197 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_208_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_198 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_198 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_209_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_199 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_199 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_210_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_200 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_200 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_211_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_201 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_201 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_212_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_202 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_202 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_213_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_203 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_203 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_214_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_204 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_204 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_215_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_205 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_205 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_216_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_206 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_206 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_217_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_207 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_207 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_218_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_208 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_208 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_219_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_209 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_209 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_220_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_210 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_210 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_221_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_211 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_211 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_222_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_212 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_212 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_223_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_213 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_213 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_224_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_214 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_214 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_225_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_215 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_215 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_226_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_216 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_216 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_227_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_217 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_217 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_228_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_218 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_218 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_229_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_219 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_219 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_230_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_220 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_220 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_231_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_221 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_221 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_232_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_222 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_222 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_233_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_223 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_223 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_234_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_224 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_224 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_235_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_225 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_225 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_236_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_226 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_226 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_237_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_227 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_227 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_238_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_228 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_228 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_239_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_229 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_229 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_240_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_230 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_230 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_241_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_231 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_231 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_242_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_232 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_232 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_243_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_233 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_233 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_244_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_234 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_234 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_245_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_235 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_235 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_246_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_236 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_236 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_247_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_237 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_237 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_248_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_238 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_238 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_249_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_239 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_239 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_250_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_240 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_240 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_251_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_241 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_241 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_252_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_242 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_242 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_253_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_243 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_243 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_254_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_244 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_244 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_255_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_245 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_245 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_256_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_246 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_246 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_257_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_247 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_247 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_258_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_248 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_248 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_259_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_249 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_249 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_260_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_250 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_250 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_261_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_251 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_251 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_262_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_252 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_252 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_263_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_253 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_253 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_264_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_254 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_254 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_265_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_255 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way0_out_255 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dec_tlu_way_wb_f <= 1'h0;
|
|
end else begin
|
|
dec_tlu_way_wb_f <= io_dec_tlu_br0_r_pkt_way;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_266_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_0 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_0 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_267_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_1 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_1 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_268_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_2 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_2 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_269_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_3 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_3 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_270_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_4 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_4 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_271_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_5 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_5 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_272_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_6 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_6 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_273_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_7 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_7 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_274_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_8 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_8 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_275_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_9 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_9 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_276_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_10 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_10 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_277_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_11 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_11 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_278_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_12 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_12 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_279_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_13 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_13 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_280_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_14 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_14 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_281_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_15 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_15 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_282_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_16 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_16 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_283_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_17 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_17 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_284_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_18 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_18 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_285_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_19 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_19 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_286_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_20 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_20 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_287_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_21 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_21 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_288_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_22 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_22 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_289_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_23 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_23 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_290_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_24 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_24 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_291_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_25 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_25 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_292_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_26 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_26 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_293_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_27 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_27 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_294_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_28 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_28 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_295_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_29 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_29 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_296_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_30 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_30 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_297_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_31 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_31 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_298_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_32 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_32 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_299_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_33 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_33 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_300_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_34 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_34 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_301_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_35 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_35 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_302_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_36 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_36 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_303_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_37 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_37 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_304_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_38 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_38 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_305_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_39 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_39 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_306_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_40 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_40 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_307_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_41 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_41 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_308_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_42 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_42 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_309_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_43 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_43 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_310_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_44 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_44 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_311_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_45 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_45 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_312_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_46 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_46 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_313_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_47 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_47 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_314_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_48 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_48 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_315_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_49 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_49 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_316_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_50 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_50 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_317_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_51 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_51 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_318_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_52 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_52 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_319_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_53 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_53 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_320_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_54 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_54 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_321_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_55 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_55 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_322_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_56 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_56 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_323_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_57 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_57 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_324_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_58 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_58 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_325_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_59 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_59 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_326_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_60 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_60 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_327_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_61 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_61 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_328_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_62 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_62 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_329_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_63 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_63 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_330_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_64 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_64 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_331_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_65 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_65 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_332_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_66 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_66 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_333_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_67 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_67 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_334_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_68 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_68 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_335_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_69 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_69 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_336_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_70 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_70 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_337_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_71 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_71 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_338_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_72 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_72 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_339_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_73 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_73 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_340_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_74 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_74 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_341_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_75 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_75 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_342_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_76 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_76 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_343_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_77 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_77 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_344_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_78 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_78 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_345_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_79 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_79 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_346_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_80 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_80 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_347_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_81 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_81 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_348_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_82 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_82 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_349_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_83 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_83 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_350_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_84 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_84 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_351_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_85 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_85 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_352_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_86 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_86 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_353_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_87 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_87 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_354_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_88 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_88 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_355_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_89 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_89 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_356_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_90 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_90 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_357_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_91 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_91 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_358_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_92 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_92 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_359_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_93 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_93 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_360_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_94 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_94 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_361_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_95 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_95 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_362_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_96 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_96 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_363_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_97 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_97 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_364_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_98 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_98 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_365_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_99 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_99 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_366_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_100 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_100 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_367_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_101 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_101 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_368_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_102 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_102 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_369_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_103 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_103 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_370_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_104 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_104 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_371_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_105 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_105 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_372_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_106 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_106 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_373_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_107 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_107 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_374_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_108 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_108 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_375_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_109 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_109 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_376_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_110 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_110 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_377_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_111 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_111 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_378_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_112 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_112 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_379_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_113 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_113 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_380_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_114 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_114 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_381_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_115 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_115 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_382_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_116 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_116 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_383_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_117 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_117 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_384_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_118 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_118 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_385_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_119 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_119 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_386_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_120 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_120 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_387_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_121 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_121 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_388_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_122 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_122 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_389_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_123 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_123 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_390_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_124 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_124 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_391_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_125 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_125 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_392_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_126 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_126 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_393_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_127 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_127 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_394_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_128 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_128 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_395_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_129 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_129 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_396_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_130 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_130 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_397_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_131 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_131 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_398_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_132 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_132 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_399_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_133 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_133 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_400_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_134 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_134 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_401_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_135 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_135 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_402_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_136 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_136 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_403_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_137 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_137 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_404_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_138 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_138 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_405_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_139 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_139 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_406_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_140 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_140 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_407_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_141 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_141 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_408_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_142 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_142 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_409_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_143 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_143 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_410_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_144 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_144 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_411_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_145 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_145 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_412_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_146 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_146 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_413_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_147 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_147 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_414_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_148 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_148 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_415_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_149 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_149 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_416_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_150 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_150 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_417_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_151 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_151 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_418_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_152 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_152 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_419_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_153 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_153 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_420_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_154 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_154 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_421_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_155 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_155 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_422_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_156 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_156 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_423_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_157 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_157 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_424_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_158 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_158 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_425_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_159 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_159 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_426_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_160 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_160 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_427_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_161 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_161 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_428_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_162 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_162 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_429_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_163 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_163 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_430_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_164 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_164 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_431_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_165 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_165 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_432_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_166 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_166 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_433_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_167 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_167 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_434_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_168 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_168 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_435_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_169 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_169 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_436_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_170 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_170 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_437_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_171 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_171 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_438_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_172 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_172 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_439_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_173 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_173 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_440_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_174 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_174 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_441_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_175 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_175 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_442_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_176 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_176 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_443_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_177 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_177 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_444_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_178 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_178 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_445_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_179 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_179 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_446_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_180 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_180 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_447_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_181 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_181 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_448_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_182 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_182 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_449_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_183 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_183 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_450_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_184 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_184 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_451_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_185 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_185 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_452_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_186 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_186 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_453_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_187 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_187 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_454_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_188 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_188 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_455_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_189 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_189 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_456_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_190 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_190 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_457_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_191 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_191 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_458_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_192 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_192 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_459_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_193 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_193 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_460_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_194 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_194 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_461_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_195 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_195 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_462_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_196 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_196 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_463_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_197 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_197 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_464_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_198 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_198 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_465_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_199 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_199 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_466_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_200 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_200 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_467_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_201 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_201 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_468_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_202 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_202 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_469_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_203 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_203 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_470_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_204 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_204 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_471_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_205 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_205 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_472_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_206 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_206 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_473_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_207 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_207 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_474_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_208 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_208 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_475_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_209 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_209 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_476_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_210 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_210 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_477_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_211 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_211 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_478_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_212 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_212 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_479_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_213 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_213 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_480_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_214 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_214 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_481_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_215 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_215 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_482_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_216 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_216 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_483_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_217 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_217 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_484_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_218 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_218 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_485_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_219 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_219 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_486_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_220 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_220 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_487_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_221 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_221 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_488_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_222 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_222 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_489_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_223 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_223 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_490_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_224 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_224 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_491_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_225 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_225 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_492_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_226 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_226 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_493_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_227 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_227 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_494_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_228 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_228 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_495_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_229 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_229 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_496_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_230 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_230 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_497_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_231 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_231 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_498_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_232 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_232 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_499_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_233 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_233 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_500_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_234 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_234 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_501_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_235 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_235 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_502_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_236 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_236 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_503_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_237 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_237 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_504_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_238 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_238 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_505_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_239 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_239 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_506_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_240 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_240 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_507_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_241 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_241 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_508_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_242 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_242 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_509_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_243 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_243 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_510_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_244 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_244 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_511_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_245 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_245 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_512_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_246 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_246 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_513_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_247 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_247 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_514_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_248 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_248 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_515_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_249 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_249 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_516_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_250 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_250 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_517_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_251 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_251 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_518_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_252 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_252 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_519_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_253 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_253 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_520_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_254 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_254 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_521_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_255 <= 22'h0;
|
|
end else begin
|
|
btb_bank0_rd_data_way1_out_255 <= {_T_537,_T_534};
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fghr <= 8'h0;
|
|
end else begin
|
|
fghr <= _T_338 | _T_337;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_0 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_0) begin
|
|
if (_T_8869) begin
|
|
bht_bank_rd_data_out_1_0 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_0 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_1 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_1) begin
|
|
if (_T_8878) begin
|
|
bht_bank_rd_data_out_1_1 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_1 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_2 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_2) begin
|
|
if (_T_8887) begin
|
|
bht_bank_rd_data_out_1_2 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_2 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_3 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_3) begin
|
|
if (_T_8896) begin
|
|
bht_bank_rd_data_out_1_3 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_3 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_4 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_4) begin
|
|
if (_T_8905) begin
|
|
bht_bank_rd_data_out_1_4 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_4 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_5 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_5) begin
|
|
if (_T_8914) begin
|
|
bht_bank_rd_data_out_1_5 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_5 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_6 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_6) begin
|
|
if (_T_8923) begin
|
|
bht_bank_rd_data_out_1_6 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_6 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_7 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_7) begin
|
|
if (_T_8932) begin
|
|
bht_bank_rd_data_out_1_7 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_7 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_8 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_8) begin
|
|
if (_T_8941) begin
|
|
bht_bank_rd_data_out_1_8 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_8 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_9 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_9) begin
|
|
if (_T_8950) begin
|
|
bht_bank_rd_data_out_1_9 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_9 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_10 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_10) begin
|
|
if (_T_8959) begin
|
|
bht_bank_rd_data_out_1_10 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_10 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_11 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_11) begin
|
|
if (_T_8968) begin
|
|
bht_bank_rd_data_out_1_11 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_11 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_12 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_12) begin
|
|
if (_T_8977) begin
|
|
bht_bank_rd_data_out_1_12 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_12 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_13 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_13) begin
|
|
if (_T_8986) begin
|
|
bht_bank_rd_data_out_1_13 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_13 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_14 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_14) begin
|
|
if (_T_8995) begin
|
|
bht_bank_rd_data_out_1_14 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_14 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_538_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_15 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_15) begin
|
|
if (_T_9004) begin
|
|
bht_bank_rd_data_out_1_15 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_15 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_16 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_0) begin
|
|
if (_T_9013) begin
|
|
bht_bank_rd_data_out_1_16 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_16 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_17 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_1) begin
|
|
if (_T_9022) begin
|
|
bht_bank_rd_data_out_1_17 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_17 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_18 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_2) begin
|
|
if (_T_9031) begin
|
|
bht_bank_rd_data_out_1_18 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_18 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_19 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_3) begin
|
|
if (_T_9040) begin
|
|
bht_bank_rd_data_out_1_19 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_19 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_20 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_4) begin
|
|
if (_T_9049) begin
|
|
bht_bank_rd_data_out_1_20 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_20 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_21 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_5) begin
|
|
if (_T_9058) begin
|
|
bht_bank_rd_data_out_1_21 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_21 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_22 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_6) begin
|
|
if (_T_9067) begin
|
|
bht_bank_rd_data_out_1_22 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_22 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_23 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_7) begin
|
|
if (_T_9076) begin
|
|
bht_bank_rd_data_out_1_23 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_23 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_24 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_8) begin
|
|
if (_T_9085) begin
|
|
bht_bank_rd_data_out_1_24 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_24 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_25 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_9) begin
|
|
if (_T_9094) begin
|
|
bht_bank_rd_data_out_1_25 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_25 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_26 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_10) begin
|
|
if (_T_9103) begin
|
|
bht_bank_rd_data_out_1_26 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_26 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_27 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_11) begin
|
|
if (_T_9112) begin
|
|
bht_bank_rd_data_out_1_27 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_27 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_28 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_12) begin
|
|
if (_T_9121) begin
|
|
bht_bank_rd_data_out_1_28 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_28 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_29 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_13) begin
|
|
if (_T_9130) begin
|
|
bht_bank_rd_data_out_1_29 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_29 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_30 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_14) begin
|
|
if (_T_9139) begin
|
|
bht_bank_rd_data_out_1_30 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_30 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_539_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_31 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_15) begin
|
|
if (_T_9148) begin
|
|
bht_bank_rd_data_out_1_31 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_31 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_32 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_0) begin
|
|
if (_T_9157) begin
|
|
bht_bank_rd_data_out_1_32 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_32 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_33 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_1) begin
|
|
if (_T_9166) begin
|
|
bht_bank_rd_data_out_1_33 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_33 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_34 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_2) begin
|
|
if (_T_9175) begin
|
|
bht_bank_rd_data_out_1_34 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_34 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_35 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_3) begin
|
|
if (_T_9184) begin
|
|
bht_bank_rd_data_out_1_35 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_35 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_36 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_4) begin
|
|
if (_T_9193) begin
|
|
bht_bank_rd_data_out_1_36 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_36 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_37 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_5) begin
|
|
if (_T_9202) begin
|
|
bht_bank_rd_data_out_1_37 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_37 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_38 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_6) begin
|
|
if (_T_9211) begin
|
|
bht_bank_rd_data_out_1_38 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_38 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_39 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_7) begin
|
|
if (_T_9220) begin
|
|
bht_bank_rd_data_out_1_39 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_39 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_40 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_8) begin
|
|
if (_T_9229) begin
|
|
bht_bank_rd_data_out_1_40 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_40 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_41 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_9) begin
|
|
if (_T_9238) begin
|
|
bht_bank_rd_data_out_1_41 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_41 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_42 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_10) begin
|
|
if (_T_9247) begin
|
|
bht_bank_rd_data_out_1_42 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_42 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_43 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_11) begin
|
|
if (_T_9256) begin
|
|
bht_bank_rd_data_out_1_43 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_43 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_44 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_12) begin
|
|
if (_T_9265) begin
|
|
bht_bank_rd_data_out_1_44 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_44 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_45 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_13) begin
|
|
if (_T_9274) begin
|
|
bht_bank_rd_data_out_1_45 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_45 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_46 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_14) begin
|
|
if (_T_9283) begin
|
|
bht_bank_rd_data_out_1_46 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_46 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_540_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_47 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_15) begin
|
|
if (_T_9292) begin
|
|
bht_bank_rd_data_out_1_47 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_47 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_48 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_0) begin
|
|
if (_T_9301) begin
|
|
bht_bank_rd_data_out_1_48 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_48 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_49 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_1) begin
|
|
if (_T_9310) begin
|
|
bht_bank_rd_data_out_1_49 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_49 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_50 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_2) begin
|
|
if (_T_9319) begin
|
|
bht_bank_rd_data_out_1_50 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_50 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_51 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_3) begin
|
|
if (_T_9328) begin
|
|
bht_bank_rd_data_out_1_51 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_51 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_52 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_4) begin
|
|
if (_T_9337) begin
|
|
bht_bank_rd_data_out_1_52 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_52 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_53 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_5) begin
|
|
if (_T_9346) begin
|
|
bht_bank_rd_data_out_1_53 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_53 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_54 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_6) begin
|
|
if (_T_9355) begin
|
|
bht_bank_rd_data_out_1_54 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_54 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_55 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_7) begin
|
|
if (_T_9364) begin
|
|
bht_bank_rd_data_out_1_55 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_55 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_56 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_8) begin
|
|
if (_T_9373) begin
|
|
bht_bank_rd_data_out_1_56 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_56 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_57 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_9) begin
|
|
if (_T_9382) begin
|
|
bht_bank_rd_data_out_1_57 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_57 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_58 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_10) begin
|
|
if (_T_9391) begin
|
|
bht_bank_rd_data_out_1_58 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_58 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_59 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_11) begin
|
|
if (_T_9400) begin
|
|
bht_bank_rd_data_out_1_59 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_59 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_60 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_12) begin
|
|
if (_T_9409) begin
|
|
bht_bank_rd_data_out_1_60 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_60 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_61 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_13) begin
|
|
if (_T_9418) begin
|
|
bht_bank_rd_data_out_1_61 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_61 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_62 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_14) begin
|
|
if (_T_9427) begin
|
|
bht_bank_rd_data_out_1_62 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_62 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_541_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_63 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_15) begin
|
|
if (_T_9436) begin
|
|
bht_bank_rd_data_out_1_63 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_63 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_64 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_0) begin
|
|
if (_T_9445) begin
|
|
bht_bank_rd_data_out_1_64 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_64 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_65 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_1) begin
|
|
if (_T_9454) begin
|
|
bht_bank_rd_data_out_1_65 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_65 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_66 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_2) begin
|
|
if (_T_9463) begin
|
|
bht_bank_rd_data_out_1_66 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_66 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_67 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_3) begin
|
|
if (_T_9472) begin
|
|
bht_bank_rd_data_out_1_67 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_67 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_68 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_4) begin
|
|
if (_T_9481) begin
|
|
bht_bank_rd_data_out_1_68 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_68 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_69 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_5) begin
|
|
if (_T_9490) begin
|
|
bht_bank_rd_data_out_1_69 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_69 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_70 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_6) begin
|
|
if (_T_9499) begin
|
|
bht_bank_rd_data_out_1_70 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_70 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_71 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_7) begin
|
|
if (_T_9508) begin
|
|
bht_bank_rd_data_out_1_71 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_71 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_72 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_8) begin
|
|
if (_T_9517) begin
|
|
bht_bank_rd_data_out_1_72 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_72 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_73 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_9) begin
|
|
if (_T_9526) begin
|
|
bht_bank_rd_data_out_1_73 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_73 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_74 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_10) begin
|
|
if (_T_9535) begin
|
|
bht_bank_rd_data_out_1_74 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_74 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_75 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_11) begin
|
|
if (_T_9544) begin
|
|
bht_bank_rd_data_out_1_75 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_75 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_76 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_12) begin
|
|
if (_T_9553) begin
|
|
bht_bank_rd_data_out_1_76 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_76 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_77 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_13) begin
|
|
if (_T_9562) begin
|
|
bht_bank_rd_data_out_1_77 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_77 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_78 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_14) begin
|
|
if (_T_9571) begin
|
|
bht_bank_rd_data_out_1_78 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_78 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_542_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_79 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_15) begin
|
|
if (_T_9580) begin
|
|
bht_bank_rd_data_out_1_79 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_79 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_80 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_0) begin
|
|
if (_T_9589) begin
|
|
bht_bank_rd_data_out_1_80 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_80 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_81 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_1) begin
|
|
if (_T_9598) begin
|
|
bht_bank_rd_data_out_1_81 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_81 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_82 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_2) begin
|
|
if (_T_9607) begin
|
|
bht_bank_rd_data_out_1_82 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_82 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_83 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_3) begin
|
|
if (_T_9616) begin
|
|
bht_bank_rd_data_out_1_83 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_83 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_84 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_4) begin
|
|
if (_T_9625) begin
|
|
bht_bank_rd_data_out_1_84 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_84 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_85 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_5) begin
|
|
if (_T_9634) begin
|
|
bht_bank_rd_data_out_1_85 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_85 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_86 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_6) begin
|
|
if (_T_9643) begin
|
|
bht_bank_rd_data_out_1_86 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_86 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_87 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_7) begin
|
|
if (_T_9652) begin
|
|
bht_bank_rd_data_out_1_87 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_87 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_88 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_8) begin
|
|
if (_T_9661) begin
|
|
bht_bank_rd_data_out_1_88 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_88 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_89 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_9) begin
|
|
if (_T_9670) begin
|
|
bht_bank_rd_data_out_1_89 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_89 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_90 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_10) begin
|
|
if (_T_9679) begin
|
|
bht_bank_rd_data_out_1_90 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_90 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_91 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_11) begin
|
|
if (_T_9688) begin
|
|
bht_bank_rd_data_out_1_91 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_91 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_92 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_12) begin
|
|
if (_T_9697) begin
|
|
bht_bank_rd_data_out_1_92 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_92 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_93 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_13) begin
|
|
if (_T_9706) begin
|
|
bht_bank_rd_data_out_1_93 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_93 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_94 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_14) begin
|
|
if (_T_9715) begin
|
|
bht_bank_rd_data_out_1_94 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_94 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_543_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_95 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_15) begin
|
|
if (_T_9724) begin
|
|
bht_bank_rd_data_out_1_95 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_95 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_96 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_0) begin
|
|
if (_T_9733) begin
|
|
bht_bank_rd_data_out_1_96 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_96 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_97 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_1) begin
|
|
if (_T_9742) begin
|
|
bht_bank_rd_data_out_1_97 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_97 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_98 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_2) begin
|
|
if (_T_9751) begin
|
|
bht_bank_rd_data_out_1_98 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_98 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_99 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_3) begin
|
|
if (_T_9760) begin
|
|
bht_bank_rd_data_out_1_99 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_99 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_100 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_4) begin
|
|
if (_T_9769) begin
|
|
bht_bank_rd_data_out_1_100 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_100 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_101 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_5) begin
|
|
if (_T_9778) begin
|
|
bht_bank_rd_data_out_1_101 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_101 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_102 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_6) begin
|
|
if (_T_9787) begin
|
|
bht_bank_rd_data_out_1_102 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_102 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_103 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_7) begin
|
|
if (_T_9796) begin
|
|
bht_bank_rd_data_out_1_103 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_103 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_104 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_8) begin
|
|
if (_T_9805) begin
|
|
bht_bank_rd_data_out_1_104 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_104 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_105 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_9) begin
|
|
if (_T_9814) begin
|
|
bht_bank_rd_data_out_1_105 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_105 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_106 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_10) begin
|
|
if (_T_9823) begin
|
|
bht_bank_rd_data_out_1_106 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_106 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_107 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_11) begin
|
|
if (_T_9832) begin
|
|
bht_bank_rd_data_out_1_107 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_107 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_108 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_12) begin
|
|
if (_T_9841) begin
|
|
bht_bank_rd_data_out_1_108 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_108 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_109 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_13) begin
|
|
if (_T_9850) begin
|
|
bht_bank_rd_data_out_1_109 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_109 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_110 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_14) begin
|
|
if (_T_9859) begin
|
|
bht_bank_rd_data_out_1_110 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_110 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_544_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_111 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_15) begin
|
|
if (_T_9868) begin
|
|
bht_bank_rd_data_out_1_111 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_111 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_112 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_0) begin
|
|
if (_T_9877) begin
|
|
bht_bank_rd_data_out_1_112 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_112 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_113 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_1) begin
|
|
if (_T_9886) begin
|
|
bht_bank_rd_data_out_1_113 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_113 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_114 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_2) begin
|
|
if (_T_9895) begin
|
|
bht_bank_rd_data_out_1_114 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_114 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_115 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_3) begin
|
|
if (_T_9904) begin
|
|
bht_bank_rd_data_out_1_115 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_115 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_116 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_4) begin
|
|
if (_T_9913) begin
|
|
bht_bank_rd_data_out_1_116 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_116 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_117 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_5) begin
|
|
if (_T_9922) begin
|
|
bht_bank_rd_data_out_1_117 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_117 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_118 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_6) begin
|
|
if (_T_9931) begin
|
|
bht_bank_rd_data_out_1_118 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_118 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_119 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_7) begin
|
|
if (_T_9940) begin
|
|
bht_bank_rd_data_out_1_119 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_119 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_120 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_8) begin
|
|
if (_T_9949) begin
|
|
bht_bank_rd_data_out_1_120 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_120 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_121 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_9) begin
|
|
if (_T_9958) begin
|
|
bht_bank_rd_data_out_1_121 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_121 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_122 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_10) begin
|
|
if (_T_9967) begin
|
|
bht_bank_rd_data_out_1_122 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_122 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_123 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_11) begin
|
|
if (_T_9976) begin
|
|
bht_bank_rd_data_out_1_123 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_123 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_124 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_12) begin
|
|
if (_T_9985) begin
|
|
bht_bank_rd_data_out_1_124 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_124 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_125 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_13) begin
|
|
if (_T_9994) begin
|
|
bht_bank_rd_data_out_1_125 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_125 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_126 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_14) begin
|
|
if (_T_10003) begin
|
|
bht_bank_rd_data_out_1_126 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_126 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_545_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_127 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_15) begin
|
|
if (_T_10012) begin
|
|
bht_bank_rd_data_out_1_127 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_127 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_128 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_0) begin
|
|
if (_T_10021) begin
|
|
bht_bank_rd_data_out_1_128 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_128 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_129 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_1) begin
|
|
if (_T_10030) begin
|
|
bht_bank_rd_data_out_1_129 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_129 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_130 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_2) begin
|
|
if (_T_10039) begin
|
|
bht_bank_rd_data_out_1_130 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_130 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_131 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_3) begin
|
|
if (_T_10048) begin
|
|
bht_bank_rd_data_out_1_131 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_131 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_132 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_4) begin
|
|
if (_T_10057) begin
|
|
bht_bank_rd_data_out_1_132 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_132 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_133 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_5) begin
|
|
if (_T_10066) begin
|
|
bht_bank_rd_data_out_1_133 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_133 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_134 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_6) begin
|
|
if (_T_10075) begin
|
|
bht_bank_rd_data_out_1_134 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_134 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_135 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_7) begin
|
|
if (_T_10084) begin
|
|
bht_bank_rd_data_out_1_135 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_135 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_136 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_8) begin
|
|
if (_T_10093) begin
|
|
bht_bank_rd_data_out_1_136 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_136 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_137 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_9) begin
|
|
if (_T_10102) begin
|
|
bht_bank_rd_data_out_1_137 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_137 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_138 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_10) begin
|
|
if (_T_10111) begin
|
|
bht_bank_rd_data_out_1_138 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_138 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_139 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_11) begin
|
|
if (_T_10120) begin
|
|
bht_bank_rd_data_out_1_139 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_139 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_140 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_12) begin
|
|
if (_T_10129) begin
|
|
bht_bank_rd_data_out_1_140 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_140 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_141 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_13) begin
|
|
if (_T_10138) begin
|
|
bht_bank_rd_data_out_1_141 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_141 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_142 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_14) begin
|
|
if (_T_10147) begin
|
|
bht_bank_rd_data_out_1_142 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_142 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_546_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_143 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_15) begin
|
|
if (_T_10156) begin
|
|
bht_bank_rd_data_out_1_143 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_143 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_144 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_0) begin
|
|
if (_T_10165) begin
|
|
bht_bank_rd_data_out_1_144 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_144 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_145 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_1) begin
|
|
if (_T_10174) begin
|
|
bht_bank_rd_data_out_1_145 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_145 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_146 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_2) begin
|
|
if (_T_10183) begin
|
|
bht_bank_rd_data_out_1_146 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_146 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_147 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_3) begin
|
|
if (_T_10192) begin
|
|
bht_bank_rd_data_out_1_147 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_147 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_148 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_4) begin
|
|
if (_T_10201) begin
|
|
bht_bank_rd_data_out_1_148 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_148 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_149 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_5) begin
|
|
if (_T_10210) begin
|
|
bht_bank_rd_data_out_1_149 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_149 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_150 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_6) begin
|
|
if (_T_10219) begin
|
|
bht_bank_rd_data_out_1_150 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_150 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_151 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_7) begin
|
|
if (_T_10228) begin
|
|
bht_bank_rd_data_out_1_151 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_151 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_152 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_8) begin
|
|
if (_T_10237) begin
|
|
bht_bank_rd_data_out_1_152 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_152 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_153 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_9) begin
|
|
if (_T_10246) begin
|
|
bht_bank_rd_data_out_1_153 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_153 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_154 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_10) begin
|
|
if (_T_10255) begin
|
|
bht_bank_rd_data_out_1_154 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_154 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_155 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_11) begin
|
|
if (_T_10264) begin
|
|
bht_bank_rd_data_out_1_155 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_155 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_156 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_12) begin
|
|
if (_T_10273) begin
|
|
bht_bank_rd_data_out_1_156 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_156 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_157 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_13) begin
|
|
if (_T_10282) begin
|
|
bht_bank_rd_data_out_1_157 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_157 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_158 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_14) begin
|
|
if (_T_10291) begin
|
|
bht_bank_rd_data_out_1_158 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_158 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_547_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_159 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_15) begin
|
|
if (_T_10300) begin
|
|
bht_bank_rd_data_out_1_159 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_159 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_160 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_0) begin
|
|
if (_T_10309) begin
|
|
bht_bank_rd_data_out_1_160 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_160 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_161 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_1) begin
|
|
if (_T_10318) begin
|
|
bht_bank_rd_data_out_1_161 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_161 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_162 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_2) begin
|
|
if (_T_10327) begin
|
|
bht_bank_rd_data_out_1_162 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_162 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_163 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_3) begin
|
|
if (_T_10336) begin
|
|
bht_bank_rd_data_out_1_163 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_163 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_164 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_4) begin
|
|
if (_T_10345) begin
|
|
bht_bank_rd_data_out_1_164 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_164 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_165 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_5) begin
|
|
if (_T_10354) begin
|
|
bht_bank_rd_data_out_1_165 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_165 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_166 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_6) begin
|
|
if (_T_10363) begin
|
|
bht_bank_rd_data_out_1_166 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_166 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_167 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_7) begin
|
|
if (_T_10372) begin
|
|
bht_bank_rd_data_out_1_167 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_167 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_168 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_8) begin
|
|
if (_T_10381) begin
|
|
bht_bank_rd_data_out_1_168 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_168 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_169 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_9) begin
|
|
if (_T_10390) begin
|
|
bht_bank_rd_data_out_1_169 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_169 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_170 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_10) begin
|
|
if (_T_10399) begin
|
|
bht_bank_rd_data_out_1_170 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_170 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_171 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_11) begin
|
|
if (_T_10408) begin
|
|
bht_bank_rd_data_out_1_171 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_171 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_172 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_12) begin
|
|
if (_T_10417) begin
|
|
bht_bank_rd_data_out_1_172 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_172 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_173 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_13) begin
|
|
if (_T_10426) begin
|
|
bht_bank_rd_data_out_1_173 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_173 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_174 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_14) begin
|
|
if (_T_10435) begin
|
|
bht_bank_rd_data_out_1_174 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_174 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_548_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_175 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_15) begin
|
|
if (_T_10444) begin
|
|
bht_bank_rd_data_out_1_175 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_175 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_176 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_0) begin
|
|
if (_T_10453) begin
|
|
bht_bank_rd_data_out_1_176 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_176 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_177 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_1) begin
|
|
if (_T_10462) begin
|
|
bht_bank_rd_data_out_1_177 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_177 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_178 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_2) begin
|
|
if (_T_10471) begin
|
|
bht_bank_rd_data_out_1_178 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_178 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_179 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_3) begin
|
|
if (_T_10480) begin
|
|
bht_bank_rd_data_out_1_179 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_179 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_180 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_4) begin
|
|
if (_T_10489) begin
|
|
bht_bank_rd_data_out_1_180 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_180 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_181 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_5) begin
|
|
if (_T_10498) begin
|
|
bht_bank_rd_data_out_1_181 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_181 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_182 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_6) begin
|
|
if (_T_10507) begin
|
|
bht_bank_rd_data_out_1_182 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_182 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_183 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_7) begin
|
|
if (_T_10516) begin
|
|
bht_bank_rd_data_out_1_183 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_183 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_184 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_8) begin
|
|
if (_T_10525) begin
|
|
bht_bank_rd_data_out_1_184 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_184 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_185 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_9) begin
|
|
if (_T_10534) begin
|
|
bht_bank_rd_data_out_1_185 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_185 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_186 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_10) begin
|
|
if (_T_10543) begin
|
|
bht_bank_rd_data_out_1_186 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_186 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_187 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_11) begin
|
|
if (_T_10552) begin
|
|
bht_bank_rd_data_out_1_187 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_187 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_188 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_12) begin
|
|
if (_T_10561) begin
|
|
bht_bank_rd_data_out_1_188 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_188 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_189 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_13) begin
|
|
if (_T_10570) begin
|
|
bht_bank_rd_data_out_1_189 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_189 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_190 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_14) begin
|
|
if (_T_10579) begin
|
|
bht_bank_rd_data_out_1_190 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_190 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_549_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_191 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_15) begin
|
|
if (_T_10588) begin
|
|
bht_bank_rd_data_out_1_191 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_191 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_192 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_0) begin
|
|
if (_T_10597) begin
|
|
bht_bank_rd_data_out_1_192 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_192 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_193 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_1) begin
|
|
if (_T_10606) begin
|
|
bht_bank_rd_data_out_1_193 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_193 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_194 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_2) begin
|
|
if (_T_10615) begin
|
|
bht_bank_rd_data_out_1_194 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_194 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_195 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_3) begin
|
|
if (_T_10624) begin
|
|
bht_bank_rd_data_out_1_195 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_195 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_196 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_4) begin
|
|
if (_T_10633) begin
|
|
bht_bank_rd_data_out_1_196 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_196 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_197 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_5) begin
|
|
if (_T_10642) begin
|
|
bht_bank_rd_data_out_1_197 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_197 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_198 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_6) begin
|
|
if (_T_10651) begin
|
|
bht_bank_rd_data_out_1_198 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_198 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_199 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_7) begin
|
|
if (_T_10660) begin
|
|
bht_bank_rd_data_out_1_199 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_199 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_200 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_8) begin
|
|
if (_T_10669) begin
|
|
bht_bank_rd_data_out_1_200 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_200 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_201 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_9) begin
|
|
if (_T_10678) begin
|
|
bht_bank_rd_data_out_1_201 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_201 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_202 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_10) begin
|
|
if (_T_10687) begin
|
|
bht_bank_rd_data_out_1_202 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_202 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_203 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_11) begin
|
|
if (_T_10696) begin
|
|
bht_bank_rd_data_out_1_203 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_203 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_204 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_12) begin
|
|
if (_T_10705) begin
|
|
bht_bank_rd_data_out_1_204 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_204 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_205 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_13) begin
|
|
if (_T_10714) begin
|
|
bht_bank_rd_data_out_1_205 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_205 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_206 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_14) begin
|
|
if (_T_10723) begin
|
|
bht_bank_rd_data_out_1_206 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_206 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_550_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_207 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_15) begin
|
|
if (_T_10732) begin
|
|
bht_bank_rd_data_out_1_207 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_207 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_208 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_0) begin
|
|
if (_T_10741) begin
|
|
bht_bank_rd_data_out_1_208 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_208 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_209 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_1) begin
|
|
if (_T_10750) begin
|
|
bht_bank_rd_data_out_1_209 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_209 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_210 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_2) begin
|
|
if (_T_10759) begin
|
|
bht_bank_rd_data_out_1_210 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_210 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_211 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_3) begin
|
|
if (_T_10768) begin
|
|
bht_bank_rd_data_out_1_211 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_211 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_212 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_4) begin
|
|
if (_T_10777) begin
|
|
bht_bank_rd_data_out_1_212 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_212 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_213 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_5) begin
|
|
if (_T_10786) begin
|
|
bht_bank_rd_data_out_1_213 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_213 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_214 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_6) begin
|
|
if (_T_10795) begin
|
|
bht_bank_rd_data_out_1_214 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_214 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_215 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_7) begin
|
|
if (_T_10804) begin
|
|
bht_bank_rd_data_out_1_215 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_215 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_216 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_8) begin
|
|
if (_T_10813) begin
|
|
bht_bank_rd_data_out_1_216 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_216 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_217 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_9) begin
|
|
if (_T_10822) begin
|
|
bht_bank_rd_data_out_1_217 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_217 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_218 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_10) begin
|
|
if (_T_10831) begin
|
|
bht_bank_rd_data_out_1_218 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_218 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_219 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_11) begin
|
|
if (_T_10840) begin
|
|
bht_bank_rd_data_out_1_219 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_219 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_220 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_12) begin
|
|
if (_T_10849) begin
|
|
bht_bank_rd_data_out_1_220 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_220 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_221 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_13) begin
|
|
if (_T_10858) begin
|
|
bht_bank_rd_data_out_1_221 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_221 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_222 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_14) begin
|
|
if (_T_10867) begin
|
|
bht_bank_rd_data_out_1_222 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_222 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_551_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_223 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_15) begin
|
|
if (_T_10876) begin
|
|
bht_bank_rd_data_out_1_223 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_223 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_224 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_0) begin
|
|
if (_T_10885) begin
|
|
bht_bank_rd_data_out_1_224 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_224 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_225 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_1) begin
|
|
if (_T_10894) begin
|
|
bht_bank_rd_data_out_1_225 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_225 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_226 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_2) begin
|
|
if (_T_10903) begin
|
|
bht_bank_rd_data_out_1_226 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_226 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_227 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_3) begin
|
|
if (_T_10912) begin
|
|
bht_bank_rd_data_out_1_227 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_227 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_228 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_4) begin
|
|
if (_T_10921) begin
|
|
bht_bank_rd_data_out_1_228 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_228 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_229 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_5) begin
|
|
if (_T_10930) begin
|
|
bht_bank_rd_data_out_1_229 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_229 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_230 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_6) begin
|
|
if (_T_10939) begin
|
|
bht_bank_rd_data_out_1_230 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_230 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_231 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_7) begin
|
|
if (_T_10948) begin
|
|
bht_bank_rd_data_out_1_231 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_231 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_232 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_8) begin
|
|
if (_T_10957) begin
|
|
bht_bank_rd_data_out_1_232 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_232 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_233 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_9) begin
|
|
if (_T_10966) begin
|
|
bht_bank_rd_data_out_1_233 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_233 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_234 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_10) begin
|
|
if (_T_10975) begin
|
|
bht_bank_rd_data_out_1_234 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_234 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_235 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_11) begin
|
|
if (_T_10984) begin
|
|
bht_bank_rd_data_out_1_235 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_235 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_236 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_12) begin
|
|
if (_T_10993) begin
|
|
bht_bank_rd_data_out_1_236 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_236 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_237 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_13) begin
|
|
if (_T_11002) begin
|
|
bht_bank_rd_data_out_1_237 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_237 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_238 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_14) begin
|
|
if (_T_11011) begin
|
|
bht_bank_rd_data_out_1_238 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_238 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_552_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_239 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_15) begin
|
|
if (_T_11020) begin
|
|
bht_bank_rd_data_out_1_239 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_239 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_240 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_0) begin
|
|
if (_T_11029) begin
|
|
bht_bank_rd_data_out_1_240 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_240 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_241 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_1) begin
|
|
if (_T_11038) begin
|
|
bht_bank_rd_data_out_1_241 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_241 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_242 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_2) begin
|
|
if (_T_11047) begin
|
|
bht_bank_rd_data_out_1_242 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_242 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_243 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_3) begin
|
|
if (_T_11056) begin
|
|
bht_bank_rd_data_out_1_243 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_243 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_244 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_4) begin
|
|
if (_T_11065) begin
|
|
bht_bank_rd_data_out_1_244 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_244 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_245 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_5) begin
|
|
if (_T_11074) begin
|
|
bht_bank_rd_data_out_1_245 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_245 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_246 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_6) begin
|
|
if (_T_11083) begin
|
|
bht_bank_rd_data_out_1_246 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_246 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_247 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_7) begin
|
|
if (_T_11092) begin
|
|
bht_bank_rd_data_out_1_247 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_247 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_248 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_8) begin
|
|
if (_T_11101) begin
|
|
bht_bank_rd_data_out_1_248 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_248 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_249 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_9) begin
|
|
if (_T_11110) begin
|
|
bht_bank_rd_data_out_1_249 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_249 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_250 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_10) begin
|
|
if (_T_11119) begin
|
|
bht_bank_rd_data_out_1_250 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_250 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_251 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_11) begin
|
|
if (_T_11128) begin
|
|
bht_bank_rd_data_out_1_251 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_251 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_252 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_12) begin
|
|
if (_T_11137) begin
|
|
bht_bank_rd_data_out_1_252 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_252 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_253 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_13) begin
|
|
if (_T_11146) begin
|
|
bht_bank_rd_data_out_1_253 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_253 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_254 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_14) begin
|
|
if (_T_11155) begin
|
|
bht_bank_rd_data_out_1_254 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_254 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_553_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_255 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_15) begin
|
|
if (_T_11164) begin
|
|
bht_bank_rd_data_out_1_255 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_255 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_0 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_0) begin
|
|
if (_T_6565) begin
|
|
bht_bank_rd_data_out_0_0 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_0 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_1 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_1) begin
|
|
if (_T_6574) begin
|
|
bht_bank_rd_data_out_0_1 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_1 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_2 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_2) begin
|
|
if (_T_6583) begin
|
|
bht_bank_rd_data_out_0_2 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_2 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_3 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_3) begin
|
|
if (_T_6592) begin
|
|
bht_bank_rd_data_out_0_3 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_3 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_4 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_4) begin
|
|
if (_T_6601) begin
|
|
bht_bank_rd_data_out_0_4 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_4 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_5 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_5) begin
|
|
if (_T_6610) begin
|
|
bht_bank_rd_data_out_0_5 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_5 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_6 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_6) begin
|
|
if (_T_6619) begin
|
|
bht_bank_rd_data_out_0_6 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_6 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_7 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_7) begin
|
|
if (_T_6628) begin
|
|
bht_bank_rd_data_out_0_7 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_7 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_8 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_8) begin
|
|
if (_T_6637) begin
|
|
bht_bank_rd_data_out_0_8 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_8 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_9 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_9) begin
|
|
if (_T_6646) begin
|
|
bht_bank_rd_data_out_0_9 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_9 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_10 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_10) begin
|
|
if (_T_6655) begin
|
|
bht_bank_rd_data_out_0_10 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_10 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_11 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_11) begin
|
|
if (_T_6664) begin
|
|
bht_bank_rd_data_out_0_11 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_11 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_12 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_12) begin
|
|
if (_T_6673) begin
|
|
bht_bank_rd_data_out_0_12 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_12 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_13 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_13) begin
|
|
if (_T_6682) begin
|
|
bht_bank_rd_data_out_0_13 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_13 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_14 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_14) begin
|
|
if (_T_6691) begin
|
|
bht_bank_rd_data_out_0_14 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_14 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_522_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_15 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_15) begin
|
|
if (_T_6700) begin
|
|
bht_bank_rd_data_out_0_15 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_15 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_16 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_0) begin
|
|
if (_T_6709) begin
|
|
bht_bank_rd_data_out_0_16 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_16 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_17 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_1) begin
|
|
if (_T_6718) begin
|
|
bht_bank_rd_data_out_0_17 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_17 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_18 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_2) begin
|
|
if (_T_6727) begin
|
|
bht_bank_rd_data_out_0_18 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_18 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_19 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_3) begin
|
|
if (_T_6736) begin
|
|
bht_bank_rd_data_out_0_19 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_19 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_20 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_4) begin
|
|
if (_T_6745) begin
|
|
bht_bank_rd_data_out_0_20 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_20 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_21 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_5) begin
|
|
if (_T_6754) begin
|
|
bht_bank_rd_data_out_0_21 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_21 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_22 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_6) begin
|
|
if (_T_6763) begin
|
|
bht_bank_rd_data_out_0_22 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_22 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_23 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_7) begin
|
|
if (_T_6772) begin
|
|
bht_bank_rd_data_out_0_23 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_23 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_24 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_8) begin
|
|
if (_T_6781) begin
|
|
bht_bank_rd_data_out_0_24 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_24 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_25 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_9) begin
|
|
if (_T_6790) begin
|
|
bht_bank_rd_data_out_0_25 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_25 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_26 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_10) begin
|
|
if (_T_6799) begin
|
|
bht_bank_rd_data_out_0_26 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_26 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_27 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_11) begin
|
|
if (_T_6808) begin
|
|
bht_bank_rd_data_out_0_27 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_27 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_28 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_12) begin
|
|
if (_T_6817) begin
|
|
bht_bank_rd_data_out_0_28 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_28 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_29 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_13) begin
|
|
if (_T_6826) begin
|
|
bht_bank_rd_data_out_0_29 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_29 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_30 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_14) begin
|
|
if (_T_6835) begin
|
|
bht_bank_rd_data_out_0_30 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_30 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_523_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_31 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_15) begin
|
|
if (_T_6844) begin
|
|
bht_bank_rd_data_out_0_31 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_31 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_32 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_0) begin
|
|
if (_T_6853) begin
|
|
bht_bank_rd_data_out_0_32 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_32 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_33 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_1) begin
|
|
if (_T_6862) begin
|
|
bht_bank_rd_data_out_0_33 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_33 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_34 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_2) begin
|
|
if (_T_6871) begin
|
|
bht_bank_rd_data_out_0_34 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_34 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_35 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_3) begin
|
|
if (_T_6880) begin
|
|
bht_bank_rd_data_out_0_35 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_35 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_36 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_4) begin
|
|
if (_T_6889) begin
|
|
bht_bank_rd_data_out_0_36 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_36 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_37 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_5) begin
|
|
if (_T_6898) begin
|
|
bht_bank_rd_data_out_0_37 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_37 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_38 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_6) begin
|
|
if (_T_6907) begin
|
|
bht_bank_rd_data_out_0_38 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_38 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_39 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_7) begin
|
|
if (_T_6916) begin
|
|
bht_bank_rd_data_out_0_39 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_39 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_40 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_8) begin
|
|
if (_T_6925) begin
|
|
bht_bank_rd_data_out_0_40 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_40 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_41 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_9) begin
|
|
if (_T_6934) begin
|
|
bht_bank_rd_data_out_0_41 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_41 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_42 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_10) begin
|
|
if (_T_6943) begin
|
|
bht_bank_rd_data_out_0_42 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_42 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_43 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_11) begin
|
|
if (_T_6952) begin
|
|
bht_bank_rd_data_out_0_43 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_43 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_44 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_12) begin
|
|
if (_T_6961) begin
|
|
bht_bank_rd_data_out_0_44 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_44 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_45 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_13) begin
|
|
if (_T_6970) begin
|
|
bht_bank_rd_data_out_0_45 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_45 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_46 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_14) begin
|
|
if (_T_6979) begin
|
|
bht_bank_rd_data_out_0_46 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_46 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_524_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_47 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_15) begin
|
|
if (_T_6988) begin
|
|
bht_bank_rd_data_out_0_47 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_47 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_48 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_0) begin
|
|
if (_T_6997) begin
|
|
bht_bank_rd_data_out_0_48 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_48 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_49 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_1) begin
|
|
if (_T_7006) begin
|
|
bht_bank_rd_data_out_0_49 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_49 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_50 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_2) begin
|
|
if (_T_7015) begin
|
|
bht_bank_rd_data_out_0_50 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_50 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_51 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_3) begin
|
|
if (_T_7024) begin
|
|
bht_bank_rd_data_out_0_51 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_51 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_52 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_4) begin
|
|
if (_T_7033) begin
|
|
bht_bank_rd_data_out_0_52 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_52 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_53 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_5) begin
|
|
if (_T_7042) begin
|
|
bht_bank_rd_data_out_0_53 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_53 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_54 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_6) begin
|
|
if (_T_7051) begin
|
|
bht_bank_rd_data_out_0_54 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_54 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_55 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_7) begin
|
|
if (_T_7060) begin
|
|
bht_bank_rd_data_out_0_55 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_55 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_56 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_8) begin
|
|
if (_T_7069) begin
|
|
bht_bank_rd_data_out_0_56 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_56 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_57 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_9) begin
|
|
if (_T_7078) begin
|
|
bht_bank_rd_data_out_0_57 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_57 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_58 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_10) begin
|
|
if (_T_7087) begin
|
|
bht_bank_rd_data_out_0_58 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_58 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_59 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_11) begin
|
|
if (_T_7096) begin
|
|
bht_bank_rd_data_out_0_59 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_59 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_60 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_12) begin
|
|
if (_T_7105) begin
|
|
bht_bank_rd_data_out_0_60 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_60 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_61 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_13) begin
|
|
if (_T_7114) begin
|
|
bht_bank_rd_data_out_0_61 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_61 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_62 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_14) begin
|
|
if (_T_7123) begin
|
|
bht_bank_rd_data_out_0_62 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_62 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_525_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_63 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_15) begin
|
|
if (_T_7132) begin
|
|
bht_bank_rd_data_out_0_63 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_63 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_64 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_0) begin
|
|
if (_T_7141) begin
|
|
bht_bank_rd_data_out_0_64 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_64 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_65 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_1) begin
|
|
if (_T_7150) begin
|
|
bht_bank_rd_data_out_0_65 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_65 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_66 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_2) begin
|
|
if (_T_7159) begin
|
|
bht_bank_rd_data_out_0_66 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_66 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_67 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_3) begin
|
|
if (_T_7168) begin
|
|
bht_bank_rd_data_out_0_67 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_67 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_68 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_4) begin
|
|
if (_T_7177) begin
|
|
bht_bank_rd_data_out_0_68 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_68 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_69 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_5) begin
|
|
if (_T_7186) begin
|
|
bht_bank_rd_data_out_0_69 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_69 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_70 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_6) begin
|
|
if (_T_7195) begin
|
|
bht_bank_rd_data_out_0_70 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_70 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_71 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_7) begin
|
|
if (_T_7204) begin
|
|
bht_bank_rd_data_out_0_71 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_71 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_72 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_8) begin
|
|
if (_T_7213) begin
|
|
bht_bank_rd_data_out_0_72 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_72 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_73 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_9) begin
|
|
if (_T_7222) begin
|
|
bht_bank_rd_data_out_0_73 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_73 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_74 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_10) begin
|
|
if (_T_7231) begin
|
|
bht_bank_rd_data_out_0_74 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_74 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_75 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_11) begin
|
|
if (_T_7240) begin
|
|
bht_bank_rd_data_out_0_75 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_75 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_76 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_12) begin
|
|
if (_T_7249) begin
|
|
bht_bank_rd_data_out_0_76 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_76 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_77 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_13) begin
|
|
if (_T_7258) begin
|
|
bht_bank_rd_data_out_0_77 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_77 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_78 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_14) begin
|
|
if (_T_7267) begin
|
|
bht_bank_rd_data_out_0_78 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_78 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_526_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_79 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_15) begin
|
|
if (_T_7276) begin
|
|
bht_bank_rd_data_out_0_79 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_79 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_80 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_0) begin
|
|
if (_T_7285) begin
|
|
bht_bank_rd_data_out_0_80 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_80 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_81 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_1) begin
|
|
if (_T_7294) begin
|
|
bht_bank_rd_data_out_0_81 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_81 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_82 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_2) begin
|
|
if (_T_7303) begin
|
|
bht_bank_rd_data_out_0_82 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_82 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_83 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_3) begin
|
|
if (_T_7312) begin
|
|
bht_bank_rd_data_out_0_83 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_83 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_84 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_4) begin
|
|
if (_T_7321) begin
|
|
bht_bank_rd_data_out_0_84 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_84 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_85 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_5) begin
|
|
if (_T_7330) begin
|
|
bht_bank_rd_data_out_0_85 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_85 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_86 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_6) begin
|
|
if (_T_7339) begin
|
|
bht_bank_rd_data_out_0_86 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_86 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_87 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_7) begin
|
|
if (_T_7348) begin
|
|
bht_bank_rd_data_out_0_87 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_87 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_88 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_8) begin
|
|
if (_T_7357) begin
|
|
bht_bank_rd_data_out_0_88 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_88 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_89 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_9) begin
|
|
if (_T_7366) begin
|
|
bht_bank_rd_data_out_0_89 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_89 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_90 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_10) begin
|
|
if (_T_7375) begin
|
|
bht_bank_rd_data_out_0_90 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_90 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_91 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_11) begin
|
|
if (_T_7384) begin
|
|
bht_bank_rd_data_out_0_91 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_91 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_92 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_12) begin
|
|
if (_T_7393) begin
|
|
bht_bank_rd_data_out_0_92 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_92 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_93 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_13) begin
|
|
if (_T_7402) begin
|
|
bht_bank_rd_data_out_0_93 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_93 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_94 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_14) begin
|
|
if (_T_7411) begin
|
|
bht_bank_rd_data_out_0_94 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_94 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_527_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_95 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_15) begin
|
|
if (_T_7420) begin
|
|
bht_bank_rd_data_out_0_95 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_95 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_96 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_0) begin
|
|
if (_T_7429) begin
|
|
bht_bank_rd_data_out_0_96 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_96 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_97 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_1) begin
|
|
if (_T_7438) begin
|
|
bht_bank_rd_data_out_0_97 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_97 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_98 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_2) begin
|
|
if (_T_7447) begin
|
|
bht_bank_rd_data_out_0_98 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_98 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_99 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_3) begin
|
|
if (_T_7456) begin
|
|
bht_bank_rd_data_out_0_99 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_99 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_100 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_4) begin
|
|
if (_T_7465) begin
|
|
bht_bank_rd_data_out_0_100 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_100 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_101 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_5) begin
|
|
if (_T_7474) begin
|
|
bht_bank_rd_data_out_0_101 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_101 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_102 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_6) begin
|
|
if (_T_7483) begin
|
|
bht_bank_rd_data_out_0_102 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_102 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_103 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_7) begin
|
|
if (_T_7492) begin
|
|
bht_bank_rd_data_out_0_103 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_103 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_104 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_8) begin
|
|
if (_T_7501) begin
|
|
bht_bank_rd_data_out_0_104 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_104 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_105 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_9) begin
|
|
if (_T_7510) begin
|
|
bht_bank_rd_data_out_0_105 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_105 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_106 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_10) begin
|
|
if (_T_7519) begin
|
|
bht_bank_rd_data_out_0_106 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_106 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_107 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_11) begin
|
|
if (_T_7528) begin
|
|
bht_bank_rd_data_out_0_107 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_107 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_108 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_12) begin
|
|
if (_T_7537) begin
|
|
bht_bank_rd_data_out_0_108 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_108 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_109 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_13) begin
|
|
if (_T_7546) begin
|
|
bht_bank_rd_data_out_0_109 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_109 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_110 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_14) begin
|
|
if (_T_7555) begin
|
|
bht_bank_rd_data_out_0_110 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_110 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_528_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_111 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_15) begin
|
|
if (_T_7564) begin
|
|
bht_bank_rd_data_out_0_111 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_111 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_112 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_0) begin
|
|
if (_T_7573) begin
|
|
bht_bank_rd_data_out_0_112 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_112 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_113 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_1) begin
|
|
if (_T_7582) begin
|
|
bht_bank_rd_data_out_0_113 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_113 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_114 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_2) begin
|
|
if (_T_7591) begin
|
|
bht_bank_rd_data_out_0_114 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_114 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_115 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_3) begin
|
|
if (_T_7600) begin
|
|
bht_bank_rd_data_out_0_115 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_115 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_116 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_4) begin
|
|
if (_T_7609) begin
|
|
bht_bank_rd_data_out_0_116 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_116 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_117 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_5) begin
|
|
if (_T_7618) begin
|
|
bht_bank_rd_data_out_0_117 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_117 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_118 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_6) begin
|
|
if (_T_7627) begin
|
|
bht_bank_rd_data_out_0_118 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_118 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_119 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_7) begin
|
|
if (_T_7636) begin
|
|
bht_bank_rd_data_out_0_119 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_119 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_120 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_8) begin
|
|
if (_T_7645) begin
|
|
bht_bank_rd_data_out_0_120 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_120 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_121 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_9) begin
|
|
if (_T_7654) begin
|
|
bht_bank_rd_data_out_0_121 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_121 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_122 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_10) begin
|
|
if (_T_7663) begin
|
|
bht_bank_rd_data_out_0_122 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_122 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_123 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_11) begin
|
|
if (_T_7672) begin
|
|
bht_bank_rd_data_out_0_123 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_123 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_124 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_12) begin
|
|
if (_T_7681) begin
|
|
bht_bank_rd_data_out_0_124 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_124 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_125 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_13) begin
|
|
if (_T_7690) begin
|
|
bht_bank_rd_data_out_0_125 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_125 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_126 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_14) begin
|
|
if (_T_7699) begin
|
|
bht_bank_rd_data_out_0_126 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_126 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_529_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_127 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_15) begin
|
|
if (_T_7708) begin
|
|
bht_bank_rd_data_out_0_127 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_127 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_128 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_0) begin
|
|
if (_T_7717) begin
|
|
bht_bank_rd_data_out_0_128 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_128 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_129 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_1) begin
|
|
if (_T_7726) begin
|
|
bht_bank_rd_data_out_0_129 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_129 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_130 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_2) begin
|
|
if (_T_7735) begin
|
|
bht_bank_rd_data_out_0_130 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_130 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_131 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_3) begin
|
|
if (_T_7744) begin
|
|
bht_bank_rd_data_out_0_131 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_131 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_132 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_4) begin
|
|
if (_T_7753) begin
|
|
bht_bank_rd_data_out_0_132 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_132 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_133 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_5) begin
|
|
if (_T_7762) begin
|
|
bht_bank_rd_data_out_0_133 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_133 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_134 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_6) begin
|
|
if (_T_7771) begin
|
|
bht_bank_rd_data_out_0_134 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_134 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_135 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_7) begin
|
|
if (_T_7780) begin
|
|
bht_bank_rd_data_out_0_135 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_135 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_136 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_8) begin
|
|
if (_T_7789) begin
|
|
bht_bank_rd_data_out_0_136 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_136 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_137 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_9) begin
|
|
if (_T_7798) begin
|
|
bht_bank_rd_data_out_0_137 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_137 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_138 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_10) begin
|
|
if (_T_7807) begin
|
|
bht_bank_rd_data_out_0_138 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_138 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_139 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_11) begin
|
|
if (_T_7816) begin
|
|
bht_bank_rd_data_out_0_139 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_139 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_140 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_12) begin
|
|
if (_T_7825) begin
|
|
bht_bank_rd_data_out_0_140 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_140 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_141 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_13) begin
|
|
if (_T_7834) begin
|
|
bht_bank_rd_data_out_0_141 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_141 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_142 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_14) begin
|
|
if (_T_7843) begin
|
|
bht_bank_rd_data_out_0_142 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_142 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_530_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_143 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_15) begin
|
|
if (_T_7852) begin
|
|
bht_bank_rd_data_out_0_143 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_143 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_144 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_0) begin
|
|
if (_T_7861) begin
|
|
bht_bank_rd_data_out_0_144 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_144 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_145 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_1) begin
|
|
if (_T_7870) begin
|
|
bht_bank_rd_data_out_0_145 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_145 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_146 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_2) begin
|
|
if (_T_7879) begin
|
|
bht_bank_rd_data_out_0_146 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_146 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_147 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_3) begin
|
|
if (_T_7888) begin
|
|
bht_bank_rd_data_out_0_147 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_147 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_148 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_4) begin
|
|
if (_T_7897) begin
|
|
bht_bank_rd_data_out_0_148 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_148 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_149 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_5) begin
|
|
if (_T_7906) begin
|
|
bht_bank_rd_data_out_0_149 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_149 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_150 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_6) begin
|
|
if (_T_7915) begin
|
|
bht_bank_rd_data_out_0_150 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_150 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_151 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_7) begin
|
|
if (_T_7924) begin
|
|
bht_bank_rd_data_out_0_151 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_151 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_152 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_8) begin
|
|
if (_T_7933) begin
|
|
bht_bank_rd_data_out_0_152 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_152 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_153 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_9) begin
|
|
if (_T_7942) begin
|
|
bht_bank_rd_data_out_0_153 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_153 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_154 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_10) begin
|
|
if (_T_7951) begin
|
|
bht_bank_rd_data_out_0_154 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_154 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_155 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_11) begin
|
|
if (_T_7960) begin
|
|
bht_bank_rd_data_out_0_155 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_155 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_156 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_12) begin
|
|
if (_T_7969) begin
|
|
bht_bank_rd_data_out_0_156 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_156 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_157 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_13) begin
|
|
if (_T_7978) begin
|
|
bht_bank_rd_data_out_0_157 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_157 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_158 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_14) begin
|
|
if (_T_7987) begin
|
|
bht_bank_rd_data_out_0_158 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_158 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_531_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_159 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_15) begin
|
|
if (_T_7996) begin
|
|
bht_bank_rd_data_out_0_159 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_159 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_160 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_0) begin
|
|
if (_T_8005) begin
|
|
bht_bank_rd_data_out_0_160 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_160 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_161 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_1) begin
|
|
if (_T_8014) begin
|
|
bht_bank_rd_data_out_0_161 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_161 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_162 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_2) begin
|
|
if (_T_8023) begin
|
|
bht_bank_rd_data_out_0_162 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_162 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_163 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_3) begin
|
|
if (_T_8032) begin
|
|
bht_bank_rd_data_out_0_163 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_163 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_164 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_4) begin
|
|
if (_T_8041) begin
|
|
bht_bank_rd_data_out_0_164 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_164 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_165 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_5) begin
|
|
if (_T_8050) begin
|
|
bht_bank_rd_data_out_0_165 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_165 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_166 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_6) begin
|
|
if (_T_8059) begin
|
|
bht_bank_rd_data_out_0_166 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_166 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_167 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_7) begin
|
|
if (_T_8068) begin
|
|
bht_bank_rd_data_out_0_167 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_167 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_168 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_8) begin
|
|
if (_T_8077) begin
|
|
bht_bank_rd_data_out_0_168 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_168 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_169 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_9) begin
|
|
if (_T_8086) begin
|
|
bht_bank_rd_data_out_0_169 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_169 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_170 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_10) begin
|
|
if (_T_8095) begin
|
|
bht_bank_rd_data_out_0_170 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_170 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_171 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_11) begin
|
|
if (_T_8104) begin
|
|
bht_bank_rd_data_out_0_171 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_171 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_172 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_12) begin
|
|
if (_T_8113) begin
|
|
bht_bank_rd_data_out_0_172 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_172 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_173 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_13) begin
|
|
if (_T_8122) begin
|
|
bht_bank_rd_data_out_0_173 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_173 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_174 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_14) begin
|
|
if (_T_8131) begin
|
|
bht_bank_rd_data_out_0_174 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_174 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_532_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_175 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_15) begin
|
|
if (_T_8140) begin
|
|
bht_bank_rd_data_out_0_175 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_175 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_176 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_0) begin
|
|
if (_T_8149) begin
|
|
bht_bank_rd_data_out_0_176 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_176 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_177 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_1) begin
|
|
if (_T_8158) begin
|
|
bht_bank_rd_data_out_0_177 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_177 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_178 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_2) begin
|
|
if (_T_8167) begin
|
|
bht_bank_rd_data_out_0_178 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_178 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_179 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_3) begin
|
|
if (_T_8176) begin
|
|
bht_bank_rd_data_out_0_179 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_179 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_180 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_4) begin
|
|
if (_T_8185) begin
|
|
bht_bank_rd_data_out_0_180 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_180 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_181 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_5) begin
|
|
if (_T_8194) begin
|
|
bht_bank_rd_data_out_0_181 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_181 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_182 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_6) begin
|
|
if (_T_8203) begin
|
|
bht_bank_rd_data_out_0_182 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_182 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_183 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_7) begin
|
|
if (_T_8212) begin
|
|
bht_bank_rd_data_out_0_183 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_183 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_184 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_8) begin
|
|
if (_T_8221) begin
|
|
bht_bank_rd_data_out_0_184 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_184 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_185 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_9) begin
|
|
if (_T_8230) begin
|
|
bht_bank_rd_data_out_0_185 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_185 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_186 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_10) begin
|
|
if (_T_8239) begin
|
|
bht_bank_rd_data_out_0_186 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_186 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_187 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_11) begin
|
|
if (_T_8248) begin
|
|
bht_bank_rd_data_out_0_187 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_187 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_188 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_12) begin
|
|
if (_T_8257) begin
|
|
bht_bank_rd_data_out_0_188 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_188 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_189 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_13) begin
|
|
if (_T_8266) begin
|
|
bht_bank_rd_data_out_0_189 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_189 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_190 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_14) begin
|
|
if (_T_8275) begin
|
|
bht_bank_rd_data_out_0_190 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_190 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_533_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_191 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_15) begin
|
|
if (_T_8284) begin
|
|
bht_bank_rd_data_out_0_191 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_191 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_192 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_0) begin
|
|
if (_T_8293) begin
|
|
bht_bank_rd_data_out_0_192 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_192 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_193 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_1) begin
|
|
if (_T_8302) begin
|
|
bht_bank_rd_data_out_0_193 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_193 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_194 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_2) begin
|
|
if (_T_8311) begin
|
|
bht_bank_rd_data_out_0_194 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_194 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_195 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_3) begin
|
|
if (_T_8320) begin
|
|
bht_bank_rd_data_out_0_195 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_195 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_196 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_4) begin
|
|
if (_T_8329) begin
|
|
bht_bank_rd_data_out_0_196 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_196 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_197 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_5) begin
|
|
if (_T_8338) begin
|
|
bht_bank_rd_data_out_0_197 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_197 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_198 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_6) begin
|
|
if (_T_8347) begin
|
|
bht_bank_rd_data_out_0_198 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_198 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_199 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_7) begin
|
|
if (_T_8356) begin
|
|
bht_bank_rd_data_out_0_199 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_199 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_200 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_8) begin
|
|
if (_T_8365) begin
|
|
bht_bank_rd_data_out_0_200 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_200 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_201 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_9) begin
|
|
if (_T_8374) begin
|
|
bht_bank_rd_data_out_0_201 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_201 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_202 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_10) begin
|
|
if (_T_8383) begin
|
|
bht_bank_rd_data_out_0_202 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_202 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_203 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_11) begin
|
|
if (_T_8392) begin
|
|
bht_bank_rd_data_out_0_203 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_203 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_204 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_12) begin
|
|
if (_T_8401) begin
|
|
bht_bank_rd_data_out_0_204 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_204 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_205 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_13) begin
|
|
if (_T_8410) begin
|
|
bht_bank_rd_data_out_0_205 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_205 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_206 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_14) begin
|
|
if (_T_8419) begin
|
|
bht_bank_rd_data_out_0_206 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_206 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_534_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_207 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_15) begin
|
|
if (_T_8428) begin
|
|
bht_bank_rd_data_out_0_207 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_207 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_208 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_0) begin
|
|
if (_T_8437) begin
|
|
bht_bank_rd_data_out_0_208 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_208 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_209 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_1) begin
|
|
if (_T_8446) begin
|
|
bht_bank_rd_data_out_0_209 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_209 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_210 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_2) begin
|
|
if (_T_8455) begin
|
|
bht_bank_rd_data_out_0_210 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_210 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_211 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_3) begin
|
|
if (_T_8464) begin
|
|
bht_bank_rd_data_out_0_211 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_211 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_212 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_4) begin
|
|
if (_T_8473) begin
|
|
bht_bank_rd_data_out_0_212 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_212 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_213 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_5) begin
|
|
if (_T_8482) begin
|
|
bht_bank_rd_data_out_0_213 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_213 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_214 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_6) begin
|
|
if (_T_8491) begin
|
|
bht_bank_rd_data_out_0_214 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_214 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_215 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_7) begin
|
|
if (_T_8500) begin
|
|
bht_bank_rd_data_out_0_215 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_215 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_216 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_8) begin
|
|
if (_T_8509) begin
|
|
bht_bank_rd_data_out_0_216 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_216 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_217 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_9) begin
|
|
if (_T_8518) begin
|
|
bht_bank_rd_data_out_0_217 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_217 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_218 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_10) begin
|
|
if (_T_8527) begin
|
|
bht_bank_rd_data_out_0_218 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_218 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_219 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_11) begin
|
|
if (_T_8536) begin
|
|
bht_bank_rd_data_out_0_219 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_219 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_220 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_12) begin
|
|
if (_T_8545) begin
|
|
bht_bank_rd_data_out_0_220 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_220 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_221 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_13) begin
|
|
if (_T_8554) begin
|
|
bht_bank_rd_data_out_0_221 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_221 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_222 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_14) begin
|
|
if (_T_8563) begin
|
|
bht_bank_rd_data_out_0_222 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_222 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_535_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_223 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_15) begin
|
|
if (_T_8572) begin
|
|
bht_bank_rd_data_out_0_223 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_223 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_224 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_0) begin
|
|
if (_T_8581) begin
|
|
bht_bank_rd_data_out_0_224 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_224 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_225 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_1) begin
|
|
if (_T_8590) begin
|
|
bht_bank_rd_data_out_0_225 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_225 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_226 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_2) begin
|
|
if (_T_8599) begin
|
|
bht_bank_rd_data_out_0_226 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_226 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_227 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_3) begin
|
|
if (_T_8608) begin
|
|
bht_bank_rd_data_out_0_227 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_227 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_228 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_4) begin
|
|
if (_T_8617) begin
|
|
bht_bank_rd_data_out_0_228 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_228 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_229 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_5) begin
|
|
if (_T_8626) begin
|
|
bht_bank_rd_data_out_0_229 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_229 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_230 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_6) begin
|
|
if (_T_8635) begin
|
|
bht_bank_rd_data_out_0_230 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_230 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_231 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_7) begin
|
|
if (_T_8644) begin
|
|
bht_bank_rd_data_out_0_231 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_231 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_232 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_8) begin
|
|
if (_T_8653) begin
|
|
bht_bank_rd_data_out_0_232 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_232 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_233 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_9) begin
|
|
if (_T_8662) begin
|
|
bht_bank_rd_data_out_0_233 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_233 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_234 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_10) begin
|
|
if (_T_8671) begin
|
|
bht_bank_rd_data_out_0_234 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_234 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_235 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_11) begin
|
|
if (_T_8680) begin
|
|
bht_bank_rd_data_out_0_235 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_235 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_236 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_12) begin
|
|
if (_T_8689) begin
|
|
bht_bank_rd_data_out_0_236 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_236 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_237 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_13) begin
|
|
if (_T_8698) begin
|
|
bht_bank_rd_data_out_0_237 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_237 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_238 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_14) begin
|
|
if (_T_8707) begin
|
|
bht_bank_rd_data_out_0_238 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_238 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_536_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_239 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_15) begin
|
|
if (_T_8716) begin
|
|
bht_bank_rd_data_out_0_239 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_239 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_240 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_0) begin
|
|
if (_T_8725) begin
|
|
bht_bank_rd_data_out_0_240 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_240 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_241 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_1) begin
|
|
if (_T_8734) begin
|
|
bht_bank_rd_data_out_0_241 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_241 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_242 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_2) begin
|
|
if (_T_8743) begin
|
|
bht_bank_rd_data_out_0_242 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_242 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_243 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_3) begin
|
|
if (_T_8752) begin
|
|
bht_bank_rd_data_out_0_243 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_243 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_244 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_4) begin
|
|
if (_T_8761) begin
|
|
bht_bank_rd_data_out_0_244 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_244 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_245 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_5) begin
|
|
if (_T_8770) begin
|
|
bht_bank_rd_data_out_0_245 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_245 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_246 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_6) begin
|
|
if (_T_8779) begin
|
|
bht_bank_rd_data_out_0_246 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_246 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_247 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_7) begin
|
|
if (_T_8788) begin
|
|
bht_bank_rd_data_out_0_247 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_247 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_248 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_8) begin
|
|
if (_T_8797) begin
|
|
bht_bank_rd_data_out_0_248 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_248 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_249 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_9) begin
|
|
if (_T_8806) begin
|
|
bht_bank_rd_data_out_0_249 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_249 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_250 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_10) begin
|
|
if (_T_8815) begin
|
|
bht_bank_rd_data_out_0_250 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_250 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_251 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_11) begin
|
|
if (_T_8824) begin
|
|
bht_bank_rd_data_out_0_251 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_251 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_252 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_12) begin
|
|
if (_T_8833) begin
|
|
bht_bank_rd_data_out_0_252 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_252 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_253 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_13) begin
|
|
if (_T_8842) begin
|
|
bht_bank_rd_data_out_0_253 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_253 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_254 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_14) begin
|
|
if (_T_8851) begin
|
|
bht_bank_rd_data_out_0_254 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_254 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_537_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_255 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_15) begin
|
|
if (_T_8860) begin
|
|
bht_bank_rd_data_out_0_255 <= io_dec_tlu_br0_r_pkt_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_255 <= io_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
exu_mp_way_f <= 1'h0;
|
|
end else begin
|
|
exu_mp_way_f <= io_exu_mp_pkt_bits_way;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
exu_flush_final_d1 <= 1'h0;
|
|
end else begin
|
|
exu_flush_final_d1 <= io_exu_flush_final;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
btb_lru_b0_f <= 256'h0;
|
|
end else begin
|
|
btb_lru_b0_f <= _T_182 | _T_184;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_fetch_adder_prior <= 30'h0;
|
|
end else begin
|
|
ifc_fetch_adder_prior <= io_ifc_fetch_addr_f[30:1];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_0 <= 32'h0;
|
|
end else begin
|
|
rets_out_0 <= _T_481 | _T_482;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_1 <= 32'h0;
|
|
end else begin
|
|
rets_out_1 <= _T_486 | _T_487;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_2 <= 32'h0;
|
|
end else begin
|
|
rets_out_2 <= _T_491 | _T_492;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_3 <= 32'h0;
|
|
end else begin
|
|
rets_out_3 <= _T_496 | _T_497;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_4 <= 32'h0;
|
|
end else begin
|
|
rets_out_4 <= _T_501 | _T_502;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_5 <= 32'h0;
|
|
end else begin
|
|
rets_out_5 <= _T_506 | _T_507;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_6 <= 32'h0;
|
|
end else begin
|
|
rets_out_6 <= _T_511 | _T_512;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_7 <= 32'h0;
|
|
end else begin
|
|
rets_out_7 <= rets_out_6;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_ifu_compress_ctl(
|
|
input [15:0] io_din,
|
|
output [31:0] io_dout
|
|
);
|
|
wire _T_2 = ~io_din[14]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_4 = ~io_din[13]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_7 = ~io_din[6]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_9 = ~io_din[5]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_11 = io_din[15] & _T_2; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_12 = _T_11 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_13 = _T_12 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_14 = _T_13 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_15 = _T_14 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_16 = _T_15 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_23 = ~io_din[11]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_28 = _T_12 & _T_23; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_29 = _T_28 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_30 = _T_29 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire out_30 = _T_16 | _T_30; // @[el2_ifu_compress_ctl.scala 17:53]
|
|
wire _T_38 = ~io_din[10]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_40 = ~io_din[9]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_42 = ~io_din[8]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_44 = ~io_din[7]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_50 = ~io_din[4]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_52 = ~io_din[3]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_54 = ~io_din[2]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_56 = _T_2 & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_57 = _T_56 & _T_23; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_58 = _T_57 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_59 = _T_58 & _T_40; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_60 = _T_59 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_61 = _T_60 & _T_44; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_62 = _T_61 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_63 = _T_62 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_64 = _T_63 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_65 = _T_64 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_66 = _T_65 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire out_20 = _T_66 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_79 = _T_28 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_90 = _T_12 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_91 = _T_90 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_92 = _T_79 | _T_91; // @[el2_ifu_compress_ctl.scala 21:46]
|
|
wire _T_102 = _T_12 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_103 = _T_102 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_104 = _T_92 | _T_103; // @[el2_ifu_compress_ctl.scala 21:80]
|
|
wire _T_114 = _T_12 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_115 = _T_114 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire out_14 = _T_104 | _T_115; // @[el2_ifu_compress_ctl.scala 21:113]
|
|
wire _T_128 = _T_12 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_129 = _T_128 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_130 = _T_129 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_142 = _T_128 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_143 = _T_142 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_144 = _T_130 | _T_143; // @[el2_ifu_compress_ctl.scala 23:50]
|
|
wire _T_147 = ~io_din[0]; // @[el2_ifu_compress_ctl.scala 23:101]
|
|
wire _T_148 = io_din[14] & _T_147; // @[el2_ifu_compress_ctl.scala 23:99]
|
|
wire out_13 = _T_144 | _T_148; // @[el2_ifu_compress_ctl.scala 23:86]
|
|
wire _T_161 = _T_102 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_162 = _T_161 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_175 = _T_162 | _T_79; // @[el2_ifu_compress_ctl.scala 25:47]
|
|
wire _T_188 = _T_175 | _T_91; // @[el2_ifu_compress_ctl.scala 25:81]
|
|
wire _T_190 = ~io_din[15]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_194 = _T_190 & _T_2; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_195 = _T_194 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_196 = _T_188 | _T_195; // @[el2_ifu_compress_ctl.scala 25:115]
|
|
wire _T_200 = io_din[15] & io_din[14]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_201 = _T_200 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire out_12 = _T_196 | _T_201; // @[el2_ifu_compress_ctl.scala 26:26]
|
|
wire _T_217 = _T_11 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_218 = _T_217 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_219 = _T_218 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_220 = _T_219 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_221 = _T_220 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_224 = _T_221 & _T_147; // @[el2_ifu_compress_ctl.scala 28:53]
|
|
wire _T_228 = _T_2 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_229 = _T_224 | _T_228; // @[el2_ifu_compress_ctl.scala 28:67]
|
|
wire _T_234 = _T_200 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire out_6 = _T_229 | _T_234; // @[el2_ifu_compress_ctl.scala 28:88]
|
|
wire _T_239 = io_din[15] & _T_147; // @[el2_ifu_compress_ctl.scala 30:24]
|
|
wire _T_243 = io_din[15] & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_244 = _T_243 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_245 = _T_239 | _T_244; // @[el2_ifu_compress_ctl.scala 30:39]
|
|
wire _T_249 = io_din[13] & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_250 = _T_245 | _T_249; // @[el2_ifu_compress_ctl.scala 30:63]
|
|
wire _T_253 = io_din[13] & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_254 = _T_250 | _T_253; // @[el2_ifu_compress_ctl.scala 30:83]
|
|
wire _T_257 = io_din[13] & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_258 = _T_254 | _T_257; // @[el2_ifu_compress_ctl.scala 30:102]
|
|
wire _T_261 = io_din[13] & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_262 = _T_258 | _T_261; // @[el2_ifu_compress_ctl.scala 31:22]
|
|
wire _T_265 = io_din[13] & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_266 = _T_262 | _T_265; // @[el2_ifu_compress_ctl.scala 31:42]
|
|
wire _T_271 = _T_266 | _T_228; // @[el2_ifu_compress_ctl.scala 31:62]
|
|
wire out_5 = _T_271 | _T_200; // @[el2_ifu_compress_ctl.scala 31:83]
|
|
wire _T_288 = _T_2 & _T_23; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_289 = _T_288 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_290 = _T_289 & _T_40; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_291 = _T_290 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_292 = _T_291 & _T_44; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_295 = _T_292 & _T_147; // @[el2_ifu_compress_ctl.scala 33:50]
|
|
wire _T_303 = _T_194 & _T_147; // @[el2_ifu_compress_ctl.scala 33:87]
|
|
wire _T_304 = _T_295 | _T_303; // @[el2_ifu_compress_ctl.scala 33:65]
|
|
wire _T_308 = _T_2 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_311 = _T_308 & _T_147; // @[el2_ifu_compress_ctl.scala 34:23]
|
|
wire _T_312 = _T_304 | _T_311; // @[el2_ifu_compress_ctl.scala 33:102]
|
|
wire _T_317 = _T_190 & io_din[14]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_318 = _T_317 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_319 = _T_312 | _T_318; // @[el2_ifu_compress_ctl.scala 34:38]
|
|
wire _T_323 = _T_2 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_326 = _T_323 & _T_147; // @[el2_ifu_compress_ctl.scala 34:82]
|
|
wire _T_327 = _T_319 | _T_326; // @[el2_ifu_compress_ctl.scala 34:62]
|
|
wire _T_331 = _T_2 & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_334 = _T_331 & _T_147; // @[el2_ifu_compress_ctl.scala 35:23]
|
|
wire _T_335 = _T_327 | _T_334; // @[el2_ifu_compress_ctl.scala 34:97]
|
|
wire _T_339 = _T_2 & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_342 = _T_339 & _T_147; // @[el2_ifu_compress_ctl.scala 35:58]
|
|
wire _T_343 = _T_335 | _T_342; // @[el2_ifu_compress_ctl.scala 35:38]
|
|
wire _T_347 = _T_2 & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_350 = _T_347 & _T_147; // @[el2_ifu_compress_ctl.scala 35:93]
|
|
wire _T_351 = _T_343 | _T_350; // @[el2_ifu_compress_ctl.scala 35:73]
|
|
wire _T_357 = _T_2 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_358 = _T_357 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire out_4 = _T_351 | _T_358; // @[el2_ifu_compress_ctl.scala 35:108]
|
|
wire _T_380 = _T_56 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_381 = _T_380 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_382 = _T_381 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_383 = _T_382 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_384 = _T_383 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_385 = _T_384 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_386 = _T_385 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_403 = _T_56 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_404 = _T_403 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_405 = _T_404 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_406 = _T_405 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_407 = _T_406 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_408 = _T_407 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_409 = _T_408 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_410 = _T_386 | _T_409; // @[el2_ifu_compress_ctl.scala 40:59]
|
|
wire _T_427 = _T_56 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_428 = _T_427 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_429 = _T_428 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_430 = _T_429 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_431 = _T_430 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_432 = _T_431 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_433 = _T_432 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_434 = _T_410 | _T_433; // @[el2_ifu_compress_ctl.scala 40:107]
|
|
wire _T_451 = _T_56 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_452 = _T_451 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_453 = _T_452 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_454 = _T_453 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_455 = _T_454 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_456 = _T_455 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_457 = _T_456 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_458 = _T_434 | _T_457; // @[el2_ifu_compress_ctl.scala 41:50]
|
|
wire _T_475 = _T_56 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_476 = _T_475 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_477 = _T_476 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_478 = _T_477 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_479 = _T_478 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_480 = _T_479 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_481 = _T_480 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_482 = _T_458 | _T_481; // @[el2_ifu_compress_ctl.scala 41:94]
|
|
wire _T_487 = ~io_din[12]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_499 = _T_11 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_500 = _T_499 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_501 = _T_500 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_502 = _T_501 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_503 = _T_502 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_504 = _T_503 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_507 = _T_504 & _T_147; // @[el2_ifu_compress_ctl.scala 42:94]
|
|
wire _T_508 = _T_482 | _T_507; // @[el2_ifu_compress_ctl.scala 42:49]
|
|
wire _T_514 = _T_190 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_515 = _T_514 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_516 = _T_508 | _T_515; // @[el2_ifu_compress_ctl.scala 42:109]
|
|
wire _T_522 = _T_514 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_523 = _T_516 | _T_522; // @[el2_ifu_compress_ctl.scala 43:26]
|
|
wire _T_529 = _T_514 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_530 = _T_523 | _T_529; // @[el2_ifu_compress_ctl.scala 43:48]
|
|
wire _T_536 = _T_514 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_537 = _T_530 | _T_536; // @[el2_ifu_compress_ctl.scala 43:70]
|
|
wire _T_543 = _T_514 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_544 = _T_537 | _T_543; // @[el2_ifu_compress_ctl.scala 43:93]
|
|
wire out_2 = _T_544 | _T_228; // @[el2_ifu_compress_ctl.scala 44:26]
|
|
wire [4:0] rs2d = io_din[6:2]; // @[el2_ifu_compress_ctl.scala 50:20]
|
|
wire [4:0] rdd = io_din[11:7]; // @[el2_ifu_compress_ctl.scala 51:19]
|
|
wire [4:0] rdpd = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
|
|
wire [4:0] rs2pd = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
|
|
wire _T_557 = _T_308 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_564 = _T_317 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_565 = _T_564 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_566 = _T_557 | _T_565; // @[el2_ifu_compress_ctl.scala 55:33]
|
|
wire _T_572 = _T_323 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_573 = _T_566 | _T_572; // @[el2_ifu_compress_ctl.scala 55:58]
|
|
wire _T_580 = _T_317 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_581 = _T_580 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_582 = _T_573 | _T_581; // @[el2_ifu_compress_ctl.scala 55:79]
|
|
wire _T_588 = _T_331 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_589 = _T_582 | _T_588; // @[el2_ifu_compress_ctl.scala 55:104]
|
|
wire _T_596 = _T_317 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_597 = _T_596 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_598 = _T_589 | _T_597; // @[el2_ifu_compress_ctl.scala 56:24]
|
|
wire _T_604 = _T_339 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_605 = _T_598 | _T_604; // @[el2_ifu_compress_ctl.scala 56:48]
|
|
wire _T_613 = _T_317 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_614 = _T_613 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_615 = _T_605 | _T_614; // @[el2_ifu_compress_ctl.scala 56:69]
|
|
wire _T_621 = _T_347 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_622 = _T_615 | _T_621; // @[el2_ifu_compress_ctl.scala 56:94]
|
|
wire _T_629 = _T_317 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_630 = _T_629 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_631 = _T_622 | _T_630; // @[el2_ifu_compress_ctl.scala 57:22]
|
|
wire _T_635 = _T_190 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_636 = _T_631 | _T_635; // @[el2_ifu_compress_ctl.scala 57:46]
|
|
wire _T_642 = _T_190 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_643 = _T_642 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire rdrd = _T_636 | _T_643; // @[el2_ifu_compress_ctl.scala 57:65]
|
|
wire _T_651 = _T_380 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_659 = _T_403 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_660 = _T_651 | _T_659; // @[el2_ifu_compress_ctl.scala 59:38]
|
|
wire _T_668 = _T_427 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_669 = _T_660 | _T_668; // @[el2_ifu_compress_ctl.scala 59:63]
|
|
wire _T_677 = _T_451 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_678 = _T_669 | _T_677; // @[el2_ifu_compress_ctl.scala 59:87]
|
|
wire _T_686 = _T_475 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_687 = _T_678 | _T_686; // @[el2_ifu_compress_ctl.scala 60:27]
|
|
wire _T_703 = _T_2 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_704 = _T_703 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_705 = _T_704 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_706 = _T_705 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_707 = _T_706 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_708 = _T_707 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_709 = _T_708 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_710 = _T_687 | _T_709; // @[el2_ifu_compress_ctl.scala 60:51]
|
|
wire _T_717 = _T_56 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_718 = _T_717 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_719 = _T_710 | _T_718; // @[el2_ifu_compress_ctl.scala 60:89]
|
|
wire _T_726 = _T_56 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_727 = _T_726 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_728 = _T_719 | _T_727; // @[el2_ifu_compress_ctl.scala 61:27]
|
|
wire _T_735 = _T_56 & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_736 = _T_735 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_737 = _T_728 | _T_736; // @[el2_ifu_compress_ctl.scala 61:51]
|
|
wire _T_744 = _T_56 & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_745 = _T_744 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_746 = _T_737 | _T_745; // @[el2_ifu_compress_ctl.scala 61:75]
|
|
wire _T_753 = _T_56 & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_754 = _T_753 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_755 = _T_746 | _T_754; // @[el2_ifu_compress_ctl.scala 61:99]
|
|
wire _T_764 = _T_194 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_765 = _T_764 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_766 = _T_755 | _T_765; // @[el2_ifu_compress_ctl.scala 62:27]
|
|
wire rdrs1 = _T_766 | _T_195; // @[el2_ifu_compress_ctl.scala 62:54]
|
|
wire _T_777 = io_din[15] & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_778 = _T_777 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_782 = io_din[15] & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_783 = _T_782 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_784 = _T_778 | _T_783; // @[el2_ifu_compress_ctl.scala 64:34]
|
|
wire _T_788 = io_din[15] & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_789 = _T_788 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_790 = _T_784 | _T_789; // @[el2_ifu_compress_ctl.scala 64:54]
|
|
wire _T_794 = io_din[15] & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_795 = _T_794 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_796 = _T_790 | _T_795; // @[el2_ifu_compress_ctl.scala 64:74]
|
|
wire _T_800 = io_din[15] & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_801 = _T_800 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_802 = _T_796 | _T_801; // @[el2_ifu_compress_ctl.scala 64:94]
|
|
wire _T_807 = _T_200 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire rs2rs2 = _T_802 | _T_807; // @[el2_ifu_compress_ctl.scala 64:114]
|
|
wire rdprd = _T_12 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_820 = io_din[15] & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_821 = _T_820 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_827 = _T_821 | _T_234; // @[el2_ifu_compress_ctl.scala 68:36]
|
|
wire _T_830 = ~io_din[1]; // @[el2_ifu_compress_ctl.scala 12:83]
|
|
wire _T_831 = io_din[14] & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_834 = _T_831 & _T_147; // @[el2_ifu_compress_ctl.scala 68:76]
|
|
wire rdprs1 = _T_827 | _T_834; // @[el2_ifu_compress_ctl.scala 68:57]
|
|
wire _T_846 = _T_128 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_847 = _T_846 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_851 = io_din[15] & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_854 = _T_851 & _T_147; // @[el2_ifu_compress_ctl.scala 70:66]
|
|
wire rs2prs2 = _T_847 | _T_854; // @[el2_ifu_compress_ctl.scala 70:47]
|
|
wire _T_859 = _T_190 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire rs2prd = _T_859 & _T_147; // @[el2_ifu_compress_ctl.scala 72:33]
|
|
wire _T_866 = _T_2 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire uimm9_2 = _T_866 & _T_147; // @[el2_ifu_compress_ctl.scala 74:34]
|
|
wire _T_875 = _T_317 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire ulwimm6_2 = _T_875 & _T_147; // @[el2_ifu_compress_ctl.scala 76:39]
|
|
wire ulwspimm7_2 = _T_317 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_897 = _T_317 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_898 = _T_897 & _T_23; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_899 = _T_898 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_900 = _T_899 & _T_40; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_901 = _T_900 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire rdeq2 = _T_901 & _T_44; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1027 = _T_194 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire rdeq1 = _T_482 | _T_1027; // @[el2_ifu_compress_ctl.scala 84:42]
|
|
wire _T_1050 = io_din[14] & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1051 = rdeq2 | _T_1050; // @[el2_ifu_compress_ctl.scala 86:53]
|
|
wire rs1eq2 = _T_1051 | uimm9_2; // @[el2_ifu_compress_ctl.scala 86:71]
|
|
wire _T_1092 = _T_357 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1093 = _T_1092 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1094 = _T_1093 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire simm5_0 = _T_1094 | _T_643; // @[el2_ifu_compress_ctl.scala 92:45]
|
|
wire _T_1112 = _T_897 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1121 = _T_897 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1122 = _T_1112 | _T_1121; // @[el2_ifu_compress_ctl.scala 96:44]
|
|
wire _T_1130 = _T_897 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1131 = _T_1122 | _T_1130; // @[el2_ifu_compress_ctl.scala 96:70]
|
|
wire _T_1139 = _T_897 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1140 = _T_1131 | _T_1139; // @[el2_ifu_compress_ctl.scala 96:95]
|
|
wire _T_1148 = _T_897 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire sluimm17_12 = _T_1140 | _T_1148; // @[el2_ifu_compress_ctl.scala 96:121]
|
|
wire uimm5_0 = _T_79 | _T_195; // @[el2_ifu_compress_ctl.scala 98:45]
|
|
wire [6:0] l1_6 = {out_6,out_5,out_4,_T_228,out_2,1'h1,1'h1}; // @[Cat.scala 29:58]
|
|
wire [4:0] _T_1192 = rdrd ? rdd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1193 = rdprd ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1194 = rs2prd ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1195 = rdeq1 ? 5'h1 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1196 = rdeq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1197 = _T_1192 | _T_1193; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1198 = _T_1197 | _T_1194; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1199 = _T_1198 | _T_1195; // @[Mux.scala 27:72]
|
|
wire [4:0] l1_11 = _T_1199 | _T_1196; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1210 = rdrs1 ? rdd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1211 = rdprs1 ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1212 = rs1eq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1213 = _T_1210 | _T_1211; // @[Mux.scala 27:72]
|
|
wire [4:0] l1_19 = _T_1213 | _T_1212; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1219 = {3'h0,1'h0,out_20}; // @[Cat.scala 29:58]
|
|
wire [4:0] _T_1222 = rs2rs2 ? rs2d : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1223 = rs2prs2 ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1224 = _T_1222 | _T_1223; // @[Mux.scala 27:72]
|
|
wire [4:0] l1_24 = _T_1219 | _T_1224; // @[el2_ifu_compress_ctl.scala 114:67]
|
|
wire [14:0] _T_1232 = {out_14,out_13,out_12,l1_11,l1_6}; // @[Cat.scala 29:58]
|
|
wire [31:0] l1 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19,_T_1232}; // @[Cat.scala 29:58]
|
|
wire [5:0] simm5d = {io_din[12],rs2d}; // @[Cat.scala 29:58]
|
|
wire [5:0] simm9d = {io_din[12],io_din[4:3],io_din[5],io_din[2],io_din[6]}; // @[Cat.scala 29:58]
|
|
wire [10:0] sjald_1 = {io_din[12],io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:4],io_din[3]}; // @[Cat.scala 29:58]
|
|
wire [19:0] sjald = {io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],sjald_1}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_1296 = {io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12]}; // @[Cat.scala 29:58]
|
|
wire [19:0] sluimmd = {_T_1296,io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],rs2d}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1314 = {simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[4:0]}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1317 = {2'h0,io_din[10:7],io_din[12:11],io_din[5],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1325 = {simm9d[5],simm9d[5],simm9d[5],simm9d[4:0],4'h0}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1328 = {5'h0,io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1331 = {4'h0,io_din[3:2],io_din[12],io_din[6:4],2'h0}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1333 = {6'h0,io_din[12],rs2d}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1339 = {sjald[19],sjald[9:0],sjald[10]}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1342 = simm5_0 ? _T_1314 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1343 = uimm9_2 ? _T_1317 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1344 = rdeq2 ? _T_1325 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1345 = ulwimm6_2 ? _T_1328 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1346 = ulwspimm7_2 ? _T_1331 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1347 = uimm5_0 ? _T_1333 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1348 = _T_228 ? _T_1339 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1349 = sluimm17_12 ? sluimmd[19:8] : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1350 = _T_1342 | _T_1343; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1351 = _T_1350 | _T_1344; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1352 = _T_1351 | _T_1345; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1353 = _T_1352 | _T_1346; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1354 = _T_1353 | _T_1347; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1355 = _T_1354 | _T_1348; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1356 = _T_1355 | _T_1349; // @[Mux.scala 27:72]
|
|
wire [11:0] l2_31 = l1[31:20] | _T_1356; // @[el2_ifu_compress_ctl.scala 133:25]
|
|
wire [7:0] _T_1363 = _T_228 ? sjald[19:12] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_1364 = sluimm17_12 ? sluimmd[7:0] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_1365 = _T_1363 | _T_1364; // @[Mux.scala 27:72]
|
|
wire [7:0] l2_19 = l1[19:12] | _T_1365; // @[el2_ifu_compress_ctl.scala 143:25]
|
|
wire [31:0] l2 = {l2_31,l2_19,l1[11:0]}; // @[Cat.scala 29:58]
|
|
wire [8:0] sbr8d = {io_din[12],io_din[6],io_din[5],io_din[2],io_din[11],io_din[10],io_din[4],io_din[3],1'h0}; // @[Cat.scala 29:58]
|
|
wire [6:0] uswimm6d = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] uswspimm7d = {io_din[8:7],io_din[12:9],2'h0}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_1400 = {sbr8d[8],sbr8d[8],sbr8d[8],sbr8d[8],sbr8d[7:5]}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_1403 = {5'h0,uswimm6d[6:5]}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_1406 = {4'h0,uswspimm7d[7:5]}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_1407 = _T_234 ? _T_1400 : 7'h0; // @[Mux.scala 27:72]
|
|
wire [6:0] _T_1408 = _T_854 ? _T_1403 : 7'h0; // @[Mux.scala 27:72]
|
|
wire [6:0] _T_1409 = _T_807 ? _T_1406 : 7'h0; // @[Mux.scala 27:72]
|
|
wire [6:0] _T_1410 = _T_1407 | _T_1408; // @[Mux.scala 27:72]
|
|
wire [6:0] _T_1411 = _T_1410 | _T_1409; // @[Mux.scala 27:72]
|
|
wire [6:0] l3_31 = l2[31:25] | _T_1411; // @[el2_ifu_compress_ctl.scala 151:25]
|
|
wire [12:0] l3_24 = l2[24:12]; // @[el2_ifu_compress_ctl.scala 154:17]
|
|
wire [4:0] _T_1417 = {sbr8d[4:1],sbr8d[8]}; // @[Cat.scala 29:58]
|
|
wire [4:0] _T_1422 = _T_234 ? _T_1417 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1423 = _T_854 ? uswimm6d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1424 = _T_807 ? uswspimm7d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1425 = _T_1422 | _T_1423; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1426 = _T_1425 | _T_1424; // @[Mux.scala 27:72]
|
|
wire [4:0] l3_11 = l2[11:7] | _T_1426; // @[el2_ifu_compress_ctl.scala 156:24]
|
|
wire [31:0] l3 = {l3_31,l3_24,l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
|
wire _T_1437 = _T_4 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1438 = _T_1437 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1439 = _T_1438 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1442 = _T_1439 & _T_147; // @[el2_ifu_compress_ctl.scala 162:39]
|
|
wire _T_1450 = _T_1437 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1451 = _T_1450 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1454 = _T_1451 & _T_147; // @[el2_ifu_compress_ctl.scala 162:79]
|
|
wire _T_1455 = _T_1442 | _T_1454; // @[el2_ifu_compress_ctl.scala 162:54]
|
|
wire _T_1464 = _T_642 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1465 = _T_1464 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1466 = _T_1455 | _T_1465; // @[el2_ifu_compress_ctl.scala 162:94]
|
|
wire _T_1474 = _T_1437 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1475 = _T_1474 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1478 = _T_1475 & _T_147; // @[el2_ifu_compress_ctl.scala 163:55]
|
|
wire _T_1479 = _T_1466 | _T_1478; // @[el2_ifu_compress_ctl.scala 163:30]
|
|
wire _T_1487 = _T_1437 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1488 = _T_1487 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1491 = _T_1488 & _T_147; // @[el2_ifu_compress_ctl.scala 163:96]
|
|
wire _T_1492 = _T_1479 | _T_1491; // @[el2_ifu_compress_ctl.scala 163:70]
|
|
wire _T_1501 = _T_642 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1502 = _T_1501 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1503 = _T_1492 | _T_1502; // @[el2_ifu_compress_ctl.scala 163:111]
|
|
wire _T_1510 = io_din[15] & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1511 = _T_1510 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1512 = _T_1511 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1513 = _T_1503 | _T_1512; // @[el2_ifu_compress_ctl.scala 164:29]
|
|
wire _T_1521 = _T_1437 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1522 = _T_1521 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1525 = _T_1522 & _T_147; // @[el2_ifu_compress_ctl.scala 164:79]
|
|
wire _T_1526 = _T_1513 | _T_1525; // @[el2_ifu_compress_ctl.scala 164:54]
|
|
wire _T_1533 = _T_487 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1534 = _T_1533 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1535 = _T_1534 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1536 = _T_1526 | _T_1535; // @[el2_ifu_compress_ctl.scala 164:94]
|
|
wire _T_1545 = _T_642 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1546 = _T_1545 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1547 = _T_1536 | _T_1546; // @[el2_ifu_compress_ctl.scala 164:118]
|
|
wire _T_1555 = _T_1437 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1556 = _T_1555 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1559 = _T_1556 & _T_147; // @[el2_ifu_compress_ctl.scala 165:28]
|
|
wire _T_1560 = _T_1547 | _T_1559; // @[el2_ifu_compress_ctl.scala 164:144]
|
|
wire _T_1567 = _T_487 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1568 = _T_1567 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1569 = _T_1568 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1570 = _T_1560 | _T_1569; // @[el2_ifu_compress_ctl.scala 165:43]
|
|
wire _T_1579 = _T_642 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1580 = _T_1579 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1581 = _T_1570 | _T_1580; // @[el2_ifu_compress_ctl.scala 165:67]
|
|
wire _T_1589 = _T_1437 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1590 = _T_1589 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1593 = _T_1590 & _T_147; // @[el2_ifu_compress_ctl.scala 166:28]
|
|
wire _T_1594 = _T_1581 | _T_1593; // @[el2_ifu_compress_ctl.scala 165:94]
|
|
wire _T_1602 = io_din[12] & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1603 = _T_1602 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1604 = _T_1603 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1605 = _T_1604 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1606 = _T_1594 | _T_1605; // @[el2_ifu_compress_ctl.scala 166:43]
|
|
wire _T_1615 = _T_642 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1616 = _T_1615 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1617 = _T_1606 | _T_1616; // @[el2_ifu_compress_ctl.scala 166:71]
|
|
wire _T_1625 = _T_1437 & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1626 = _T_1625 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1629 = _T_1626 & _T_147; // @[el2_ifu_compress_ctl.scala 167:28]
|
|
wire _T_1630 = _T_1617 | _T_1629; // @[el2_ifu_compress_ctl.scala 166:97]
|
|
wire _T_1636 = io_din[13] & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1637 = _T_1636 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1638 = _T_1637 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1639 = _T_1630 | _T_1638; // @[el2_ifu_compress_ctl.scala 167:43]
|
|
wire _T_1648 = _T_642 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1649 = _T_1648 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1650 = _T_1639 | _T_1649; // @[el2_ifu_compress_ctl.scala 167:67]
|
|
wire _T_1658 = _T_1437 & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1659 = _T_1658 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1662 = _T_1659 & _T_147; // @[el2_ifu_compress_ctl.scala 168:28]
|
|
wire _T_1663 = _T_1650 | _T_1662; // @[el2_ifu_compress_ctl.scala 167:93]
|
|
wire _T_1669 = io_din[13] & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1670 = _T_1669 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1671 = _T_1670 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1672 = _T_1663 | _T_1671; // @[el2_ifu_compress_ctl.scala 168:43]
|
|
wire _T_1680 = _T_1437 & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1681 = _T_1680 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1684 = _T_1681 & _T_147; // @[el2_ifu_compress_ctl.scala 168:91]
|
|
wire _T_1685 = _T_1672 | _T_1684; // @[el2_ifu_compress_ctl.scala 168:66]
|
|
wire _T_1694 = _T_642 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1695 = _T_1694 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1696 = _T_1685 | _T_1695; // @[el2_ifu_compress_ctl.scala 168:106]
|
|
wire _T_1702 = io_din[13] & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1703 = _T_1702 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1704 = _T_1703 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1705 = _T_1696 | _T_1704; // @[el2_ifu_compress_ctl.scala 169:29]
|
|
wire _T_1711 = io_din[13] & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1712 = _T_1711 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1713 = _T_1712 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1714 = _T_1705 | _T_1713; // @[el2_ifu_compress_ctl.scala 169:52]
|
|
wire _T_1720 = io_din[14] & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1721 = _T_1720 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1722 = _T_1714 | _T_1721; // @[el2_ifu_compress_ctl.scala 169:75]
|
|
wire _T_1731 = _T_703 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1732 = _T_1731 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1733 = _T_1722 | _T_1732; // @[el2_ifu_compress_ctl.scala 169:98]
|
|
wire _T_1740 = _T_820 & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1741 = _T_1740 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1744 = _T_1741 & _T_147; // @[el2_ifu_compress_ctl.scala 170:54]
|
|
wire _T_1745 = _T_1733 | _T_1744; // @[el2_ifu_compress_ctl.scala 170:29]
|
|
wire _T_1754 = _T_642 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1755 = _T_1754 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1758 = _T_1755 & _T_147; // @[el2_ifu_compress_ctl.scala 170:96]
|
|
wire _T_1759 = _T_1745 | _T_1758; // @[el2_ifu_compress_ctl.scala 170:69]
|
|
wire _T_1768 = _T_642 & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1769 = _T_1768 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
|
wire _T_1770 = _T_1759 | _T_1769; // @[el2_ifu_compress_ctl.scala 170:111]
|
|
wire _T_1777 = _T_1720 & _T_147; // @[el2_ifu_compress_ctl.scala 171:50]
|
|
wire legal = _T_1770 | _T_1777; // @[el2_ifu_compress_ctl.scala 171:30]
|
|
wire [9:0] _T_1787 = {legal,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_1796 = {_T_1787,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_1805 = {_T_1796,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1809 = {_T_1805,legal,legal,legal,legal}; // @[Cat.scala 29:58]
|
|
assign io_dout = l3 & _T_1809; // @[el2_ifu_compress_ctl.scala 173:10]
|
|
endmodule
|
|
module el2_ifu_aln_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_scan_mode,
|
|
input io_active_clk,
|
|
input io_ifu_async_error_start,
|
|
input io_iccm_rd_ecc_double_err,
|
|
input io_ic_access_fault_f,
|
|
input [1:0] io_ic_access_fault_type_f,
|
|
input [7:0] io_ifu_bp_fghr_f,
|
|
input [30:0] io_ifu_bp_btb_target_f,
|
|
input [11:0] io_ifu_bp_poffset_f,
|
|
input [1:0] io_ifu_bp_hist0_f,
|
|
input [1:0] io_ifu_bp_hist1_f,
|
|
input [1:0] io_ifu_bp_pc4_f,
|
|
input [1:0] io_ifu_bp_way_f,
|
|
input [1:0] io_ifu_bp_valid_f,
|
|
input [1:0] io_ifu_bp_ret_f,
|
|
input io_exu_flush_final,
|
|
input io_dec_i0_decode_d,
|
|
input [31:0] io_ifu_fetch_data_f,
|
|
input [1:0] io_ifu_fetch_val,
|
|
input [30:0] io_ifu_fetch_pc,
|
|
output io_ifu_i0_valid,
|
|
output io_ifu_i0_icaf,
|
|
output [1:0] io_ifu_i0_icaf_type,
|
|
output io_ifu_i0_icaf_f1,
|
|
output io_ifu_i0_dbecc,
|
|
output [31:0] io_ifu_i0_instr,
|
|
output [30:0] io_ifu_i0_pc,
|
|
output io_ifu_i0_pc4,
|
|
output io_ifu_fb_consume1,
|
|
output io_ifu_fb_consume2,
|
|
output [7:0] io_ifu_i0_bp_index,
|
|
output [7:0] io_ifu_i0_bp_fghr,
|
|
output [4:0] io_ifu_i0_bp_btag,
|
|
output io_ifu_pmu_instr_aligned,
|
|
output [15:0] io_ifu_i0_cinst,
|
|
output io_i0_brp_valid,
|
|
output [11:0] io_i0_brp_toffset,
|
|
output [1:0] io_i0_brp_hist,
|
|
output io_i0_brp_br_error,
|
|
output io_i0_brp_br_start_error,
|
|
output [30:0] io_i0_brp_prett,
|
|
output io_i0_brp_way,
|
|
output io_i0_brp_ret
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [63:0] _RAND_18;
|
|
reg [63:0] _RAND_19;
|
|
reg [63:0] _RAND_20;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire [15:0] decompressed_io_din; // @[el2_ifu_aln_ctl.scala 366:28]
|
|
wire [31:0] decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 366:28]
|
|
reg error_stall; // @[el2_ifu_aln_ctl.scala 128:51]
|
|
wire _T = error_stall | io_ifu_async_error_start; // @[el2_ifu_aln_ctl.scala 126:34]
|
|
wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_aln_ctl.scala 126:64]
|
|
reg [1:0] wrptr; // @[el2_ifu_aln_ctl.scala 129:48]
|
|
reg [1:0] rdptr; // @[el2_ifu_aln_ctl.scala 130:48]
|
|
reg [1:0] f2val; // @[el2_ifu_aln_ctl.scala 132:48]
|
|
reg [1:0] f1val; // @[el2_ifu_aln_ctl.scala 133:48]
|
|
reg [1:0] f0val; // @[el2_ifu_aln_ctl.scala 134:48]
|
|
reg q2off; // @[el2_ifu_aln_ctl.scala 136:48]
|
|
reg q1off; // @[el2_ifu_aln_ctl.scala 137:48]
|
|
reg q0off; // @[el2_ifu_aln_ctl.scala 138:48]
|
|
wire _T_785 = ~error_stall; // @[el2_ifu_aln_ctl.scala 408:39]
|
|
wire i0_shift = io_dec_i0_decode_d & _T_785; // @[el2_ifu_aln_ctl.scala 408:37]
|
|
wire _T_186 = rdptr == 2'h0; // @[el2_ifu_aln_ctl.scala 188:31]
|
|
wire _T_189 = _T_186 & q0off; // @[Mux.scala 27:72]
|
|
wire _T_187 = rdptr == 2'h1; // @[el2_ifu_aln_ctl.scala 189:11]
|
|
wire _T_190 = _T_187 & q1off; // @[Mux.scala 27:72]
|
|
wire _T_192 = _T_189 | _T_190; // @[Mux.scala 27:72]
|
|
wire _T_188 = rdptr == 2'h2; // @[el2_ifu_aln_ctl.scala 190:11]
|
|
wire _T_191 = _T_188 & q2off; // @[Mux.scala 27:72]
|
|
wire q0ptr = _T_192 | _T_191; // @[Mux.scala 27:72]
|
|
wire _T_202 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 194:26]
|
|
wire [1:0] q0sel = {q0ptr,_T_202}; // @[Cat.scala 29:58]
|
|
wire [2:0] qren = {_T_188,_T_187,_T_186}; // @[Cat.scala 29:58]
|
|
reg [31:0] q1; // @[el2_lib.scala 514:16]
|
|
reg [31:0] q0; // @[el2_lib.scala 514:16]
|
|
wire [63:0] _T_479 = {q1,q0}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_486 = qren[0] ? _T_479 : 64'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] q2; // @[el2_lib.scala 514:16]
|
|
wire [63:0] _T_482 = {q2,q1}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_487 = qren[1] ? _T_482 : 64'h0; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_489 = _T_486 | _T_487; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_485 = {q0,q2}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_488 = qren[2] ? _T_485 : 64'h0; // @[Mux.scala 27:72]
|
|
wire [63:0] qeff = _T_489 | _T_488; // @[Mux.scala 27:72]
|
|
wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 310:42]
|
|
wire [31:0] _T_496 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_497 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _GEN_0 = {{16'd0}, _T_497}; // @[Mux.scala 27:72]
|
|
wire [31:0] q0final = _T_496 | _GEN_0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_520 = f0val[1] ? q0final : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_513 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 316:58]
|
|
wire _T_515 = _T_513 & f0val[0]; // @[el2_ifu_aln_ctl.scala 316:68]
|
|
wire _T_197 = _T_186 & q1off; // @[Mux.scala 27:72]
|
|
wire _T_198 = _T_187 & q2off; // @[Mux.scala 27:72]
|
|
wire _T_200 = _T_197 | _T_198; // @[Mux.scala 27:72]
|
|
wire _T_199 = _T_188 & q0off; // @[Mux.scala 27:72]
|
|
wire q1ptr = _T_200 | _T_199; // @[Mux.scala 27:72]
|
|
wire _T_203 = ~q1ptr; // @[el2_ifu_aln_ctl.scala 196:26]
|
|
wire [1:0] q1sel = {q1ptr,_T_203}; // @[Cat.scala 29:58]
|
|
wire [31:0] q1eff = qeff[63:32]; // @[el2_ifu_aln_ctl.scala 310:29]
|
|
wire [15:0] _T_506 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_507 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] q1final = _T_506 | _T_507; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_519 = {q1final,q0final[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_521 = _T_515 ? _T_519 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] aligndata = _T_520 | _T_521; // @[Mux.scala 27:72]
|
|
wire first4B = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 348:29]
|
|
wire first2B = ~first4B; // @[el2_ifu_aln_ctl.scala 350:17]
|
|
wire shift_2B = i0_shift & first2B; // @[el2_ifu_aln_ctl.scala 412:24]
|
|
wire [1:0] _T_443 = {1'h0,f0val[1]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_448 = shift_2B ? _T_443 : 2'h0; // @[Mux.scala 27:72]
|
|
wire _T_444 = ~shift_2B; // @[el2_ifu_aln_ctl.scala 300:18]
|
|
wire shift_4B = i0_shift & first4B; // @[el2_ifu_aln_ctl.scala 413:24]
|
|
wire _T_445 = ~shift_4B; // @[el2_ifu_aln_ctl.scala 300:30]
|
|
wire _T_446 = _T_444 & _T_445; // @[el2_ifu_aln_ctl.scala 300:28]
|
|
wire [1:0] _T_449 = _T_446 ? f0val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] sf0val = _T_448 | _T_449; // @[Mux.scala 27:72]
|
|
wire sf0_valid = sf0val[0]; // @[el2_ifu_aln_ctl.scala 253:22]
|
|
wire _T_351 = ~sf0_valid; // @[el2_ifu_aln_ctl.scala 272:26]
|
|
wire _T_802 = f0val[0] & _T_513; // @[el2_ifu_aln_ctl.scala 416:28]
|
|
wire f1_shift_2B = _T_802 & shift_4B; // @[el2_ifu_aln_ctl.scala 416:40]
|
|
wire _T_417 = f1_shift_2B & f1val[1]; // @[Mux.scala 27:72]
|
|
wire _T_416 = ~f1_shift_2B; // @[el2_ifu_aln_ctl.scala 293:53]
|
|
wire [1:0] _T_418 = _T_416 ? f1val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_1 = {{1'd0}, _T_417}; // @[Mux.scala 27:72]
|
|
wire [1:0] sf1val = _GEN_1 | _T_418; // @[Mux.scala 27:72]
|
|
wire sf1_valid = sf1val[0]; // @[el2_ifu_aln_ctl.scala 252:22]
|
|
wire _T_352 = _T_351 & sf1_valid; // @[el2_ifu_aln_ctl.scala 272:37]
|
|
wire f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 251:20]
|
|
wire _T_353 = _T_352 & f2_valid; // @[el2_ifu_aln_ctl.scala 272:50]
|
|
wire ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 261:30]
|
|
wire _T_354 = _T_353 & ifvalid; // @[el2_ifu_aln_ctl.scala 272:62]
|
|
wire _T_355 = sf0_valid & sf1_valid; // @[el2_ifu_aln_ctl.scala 273:37]
|
|
wire _T_356 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 273:52]
|
|
wire _T_357 = _T_355 & _T_356; // @[el2_ifu_aln_ctl.scala 273:50]
|
|
wire _T_358 = _T_357 & ifvalid; // @[el2_ifu_aln_ctl.scala 273:62]
|
|
wire fetch_to_f2 = _T_354 | _T_358; // @[el2_ifu_aln_ctl.scala 272:74]
|
|
reg [30:0] f2pc; // @[el2_lib.scala 514:16]
|
|
wire _T_335 = ~sf1_valid; // @[el2_ifu_aln_ctl.scala 268:39]
|
|
wire _T_336 = _T_351 & _T_335; // @[el2_ifu_aln_ctl.scala 268:37]
|
|
wire _T_337 = _T_336 & f2_valid; // @[el2_ifu_aln_ctl.scala 268:50]
|
|
wire _T_338 = _T_337 & ifvalid; // @[el2_ifu_aln_ctl.scala 268:62]
|
|
wire _T_342 = _T_352 & _T_356; // @[el2_ifu_aln_ctl.scala 269:50]
|
|
wire _T_343 = _T_342 & ifvalid; // @[el2_ifu_aln_ctl.scala 269:62]
|
|
wire _T_344 = _T_338 | _T_343; // @[el2_ifu_aln_ctl.scala 268:74]
|
|
wire _T_346 = sf0_valid & _T_335; // @[el2_ifu_aln_ctl.scala 270:37]
|
|
wire _T_348 = _T_346 & _T_356; // @[el2_ifu_aln_ctl.scala 270:50]
|
|
wire _T_349 = _T_348 & ifvalid; // @[el2_ifu_aln_ctl.scala 270:62]
|
|
wire fetch_to_f1 = _T_344 | _T_349; // @[el2_ifu_aln_ctl.scala 269:74]
|
|
wire _T_25 = fetch_to_f1 | _T_353; // @[el2_ifu_aln_ctl.scala 157:33]
|
|
reg [30:0] f1pc; // @[el2_lib.scala 514:16]
|
|
wire _T_332 = _T_336 & _T_356; // @[el2_ifu_aln_ctl.scala 267:50]
|
|
wire fetch_to_f0 = _T_332 & ifvalid; // @[el2_ifu_aln_ctl.scala 267:62]
|
|
wire _T_27 = fetch_to_f0 | _T_337; // @[el2_ifu_aln_ctl.scala 158:33]
|
|
wire _T_28 = _T_27 | _T_352; // @[el2_ifu_aln_ctl.scala 158:47]
|
|
wire _T_29 = _T_28 | shift_2B; // @[el2_ifu_aln_ctl.scala 158:61]
|
|
reg [30:0] f0pc; // @[el2_lib.scala 514:16]
|
|
wire _T_35 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 161:21]
|
|
wire _T_36 = _T_35 & ifvalid; // @[el2_ifu_aln_ctl.scala 161:29]
|
|
wire _T_37 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 161:46]
|
|
wire _T_38 = _T_37 & ifvalid; // @[el2_ifu_aln_ctl.scala 161:54]
|
|
wire _T_39 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 161:71]
|
|
wire _T_40 = _T_39 & ifvalid; // @[el2_ifu_aln_ctl.scala 161:79]
|
|
wire [2:0] qwen = {_T_36,_T_38,_T_40}; // @[Cat.scala 29:58]
|
|
reg [11:0] brdata2; // @[el2_lib.scala 514:16]
|
|
reg [11:0] brdata1; // @[el2_lib.scala 514:16]
|
|
reg [11:0] brdata0; // @[el2_lib.scala 514:16]
|
|
reg [54:0] misc2; // @[el2_lib.scala 514:16]
|
|
reg [54:0] misc1; // @[el2_lib.scala 514:16]
|
|
reg [54:0] misc0; // @[el2_lib.scala 514:16]
|
|
wire _T_44 = qren[0] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 163:34]
|
|
wire _T_46 = _T_44 & _T_1; // @[el2_ifu_aln_ctl.scala 163:55]
|
|
wire _T_49 = qren[1] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 164:14]
|
|
wire _T_51 = _T_49 & _T_1; // @[el2_ifu_aln_ctl.scala 164:35]
|
|
wire _T_59 = qren[0] & io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 166:14]
|
|
wire _T_61 = _T_59 & _T_1; // @[el2_ifu_aln_ctl.scala 166:35]
|
|
wire _T_69 = qren[2] & io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 168:14]
|
|
wire _T_71 = _T_69 & _T_1; // @[el2_ifu_aln_ctl.scala 168:35]
|
|
wire _T_73 = ~io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 169:6]
|
|
wire _T_74 = ~io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 169:28]
|
|
wire _T_75 = _T_73 & _T_74; // @[el2_ifu_aln_ctl.scala 169:26]
|
|
wire _T_77 = _T_75 & _T_1; // @[el2_ifu_aln_ctl.scala 169:48]
|
|
wire [1:0] _T_80 = _T_51 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_82 = _T_61 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_85 = _T_77 ? rdptr : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_2 = {{1'd0}, _T_46}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_86 = _GEN_2 | _T_80; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_88 = _T_86 | _T_82; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_3 = {{1'd0}, _T_71}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_90 = _T_88 | _GEN_3; // @[Mux.scala 27:72]
|
|
wire _T_95 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 171:34]
|
|
wire _T_99 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 172:14]
|
|
wire _T_105 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 174:6]
|
|
wire _T_107 = _T_105 & _T_1; // @[el2_ifu_aln_ctl.scala 174:15]
|
|
wire [1:0] _T_110 = _T_99 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_112 = _T_107 ? wrptr : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_4 = {{1'd0}, _T_95}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_113 = _GEN_4 | _T_110; // @[Mux.scala 27:72]
|
|
wire _T_118 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 176:26]
|
|
wire _T_120 = _T_118 & _T_188; // @[el2_ifu_aln_ctl.scala 176:35]
|
|
wire _T_795 = shift_2B & f0val[0]; // @[Mux.scala 27:72]
|
|
wire _T_796 = shift_4B & _T_802; // @[Mux.scala 27:72]
|
|
wire f0_shift_2B = _T_795 | _T_796; // @[Mux.scala 27:72]
|
|
wire _T_122 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 176:74]
|
|
wire _T_126 = _T_118 & _T_187; // @[el2_ifu_aln_ctl.scala 177:15]
|
|
wire _T_128 = q2off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 177:54]
|
|
wire _T_132 = _T_118 & _T_186; // @[el2_ifu_aln_ctl.scala 178:15]
|
|
wire _T_134 = _T_120 & _T_122; // @[Mux.scala 27:72]
|
|
wire _T_135 = _T_126 & _T_128; // @[Mux.scala 27:72]
|
|
wire _T_136 = _T_132 & q2off; // @[Mux.scala 27:72]
|
|
wire _T_137 = _T_134 | _T_135; // @[Mux.scala 27:72]
|
|
wire _T_141 = ~qwen[1]; // @[el2_ifu_aln_ctl.scala 180:26]
|
|
wire _T_143 = _T_141 & _T_187; // @[el2_ifu_aln_ctl.scala 180:35]
|
|
wire _T_145 = q1off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 180:74]
|
|
wire _T_149 = _T_141 & _T_186; // @[el2_ifu_aln_ctl.scala 181:15]
|
|
wire _T_151 = q1off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 181:54]
|
|
wire _T_155 = _T_141 & _T_188; // @[el2_ifu_aln_ctl.scala 182:15]
|
|
wire _T_157 = _T_143 & _T_145; // @[Mux.scala 27:72]
|
|
wire _T_158 = _T_149 & _T_151; // @[Mux.scala 27:72]
|
|
wire _T_159 = _T_155 & q1off; // @[Mux.scala 27:72]
|
|
wire _T_160 = _T_157 | _T_158; // @[Mux.scala 27:72]
|
|
wire _T_164 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 184:26]
|
|
wire _T_166 = _T_164 & _T_186; // @[el2_ifu_aln_ctl.scala 184:35]
|
|
wire _T_168 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 184:76]
|
|
wire _T_172 = _T_164 & _T_188; // @[el2_ifu_aln_ctl.scala 185:35]
|
|
wire _T_174 = q0off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 185:76]
|
|
wire _T_178 = _T_164 & _T_187; // @[el2_ifu_aln_ctl.scala 186:35]
|
|
wire _T_180 = _T_166 & _T_168; // @[Mux.scala 27:72]
|
|
wire _T_181 = _T_172 & _T_174; // @[Mux.scala 27:72]
|
|
wire _T_182 = _T_178 & q0off; // @[Mux.scala 27:72]
|
|
wire _T_183 = _T_180 | _T_181; // @[Mux.scala 27:72]
|
|
wire [50:0] _T_205 = {io_ifu_bp_btb_target_f,io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_207 = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f}; // @[Cat.scala 29:58]
|
|
wire [109:0] _T_211 = {misc1,misc0}; // @[Cat.scala 29:58]
|
|
wire [109:0] _T_214 = {misc2,misc1}; // @[Cat.scala 29:58]
|
|
wire [109:0] _T_217 = {misc0,misc2}; // @[Cat.scala 29:58]
|
|
wire [109:0] _T_218 = qren[0] ? _T_211 : 110'h0; // @[Mux.scala 27:72]
|
|
wire [109:0] _T_219 = qren[1] ? _T_214 : 110'h0; // @[Mux.scala 27:72]
|
|
wire [109:0] _T_220 = qren[2] ? _T_217 : 110'h0; // @[Mux.scala 27:72]
|
|
wire [109:0] _T_221 = _T_218 | _T_219; // @[Mux.scala 27:72]
|
|
wire [109:0] misceff = _T_221 | _T_220; // @[Mux.scala 27:72]
|
|
wire [54:0] misc1eff = misceff[109:55]; // @[el2_ifu_aln_ctl.scala 205:25]
|
|
wire [54:0] misc0eff = misceff[54:0]; // @[el2_ifu_aln_ctl.scala 206:25]
|
|
wire f1dbecc = misc1eff[54]; // @[el2_ifu_aln_ctl.scala 209:25]
|
|
wire f1icaf = misc1eff[53]; // @[el2_ifu_aln_ctl.scala 210:21]
|
|
wire [1:0] f1ictype = misc1eff[52:51]; // @[el2_ifu_aln_ctl.scala 211:26]
|
|
wire [30:0] f1prett = misc1eff[50:20]; // @[el2_ifu_aln_ctl.scala 212:25]
|
|
wire [11:0] f1poffset = misc1eff[19:8]; // @[el2_ifu_aln_ctl.scala 213:27]
|
|
wire [7:0] f1fghr = misc1eff[7:0]; // @[el2_ifu_aln_ctl.scala 214:24]
|
|
wire f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 216:25]
|
|
wire f0icaf = misc0eff[53]; // @[el2_ifu_aln_ctl.scala 217:21]
|
|
wire [1:0] f0ictype = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 218:26]
|
|
wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 219:25]
|
|
wire [11:0] f0poffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 220:27]
|
|
wire [7:0] f0fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 221:24]
|
|
wire [5:0] _T_241 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58]
|
|
wire [5:0] _T_246 = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1]}; // @[Cat.scala 29:58]
|
|
wire [23:0] _T_250 = {brdata1,brdata0}; // @[Cat.scala 29:58]
|
|
wire [23:0] _T_253 = {brdata2,brdata1}; // @[Cat.scala 29:58]
|
|
wire [23:0] _T_256 = {brdata0,brdata2}; // @[Cat.scala 29:58]
|
|
wire [23:0] _T_257 = qren[0] ? _T_250 : 24'h0; // @[Mux.scala 27:72]
|
|
wire [23:0] _T_258 = qren[1] ? _T_253 : 24'h0; // @[Mux.scala 27:72]
|
|
wire [23:0] _T_259 = qren[2] ? _T_256 : 24'h0; // @[Mux.scala 27:72]
|
|
wire [23:0] _T_260 = _T_257 | _T_258; // @[Mux.scala 27:72]
|
|
wire [23:0] brdataeff = _T_260 | _T_259; // @[Mux.scala 27:72]
|
|
wire [11:0] brdata0eff = brdataeff[11:0]; // @[el2_ifu_aln_ctl.scala 231:43]
|
|
wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 231:61]
|
|
wire [11:0] _T_267 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_268 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _GEN_5 = {{6'd0}, _T_268}; // @[Mux.scala 27:72]
|
|
wire [11:0] brdata0final = _T_267 | _GEN_5; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_275 = q1sel[0] ? brdata1eff : 12'h0; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_276 = q1sel[1] ? brdata1eff[11:6] : 6'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _GEN_6 = {{6'd0}, _T_276}; // @[Mux.scala 27:72]
|
|
wire [11:0] brdata1final = _T_275 | _GEN_6; // @[Mux.scala 27:72]
|
|
wire [1:0] f0ret = {brdata0final[6],brdata0final[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0brend = {brdata0final[7],brdata0final[1]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0way = {brdata0final[8],brdata0final[2]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0pc4 = {brdata0final[9],brdata0final[3]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0hist0 = {brdata0final[10],brdata0final[4]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0hist1 = {brdata0final[11],brdata0final[5]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1ret = {brdata1final[6],brdata1final[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1brend = {brdata1final[7],brdata1final[1]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1way = {brdata1final[8],brdata1final[2]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1pc4 = {brdata1final[9],brdata1final[3]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1hist0 = {brdata1final[10],brdata1final[4]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1hist1 = {brdata1final[11],brdata1final[5]}; // @[Cat.scala 29:58]
|
|
wire consume_fb0 = _T_351 & f0val[0]; // @[el2_ifu_aln_ctl.scala 255:32]
|
|
wire consume_fb1 = _T_335 & f1val[0]; // @[el2_ifu_aln_ctl.scala 256:32]
|
|
wire _T_311 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 258:39]
|
|
wire _T_312 = consume_fb0 & _T_311; // @[el2_ifu_aln_ctl.scala 258:37]
|
|
wire _T_315 = consume_fb0 & consume_fb1; // @[el2_ifu_aln_ctl.scala 259:37]
|
|
wire [30:0] f0pc_plus1 = f0pc + 31'h1; // @[el2_ifu_aln_ctl.scala 275:25]
|
|
wire [30:0] f1pc_plus1 = f1pc + 31'h1; // @[el2_ifu_aln_ctl.scala 277:25]
|
|
wire [30:0] _T_363 = f1_shift_2B ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
|
|
wire [30:0] _T_364 = _T_363 & f1pc_plus1; // @[el2_ifu_aln_ctl.scala 279:38]
|
|
wire [30:0] _T_367 = _T_416 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
|
|
wire [30:0] _T_368 = _T_367 & f1pc; // @[el2_ifu_aln_ctl.scala 279:78]
|
|
wire [30:0] sf1pc = _T_364 | _T_368; // @[el2_ifu_aln_ctl.scala 279:52]
|
|
wire _T_371 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 283:6]
|
|
wire _T_372 = ~_T_353; // @[el2_ifu_aln_ctl.scala 283:21]
|
|
wire _T_373 = _T_371 & _T_372; // @[el2_ifu_aln_ctl.scala 283:19]
|
|
wire [30:0] _T_375 = fetch_to_f1 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_376 = _T_353 ? f2pc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_377 = _T_373 ? sf1pc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_378 = _T_375 | _T_376; // @[Mux.scala 27:72]
|
|
wire _T_384 = ~fetch_to_f0; // @[el2_ifu_aln_ctl.scala 288:24]
|
|
wire _T_385 = ~_T_337; // @[el2_ifu_aln_ctl.scala 288:39]
|
|
wire _T_386 = _T_384 & _T_385; // @[el2_ifu_aln_ctl.scala 288:37]
|
|
wire _T_387 = ~_T_352; // @[el2_ifu_aln_ctl.scala 288:54]
|
|
wire _T_388 = _T_386 & _T_387; // @[el2_ifu_aln_ctl.scala 288:52]
|
|
wire [30:0] _T_390 = fetch_to_f0 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_391 = _T_337 ? f2pc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_392 = _T_352 ? sf1pc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_393 = _T_388 ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_394 = _T_390 | _T_391; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_395 = _T_394 | _T_392; // @[Mux.scala 27:72]
|
|
wire _T_399 = fetch_to_f2 & _T_1; // @[el2_ifu_aln_ctl.scala 290:38]
|
|
wire _T_401 = ~fetch_to_f2; // @[el2_ifu_aln_ctl.scala 291:25]
|
|
wire _T_403 = _T_401 & _T_372; // @[el2_ifu_aln_ctl.scala 291:38]
|
|
wire _T_405 = _T_403 & _T_385; // @[el2_ifu_aln_ctl.scala 291:53]
|
|
wire _T_407 = _T_405 & _T_1; // @[el2_ifu_aln_ctl.scala 291:68]
|
|
wire [1:0] _T_409 = _T_399 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_410 = _T_407 ? f2val : 2'h0; // @[Mux.scala 27:72]
|
|
wire _T_422 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 295:39]
|
|
wire _T_425 = _T_353 & _T_1; // @[el2_ifu_aln_ctl.scala 296:54]
|
|
wire _T_431 = _T_373 & _T_387; // @[el2_ifu_aln_ctl.scala 297:54]
|
|
wire _T_433 = _T_431 & _T_1; // @[el2_ifu_aln_ctl.scala 297:69]
|
|
wire [1:0] _T_435 = _T_422 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_436 = _T_425 ? f2val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_437 = _T_433 ? sf1val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_438 = _T_435 | _T_436; // @[Mux.scala 27:72]
|
|
wire _T_453 = fetch_to_f0 & _T_1; // @[el2_ifu_aln_ctl.scala 302:38]
|
|
wire _T_456 = _T_337 & _T_1; // @[el2_ifu_aln_ctl.scala 303:54]
|
|
wire _T_459 = _T_352 & _T_1; // @[el2_ifu_aln_ctl.scala 304:69]
|
|
wire _T_467 = _T_388 & _T_1; // @[el2_ifu_aln_ctl.scala 305:69]
|
|
wire [1:0] _T_469 = _T_453 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_470 = _T_456 ? f2val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_471 = _T_459 ? sf1val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_472 = _T_467 ? sf0val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_473 = _T_469 | _T_470; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_474 = _T_473 | _T_471; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_530 = {f1val[0],1'h1}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_531 = f0val[1] ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_532 = _T_515 ? _T_530 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignval = _T_531 | _T_532; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_542 = {f1icaf,f0icaf}; // @[Cat.scala 29:58]
|
|
wire _T_543 = f0val[1] & f0icaf; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_544 = _T_515 ? _T_542 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_7 = {{1'd0}, _T_543}; // @[Mux.scala 27:72]
|
|
wire [1:0] alignicaf = _GEN_7 | _T_544; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_549 = f0dbecc ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_555 = {f1dbecc,f0dbecc}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_556 = f0val[1] ? _T_549 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_557 = _T_515 ? _T_555 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] aligndbecc = _T_556 | _T_557; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_568 = {f1brend[0],f0brend[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_569 = f0val[1] ? f0brend : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_570 = _T_515 ? _T_568 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignbrend = _T_569 | _T_570; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_581 = {f1pc4[0],f0pc4[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_582 = f0val[1] ? f0pc4 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_583 = _T_515 ? _T_581 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignpc4 = _T_582 | _T_583; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_594 = {f1ret[0],f0ret[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_595 = f0val[1] ? f0ret : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_596 = _T_515 ? _T_594 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignret = _T_595 | _T_596; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_607 = {f1way[0],f0way[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_608 = f0val[1] ? f0way : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_609 = _T_515 ? _T_607 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignway = _T_608 | _T_609; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_620 = {f1hist1[0],f0hist1[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_621 = f0val[1] ? f0hist1 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_622 = _T_515 ? _T_620 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignhist1 = _T_621 | _T_622; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_633 = {f1hist0[0],f0hist0[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_634 = f0val[1] ? f0hist0 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_635 = _T_515 ? _T_633 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignhist0 = _T_634 | _T_635; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_647 = f0val[1] ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_648 = _T_515 ? f1pc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] secondpc = _T_647 | _T_648; // @[Mux.scala 27:72]
|
|
wire _T_657 = first4B & alignval[1]; // @[Mux.scala 27:72]
|
|
wire _T_658 = first2B & alignval[0]; // @[Mux.scala 27:72]
|
|
wire _T_662 = |alignicaf; // @[el2_ifu_aln_ctl.scala 354:59]
|
|
wire _T_665 = first4B & _T_662; // @[Mux.scala 27:72]
|
|
wire _T_666 = first2B & alignicaf[0]; // @[Mux.scala 27:72]
|
|
wire _T_671 = first4B & _T_513; // @[el2_ifu_aln_ctl.scala 356:39]
|
|
wire _T_673 = _T_671 & f0val[0]; // @[el2_ifu_aln_ctl.scala 356:51]
|
|
wire _T_675 = ~alignicaf[0]; // @[el2_ifu_aln_ctl.scala 356:64]
|
|
wire _T_676 = _T_673 & _T_675; // @[el2_ifu_aln_ctl.scala 356:62]
|
|
wire _T_678 = ~aligndbecc[0]; // @[el2_ifu_aln_ctl.scala 356:80]
|
|
wire _T_679 = _T_676 & _T_678; // @[el2_ifu_aln_ctl.scala 356:78]
|
|
wire icaf_eff = alignicaf[1] | aligndbecc[1]; // @[el2_ifu_aln_ctl.scala 358:31]
|
|
wire _T_684 = first4B & icaf_eff; // @[el2_ifu_aln_ctl.scala 360:32]
|
|
wire _T_687 = |aligndbecc; // @[el2_ifu_aln_ctl.scala 362:59]
|
|
wire _T_690 = first4B & _T_687; // @[Mux.scala 27:72]
|
|
wire _T_691 = first2B & aligndbecc[0]; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_696 = first4B ? aligndata : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_697 = first2B ? decompressed_io_dout : 32'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_702 = f0pc[8:1] ^ f0pc[16:9]; // @[el2_lib.scala 191:47]
|
|
wire [7:0] firstpc_hash = _T_702 ^ f0pc[24:17]; // @[el2_lib.scala 191:85]
|
|
wire [7:0] _T_706 = secondpc[8:1] ^ secondpc[16:9]; // @[el2_lib.scala 191:47]
|
|
wire [7:0] secondpc_hash = _T_706 ^ secondpc[24:17]; // @[el2_lib.scala 191:85]
|
|
wire [4:0] _T_712 = f0pc[13:9] ^ f0pc[18:14]; // @[el2_lib.scala 182:111]
|
|
wire [4:0] firstbrtag_hash = _T_712 ^ f0pc[23:19]; // @[el2_lib.scala 182:111]
|
|
wire [4:0] _T_717 = secondpc[13:9] ^ secondpc[18:14]; // @[el2_lib.scala 182:111]
|
|
wire [4:0] secondbrtag_hash = _T_717 ^ secondpc[23:19]; // @[el2_lib.scala 182:111]
|
|
wire _T_719 = first2B & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:30]
|
|
wire _T_721 = first4B & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 378:58]
|
|
wire _T_722 = _T_719 | _T_721; // @[el2_ifu_aln_ctl.scala 378:47]
|
|
wire _T_726 = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:100]
|
|
wire _T_729 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:29]
|
|
wire _T_731 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:55]
|
|
wire _T_734 = first2B & alignpc4[0]; // @[el2_ifu_aln_ctl.scala 382:29]
|
|
wire _T_736 = first4B & alignpc4[1]; // @[el2_ifu_aln_ctl.scala 382:55]
|
|
wire i0_brp_pc4 = _T_734 | _T_736; // @[el2_ifu_aln_ctl.scala 382:44]
|
|
wire _T_738 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:33]
|
|
wire _T_744 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:34]
|
|
wire _T_746 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:62]
|
|
wire _T_747 = _T_744 | _T_746; // @[el2_ifu_aln_ctl.scala 386:51]
|
|
wire _T_749 = first2B & alignhist0[0]; // @[el2_ifu_aln_ctl.scala 387:14]
|
|
wire _T_751 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 387:42]
|
|
wire _T_752 = _T_749 | _T_751; // @[el2_ifu_aln_ctl.scala 387:31]
|
|
wire i0_ends_f1 = first4B & _T_515; // @[el2_ifu_aln_ctl.scala 389:28]
|
|
wire _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:42]
|
|
wire _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:56]
|
|
wire _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:89]
|
|
wire _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:87]
|
|
wire _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:101]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en),
|
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en),
|
|
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_8_io_l1clk),
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en),
|
|
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_9_io_l1clk),
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en),
|
|
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_10_io_l1clk),
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en),
|
|
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_11_io_l1clk),
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en),
|
|
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
|
);
|
|
el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 366:28]
|
|
.io_din(decompressed_io_din),
|
|
.io_dout(decompressed_io_dout)
|
|
);
|
|
assign io_ifu_i0_valid = _T_657 | _T_658; // @[el2_ifu_aln_ctl.scala 47:19 el2_ifu_aln_ctl.scala 352:19]
|
|
assign io_ifu_i0_icaf = _T_665 | _T_666; // @[el2_ifu_aln_ctl.scala 48:18 el2_ifu_aln_ctl.scala 354:18]
|
|
assign io_ifu_i0_icaf_type = _T_679 ? f1ictype : f0ictype; // @[el2_ifu_aln_ctl.scala 49:23 el2_ifu_aln_ctl.scala 356:23]
|
|
assign io_ifu_i0_icaf_f1 = _T_684 & _T_515; // @[el2_ifu_aln_ctl.scala 50:21 el2_ifu_aln_ctl.scala 360:21]
|
|
assign io_ifu_i0_dbecc = _T_690 | _T_691; // @[el2_ifu_aln_ctl.scala 51:19 el2_ifu_aln_ctl.scala 362:19]
|
|
assign io_ifu_i0_instr = _T_696 | _T_697; // @[el2_ifu_aln_ctl.scala 52:19 el2_ifu_aln_ctl.scala 368:19]
|
|
assign io_ifu_i0_pc = f0pc; // @[el2_ifu_aln_ctl.scala 53:16 el2_ifu_aln_ctl.scala 340:16]
|
|
assign io_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 54:17 el2_ifu_aln_ctl.scala 344:17]
|
|
assign io_ifu_fb_consume1 = _T_312 & _T_1; // @[el2_ifu_aln_ctl.scala 55:22 el2_ifu_aln_ctl.scala 258:22]
|
|
assign io_ifu_fb_consume2 = _T_315 & _T_1; // @[el2_ifu_aln_ctl.scala 56:22 el2_ifu_aln_ctl.scala 259:22]
|
|
assign io_ifu_i0_bp_index = _T_738 ? firstpc_hash : secondpc_hash; // @[el2_ifu_aln_ctl.scala 57:22 el2_ifu_aln_ctl.scala 400:22]
|
|
assign io_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : f0fghr; // @[el2_ifu_aln_ctl.scala 58:21 el2_ifu_aln_ctl.scala 402:21]
|
|
assign io_ifu_i0_bp_btag = _T_738 ? firstbrtag_hash : secondbrtag_hash; // @[el2_ifu_aln_ctl.scala 59:21 el2_ifu_aln_ctl.scala 404:21]
|
|
assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_785; // @[el2_ifu_aln_ctl.scala 60:28 el2_ifu_aln_ctl.scala 410:28]
|
|
assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 61:19 el2_ifu_aln_ctl.scala 346:19]
|
|
assign io_i0_brp_valid = _T_722 | _T_726; // @[el2_ifu_aln_ctl.scala 378:19]
|
|
assign io_i0_brp_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:21]
|
|
assign io_i0_brp_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:18]
|
|
assign io_i0_brp_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:22]
|
|
assign io_i0_brp_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29]
|
|
assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:19]
|
|
assign io_i0_brp_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17]
|
|
assign io_i0_brp_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:17]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = _T_354 | _T_358; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = _T_25 | f1_shift_2B; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_2_io_en = _T_29 | shift_4B; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = qwen[2]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_4_io_en = qwen[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_5_io_en = qwen[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_6_io_en = qwen[2]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_7_io_en = qwen[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_8_io_en = qwen[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_9_io_en = qwen[2]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_10_io_en = qwen[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_11_io_en = qwen[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 406:23]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
error_stall = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
wrptr = _RAND_1[1:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
rdptr = _RAND_2[1:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
f2val = _RAND_3[1:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
f1val = _RAND_4[1:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
f0val = _RAND_5[1:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
q2off = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
q1off = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
q0off = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
q1 = _RAND_9[31:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
q0 = _RAND_10[31:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
q2 = _RAND_11[31:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
f2pc = _RAND_12[30:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
f1pc = _RAND_13[30:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
f0pc = _RAND_14[30:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
brdata2 = _RAND_15[11:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
brdata1 = _RAND_16[11:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
brdata0 = _RAND_17[11:0];
|
|
_RAND_18 = {2{`RANDOM}};
|
|
misc2 = _RAND_18[54:0];
|
|
_RAND_19 = {2{`RANDOM}};
|
|
misc1 = _RAND_19[54:0];
|
|
_RAND_20 = {2{`RANDOM}};
|
|
misc0 = _RAND_20[54:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
error_stall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
wrptr = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
rdptr = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
f2val = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
f1val = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
f0val = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
q2off = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
q1off = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
q0off = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
q1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
q0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
q2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
f2pc = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
f1pc = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
f0pc = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
brdata2 = 12'h0;
|
|
end
|
|
if (reset) begin
|
|
brdata1 = 12'h0;
|
|
end
|
|
if (reset) begin
|
|
brdata0 = 12'h0;
|
|
end
|
|
if (reset) begin
|
|
misc2 = 55'h0;
|
|
end
|
|
if (reset) begin
|
|
misc1 = 55'h0;
|
|
end
|
|
if (reset) begin
|
|
misc0 = 55'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
error_stall <= 1'h0;
|
|
end else begin
|
|
error_stall <= _T & _T_1;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
wrptr <= 2'h0;
|
|
end else begin
|
|
wrptr <= _T_113 | _T_112;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
rdptr <= 2'h0;
|
|
end else begin
|
|
rdptr <= _T_90 | _T_85;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
f2val <= 2'h0;
|
|
end else begin
|
|
f2val <= _T_409 | _T_410;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
f1val <= 2'h0;
|
|
end else begin
|
|
f1val <= _T_438 | _T_437;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
f0val <= 2'h0;
|
|
end else begin
|
|
f0val <= _T_474 | _T_472;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
q2off <= 1'h0;
|
|
end else begin
|
|
q2off <= _T_137 | _T_136;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
q1off <= 1'h0;
|
|
end else begin
|
|
q1off <= _T_160 | _T_159;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
q0off <= 1'h0;
|
|
end else begin
|
|
q0off <= _T_183 | _T_182;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
q1 <= 32'h0;
|
|
end else begin
|
|
q1 <= io_ifu_fetch_data_f;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
q0 <= 32'h0;
|
|
end else begin
|
|
q0 <= io_ifu_fetch_data_f;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
q2 <= 32'h0;
|
|
end else begin
|
|
q2 <= io_ifu_fetch_data_f;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
f2pc <= 31'h0;
|
|
end else begin
|
|
f2pc <= io_ifu_fetch_pc;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
f1pc <= 31'h0;
|
|
end else begin
|
|
f1pc <= _T_378 | _T_377;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
f0pc <= 31'h0;
|
|
end else begin
|
|
f0pc <= _T_395 | _T_393;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
brdata2 <= 12'h0;
|
|
end else begin
|
|
brdata2 <= {_T_246,_T_241};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
brdata1 <= 12'h0;
|
|
end else begin
|
|
brdata1 <= {_T_246,_T_241};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
brdata0 <= 12'h0;
|
|
end else begin
|
|
brdata0 <= {_T_246,_T_241};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
misc2 <= 55'h0;
|
|
end else begin
|
|
misc2 <= {_T_207,_T_205};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
misc1 <= 55'h0;
|
|
end else begin
|
|
misc1 <= {_T_207,_T_205};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
misc0 <= 55'h0;
|
|
end else begin
|
|
misc0 <= {_T_207,_T_205};
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_ifu_ifc_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_free_clk,
|
|
input io_active_clk,
|
|
input io_scan_mode,
|
|
input io_ic_hit_f,
|
|
input io_ifu_ic_mb_empty,
|
|
input io_ifu_fb_consume1,
|
|
input io_ifu_fb_consume2,
|
|
input io_dec_tlu_flush_noredir_wb,
|
|
input io_exu_flush_final,
|
|
input [30:0] io_exu_flush_path_final,
|
|
input io_ifu_bp_hit_taken_f,
|
|
input [30:0] io_ifu_bp_btb_target_f,
|
|
input io_ic_dma_active,
|
|
input io_ic_write_stall,
|
|
input io_dma_iccm_stall_any,
|
|
input [31:0] io_dec_tlu_mrac_ff,
|
|
output [30:0] io_ifc_fetch_addr_f,
|
|
output [30:0] io_ifc_fetch_addr_bf,
|
|
output io_ifc_fetch_req_f,
|
|
output io_ifu_pmu_fetch_stall,
|
|
output io_ifc_fetch_uncacheable_bf,
|
|
output io_ifc_fetch_req_bf,
|
|
output io_ifc_fetch_req_bf_raw,
|
|
output io_ifc_iccm_access_bf,
|
|
output io_ifc_region_acc_fault_bf,
|
|
output io_ifc_dma_access_ok
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 63:58]
|
|
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 62:36]
|
|
reg miss_a; // @[el2_ifu_ifc_ctl.scala 65:44]
|
|
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 67:26]
|
|
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 67:49]
|
|
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 67:71]
|
|
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctl.scala 67:69]
|
|
wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctl.scala 67:46]
|
|
wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 68:46]
|
|
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 68:67]
|
|
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 68:92]
|
|
wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 69:69]
|
|
wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctl.scala 69:67]
|
|
wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 69:92]
|
|
wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
|
|
wire _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63]
|
|
wire _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24]
|
|
wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109]
|
|
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
|
|
wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
|
|
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:45]
|
|
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 119:17]
|
|
wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
|
|
wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctl.scala 84:70]
|
|
wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
|
wire _T_81 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
|
|
wire _T_82 = io_ifu_fb_consume1 & _T_81; // @[el2_ifu_ifc_ctl.scala 106:36]
|
|
wire _T_48 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
|
|
wire miss_f = _T_48 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
|
|
wire _T_84 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
|
|
wire _T_85 = _T_82 & _T_84; // @[el2_ifu_ifc_ctl.scala 106:58]
|
|
wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
|
|
wire fb_right = _T_85 | _T_86; // @[el2_ifu_ifc_ctl.scala 106:92]
|
|
wire _T_98 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
|
|
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 124:50]
|
|
wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72]
|
|
wire fb_right2 = io_ifu_fb_consume2 & _T_84; // @[el2_ifu_ifc_ctl.scala 109:36]
|
|
wire _T_103 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
|
|
wire [3:0] _T_106 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_123 = _T_103 ? _T_106 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72]
|
|
wire _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
|
|
wire _T_92 = ~_T_91; // @[el2_ifu_ifc_ctl.scala 110:35]
|
|
wire _T_93 = io_ifc_fetch_req_f & _T_92; // @[el2_ifu_ifc_ctl.scala 110:33]
|
|
wire _T_94 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
|
|
wire fb_left = _T_93 & _T_94; // @[el2_ifu_ifc_ctl.scala 110:78]
|
|
wire _T_108 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
|
|
wire [3:0] _T_111 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_124 = _T_108 ? _T_111 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
|
|
wire _T_113 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
|
|
wire _T_114 = _T_2 & _T_113; // @[el2_ifu_ifc_ctl.scala 116:16]
|
|
wire _T_115 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
|
|
wire _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctl.scala 116:28]
|
|
wire _T_117 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
|
|
wire _T_118 = _T_116 & _T_117; // @[el2_ifu_ifc_ctl.scala 116:41]
|
|
wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72]
|
|
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 122:30]
|
|
wire _T_37 = fb_full_f_ns & _T_36; // @[el2_ifu_ifc_ctl.scala 84:68]
|
|
wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctl.scala 84:53]
|
|
wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[el2_ifu_ifc_ctl.scala 84:51]
|
|
wire _T_40 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
|
|
wire _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctl.scala 84:114]
|
|
wire _T_42 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
|
|
wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctl.scala 85:16]
|
|
wire _T_44 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
|
|
wire _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
|
|
wire _T_53 = _T_51 & _T_40; // @[el2_ifu_ifc_ctl.scala 91:61]
|
|
wire _T_55 = _T_53 & _T_94; // @[el2_ifu_ifc_ctl.scala 91:74]
|
|
wire _T_56 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
|
|
wire mb_empty_mod = _T_55 & _T_56; // @[el2_ifu_ifc_ctl.scala 91:84]
|
|
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 93:35]
|
|
wire _T_60 = io_exu_flush_final & _T_44; // @[el2_ifu_ifc_ctl.scala 95:36]
|
|
wire leave_idle = _T_60 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
|
|
wire _T_63 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
|
|
wire _T_65 = _T_63 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
|
|
wire _T_66 = _T_65 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
|
|
wire _T_67 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
|
|
wire _T_68 = _T_66 & _T_67; // @[el2_ifu_ifc_ctl.scala 97:53]
|
|
wire _T_70 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
|
|
wire _T_71 = state[1] & _T_70; // @[el2_ifu_ifc_ctl.scala 98:15]
|
|
wire _T_73 = _T_71 & _T_67; // @[el2_ifu_ifc_ctl.scala 98:31]
|
|
wire next_state_1 = _T_68 | _T_73; // @[el2_ifu_ifc_ctl.scala 97:67]
|
|
wire _T_75 = _T_67 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
|
|
wire _T_78 = state[0] & _T_67; // @[el2_ifu_ifc_ctl.scala 100:60]
|
|
wire next_state_0 = _T_75 | _T_78; // @[el2_ifu_ifc_ctl.scala 100:48]
|
|
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 120:16]
|
|
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 123:52]
|
|
wire _T_136 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 127:61]
|
|
wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctl.scala 127:19]
|
|
wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctl.scala 127:17]
|
|
wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctl.scala 127:84]
|
|
wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctl.scala 126:60]
|
|
wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
|
wire iccm_acc_in_region_bf = _T_142[31:28] == 4'he; // @[el2_lib.scala 224:47]
|
|
wire iccm_acc_in_range_bf = _T_142[31:16] == 16'hee00; // @[el2_lib.scala 227:29]
|
|
wire _T_145 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 133:30]
|
|
wire _T_148 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 134:16]
|
|
wire _T_149 = _T_145 | _T_148; // @[el2_ifu_ifc_ctl.scala 133:53]
|
|
wire _T_150 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 135:13]
|
|
wire _T_151 = wfm & _T_150; // @[el2_ifu_ifc_ctl.scala 135:11]
|
|
wire _T_152 = _T_149 | _T_151; // @[el2_ifu_ifc_ctl.scala 134:62]
|
|
wire _T_153 = _T_152 | idle; // @[el2_ifu_ifc_ctl.scala 135:35]
|
|
wire _T_155 = _T_153 & _T_2; // @[el2_ifu_ifc_ctl.scala 135:44]
|
|
wire _T_157 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 137:33]
|
|
wire [4:0] _T_160 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_161 = io_dec_tlu_mrac_ff >> _T_160; // @[el2_ifu_ifc_ctl.scala 138:53]
|
|
reg _T_164; // @[el2_ifu_ifc_ctl.scala 140:57]
|
|
reg [30:0] _T_166; // @[el2_lib.scala 514:16]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
assign io_ifc_fetch_addr_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:23]
|
|
assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24]
|
|
assign io_ifc_fetch_req_f = _T_164; // @[el2_ifu_ifc_ctl.scala 140:22]
|
|
assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctl.scala 126:26]
|
|
assign io_ifc_fetch_uncacheable_bf = ~_T_161[0]; // @[el2_ifu_ifc_ctl.scala 138:31]
|
|
assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[el2_ifu_ifc_ctl.scala 84:23]
|
|
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 82:27]
|
|
assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 132:25]
|
|
assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 137:30]
|
|
assign io_ifc_dma_access_ok = _T_155 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 133:24]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
dma_iccm_stall_any_f = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
miss_a = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
state = _RAND_2[1:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
fb_write_f = _RAND_3[3:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
fb_full_f = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_164 = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_166 = _RAND_6[30:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
dma_iccm_stall_any_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
miss_a = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
state = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fb_write_f = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
fb_full_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_164 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_166 = 31'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_iccm_stall_any_f <= 1'h0;
|
|
end else begin
|
|
dma_iccm_stall_any_f <= io_dma_iccm_stall_any;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
miss_a <= 1'h0;
|
|
end else begin
|
|
miss_a <= _T_48 & _T_2;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
state <= 2'h0;
|
|
end else begin
|
|
state <= {next_state_1,next_state_0};
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fb_write_f <= 4'h0;
|
|
end else begin
|
|
fb_write_f <= _T_128 | _T_125;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fb_full_f <= 1'h0;
|
|
end else begin
|
|
fb_full_f <= fb_write_ns[3];
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_164 <= 1'h0;
|
|
end else begin
|
|
_T_164 <= io_ifc_fetch_req_bf;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_166 <= 31'h0;
|
|
end else begin
|
|
_T_166 <= io_ifc_fetch_addr_bf;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_ifu(
|
|
input clock,
|
|
input reset,
|
|
input io_free_clk,
|
|
input io_active_clk,
|
|
input io_dec_i0_decode_d,
|
|
input io_exu_flush_final,
|
|
input io_dec_tlu_i0_commit_cmt,
|
|
input io_dec_tlu_flush_err_wb,
|
|
input io_dec_tlu_flush_noredir_wb,
|
|
input [30:0] io_exu_flush_path_final,
|
|
input [31:0] io_dec_tlu_mrac_ff,
|
|
input io_dec_tlu_fence_i_wb,
|
|
input io_dec_tlu_flush_leak_one_wb,
|
|
input io_dec_tlu_bpred_disable,
|
|
input io_dec_tlu_core_ecc_disable,
|
|
input io_dec_tlu_force_halt,
|
|
output io_ifu_axi_arvalid,
|
|
input io_ifu_axi_arready,
|
|
output [2:0] io_ifu_axi_arid,
|
|
output [31:0] io_ifu_axi_araddr,
|
|
output [3:0] io_ifu_axi_arregion,
|
|
input io_ifu_axi_rvalid,
|
|
input [2:0] io_ifu_axi_rid,
|
|
input [63:0] io_ifu_axi_rdata,
|
|
input [1:0] io_ifu_axi_rresp,
|
|
input io_ifu_bus_clk_en,
|
|
input io_dma_iccm_req,
|
|
input [31:0] io_dma_mem_addr,
|
|
input [2:0] io_dma_mem_sz,
|
|
input io_dma_mem_write,
|
|
input [63:0] io_dma_mem_wdata,
|
|
input [2:0] io_dma_mem_tag,
|
|
input io_dma_iccm_stall_any,
|
|
output io_iccm_dma_ecc_error,
|
|
output io_iccm_dma_rvalid,
|
|
output [63:0] io_iccm_dma_rdata,
|
|
output [2:0] io_iccm_dma_rtag,
|
|
output io_iccm_ready,
|
|
output io_ifu_pmu_instr_aligned,
|
|
output io_ifu_pmu_fetch_stall,
|
|
output io_ifu_ic_error_start,
|
|
output [30:0] io_ic_rw_addr,
|
|
output [1:0] io_ic_wr_en,
|
|
output io_ic_rd_en,
|
|
output [70:0] io_ic_wr_data_0,
|
|
output [70:0] io_ic_wr_data_1,
|
|
input [63:0] io_ic_rd_data,
|
|
input [70:0] io_ic_debug_rd_data,
|
|
input [25:0] io_ictag_debug_rd_data,
|
|
output [70:0] io_ic_debug_wr_data,
|
|
output [70:0] io_ifu_ic_debug_rd_data,
|
|
input [1:0] io_ic_eccerr,
|
|
output [63:0] io_ic_premux_data,
|
|
output io_ic_sel_premux_data,
|
|
output [9:0] io_ic_debug_addr,
|
|
output io_ic_debug_rd_en,
|
|
output io_ic_debug_wr_en,
|
|
output io_ic_debug_tag_array,
|
|
output [1:0] io_ic_debug_way,
|
|
output [1:0] io_ic_tag_valid,
|
|
input [1:0] io_ic_rd_hit,
|
|
input io_ic_tag_perr,
|
|
output [14:0] io_iccm_rw_addr,
|
|
output io_iccm_wren,
|
|
output io_iccm_rden,
|
|
output [77:0] io_iccm_wr_data,
|
|
output [2:0] io_iccm_wr_size,
|
|
input [63:0] io_iccm_rd_data,
|
|
input [77:0] io_iccm_rd_data_ecc,
|
|
output io_ifu_iccm_rd_ecc_single_err,
|
|
output io_ifu_pmu_ic_miss,
|
|
output io_ifu_pmu_ic_hit,
|
|
output io_ifu_pmu_bus_error,
|
|
output io_ifu_pmu_bus_busy,
|
|
output io_ifu_pmu_bus_trxn,
|
|
output io_ifu_i0_icaf,
|
|
output [1:0] io_ifu_i0_icaf_type,
|
|
output io_ifu_i0_valid,
|
|
output io_ifu_i0_icaf_f1,
|
|
output io_ifu_i0_dbecc,
|
|
output io_iccm_dma_sb_error,
|
|
output [31:0] io_ifu_i0_instr,
|
|
output [30:0] io_ifu_i0_pc,
|
|
output io_ifu_i0_pc4,
|
|
output io_ifu_miss_state_idle,
|
|
output io_i0_brp_valid,
|
|
output [11:0] io_i0_brp_toffset,
|
|
output [1:0] io_i0_brp_hist,
|
|
output io_i0_brp_br_error,
|
|
output io_i0_brp_br_start_error,
|
|
output [30:0] io_i0_brp_prett,
|
|
output io_i0_brp_way,
|
|
output io_i0_brp_ret,
|
|
output [7:0] io_ifu_i0_bp_index,
|
|
output [7:0] io_ifu_i0_bp_fghr,
|
|
output [4:0] io_ifu_i0_bp_btag,
|
|
input io_exu_mp_pkt_bits_misp,
|
|
input io_exu_mp_pkt_bits_ataken,
|
|
input io_exu_mp_pkt_bits_boffset,
|
|
input io_exu_mp_pkt_bits_pc4,
|
|
input [1:0] io_exu_mp_pkt_bits_hist,
|
|
input [11:0] io_exu_mp_pkt_bits_toffset,
|
|
input io_exu_mp_pkt_bits_pcall,
|
|
input io_exu_mp_pkt_bits_pret,
|
|
input io_exu_mp_pkt_bits_pja,
|
|
input io_exu_mp_pkt_bits_way,
|
|
input [7:0] io_exu_mp_eghr,
|
|
input [7:0] io_exu_mp_fghr,
|
|
input [7:0] io_exu_mp_index,
|
|
input [4:0] io_exu_mp_btag,
|
|
input io_dec_tlu_br0_r_pkt_valid,
|
|
input [1:0] io_dec_tlu_br0_r_pkt_hist,
|
|
input io_dec_tlu_br0_r_pkt_br_error,
|
|
input io_dec_tlu_br0_r_pkt_br_start_error,
|
|
input io_dec_tlu_br0_r_pkt_way,
|
|
input io_dec_tlu_br0_r_pkt_middle,
|
|
input [7:0] io_exu_i0_br_fghr_r,
|
|
input [7:0] io_exu_i0_br_index_r,
|
|
input io_dec_tlu_flush_lower_wb,
|
|
output [15:0] io_ifu_i0_cinst,
|
|
input [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata,
|
|
input [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics,
|
|
input io_dec_tlu_ic_diag_pkt_icache_rd_valid,
|
|
input io_dec_tlu_ic_diag_pkt_icache_wr_valid,
|
|
output io_ifu_ic_debug_rd_data_valid,
|
|
output io_iccm_buf_correct_ecc,
|
|
output io_iccm_correction_state,
|
|
input io_scan_mode
|
|
);
|
|
wire mem_ctl_ch_clock; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_reset; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_free_clk; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_active_clk; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_exu_flush_final; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_dec_tlu_flush_err_wb; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_dec_tlu_i0_commit_cmt; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_dec_tlu_force_halt; // @[el2_ifu.scala 146:26]
|
|
wire [30:0] mem_ctl_ch_io_ifc_fetch_addr_bf; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifc_fetch_uncacheable_bf; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifc_fetch_req_bf; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifc_fetch_req_bf_raw; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifc_iccm_access_bf; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifc_region_acc_fault_bf; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifc_dma_access_ok; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_dec_tlu_fence_i_wb; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_bp_hit_taken_f; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_bp_inst_mask_f; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_axi_arready; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_axi_rvalid; // @[el2_ifu.scala 146:26]
|
|
wire [2:0] mem_ctl_ch_io_ifu_axi_rid; // @[el2_ifu.scala 146:26]
|
|
wire [63:0] mem_ctl_ch_io_ifu_axi_rdata; // @[el2_ifu.scala 146:26]
|
|
wire [1:0] mem_ctl_ch_io_ifu_axi_rresp; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_bus_clk_en; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_dma_iccm_req; // @[el2_ifu.scala 146:26]
|
|
wire [31:0] mem_ctl_ch_io_dma_mem_addr; // @[el2_ifu.scala 146:26]
|
|
wire [2:0] mem_ctl_ch_io_dma_mem_sz; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_dma_mem_write; // @[el2_ifu.scala 146:26]
|
|
wire [63:0] mem_ctl_ch_io_dma_mem_wdata; // @[el2_ifu.scala 146:26]
|
|
wire [2:0] mem_ctl_ch_io_dma_mem_tag; // @[el2_ifu.scala 146:26]
|
|
wire [63:0] mem_ctl_ch_io_ic_rd_data; // @[el2_ifu.scala 146:26]
|
|
wire [70:0] mem_ctl_ch_io_ic_debug_rd_data; // @[el2_ifu.scala 146:26]
|
|
wire [25:0] mem_ctl_ch_io_ictag_debug_rd_data; // @[el2_ifu.scala 146:26]
|
|
wire [1:0] mem_ctl_ch_io_ic_eccerr; // @[el2_ifu.scala 146:26]
|
|
wire [1:0] mem_ctl_ch_io_ic_rd_hit; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ic_tag_perr; // @[el2_ifu.scala 146:26]
|
|
wire [63:0] mem_ctl_ch_io_iccm_rd_data; // @[el2_ifu.scala 146:26]
|
|
wire [77:0] mem_ctl_ch_io_iccm_rd_data_ecc; // @[el2_ifu.scala 146:26]
|
|
wire [1:0] mem_ctl_ch_io_ifu_fetch_val; // @[el2_ifu.scala 146:26]
|
|
wire [70:0] mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu.scala 146:26]
|
|
wire [16:0] mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_miss_state_idle; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_ic_mb_empty; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ic_dma_active; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ic_write_stall; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_pmu_ic_miss; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_pmu_ic_hit; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_pmu_bus_error; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_pmu_bus_busy; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_pmu_bus_trxn; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_axi_arvalid; // @[el2_ifu.scala 146:26]
|
|
wire [2:0] mem_ctl_ch_io_ifu_axi_arid; // @[el2_ifu.scala 146:26]
|
|
wire [31:0] mem_ctl_ch_io_ifu_axi_araddr; // @[el2_ifu.scala 146:26]
|
|
wire [3:0] mem_ctl_ch_io_ifu_axi_arregion; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_axi_rready; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_iccm_dma_ecc_error; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_iccm_dma_rvalid; // @[el2_ifu.scala 146:26]
|
|
wire [63:0] mem_ctl_ch_io_iccm_dma_rdata; // @[el2_ifu.scala 146:26]
|
|
wire [2:0] mem_ctl_ch_io_iccm_dma_rtag; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_iccm_ready; // @[el2_ifu.scala 146:26]
|
|
wire [30:0] mem_ctl_ch_io_ic_rw_addr; // @[el2_ifu.scala 146:26]
|
|
wire [1:0] mem_ctl_ch_io_ic_wr_en; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ic_rd_en; // @[el2_ifu.scala 146:26]
|
|
wire [70:0] mem_ctl_ch_io_ic_wr_data_0; // @[el2_ifu.scala 146:26]
|
|
wire [70:0] mem_ctl_ch_io_ic_wr_data_1; // @[el2_ifu.scala 146:26]
|
|
wire [70:0] mem_ctl_ch_io_ic_debug_wr_data; // @[el2_ifu.scala 146:26]
|
|
wire [70:0] mem_ctl_ch_io_ifu_ic_debug_rd_data; // @[el2_ifu.scala 146:26]
|
|
wire [9:0] mem_ctl_ch_io_ic_debug_addr; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ic_debug_rd_en; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ic_debug_wr_en; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ic_debug_tag_array; // @[el2_ifu.scala 146:26]
|
|
wire [1:0] mem_ctl_ch_io_ic_debug_way; // @[el2_ifu.scala 146:26]
|
|
wire [1:0] mem_ctl_ch_io_ic_tag_valid; // @[el2_ifu.scala 146:26]
|
|
wire [14:0] mem_ctl_ch_io_iccm_rw_addr; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_iccm_wren; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_iccm_rden; // @[el2_ifu.scala 146:26]
|
|
wire [77:0] mem_ctl_ch_io_iccm_wr_data; // @[el2_ifu.scala 146:26]
|
|
wire [2:0] mem_ctl_ch_io_iccm_wr_size; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ic_hit_f; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ic_access_fault_f; // @[el2_ifu.scala 146:26]
|
|
wire [1:0] mem_ctl_ch_io_ic_access_fault_type_f; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_iccm_rd_ecc_single_err; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_iccm_rd_ecc_double_err; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ic_error_start; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_async_error_start; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_iccm_dma_sb_error; // @[el2_ifu.scala 146:26]
|
|
wire [1:0] mem_ctl_ch_io_ic_fetch_val_f; // @[el2_ifu.scala 146:26]
|
|
wire [31:0] mem_ctl_ch_io_ic_data_f; // @[el2_ifu.scala 146:26]
|
|
wire [63:0] mem_ctl_ch_io_ic_premux_data; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ic_sel_premux_data; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_dec_tlu_core_ecc_disable; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_ifu_ic_debug_rd_data_valid; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_iccm_buf_correct_ecc; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_iccm_correction_state; // @[el2_ifu.scala 146:26]
|
|
wire mem_ctl_ch_io_scan_mode; // @[el2_ifu.scala 146:26]
|
|
wire bp_ctl_ch_clock; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_reset; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_active_clk; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_ic_hit_f; // @[el2_ifu.scala 147:25]
|
|
wire [30:0] bp_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 147:25]
|
|
wire [1:0] bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 147:25]
|
|
wire [7:0] bp_ctl_ch_io_exu_i0_br_fghr_r; // @[el2_ifu.scala 147:25]
|
|
wire [7:0] bp_ctl_ch_io_exu_i0_br_index_r; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_dec_tlu_flush_leak_one_wb; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_dec_tlu_bpred_disable; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_exu_mp_pkt_bits_misp; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_exu_mp_pkt_bits_ataken; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_exu_mp_pkt_bits_boffset; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_exu_mp_pkt_bits_pc4; // @[el2_ifu.scala 147:25]
|
|
wire [1:0] bp_ctl_ch_io_exu_mp_pkt_bits_hist; // @[el2_ifu.scala 147:25]
|
|
wire [11:0] bp_ctl_ch_io_exu_mp_pkt_bits_toffset; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_exu_mp_pkt_bits_pcall; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_exu_mp_pkt_bits_pret; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_exu_mp_pkt_bits_pja; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_exu_mp_pkt_bits_way; // @[el2_ifu.scala 147:25]
|
|
wire [7:0] bp_ctl_ch_io_exu_mp_eghr; // @[el2_ifu.scala 147:25]
|
|
wire [7:0] bp_ctl_ch_io_exu_mp_fghr; // @[el2_ifu.scala 147:25]
|
|
wire [7:0] bp_ctl_ch_io_exu_mp_index; // @[el2_ifu.scala 147:25]
|
|
wire [4:0] bp_ctl_ch_io_exu_mp_btag; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_exu_flush_final; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_ifu_bp_hit_taken_f; // @[el2_ifu.scala 147:25]
|
|
wire [30:0] bp_ctl_ch_io_ifu_bp_btb_target_f; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_ifu_bp_inst_mask_f; // @[el2_ifu.scala 147:25]
|
|
wire [7:0] bp_ctl_ch_io_ifu_bp_fghr_f; // @[el2_ifu.scala 147:25]
|
|
wire [1:0] bp_ctl_ch_io_ifu_bp_way_f; // @[el2_ifu.scala 147:25]
|
|
wire [1:0] bp_ctl_ch_io_ifu_bp_ret_f; // @[el2_ifu.scala 147:25]
|
|
wire [1:0] bp_ctl_ch_io_ifu_bp_hist1_f; // @[el2_ifu.scala 147:25]
|
|
wire [1:0] bp_ctl_ch_io_ifu_bp_hist0_f; // @[el2_ifu.scala 147:25]
|
|
wire [1:0] bp_ctl_ch_io_ifu_bp_pc4_f; // @[el2_ifu.scala 147:25]
|
|
wire [1:0] bp_ctl_ch_io_ifu_bp_valid_f; // @[el2_ifu.scala 147:25]
|
|
wire [11:0] bp_ctl_ch_io_ifu_bp_poffset_f; // @[el2_ifu.scala 147:25]
|
|
wire bp_ctl_ch_io_scan_mode; // @[el2_ifu.scala 147:25]
|
|
wire aln_ctl_ch_clock; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_reset; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_scan_mode; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_active_clk; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_ifu_async_error_start; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_iccm_rd_ecc_double_err; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_ic_access_fault_f; // @[el2_ifu.scala 148:26]
|
|
wire [1:0] aln_ctl_ch_io_ic_access_fault_type_f; // @[el2_ifu.scala 148:26]
|
|
wire [7:0] aln_ctl_ch_io_ifu_bp_fghr_f; // @[el2_ifu.scala 148:26]
|
|
wire [30:0] aln_ctl_ch_io_ifu_bp_btb_target_f; // @[el2_ifu.scala 148:26]
|
|
wire [11:0] aln_ctl_ch_io_ifu_bp_poffset_f; // @[el2_ifu.scala 148:26]
|
|
wire [1:0] aln_ctl_ch_io_ifu_bp_hist0_f; // @[el2_ifu.scala 148:26]
|
|
wire [1:0] aln_ctl_ch_io_ifu_bp_hist1_f; // @[el2_ifu.scala 148:26]
|
|
wire [1:0] aln_ctl_ch_io_ifu_bp_pc4_f; // @[el2_ifu.scala 148:26]
|
|
wire [1:0] aln_ctl_ch_io_ifu_bp_way_f; // @[el2_ifu.scala 148:26]
|
|
wire [1:0] aln_ctl_ch_io_ifu_bp_valid_f; // @[el2_ifu.scala 148:26]
|
|
wire [1:0] aln_ctl_ch_io_ifu_bp_ret_f; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_exu_flush_final; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_dec_i0_decode_d; // @[el2_ifu.scala 148:26]
|
|
wire [31:0] aln_ctl_ch_io_ifu_fetch_data_f; // @[el2_ifu.scala 148:26]
|
|
wire [1:0] aln_ctl_ch_io_ifu_fetch_val; // @[el2_ifu.scala 148:26]
|
|
wire [30:0] aln_ctl_ch_io_ifu_fetch_pc; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_ifu_i0_valid; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_ifu_i0_icaf; // @[el2_ifu.scala 148:26]
|
|
wire [1:0] aln_ctl_ch_io_ifu_i0_icaf_type; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_ifu_i0_icaf_f1; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_ifu_i0_dbecc; // @[el2_ifu.scala 148:26]
|
|
wire [31:0] aln_ctl_ch_io_ifu_i0_instr; // @[el2_ifu.scala 148:26]
|
|
wire [30:0] aln_ctl_ch_io_ifu_i0_pc; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_ifu_i0_pc4; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_ifu_fb_consume1; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_ifu_fb_consume2; // @[el2_ifu.scala 148:26]
|
|
wire [7:0] aln_ctl_ch_io_ifu_i0_bp_index; // @[el2_ifu.scala 148:26]
|
|
wire [7:0] aln_ctl_ch_io_ifu_i0_bp_fghr; // @[el2_ifu.scala 148:26]
|
|
wire [4:0] aln_ctl_ch_io_ifu_i0_bp_btag; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_ifu_pmu_instr_aligned; // @[el2_ifu.scala 148:26]
|
|
wire [15:0] aln_ctl_ch_io_ifu_i0_cinst; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 148:26]
|
|
wire [11:0] aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 148:26]
|
|
wire [1:0] aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 148:26]
|
|
wire [30:0] aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 148:26]
|
|
wire aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 148:26]
|
|
wire ifc_ctl_ch_clock; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_reset; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_free_clk; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_active_clk; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_scan_mode; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ic_hit_f; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifu_ic_mb_empty; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifu_fb_consume1; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifu_fb_consume2; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_dec_tlu_flush_noredir_wb; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_exu_flush_final; // @[el2_ifu.scala 149:26]
|
|
wire [30:0] ifc_ctl_ch_io_exu_flush_path_final; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifu_bp_hit_taken_f; // @[el2_ifu.scala 149:26]
|
|
wire [30:0] ifc_ctl_ch_io_ifu_bp_btb_target_f; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ic_dma_active; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ic_write_stall; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_dma_iccm_stall_any; // @[el2_ifu.scala 149:26]
|
|
wire [31:0] ifc_ctl_ch_io_dec_tlu_mrac_ff; // @[el2_ifu.scala 149:26]
|
|
wire [30:0] ifc_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 149:26]
|
|
wire [30:0] ifc_ctl_ch_io_ifc_fetch_addr_bf; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifu_pmu_fetch_stall; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifc_fetch_uncacheable_bf; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifc_fetch_req_bf; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifc_fetch_req_bf_raw; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifc_iccm_access_bf; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifc_region_acc_fault_bf; // @[el2_ifu.scala 149:26]
|
|
wire ifc_ctl_ch_io_ifc_dma_access_ok; // @[el2_ifu.scala 149:26]
|
|
el2_ifu_mem_ctl mem_ctl_ch ( // @[el2_ifu.scala 146:26]
|
|
.clock(mem_ctl_ch_clock),
|
|
.reset(mem_ctl_ch_reset),
|
|
.io_free_clk(mem_ctl_ch_io_free_clk),
|
|
.io_active_clk(mem_ctl_ch_io_active_clk),
|
|
.io_exu_flush_final(mem_ctl_ch_io_exu_flush_final),
|
|
.io_dec_tlu_flush_lower_wb(mem_ctl_ch_io_dec_tlu_flush_lower_wb),
|
|
.io_dec_tlu_flush_err_wb(mem_ctl_ch_io_dec_tlu_flush_err_wb),
|
|
.io_dec_tlu_i0_commit_cmt(mem_ctl_ch_io_dec_tlu_i0_commit_cmt),
|
|
.io_dec_tlu_force_halt(mem_ctl_ch_io_dec_tlu_force_halt),
|
|
.io_ifc_fetch_addr_bf(mem_ctl_ch_io_ifc_fetch_addr_bf),
|
|
.io_ifc_fetch_uncacheable_bf(mem_ctl_ch_io_ifc_fetch_uncacheable_bf),
|
|
.io_ifc_fetch_req_bf(mem_ctl_ch_io_ifc_fetch_req_bf),
|
|
.io_ifc_fetch_req_bf_raw(mem_ctl_ch_io_ifc_fetch_req_bf_raw),
|
|
.io_ifc_iccm_access_bf(mem_ctl_ch_io_ifc_iccm_access_bf),
|
|
.io_ifc_region_acc_fault_bf(mem_ctl_ch_io_ifc_region_acc_fault_bf),
|
|
.io_ifc_dma_access_ok(mem_ctl_ch_io_ifc_dma_access_ok),
|
|
.io_dec_tlu_fence_i_wb(mem_ctl_ch_io_dec_tlu_fence_i_wb),
|
|
.io_ifu_bp_hit_taken_f(mem_ctl_ch_io_ifu_bp_hit_taken_f),
|
|
.io_ifu_bp_inst_mask_f(mem_ctl_ch_io_ifu_bp_inst_mask_f),
|
|
.io_ifu_axi_arready(mem_ctl_ch_io_ifu_axi_arready),
|
|
.io_ifu_axi_rvalid(mem_ctl_ch_io_ifu_axi_rvalid),
|
|
.io_ifu_axi_rid(mem_ctl_ch_io_ifu_axi_rid),
|
|
.io_ifu_axi_rdata(mem_ctl_ch_io_ifu_axi_rdata),
|
|
.io_ifu_axi_rresp(mem_ctl_ch_io_ifu_axi_rresp),
|
|
.io_ifu_bus_clk_en(mem_ctl_ch_io_ifu_bus_clk_en),
|
|
.io_dma_iccm_req(mem_ctl_ch_io_dma_iccm_req),
|
|
.io_dma_mem_addr(mem_ctl_ch_io_dma_mem_addr),
|
|
.io_dma_mem_sz(mem_ctl_ch_io_dma_mem_sz),
|
|
.io_dma_mem_write(mem_ctl_ch_io_dma_mem_write),
|
|
.io_dma_mem_wdata(mem_ctl_ch_io_dma_mem_wdata),
|
|
.io_dma_mem_tag(mem_ctl_ch_io_dma_mem_tag),
|
|
.io_ic_rd_data(mem_ctl_ch_io_ic_rd_data),
|
|
.io_ic_debug_rd_data(mem_ctl_ch_io_ic_debug_rd_data),
|
|
.io_ictag_debug_rd_data(mem_ctl_ch_io_ictag_debug_rd_data),
|
|
.io_ic_eccerr(mem_ctl_ch_io_ic_eccerr),
|
|
.io_ic_rd_hit(mem_ctl_ch_io_ic_rd_hit),
|
|
.io_ic_tag_perr(mem_ctl_ch_io_ic_tag_perr),
|
|
.io_iccm_rd_data(mem_ctl_ch_io_iccm_rd_data),
|
|
.io_iccm_rd_data_ecc(mem_ctl_ch_io_iccm_rd_data_ecc),
|
|
.io_ifu_fetch_val(mem_ctl_ch_io_ifu_fetch_val),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wrdata(mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_wrdata),
|
|
.io_dec_tlu_ic_diag_pkt_icache_dicawics(mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_dicawics),
|
|
.io_dec_tlu_ic_diag_pkt_icache_rd_valid(mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_rd_valid),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wr_valid(mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_wr_valid),
|
|
.io_ifu_miss_state_idle(mem_ctl_ch_io_ifu_miss_state_idle),
|
|
.io_ifu_ic_mb_empty(mem_ctl_ch_io_ifu_ic_mb_empty),
|
|
.io_ic_dma_active(mem_ctl_ch_io_ic_dma_active),
|
|
.io_ic_write_stall(mem_ctl_ch_io_ic_write_stall),
|
|
.io_ifu_pmu_ic_miss(mem_ctl_ch_io_ifu_pmu_ic_miss),
|
|
.io_ifu_pmu_ic_hit(mem_ctl_ch_io_ifu_pmu_ic_hit),
|
|
.io_ifu_pmu_bus_error(mem_ctl_ch_io_ifu_pmu_bus_error),
|
|
.io_ifu_pmu_bus_busy(mem_ctl_ch_io_ifu_pmu_bus_busy),
|
|
.io_ifu_pmu_bus_trxn(mem_ctl_ch_io_ifu_pmu_bus_trxn),
|
|
.io_ifu_axi_arvalid(mem_ctl_ch_io_ifu_axi_arvalid),
|
|
.io_ifu_axi_arid(mem_ctl_ch_io_ifu_axi_arid),
|
|
.io_ifu_axi_araddr(mem_ctl_ch_io_ifu_axi_araddr),
|
|
.io_ifu_axi_arregion(mem_ctl_ch_io_ifu_axi_arregion),
|
|
.io_ifu_axi_rready(mem_ctl_ch_io_ifu_axi_rready),
|
|
.io_iccm_dma_ecc_error(mem_ctl_ch_io_iccm_dma_ecc_error),
|
|
.io_iccm_dma_rvalid(mem_ctl_ch_io_iccm_dma_rvalid),
|
|
.io_iccm_dma_rdata(mem_ctl_ch_io_iccm_dma_rdata),
|
|
.io_iccm_dma_rtag(mem_ctl_ch_io_iccm_dma_rtag),
|
|
.io_iccm_ready(mem_ctl_ch_io_iccm_ready),
|
|
.io_ic_rw_addr(mem_ctl_ch_io_ic_rw_addr),
|
|
.io_ic_wr_en(mem_ctl_ch_io_ic_wr_en),
|
|
.io_ic_rd_en(mem_ctl_ch_io_ic_rd_en),
|
|
.io_ic_wr_data_0(mem_ctl_ch_io_ic_wr_data_0),
|
|
.io_ic_wr_data_1(mem_ctl_ch_io_ic_wr_data_1),
|
|
.io_ic_debug_wr_data(mem_ctl_ch_io_ic_debug_wr_data),
|
|
.io_ifu_ic_debug_rd_data(mem_ctl_ch_io_ifu_ic_debug_rd_data),
|
|
.io_ic_debug_addr(mem_ctl_ch_io_ic_debug_addr),
|
|
.io_ic_debug_rd_en(mem_ctl_ch_io_ic_debug_rd_en),
|
|
.io_ic_debug_wr_en(mem_ctl_ch_io_ic_debug_wr_en),
|
|
.io_ic_debug_tag_array(mem_ctl_ch_io_ic_debug_tag_array),
|
|
.io_ic_debug_way(mem_ctl_ch_io_ic_debug_way),
|
|
.io_ic_tag_valid(mem_ctl_ch_io_ic_tag_valid),
|
|
.io_iccm_rw_addr(mem_ctl_ch_io_iccm_rw_addr),
|
|
.io_iccm_wren(mem_ctl_ch_io_iccm_wren),
|
|
.io_iccm_rden(mem_ctl_ch_io_iccm_rden),
|
|
.io_iccm_wr_data(mem_ctl_ch_io_iccm_wr_data),
|
|
.io_iccm_wr_size(mem_ctl_ch_io_iccm_wr_size),
|
|
.io_ic_hit_f(mem_ctl_ch_io_ic_hit_f),
|
|
.io_ic_access_fault_f(mem_ctl_ch_io_ic_access_fault_f),
|
|
.io_ic_access_fault_type_f(mem_ctl_ch_io_ic_access_fault_type_f),
|
|
.io_iccm_rd_ecc_single_err(mem_ctl_ch_io_iccm_rd_ecc_single_err),
|
|
.io_iccm_rd_ecc_double_err(mem_ctl_ch_io_iccm_rd_ecc_double_err),
|
|
.io_ic_error_start(mem_ctl_ch_io_ic_error_start),
|
|
.io_ifu_async_error_start(mem_ctl_ch_io_ifu_async_error_start),
|
|
.io_iccm_dma_sb_error(mem_ctl_ch_io_iccm_dma_sb_error),
|
|
.io_ic_fetch_val_f(mem_ctl_ch_io_ic_fetch_val_f),
|
|
.io_ic_data_f(mem_ctl_ch_io_ic_data_f),
|
|
.io_ic_premux_data(mem_ctl_ch_io_ic_premux_data),
|
|
.io_ic_sel_premux_data(mem_ctl_ch_io_ic_sel_premux_data),
|
|
.io_dec_tlu_core_ecc_disable(mem_ctl_ch_io_dec_tlu_core_ecc_disable),
|
|
.io_ifu_ic_debug_rd_data_valid(mem_ctl_ch_io_ifu_ic_debug_rd_data_valid),
|
|
.io_iccm_buf_correct_ecc(mem_ctl_ch_io_iccm_buf_correct_ecc),
|
|
.io_iccm_correction_state(mem_ctl_ch_io_iccm_correction_state),
|
|
.io_scan_mode(mem_ctl_ch_io_scan_mode)
|
|
);
|
|
el2_ifu_bp_ctl bp_ctl_ch ( // @[el2_ifu.scala 147:25]
|
|
.clock(bp_ctl_ch_clock),
|
|
.reset(bp_ctl_ch_reset),
|
|
.io_active_clk(bp_ctl_ch_io_active_clk),
|
|
.io_ic_hit_f(bp_ctl_ch_io_ic_hit_f),
|
|
.io_ifc_fetch_addr_f(bp_ctl_ch_io_ifc_fetch_addr_f),
|
|
.io_ifc_fetch_req_f(bp_ctl_ch_io_ifc_fetch_req_f),
|
|
.io_dec_tlu_br0_r_pkt_valid(bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid),
|
|
.io_dec_tlu_br0_r_pkt_hist(bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist),
|
|
.io_dec_tlu_br0_r_pkt_br_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error),
|
|
.io_dec_tlu_br0_r_pkt_br_start_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error),
|
|
.io_dec_tlu_br0_r_pkt_way(bp_ctl_ch_io_dec_tlu_br0_r_pkt_way),
|
|
.io_dec_tlu_br0_r_pkt_middle(bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle),
|
|
.io_exu_i0_br_fghr_r(bp_ctl_ch_io_exu_i0_br_fghr_r),
|
|
.io_exu_i0_br_index_r(bp_ctl_ch_io_exu_i0_br_index_r),
|
|
.io_dec_tlu_flush_lower_wb(bp_ctl_ch_io_dec_tlu_flush_lower_wb),
|
|
.io_dec_tlu_flush_leak_one_wb(bp_ctl_ch_io_dec_tlu_flush_leak_one_wb),
|
|
.io_dec_tlu_bpred_disable(bp_ctl_ch_io_dec_tlu_bpred_disable),
|
|
.io_exu_mp_pkt_bits_misp(bp_ctl_ch_io_exu_mp_pkt_bits_misp),
|
|
.io_exu_mp_pkt_bits_ataken(bp_ctl_ch_io_exu_mp_pkt_bits_ataken),
|
|
.io_exu_mp_pkt_bits_boffset(bp_ctl_ch_io_exu_mp_pkt_bits_boffset),
|
|
.io_exu_mp_pkt_bits_pc4(bp_ctl_ch_io_exu_mp_pkt_bits_pc4),
|
|
.io_exu_mp_pkt_bits_hist(bp_ctl_ch_io_exu_mp_pkt_bits_hist),
|
|
.io_exu_mp_pkt_bits_toffset(bp_ctl_ch_io_exu_mp_pkt_bits_toffset),
|
|
.io_exu_mp_pkt_bits_pcall(bp_ctl_ch_io_exu_mp_pkt_bits_pcall),
|
|
.io_exu_mp_pkt_bits_pret(bp_ctl_ch_io_exu_mp_pkt_bits_pret),
|
|
.io_exu_mp_pkt_bits_pja(bp_ctl_ch_io_exu_mp_pkt_bits_pja),
|
|
.io_exu_mp_pkt_bits_way(bp_ctl_ch_io_exu_mp_pkt_bits_way),
|
|
.io_exu_mp_eghr(bp_ctl_ch_io_exu_mp_eghr),
|
|
.io_exu_mp_fghr(bp_ctl_ch_io_exu_mp_fghr),
|
|
.io_exu_mp_index(bp_ctl_ch_io_exu_mp_index),
|
|
.io_exu_mp_btag(bp_ctl_ch_io_exu_mp_btag),
|
|
.io_exu_flush_final(bp_ctl_ch_io_exu_flush_final),
|
|
.io_ifu_bp_hit_taken_f(bp_ctl_ch_io_ifu_bp_hit_taken_f),
|
|
.io_ifu_bp_btb_target_f(bp_ctl_ch_io_ifu_bp_btb_target_f),
|
|
.io_ifu_bp_inst_mask_f(bp_ctl_ch_io_ifu_bp_inst_mask_f),
|
|
.io_ifu_bp_fghr_f(bp_ctl_ch_io_ifu_bp_fghr_f),
|
|
.io_ifu_bp_way_f(bp_ctl_ch_io_ifu_bp_way_f),
|
|
.io_ifu_bp_ret_f(bp_ctl_ch_io_ifu_bp_ret_f),
|
|
.io_ifu_bp_hist1_f(bp_ctl_ch_io_ifu_bp_hist1_f),
|
|
.io_ifu_bp_hist0_f(bp_ctl_ch_io_ifu_bp_hist0_f),
|
|
.io_ifu_bp_pc4_f(bp_ctl_ch_io_ifu_bp_pc4_f),
|
|
.io_ifu_bp_valid_f(bp_ctl_ch_io_ifu_bp_valid_f),
|
|
.io_ifu_bp_poffset_f(bp_ctl_ch_io_ifu_bp_poffset_f),
|
|
.io_scan_mode(bp_ctl_ch_io_scan_mode)
|
|
);
|
|
el2_ifu_aln_ctl aln_ctl_ch ( // @[el2_ifu.scala 148:26]
|
|
.clock(aln_ctl_ch_clock),
|
|
.reset(aln_ctl_ch_reset),
|
|
.io_scan_mode(aln_ctl_ch_io_scan_mode),
|
|
.io_active_clk(aln_ctl_ch_io_active_clk),
|
|
.io_ifu_async_error_start(aln_ctl_ch_io_ifu_async_error_start),
|
|
.io_iccm_rd_ecc_double_err(aln_ctl_ch_io_iccm_rd_ecc_double_err),
|
|
.io_ic_access_fault_f(aln_ctl_ch_io_ic_access_fault_f),
|
|
.io_ic_access_fault_type_f(aln_ctl_ch_io_ic_access_fault_type_f),
|
|
.io_ifu_bp_fghr_f(aln_ctl_ch_io_ifu_bp_fghr_f),
|
|
.io_ifu_bp_btb_target_f(aln_ctl_ch_io_ifu_bp_btb_target_f),
|
|
.io_ifu_bp_poffset_f(aln_ctl_ch_io_ifu_bp_poffset_f),
|
|
.io_ifu_bp_hist0_f(aln_ctl_ch_io_ifu_bp_hist0_f),
|
|
.io_ifu_bp_hist1_f(aln_ctl_ch_io_ifu_bp_hist1_f),
|
|
.io_ifu_bp_pc4_f(aln_ctl_ch_io_ifu_bp_pc4_f),
|
|
.io_ifu_bp_way_f(aln_ctl_ch_io_ifu_bp_way_f),
|
|
.io_ifu_bp_valid_f(aln_ctl_ch_io_ifu_bp_valid_f),
|
|
.io_ifu_bp_ret_f(aln_ctl_ch_io_ifu_bp_ret_f),
|
|
.io_exu_flush_final(aln_ctl_ch_io_exu_flush_final),
|
|
.io_dec_i0_decode_d(aln_ctl_ch_io_dec_i0_decode_d),
|
|
.io_ifu_fetch_data_f(aln_ctl_ch_io_ifu_fetch_data_f),
|
|
.io_ifu_fetch_val(aln_ctl_ch_io_ifu_fetch_val),
|
|
.io_ifu_fetch_pc(aln_ctl_ch_io_ifu_fetch_pc),
|
|
.io_ifu_i0_valid(aln_ctl_ch_io_ifu_i0_valid),
|
|
.io_ifu_i0_icaf(aln_ctl_ch_io_ifu_i0_icaf),
|
|
.io_ifu_i0_icaf_type(aln_ctl_ch_io_ifu_i0_icaf_type),
|
|
.io_ifu_i0_icaf_f1(aln_ctl_ch_io_ifu_i0_icaf_f1),
|
|
.io_ifu_i0_dbecc(aln_ctl_ch_io_ifu_i0_dbecc),
|
|
.io_ifu_i0_instr(aln_ctl_ch_io_ifu_i0_instr),
|
|
.io_ifu_i0_pc(aln_ctl_ch_io_ifu_i0_pc),
|
|
.io_ifu_i0_pc4(aln_ctl_ch_io_ifu_i0_pc4),
|
|
.io_ifu_fb_consume1(aln_ctl_ch_io_ifu_fb_consume1),
|
|
.io_ifu_fb_consume2(aln_ctl_ch_io_ifu_fb_consume2),
|
|
.io_ifu_i0_bp_index(aln_ctl_ch_io_ifu_i0_bp_index),
|
|
.io_ifu_i0_bp_fghr(aln_ctl_ch_io_ifu_i0_bp_fghr),
|
|
.io_ifu_i0_bp_btag(aln_ctl_ch_io_ifu_i0_bp_btag),
|
|
.io_ifu_pmu_instr_aligned(aln_ctl_ch_io_ifu_pmu_instr_aligned),
|
|
.io_ifu_i0_cinst(aln_ctl_ch_io_ifu_i0_cinst),
|
|
.io_i0_brp_valid(aln_ctl_ch_io_i0_brp_valid),
|
|
.io_i0_brp_toffset(aln_ctl_ch_io_i0_brp_toffset),
|
|
.io_i0_brp_hist(aln_ctl_ch_io_i0_brp_hist),
|
|
.io_i0_brp_br_error(aln_ctl_ch_io_i0_brp_br_error),
|
|
.io_i0_brp_br_start_error(aln_ctl_ch_io_i0_brp_br_start_error),
|
|
.io_i0_brp_prett(aln_ctl_ch_io_i0_brp_prett),
|
|
.io_i0_brp_way(aln_ctl_ch_io_i0_brp_way),
|
|
.io_i0_brp_ret(aln_ctl_ch_io_i0_brp_ret)
|
|
);
|
|
el2_ifu_ifc_ctl ifc_ctl_ch ( // @[el2_ifu.scala 149:26]
|
|
.clock(ifc_ctl_ch_clock),
|
|
.reset(ifc_ctl_ch_reset),
|
|
.io_free_clk(ifc_ctl_ch_io_free_clk),
|
|
.io_active_clk(ifc_ctl_ch_io_active_clk),
|
|
.io_scan_mode(ifc_ctl_ch_io_scan_mode),
|
|
.io_ic_hit_f(ifc_ctl_ch_io_ic_hit_f),
|
|
.io_ifu_ic_mb_empty(ifc_ctl_ch_io_ifu_ic_mb_empty),
|
|
.io_ifu_fb_consume1(ifc_ctl_ch_io_ifu_fb_consume1),
|
|
.io_ifu_fb_consume2(ifc_ctl_ch_io_ifu_fb_consume2),
|
|
.io_dec_tlu_flush_noredir_wb(ifc_ctl_ch_io_dec_tlu_flush_noredir_wb),
|
|
.io_exu_flush_final(ifc_ctl_ch_io_exu_flush_final),
|
|
.io_exu_flush_path_final(ifc_ctl_ch_io_exu_flush_path_final),
|
|
.io_ifu_bp_hit_taken_f(ifc_ctl_ch_io_ifu_bp_hit_taken_f),
|
|
.io_ifu_bp_btb_target_f(ifc_ctl_ch_io_ifu_bp_btb_target_f),
|
|
.io_ic_dma_active(ifc_ctl_ch_io_ic_dma_active),
|
|
.io_ic_write_stall(ifc_ctl_ch_io_ic_write_stall),
|
|
.io_dma_iccm_stall_any(ifc_ctl_ch_io_dma_iccm_stall_any),
|
|
.io_dec_tlu_mrac_ff(ifc_ctl_ch_io_dec_tlu_mrac_ff),
|
|
.io_ifc_fetch_addr_f(ifc_ctl_ch_io_ifc_fetch_addr_f),
|
|
.io_ifc_fetch_addr_bf(ifc_ctl_ch_io_ifc_fetch_addr_bf),
|
|
.io_ifc_fetch_req_f(ifc_ctl_ch_io_ifc_fetch_req_f),
|
|
.io_ifu_pmu_fetch_stall(ifc_ctl_ch_io_ifu_pmu_fetch_stall),
|
|
.io_ifc_fetch_uncacheable_bf(ifc_ctl_ch_io_ifc_fetch_uncacheable_bf),
|
|
.io_ifc_fetch_req_bf(ifc_ctl_ch_io_ifc_fetch_req_bf),
|
|
.io_ifc_fetch_req_bf_raw(ifc_ctl_ch_io_ifc_fetch_req_bf_raw),
|
|
.io_ifc_iccm_access_bf(ifc_ctl_ch_io_ifc_iccm_access_bf),
|
|
.io_ifc_region_acc_fault_bf(ifc_ctl_ch_io_ifc_region_acc_fault_bf),
|
|
.io_ifc_dma_access_ok(ifc_ctl_ch_io_ifc_dma_access_ok)
|
|
);
|
|
assign io_ifu_axi_arvalid = mem_ctl_ch_io_ifu_axi_arvalid; // @[el2_ifu.scala 273:22]
|
|
assign io_ifu_axi_arid = mem_ctl_ch_io_ifu_axi_arid; // @[el2_ifu.scala 274:19]
|
|
assign io_ifu_axi_araddr = mem_ctl_ch_io_ifu_axi_araddr; // @[el2_ifu.scala 275:21]
|
|
assign io_ifu_axi_arregion = mem_ctl_ch_io_ifu_axi_arregion; // @[el2_ifu.scala 276:23]
|
|
assign io_iccm_dma_ecc_error = mem_ctl_ch_io_iccm_dma_ecc_error; // @[el2_ifu.scala 285:25]
|
|
assign io_iccm_dma_rvalid = mem_ctl_ch_io_iccm_dma_rvalid; // @[el2_ifu.scala 286:22]
|
|
assign io_iccm_dma_rdata = mem_ctl_ch_io_iccm_dma_rdata; // @[el2_ifu.scala 287:21]
|
|
assign io_iccm_dma_rtag = mem_ctl_ch_io_iccm_dma_rtag; // @[el2_ifu.scala 288:20]
|
|
assign io_iccm_ready = mem_ctl_ch_io_iccm_ready; // @[el2_ifu.scala 289:17]
|
|
assign io_ifu_pmu_instr_aligned = aln_ctl_ch_io_ifu_pmu_instr_aligned; // @[el2_ifu.scala 290:28]
|
|
assign io_ifu_pmu_fetch_stall = ifc_ctl_ch_io_ifu_pmu_fetch_stall; // @[el2_ifu.scala 291:26]
|
|
assign io_ifu_ic_error_start = mem_ctl_ch_io_ic_error_start; // @[el2_ifu.scala 292:25]
|
|
assign io_ic_rw_addr = mem_ctl_ch_io_ic_rw_addr; // @[el2_ifu.scala 294:17]
|
|
assign io_ic_wr_en = mem_ctl_ch_io_ic_wr_en; // @[el2_ifu.scala 295:15]
|
|
assign io_ic_rd_en = mem_ctl_ch_io_ic_rd_en; // @[el2_ifu.scala 296:15]
|
|
assign io_ic_wr_data_0 = mem_ctl_ch_io_ic_wr_data_0; // @[el2_ifu.scala 297:17]
|
|
assign io_ic_wr_data_1 = mem_ctl_ch_io_ic_wr_data_1; // @[el2_ifu.scala 297:17]
|
|
assign io_ic_debug_wr_data = mem_ctl_ch_io_ic_debug_wr_data; // @[el2_ifu.scala 298:23]
|
|
assign io_ifu_ic_debug_rd_data = mem_ctl_ch_io_ifu_ic_debug_rd_data; // @[el2_ifu.scala 299:27]
|
|
assign io_ic_premux_data = mem_ctl_ch_io_ic_premux_data; // @[el2_ifu.scala 339:21]
|
|
assign io_ic_sel_premux_data = mem_ctl_ch_io_ic_sel_premux_data; // @[el2_ifu.scala 300:25]
|
|
assign io_ic_debug_addr = mem_ctl_ch_io_ic_debug_addr; // @[el2_ifu.scala 301:20]
|
|
assign io_ic_debug_rd_en = mem_ctl_ch_io_ic_debug_rd_en; // @[el2_ifu.scala 302:21]
|
|
assign io_ic_debug_wr_en = mem_ctl_ch_io_ic_debug_wr_en; // @[el2_ifu.scala 303:21]
|
|
assign io_ic_debug_tag_array = mem_ctl_ch_io_ic_debug_tag_array; // @[el2_ifu.scala 304:25]
|
|
assign io_ic_debug_way = mem_ctl_ch_io_ic_debug_way; // @[el2_ifu.scala 305:19]
|
|
assign io_ic_tag_valid = mem_ctl_ch_io_ic_tag_valid; // @[el2_ifu.scala 306:19]
|
|
assign io_iccm_rw_addr = mem_ctl_ch_io_iccm_rw_addr; // @[el2_ifu.scala 307:19]
|
|
assign io_iccm_wren = mem_ctl_ch_io_iccm_wren; // @[el2_ifu.scala 308:16]
|
|
assign io_iccm_rden = mem_ctl_ch_io_iccm_rden; // @[el2_ifu.scala 309:16]
|
|
assign io_iccm_wr_data = mem_ctl_ch_io_iccm_wr_data; // @[el2_ifu.scala 310:19]
|
|
assign io_iccm_wr_size = mem_ctl_ch_io_iccm_wr_size; // @[el2_ifu.scala 311:19]
|
|
assign io_ifu_iccm_rd_ecc_single_err = mem_ctl_ch_io_iccm_rd_ecc_single_err; // @[el2_ifu.scala 312:33]
|
|
assign io_ifu_pmu_ic_miss = mem_ctl_ch_io_ifu_pmu_ic_miss; // @[el2_ifu.scala 314:22]
|
|
assign io_ifu_pmu_ic_hit = mem_ctl_ch_io_ifu_pmu_ic_hit; // @[el2_ifu.scala 315:21]
|
|
assign io_ifu_pmu_bus_error = mem_ctl_ch_io_ifu_pmu_bus_error; // @[el2_ifu.scala 316:24]
|
|
assign io_ifu_pmu_bus_busy = mem_ctl_ch_io_ifu_pmu_bus_busy; // @[el2_ifu.scala 317:23]
|
|
assign io_ifu_pmu_bus_trxn = mem_ctl_ch_io_ifu_pmu_bus_trxn; // @[el2_ifu.scala 318:23]
|
|
assign io_ifu_i0_icaf = aln_ctl_ch_io_ifu_i0_icaf; // @[el2_ifu.scala 320:18]
|
|
assign io_ifu_i0_icaf_type = aln_ctl_ch_io_ifu_i0_icaf_type; // @[el2_ifu.scala 321:23]
|
|
assign io_ifu_i0_valid = aln_ctl_ch_io_ifu_i0_valid; // @[el2_ifu.scala 322:19]
|
|
assign io_ifu_i0_icaf_f1 = aln_ctl_ch_io_ifu_i0_icaf_f1; // @[el2_ifu.scala 323:21]
|
|
assign io_ifu_i0_dbecc = aln_ctl_ch_io_ifu_i0_dbecc; // @[el2_ifu.scala 324:19]
|
|
assign io_iccm_dma_sb_error = mem_ctl_ch_io_iccm_dma_sb_error; // @[el2_ifu.scala 325:24]
|
|
assign io_ifu_i0_instr = aln_ctl_ch_io_ifu_i0_instr; // @[el2_ifu.scala 326:19]
|
|
assign io_ifu_i0_pc = aln_ctl_ch_io_ifu_i0_pc; // @[el2_ifu.scala 327:16]
|
|
assign io_ifu_i0_pc4 = aln_ctl_ch_io_ifu_i0_pc4; // @[el2_ifu.scala 328:17]
|
|
assign io_ifu_miss_state_idle = mem_ctl_ch_io_ifu_miss_state_idle; // @[el2_ifu.scala 329:26]
|
|
assign io_i0_brp_valid = aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 331:13]
|
|
assign io_i0_brp_toffset = aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 331:13]
|
|
assign io_i0_brp_hist = aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 331:13]
|
|
assign io_i0_brp_br_error = aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 331:13]
|
|
assign io_i0_brp_br_start_error = aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 331:13]
|
|
assign io_i0_brp_prett = aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 331:13]
|
|
assign io_i0_brp_way = aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 331:13]
|
|
assign io_i0_brp_ret = aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 331:13]
|
|
assign io_ifu_i0_bp_index = aln_ctl_ch_io_ifu_i0_bp_index; // @[el2_ifu.scala 332:22]
|
|
assign io_ifu_i0_bp_fghr = aln_ctl_ch_io_ifu_i0_bp_fghr; // @[el2_ifu.scala 333:21]
|
|
assign io_ifu_i0_bp_btag = aln_ctl_ch_io_ifu_i0_bp_btag; // @[el2_ifu.scala 334:21]
|
|
assign io_ifu_i0_cinst = aln_ctl_ch_io_ifu_i0_cinst; // @[el2_ifu.scala 335:19]
|
|
assign io_ifu_ic_debug_rd_data_valid = mem_ctl_ch_io_ifu_ic_debug_rd_data_valid; // @[el2_ifu.scala 336:33]
|
|
assign io_iccm_buf_correct_ecc = mem_ctl_ch_io_iccm_buf_correct_ecc; // @[el2_ifu.scala 337:27]
|
|
assign io_iccm_correction_state = mem_ctl_ch_io_iccm_correction_state; // @[el2_ifu.scala 338:28]
|
|
assign mem_ctl_ch_clock = clock;
|
|
assign mem_ctl_ch_reset = reset;
|
|
assign mem_ctl_ch_io_free_clk = io_free_clk; // @[el2_ifu.scala 212:26]
|
|
assign mem_ctl_ch_io_active_clk = io_active_clk; // @[el2_ifu.scala 213:28]
|
|
assign mem_ctl_ch_io_exu_flush_final = io_exu_flush_final; // @[el2_ifu.scala 214:33]
|
|
assign mem_ctl_ch_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 215:40]
|
|
assign mem_ctl_ch_io_dec_tlu_flush_err_wb = io_dec_tlu_flush_err_wb; // @[el2_ifu.scala 216:38]
|
|
assign mem_ctl_ch_io_dec_tlu_i0_commit_cmt = io_dec_tlu_i0_commit_cmt; // @[el2_ifu.scala 217:39]
|
|
assign mem_ctl_ch_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[el2_ifu.scala 218:36]
|
|
assign mem_ctl_ch_io_ifc_fetch_addr_bf = ifc_ctl_ch_io_ifc_fetch_addr_bf; // @[el2_ifu.scala 219:35]
|
|
assign mem_ctl_ch_io_ifc_fetch_uncacheable_bf = ifc_ctl_ch_io_ifc_fetch_uncacheable_bf; // @[el2_ifu.scala 220:42]
|
|
assign mem_ctl_ch_io_ifc_fetch_req_bf = ifc_ctl_ch_io_ifc_fetch_req_bf; // @[el2_ifu.scala 221:34]
|
|
assign mem_ctl_ch_io_ifc_fetch_req_bf_raw = ifc_ctl_ch_io_ifc_fetch_req_bf_raw; // @[el2_ifu.scala 222:38]
|
|
assign mem_ctl_ch_io_ifc_iccm_access_bf = ifc_ctl_ch_io_ifc_iccm_access_bf; // @[el2_ifu.scala 223:36]
|
|
assign mem_ctl_ch_io_ifc_region_acc_fault_bf = ifc_ctl_ch_io_ifc_region_acc_fault_bf; // @[el2_ifu.scala 224:41]
|
|
assign mem_ctl_ch_io_ifc_dma_access_ok = ifc_ctl_ch_io_ifc_dma_access_ok; // @[el2_ifu.scala 225:35]
|
|
assign mem_ctl_ch_io_dec_tlu_fence_i_wb = io_dec_tlu_fence_i_wb; // @[el2_ifu.scala 226:36]
|
|
assign mem_ctl_ch_io_ifu_bp_hit_taken_f = bp_ctl_ch_io_ifu_bp_hit_taken_f; // @[el2_ifu.scala 227:36]
|
|
assign mem_ctl_ch_io_ifu_bp_inst_mask_f = bp_ctl_ch_io_ifu_bp_inst_mask_f; // @[el2_ifu.scala 228:36]
|
|
assign mem_ctl_ch_io_ifu_axi_arready = io_ifu_axi_arready; // @[el2_ifu.scala 229:33]
|
|
assign mem_ctl_ch_io_ifu_axi_rvalid = io_ifu_axi_rvalid; // @[el2_ifu.scala 230:32]
|
|
assign mem_ctl_ch_io_ifu_axi_rid = io_ifu_axi_rid; // @[el2_ifu.scala 231:29]
|
|
assign mem_ctl_ch_io_ifu_axi_rdata = io_ifu_axi_rdata; // @[el2_ifu.scala 232:31]
|
|
assign mem_ctl_ch_io_ifu_axi_rresp = io_ifu_axi_rresp; // @[el2_ifu.scala 233:31]
|
|
assign mem_ctl_ch_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[el2_ifu.scala 234:32]
|
|
assign mem_ctl_ch_io_dma_iccm_req = io_dma_iccm_req; // @[el2_ifu.scala 235:30]
|
|
assign mem_ctl_ch_io_dma_mem_addr = io_dma_mem_addr; // @[el2_ifu.scala 236:30]
|
|
assign mem_ctl_ch_io_dma_mem_sz = io_dma_mem_sz; // @[el2_ifu.scala 237:28]
|
|
assign mem_ctl_ch_io_dma_mem_write = io_dma_mem_write; // @[el2_ifu.scala 238:31]
|
|
assign mem_ctl_ch_io_dma_mem_wdata = io_dma_mem_wdata; // @[el2_ifu.scala 239:31]
|
|
assign mem_ctl_ch_io_dma_mem_tag = io_dma_mem_tag; // @[el2_ifu.scala 240:29]
|
|
assign mem_ctl_ch_io_ic_rd_data = io_ic_rd_data; // @[el2_ifu.scala 241:28]
|
|
assign mem_ctl_ch_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[el2_ifu.scala 242:34]
|
|
assign mem_ctl_ch_io_ictag_debug_rd_data = io_ictag_debug_rd_data; // @[el2_ifu.scala 243:37]
|
|
assign mem_ctl_ch_io_ic_eccerr = io_ic_eccerr; // @[el2_ifu.scala 244:27]
|
|
assign mem_ctl_ch_io_ic_rd_hit = io_ic_rd_hit; // @[el2_ifu.scala 246:27]
|
|
assign mem_ctl_ch_io_ic_tag_perr = io_ic_tag_perr; // @[el2_ifu.scala 247:29]
|
|
assign mem_ctl_ch_io_iccm_rd_data = io_iccm_rd_data; // @[el2_ifu.scala 248:30]
|
|
assign mem_ctl_ch_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[el2_ifu.scala 249:34]
|
|
assign mem_ctl_ch_io_ifu_fetch_val = mem_ctl_ch_io_ic_fetch_val_f; // @[el2_ifu.scala 250:31]
|
|
assign mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_wrdata = io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu.scala 251:37]
|
|
assign mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_dicawics = io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_ifu.scala 251:37]
|
|
assign mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_rd_valid = io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_ifu.scala 251:37]
|
|
assign mem_ctl_ch_io_dec_tlu_ic_diag_pkt_icache_wr_valid = io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_ifu.scala 251:37]
|
|
assign mem_ctl_ch_io_dec_tlu_core_ecc_disable = io_dec_tlu_core_ecc_disable; // @[el2_ifu.scala 252:42]
|
|
assign mem_ctl_ch_io_scan_mode = io_scan_mode; // @[el2_ifu.scala 253:27]
|
|
assign bp_ctl_ch_clock = clock;
|
|
assign bp_ctl_ch_reset = reset;
|
|
assign bp_ctl_ch_io_active_clk = io_active_clk; // @[el2_ifu.scala 194:27]
|
|
assign bp_ctl_ch_io_ic_hit_f = mem_ctl_ch_io_ic_hit_f; // @[el2_ifu.scala 195:25]
|
|
assign bp_ctl_ch_io_ifc_fetch_addr_f = ifc_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 196:33]
|
|
assign bp_ctl_ch_io_ifc_fetch_req_f = ifc_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 197:32]
|
|
assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid = io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 198:34]
|
|
assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist = io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 198:34]
|
|
assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error = io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 198:34]
|
|
assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error = io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 198:34]
|
|
assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_way = io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 198:34]
|
|
assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle = io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 198:34]
|
|
assign bp_ctl_ch_io_exu_i0_br_fghr_r = io_exu_i0_br_fghr_r; // @[el2_ifu.scala 199:33]
|
|
assign bp_ctl_ch_io_exu_i0_br_index_r = io_exu_i0_br_index_r; // @[el2_ifu.scala 200:34]
|
|
assign bp_ctl_ch_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 201:39]
|
|
assign bp_ctl_ch_io_dec_tlu_flush_leak_one_wb = io_dec_tlu_flush_leak_one_wb; // @[el2_ifu.scala 202:42]
|
|
assign bp_ctl_ch_io_dec_tlu_bpred_disable = io_dec_tlu_bpred_disable; // @[el2_ifu.scala 203:38]
|
|
assign bp_ctl_ch_io_exu_mp_pkt_bits_misp = io_exu_mp_pkt_bits_misp; // @[el2_ifu.scala 204:27]
|
|
assign bp_ctl_ch_io_exu_mp_pkt_bits_ataken = io_exu_mp_pkt_bits_ataken; // @[el2_ifu.scala 204:27]
|
|
assign bp_ctl_ch_io_exu_mp_pkt_bits_boffset = io_exu_mp_pkt_bits_boffset; // @[el2_ifu.scala 204:27]
|
|
assign bp_ctl_ch_io_exu_mp_pkt_bits_pc4 = io_exu_mp_pkt_bits_pc4; // @[el2_ifu.scala 204:27]
|
|
assign bp_ctl_ch_io_exu_mp_pkt_bits_hist = io_exu_mp_pkt_bits_hist; // @[el2_ifu.scala 204:27]
|
|
assign bp_ctl_ch_io_exu_mp_pkt_bits_toffset = io_exu_mp_pkt_bits_toffset; // @[el2_ifu.scala 204:27]
|
|
assign bp_ctl_ch_io_exu_mp_pkt_bits_pcall = io_exu_mp_pkt_bits_pcall; // @[el2_ifu.scala 204:27]
|
|
assign bp_ctl_ch_io_exu_mp_pkt_bits_pret = io_exu_mp_pkt_bits_pret; // @[el2_ifu.scala 204:27]
|
|
assign bp_ctl_ch_io_exu_mp_pkt_bits_pja = io_exu_mp_pkt_bits_pja; // @[el2_ifu.scala 204:27]
|
|
assign bp_ctl_ch_io_exu_mp_pkt_bits_way = io_exu_mp_pkt_bits_way; // @[el2_ifu.scala 204:27]
|
|
assign bp_ctl_ch_io_exu_mp_eghr = io_exu_mp_eghr; // @[el2_ifu.scala 205:28]
|
|
assign bp_ctl_ch_io_exu_mp_fghr = io_exu_mp_fghr; // @[el2_ifu.scala 206:28]
|
|
assign bp_ctl_ch_io_exu_mp_index = io_exu_mp_index; // @[el2_ifu.scala 207:29]
|
|
assign bp_ctl_ch_io_exu_mp_btag = io_exu_mp_btag; // @[el2_ifu.scala 208:28]
|
|
assign bp_ctl_ch_io_exu_flush_final = io_exu_flush_final; // @[el2_ifu.scala 209:32]
|
|
assign bp_ctl_ch_io_scan_mode = io_scan_mode; // @[el2_ifu.scala 193:26]
|
|
assign aln_ctl_ch_clock = clock;
|
|
assign aln_ctl_ch_reset = reset;
|
|
assign aln_ctl_ch_io_scan_mode = io_scan_mode; // @[el2_ifu.scala 171:27]
|
|
assign aln_ctl_ch_io_active_clk = io_active_clk; // @[el2_ifu.scala 172:28]
|
|
assign aln_ctl_ch_io_ifu_async_error_start = mem_ctl_ch_io_ifu_async_error_start; // @[el2_ifu.scala 173:39]
|
|
assign aln_ctl_ch_io_iccm_rd_ecc_double_err = mem_ctl_ch_io_iccm_rd_ecc_double_err; // @[el2_ifu.scala 174:40]
|
|
assign aln_ctl_ch_io_ic_access_fault_f = mem_ctl_ch_io_ic_access_fault_f; // @[el2_ifu.scala 175:35]
|
|
assign aln_ctl_ch_io_ic_access_fault_type_f = mem_ctl_ch_io_ic_access_fault_type_f; // @[el2_ifu.scala 176:40]
|
|
assign aln_ctl_ch_io_ifu_bp_fghr_f = bp_ctl_ch_io_ifu_bp_fghr_f; // @[el2_ifu.scala 177:31]
|
|
assign aln_ctl_ch_io_ifu_bp_btb_target_f = bp_ctl_ch_io_ifu_bp_btb_target_f; // @[el2_ifu.scala 178:37]
|
|
assign aln_ctl_ch_io_ifu_bp_poffset_f = bp_ctl_ch_io_ifu_bp_poffset_f; // @[el2_ifu.scala 179:34]
|
|
assign aln_ctl_ch_io_ifu_bp_hist0_f = bp_ctl_ch_io_ifu_bp_hist0_f; // @[el2_ifu.scala 180:32]
|
|
assign aln_ctl_ch_io_ifu_bp_hist1_f = bp_ctl_ch_io_ifu_bp_hist1_f; // @[el2_ifu.scala 181:32]
|
|
assign aln_ctl_ch_io_ifu_bp_pc4_f = bp_ctl_ch_io_ifu_bp_pc4_f; // @[el2_ifu.scala 182:30]
|
|
assign aln_ctl_ch_io_ifu_bp_way_f = bp_ctl_ch_io_ifu_bp_way_f; // @[el2_ifu.scala 183:30]
|
|
assign aln_ctl_ch_io_ifu_bp_valid_f = bp_ctl_ch_io_ifu_bp_valid_f; // @[el2_ifu.scala 184:32]
|
|
assign aln_ctl_ch_io_ifu_bp_ret_f = bp_ctl_ch_io_ifu_bp_ret_f; // @[el2_ifu.scala 185:30]
|
|
assign aln_ctl_ch_io_exu_flush_final = io_exu_flush_final; // @[el2_ifu.scala 186:33]
|
|
assign aln_ctl_ch_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[el2_ifu.scala 187:33]
|
|
assign aln_ctl_ch_io_ifu_fetch_data_f = mem_ctl_ch_io_ic_data_f; // @[el2_ifu.scala 188:34]
|
|
assign aln_ctl_ch_io_ifu_fetch_val = mem_ctl_ch_io_ifu_fetch_val; // @[el2_ifu.scala 189:31]
|
|
assign aln_ctl_ch_io_ifu_fetch_pc = ifc_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 190:30]
|
|
assign ifc_ctl_ch_clock = clock;
|
|
assign ifc_ctl_ch_reset = reset;
|
|
assign ifc_ctl_ch_io_free_clk = io_free_clk; // @[el2_ifu.scala 152:26]
|
|
assign ifc_ctl_ch_io_active_clk = io_active_clk; // @[el2_ifu.scala 151:28]
|
|
assign ifc_ctl_ch_io_scan_mode = io_scan_mode; // @[el2_ifu.scala 153:27]
|
|
assign ifc_ctl_ch_io_ic_hit_f = mem_ctl_ch_io_ic_hit_f; // @[el2_ifu.scala 154:26]
|
|
assign ifc_ctl_ch_io_ifu_ic_mb_empty = mem_ctl_ch_io_ifu_ic_mb_empty; // @[el2_ifu.scala 166:33]
|
|
assign ifc_ctl_ch_io_ifu_fb_consume1 = aln_ctl_ch_io_ifu_fb_consume1; // @[el2_ifu.scala 155:33]
|
|
assign ifc_ctl_ch_io_ifu_fb_consume2 = aln_ctl_ch_io_ifu_fb_consume2; // @[el2_ifu.scala 156:33]
|
|
assign ifc_ctl_ch_io_dec_tlu_flush_noredir_wb = io_dec_tlu_flush_noredir_wb; // @[el2_ifu.scala 157:42]
|
|
assign ifc_ctl_ch_io_exu_flush_final = io_exu_flush_final; // @[el2_ifu.scala 158:33]
|
|
assign ifc_ctl_ch_io_exu_flush_path_final = io_exu_flush_path_final; // @[el2_ifu.scala 159:38]
|
|
assign ifc_ctl_ch_io_ifu_bp_hit_taken_f = bp_ctl_ch_io_ifu_bp_hit_taken_f; // @[el2_ifu.scala 160:36]
|
|
assign ifc_ctl_ch_io_ifu_bp_btb_target_f = bp_ctl_ch_io_ifu_bp_btb_target_f; // @[el2_ifu.scala 161:37]
|
|
assign ifc_ctl_ch_io_ic_dma_active = mem_ctl_ch_io_ic_dma_active; // @[el2_ifu.scala 162:31]
|
|
assign ifc_ctl_ch_io_ic_write_stall = mem_ctl_ch_io_ic_write_stall; // @[el2_ifu.scala 163:32]
|
|
assign ifc_ctl_ch_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[el2_ifu.scala 164:36]
|
|
assign ifc_ctl_ch_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[el2_ifu.scala 165:33]
|
|
endmodule
|
|
module el2_dec_ib_ctl(
|
|
input io_dbg_cmd_valid,
|
|
input io_dbg_cmd_write,
|
|
input [1:0] io_dbg_cmd_type,
|
|
input [31:0] io_dbg_cmd_addr,
|
|
input io_i0_brp_valid,
|
|
input [11:0] io_i0_brp_toffset,
|
|
input [1:0] io_i0_brp_hist,
|
|
input io_i0_brp_br_error,
|
|
input io_i0_brp_br_start_error,
|
|
input [30:0] io_i0_brp_prett,
|
|
input io_i0_brp_way,
|
|
input io_i0_brp_ret,
|
|
input [7:0] io_ifu_i0_bp_index,
|
|
input [7:0] io_ifu_i0_bp_fghr,
|
|
input [4:0] io_ifu_i0_bp_btag,
|
|
input io_ifu_i0_pc4,
|
|
input io_ifu_i0_valid,
|
|
input io_ifu_i0_icaf,
|
|
input [1:0] io_ifu_i0_icaf_type,
|
|
input io_ifu_i0_icaf_f1,
|
|
input io_ifu_i0_dbecc,
|
|
input [31:0] io_ifu_i0_instr,
|
|
input [30:0] io_ifu_i0_pc,
|
|
output io_dec_ib0_valid_d,
|
|
output [1:0] io_dec_i0_icaf_type_d,
|
|
output [31:0] io_dec_i0_instr_d,
|
|
output [30:0] io_dec_i0_pc_d,
|
|
output io_dec_i0_pc4_d,
|
|
output io_dec_i0_brp_valid,
|
|
output [11:0] io_dec_i0_brp_toffset,
|
|
output [1:0] io_dec_i0_brp_hist,
|
|
output io_dec_i0_brp_br_error,
|
|
output io_dec_i0_brp_br_start_error,
|
|
output [30:0] io_dec_i0_brp_prett,
|
|
output io_dec_i0_brp_way,
|
|
output io_dec_i0_brp_ret,
|
|
output [7:0] io_dec_i0_bp_index,
|
|
output [7:0] io_dec_i0_bp_fghr,
|
|
output [4:0] io_dec_i0_bp_btag,
|
|
output io_dec_i0_icaf_d,
|
|
output io_dec_i0_icaf_f1_d,
|
|
output io_dec_i0_dbecc_d,
|
|
output io_dec_debug_wdata_rs1_d,
|
|
output io_dec_debug_fence_d
|
|
);
|
|
wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 31:60]
|
|
wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 31:41]
|
|
wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 32:38]
|
|
wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 32:36]
|
|
wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 33:36]
|
|
wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 35:55]
|
|
wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 35:37]
|
|
wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 36:37]
|
|
wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 37:55]
|
|
wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 37:37]
|
|
wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 38:37]
|
|
wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 40:40]
|
|
wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 41:40]
|
|
wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58]
|
|
wire [13:0] _T_12 = {3'h6,dreg,6'h33}; // @[Cat.scala 29:58]
|
|
wire [25:0] _T_14 = {dcsr,14'h2073}; // @[Cat.scala 29:58]
|
|
wire [24:0] _T_16 = {dcsr,13'h1073}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [13:0] _T_18 = debug_write_gpr ? _T_12 : 14'h0; // @[Mux.scala 27:72]
|
|
wire [25:0] _T_19 = debug_read_csr ? _T_14 : 26'h0; // @[Mux.scala 27:72]
|
|
wire [24:0] _T_20 = debug_write_csr ? _T_16 : 25'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _GEN_0 = {{18'd0}, _T_18}; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_21 = _T_17 | _GEN_0; // @[Mux.scala 27:72]
|
|
wire [31:0] _GEN_1 = {{6'd0}, _T_19}; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_22 = _T_21 | _GEN_1; // @[Mux.scala 27:72]
|
|
wire [31:0] _GEN_2 = {{7'd0}, _T_20}; // @[Mux.scala 27:72]
|
|
wire [31:0] ib0_debug_in = _T_22 | _GEN_2; // @[Mux.scala 27:72]
|
|
wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 54:51]
|
|
assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 56:22]
|
|
assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 13:31]
|
|
assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 57:22]
|
|
assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 11:31]
|
|
assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 12:31]
|
|
assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 14:31]
|
|
assign io_dec_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec_ib_ctl.scala 14:31]
|
|
assign io_dec_i0_brp_hist = io_i0_brp_hist; // @[el2_dec_ib_ctl.scala 14:31]
|
|
assign io_dec_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec_ib_ctl.scala 14:31]
|
|
assign io_dec_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec_ib_ctl.scala 14:31]
|
|
assign io_dec_i0_brp_prett = io_i0_brp_prett; // @[el2_dec_ib_ctl.scala 14:31]
|
|
assign io_dec_i0_brp_way = io_i0_brp_way; // @[el2_dec_ib_ctl.scala 14:31]
|
|
assign io_dec_i0_brp_ret = io_i0_brp_ret; // @[el2_dec_ib_ctl.scala 14:31]
|
|
assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 15:31]
|
|
assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 16:31]
|
|
assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 17:31]
|
|
assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 10:31]
|
|
assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 8:31]
|
|
assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 9:31]
|
|
assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 51:28]
|
|
assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 54:24]
|
|
endmodule
|
|
module el2_dec_dec_ctl(
|
|
input [31:0] io_ins,
|
|
output io_out_alu,
|
|
output io_out_rs1,
|
|
output io_out_rs2,
|
|
output io_out_imm12,
|
|
output io_out_rd,
|
|
output io_out_shimm5,
|
|
output io_out_imm20,
|
|
output io_out_pc,
|
|
output io_out_load,
|
|
output io_out_store,
|
|
output io_out_lsu,
|
|
output io_out_add,
|
|
output io_out_sub,
|
|
output io_out_land,
|
|
output io_out_lor,
|
|
output io_out_lxor,
|
|
output io_out_sll,
|
|
output io_out_sra,
|
|
output io_out_srl,
|
|
output io_out_slt,
|
|
output io_out_unsign,
|
|
output io_out_condbr,
|
|
output io_out_beq,
|
|
output io_out_bne,
|
|
output io_out_bge,
|
|
output io_out_blt,
|
|
output io_out_jal,
|
|
output io_out_by,
|
|
output io_out_half,
|
|
output io_out_word,
|
|
output io_out_csr_read,
|
|
output io_out_csr_clr,
|
|
output io_out_csr_set,
|
|
output io_out_csr_write,
|
|
output io_out_csr_imm,
|
|
output io_out_presync,
|
|
output io_out_postsync,
|
|
output io_out_ebreak,
|
|
output io_out_ecall,
|
|
output io_out_mret,
|
|
output io_out_mul,
|
|
output io_out_rs1_sign,
|
|
output io_out_rs2_sign,
|
|
output io_out_low,
|
|
output io_out_div,
|
|
output io_out_rem,
|
|
output io_out_fence,
|
|
output io_out_fence_i,
|
|
output io_out_pm_alu,
|
|
output io_out_legal
|
|
);
|
|
wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 20:27]
|
|
wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 20:42]
|
|
wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 20:53]
|
|
wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 20:39]
|
|
wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 20:68]
|
|
wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 20:78]
|
|
wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 21:43]
|
|
wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 21:70]
|
|
wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 22:29]
|
|
wire _T_48 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_49 = _T_48 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_50 = _T_43 | _T_49; // @[el2_dec_dec_ctl.scala 22:56]
|
|
wire _T_56 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_57 = _T_56 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_58 = _T_50 | _T_57; // @[el2_dec_dec_ctl.scala 23:29]
|
|
wire _T_63 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_64 = _T_63 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_65 = _T_58 | _T_64; // @[el2_dec_dec_ctl.scala 23:55]
|
|
wire _T_71 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_72 = _T_71 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_73 = _T_65 | _T_72; // @[el2_dec_dec_ctl.scala 24:29]
|
|
wire _T_78 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_79 = _T_78 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_80 = _T_73 | _T_79; // @[el2_dec_dec_ctl.scala 24:55]
|
|
wire _T_86 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_87 = _T_86 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_88 = _T_80 | _T_87; // @[el2_dec_dec_ctl.scala 25:29]
|
|
wire _T_93 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_94 = _T_93 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_95 = _T_88 | _T_94; // @[el2_dec_dec_ctl.scala 25:55]
|
|
wire _T_97 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_99 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_100 = _T_97 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_101 = _T_95 | _T_100; // @[el2_dec_dec_ctl.scala 26:29]
|
|
wire _T_103 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_106 = _T_103 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_113 = io_ins[5] & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_114 = _T_113 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_120 = _T_103 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_121 = _T_120 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_129 = _T_100 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_136 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_137 = _T_136 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_138 = _T_137 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_139 = _T_129 | _T_138; // @[el2_dec_dec_ctl.scala 28:42]
|
|
wire _T_143 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_146 = _T_16 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_147 = _T_146 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_148 = _T_147 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_149 = _T_139 | _T_148; // @[el2_dec_dec_ctl.scala 28:70]
|
|
wire _T_157 = _T_143 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_158 = _T_157 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_159 = _T_158 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_165 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 30:28]
|
|
wire _T_168 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 30:55]
|
|
wire _T_169 = _T_165 | _T_168; // @[el2_dec_dec_ctl.scala 30:42]
|
|
wire _T_180 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_181 = _T_180 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_182 = _T_181 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_186 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 32:29]
|
|
wire _T_189 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 32:53]
|
|
wire _T_195 = _T_9 & _T_99; // @[el2_dec_dec_ctl.scala 33:28]
|
|
wire _T_197 = _T_195 & io_ins[2]; // @[el2_dec_dec_ctl.scala 33:41]
|
|
wire _T_208 = _T_9 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_223 = _T_103 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_235 = _T_19 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_236 = _T_235 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_237 = _T_236 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_245 = _T_237 | _T_197; // @[el2_dec_dec_ctl.scala 37:49]
|
|
wire _T_247 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_261 = _T_247 & _T_4; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_262 = _T_261 & _T_14; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_263 = _T_262 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_264 = _T_263 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_265 = _T_264 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_266 = _T_265 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_267 = _T_266 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_278 = io_ins[30] & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_279 = _T_278 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_280 = _T_279 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_281 = _T_280 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_282 = _T_281 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_293 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_294 = _T_293 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_295 = _T_294 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_296 = _T_295 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_297 = _T_296 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_298 = _T_282 | _T_297; // @[el2_dec_dec_ctl.scala 39:49]
|
|
wire _T_307 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_308 = _T_307 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_309 = _T_308 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_310 = _T_309 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_311 = _T_298 | _T_310; // @[el2_dec_dec_ctl.scala 39:85]
|
|
wire _T_317 = io_ins[6] & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_318 = _T_317 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_327 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_328 = _T_327 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_329 = _T_328 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_330 = _T_329 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_340 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_341 = _T_340 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_342 = _T_341 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_343 = _T_342 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_344 = _T_343 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_349 = _T_103 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_362 = _T_341 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_363 = _T_362 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_364 = _T_363 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_365 = _T_349 | _T_364; // @[el2_dec_dec_ctl.scala 42:37]
|
|
wire _T_369 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_370 = _T_369 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_371 = _T_365 | _T_370; // @[el2_dec_dec_ctl.scala 42:74]
|
|
wire _T_381 = _T_371 | _T_148; // @[el2_dec_dec_ctl.scala 43:26]
|
|
wire _T_391 = _T_327 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_392 = _T_391 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_393 = _T_392 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_406 = _T_340 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_407 = _T_406 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_408 = _T_407 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_409 = _T_408 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_420 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_421 = _T_420 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_422 = _T_421 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_423 = _T_422 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_424 = _T_423 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_439 = _T_293 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_440 = _T_439 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_441 = _T_440 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_442 = _T_441 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_453 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_454 = _T_453 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_455 = _T_454 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_456 = _T_455 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_472 = _T_261 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_473 = _T_472 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_474 = _T_473 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_475 = _T_474 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_476 = _T_475 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_515 = _T_307 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_516 = _T_515 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_517 = _T_516 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_524 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_525 = _T_524 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_526 = _T_525 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_527 = _T_517 | _T_526; // @[el2_dec_dec_ctl.scala 50:51]
|
|
wire _T_533 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_534 = _T_533 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_535 = _T_527 | _T_534; // @[el2_dec_dec_ctl.scala 50:79]
|
|
wire _T_548 = _T_294 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_549 = _T_548 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_550 = _T_549 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_551 = _T_535 | _T_550; // @[el2_dec_dec_ctl.scala 51:29]
|
|
wire _T_560 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_561 = _T_560 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_562 = _T_561 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_563 = _T_562 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_564 = _T_563 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_582 = _T_14 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_583 = _T_582 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_584 = _T_583 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_594 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_595 = _T_594 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_596 = _T_595 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_605 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_606 = _T_605 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_607 = _T_606 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_617 = io_ins[14] & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_618 = _T_617 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_619 = _T_618 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_635 = _T_146 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_636 = _T_635 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_645 = io_ins[12] & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_646 = _T_645 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_653 = io_ins[13] & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_659 = _T_524 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_663 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_664 = _T_663 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_665 = _T_659 | _T_664; // @[el2_dec_dec_ctl.scala 62:44]
|
|
wire _T_669 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_670 = _T_669 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_671 = _T_665 | _T_670; // @[el2_dec_dec_ctl.scala 62:67]
|
|
wire _T_675 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_676 = _T_675 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_677 = _T_671 | _T_676; // @[el2_dec_dec_ctl.scala 63:26]
|
|
wire _T_681 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_682 = _T_681 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_683 = _T_677 | _T_682; // @[el2_dec_dec_ctl.scala 63:49]
|
|
wire _T_687 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_688 = _T_687 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_696 = _T_93 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_697 = _T_696 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_698 = _T_697 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_705 = _T_78 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_706 = _T_705 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_707 = _T_706 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_708 = _T_698 | _T_707; // @[el2_dec_dec_ctl.scala 65:49]
|
|
wire _T_715 = _T_63 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_716 = _T_715 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_717 = _T_716 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_718 = _T_708 | _T_717; // @[el2_dec_dec_ctl.scala 65:79]
|
|
wire _T_725 = _T_48 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_726 = _T_725 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_727 = _T_726 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_728 = _T_718 | _T_727; // @[el2_dec_dec_ctl.scala 66:33]
|
|
wire _T_735 = _T_33 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_736 = _T_735 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_737 = _T_736 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_745 = _T_180 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_753 = _T_420 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_754 = _T_753 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_759 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_760 = _T_759 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_761 = _T_760 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_762 = _T_754 | _T_761; // @[el2_dec_dec_ctl.scala 69:47]
|
|
wire _T_767 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_768 = _T_767 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_769 = _T_768 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_770 = _T_762 | _T_769; // @[el2_dec_dec_ctl.scala 69:74]
|
|
wire _T_775 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_776 = _T_775 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_777 = _T_776 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_778 = _T_770 | _T_777; // @[el2_dec_dec_ctl.scala 70:30]
|
|
wire _T_783 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_784 = _T_783 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_785 = _T_784 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_786 = _T_778 | _T_785; // @[el2_dec_dec_ctl.scala 70:57]
|
|
wire _T_791 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_792 = _T_791 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_793 = _T_792 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_800 = io_ins[15] & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_801 = _T_800 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_802 = _T_801 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_808 = io_ins[16] & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_809 = _T_808 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_810 = _T_809 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_811 = _T_802 | _T_810; // @[el2_dec_dec_ctl.scala 72:47]
|
|
wire _T_817 = io_ins[17] & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_818 = _T_817 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_819 = _T_818 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_820 = _T_811 | _T_819; // @[el2_dec_dec_ctl.scala 72:75]
|
|
wire _T_826 = io_ins[18] & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_827 = _T_826 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_828 = _T_827 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_829 = _T_820 | _T_828; // @[el2_dec_dec_ctl.scala 73:31]
|
|
wire _T_835 = io_ins[19] & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_836 = _T_835 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_837 = _T_836 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_840 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_848 = _T_840 & io_ins[20]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_849 = _T_848 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_850 = _T_849 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_851 = _T_850 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_854 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_856 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_863 = _T_854 & _T_856; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_864 = _T_863 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_865 = _T_864 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_866 = _T_865 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_875 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_876 = _T_875 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_877 = _T_876 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_888 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_889 = _T_888 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_890 = _T_889 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_891 = _T_890 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_906 = _T_888 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_907 = _T_906 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_908 = _T_907 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_909 = _T_908 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_910 = _T_909 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_911 = _T_910 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_924 = _T_888 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_925 = _T_924 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_926 = _T_925 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_927 = _T_926 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_928 = _T_927 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_960 = _T_924 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_961 = _T_960 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_962 = _T_961 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_972 = _T_560 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_973 = _T_972 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_984 = _T_560 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_985 = _T_984 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_986 = _T_985 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_991 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_996 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_997 = _T_996 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1005 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1006 = _T_1005 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1007 = _T_1006 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1008 = _T_1007 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1012 = _T_1008 | _T_189; // @[el2_dec_dec_ctl.scala 87:51]
|
|
wire _T_1018 = _T_4 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1019 = _T_1018 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1020 = _T_1012 | _T_1019; // @[el2_dec_dec_ctl.scala 87:72]
|
|
wire _T_1036 = _T_86 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1037 = _T_1036 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1038 = _T_991 | _T_1037; // @[el2_dec_dec_ctl.scala 89:41]
|
|
wire _T_1045 = _T_71 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1046 = _T_1045 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1047 = _T_1038 | _T_1046; // @[el2_dec_dec_ctl.scala 89:68]
|
|
wire _T_1054 = _T_56 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1055 = _T_1054 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1056 = _T_1047 | _T_1055; // @[el2_dec_dec_ctl.scala 90:30]
|
|
wire _T_1063 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1064 = _T_1063 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1065 = _T_1056 | _T_1064; // @[el2_dec_dec_ctl.scala 90:57]
|
|
wire _T_1072 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1073 = _T_1072 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1074 = _T_1065 | _T_1073; // @[el2_dec_dec_ctl.scala 91:31]
|
|
wire _T_1080 = _T_93 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1081 = _T_1080 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1082 = _T_1074 | _T_1081; // @[el2_dec_dec_ctl.scala 91:59]
|
|
wire _T_1088 = _T_78 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1089 = _T_1088 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1090 = _T_1082 | _T_1089; // @[el2_dec_dec_ctl.scala 92:30]
|
|
wire _T_1096 = _T_63 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1097 = _T_1096 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1098 = _T_1090 | _T_1097; // @[el2_dec_dec_ctl.scala 92:57]
|
|
wire _T_1104 = _T_48 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1105 = _T_1104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1106 = _T_1098 | _T_1105; // @[el2_dec_dec_ctl.scala 93:30]
|
|
wire _T_1112 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1113 = _T_1112 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1129 = _T_840 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1130 = _T_1129 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1131 = _T_1130 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1132 = _T_1131 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1133 = _T_997 | _T_1132; // @[el2_dec_dec_ctl.scala 95:45]
|
|
wire _T_1142 = _T_1133 | _T_1037; // @[el2_dec_dec_ctl.scala 95:78]
|
|
wire _T_1151 = _T_1142 | _T_1046; // @[el2_dec_dec_ctl.scala 96:30]
|
|
wire _T_1160 = _T_1151 | _T_1055; // @[el2_dec_dec_ctl.scala 96:57]
|
|
wire _T_1169 = _T_1160 | _T_1064; // @[el2_dec_dec_ctl.scala 97:30]
|
|
wire _T_1178 = _T_1169 | _T_1073; // @[el2_dec_dec_ctl.scala 97:58]
|
|
wire _T_1186 = _T_1178 | _T_1081; // @[el2_dec_dec_ctl.scala 98:31]
|
|
wire _T_1194 = _T_1186 | _T_1089; // @[el2_dec_dec_ctl.scala 98:58]
|
|
wire _T_1202 = _T_1194 | _T_1097; // @[el2_dec_dec_ctl.scala 99:30]
|
|
wire _T_1210 = _T_1202 | _T_1105; // @[el2_dec_dec_ctl.scala 99:57]
|
|
wire _T_1220 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1226 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1228 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1232 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1234 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1241 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1243 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1245 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1247 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1249 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1253 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1255 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1257 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1259 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1261 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1271 = _T_1220 & _T_247; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1272 = _T_1271 & io_ins[29]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1273 = _T_1272 & io_ins[28]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1274 = _T_1273 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1275 = _T_1274 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1276 = _T_1275 & _T_4; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1277 = _T_1276 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1278 = _T_1277 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1279 = _T_1278 & _T_840; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1280 = _T_1279 & io_ins[21]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1281 = _T_1280 & _T_856; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1282 = _T_1281 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1283 = _T_1282 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1284 = _T_1283 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1285 = _T_1284 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1286 = _T_1285 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1287 = _T_1286 & _T_14; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1288 = _T_1287 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1289 = _T_1288 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1290 = _T_1289 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1291 = _T_1290 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1292 = _T_1291 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1293 = _T_1292 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1294 = _T_1293 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1295 = _T_1294 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1296 = _T_1295 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1297 = _T_1296 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1298 = _T_1297 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1299 = _T_1298 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1305 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1353 = _T_1271 & _T_1305; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1354 = _T_1353 & io_ins[28]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1355 = _T_1354 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1356 = _T_1355 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1357 = _T_1356 & _T_4; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1358 = _T_1357 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1359 = _T_1358 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1360 = _T_1359 & io_ins[22]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1361 = _T_1360 & _T_854; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1362 = _T_1361 & io_ins[20]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1363 = _T_1362 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1364 = _T_1363 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1365 = _T_1364 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1366 = _T_1365 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1367 = _T_1366 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1368 = _T_1367 & _T_14; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1369 = _T_1368 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1370 = _T_1369 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1371 = _T_1370 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1372 = _T_1371 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1373 = _T_1372 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1374 = _T_1373 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1375 = _T_1374 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1376 = _T_1375 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1377 = _T_1376 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1378 = _T_1377 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1379 = _T_1378 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1380 = _T_1379 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1381 = _T_1299 | _T_1380; // @[el2_dec_dec_ctl.scala 101:136]
|
|
wire _T_1389 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 15:46]
|
|
wire _T_1436 = _T_1353 & _T_1389; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1437 = _T_1436 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1438 = _T_1437 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1439 = _T_1438 & _T_4; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1440 = _T_1439 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1441 = _T_1440 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1442 = _T_1441 & _T_840; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1443 = _T_1442 & _T_854; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1444 = _T_1443 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1445 = _T_1444 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1446 = _T_1445 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1447 = _T_1446 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1448 = _T_1447 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1449 = _T_1448 & _T_14; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1450 = _T_1449 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1451 = _T_1450 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1452 = _T_1451 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1453 = _T_1452 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1454 = _T_1453 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1455 = _T_1454 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1456 = _T_1455 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1457 = _T_1456 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1458 = _T_1457 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1459 = _T_1458 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1460 = _T_1459 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1461 = _T_1381 | _T_1460; // @[el2_dec_dec_ctl.scala 102:122]
|
|
wire _T_1489 = _T_1439 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1490 = _T_1489 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1491 = _T_1490 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1492 = _T_1491 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1493 = _T_1492 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1494 = _T_1461 | _T_1493; // @[el2_dec_dec_ctl.scala 103:119]
|
|
wire _T_1521 = _T_1220 & _T_1305; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1522 = _T_1521 & _T_1389; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1523 = _T_1522 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1524 = _T_1523 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1525 = _T_1524 & _T_4; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1526 = _T_1525 & _T_14; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1527 = _T_1526 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1528 = _T_1527 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1529 = _T_1528 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1530 = _T_1529 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1531 = _T_1530 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1532 = _T_1531 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1533 = _T_1532 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1534 = _T_1494 | _T_1533; // @[el2_dec_dec_ctl.scala 104:60]
|
|
wire _T_1563 = _T_1525 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1564 = _T_1563 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1565 = _T_1564 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1566 = _T_1565 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1567 = _T_1566 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1568 = _T_1567 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1569 = _T_1568 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1570 = _T_1569 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1571 = _T_1534 | _T_1570; // @[el2_dec_dec_ctl.scala 105:69]
|
|
wire _T_1597 = _T_1438 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1598 = _T_1597 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1599 = _T_1598 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1600 = _T_1599 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1601 = _T_1600 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1602 = _T_1601 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1603 = _T_1571 | _T_1602; // @[el2_dec_dec_ctl.scala 106:66]
|
|
wire _T_1620 = _T_235 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1621 = _T_1620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1622 = _T_1621 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1623 = _T_1622 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1624 = _T_1623 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1625 = _T_1624 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1626 = _T_1603 | _T_1625; // @[el2_dec_dec_ctl.scala 107:58]
|
|
wire _T_1638 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1640 = _T_1639 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1641 = _T_1640 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1642 = _T_1641 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1643 = _T_1642 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1644 = _T_1643 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1645 = _T_1626 | _T_1644; // @[el2_dec_dec_ctl.scala 108:46]
|
|
wire _T_1657 = _T_143 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1658 = _T_1657 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1659 = _T_1658 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1660 = _T_1659 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1661 = _T_1660 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1662 = _T_1661 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1663 = _T_1645 | _T_1662; // @[el2_dec_dec_ctl.scala 109:40]
|
|
wire _T_1678 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1679 = _T_1678 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1680 = _T_1679 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1681 = _T_1680 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1682 = _T_1681 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1683 = _T_1682 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1684 = _T_1663 | _T_1683; // @[el2_dec_dec_ctl.scala 110:39]
|
|
wire _T_1695 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1696 = _T_1695 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1697 = _T_1696 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1698 = _T_1697 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1699 = _T_1698 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1700 = _T_1699 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1701 = _T_1700 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1702 = _T_1684 | _T_1701; // @[el2_dec_dec_ctl.scala 111:43]
|
|
wire _T_1771 = _T_1443 & _T_856; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1772 = _T_1771 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1773 = _T_1772 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1774 = _T_1773 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1775 = _T_1774 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1776 = _T_1775 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1777 = _T_1776 & _T_14; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1778 = _T_1777 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1779 = _T_1778 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1780 = _T_1779 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1781 = _T_1780 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1782 = _T_1781 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1783 = _T_1782 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1784 = _T_1783 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1785 = _T_1784 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1786 = _T_1785 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1787 = _T_1786 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1788 = _T_1787 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1789 = _T_1788 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1790 = _T_1789 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1791 = _T_1702 | _T_1790; // @[el2_dec_dec_ctl.scala 112:39]
|
|
wire _T_1839 = _T_1436 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1840 = _T_1839 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1841 = _T_1840 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1842 = _T_1841 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1843 = _T_1842 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1844 = _T_1843 & _T_14; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1845 = _T_1844 & _T_16; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1846 = _T_1845 & _T_143; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1847 = _T_1846 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1848 = _T_1847 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1849 = _T_1848 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1850 = _T_1849 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1851 = _T_1850 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1852 = _T_1851 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1853 = _T_1852 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1854 = _T_1853 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1855 = _T_1854 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1856 = _T_1855 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1857 = _T_1856 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1858 = _T_1857 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1859 = _T_1791 | _T_1858; // @[el2_dec_dec_ctl.scala 113:130]
|
|
wire _T_1871 = _T_524 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1872 = _T_1871 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1873 = _T_1872 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1874 = _T_1873 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1875 = _T_1874 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1876 = _T_1875 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1877 = _T_1859 | _T_1876; // @[el2_dec_dec_ctl.scala 114:102]
|
|
wire _T_1892 = _T_16 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1893 = _T_1892 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1894 = _T_1893 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1895 = _T_1894 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1896 = _T_1895 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1897 = _T_1896 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1898 = _T_1897 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1899 = _T_1877 | _T_1898; // @[el2_dec_dec_ctl.scala 115:39]
|
|
wire _T_1908 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1909 = _T_1908 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1910 = _T_1909 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1911 = _T_1910 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1912 = _T_1911 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1913 = _T_1912 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1914 = _T_1899 | _T_1913; // @[el2_dec_dec_ctl.scala 116:43]
|
|
wire _T_1926 = _T_653 & _T_9; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1927 = _T_1926 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1928 = _T_1927 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1929 = _T_1928 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1930 = _T_1929 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1931 = _T_1914 | _T_1930; // @[el2_dec_dec_ctl.scala 117:35]
|
|
wire _T_1947 = _T_582 & _T_103; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1948 = _T_1947 & _T_97; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1949 = _T_1948 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1950 = _T_1949 & _T_18; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1951 = _T_1950 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1952 = _T_1951 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1953 = _T_1931 | _T_1952; // @[el2_dec_dec_ctl.scala 118:38]
|
|
wire _T_1962 = _T_103 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1963 = _T_1962 & _T_99; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1964 = _T_1963 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1965 = _T_1964 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
wire _T_1966 = _T_1965 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17]
|
|
assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 20:14]
|
|
assign io_out_rs1 = _T_101 | _T_106; // @[el2_dec_dec_ctl.scala 21:14]
|
|
assign io_out_rs2 = _T_114 | _T_121; // @[el2_dec_dec_ctl.scala 27:14]
|
|
assign io_out_imm12 = _T_149 | _T_159; // @[el2_dec_dec_ctl.scala 28:16]
|
|
assign io_out_rd = _T_169 | io_ins[4]; // @[el2_dec_dec_ctl.scala 30:13]
|
|
assign io_out_shimm5 = _T_182 & _T_18; // @[el2_dec_dec_ctl.scala 31:17]
|
|
assign io_out_imm20 = _T_186 | _T_189; // @[el2_dec_dec_ctl.scala 32:16]
|
|
assign io_out_pc = _T_197 | _T_186; // @[el2_dec_dec_ctl.scala 33:13]
|
|
assign io_out_load = _T_208 & _T_18; // @[el2_dec_dec_ctl.scala 34:15]
|
|
assign io_out_store = _T_120 & _T_97; // @[el2_dec_dec_ctl.scala 35:16]
|
|
assign io_out_lsu = _T_223 & _T_18; // @[el2_dec_dec_ctl.scala 36:14]
|
|
assign io_out_add = _T_245 | _T_267; // @[el2_dec_dec_ctl.scala 37:14]
|
|
assign io_out_sub = _T_311 | _T_318; // @[el2_dec_dec_ctl.scala 39:14]
|
|
assign io_out_land = _T_330 | _T_344; // @[el2_dec_dec_ctl.scala 41:15]
|
|
assign io_out_lor = _T_381 | _T_393; // @[el2_dec_dec_ctl.scala 42:14]
|
|
assign io_out_lxor = _T_409 | _T_424; // @[el2_dec_dec_ctl.scala 45:15]
|
|
assign io_out_sll = _T_442 & _T_18; // @[el2_dec_dec_ctl.scala 46:14]
|
|
assign io_out_sra = _T_456 & _T_18; // @[el2_dec_dec_ctl.scala 47:14]
|
|
assign io_out_srl = _T_476 & _T_18; // @[el2_dec_dec_ctl.scala 48:14]
|
|
assign io_out_slt = _T_297 | _T_310; // @[el2_dec_dec_ctl.scala 49:14]
|
|
assign io_out_unsign = _T_551 | _T_564; // @[el2_dec_dec_ctl.scala 50:17]
|
|
assign io_out_condbr = _T_317 & _T_18; // @[el2_dec_dec_ctl.scala 53:17]
|
|
assign io_out_beq = _T_584 & _T_18; // @[el2_dec_dec_ctl.scala 54:14]
|
|
assign io_out_bne = _T_596 & _T_18; // @[el2_dec_dec_ctl.scala 55:14]
|
|
assign io_out_bge = _T_607 & _T_18; // @[el2_dec_dec_ctl.scala 56:14]
|
|
assign io_out_blt = _T_619 & _T_18; // @[el2_dec_dec_ctl.scala 57:14]
|
|
assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 58:14]
|
|
assign io_out_by = _T_636 & _T_18; // @[el2_dec_dec_ctl.scala 59:13]
|
|
assign io_out_half = _T_646 & _T_18; // @[el2_dec_dec_ctl.scala 60:15]
|
|
assign io_out_word = _T_653 & _T_97; // @[el2_dec_dec_ctl.scala 61:15]
|
|
assign io_out_csr_read = _T_683 | _T_688; // @[el2_dec_dec_ctl.scala 62:19]
|
|
assign io_out_csr_clr = _T_728 | _T_737; // @[el2_dec_dec_ctl.scala 65:18]
|
|
assign io_out_csr_set = _T_829 | _T_837; // @[el2_dec_dec_ctl.scala 72:18]
|
|
assign io_out_csr_write = _T_745 & io_ins[4]; // @[el2_dec_dec_ctl.scala 68:20]
|
|
assign io_out_csr_imm = _T_786 | _T_793; // @[el2_dec_dec_ctl.scala 69:18]
|
|
assign io_out_presync = _T_1106 | _T_1113; // @[el2_dec_dec_ctl.scala 89:18]
|
|
assign io_out_postsync = _T_1210 | _T_1113; // @[el2_dec_dec_ctl.scala 95:19]
|
|
assign io_out_ebreak = _T_851 & io_ins[4]; // @[el2_dec_dec_ctl.scala 75:17]
|
|
assign io_out_ecall = _T_866 & io_ins[4]; // @[el2_dec_dec_ctl.scala 76:16]
|
|
assign io_out_mret = _T_877 & io_ins[4]; // @[el2_dec_dec_ctl.scala 77:15]
|
|
assign io_out_mul = _T_891 & _T_18; // @[el2_dec_dec_ctl.scala 78:14]
|
|
assign io_out_rs1_sign = _T_911 | _T_928; // @[el2_dec_dec_ctl.scala 79:19]
|
|
assign io_out_rs2_sign = _T_927 & _T_18; // @[el2_dec_dec_ctl.scala 81:19]
|
|
assign io_out_low = _T_962 & _T_18; // @[el2_dec_dec_ctl.scala 82:14]
|
|
assign io_out_div = _T_973 & _T_18; // @[el2_dec_dec_ctl.scala 83:14]
|
|
assign io_out_rem = _T_986 & _T_18; // @[el2_dec_dec_ctl.scala 84:14]
|
|
assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 85:16]
|
|
assign io_out_fence_i = _T_996 & io_ins[3]; // @[el2_dec_dec_ctl.scala 86:18]
|
|
assign io_out_pm_alu = _T_1020 | _T_11; // @[el2_dec_dec_ctl.scala 87:17]
|
|
assign io_out_legal = _T_1953 | _T_1966; // @[el2_dec_dec_ctl.scala 101:16]
|
|
endmodule
|
|
module el2_dec_decode_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_dec_tlu_flush_extint,
|
|
input io_dec_tlu_force_halt,
|
|
output io_dec_extint_stall,
|
|
input [15:0] io_ifu_i0_cinst,
|
|
output [31:0] io_dec_i0_inst_wb1,
|
|
output [30:0] io_dec_i0_pc_wb1,
|
|
input io_lsu_nonblock_load_valid_m,
|
|
input [1:0] io_lsu_nonblock_load_tag_m,
|
|
input io_lsu_nonblock_load_inv_r,
|
|
input [1:0] io_lsu_nonblock_load_inv_tag_r,
|
|
input io_lsu_nonblock_load_data_valid,
|
|
input io_lsu_nonblock_load_data_error,
|
|
input [1:0] io_lsu_nonblock_load_data_tag,
|
|
input [31:0] io_lsu_nonblock_load_data,
|
|
input [3:0] io_dec_i0_trigger_match_d,
|
|
input io_dec_tlu_wr_pause_r,
|
|
input io_dec_tlu_pipelining_disable,
|
|
input [3:0] io_lsu_trigger_match_m,
|
|
input io_lsu_pmu_misaligned_m,
|
|
input io_dec_tlu_debug_stall,
|
|
input io_dec_tlu_flush_leak_one_r,
|
|
input io_dec_debug_fence_d,
|
|
input [1:0] io_dbg_cmd_wrdata,
|
|
input io_dec_i0_icaf_d,
|
|
input io_dec_i0_icaf_f1_d,
|
|
input [1:0] io_dec_i0_icaf_type_d,
|
|
input io_dec_i0_dbecc_d,
|
|
input io_dec_i0_brp_valid,
|
|
input [11:0] io_dec_i0_brp_toffset,
|
|
input [1:0] io_dec_i0_brp_hist,
|
|
input io_dec_i0_brp_br_error,
|
|
input io_dec_i0_brp_br_start_error,
|
|
input [30:0] io_dec_i0_brp_prett,
|
|
input io_dec_i0_brp_way,
|
|
input io_dec_i0_brp_ret,
|
|
input [7:0] io_dec_i0_bp_index,
|
|
input [7:0] io_dec_i0_bp_fghr,
|
|
input [4:0] io_dec_i0_bp_btag,
|
|
input io_lsu_idle_any,
|
|
input io_lsu_load_stall_any,
|
|
input io_lsu_store_stall_any,
|
|
input io_dma_dccm_stall_any,
|
|
input io_exu_div_wren,
|
|
input io_dec_tlu_i0_kill_writeb_wb,
|
|
input io_dec_tlu_flush_lower_wb,
|
|
input io_dec_tlu_i0_kill_writeb_r,
|
|
input io_dec_tlu_flush_lower_r,
|
|
input io_dec_tlu_flush_pause_r,
|
|
input io_dec_tlu_presync_d,
|
|
input io_dec_tlu_postsync_d,
|
|
input io_dec_i0_pc4_d,
|
|
input [31:0] io_dec_csr_rddata_d,
|
|
input io_dec_csr_legal_d,
|
|
input [31:0] io_exu_csr_rs1_x,
|
|
input [31:0] io_lsu_result_m,
|
|
input [31:0] io_lsu_result_corr_r,
|
|
input io_exu_flush_final,
|
|
input [30:0] io_exu_i0_pc_x,
|
|
input [31:0] io_dec_i0_instr_d,
|
|
input io_dec_ib0_valid_d,
|
|
input [31:0] io_exu_i0_result_x,
|
|
input io_free_clk,
|
|
input io_active_clk,
|
|
input io_clk_override,
|
|
output io_dec_i0_rs1_en_d,
|
|
output io_dec_i0_rs2_en_d,
|
|
output [4:0] io_dec_i0_rs1_d,
|
|
output [4:0] io_dec_i0_rs2_d,
|
|
output [31:0] io_dec_i0_immed_d,
|
|
output [11:0] io_dec_i0_br_immed_d,
|
|
output io_i0_ap_land,
|
|
output io_i0_ap_lor,
|
|
output io_i0_ap_lxor,
|
|
output io_i0_ap_sll,
|
|
output io_i0_ap_srl,
|
|
output io_i0_ap_sra,
|
|
output io_i0_ap_beq,
|
|
output io_i0_ap_bne,
|
|
output io_i0_ap_blt,
|
|
output io_i0_ap_bge,
|
|
output io_i0_ap_add,
|
|
output io_i0_ap_sub,
|
|
output io_i0_ap_slt,
|
|
output io_i0_ap_unsign,
|
|
output io_i0_ap_jal,
|
|
output io_i0_ap_predict_t,
|
|
output io_i0_ap_predict_nt,
|
|
output io_i0_ap_csr_write,
|
|
output io_i0_ap_csr_imm,
|
|
output io_dec_i0_decode_d,
|
|
output io_dec_i0_alu_decode_d,
|
|
output [31:0] io_dec_i0_rs1_bypass_data_d,
|
|
output [31:0] io_dec_i0_rs2_bypass_data_d,
|
|
output [4:0] io_dec_i0_waddr_r,
|
|
output io_dec_i0_wen_r,
|
|
output [31:0] io_dec_i0_wdata_r,
|
|
output io_dec_i0_select_pc_d,
|
|
output [1:0] io_dec_i0_rs1_bypass_en_d,
|
|
output [1:0] io_dec_i0_rs2_bypass_en_d,
|
|
output io_lsu_p_valid,
|
|
output io_lsu_p_bits_fast_int,
|
|
output io_lsu_p_bits_by,
|
|
output io_lsu_p_bits_half,
|
|
output io_lsu_p_bits_word,
|
|
output io_lsu_p_bits_load,
|
|
output io_lsu_p_bits_store,
|
|
output io_lsu_p_bits_unsign,
|
|
output io_lsu_p_bits_store_data_bypass_d,
|
|
output io_lsu_p_bits_load_ldst_bypass_d,
|
|
output io_mul_p_valid,
|
|
output io_mul_p_bits_rs1_sign,
|
|
output io_mul_p_bits_rs2_sign,
|
|
output io_mul_p_bits_low,
|
|
output io_div_p_valid,
|
|
output io_div_p_bits_unsign,
|
|
output io_div_p_bits_rem,
|
|
output [4:0] io_div_waddr_wb,
|
|
output io_dec_div_cancel,
|
|
output io_dec_lsu_valid_raw_d,
|
|
output [11:0] io_dec_lsu_offset_d,
|
|
output io_dec_csr_ren_d,
|
|
output io_dec_csr_wen_unq_d,
|
|
output io_dec_csr_any_unq_d,
|
|
output [11:0] io_dec_csr_rdaddr_d,
|
|
output io_dec_csr_wen_r,
|
|
output [11:0] io_dec_csr_wraddr_r,
|
|
output [31:0] io_dec_csr_wrdata_r,
|
|
output io_dec_csr_stall_int_ff,
|
|
output io_dec_tlu_i0_valid_r,
|
|
output io_dec_tlu_packet_r_legal,
|
|
output io_dec_tlu_packet_r_icaf,
|
|
output io_dec_tlu_packet_r_icaf_f1,
|
|
output [1:0] io_dec_tlu_packet_r_icaf_type,
|
|
output io_dec_tlu_packet_r_fence_i,
|
|
output [3:0] io_dec_tlu_packet_r_i0trigger,
|
|
output [3:0] io_dec_tlu_packet_r_pmu_i0_itype,
|
|
output io_dec_tlu_packet_r_pmu_i0_br_unpred,
|
|
output io_dec_tlu_packet_r_pmu_divide,
|
|
output io_dec_tlu_packet_r_pmu_lsu_misaligned,
|
|
output [30:0] io_dec_tlu_i0_pc_r,
|
|
output [31:0] io_dec_illegal_inst,
|
|
output [30:0] io_pred_correct_npc_x,
|
|
output io_dec_i0_predict_p_d_valid,
|
|
output io_dec_i0_predict_p_d_bits_pc4,
|
|
output [1:0] io_dec_i0_predict_p_d_bits_hist,
|
|
output [11:0] io_dec_i0_predict_p_d_bits_toffset,
|
|
output io_dec_i0_predict_p_d_bits_br_error,
|
|
output io_dec_i0_predict_p_d_bits_br_start_error,
|
|
output [30:0] io_dec_i0_predict_p_d_bits_prett,
|
|
output io_dec_i0_predict_p_d_bits_pcall,
|
|
output io_dec_i0_predict_p_d_bits_pret,
|
|
output io_dec_i0_predict_p_d_bits_pja,
|
|
output io_dec_i0_predict_p_d_bits_way,
|
|
output [7:0] io_i0_predict_fghr_d,
|
|
output [7:0] io_i0_predict_index_d,
|
|
output [4:0] io_i0_predict_btag_d,
|
|
output [1:0] io_dec_data_en,
|
|
output [1:0] io_dec_ctl_en,
|
|
output io_dec_pmu_instr_decoded,
|
|
output io_dec_pmu_decode_stall,
|
|
output io_dec_pmu_presync_stall,
|
|
output io_dec_pmu_postsync_stall,
|
|
output io_dec_nonblock_load_wen,
|
|
output [4:0] io_dec_nonblock_load_waddr,
|
|
output io_dec_pause_state,
|
|
output io_dec_pause_state_cg,
|
|
output io_dec_div_active,
|
|
input io_scan_mode
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
reg [31:0] _RAND_75;
|
|
reg [31:0] _RAND_76;
|
|
reg [31:0] _RAND_77;
|
|
reg [31:0] _RAND_78;
|
|
reg [31:0] _RAND_79;
|
|
reg [31:0] _RAND_80;
|
|
reg [31:0] _RAND_81;
|
|
reg [31:0] _RAND_82;
|
|
reg [31:0] _RAND_83;
|
|
reg [31:0] _RAND_84;
|
|
reg [31:0] _RAND_85;
|
|
reg [31:0] _RAND_86;
|
|
reg [31:0] _RAND_87;
|
|
reg [31:0] _RAND_88;
|
|
reg [31:0] _RAND_89;
|
|
reg [31:0] _RAND_90;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire [31:0] i0_dec_io_ins; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 392:22]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_6_io_en; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_7_io_en; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_8_io_en; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_9_io_en; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
reg tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 499:55]
|
|
wire _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 211:51]
|
|
reg tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 500:55]
|
|
wire _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 212:32]
|
|
wire _T_3 = _T_1 | _T_2; // @[el2_dec_decode_ctl.scala 211:73]
|
|
wire _T_4 = io_dec_tlu_flush_extint ^ io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 213:32]
|
|
wire _T_5 = _T_3 | _T_4; // @[el2_dec_decode_ctl.scala 212:56]
|
|
reg leak1_i1_stall; // @[el2_dec_decode_ctl.scala 400:56]
|
|
wire _T_280 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 399:73]
|
|
wire _T_281 = leak1_i1_stall & _T_280; // @[el2_dec_decode_ctl.scala 399:71]
|
|
wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_281; // @[el2_dec_decode_ctl.scala 399:53]
|
|
wire _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[el2_dec_decode_ctl.scala 214:32]
|
|
wire _T_7 = _T_5 | _T_6; // @[el2_dec_decode_ctl.scala 213:56]
|
|
wire _T_284 = io_dec_i0_decode_d & leak1_i1_stall; // @[el2_dec_decode_ctl.scala 402:45]
|
|
reg leak1_i0_stall; // @[el2_dec_decode_ctl.scala 403:56]
|
|
wire _T_286 = leak1_i0_stall & _T_280; // @[el2_dec_decode_ctl.scala 402:81]
|
|
wire leak1_i0_stall_in = _T_284 | _T_286; // @[el2_dec_decode_ctl.scala 402:63]
|
|
wire _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[el2_dec_decode_ctl.scala 215:32]
|
|
wire _T_9 = _T_7 | _T_8; // @[el2_dec_decode_ctl.scala 214:56]
|
|
reg pause_stall; // @[el2_dec_decode_ctl.scala 497:50]
|
|
wire _T_412 = io_dec_tlu_wr_pause_r | pause_stall; // @[el2_dec_decode_ctl.scala 496:44]
|
|
wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[el2_dec_decode_ctl.scala 495:49]
|
|
wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[el2_dec_decode_ctl.scala 495:47]
|
|
reg [31:0] write_csr_data; // @[el2_lib.scala 514:16]
|
|
wire _T_410 = write_csr_data == 32'h0; // @[el2_dec_decode_ctl.scala 495:109]
|
|
wire _T_411 = pause_stall & _T_410; // @[el2_dec_decode_ctl.scala 495:91]
|
|
wire clear_pause = _T_409 | _T_411; // @[el2_dec_decode_ctl.scala 495:76]
|
|
wire _T_413 = ~clear_pause; // @[el2_dec_decode_ctl.scala 496:61]
|
|
wire pause_state_in = _T_412 & _T_413; // @[el2_dec_decode_ctl.scala 496:59]
|
|
wire _T_10 = pause_state_in ^ pause_stall; // @[el2_dec_decode_ctl.scala 216:32]
|
|
wire _T_11 = _T_9 | _T_10; // @[el2_dec_decode_ctl.scala 215:56]
|
|
wire _T_18 = ~leak1_i1_stall; // @[el2_dec_decode_ctl.scala 226:62]
|
|
wire i0_brp_valid = io_dec_i0_brp_valid & _T_18; // @[el2_dec_decode_ctl.scala 226:60]
|
|
wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire [19:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21]}; // @[Cat.scala 29:58]
|
|
wire _T_298 = i0_pcall_imm[19:12] == 8'hff; // @[el2_dec_decode_ctl.scala 408:79]
|
|
wire _T_300 = i0_pcall_imm[19:12] == 8'h0; // @[el2_dec_decode_ctl.scala 408:112]
|
|
wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_298 : _T_300; // @[el2_dec_decode_ctl.scala 408:33]
|
|
wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 409:47]
|
|
wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[el2_dec_decode_ctl.scala 622:16]
|
|
wire _T_302 = i0r_rd == 5'h1; // @[el2_dec_decode_ctl.scala 409:76]
|
|
wire _T_303 = i0r_rd == 5'h5; // @[el2_dec_decode_ctl.scala 409:98]
|
|
wire _T_304 = _T_302 | _T_303; // @[el2_dec_decode_ctl.scala 409:89]
|
|
wire i0_pcall_case = _T_301 & _T_304; // @[el2_dec_decode_ctl.scala 409:65]
|
|
wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 411:38]
|
|
wire _T_20 = i0_dp_raw_condbr | i0_pcall_raw; // @[el2_dec_decode_ctl.scala 237:75]
|
|
wire _T_309 = ~_T_304; // @[el2_dec_decode_ctl.scala 410:67]
|
|
wire i0_pja_case = _T_301 & _T_309; // @[el2_dec_decode_ctl.scala 410:65]
|
|
wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 413:38]
|
|
wire _T_21 = _T_20 | i0_pja_raw; // @[el2_dec_decode_ctl.scala 237:90]
|
|
wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 417:37]
|
|
wire _T_326 = i0r_rd == 5'h0; // @[el2_dec_decode_ctl.scala 417:65]
|
|
wire _T_327 = _T_325 & _T_326; // @[el2_dec_decode_ctl.scala 417:55]
|
|
wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 620:16]
|
|
wire _T_328 = i0r_rs1 == 5'h1; // @[el2_dec_decode_ctl.scala 417:89]
|
|
wire _T_329 = i0r_rs1 == 5'h5; // @[el2_dec_decode_ctl.scala 417:111]
|
|
wire _T_330 = _T_328 | _T_329; // @[el2_dec_decode_ctl.scala 417:101]
|
|
wire i0_pret_case = _T_327 & _T_330; // @[el2_dec_decode_ctl.scala 417:79]
|
|
wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 418:32]
|
|
wire _T_22 = _T_21 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 237:103]
|
|
wire _T_23 = ~_T_22; // @[el2_dec_decode_ctl.scala 237:56]
|
|
wire i0_notbr_error = i0_brp_valid & _T_23; // @[el2_dec_decode_ctl.scala 237:54]
|
|
wire _T_31 = io_dec_i0_brp_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:57]
|
|
wire _T_25 = i0_brp_valid & io_dec_i0_brp_hist[1]; // @[el2_dec_decode_ctl.scala 240:47]
|
|
wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 415:41]
|
|
wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58]
|
|
wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 415:26]
|
|
wire _T_26 = io_dec_i0_brp_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:96]
|
|
wire _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:71]
|
|
wire _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:116]
|
|
wire i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:114]
|
|
wire _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:74]
|
|
wire _T_29 = i0_brp_valid & io_dec_i0_brp_ret; // @[el2_dec_decode_ctl.scala 241:47]
|
|
wire i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:67]
|
|
wire i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:96]
|
|
wire _T_39 = i0_br_error | io_dec_i0_brp_br_start_error; // @[el2_dec_decode_ctl.scala 247:47]
|
|
wire i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:79]
|
|
wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 256:36]
|
|
wire _T_41 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 260:25]
|
|
wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_postsync = _T_41 | i0_dp_raw_postsync; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire _T_439 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[el2_dec_decode_ctl.scala 526:36]
|
|
wire debug_fence_i = io_dec_debug_fence_d & io_dbg_cmd_wrdata[0]; // @[el2_dec_decode_ctl.scala 518:48]
|
|
wire _T_440 = _T_439 | debug_fence_i; // @[el2_dec_decode_ctl.scala 526:60]
|
|
wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_csr_write = _T_41 ? 1'h0 : i0_dp_raw_csr_write; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire _T_343 = ~io_dec_debug_fence_d; // @[el2_dec_decode_ctl.scala 457:42]
|
|
wire i0_csr_write = i0_dp_csr_write & _T_343; // @[el2_dec_decode_ctl.scala 457:40]
|
|
wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_csr_read = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire _T_347 = ~i0_dp_csr_read; // @[el2_dec_decode_ctl.scala 462:41]
|
|
wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 462:39]
|
|
wire _T_442 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[el2_dec_decode_ctl.scala 526:112]
|
|
wire _T_443 = i0_csr_write_only_d & _T_442; // @[el2_dec_decode_ctl.scala 526:99]
|
|
wire i0_postsync = _T_440 | _T_443; // @[el2_dec_decode_ctl.scala 526:76]
|
|
wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_legal = _T_41 | i0_dp_raw_legal; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 528:34]
|
|
wire _T_444 = ~any_csr_d; // @[el2_dec_decode_ctl.scala 530:40]
|
|
wire _T_445 = _T_444 | io_dec_csr_legal_d; // @[el2_dec_decode_ctl.scala 530:51]
|
|
wire i0_legal = i0_dp_legal & _T_445; // @[el2_dec_decode_ctl.scala 530:37]
|
|
wire _T_504 = ~i0_legal; // @[el2_dec_decode_ctl.scala 570:56]
|
|
wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 570:54]
|
|
wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 570:39]
|
|
reg postsync_stall; // @[el2_dec_decode_ctl.scala 568:53]
|
|
reg x_d_i0valid; // @[el2_lib.scala 524:16]
|
|
wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 570:88]
|
|
wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 570:69]
|
|
wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32]
|
|
wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56]
|
|
reg flush_final_r; // @[el2_dec_decode_ctl.scala 616:52]
|
|
wire _T_14 = io_exu_flush_final ^ flush_final_r; // @[el2_dec_decode_ctl.scala 218:32]
|
|
wire _T_15 = _T_13 | _T_14; // @[el2_dec_decode_ctl.scala 217:56]
|
|
wire shift_illegal = io_dec_i0_decode_d & _T_504; // @[el2_dec_decode_ctl.scala 534:47]
|
|
reg illegal_lockout; // @[el2_dec_decode_ctl.scala 538:54]
|
|
wire _T_466 = shift_illegal | illegal_lockout; // @[el2_dec_decode_ctl.scala 537:40]
|
|
wire _T_467 = ~flush_final_r; // @[el2_dec_decode_ctl.scala 537:61]
|
|
wire illegal_lockout_in = _T_466 & _T_467; // @[el2_dec_decode_ctl.scala 537:59]
|
|
wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:32]
|
|
wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 644:46]
|
|
wire _T_33 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 243:72]
|
|
wire _T_36 = io_dec_i0_brp_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:89]
|
|
wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_fence_i = _T_41 ? 1'h0 : i0_dp_raw_fence_i; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_fence = _T_41 ? 1'h0 : i0_dp_raw_fence; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_div = i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_div = _T_41 ? 1'h0 : i0_dp_raw_div; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_low = i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_mul = _T_41 ? 1'h0 : i0_dp_raw_mul; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_mret = _T_41 ? 1'h0 : i0_dp_raw_mret; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_ecall = _T_41 ? 1'h0 : i0_dp_raw_ecall; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_ebreak = _T_41 ? 1'h0 : i0_dp_raw_ebreak; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_presync = _T_41 ? 1'h0 : i0_dp_raw_presync; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_csr_set = _T_41 ? 1'h0 : i0_dp_raw_csr_set; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_csr_clr = _T_41 ? 1'h0 : i0_dp_raw_csr_clr; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_word = i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_word = _T_41 ? 1'h0 : i0_dp_raw_word; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_half = i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_half = _T_41 ? 1'h0 : i0_dp_raw_half; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_by = i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_by = _T_41 ? 1'h0 : i0_dp_raw_by; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_jal = _T_41 ? 1'h0 : i0_dp_raw_jal; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_condbr = _T_41 ? 1'h0 : i0_dp_raw_condbr; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_land = i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_add = i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_lsu = _T_41 ? 1'h0 : i0_dp_raw_lsu; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_store = i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_store = _T_41 ? 1'h0 : i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_load = i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_load = _T_41 ? 1'h0 : i0_dp_raw_load; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_imm20 = _T_41 ? 1'h0 : i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_shimm5 = _T_41 ? 1'h0 : i0_dp_raw_shimm5; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_rd = _T_41 ? 1'h0 : i0_dp_raw_rd; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_imm12 = _T_41 ? 1'h0 : i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_rs2 = _T_41 | i0_dp_raw_rs2; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_rs1 = _T_41 | i0_dp_raw_rs1; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
|
|
wire i0_dp_alu = _T_41 | i0_dp_raw_alu; // @[el2_dec_decode_ctl.scala 260:50]
|
|
wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 412:38]
|
|
wire _T_44 = i0_dp_condbr | i0_pcall; // @[el2_dec_decode_ctl.scala 274:38]
|
|
wire i0_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 414:38]
|
|
wire _T_45 = _T_44 | i0_pja; // @[el2_dec_decode_ctl.scala 274:49]
|
|
wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 419:32]
|
|
wire i0_predict_br = _T_45 | i0_pret; // @[el2_dec_decode_ctl.scala 274:58]
|
|
wire _T_47 = io_dec_i0_brp_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:50]
|
|
wire _T_48 = ~_T_47; // @[el2_dec_decode_ctl.scala 276:26]
|
|
wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 278:20]
|
|
wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 311:63]
|
|
reg [2:0] cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 322:67]
|
|
wire _T_94 = _GEN_123 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
|
wire _T_95 = cam_data_reset & _T_94; // @[el2_dec_decode_ctl.scala 322:45]
|
|
reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 322:83]
|
|
wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 326:39]
|
|
wire _T_51 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 303:78]
|
|
reg [2:0] cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire _T_120 = _GEN_123 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
|
wire _T_121 = cam_data_reset & _T_120; // @[el2_dec_decode_ctl.scala 322:45]
|
|
reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 322:83]
|
|
wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 326:39]
|
|
wire _T_54 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 303:78]
|
|
wire _T_57 = cam_0_valid & _T_54; // @[el2_dec_decode_ctl.scala 303:126]
|
|
wire [1:0] _T_59 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 303:158]
|
|
reg [2:0] cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire _T_146 = _GEN_123 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
|
wire _T_147 = cam_data_reset & _T_146; // @[el2_dec_decode_ctl.scala 322:45]
|
|
reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 322:83]
|
|
wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 326:39]
|
|
wire _T_60 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 303:78]
|
|
wire _T_63 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 303:126]
|
|
wire _T_66 = _T_63 & _T_60; // @[el2_dec_decode_ctl.scala 303:126]
|
|
wire [2:0] _T_68 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 303:158]
|
|
reg [2:0] cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire _T_172 = _GEN_123 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
|
wire _T_173 = cam_data_reset & _T_172; // @[el2_dec_decode_ctl.scala 322:45]
|
|
reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 322:83]
|
|
wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 326:39]
|
|
wire _T_69 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 303:78]
|
|
wire _T_75 = _T_63 & cam_2_valid; // @[el2_dec_decode_ctl.scala 303:126]
|
|
wire _T_78 = _T_75 & _T_69; // @[el2_dec_decode_ctl.scala 303:126]
|
|
wire [3:0] _T_80 = {io_lsu_nonblock_load_valid_m, 3'h0}; // @[el2_dec_decode_ctl.scala 303:158]
|
|
wire _T_81 = _T_51 & io_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_82 = _T_57 ? _T_59 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_83 = _T_66 ? _T_68 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_84 = _T_78 ? _T_80 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_127 = {{1'd0}, _T_81}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_85 = _GEN_127 | _T_82; // @[Mux.scala 27:72]
|
|
wire [2:0] _GEN_128 = {{1'd0}, _T_85}; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_86 = _GEN_128 | _T_83; // @[Mux.scala 27:72]
|
|
wire [3:0] _GEN_129 = {{1'd0}, _T_86}; // @[Mux.scala 27:72]
|
|
wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72]
|
|
reg x_d_i0load; // @[el2_lib.scala 524:16]
|
|
reg [4:0] x_d_i0rd; // @[el2_lib.scala 524:16]
|
|
wire [4:0] nonblock_load_rd = x_d_i0load ? x_d_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31]
|
|
reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 652:72]
|
|
wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58]
|
|
wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 655:49]
|
|
wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 655:53]
|
|
reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20]
|
|
reg r_d_i0load; // @[el2_lib.scala 524:16]
|
|
wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 319:56]
|
|
wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 321:66]
|
|
wire _T_91 = _GEN_130 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
|
wire _T_92 = io_lsu_nonblock_load_inv_r & _T_91; // @[el2_dec_decode_ctl.scala 321:45]
|
|
wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:82]
|
|
reg r_d_i0v; // @[el2_lib.scala 524:16]
|
|
wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:41]
|
|
wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:39]
|
|
wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:42]
|
|
wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:40]
|
|
reg [4:0] r_d_i0rd; // @[el2_lib.scala 524:16]
|
|
reg [4:0] cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire _T_103 = r_d_i0rd == cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
|
wire _T_104 = i0_wen_r & _T_103; // @[el2_dec_decode_ctl.scala 334:64]
|
|
reg cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire _T_106 = _T_104 & cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:95]
|
|
wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[el2_dec_decode_ctl.scala 334:44]
|
|
wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:116]
|
|
wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:116]
|
|
wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 329:28]
|
|
wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 329:28]
|
|
wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[el2_dec_decode_ctl.scala 339:44]
|
|
wire _T_112 = _T_110 & cam_0_valid; // @[el2_dec_decode_ctl.scala 339:95]
|
|
wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 348:66]
|
|
wire _T_117 = _GEN_130 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
|
wire _T_118 = io_lsu_nonblock_load_inv_r & _T_117; // @[el2_dec_decode_ctl.scala 321:45]
|
|
wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:82]
|
|
reg [4:0] cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire _T_129 = r_d_i0rd == cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
|
wire _T_130 = i0_wen_r & _T_129; // @[el2_dec_decode_ctl.scala 334:64]
|
|
reg cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire _T_132 = _T_130 & cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:95]
|
|
wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[el2_dec_decode_ctl.scala 334:44]
|
|
wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:116]
|
|
wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:116]
|
|
wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 329:28]
|
|
wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 329:28]
|
|
wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[el2_dec_decode_ctl.scala 339:44]
|
|
wire _T_138 = _T_136 & cam_1_valid; // @[el2_dec_decode_ctl.scala 339:95]
|
|
wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 348:66]
|
|
wire _T_143 = _GEN_130 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
|
wire _T_144 = io_lsu_nonblock_load_inv_r & _T_143; // @[el2_dec_decode_ctl.scala 321:45]
|
|
wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:82]
|
|
reg [4:0] cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire _T_155 = r_d_i0rd == cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
|
wire _T_156 = i0_wen_r & _T_155; // @[el2_dec_decode_ctl.scala 334:64]
|
|
reg cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire _T_158 = _T_156 & cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:95]
|
|
wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[el2_dec_decode_ctl.scala 334:44]
|
|
wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:116]
|
|
wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:116]
|
|
wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 329:28]
|
|
wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 329:28]
|
|
wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[el2_dec_decode_ctl.scala 339:44]
|
|
wire _T_164 = _T_162 & cam_2_valid; // @[el2_dec_decode_ctl.scala 339:95]
|
|
wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 348:66]
|
|
wire _T_169 = _GEN_130 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
|
wire _T_170 = io_lsu_nonblock_load_inv_r & _T_169; // @[el2_dec_decode_ctl.scala 321:45]
|
|
wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:82]
|
|
reg [4:0] cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire _T_181 = r_d_i0rd == cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
|
wire _T_182 = i0_wen_r & _T_181; // @[el2_dec_decode_ctl.scala 334:64]
|
|
reg cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
|
wire _T_184 = _T_182 & cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:95]
|
|
wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[el2_dec_decode_ctl.scala 334:44]
|
|
wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:116]
|
|
wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:116]
|
|
wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 329:28]
|
|
wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 329:28]
|
|
wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[el2_dec_decode_ctl.scala 339:44]
|
|
wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:95]
|
|
wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:66]
|
|
wire _T_195 = r_d_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:44]
|
|
wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:76]
|
|
wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 354:95]
|
|
wire _T_197 = _T_196 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 354:95]
|
|
wire _T_198 = _T_197 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 354:95]
|
|
wire _T_200 = io_lsu_nonblock_load_data_valid & _T_198; // @[el2_dec_decode_ctl.scala 354:64]
|
|
wire _T_201 = ~nonblock_load_cancel; // @[el2_dec_decode_ctl.scala 354:109]
|
|
wire _T_203 = nonblock_load_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 355:54]
|
|
wire _T_204 = _T_203 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 355:66]
|
|
wire _T_205 = _T_204 & io_dec_i0_rs1_en_d; // @[el2_dec_decode_ctl.scala 355:97]
|
|
wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 621:16]
|
|
wire _T_206 = nonblock_load_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 355:137]
|
|
wire _T_207 = _T_206 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 355:149]
|
|
wire _T_208 = _T_207 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 355:180]
|
|
wire i0_nonblock_boundary_stall = _T_205 | _T_208; // @[el2_dec_decode_ctl.scala 355:118]
|
|
wire [4:0] _T_210 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
|
wire [4:0] _T_211 = _T_210 & cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
|
wire _T_212 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:121]
|
|
wire _T_213 = cam_raw_0_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149]
|
|
wire _T_214 = _T_212 & _T_213; // @[el2_dec_decode_ctl.scala 359:136]
|
|
wire _T_215 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:182]
|
|
wire _T_216 = cam_raw_0_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210]
|
|
wire _T_217 = _T_215 & _T_216; // @[el2_dec_decode_ctl.scala 359:197]
|
|
wire [4:0] _T_219 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
|
wire [4:0] _T_220 = _T_219 & cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
|
wire _T_221 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:121]
|
|
wire _T_222 = cam_raw_1_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149]
|
|
wire _T_223 = _T_221 & _T_222; // @[el2_dec_decode_ctl.scala 359:136]
|
|
wire _T_224 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:182]
|
|
wire _T_225 = cam_raw_1_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210]
|
|
wire _T_226 = _T_224 & _T_225; // @[el2_dec_decode_ctl.scala 359:197]
|
|
wire [4:0] _T_228 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
|
wire [4:0] _T_229 = _T_228 & cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
|
wire _T_230 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:121]
|
|
wire _T_231 = cam_raw_2_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149]
|
|
wire _T_232 = _T_230 & _T_231; // @[el2_dec_decode_ctl.scala 359:136]
|
|
wire _T_233 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:182]
|
|
wire _T_234 = cam_raw_2_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210]
|
|
wire _T_235 = _T_233 & _T_234; // @[el2_dec_decode_ctl.scala 359:197]
|
|
wire [4:0] _T_237 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
|
wire [4:0] _T_238 = _T_237 & cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
|
wire _T_239 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:121]
|
|
wire _T_240 = cam_raw_3_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149]
|
|
wire _T_241 = _T_239 & _T_240; // @[el2_dec_decode_ctl.scala 359:136]
|
|
wire _T_242 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:182]
|
|
wire _T_243 = cam_raw_3_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210]
|
|
wire _T_244 = _T_242 & _T_243; // @[el2_dec_decode_ctl.scala 359:197]
|
|
wire [4:0] _T_245 = _T_211 | _T_220; // @[el2_dec_decode_ctl.scala 360:69]
|
|
wire [4:0] _T_246 = _T_245 | _T_229; // @[el2_dec_decode_ctl.scala 360:69]
|
|
wire _T_247 = _T_214 | _T_223; // @[el2_dec_decode_ctl.scala 360:102]
|
|
wire _T_248 = _T_247 | _T_232; // @[el2_dec_decode_ctl.scala 360:102]
|
|
wire ld_stall_1 = _T_248 | _T_241; // @[el2_dec_decode_ctl.scala 360:102]
|
|
wire _T_249 = _T_217 | _T_226; // @[el2_dec_decode_ctl.scala 360:134]
|
|
wire _T_250 = _T_249 | _T_235; // @[el2_dec_decode_ctl.scala 360:134]
|
|
wire ld_stall_2 = _T_250 | _T_244; // @[el2_dec_decode_ctl.scala 360:134]
|
|
wire _T_251 = ld_stall_1 | ld_stall_2; // @[el2_dec_decode_ctl.scala 362:38]
|
|
wire i0_nonblock_load_stall = _T_251 | i0_nonblock_boundary_stall; // @[el2_dec_decode_ctl.scala 362:51]
|
|
wire _T_253 = ~i0_predict_br; // @[el2_dec_decode_ctl.scala 371:34]
|
|
wire [3:0] _T_255 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 455:36]
|
|
wire _T_256 = csr_read & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 383:16]
|
|
wire _T_258 = ~csr_read; // @[el2_dec_decode_ctl.scala 384:6]
|
|
wire _T_259 = _T_258 & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 384:16]
|
|
wire _T_261 = ~io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 385:18]
|
|
wire _T_262 = csr_read & _T_261; // @[el2_dec_decode_ctl.scala 385:16]
|
|
wire [3:0] _T_264 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_265 = i0_dp_load ? 4'h2 : _T_264; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_266 = i0_dp_store ? 4'h3 : _T_265; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_267 = i0_dp_pm_alu ? 4'h4 : _T_266; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_268 = _T_262 ? 4'h5 : _T_267; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_269 = _T_259 ? 4'h6 : _T_268; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_270 = _T_256 ? 4'h7 : _T_269; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_271 = i0_dp_ebreak ? 4'h8 : _T_270; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_272 = i0_dp_ecall ? 4'h9 : _T_271; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_273 = i0_dp_fence ? 4'ha : _T_272; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_274 = i0_dp_fence_i ? 4'hb : _T_273; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_275 = i0_dp_mret ? 4'hc : _T_274; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_276 = i0_dp_condbr ? 4'hd : _T_275; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_277 = i0_dp_jal ? 4'he : _T_276; // @[Mux.scala 98:16]
|
|
reg lsu_idle; // @[el2_dec_decode_ctl.scala 396:45]
|
|
wire _T_333 = ~i0_pcall_case; // @[el2_dec_decode_ctl.scala 420:35]
|
|
wire _T_334 = i0_dp_jal & _T_333; // @[el2_dec_decode_ctl.scala 420:32]
|
|
wire _T_335 = ~i0_pja_case; // @[el2_dec_decode_ctl.scala 420:52]
|
|
wire _T_336 = _T_334 & _T_335; // @[el2_dec_decode_ctl.scala 420:50]
|
|
wire _T_337 = ~i0_pret_case; // @[el2_dec_decode_ctl.scala 420:67]
|
|
reg _T_339; // @[el2_dec_decode_ctl.scala 432:58]
|
|
wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 574:40]
|
|
wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 788:43]
|
|
reg x_d_i0v; // @[el2_lib.scala 524:16]
|
|
wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 768:48]
|
|
wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:70]
|
|
wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:58]
|
|
wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 769:48]
|
|
wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:70]
|
|
wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:58]
|
|
wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 775:63]
|
|
wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 775:24]
|
|
wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 788:58]
|
|
reg i0_x_c_load; // @[Reg.scala 15:16]
|
|
reg i0_r_c_load; // @[Reg.scala 15:16]
|
|
wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 774:61]
|
|
wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 774:24]
|
|
wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 788:78]
|
|
wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 771:48]
|
|
wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:70]
|
|
wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:58]
|
|
wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 772:48]
|
|
wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:70]
|
|
wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:58]
|
|
wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 777:63]
|
|
wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 777:24]
|
|
wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 789:43]
|
|
wire _T_896_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 776:61]
|
|
wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 776:24]
|
|
wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 789:63]
|
|
wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 463:42]
|
|
reg r_d_csrwen; // @[el2_lib.scala 524:16]
|
|
reg r_d_i0valid; // @[el2_lib.scala 524:16]
|
|
wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 471:34]
|
|
reg [11:0] r_d_csrwaddr; // @[el2_lib.scala 524:16]
|
|
wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:45]
|
|
wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:75]
|
|
wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:59]
|
|
wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 474:90]
|
|
wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 474:103]
|
|
wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:119]
|
|
reg csr_read_x; // @[el2_dec_decode_ctl.scala 476:52]
|
|
reg csr_clr_x; // @[el2_dec_decode_ctl.scala 477:51]
|
|
reg csr_set_x; // @[el2_dec_decode_ctl.scala 478:51]
|
|
reg csr_write_x; // @[el2_dec_decode_ctl.scala 479:53]
|
|
reg csr_imm_x; // @[el2_dec_decode_ctl.scala 480:51]
|
|
wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[el2_dec_decode_ctl.scala 657:50]
|
|
reg [4:0] csrimm_x; // @[el2_lib.scala 514:16]
|
|
reg [31:0] csr_rddata_x; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_394 = {27'h0,csrimm_x}; // @[Cat.scala 29:58]
|
|
wire _T_396 = ~csr_imm_x; // @[el2_dec_decode_ctl.scala 488:5]
|
|
wire [31:0] _T_397 = csr_imm_x ? _T_394 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_398 = _T_396 ? io_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] csr_mask_x = _T_397 | _T_398; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_400 = ~csr_mask_x; // @[el2_dec_decode_ctl.scala 491:38]
|
|
wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[el2_dec_decode_ctl.scala 491:35]
|
|
wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[el2_dec_decode_ctl.scala 492:35]
|
|
wire [31:0] _T_403 = csr_clr_x ? _T_401 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_404 = csr_set_x ? _T_402 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_405 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_406 = _T_403 | _T_404; // @[Mux.scala 27:72]
|
|
wire [31:0] write_csr_data_x = _T_406 | _T_405; // @[Mux.scala 27:72]
|
|
wire _T_418 = ~tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 502:44]
|
|
wire _T_419 = ~tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 502:64]
|
|
wire _T_420 = _T_418 & _T_419; // @[el2_dec_decode_ctl.scala 502:61]
|
|
wire [31:0] _T_423 = write_csr_data - 32'h1; // @[el2_dec_decode_ctl.scala 505:59]
|
|
wire _T_425 = csr_clr_x | csr_set_x; // @[el2_dec_decode_ctl.scala 507:34]
|
|
wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 507:46]
|
|
wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 507:61]
|
|
wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 507:75]
|
|
reg r_d_csrwonly; // @[el2_lib.scala 524:16]
|
|
wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 710:37]
|
|
reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16]
|
|
wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 710:27]
|
|
reg x_d_csrwonly; // @[el2_lib.scala 524:16]
|
|
wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 516:38]
|
|
reg wbd_csrwonly; // @[el2_lib.scala 524:16]
|
|
wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 516:53]
|
|
wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 519:48]
|
|
wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 520:40]
|
|
wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 523:34]
|
|
wire _T_437 = _T_436 | debug_fence_i; // @[el2_dec_decode_ctl.scala 523:57]
|
|
wire _T_438 = _T_437 | debug_fence_raw; // @[el2_dec_decode_ctl.scala 523:73]
|
|
wire i0_presync = _T_438 | io_dec_tlu_pipelining_disable; // @[el2_dec_decode_ctl.scala 523:91]
|
|
wire [31:0] _T_462 = {16'h0,io_ifu_i0_cinst}; // @[Cat.scala 29:58]
|
|
wire _T_464 = ~illegal_lockout; // @[el2_dec_decode_ctl.scala 535:44]
|
|
reg [31:0] _T_465; // @[el2_lib.scala 514:16]
|
|
wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[el2_dec_decode_ctl.scala 539:42]
|
|
wire _T_470 = i0_dp_csr_read & prior_csr_write; // @[el2_dec_decode_ctl.scala 541:40]
|
|
wire _T_471 = _T_470 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 541:59]
|
|
wire _T_472 = _T_471 | pause_stall; // @[el2_dec_decode_ctl.scala 541:81]
|
|
wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 541:95]
|
|
wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 542:20]
|
|
wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 542:45]
|
|
wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 564:41]
|
|
wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31]
|
|
wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 567:37]
|
|
wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 542:62]
|
|
wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 543:19]
|
|
wire _T_478 = ~lsu_idle; // @[el2_dec_decode_ctl.scala 543:36]
|
|
wire _T_479 = _T_477 & _T_478; // @[el2_dec_decode_ctl.scala 543:34]
|
|
wire _T_480 = _T_476 | _T_479; // @[el2_dec_decode_ctl.scala 542:79]
|
|
wire _T_481 = _T_480 | i0_nonblock_load_stall; // @[el2_dec_decode_ctl.scala 543:47]
|
|
wire _T_822 = io_dec_i0_rs1_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 738:49]
|
|
wire _T_823 = io_div_waddr_wb == i0r_rs1; // @[el2_dec_decode_ctl.scala 738:88]
|
|
wire _T_824 = _T_822 & _T_823; // @[el2_dec_decode_ctl.scala 738:69]
|
|
wire _T_825 = io_dec_i0_rs2_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 739:25]
|
|
wire _T_826 = io_div_waddr_wb == i0r_rs2; // @[el2_dec_decode_ctl.scala 739:64]
|
|
wire _T_827 = _T_825 & _T_826; // @[el2_dec_decode_ctl.scala 739:45]
|
|
wire i0_nonblock_div_stall = _T_824 | _T_827; // @[el2_dec_decode_ctl.scala 738:102]
|
|
wire _T_483 = _T_481 | i0_nonblock_div_stall; // @[el2_dec_decode_ctl.scala 544:21]
|
|
wire i0_block_raw_d = _T_483 | i0_div_prior_div_stall; // @[el2_dec_decode_ctl.scala 544:45]
|
|
wire _T_484 = io_lsu_store_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 546:65]
|
|
wire i0_store_stall_d = i0_dp_store & _T_484; // @[el2_dec_decode_ctl.scala 546:39]
|
|
wire _T_485 = io_lsu_load_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 547:63]
|
|
wire i0_load_stall_d = i0_dp_load & _T_485; // @[el2_dec_decode_ctl.scala 547:38]
|
|
wire _T_486 = i0_block_raw_d | i0_store_stall_d; // @[el2_dec_decode_ctl.scala 548:38]
|
|
wire i0_block_d = _T_486 | i0_load_stall_d; // @[el2_dec_decode_ctl.scala 548:57]
|
|
wire _T_487 = ~i0_block_d; // @[el2_dec_decode_ctl.scala 552:46]
|
|
wire _T_488 = io_dec_ib0_valid_d & _T_487; // @[el2_dec_decode_ctl.scala 552:44]
|
|
wire _T_490 = _T_488 & _T_280; // @[el2_dec_decode_ctl.scala 552:61]
|
|
wire _T_493 = ~i0_block_raw_d; // @[el2_dec_decode_ctl.scala 553:46]
|
|
wire _T_494 = io_dec_ib0_valid_d & _T_493; // @[el2_dec_decode_ctl.scala 553:44]
|
|
wire _T_496 = _T_494 & _T_280; // @[el2_dec_decode_ctl.scala 553:61]
|
|
wire i0_exudecode_d = _T_496 & _T_467; // @[el2_dec_decode_ctl.scala 553:89]
|
|
wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[el2_dec_decode_ctl.scala 554:46]
|
|
wire _T_498 = ~io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 558:51]
|
|
wire _T_517 = i0_dp_fence_i | debug_fence_i; // @[el2_dec_decode_ctl.scala 586:44]
|
|
wire [3:0] _T_522 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58]
|
|
wire _T_704 = |i0_pipe_en[3:2]; // @[el2_dec_decode_ctl.scala 654:49]
|
|
wire i0_x_ctl_en = _T_704 | io_clk_override; // @[el2_dec_decode_ctl.scala 654:53]
|
|
reg x_t_legal; // @[el2_lib.scala 524:16]
|
|
reg x_t_icaf; // @[el2_lib.scala 524:16]
|
|
reg x_t_icaf_f1; // @[el2_lib.scala 524:16]
|
|
reg [1:0] x_t_icaf_type; // @[el2_lib.scala 524:16]
|
|
reg x_t_fence_i; // @[el2_lib.scala 524:16]
|
|
reg [3:0] x_t_i0trigger; // @[el2_lib.scala 524:16]
|
|
reg [3:0] x_t_pmu_i0_itype; // @[el2_lib.scala 524:16]
|
|
reg x_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16]
|
|
wire [3:0] _T_530 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_531 = ~_T_530; // @[el2_dec_decode_ctl.scala 599:39]
|
|
reg r_t_legal; // @[el2_lib.scala 524:16]
|
|
reg r_t_icaf; // @[el2_lib.scala 524:16]
|
|
reg r_t_icaf_f1; // @[el2_lib.scala 524:16]
|
|
reg [1:0] r_t_icaf_type; // @[el2_lib.scala 524:16]
|
|
reg r_t_fence_i; // @[el2_lib.scala 524:16]
|
|
reg [3:0] r_t_i0trigger; // @[el2_lib.scala 524:16]
|
|
reg [3:0] r_t_pmu_i0_itype; // @[el2_lib.scala 524:16]
|
|
reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16]
|
|
reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 602:36]
|
|
reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 603:37]
|
|
reg r_d_i0store; // @[el2_lib.scala 524:16]
|
|
wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 607:56]
|
|
wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:72]
|
|
wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:95]
|
|
reg r_d_i0div; // @[el2_lib.scala 524:16]
|
|
wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 613:53]
|
|
wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 624:49]
|
|
wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 625:49]
|
|
wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 626:48]
|
|
wire i0_rd_en_d = i0_dp_rd & _T_560; // @[el2_dec_decode_ctl.scala 626:37]
|
|
wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 630:38]
|
|
wire _T_561 = ~i0_dp_jal; // @[el2_dec_decode_ctl.scala 631:27]
|
|
wire i0_uiimm20 = _T_561 & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 631:38]
|
|
wire [31:0] _T_563 = i0_dp_csr_read ? io_dec_csr_rddata_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [9:0] _T_577 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_586 = {_T_577,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_589 = {_T_586,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31:20]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_684 = i0_dp_imm12 ? _T_589 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_618 = {27'h0,i0r_rs2}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_685 = i0_dp_shimm5 ? _T_618 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_689 = _T_684 | _T_685; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_638 = {_T_577,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_686 = i0_jalimm20 ? _T_638 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_690 = _T_689 | _T_686; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_652 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_687 = i0_uiimm20 ? _T_652 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_691 = _T_690 | _T_687; // @[Mux.scala 27:72]
|
|
wire _T_653 = i0_csr_write_only_d & i0_dp_csr_imm; // @[el2_dec_decode_ctl.scala 642:26]
|
|
wire [31:0] _T_683 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_688 = _T_653 ? _T_683 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] i0_immed_d = _T_691 | _T_688; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_564 = _T_347 ? i0_immed_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 646:44]
|
|
wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 647:44]
|
|
wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 648:44]
|
|
reg i0_x_c_mul; // @[Reg.scala 15:16]
|
|
reg i0_x_c_alu; // @[Reg.scala 15:16]
|
|
reg i0_r_c_mul; // @[Reg.scala 15:16]
|
|
reg i0_r_c_alu; // @[Reg.scala 15:16]
|
|
wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 656:49]
|
|
wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 658:50]
|
|
reg x_d_i0store; // @[el2_lib.scala 524:16]
|
|
reg x_d_i0div; // @[el2_lib.scala 524:16]
|
|
reg x_d_csrwen; // @[el2_lib.scala 524:16]
|
|
reg [11:0] x_d_csrwaddr; // @[el2_lib.scala 524:16]
|
|
wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:37]
|
|
wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 681:37]
|
|
wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 696:49]
|
|
wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 696:47]
|
|
wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:65]
|
|
wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 705:42]
|
|
wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 711:52]
|
|
wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58]
|
|
reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16]
|
|
wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 719:40]
|
|
wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:55]
|
|
wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:69]
|
|
wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:57]
|
|
wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:30]
|
|
wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:86]
|
|
wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:30]
|
|
wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:57]
|
|
wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:59]
|
|
wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 727:51]
|
|
wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 728:26]
|
|
wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 728:24]
|
|
wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:51]
|
|
wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 728:39]
|
|
wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:72]
|
|
wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 727:65]
|
|
wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 731:55]
|
|
wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 733:62]
|
|
wire _T_818 = io_dec_div_active & _T_817; // @[el2_dec_decode_ctl.scala 733:60]
|
|
wire _T_819 = ~nonblock_div_cancel; // @[el2_dec_decode_ctl.scala 733:81]
|
|
wire _T_820 = _T_818 & _T_819; // @[el2_dec_decode_ctl.scala 733:79]
|
|
reg _T_821; // @[el2_dec_decode_ctl.scala 735:54]
|
|
reg [4:0] _T_830; // @[Reg.scala 27:20]
|
|
reg [31:0] i0_inst_x; // @[el2_lib.scala 514:16]
|
|
reg [31:0] i0_inst_r; // @[el2_lib.scala 514:16]
|
|
reg [31:0] i0_inst_wb; // @[el2_lib.scala 514:16]
|
|
reg [31:0] _T_837; // @[el2_lib.scala 514:16]
|
|
reg [30:0] i0_pc_wb; // @[el2_lib.scala 514:16]
|
|
reg [30:0] _T_840; // @[el2_lib.scala 514:16]
|
|
reg [30:0] dec_i0_pc_r; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_842 = {io_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_843 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_846 = _T_842[12:1] + _T_843[12:1]; // @[el2_lib.scala 208:31]
|
|
wire [18:0] _T_849 = _T_842[31:13] + 19'h1; // @[el2_lib.scala 209:27]
|
|
wire [18:0] _T_852 = _T_842[31:13] - 19'h1; // @[el2_lib.scala 210:27]
|
|
wire _T_855 = ~_T_846[12]; // @[el2_lib.scala 212:28]
|
|
wire _T_856 = _T_843[12] ^ _T_855; // @[el2_lib.scala 212:26]
|
|
wire _T_859 = ~_T_843[12]; // @[el2_lib.scala 213:20]
|
|
wire _T_861 = _T_859 & _T_846[12]; // @[el2_lib.scala 213:26]
|
|
wire _T_865 = _T_843[12] & _T_855; // @[el2_lib.scala 214:26]
|
|
wire [18:0] _T_867 = _T_856 ? _T_842[31:13] : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_868 = _T_861 ? _T_849 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_869 = _T_865 ? _T_852 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_870 = _T_867 | _T_868; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_871 = _T_870 | _T_869; // @[Mux.scala 27:72]
|
|
wire [31:0] temp_pred_correct_npc_x = {_T_871,_T_846[11:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_887_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 774:61]
|
|
wire _T_887_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 774:61]
|
|
wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_887_mul; // @[el2_dec_decode_ctl.scala 774:24]
|
|
wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_887_alu; // @[el2_dec_decode_ctl.scala 774:24]
|
|
wire _T_896_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 776:61]
|
|
wire _T_896_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 776:61]
|
|
wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_896_mul; // @[el2_dec_decode_ctl.scala 776:24]
|
|
wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_896_alu; // @[el2_dec_decode_ctl.scala 776:24]
|
|
wire _T_909 = io_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 794:62]
|
|
wire _T_910 = io_dec_nonblock_load_waddr == i0r_rs1; // @[el2_dec_decode_ctl.scala 794:119]
|
|
wire i0_rs1_nonblock_load_bypass_en_d = _T_909 & _T_910; // @[el2_dec_decode_ctl.scala 794:89]
|
|
wire _T_911 = io_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 796:62]
|
|
wire _T_912 = io_dec_nonblock_load_waddr == i0r_rs2; // @[el2_dec_decode_ctl.scala 796:119]
|
|
wire i0_rs2_nonblock_load_bypass_en_d = _T_911 & _T_912; // @[el2_dec_decode_ctl.scala 796:89]
|
|
wire _T_914 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[el2_dec_decode_ctl.scala 799:66]
|
|
wire _T_915 = i0_rs1_depth_d[0] & _T_914; // @[el2_dec_decode_ctl.scala 799:45]
|
|
wire _T_917 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 799:108]
|
|
wire _T_920 = _T_914 | i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 799:196]
|
|
wire _T_921 = i0_rs1_depth_d[1] & _T_920; // @[el2_dec_decode_ctl.scala 799:153]
|
|
wire [2:0] i0_rs1bypass = {_T_915,_T_917,_T_921}; // @[Cat.scala 29:58]
|
|
wire _T_925 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[el2_dec_decode_ctl.scala 801:67]
|
|
wire _T_926 = i0_rs2_depth_d[0] & _T_925; // @[el2_dec_decode_ctl.scala 801:45]
|
|
wire _T_928 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 801:109]
|
|
wire _T_931 = _T_925 | i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 801:196]
|
|
wire _T_932 = i0_rs2_depth_d[1] & _T_931; // @[el2_dec_decode_ctl.scala 801:153]
|
|
wire [2:0] i0_rs2bypass = {_T_926,_T_928,_T_932}; // @[Cat.scala 29:58]
|
|
wire _T_938 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 803:75]
|
|
wire _T_940 = ~i0_rs1bypass[2]; // @[el2_dec_decode_ctl.scala 803:96]
|
|
wire _T_941 = _T_940 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 803:113]
|
|
wire _T_942 = _T_938 | _T_941; // @[el2_dec_decode_ctl.scala 803:93]
|
|
wire _T_947 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 804:75]
|
|
wire _T_949 = ~i0_rs2bypass[2]; // @[el2_dec_decode_ctl.scala 804:96]
|
|
wire _T_950 = _T_949 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 804:113]
|
|
wire _T_951 = _T_947 | _T_950; // @[el2_dec_decode_ctl.scala 804:93]
|
|
wire _T_958 = ~i0_rs1bypass[1]; // @[el2_dec_decode_ctl.scala 810:6]
|
|
wire _T_960 = ~i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 810:25]
|
|
wire _T_961 = _T_958 & _T_960; // @[el2_dec_decode_ctl.scala 810:23]
|
|
wire _T_962 = _T_961 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 810:42]
|
|
wire [31:0] _T_964 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_965 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_966 = _T_962 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_967 = _T_964 | _T_965; // @[Mux.scala 27:72]
|
|
wire _T_975 = ~i0_rs2bypass[1]; // @[el2_dec_decode_ctl.scala 815:6]
|
|
wire _T_977 = ~i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 815:25]
|
|
wire _T_978 = _T_975 & _T_977; // @[el2_dec_decode_ctl.scala 815:23]
|
|
wire _T_979 = _T_978 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 815:42]
|
|
wire [31:0] _T_981 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_982 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_983 = _T_979 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_984 = _T_981 | _T_982; // @[Mux.scala 27:72]
|
|
wire _T_987 = i0_dp_raw_load | i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 817:68]
|
|
wire _T_988 = io_dec_ib0_valid_d & _T_987; // @[el2_dec_decode_ctl.scala 817:50]
|
|
wire _T_989 = ~io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 817:89]
|
|
wire _T_990 = _T_988 & _T_989; // @[el2_dec_decode_ctl.scala 817:87]
|
|
wire _T_992 = _T_990 & _T_493; // @[el2_dec_decode_ctl.scala 817:112]
|
|
wire _T_994 = ~io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 819:6]
|
|
wire _T_995 = _T_994 & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 819:27]
|
|
wire _T_996 = _T_995 & i0_dp_load; // @[el2_dec_decode_ctl.scala 819:39]
|
|
wire _T_1001 = _T_995 & i0_dp_store; // @[el2_dec_decode_ctl.scala 820:39]
|
|
wire [11:0] _T_1005 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1006 = _T_996 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1007 = _T_1001 ? _T_1005 : 12'h0; // @[Mux.scala 27:72]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
el2_dec_dec_ctl i0_dec ( // @[el2_dec_decode_ctl.scala 392:22]
|
|
.io_ins(i0_dec_io_ins),
|
|
.io_out_alu(i0_dec_io_out_alu),
|
|
.io_out_rs1(i0_dec_io_out_rs1),
|
|
.io_out_rs2(i0_dec_io_out_rs2),
|
|
.io_out_imm12(i0_dec_io_out_imm12),
|
|
.io_out_rd(i0_dec_io_out_rd),
|
|
.io_out_shimm5(i0_dec_io_out_shimm5),
|
|
.io_out_imm20(i0_dec_io_out_imm20),
|
|
.io_out_pc(i0_dec_io_out_pc),
|
|
.io_out_load(i0_dec_io_out_load),
|
|
.io_out_store(i0_dec_io_out_store),
|
|
.io_out_lsu(i0_dec_io_out_lsu),
|
|
.io_out_add(i0_dec_io_out_add),
|
|
.io_out_sub(i0_dec_io_out_sub),
|
|
.io_out_land(i0_dec_io_out_land),
|
|
.io_out_lor(i0_dec_io_out_lor),
|
|
.io_out_lxor(i0_dec_io_out_lxor),
|
|
.io_out_sll(i0_dec_io_out_sll),
|
|
.io_out_sra(i0_dec_io_out_sra),
|
|
.io_out_srl(i0_dec_io_out_srl),
|
|
.io_out_slt(i0_dec_io_out_slt),
|
|
.io_out_unsign(i0_dec_io_out_unsign),
|
|
.io_out_condbr(i0_dec_io_out_condbr),
|
|
.io_out_beq(i0_dec_io_out_beq),
|
|
.io_out_bne(i0_dec_io_out_bne),
|
|
.io_out_bge(i0_dec_io_out_bge),
|
|
.io_out_blt(i0_dec_io_out_blt),
|
|
.io_out_jal(i0_dec_io_out_jal),
|
|
.io_out_by(i0_dec_io_out_by),
|
|
.io_out_half(i0_dec_io_out_half),
|
|
.io_out_word(i0_dec_io_out_word),
|
|
.io_out_csr_read(i0_dec_io_out_csr_read),
|
|
.io_out_csr_clr(i0_dec_io_out_csr_clr),
|
|
.io_out_csr_set(i0_dec_io_out_csr_set),
|
|
.io_out_csr_write(i0_dec_io_out_csr_write),
|
|
.io_out_csr_imm(i0_dec_io_out_csr_imm),
|
|
.io_out_presync(i0_dec_io_out_presync),
|
|
.io_out_postsync(i0_dec_io_out_postsync),
|
|
.io_out_ebreak(i0_dec_io_out_ebreak),
|
|
.io_out_ecall(i0_dec_io_out_ecall),
|
|
.io_out_mret(i0_dec_io_out_mret),
|
|
.io_out_mul(i0_dec_io_out_mul),
|
|
.io_out_rs1_sign(i0_dec_io_out_rs1_sign),
|
|
.io_out_rs2_sign(i0_dec_io_out_rs2_sign),
|
|
.io_out_low(i0_dec_io_out_low),
|
|
.io_out_div(i0_dec_io_out_div),
|
|
.io_out_rem(i0_dec_io_out_rem),
|
|
.io_out_fence(i0_dec_io_out_fence),
|
|
.io_out_fence_i(i0_dec_io_out_fence_i),
|
|
.io_out_pm_alu(i0_dec_io_out_pm_alu),
|
|
.io_out_legal(i0_dec_io_out_legal)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 518:23]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 518:23]
|
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en),
|
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 518:23]
|
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en),
|
|
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 518:23]
|
|
.io_l1clk(rvclkhdr_8_io_l1clk),
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en),
|
|
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 518:23]
|
|
.io_l1clk(rvclkhdr_9_io_l1clk),
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en),
|
|
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_10_io_l1clk),
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en),
|
|
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_11_io_l1clk),
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en),
|
|
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_12_io_l1clk),
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en),
|
|
.io_scan_mode(rvclkhdr_12_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_13_io_l1clk),
|
|
.io_clk(rvclkhdr_13_io_clk),
|
|
.io_en(rvclkhdr_13_io_en),
|
|
.io_scan_mode(rvclkhdr_13_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_14_io_l1clk),
|
|
.io_clk(rvclkhdr_14_io_clk),
|
|
.io_en(rvclkhdr_14_io_en),
|
|
.io_scan_mode(rvclkhdr_14_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_15_io_l1clk),
|
|
.io_clk(rvclkhdr_15_io_clk),
|
|
.io_en(rvclkhdr_15_io_en),
|
|
.io_scan_mode(rvclkhdr_15_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_16_io_l1clk),
|
|
.io_clk(rvclkhdr_16_io_clk),
|
|
.io_en(rvclkhdr_16_io_en),
|
|
.io_scan_mode(rvclkhdr_16_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_17_io_l1clk),
|
|
.io_clk(rvclkhdr_17_io_clk),
|
|
.io_en(rvclkhdr_17_io_en),
|
|
.io_scan_mode(rvclkhdr_17_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_18_io_l1clk),
|
|
.io_clk(rvclkhdr_18_io_clk),
|
|
.io_en(rvclkhdr_18_io_en),
|
|
.io_scan_mode(rvclkhdr_18_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_19_io_l1clk),
|
|
.io_clk(rvclkhdr_19_io_clk),
|
|
.io_en(rvclkhdr_19_io_en),
|
|
.io_scan_mode(rvclkhdr_19_io_scan_mode)
|
|
);
|
|
assign io_dec_extint_stall = _T_339; // @[el2_dec_decode_ctl.scala 432:23]
|
|
assign io_dec_i0_inst_wb1 = _T_837; // @[el2_dec_decode_ctl.scala 753:22]
|
|
assign io_dec_i0_pc_wb1 = _T_840; // @[el2_dec_decode_ctl.scala 756:20]
|
|
assign io_dec_i0_rs1_en_d = i0_dp_rs1 & _T_556; // @[el2_dec_decode_ctl.scala 624:24]
|
|
assign io_dec_i0_rs2_en_d = i0_dp_rs2 & _T_558; // @[el2_dec_decode_ctl.scala 625:24]
|
|
assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 627:19]
|
|
assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 628:19]
|
|
assign io_dec_i0_immed_d = _T_563 | _T_564; // @[el2_dec_decode_ctl.scala 633:21]
|
|
assign io_dec_i0_br_immed_d = _T_768 ? i0_br_offset : _T_781; // @[el2_dec_decode_ctl.scala 711:24]
|
|
assign io_i0_ap_land = _T_41 ? 1'h0 : i0_dp_raw_land; // @[el2_dec_decode_ctl.scala 285:20]
|
|
assign io_i0_ap_lor = _T_41 | i0_dp_raw_lor; // @[el2_dec_decode_ctl.scala 286:20]
|
|
assign io_i0_ap_lxor = _T_41 ? 1'h0 : i0_dp_raw_lxor; // @[el2_dec_decode_ctl.scala 287:20]
|
|
assign io_i0_ap_sll = _T_41 ? 1'h0 : i0_dp_raw_sll; // @[el2_dec_decode_ctl.scala 288:20]
|
|
assign io_i0_ap_srl = _T_41 ? 1'h0 : i0_dp_raw_srl; // @[el2_dec_decode_ctl.scala 289:20]
|
|
assign io_i0_ap_sra = _T_41 ? 1'h0 : i0_dp_raw_sra; // @[el2_dec_decode_ctl.scala 290:20]
|
|
assign io_i0_ap_beq = _T_41 ? 1'h0 : i0_dp_raw_beq; // @[el2_dec_decode_ctl.scala 293:20]
|
|
assign io_i0_ap_bne = _T_41 ? 1'h0 : i0_dp_raw_bne; // @[el2_dec_decode_ctl.scala 294:20]
|
|
assign io_i0_ap_blt = _T_41 ? 1'h0 : i0_dp_raw_blt; // @[el2_dec_decode_ctl.scala 295:20]
|
|
assign io_i0_ap_bge = _T_41 ? 1'h0 : i0_dp_raw_bge; // @[el2_dec_decode_ctl.scala 296:20]
|
|
assign io_i0_ap_add = _T_41 ? 1'h0 : i0_dp_raw_add; // @[el2_dec_decode_ctl.scala 283:20]
|
|
assign io_i0_ap_sub = _T_41 ? 1'h0 : i0_dp_raw_sub; // @[el2_dec_decode_ctl.scala 284:20]
|
|
assign io_i0_ap_slt = _T_41 ? 1'h0 : i0_dp_raw_slt; // @[el2_dec_decode_ctl.scala 291:20]
|
|
assign io_i0_ap_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 292:20]
|
|
assign io_i0_ap_jal = _T_336 & _T_337; // @[el2_dec_decode_ctl.scala 299:22]
|
|
assign io_i0_ap_predict_t = _T_47 & i0_predict_br; // @[el2_dec_decode_ctl.scala 281:26]
|
|
assign io_i0_ap_predict_nt = _T_48 & i0_predict_br; // @[el2_dec_decode_ctl.scala 280:26]
|
|
assign io_i0_ap_csr_write = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 297:22]
|
|
assign io_i0_ap_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 298:22]
|
|
assign io_dec_i0_decode_d = _T_490 & _T_467; // @[el2_dec_decode_ctl.scala 552:22 el2_dec_decode_ctl.scala 618:22]
|
|
assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 572:26]
|
|
assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 807:31]
|
|
assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 812:31]
|
|
assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 694:27]
|
|
assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 696:32]
|
|
assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 697:26]
|
|
assign io_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 271:25]
|
|
assign io_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_942}; // @[el2_dec_decode_ctl.scala 803:34]
|
|
assign io_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_951}; // @[el2_dec_decode_ctl.scala 804:34]
|
|
assign io_lsu_p_valid = io_dec_extint_stall | lsu_decode_d; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 439:24 el2_dec_decode_ctl.scala 441:35]
|
|
assign io_lsu_p_bits_fast_int = io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 438:29]
|
|
assign io_lsu_p_bits_by = io_dec_extint_stall ? 1'h0 : i0_dp_by; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 444:40]
|
|
assign io_lsu_p_bits_half = io_dec_extint_stall ? 1'h0 : i0_dp_half; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 445:40]
|
|
assign io_lsu_p_bits_word = io_dec_extint_stall | i0_dp_word; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 437:29 el2_dec_decode_ctl.scala 446:40]
|
|
assign io_lsu_p_bits_load = io_dec_extint_stall | i0_dp_load; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 436:29 el2_dec_decode_ctl.scala 442:40]
|
|
assign io_lsu_p_bits_store = io_dec_extint_stall ? 1'h0 : i0_dp_store; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 443:40]
|
|
assign io_lsu_p_bits_unsign = io_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 450:40]
|
|
assign io_lsu_p_bits_store_data_bypass_d = io_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 448:40]
|
|
assign io_lsu_p_bits_load_ldst_bypass_d = io_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 447:40]
|
|
assign io_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 427:21]
|
|
assign io_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 428:26]
|
|
assign io_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 429:26]
|
|
assign io_mul_p_bits_low = _T_41 ? 1'h0 : i0_dp_raw_low; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 430:26]
|
|
assign io_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 423:21]
|
|
assign io_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 424:26]
|
|
assign io_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[el2_dec_decode_ctl.scala 425:26]
|
|
assign io_div_waddr_wb = _T_830; // @[el2_dec_decode_ctl.scala 741:19]
|
|
assign io_dec_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 730:29]
|
|
assign io_dec_lsu_valid_raw_d = _T_992 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 817:26]
|
|
assign io_dec_lsu_offset_d = _T_1006 | _T_1007; // @[el2_dec_decode_ctl.scala 818:23]
|
|
assign io_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 454:21]
|
|
assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[el2_dec_decode_ctl.scala 463:24]
|
|
assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 529:24]
|
|
assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 466:24]
|
|
assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 471:20]
|
|
assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23]
|
|
assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24]
|
|
assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 474:27]
|
|
assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29]
|
|
assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 612:39]
|
|
assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 612:39]
|
|
assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 612:39]
|
|
assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[el2_dec_decode_ctl.scala 612:39]
|
|
assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[el2_dec_decode_ctl.scala 612:39]
|
|
assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 612:39]
|
|
assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 612:39]
|
|
assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 612:39]
|
|
assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39]
|
|
assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 612:39]
|
|
assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 759:27]
|
|
assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 536:23]
|
|
assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 764:25]
|
|
assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 236:38]
|
|
assign io_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 234:43]
|
|
assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_hist; // @[el2_dec_decode_ctl.scala 235:43]
|
|
assign io_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 248:49]
|
|
assign io_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[el2_dec_decode_ctl.scala 243:56]
|
|
assign io_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[el2_dec_decode_ctl.scala 244:56]
|
|
assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_prett; // @[el2_dec_decode_ctl.scala 233:43]
|
|
assign io_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 230:43]
|
|
assign io_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 232:43]
|
|
assign io_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 231:43]
|
|
assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_way; // @[el2_dec_decode_ctl.scala 250:56]
|
|
assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 249:32]
|
|
assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 245:32]
|
|
assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 246:32]
|
|
assign io_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[el2_dec_decode_ctl.scala 662:27]
|
|
assign io_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[el2_dec_decode_ctl.scala 663:27]
|
|
assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 557:28]
|
|
assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_498; // @[el2_dec_decode_ctl.scala 558:27]
|
|
assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 560:29]
|
|
assign io_dec_pmu_postsync_stall = postsync_stall; // @[el2_dec_decode_ctl.scala 559:29]
|
|
assign io_dec_nonblock_load_wen = _T_200 & _T_201; // @[el2_dec_decode_ctl.scala 354:28]
|
|
assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[el2_dec_decode_ctl.scala 351:29 el2_dec_decode_ctl.scala 361:29]
|
|
assign io_dec_pause_state = pause_stall; // @[el2_dec_decode_ctl.scala 498:22]
|
|
assign io_dec_pause_state_cg = pause_stall & _T_420; // @[el2_dec_decode_ctl.scala 502:25]
|
|
assign io_dec_div_active = _T_821; // @[el2_dec_decode_ctl.scala 735:21]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_io_en = _T_15 | _T_16; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign i0_dec_io_ins = io_dec_i0_instr_d; // @[el2_dec_decode_ctl.scala 393:16]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_2_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = _T_428 | pause_stall; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_4_io_en = shift_illegal & _T_464; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 520:18]
|
|
assign rvclkhdr_5_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24]
|
|
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 520:18]
|
|
assign rvclkhdr_6_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17]
|
|
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24]
|
|
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 520:18]
|
|
assign rvclkhdr_7_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17]
|
|
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24]
|
|
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 520:18]
|
|
assign rvclkhdr_8_io_en = _T_707 | io_clk_override; // @[el2_lib.scala 521:17]
|
|
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24]
|
|
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 520:18]
|
|
assign rvclkhdr_9_io_en = _T_710 | io_clk_override; // @[el2_lib.scala 521:17]
|
|
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24]
|
|
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_10_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_11_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_12_io_en = i0_legal_decode_d & i0_dp_div; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_13_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_14_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_15_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_16_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_17_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_18_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_19_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
tlu_wr_pause_r1 = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
tlu_wr_pause_r2 = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
leak1_i1_stall = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
leak1_i0_stall = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
pause_stall = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
write_csr_data = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
postsync_stall = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
x_d_i0valid = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
flush_final_r = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
illegal_lockout = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
cam_raw_0_tag = _RAND_10[2:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
cam_raw_0_valid = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
cam_raw_1_tag = _RAND_12[2:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
cam_raw_1_valid = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
cam_raw_2_tag = _RAND_14[2:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
cam_raw_2_valid = _RAND_15[0:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
cam_raw_3_tag = _RAND_16[2:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
cam_raw_3_valid = _RAND_17[0:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
x_d_i0load = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
x_d_i0rd = _RAND_19[4:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
_T_701 = _RAND_20[2:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
nonblock_load_valid_m_delay = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
r_d_i0load = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
r_d_i0v = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
r_d_i0rd = _RAND_24[4:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
cam_raw_0_rd = _RAND_25[4:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
cam_raw_0_wb = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
cam_raw_1_rd = _RAND_27[4:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
cam_raw_1_wb = _RAND_28[0:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
cam_raw_2_rd = _RAND_29[4:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
cam_raw_2_wb = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
cam_raw_3_rd = _RAND_31[4:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
cam_raw_3_wb = _RAND_32[0:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
lsu_idle = _RAND_33[0:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
_T_339 = _RAND_34[0:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
x_d_i0v = _RAND_35[0:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
i0_x_c_load = _RAND_36[0:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
i0_r_c_load = _RAND_37[0:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
r_d_csrwen = _RAND_38[0:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
r_d_i0valid = _RAND_39[0:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
r_d_csrwaddr = _RAND_40[11:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
csr_read_x = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
csr_clr_x = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
csr_set_x = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
csr_write_x = _RAND_44[0:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
csr_imm_x = _RAND_45[0:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
csrimm_x = _RAND_46[4:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
csr_rddata_x = _RAND_47[31:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
r_d_csrwonly = _RAND_48[0:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
i0_result_r_raw = _RAND_49[31:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
x_d_csrwonly = _RAND_50[0:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
wbd_csrwonly = _RAND_51[0:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
_T_465 = _RAND_52[31:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
x_t_legal = _RAND_53[0:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
x_t_icaf = _RAND_54[0:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
x_t_icaf_f1 = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
x_t_icaf_type = _RAND_56[1:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
x_t_fence_i = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
x_t_i0trigger = _RAND_58[3:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
x_t_pmu_i0_itype = _RAND_59[3:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
x_t_pmu_i0_br_unpred = _RAND_60[0:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
r_t_legal = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
r_t_icaf = _RAND_62[0:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
r_t_icaf_f1 = _RAND_63[0:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
r_t_icaf_type = _RAND_64[1:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
r_t_fence_i = _RAND_65[0:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
r_t_i0trigger = _RAND_66[3:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
r_t_pmu_i0_itype = _RAND_67[3:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
r_t_pmu_i0_br_unpred = _RAND_68[0:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
lsu_trigger_match_r = _RAND_69[3:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
lsu_pmu_misaligned_r = _RAND_70[0:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
r_d_i0store = _RAND_71[0:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
r_d_i0div = _RAND_72[0:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
i0_x_c_mul = _RAND_73[0:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
i0_x_c_alu = _RAND_74[0:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
i0_r_c_mul = _RAND_75[0:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
i0_r_c_alu = _RAND_76[0:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
x_d_i0store = _RAND_77[0:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
x_d_i0div = _RAND_78[0:0];
|
|
_RAND_79 = {1{`RANDOM}};
|
|
x_d_csrwen = _RAND_79[0:0];
|
|
_RAND_80 = {1{`RANDOM}};
|
|
x_d_csrwaddr = _RAND_80[11:0];
|
|
_RAND_81 = {1{`RANDOM}};
|
|
last_br_immed_x = _RAND_81[11:0];
|
|
_RAND_82 = {1{`RANDOM}};
|
|
_T_821 = _RAND_82[0:0];
|
|
_RAND_83 = {1{`RANDOM}};
|
|
_T_830 = _RAND_83[4:0];
|
|
_RAND_84 = {1{`RANDOM}};
|
|
i0_inst_x = _RAND_84[31:0];
|
|
_RAND_85 = {1{`RANDOM}};
|
|
i0_inst_r = _RAND_85[31:0];
|
|
_RAND_86 = {1{`RANDOM}};
|
|
i0_inst_wb = _RAND_86[31:0];
|
|
_RAND_87 = {1{`RANDOM}};
|
|
_T_837 = _RAND_87[31:0];
|
|
_RAND_88 = {1{`RANDOM}};
|
|
i0_pc_wb = _RAND_88[30:0];
|
|
_RAND_89 = {1{`RANDOM}};
|
|
_T_840 = _RAND_89[30:0];
|
|
_RAND_90 = {1{`RANDOM}};
|
|
dec_i0_pc_r = _RAND_90[30:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
tlu_wr_pause_r1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
tlu_wr_pause_r2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
leak1_i1_stall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
leak1_i0_stall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
pause_stall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
write_csr_data = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
postsync_stall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_i0valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
flush_final_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
illegal_lockout = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_0_tag = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_0_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_1_tag = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_1_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_2_tag = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_2_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_3_tag = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_3_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_i0load = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_i0rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_701 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
nonblock_load_valid_m_delay = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_i0load = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_i0v = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_i0rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_0_rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_0_wb = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_1_rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_1_wb = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_2_rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_2_wb = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_3_rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_3_wb = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_idle = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_339 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_i0v = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_csrwen = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_i0valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_csrwaddr = 12'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_read_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_clr_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_set_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_write_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_imm_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
csrimm_x = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_rddata_x = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_csrwonly = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_result_r_raw = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_csrwonly = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
wbd_csrwonly = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_465 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_legal = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_icaf = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_icaf_f1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_icaf_type = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_fence_i = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_i0trigger = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_pmu_i0_itype = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_pmu_i0_br_unpred = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_legal = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_icaf = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_icaf_f1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_icaf_type = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_fence_i = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_i0trigger = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_pmu_i0_itype = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_pmu_i0_br_unpred = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_trigger_match_r = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_pmu_misaligned_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_i0store = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_i0div = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_i0store = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_i0div = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_csrwen = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_csrwaddr = 12'h0;
|
|
end
|
|
if (reset) begin
|
|
last_br_immed_x = 12'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_821 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_830 = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_inst_x = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_inst_r = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_inst_wb = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_837 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pc_wb = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_840 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_i0_pc_r = 31'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_active_clk) begin
|
|
if (i0_x_ctl_en) begin
|
|
i0_x_c_load <= i0_d_c_load;
|
|
end
|
|
if (i0_r_ctl_en) begin
|
|
i0_r_c_load <= i0_x_c_load;
|
|
end
|
|
if (i0_x_ctl_en) begin
|
|
i0_x_c_mul <= i0_d_c_mul;
|
|
end
|
|
if (i0_x_ctl_en) begin
|
|
i0_x_c_alu <= i0_d_c_alu;
|
|
end
|
|
if (i0_r_ctl_en) begin
|
|
i0_r_c_mul <= i0_x_c_mul;
|
|
end
|
|
if (i0_r_ctl_en) begin
|
|
i0_r_c_alu <= i0_x_c_alu;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
tlu_wr_pause_r1 <= 1'h0;
|
|
end else begin
|
|
tlu_wr_pause_r1 <= io_dec_tlu_wr_pause_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
tlu_wr_pause_r2 <= 1'h0;
|
|
end else begin
|
|
tlu_wr_pause_r2 <= tlu_wr_pause_r1;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
leak1_i1_stall <= 1'h0;
|
|
end else begin
|
|
leak1_i1_stall <= io_dec_tlu_flush_leak_one_r | _T_281;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
leak1_i0_stall <= 1'h0;
|
|
end else begin
|
|
leak1_i0_stall <= _T_284 | _T_286;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
pause_stall <= 1'h0;
|
|
end else begin
|
|
pause_stall <= _T_412 & _T_413;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
write_csr_data <= 32'h0;
|
|
end else if (pause_stall) begin
|
|
write_csr_data <= _T_423;
|
|
end else if (io_dec_tlu_wr_pause_r) begin
|
|
write_csr_data <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
write_csr_data <= write_csr_data_x;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
postsync_stall <= 1'h0;
|
|
end else begin
|
|
postsync_stall <= _T_506 | _T_507;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_i0valid <= 1'h0;
|
|
end else begin
|
|
x_d_i0valid <= io_dec_i0_decode_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
flush_final_r <= 1'h0;
|
|
end else begin
|
|
flush_final_r <= io_exu_flush_final;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
illegal_lockout <= 1'h0;
|
|
end else begin
|
|
illegal_lockout <= _T_466 & _T_467;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_0_tag <= 3'h0;
|
|
end else if (cam_wen[0]) begin
|
|
cam_raw_0_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
|
end else if (_T_107) begin
|
|
cam_raw_0_tag <= 3'h0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_0_valid <= 1'h0;
|
|
end else if (io_dec_tlu_force_halt) begin
|
|
cam_raw_0_valid <= 1'h0;
|
|
end else begin
|
|
cam_raw_0_valid <= _GEN_56;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_1_tag <= 3'h0;
|
|
end else if (cam_wen[1]) begin
|
|
cam_raw_1_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
|
end else if (_T_133) begin
|
|
cam_raw_1_tag <= 3'h0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_1_valid <= 1'h0;
|
|
end else if (io_dec_tlu_force_halt) begin
|
|
cam_raw_1_valid <= 1'h0;
|
|
end else begin
|
|
cam_raw_1_valid <= _GEN_67;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_2_tag <= 3'h0;
|
|
end else if (cam_wen[2]) begin
|
|
cam_raw_2_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
|
end else if (_T_159) begin
|
|
cam_raw_2_tag <= 3'h0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_2_valid <= 1'h0;
|
|
end else if (io_dec_tlu_force_halt) begin
|
|
cam_raw_2_valid <= 1'h0;
|
|
end else begin
|
|
cam_raw_2_valid <= _GEN_78;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_3_tag <= 3'h0;
|
|
end else if (cam_wen[3]) begin
|
|
cam_raw_3_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
|
end else if (_T_185) begin
|
|
cam_raw_3_tag <= 3'h0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_3_valid <= 1'h0;
|
|
end else if (io_dec_tlu_force_halt) begin
|
|
cam_raw_3_valid <= 1'h0;
|
|
end else begin
|
|
cam_raw_3_valid <= _GEN_89;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_i0load <= 1'h0;
|
|
end else begin
|
|
x_d_i0load <= i0_dp_load & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_i0rd <= 5'h0;
|
|
end else begin
|
|
x_d_i0rd <= io_dec_i0_instr_d[11:7];
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_701 <= 3'h0;
|
|
end else begin
|
|
_T_701 <= i0_pipe_en[3:1];
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
nonblock_load_valid_m_delay <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
nonblock_load_valid_m_delay <= io_lsu_nonblock_load_valid_m;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_i0load <= 1'h0;
|
|
end else begin
|
|
r_d_i0load <= x_d_i0load;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_i0v <= 1'h0;
|
|
end else begin
|
|
r_d_i0v <= _T_733 & _T_280;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_i0rd <= 5'h0;
|
|
end else begin
|
|
r_d_i0rd <= x_d_i0rd;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_0_rd <= 5'h0;
|
|
end else if (cam_wen[0]) begin
|
|
if (x_d_i0load) begin
|
|
cam_raw_0_rd <= x_d_i0rd;
|
|
end else begin
|
|
cam_raw_0_rd <= 5'h0;
|
|
end
|
|
end else if (_T_107) begin
|
|
cam_raw_0_rd <= 5'h0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_0_wb <= 1'h0;
|
|
end else begin
|
|
cam_raw_0_wb <= _T_112 | _GEN_57;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_1_rd <= 5'h0;
|
|
end else if (cam_wen[1]) begin
|
|
if (x_d_i0load) begin
|
|
cam_raw_1_rd <= x_d_i0rd;
|
|
end else begin
|
|
cam_raw_1_rd <= 5'h0;
|
|
end
|
|
end else if (_T_133) begin
|
|
cam_raw_1_rd <= 5'h0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_1_wb <= 1'h0;
|
|
end else begin
|
|
cam_raw_1_wb <= _T_138 | _GEN_68;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_2_rd <= 5'h0;
|
|
end else if (cam_wen[2]) begin
|
|
if (x_d_i0load) begin
|
|
cam_raw_2_rd <= x_d_i0rd;
|
|
end else begin
|
|
cam_raw_2_rd <= 5'h0;
|
|
end
|
|
end else if (_T_159) begin
|
|
cam_raw_2_rd <= 5'h0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_2_wb <= 1'h0;
|
|
end else begin
|
|
cam_raw_2_wb <= _T_164 | _GEN_79;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_3_rd <= 5'h0;
|
|
end else if (cam_wen[3]) begin
|
|
if (x_d_i0load) begin
|
|
cam_raw_3_rd <= x_d_i0rd;
|
|
end else begin
|
|
cam_raw_3_rd <= 5'h0;
|
|
end
|
|
end else if (_T_185) begin
|
|
cam_raw_3_rd <= 5'h0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_3_wb <= 1'h0;
|
|
end else begin
|
|
cam_raw_3_wb <= _T_190 | _GEN_90;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_idle <= 1'h0;
|
|
end else begin
|
|
lsu_idle <= io_lsu_idle_any;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_339 <= 1'h0;
|
|
end else begin
|
|
_T_339 <= io_dec_tlu_flush_extint;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_i0v <= 1'h0;
|
|
end else begin
|
|
x_d_i0v <= i0_rd_en_d & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_csrwen <= 1'h0;
|
|
end else begin
|
|
r_d_csrwen <= x_d_csrwen;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_i0valid <= 1'h0;
|
|
end else begin
|
|
r_d_i0valid <= _T_737 & _T_280;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_csrwaddr <= 12'h0;
|
|
end else begin
|
|
r_d_csrwaddr <= x_d_csrwaddr;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
csr_read_x <= 1'h0;
|
|
end else begin
|
|
csr_read_x <= i0_dp_csr_read & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
csr_clr_x <= 1'h0;
|
|
end else begin
|
|
csr_clr_x <= i0_dp_csr_clr & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
csr_set_x <= 1'h0;
|
|
end else begin
|
|
csr_set_x <= i0_dp_csr_set & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
csr_write_x <= 1'h0;
|
|
end else begin
|
|
csr_write_x <= i0_csr_write & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
csr_imm_x <= 1'h0;
|
|
end else if (_T_41) begin
|
|
csr_imm_x <= 1'h0;
|
|
end else begin
|
|
csr_imm_x <= i0_dp_raw_csr_imm;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
csrimm_x <= 5'h0;
|
|
end else begin
|
|
csrimm_x <= io_dec_i0_instr_d[19:15];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
csr_rddata_x <= 32'h0;
|
|
end else begin
|
|
csr_rddata_x <= io_dec_csr_rddata_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_csrwonly <= 1'h0;
|
|
end else begin
|
|
r_d_csrwonly <= x_d_csrwonly;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_result_r_raw <= 32'h0;
|
|
end else if (_T_761) begin
|
|
i0_result_r_raw <= io_lsu_result_m;
|
|
end else begin
|
|
i0_result_r_raw <= io_exu_i0_result_x;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_csrwonly <= 1'h0;
|
|
end else begin
|
|
x_d_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
wbd_csrwonly <= 1'h0;
|
|
end else begin
|
|
wbd_csrwonly <= r_d_csrwonly;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_465 <= 32'h0;
|
|
end else if (io_dec_i0_pc4_d) begin
|
|
_T_465 <= io_dec_i0_instr_d;
|
|
end else begin
|
|
_T_465 <= _T_462;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_legal <= 1'h0;
|
|
end else begin
|
|
x_t_legal <= io_dec_i0_decode_d & i0_legal;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_icaf <= 1'h0;
|
|
end else begin
|
|
x_t_icaf <= i0_icaf_d & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_icaf_f1 <= 1'h0;
|
|
end else begin
|
|
x_t_icaf_f1 <= io_dec_i0_icaf_f1_d & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_icaf_type <= 2'h0;
|
|
end else begin
|
|
x_t_icaf_type <= io_dec_i0_icaf_type_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_fence_i <= 1'h0;
|
|
end else begin
|
|
x_t_fence_i <= _T_517 & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_i0trigger <= 4'h0;
|
|
end else begin
|
|
x_t_i0trigger <= io_dec_i0_trigger_match_d & _T_522;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_pmu_i0_itype <= 4'h0;
|
|
end else begin
|
|
x_t_pmu_i0_itype <= _T_255 & _T_277;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_pmu_i0_br_unpred <= 1'h0;
|
|
end else begin
|
|
x_t_pmu_i0_br_unpred <= i0_dp_jal & _T_253;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_legal <= 1'h0;
|
|
end else begin
|
|
r_t_legal <= x_t_legal;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_icaf <= 1'h0;
|
|
end else begin
|
|
r_t_icaf <= x_t_icaf;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_icaf_f1 <= 1'h0;
|
|
end else begin
|
|
r_t_icaf_f1 <= x_t_icaf_f1;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_icaf_type <= 2'h0;
|
|
end else begin
|
|
r_t_icaf_type <= x_t_icaf_type;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_fence_i <= 1'h0;
|
|
end else begin
|
|
r_t_fence_i <= x_t_fence_i;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_i0trigger <= 4'h0;
|
|
end else begin
|
|
r_t_i0trigger <= x_t_i0trigger & _T_531;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_pmu_i0_itype <= 4'h0;
|
|
end else begin
|
|
r_t_pmu_i0_itype <= x_t_pmu_i0_itype;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_pmu_i0_br_unpred <= 1'h0;
|
|
end else begin
|
|
r_t_pmu_i0_br_unpred <= x_t_pmu_i0_br_unpred;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_trigger_match_r <= 4'h0;
|
|
end else begin
|
|
lsu_trigger_match_r <= io_lsu_trigger_match_m;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_pmu_misaligned_r <= 1'h0;
|
|
end else begin
|
|
lsu_pmu_misaligned_r <= io_lsu_pmu_misaligned_m;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_i0store <= 1'h0;
|
|
end else begin
|
|
r_d_i0store <= x_d_i0store;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_i0div <= 1'h0;
|
|
end else begin
|
|
r_d_i0div <= x_d_i0div;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_i0store <= 1'h0;
|
|
end else begin
|
|
x_d_i0store <= i0_dp_store & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_i0div <= 1'h0;
|
|
end else begin
|
|
x_d_i0div <= i0_dp_div & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_csrwen <= 1'h0;
|
|
end else begin
|
|
x_d_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_csrwaddr <= 12'h0;
|
|
end else begin
|
|
x_d_csrwaddr <= io_dec_i0_instr_d[31:20];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
last_br_immed_x <= 12'h0;
|
|
end else if (io_i0_ap_predict_nt) begin
|
|
last_br_immed_x <= _T_781;
|
|
end else if (_T_314) begin
|
|
last_br_immed_x <= i0_pcall_imm[11:0];
|
|
end else begin
|
|
last_br_immed_x <= _T_323;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_821 <= 1'h0;
|
|
end else begin
|
|
_T_821 <= i0_div_decode_d | _T_820;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_830 <= 5'h0;
|
|
end else if (i0_div_decode_d) begin
|
|
_T_830 <= i0r_rd;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_inst_x <= 32'h0;
|
|
end else if (io_dec_i0_pc4_d) begin
|
|
i0_inst_x <= io_dec_i0_instr_d;
|
|
end else begin
|
|
i0_inst_x <= _T_462;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_inst_r <= 32'h0;
|
|
end else begin
|
|
i0_inst_r <= i0_inst_x;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_inst_wb <= 32'h0;
|
|
end else begin
|
|
i0_inst_wb <= i0_inst_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_837 <= 32'h0;
|
|
end else begin
|
|
_T_837 <= i0_inst_wb;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pc_wb <= 31'h0;
|
|
end else begin
|
|
i0_pc_wb <= io_dec_tlu_i0_pc_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_840 <= 31'h0;
|
|
end else begin
|
|
_T_840 <= i0_pc_wb;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
dec_i0_pc_r <= 31'h0;
|
|
end else begin
|
|
dec_i0_pc_r <= io_exu_i0_pc_x;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_dec_gpr_ctl(
|
|
input clock,
|
|
input reset,
|
|
input [4:0] io_raddr0,
|
|
input [4:0] io_raddr1,
|
|
input io_wen0,
|
|
input [4:0] io_waddr0,
|
|
input [31:0] io_wd0,
|
|
input io_wen1,
|
|
input [4:0] io_waddr1,
|
|
input [31:0] io_wd1,
|
|
input io_wen2,
|
|
input [4:0] io_waddr2,
|
|
input [31:0] io_wd2,
|
|
output [31:0] io_rd0,
|
|
output [31:0] io_rd1,
|
|
input io_scan_mode
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire _T = io_waddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_1 = io_wen0 & _T; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_2 = io_waddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_1 = io_wen1 & _T_2; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_4 = io_waddr2 == 5'h1; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_1 = io_wen2 & _T_4; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_7 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_8 = _T_7 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_10 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_11 = _T_10 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_12 = _T_8 | _T_11; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_14 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_15 = _T_14 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_17 = io_waddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_2 = io_wen0 & _T_17; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_19 = io_waddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_2 = io_wen1 & _T_19; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_21 = io_waddr2 == 5'h2; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_2 = io_wen2 & _T_21; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_24 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_25 = _T_24 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_27 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_28 = _T_27 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_29 = _T_25 | _T_28; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_31 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_32 = _T_31 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_34 = io_waddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_3 = io_wen0 & _T_34; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_36 = io_waddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_3 = io_wen1 & _T_36; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_38 = io_waddr2 == 5'h3; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_3 = io_wen2 & _T_38; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_41 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_42 = _T_41 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_44 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_45 = _T_44 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_46 = _T_42 | _T_45; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_48 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_49 = _T_48 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_51 = io_waddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_4 = io_wen0 & _T_51; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_53 = io_waddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_4 = io_wen1 & _T_53; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_55 = io_waddr2 == 5'h4; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_4 = io_wen2 & _T_55; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_58 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_59 = _T_58 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_61 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_62 = _T_61 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_63 = _T_59 | _T_62; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_65 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_66 = _T_65 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_68 = io_waddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_5 = io_wen0 & _T_68; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_70 = io_waddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_5 = io_wen1 & _T_70; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_72 = io_waddr2 == 5'h5; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_5 = io_wen2 & _T_72; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_75 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_76 = _T_75 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_78 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_79 = _T_78 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_80 = _T_76 | _T_79; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_82 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_83 = _T_82 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_85 = io_waddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_6 = io_wen0 & _T_85; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_87 = io_waddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_6 = io_wen1 & _T_87; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_89 = io_waddr2 == 5'h6; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_6 = io_wen2 & _T_89; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_92 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_93 = _T_92 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_95 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_96 = _T_95 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_97 = _T_93 | _T_96; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_99 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_100 = _T_99 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_102 = io_waddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_7 = io_wen0 & _T_102; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_104 = io_waddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_7 = io_wen1 & _T_104; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_106 = io_waddr2 == 5'h7; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_7 = io_wen2 & _T_106; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_109 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_110 = _T_109 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_112 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_113 = _T_112 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_114 = _T_110 | _T_113; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_116 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_117 = _T_116 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_119 = io_waddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_8 = io_wen0 & _T_119; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_121 = io_waddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_8 = io_wen1 & _T_121; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_123 = io_waddr2 == 5'h8; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_8 = io_wen2 & _T_123; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_126 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_127 = _T_126 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_129 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_130 = _T_129 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_131 = _T_127 | _T_130; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_133 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_134 = _T_133 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_136 = io_waddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_9 = io_wen0 & _T_136; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_138 = io_waddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_9 = io_wen1 & _T_138; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_140 = io_waddr2 == 5'h9; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_9 = io_wen2 & _T_140; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_143 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_144 = _T_143 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_146 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_147 = _T_146 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_148 = _T_144 | _T_147; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_150 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_151 = _T_150 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_153 = io_waddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_10 = io_wen0 & _T_153; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_155 = io_waddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_10 = io_wen1 & _T_155; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_157 = io_waddr2 == 5'ha; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_10 = io_wen2 & _T_157; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_160 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_161 = _T_160 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_163 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_164 = _T_163 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_165 = _T_161 | _T_164; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_167 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_168 = _T_167 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_170 = io_waddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_11 = io_wen0 & _T_170; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_172 = io_waddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_11 = io_wen1 & _T_172; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_174 = io_waddr2 == 5'hb; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_11 = io_wen2 & _T_174; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_177 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_178 = _T_177 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_180 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_181 = _T_180 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_182 = _T_178 | _T_181; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_184 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_185 = _T_184 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_187 = io_waddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_12 = io_wen0 & _T_187; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_189 = io_waddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_12 = io_wen1 & _T_189; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_191 = io_waddr2 == 5'hc; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_12 = io_wen2 & _T_191; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_194 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_195 = _T_194 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_197 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_198 = _T_197 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_199 = _T_195 | _T_198; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_201 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_202 = _T_201 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_204 = io_waddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_13 = io_wen0 & _T_204; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_206 = io_waddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_13 = io_wen1 & _T_206; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_208 = io_waddr2 == 5'hd; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_13 = io_wen2 & _T_208; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_211 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_212 = _T_211 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_214 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_215 = _T_214 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_216 = _T_212 | _T_215; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_218 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_219 = _T_218 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_221 = io_waddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_14 = io_wen0 & _T_221; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_223 = io_waddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_14 = io_wen1 & _T_223; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_225 = io_waddr2 == 5'he; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_14 = io_wen2 & _T_225; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_228 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_229 = _T_228 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_231 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_232 = _T_231 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_233 = _T_229 | _T_232; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_235 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_236 = _T_235 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_238 = io_waddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_15 = io_wen0 & _T_238; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_240 = io_waddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_15 = io_wen1 & _T_240; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_242 = io_waddr2 == 5'hf; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_15 = io_wen2 & _T_242; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_245 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_246 = _T_245 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_248 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_249 = _T_248 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_250 = _T_246 | _T_249; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_252 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_253 = _T_252 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_255 = io_waddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_16 = io_wen0 & _T_255; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_257 = io_waddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_16 = io_wen1 & _T_257; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_259 = io_waddr2 == 5'h10; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_16 = io_wen2 & _T_259; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_262 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_263 = _T_262 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_265 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_266 = _T_265 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_267 = _T_263 | _T_266; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_269 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_270 = _T_269 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_272 = io_waddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_17 = io_wen0 & _T_272; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_274 = io_waddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_17 = io_wen1 & _T_274; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_276 = io_waddr2 == 5'h11; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_17 = io_wen2 & _T_276; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_279 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_280 = _T_279 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_282 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_283 = _T_282 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_284 = _T_280 | _T_283; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_286 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_287 = _T_286 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_289 = io_waddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_18 = io_wen0 & _T_289; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_291 = io_waddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_18 = io_wen1 & _T_291; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_293 = io_waddr2 == 5'h12; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_18 = io_wen2 & _T_293; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_296 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_297 = _T_296 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_299 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_300 = _T_299 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_301 = _T_297 | _T_300; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_303 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_304 = _T_303 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_306 = io_waddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_19 = io_wen0 & _T_306; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_308 = io_waddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_19 = io_wen1 & _T_308; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_310 = io_waddr2 == 5'h13; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_19 = io_wen2 & _T_310; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_313 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_314 = _T_313 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_316 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_317 = _T_316 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_318 = _T_314 | _T_317; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_320 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_321 = _T_320 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_323 = io_waddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_20 = io_wen0 & _T_323; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_325 = io_waddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_20 = io_wen1 & _T_325; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_327 = io_waddr2 == 5'h14; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_20 = io_wen2 & _T_327; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_330 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_331 = _T_330 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_333 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_334 = _T_333 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_335 = _T_331 | _T_334; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_337 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_338 = _T_337 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_340 = io_waddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_21 = io_wen0 & _T_340; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_342 = io_waddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_21 = io_wen1 & _T_342; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_344 = io_waddr2 == 5'h15; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_21 = io_wen2 & _T_344; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_347 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_348 = _T_347 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_350 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_351 = _T_350 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_352 = _T_348 | _T_351; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_354 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_355 = _T_354 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_357 = io_waddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_22 = io_wen0 & _T_357; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_359 = io_waddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_22 = io_wen1 & _T_359; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_361 = io_waddr2 == 5'h16; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_22 = io_wen2 & _T_361; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_364 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_365 = _T_364 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_367 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_368 = _T_367 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_369 = _T_365 | _T_368; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_371 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_372 = _T_371 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_374 = io_waddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_23 = io_wen0 & _T_374; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_376 = io_waddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_23 = io_wen1 & _T_376; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_378 = io_waddr2 == 5'h17; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_23 = io_wen2 & _T_378; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_381 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_382 = _T_381 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_384 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_385 = _T_384 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_386 = _T_382 | _T_385; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_388 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_389 = _T_388 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_391 = io_waddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_24 = io_wen0 & _T_391; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_393 = io_waddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_24 = io_wen1 & _T_393; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_395 = io_waddr2 == 5'h18; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_24 = io_wen2 & _T_395; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_398 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_399 = _T_398 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_401 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_402 = _T_401 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_403 = _T_399 | _T_402; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_405 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_406 = _T_405 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_408 = io_waddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_25 = io_wen0 & _T_408; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_410 = io_waddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_25 = io_wen1 & _T_410; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_412 = io_waddr2 == 5'h19; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_25 = io_wen2 & _T_412; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_415 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_416 = _T_415 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_418 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_419 = _T_418 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_420 = _T_416 | _T_419; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_422 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_423 = _T_422 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_425 = io_waddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_26 = io_wen0 & _T_425; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_427 = io_waddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_26 = io_wen1 & _T_427; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_429 = io_waddr2 == 5'h1a; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_26 = io_wen2 & _T_429; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_432 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_433 = _T_432 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_435 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_436 = _T_435 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_437 = _T_433 | _T_436; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_439 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_440 = _T_439 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_442 = io_waddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_27 = io_wen0 & _T_442; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_444 = io_waddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_27 = io_wen1 & _T_444; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_446 = io_waddr2 == 5'h1b; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_27 = io_wen2 & _T_446; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_449 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_450 = _T_449 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_452 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_453 = _T_452 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_454 = _T_450 | _T_453; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_456 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_457 = _T_456 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_459 = io_waddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_28 = io_wen0 & _T_459; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_461 = io_waddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_28 = io_wen1 & _T_461; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_463 = io_waddr2 == 5'h1c; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_28 = io_wen2 & _T_463; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_466 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_467 = _T_466 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_469 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_470 = _T_469 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_471 = _T_467 | _T_470; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_473 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_474 = _T_473 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_476 = io_waddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_29 = io_wen0 & _T_476; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_478 = io_waddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_29 = io_wen1 & _T_478; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_480 = io_waddr2 == 5'h1d; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_29 = io_wen2 & _T_480; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_483 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_484 = _T_483 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_486 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_487 = _T_486 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_488 = _T_484 | _T_487; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_490 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_491 = _T_490 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_493 = io_waddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_30 = io_wen0 & _T_493; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_495 = io_waddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_30 = io_wen1 & _T_495; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_497 = io_waddr2 == 5'h1e; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_30 = io_wen2 & _T_497; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_500 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_501 = _T_500 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_503 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_504 = _T_503 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_505 = _T_501 | _T_504; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_507 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_508 = _T_507 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire _T_510 = io_waddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 35:40]
|
|
wire w0v_31 = io_wen0 & _T_510; // @[el2_dec_gpr_ctl.scala 35:28]
|
|
wire _T_512 = io_waddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 36:40]
|
|
wire w1v_31 = io_wen1 & _T_512; // @[el2_dec_gpr_ctl.scala 36:28]
|
|
wire _T_514 = io_waddr2 == 5'h1f; // @[el2_dec_gpr_ctl.scala 37:40]
|
|
wire w2v_31 = io_wen2 & _T_514; // @[el2_dec_gpr_ctl.scala 37:28]
|
|
wire [31:0] _T_517 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_518 = _T_517 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37]
|
|
wire [31:0] _T_520 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_521 = _T_520 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66]
|
|
wire [31:0] _T_522 = _T_518 | _T_521; // @[el2_dec_gpr_ctl.scala 38:47]
|
|
wire [31:0] _T_524 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_525 = _T_524 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95]
|
|
wire [9:0] _T_535 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_544 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_535}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_553 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_544}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_557 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_553}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_566 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_575 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_566}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_584 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_575}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_588 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_584}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_589 = _T_557 | _T_588; // @[el2_dec_gpr_ctl.scala 40:51]
|
|
wire [9:0] _T_598 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_607 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_598}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_616 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_607}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_620 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_616}; // @[Cat.scala 29:58]
|
|
wire [31:0] gpr_wr_en = _T_589 | _T_620; // @[el2_dec_gpr_ctl.scala 40:89]
|
|
reg [31:0] gpr_out_1; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_2; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_3; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_4; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_5; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_6; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_7; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_8; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_9; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_10; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_11; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_12; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_13; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_14; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_15; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_16; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_17; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_18; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_19; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_20; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_21; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_22; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_23; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_24; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_25; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_26; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_27; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_28; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_29; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_30; // @[el2_lib.scala 514:16]
|
|
reg [31:0] gpr_out_31; // @[el2_lib.scala 514:16]
|
|
wire _T_684 = io_raddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_686 = io_raddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_688 = io_raddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_690 = io_raddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_692 = io_raddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_694 = io_raddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_696 = io_raddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_698 = io_raddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_700 = io_raddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_702 = io_raddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_704 = io_raddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_706 = io_raddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_708 = io_raddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_710 = io_raddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_712 = io_raddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_714 = io_raddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_716 = io_raddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_718 = io_raddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_720 = io_raddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_722 = io_raddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_724 = io_raddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_726 = io_raddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_728 = io_raddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_730 = io_raddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_732 = io_raddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_734 = io_raddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_736 = io_raddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_738 = io_raddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_740 = io_raddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_742 = io_raddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire _T_744 = io_raddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 47:49]
|
|
wire [31:0] _T_746 = _T_684 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_747 = _T_686 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_748 = _T_688 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_749 = _T_690 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_750 = _T_692 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_751 = _T_694 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_752 = _T_696 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_753 = _T_698 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_754 = _T_700 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_755 = _T_702 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_756 = _T_704 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_757 = _T_706 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_758 = _T_708 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_759 = _T_710 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_760 = _T_712 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_761 = _T_714 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_762 = _T_716 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_763 = _T_718 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_764 = _T_720 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_765 = _T_722 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_766 = _T_724 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_767 = _T_726 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_768 = _T_728 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_769 = _T_730 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_770 = _T_732 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_771 = _T_734 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_772 = _T_736 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_773 = _T_738 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_774 = _T_740 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_775 = _T_742 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_776 = _T_744 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_777 = _T_746 | _T_747; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_778 = _T_777 | _T_748; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_779 = _T_778 | _T_749; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_780 = _T_779 | _T_750; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_781 = _T_780 | _T_751; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_782 = _T_781 | _T_752; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_783 = _T_782 | _T_753; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_784 = _T_783 | _T_754; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_785 = _T_784 | _T_755; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_786 = _T_785 | _T_756; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_787 = _T_786 | _T_757; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_788 = _T_787 | _T_758; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_789 = _T_788 | _T_759; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_790 = _T_789 | _T_760; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_791 = _T_790 | _T_761; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_792 = _T_791 | _T_762; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_793 = _T_792 | _T_763; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_794 = _T_793 | _T_764; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_795 = _T_794 | _T_765; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_796 = _T_795 | _T_766; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_797 = _T_796 | _T_767; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_798 = _T_797 | _T_768; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_799 = _T_798 | _T_769; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_800 = _T_799 | _T_770; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_801 = _T_800 | _T_771; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_802 = _T_801 | _T_772; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_803 = _T_802 | _T_773; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_804 = _T_803 | _T_774; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_805 = _T_804 | _T_775; // @[Mux.scala 27:72]
|
|
wire _T_808 = io_raddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_810 = io_raddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_812 = io_raddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_814 = io_raddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_816 = io_raddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_818 = io_raddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_820 = io_raddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_822 = io_raddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_824 = io_raddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_826 = io_raddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_828 = io_raddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_830 = io_raddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_832 = io_raddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_834 = io_raddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_836 = io_raddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_838 = io_raddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_840 = io_raddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_842 = io_raddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_844 = io_raddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_846 = io_raddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_848 = io_raddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_850 = io_raddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_852 = io_raddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_854 = io_raddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_856 = io_raddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_858 = io_raddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_860 = io_raddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_862 = io_raddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_864 = io_raddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_866 = io_raddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire _T_868 = io_raddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 48:49]
|
|
wire [31:0] _T_870 = _T_808 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_871 = _T_810 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_872 = _T_812 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_873 = _T_814 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_874 = _T_816 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_875 = _T_818 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_876 = _T_820 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_877 = _T_822 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_878 = _T_824 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_879 = _T_826 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_880 = _T_828 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_881 = _T_830 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_882 = _T_832 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_883 = _T_834 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_884 = _T_836 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_885 = _T_838 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_886 = _T_840 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_887 = _T_842 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_888 = _T_844 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_889 = _T_846 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_890 = _T_848 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_891 = _T_850 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_892 = _T_852 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_893 = _T_854 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_894 = _T_856 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_895 = _T_858 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_896 = _T_860 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_897 = _T_862 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_898 = _T_864 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_899 = _T_866 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_900 = _T_868 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_901 = _T_870 | _T_871; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_902 = _T_901 | _T_872; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_903 = _T_902 | _T_873; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_904 = _T_903 | _T_874; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_905 = _T_904 | _T_875; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_906 = _T_905 | _T_876; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_907 = _T_906 | _T_877; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_908 = _T_907 | _T_878; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_909 = _T_908 | _T_879; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_910 = _T_909 | _T_880; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_911 = _T_910 | _T_881; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_912 = _T_911 | _T_882; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_913 = _T_912 | _T_883; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_914 = _T_913 | _T_884; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_915 = _T_914 | _T_885; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_916 = _T_915 | _T_886; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_917 = _T_916 | _T_887; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_918 = _T_917 | _T_888; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_919 = _T_918 | _T_889; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_920 = _T_919 | _T_890; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_921 = _T_920 | _T_891; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_922 = _T_921 | _T_892; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_923 = _T_922 | _T_893; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_924 = _T_923 | _T_894; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_925 = _T_924 | _T_895; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_926 = _T_925 | _T_896; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_927 = _T_926 | _T_897; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_928 = _T_927 | _T_898; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_929 = _T_928 | _T_899; // @[Mux.scala 27:72]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en),
|
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en),
|
|
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_8_io_l1clk),
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en),
|
|
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_9_io_l1clk),
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en),
|
|
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_10_io_l1clk),
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en),
|
|
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_11_io_l1clk),
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en),
|
|
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_12_io_l1clk),
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en),
|
|
.io_scan_mode(rvclkhdr_12_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_13_io_l1clk),
|
|
.io_clk(rvclkhdr_13_io_clk),
|
|
.io_en(rvclkhdr_13_io_en),
|
|
.io_scan_mode(rvclkhdr_13_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_14_io_l1clk),
|
|
.io_clk(rvclkhdr_14_io_clk),
|
|
.io_en(rvclkhdr_14_io_en),
|
|
.io_scan_mode(rvclkhdr_14_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_15_io_l1clk),
|
|
.io_clk(rvclkhdr_15_io_clk),
|
|
.io_en(rvclkhdr_15_io_en),
|
|
.io_scan_mode(rvclkhdr_15_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_16_io_l1clk),
|
|
.io_clk(rvclkhdr_16_io_clk),
|
|
.io_en(rvclkhdr_16_io_en),
|
|
.io_scan_mode(rvclkhdr_16_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_17_io_l1clk),
|
|
.io_clk(rvclkhdr_17_io_clk),
|
|
.io_en(rvclkhdr_17_io_en),
|
|
.io_scan_mode(rvclkhdr_17_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_18_io_l1clk),
|
|
.io_clk(rvclkhdr_18_io_clk),
|
|
.io_en(rvclkhdr_18_io_en),
|
|
.io_scan_mode(rvclkhdr_18_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_19_io_l1clk),
|
|
.io_clk(rvclkhdr_19_io_clk),
|
|
.io_en(rvclkhdr_19_io_en),
|
|
.io_scan_mode(rvclkhdr_19_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_20_io_l1clk),
|
|
.io_clk(rvclkhdr_20_io_clk),
|
|
.io_en(rvclkhdr_20_io_en),
|
|
.io_scan_mode(rvclkhdr_20_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_21_io_l1clk),
|
|
.io_clk(rvclkhdr_21_io_clk),
|
|
.io_en(rvclkhdr_21_io_en),
|
|
.io_scan_mode(rvclkhdr_21_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_22_io_l1clk),
|
|
.io_clk(rvclkhdr_22_io_clk),
|
|
.io_en(rvclkhdr_22_io_en),
|
|
.io_scan_mode(rvclkhdr_22_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_23_io_l1clk),
|
|
.io_clk(rvclkhdr_23_io_clk),
|
|
.io_en(rvclkhdr_23_io_en),
|
|
.io_scan_mode(rvclkhdr_23_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_24_io_l1clk),
|
|
.io_clk(rvclkhdr_24_io_clk),
|
|
.io_en(rvclkhdr_24_io_en),
|
|
.io_scan_mode(rvclkhdr_24_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_25_io_l1clk),
|
|
.io_clk(rvclkhdr_25_io_clk),
|
|
.io_en(rvclkhdr_25_io_en),
|
|
.io_scan_mode(rvclkhdr_25_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_26_io_l1clk),
|
|
.io_clk(rvclkhdr_26_io_clk),
|
|
.io_en(rvclkhdr_26_io_en),
|
|
.io_scan_mode(rvclkhdr_26_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_27_io_l1clk),
|
|
.io_clk(rvclkhdr_27_io_clk),
|
|
.io_en(rvclkhdr_27_io_en),
|
|
.io_scan_mode(rvclkhdr_27_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_28_io_l1clk),
|
|
.io_clk(rvclkhdr_28_io_clk),
|
|
.io_en(rvclkhdr_28_io_en),
|
|
.io_scan_mode(rvclkhdr_28_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_29_io_l1clk),
|
|
.io_clk(rvclkhdr_29_io_clk),
|
|
.io_en(rvclkhdr_29_io_en),
|
|
.io_scan_mode(rvclkhdr_29_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_30_io_l1clk),
|
|
.io_clk(rvclkhdr_30_io_clk),
|
|
.io_en(rvclkhdr_30_io_en),
|
|
.io_scan_mode(rvclkhdr_30_io_scan_mode)
|
|
);
|
|
assign io_rd0 = _T_805 | _T_776; // @[el2_dec_gpr_ctl.scala 31:9 el2_dec_gpr_ctl.scala 47:9]
|
|
assign io_rd1 = _T_929 | _T_900; // @[el2_dec_gpr_ctl.scala 32:9 el2_dec_gpr_ctl.scala 48:9]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = gpr_wr_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = gpr_wr_en[2]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_2_io_en = gpr_wr_en[3]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = gpr_wr_en[4]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_4_io_en = gpr_wr_en[5]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_5_io_en = gpr_wr_en[6]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_6_io_en = gpr_wr_en[7]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_7_io_en = gpr_wr_en[8]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_8_io_en = gpr_wr_en[9]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_9_io_en = gpr_wr_en[10]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_10_io_en = gpr_wr_en[11]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_11_io_en = gpr_wr_en[12]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_12_io_en = gpr_wr_en[13]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_13_io_en = gpr_wr_en[14]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_14_io_en = gpr_wr_en[15]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_15_io_en = gpr_wr_en[16]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_16_io_en = gpr_wr_en[17]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_17_io_en = gpr_wr_en[18]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_18_io_en = gpr_wr_en[19]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_19_io_en = gpr_wr_en[20]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_20_io_en = gpr_wr_en[21]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_21_io_en = gpr_wr_en[22]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_22_io_en = gpr_wr_en[23]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_23_io_en = gpr_wr_en[24]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_24_io_en = gpr_wr_en[25]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_25_io_en = gpr_wr_en[26]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_26_io_en = gpr_wr_en[27]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_27_io_en = gpr_wr_en[28]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_28_io_en = gpr_wr_en[29]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_29_io_en = gpr_wr_en[30]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_30_io_en = gpr_wr_en[31]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
gpr_out_1 = _RAND_0[31:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
gpr_out_2 = _RAND_1[31:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
gpr_out_3 = _RAND_2[31:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
gpr_out_4 = _RAND_3[31:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
gpr_out_5 = _RAND_4[31:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
gpr_out_6 = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
gpr_out_7 = _RAND_6[31:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
gpr_out_8 = _RAND_7[31:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
gpr_out_9 = _RAND_8[31:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
gpr_out_10 = _RAND_9[31:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
gpr_out_11 = _RAND_10[31:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
gpr_out_12 = _RAND_11[31:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
gpr_out_13 = _RAND_12[31:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
gpr_out_14 = _RAND_13[31:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
gpr_out_15 = _RAND_14[31:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
gpr_out_16 = _RAND_15[31:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
gpr_out_17 = _RAND_16[31:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
gpr_out_18 = _RAND_17[31:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
gpr_out_19 = _RAND_18[31:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
gpr_out_20 = _RAND_19[31:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
gpr_out_21 = _RAND_20[31:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
gpr_out_22 = _RAND_21[31:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
gpr_out_23 = _RAND_22[31:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
gpr_out_24 = _RAND_23[31:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
gpr_out_25 = _RAND_24[31:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
gpr_out_26 = _RAND_25[31:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
gpr_out_27 = _RAND_26[31:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
gpr_out_28 = _RAND_27[31:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
gpr_out_29 = _RAND_28[31:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
gpr_out_30 = _RAND_29[31:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
gpr_out_31 = _RAND_30[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
gpr_out_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_4 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_5 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_6 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_7 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_8 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_9 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_10 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_11 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_12 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_13 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_14 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_15 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_16 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_17 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_18 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_19 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_20 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_21 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_22 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_23 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_24 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_25 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_26 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_27 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_28 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_29 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_30 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_31 = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_1 <= 32'h0;
|
|
end else begin
|
|
gpr_out_1 <= _T_12 | _T_15;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_2 <= 32'h0;
|
|
end else begin
|
|
gpr_out_2 <= _T_29 | _T_32;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_3 <= 32'h0;
|
|
end else begin
|
|
gpr_out_3 <= _T_46 | _T_49;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_4 <= 32'h0;
|
|
end else begin
|
|
gpr_out_4 <= _T_63 | _T_66;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_5 <= 32'h0;
|
|
end else begin
|
|
gpr_out_5 <= _T_80 | _T_83;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_6 <= 32'h0;
|
|
end else begin
|
|
gpr_out_6 <= _T_97 | _T_100;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_7 <= 32'h0;
|
|
end else begin
|
|
gpr_out_7 <= _T_114 | _T_117;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_8 <= 32'h0;
|
|
end else begin
|
|
gpr_out_8 <= _T_131 | _T_134;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_9 <= 32'h0;
|
|
end else begin
|
|
gpr_out_9 <= _T_148 | _T_151;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_10 <= 32'h0;
|
|
end else begin
|
|
gpr_out_10 <= _T_165 | _T_168;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_11 <= 32'h0;
|
|
end else begin
|
|
gpr_out_11 <= _T_182 | _T_185;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_12 <= 32'h0;
|
|
end else begin
|
|
gpr_out_12 <= _T_199 | _T_202;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_13 <= 32'h0;
|
|
end else begin
|
|
gpr_out_13 <= _T_216 | _T_219;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_14 <= 32'h0;
|
|
end else begin
|
|
gpr_out_14 <= _T_233 | _T_236;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_15 <= 32'h0;
|
|
end else begin
|
|
gpr_out_15 <= _T_250 | _T_253;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_16 <= 32'h0;
|
|
end else begin
|
|
gpr_out_16 <= _T_267 | _T_270;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_17 <= 32'h0;
|
|
end else begin
|
|
gpr_out_17 <= _T_284 | _T_287;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_18 <= 32'h0;
|
|
end else begin
|
|
gpr_out_18 <= _T_301 | _T_304;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_19 <= 32'h0;
|
|
end else begin
|
|
gpr_out_19 <= _T_318 | _T_321;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_20 <= 32'h0;
|
|
end else begin
|
|
gpr_out_20 <= _T_335 | _T_338;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_21 <= 32'h0;
|
|
end else begin
|
|
gpr_out_21 <= _T_352 | _T_355;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_22 <= 32'h0;
|
|
end else begin
|
|
gpr_out_22 <= _T_369 | _T_372;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_23 <= 32'h0;
|
|
end else begin
|
|
gpr_out_23 <= _T_386 | _T_389;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_24 <= 32'h0;
|
|
end else begin
|
|
gpr_out_24 <= _T_403 | _T_406;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_25 <= 32'h0;
|
|
end else begin
|
|
gpr_out_25 <= _T_420 | _T_423;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_26 <= 32'h0;
|
|
end else begin
|
|
gpr_out_26 <= _T_437 | _T_440;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_27 <= 32'h0;
|
|
end else begin
|
|
gpr_out_27 <= _T_454 | _T_457;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_28 <= 32'h0;
|
|
end else begin
|
|
gpr_out_28 <= _T_471 | _T_474;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_29 <= 32'h0;
|
|
end else begin
|
|
gpr_out_29 <= _T_488 | _T_491;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_30 <= 32'h0;
|
|
end else begin
|
|
gpr_out_30 <= _T_505 | _T_508;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_31 <= 32'h0;
|
|
end else begin
|
|
gpr_out_31 <= _T_522 | _T_525;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_dec_timer_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_free_clk,
|
|
input io_scan_mode,
|
|
input io_dec_csr_wen_r_mod,
|
|
input [11:0] io_dec_csr_wraddr_r,
|
|
input [31:0] io_dec_csr_wrdata_r,
|
|
input io_csr_mitctl0,
|
|
input io_csr_mitctl1,
|
|
input io_csr_mitb0,
|
|
input io_csr_mitb1,
|
|
input io_csr_mitcnt0,
|
|
input io_csr_mitcnt1,
|
|
input io_dec_pause_state,
|
|
input io_dec_tlu_pmu_fw_halted,
|
|
input io_internal_dbg_halt_timers,
|
|
output [31:0] io_dec_timer_rddata_d,
|
|
output io_dec_timer_read_d,
|
|
output io_dec_timer_t0_pulse,
|
|
output io_dec_timer_t1_pulse
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
reg [31:0] mitcnt0; // @[el2_lib.scala 514:16]
|
|
reg [31:0] mitb0_b; // @[el2_lib.scala 514:16]
|
|
wire [31:0] mitb0 = ~mitb0_b; // @[el2_dec_tlu_ctl.scala 2791:14]
|
|
wire mit0_match_ns = mitcnt0 >= mitb0; // @[el2_dec_tlu_ctl.scala 2752:30]
|
|
reg [31:0] mitcnt1; // @[el2_lib.scala 514:16]
|
|
reg [31:0] mitb1_b; // @[el2_lib.scala 514:16]
|
|
wire [31:0] mitb1 = ~mitb1_b; // @[el2_dec_tlu_ctl.scala 2800:12]
|
|
wire mit1_match_ns = mitcnt1 >= mitb1; // @[el2_dec_tlu_ctl.scala 2753:30]
|
|
wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[el2_dec_tlu_ctl.scala 2763:66]
|
|
wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[el2_dec_tlu_ctl.scala 2763:43]
|
|
reg [1:0] _T_57; // @[el2_dec_tlu_ctl.scala 2816:67]
|
|
reg mitctl0_0_b; // @[el2_dec_tlu_ctl.scala 2815:54]
|
|
wire _T_58 = ~mitctl0_0_b; // @[el2_dec_tlu_ctl.scala 2816:90]
|
|
wire [2:0] mitctl0 = {_T_57,_T_58}; // @[Cat.scala 29:58]
|
|
wire _T_2 = ~io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 2765:50]
|
|
wire _T_4 = _T_2 | mitctl0[2]; // @[el2_dec_tlu_ctl.scala 2765:70]
|
|
wire _T_5 = mitctl0[0] & _T_4; // @[el2_dec_tlu_ctl.scala 2765:47]
|
|
wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 2765:106]
|
|
wire _T_8 = _T_6 | mitctl0[1]; // @[el2_dec_tlu_ctl.scala 2765:132]
|
|
wire _T_9 = _T_5 & _T_8; // @[el2_dec_tlu_ctl.scala 2765:103]
|
|
wire _T_10 = ~io_internal_dbg_halt_timers; // @[el2_dec_tlu_ctl.scala 2765:167]
|
|
wire mitcnt0_inc_ok = _T_9 & _T_10; // @[el2_dec_tlu_ctl.scala 2765:165]
|
|
wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[el2_dec_tlu_ctl.scala 2766:29]
|
|
wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[el2_dec_tlu_ctl.scala 2768:59]
|
|
wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[el2_dec_tlu_ctl.scala 2775:66]
|
|
wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[el2_dec_tlu_ctl.scala 2775:43]
|
|
reg [2:0] _T_66; // @[el2_dec_tlu_ctl.scala 2830:46]
|
|
reg mitctl1_0_b; // @[el2_dec_tlu_ctl.scala 2829:49]
|
|
wire _T_67 = ~mitctl1_0_b; // @[el2_dec_tlu_ctl.scala 2830:69]
|
|
wire [3:0] mitctl1 = {_T_66,_T_67}; // @[Cat.scala 29:58]
|
|
wire _T_23 = _T_2 | mitctl1[2]; // @[el2_dec_tlu_ctl.scala 2777:70]
|
|
wire _T_24 = mitctl1[0] & _T_23; // @[el2_dec_tlu_ctl.scala 2777:47]
|
|
wire _T_27 = _T_6 | mitctl1[1]; // @[el2_dec_tlu_ctl.scala 2777:132]
|
|
wire _T_28 = _T_24 & _T_27; // @[el2_dec_tlu_ctl.scala 2777:103]
|
|
wire mitcnt1_inc_ok = _T_28 & _T_10; // @[el2_dec_tlu_ctl.scala 2777:165]
|
|
wire _T_32 = ~mitctl1[3]; // @[el2_dec_tlu_ctl.scala 2780:54]
|
|
wire _T_33 = _T_32 | mit0_match_ns; // @[el2_dec_tlu_ctl.scala 2780:66]
|
|
wire [31:0] _T_34 = {31'h0,_T_33}; // @[Cat.scala 29:58]
|
|
wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[el2_dec_tlu_ctl.scala 2780:29]
|
|
wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[el2_dec_tlu_ctl.scala 2782:52]
|
|
wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[el2_dec_tlu_ctl.scala 2789:64]
|
|
wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[el2_dec_tlu_ctl.scala 2798:63]
|
|
wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[el2_dec_tlu_ctl.scala 2811:66]
|
|
wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[el2_dec_tlu_ctl.scala 2811:43]
|
|
wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[el2_dec_tlu_ctl.scala 2812:31]
|
|
wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[el2_dec_tlu_ctl.scala 2826:65]
|
|
wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[el2_dec_tlu_ctl.scala 2826:43]
|
|
wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[el2_dec_tlu_ctl.scala 2827:31]
|
|
wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 2832:43]
|
|
wire _T_70 = _T_69 | io_csr_mitb1; // @[el2_dec_tlu_ctl.scala 2832:60]
|
|
wire _T_71 = _T_70 | io_csr_mitb0; // @[el2_dec_tlu_ctl.scala 2832:75]
|
|
wire _T_72 = _T_71 | io_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 2832:90]
|
|
wire [31:0] _T_81 = {29'h0,_T_57,_T_58}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_84 = {28'h0,_T_66,_T_67}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_85 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_86 = io_csr_mitcnt1 ? mitcnt1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_87 = io_csr_mitb0 ? mitb0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_88 = io_csr_mitb1 ? mitb1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_89 = io_csr_mitctl0 ? _T_81 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_90 = io_csr_mitctl1 ? _T_84 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_91 = _T_85 | _T_86; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_92 = _T_91 | _T_87; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_93 = _T_92 | _T_88; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_94 = _T_93 | _T_89; // @[Mux.scala 27:72]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[el2_dec_tlu_ctl.scala 2833:33]
|
|
assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 2832:25]
|
|
assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[el2_dec_tlu_ctl.scala 2755:25]
|
|
assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[el2_dec_tlu_ctl.scala 2756:25]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = _T_39 | mit1_match_ns; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_2_io_en = io_dec_csr_wen_r_mod & _T_43; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = io_dec_csr_wen_r_mod & _T_47; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
mitcnt0 = _RAND_0[31:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
mitb0_b = _RAND_1[31:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
mitcnt1 = _RAND_2[31:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
mitb1_b = _RAND_3[31:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_57 = _RAND_4[1:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
mitctl0_0_b = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_66 = _RAND_6[2:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
mitctl1_0_b = _RAND_7[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
mitcnt0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mitb0_b = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mitcnt1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mitb1_b = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_57 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
mitctl0_0_b = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_66 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
mitctl1_0_b = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mitcnt0 <= 32'h0;
|
|
end else if (mit0_match_ns) begin
|
|
mitcnt0 <= 32'h0;
|
|
end else if (wr_mitcnt0_r) begin
|
|
mitcnt0 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mitcnt0 <= mitcnt0_inc;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mitb0_b <= 32'h0;
|
|
end else begin
|
|
mitb0_b <= ~io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mitcnt1 <= 32'h0;
|
|
end else if (mit1_match_ns) begin
|
|
mitcnt1 <= 32'h0;
|
|
end else if (wr_mitcnt1_r) begin
|
|
mitcnt1 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mitcnt1 <= mitcnt1_inc;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mitb1_b <= 32'h0;
|
|
end else begin
|
|
mitb1_b <= ~io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_57 <= 2'h0;
|
|
end else begin
|
|
_T_57 <= mitctl0_ns[2:1];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mitctl0_0_b <= 1'h0;
|
|
end else begin
|
|
mitctl0_0_b <= ~mitctl0_ns[0];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_66 <= 3'h0;
|
|
end else begin
|
|
_T_66 <= mitctl1_ns[3:1];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mitctl1_0_b <= 1'h0;
|
|
end else begin
|
|
mitctl1_0_b <= ~mitctl1_ns[0];
|
|
end
|
|
end
|
|
endmodule
|
|
module csr_tlu(
|
|
input clock,
|
|
input reset,
|
|
input io_free_clk,
|
|
input io_active_clk,
|
|
input io_scan_mode,
|
|
input [31:0] io_dec_csr_wrdata_r,
|
|
input [11:0] io_dec_csr_wraddr_r,
|
|
input [11:0] io_dec_csr_rdaddr_d,
|
|
input io_dec_csr_wen_unq_d,
|
|
input io_dec_i0_decode_d,
|
|
output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata,
|
|
output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics,
|
|
output io_dec_tlu_ic_diag_pkt_icache_rd_valid,
|
|
output io_dec_tlu_ic_diag_pkt_icache_wr_valid,
|
|
input io_ifu_ic_debug_rd_data_valid,
|
|
output io_trigger_pkt_any_0_select,
|
|
output io_trigger_pkt_any_0_match_pkt,
|
|
output io_trigger_pkt_any_0_store,
|
|
output io_trigger_pkt_any_0_load,
|
|
output io_trigger_pkt_any_0_execute,
|
|
output io_trigger_pkt_any_0_m,
|
|
output [31:0] io_trigger_pkt_any_0_tdata2,
|
|
output io_trigger_pkt_any_1_select,
|
|
output io_trigger_pkt_any_1_match_pkt,
|
|
output io_trigger_pkt_any_1_store,
|
|
output io_trigger_pkt_any_1_load,
|
|
output io_trigger_pkt_any_1_execute,
|
|
output io_trigger_pkt_any_1_m,
|
|
output [31:0] io_trigger_pkt_any_1_tdata2,
|
|
output io_trigger_pkt_any_2_select,
|
|
output io_trigger_pkt_any_2_match_pkt,
|
|
output io_trigger_pkt_any_2_store,
|
|
output io_trigger_pkt_any_2_load,
|
|
output io_trigger_pkt_any_2_execute,
|
|
output io_trigger_pkt_any_2_m,
|
|
output [31:0] io_trigger_pkt_any_2_tdata2,
|
|
output io_trigger_pkt_any_3_select,
|
|
output io_trigger_pkt_any_3_match_pkt,
|
|
output io_trigger_pkt_any_3_store,
|
|
output io_trigger_pkt_any_3_load,
|
|
output io_trigger_pkt_any_3_execute,
|
|
output io_trigger_pkt_any_3_m,
|
|
output [31:0] io_trigger_pkt_any_3_tdata2,
|
|
input io_ifu_pmu_bus_trxn,
|
|
input io_dma_iccm_stall_any,
|
|
input io_dma_dccm_stall_any,
|
|
input io_lsu_store_stall_any,
|
|
input io_dec_pmu_presync_stall,
|
|
input io_dec_pmu_postsync_stall,
|
|
input io_dec_pmu_decode_stall,
|
|
input io_ifu_pmu_fetch_stall,
|
|
input [1:0] io_dec_tlu_packet_r_icaf_type,
|
|
input [3:0] io_dec_tlu_packet_r_pmu_i0_itype,
|
|
input io_dec_tlu_packet_r_pmu_i0_br_unpred,
|
|
input io_dec_tlu_packet_r_pmu_divide,
|
|
input io_dec_tlu_packet_r_pmu_lsu_misaligned,
|
|
input io_exu_pmu_i0_br_ataken,
|
|
input io_exu_pmu_i0_br_misp,
|
|
input io_dec_pmu_instr_decoded,
|
|
input io_ifu_pmu_instr_aligned,
|
|
input io_exu_pmu_i0_pc4,
|
|
input io_ifu_pmu_ic_miss,
|
|
input io_ifu_pmu_ic_hit,
|
|
output io_dec_tlu_int_valid_wb1,
|
|
output io_dec_tlu_i0_exc_valid_wb1,
|
|
output io_dec_tlu_i0_valid_wb1,
|
|
input io_dec_csr_wen_r,
|
|
output [31:0] io_dec_tlu_mtval_wb1,
|
|
output [4:0] io_dec_tlu_exc_cause_wb1,
|
|
output io_dec_tlu_perfcnt0,
|
|
output io_dec_tlu_perfcnt1,
|
|
output io_dec_tlu_perfcnt2,
|
|
output io_dec_tlu_perfcnt3,
|
|
input io_dec_tlu_dbg_halted,
|
|
input io_dma_pmu_dccm_write,
|
|
input io_dma_pmu_dccm_read,
|
|
input io_dma_pmu_any_write,
|
|
input io_dma_pmu_any_read,
|
|
input io_lsu_pmu_bus_busy,
|
|
input [30:0] io_dec_tlu_i0_pc_r,
|
|
input io_dec_tlu_i0_valid_r,
|
|
input io_dec_csr_any_unq_d,
|
|
output io_dec_tlu_misc_clk_override,
|
|
output io_dec_tlu_dec_clk_override,
|
|
output io_dec_tlu_lsu_clk_override,
|
|
output io_dec_tlu_pic_clk_override,
|
|
output io_dec_tlu_dccm_clk_override,
|
|
output io_dec_tlu_icm_clk_override,
|
|
output [31:0] io_dec_csr_rddata_d,
|
|
output io_dec_tlu_pipelining_disable,
|
|
output io_dec_tlu_wr_pause_r,
|
|
input io_ifu_pmu_bus_busy,
|
|
input io_lsu_pmu_bus_error,
|
|
input io_ifu_pmu_bus_error,
|
|
input io_lsu_pmu_bus_misaligned,
|
|
input io_lsu_pmu_bus_trxn,
|
|
input [70:0] io_ifu_ic_debug_rd_data,
|
|
output [3:0] io_dec_tlu_meipt,
|
|
input [3:0] io_pic_pl,
|
|
output [3:0] io_dec_tlu_meicurpl,
|
|
output [29:0] io_dec_tlu_meihap,
|
|
input [7:0] io_pic_claimid,
|
|
input io_iccm_dma_sb_error,
|
|
input [31:0] io_lsu_imprecise_error_addr_any,
|
|
input io_lsu_imprecise_error_load_any,
|
|
input io_lsu_imprecise_error_store_any,
|
|
output [31:0] io_dec_tlu_mrac_ff,
|
|
output io_dec_tlu_wb_coalescing_disable,
|
|
output io_dec_tlu_bpred_disable,
|
|
output io_dec_tlu_sideeffect_posted_disable,
|
|
output io_dec_tlu_core_ecc_disable,
|
|
output io_dec_tlu_external_ldfwd_disable,
|
|
output [2:0] io_dec_tlu_dma_qos_prty,
|
|
input [31:0] io_dec_illegal_inst,
|
|
input [3:0] io_lsu_error_pkt_r_bits_mscause,
|
|
input io_mexintpend,
|
|
input [30:0] io_exu_npc_r,
|
|
input io_mpc_reset_run_req,
|
|
input [30:0] io_rst_vec,
|
|
input [27:0] io_core_id,
|
|
input [31:0] io_dec_timer_rddata_d,
|
|
input io_dec_timer_read_d,
|
|
output io_dec_csr_wen_r_mod,
|
|
input io_rfpc_i0_r,
|
|
input io_i0_trigger_hit_r,
|
|
output io_fw_halt_req,
|
|
output [1:0] io_mstatus,
|
|
input io_exc_or_int_valid_r,
|
|
input io_mret_r,
|
|
output io_mstatus_mie_ns,
|
|
input io_dcsr_single_step_running_f,
|
|
output [15:0] io_dcsr,
|
|
output [30:0] io_mtvec,
|
|
output [5:0] io_mip,
|
|
input io_dec_timer_t0_pulse,
|
|
input io_dec_timer_t1_pulse,
|
|
input io_timer_int_sync,
|
|
input io_soft_int_sync,
|
|
output [5:0] io_mie_ns,
|
|
input io_csr_wr_clk,
|
|
input io_ebreak_to_debug_mode_r,
|
|
input io_dec_tlu_pmu_fw_halted,
|
|
input [1:0] io_lsu_fir_error,
|
|
output [30:0] io_npc_r,
|
|
input io_tlu_flush_lower_r_d1,
|
|
input io_dec_tlu_flush_noredir_r_d1,
|
|
input [30:0] io_tlu_flush_path_r_d1,
|
|
output [30:0] io_npc_r_d1,
|
|
input io_reset_delayed,
|
|
output [30:0] io_mepc,
|
|
input io_interrupt_valid_r,
|
|
input io_i0_exception_valid_r,
|
|
input io_lsu_exc_valid_r,
|
|
input io_mepc_trigger_hit_sel_pc_r,
|
|
input io_e4e5_int_clk,
|
|
input io_lsu_i0_exc_r,
|
|
input io_inst_acc_r,
|
|
input io_inst_acc_second_r,
|
|
input io_take_nmi,
|
|
input [31:0] io_lsu_error_pkt_addr_r,
|
|
input [4:0] io_exc_cause_r,
|
|
input io_i0_valid_wb,
|
|
input io_exc_or_int_valid_r_d1,
|
|
input io_interrupt_valid_r_d1,
|
|
input io_clk_override,
|
|
input io_i0_exception_valid_r_d1,
|
|
input io_lsu_i0_exc_r_d1,
|
|
input [4:0] io_exc_cause_wb,
|
|
input io_nmi_lsu_store_type,
|
|
input io_nmi_lsu_load_type,
|
|
input io_tlu_i0_commit_cmt,
|
|
input io_ebreak_r,
|
|
input io_ecall_r,
|
|
input io_illegal_r,
|
|
output io_mdseac_locked_ns,
|
|
input io_mdseac_locked_f,
|
|
input io_nmi_int_detected_f,
|
|
input io_internal_dbg_halt_mode_f2,
|
|
input io_ext_int_freeze_d1,
|
|
input io_ic_perr_r_d1,
|
|
input io_iccm_sbecc_r_d1,
|
|
input io_lsu_single_ecc_error_r_d1,
|
|
input io_ifu_miss_state_idle_f,
|
|
input io_lsu_idle_any_f,
|
|
input io_dbg_tlu_halted_f,
|
|
input io_dbg_tlu_halted,
|
|
input io_debug_halt_req_f,
|
|
output io_force_halt,
|
|
input io_take_ext_int_start,
|
|
input io_trigger_hit_dmode_r_d1,
|
|
input io_trigger_hit_r_d1,
|
|
input io_dcsr_single_step_done_f,
|
|
input io_ebreak_to_debug_mode_r_d1,
|
|
input io_debug_halt_req,
|
|
input io_allow_dbg_halt_csr_write,
|
|
input io_internal_dbg_halt_mode_f,
|
|
input io_enter_debug_halt_req,
|
|
input io_internal_dbg_halt_mode,
|
|
input io_request_debug_mode_done,
|
|
input io_request_debug_mode_r,
|
|
output [30:0] io_dpc,
|
|
input [3:0] io_update_hit_bit_r,
|
|
input io_take_timer_int,
|
|
input io_take_int_timer0_int,
|
|
input io_take_int_timer1_int,
|
|
input io_take_ext_int,
|
|
input io_tlu_flush_lower_r,
|
|
input io_dec_tlu_br0_error_r,
|
|
input io_dec_tlu_br0_start_error_r,
|
|
input io_lsu_pmu_load_external_r,
|
|
input io_lsu_pmu_store_external_r,
|
|
input io_csr_pkt_csr_misa,
|
|
input io_csr_pkt_csr_mvendorid,
|
|
input io_csr_pkt_csr_marchid,
|
|
input io_csr_pkt_csr_mimpid,
|
|
input io_csr_pkt_csr_mhartid,
|
|
input io_csr_pkt_csr_mstatus,
|
|
input io_csr_pkt_csr_mtvec,
|
|
input io_csr_pkt_csr_mip,
|
|
input io_csr_pkt_csr_mie,
|
|
input io_csr_pkt_csr_mcyclel,
|
|
input io_csr_pkt_csr_mcycleh,
|
|
input io_csr_pkt_csr_minstretl,
|
|
input io_csr_pkt_csr_minstreth,
|
|
input io_csr_pkt_csr_mscratch,
|
|
input io_csr_pkt_csr_mepc,
|
|
input io_csr_pkt_csr_mcause,
|
|
input io_csr_pkt_csr_mscause,
|
|
input io_csr_pkt_csr_mtval,
|
|
input io_csr_pkt_csr_mrac,
|
|
input io_csr_pkt_csr_mdseac,
|
|
input io_csr_pkt_csr_meihap,
|
|
input io_csr_pkt_csr_meivt,
|
|
input io_csr_pkt_csr_meipt,
|
|
input io_csr_pkt_csr_meicurpl,
|
|
input io_csr_pkt_csr_meicidpl,
|
|
input io_csr_pkt_csr_dcsr,
|
|
input io_csr_pkt_csr_mcgc,
|
|
input io_csr_pkt_csr_mfdc,
|
|
input io_csr_pkt_csr_dpc,
|
|
input io_csr_pkt_csr_mtsel,
|
|
input io_csr_pkt_csr_mtdata1,
|
|
input io_csr_pkt_csr_mtdata2,
|
|
input io_csr_pkt_csr_mhpmc3,
|
|
input io_csr_pkt_csr_mhpmc4,
|
|
input io_csr_pkt_csr_mhpmc5,
|
|
input io_csr_pkt_csr_mhpmc6,
|
|
input io_csr_pkt_csr_mhpmc3h,
|
|
input io_csr_pkt_csr_mhpmc4h,
|
|
input io_csr_pkt_csr_mhpmc5h,
|
|
input io_csr_pkt_csr_mhpmc6h,
|
|
input io_csr_pkt_csr_mhpme3,
|
|
input io_csr_pkt_csr_mhpme4,
|
|
input io_csr_pkt_csr_mhpme5,
|
|
input io_csr_pkt_csr_mhpme6,
|
|
input io_csr_pkt_csr_mcountinhibit,
|
|
input io_csr_pkt_csr_mpmc,
|
|
input io_csr_pkt_csr_micect,
|
|
input io_csr_pkt_csr_miccmect,
|
|
input io_csr_pkt_csr_mdccmect,
|
|
input io_csr_pkt_csr_mfdht,
|
|
input io_csr_pkt_csr_mfdhs,
|
|
input io_csr_pkt_csr_dicawics,
|
|
input io_csr_pkt_csr_dicad0h,
|
|
input io_csr_pkt_csr_dicad0,
|
|
input io_csr_pkt_csr_dicad1,
|
|
output [9:0] io_mtdata1_t_0,
|
|
output [9:0] io_mtdata1_t_1,
|
|
output [9:0] io_mtdata1_t_2,
|
|
output [9:0] io_mtdata1_t_3
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [63:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [63:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [95:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_31_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_31_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_31_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_31_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_32_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_32_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_32_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_32_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_33_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_33_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_33_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_33_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_34_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_34_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_34_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_34_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire _T = ~io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 1530:46]
|
|
wire _T_1 = io_dec_csr_wen_r & _T; // @[el2_dec_tlu_ctl.scala 1530:44]
|
|
wire _T_2 = ~io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 1530:69]
|
|
wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[el2_dec_tlu_ctl.scala 1531:72]
|
|
wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[el2_dec_tlu_ctl.scala 1531:43]
|
|
wire _T_496 = io_dec_csr_wraddr_r == 12'h7c6; // @[el2_dec_tlu_ctl.scala 1917:69]
|
|
wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_496; // @[el2_dec_tlu_ctl.scala 1917:40]
|
|
wire _T_507 = ~io_dec_csr_wrdata_r[1]; // @[el2_dec_tlu_ctl.scala 1924:38]
|
|
reg mpmc_b; // @[el2_dec_tlu_ctl.scala 1926:45]
|
|
wire mpmc = ~mpmc_b; // @[el2_dec_tlu_ctl.scala 1929:11]
|
|
wire _T_508 = ~mpmc; // @[el2_dec_tlu_ctl.scala 1924:63]
|
|
wire mpmc_b_ns = wr_mpmc_r ? _T_507 : _T_508; // @[el2_dec_tlu_ctl.scala 1924:19]
|
|
wire _T_6 = ~mpmc_b_ns; // @[el2_dec_tlu_ctl.scala 1534:29]
|
|
wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 1534:40]
|
|
wire _T_7 = ~wr_mstatus_r; // @[el2_dec_tlu_ctl.scala 1537:6]
|
|
wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1537:20]
|
|
wire _T_12 = wr_mstatus_r & io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1538:19]
|
|
wire _T_15 = ~io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1539:18]
|
|
wire _T_16 = io_mret_r & _T_15; // @[el2_dec_tlu_ctl.scala 1539:16]
|
|
wire [1:0] _T_19 = {1'h1,io_mstatus[1]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_22 = {io_mstatus[1],1'h1}; // @[Cat.scala 29:58]
|
|
wire _T_24 = wr_mstatus_r & _T_15; // @[el2_dec_tlu_ctl.scala 1541:19]
|
|
wire [1:0] _T_28 = {io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58]
|
|
wire _T_31 = _T_7 & _T_15; // @[el2_dec_tlu_ctl.scala 1542:20]
|
|
wire _T_32 = ~io_mret_r; // @[el2_dec_tlu_ctl.scala 1542:47]
|
|
wire _T_33 = _T_31 & _T_32; // @[el2_dec_tlu_ctl.scala 1542:45]
|
|
wire _T_34 = ~set_mie_pmu_fw_halt; // @[el2_dec_tlu_ctl.scala 1542:60]
|
|
wire _T_35 = _T_33 & _T_34; // @[el2_dec_tlu_ctl.scala 1542:58]
|
|
wire _T_37 = _T_8 & io_mstatus[0]; // @[Mux.scala 27:72]
|
|
wire _T_38 = _T_12 & io_dec_csr_wrdata_r[3]; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_39 = _T_16 ? _T_19 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_40 = set_mie_pmu_fw_halt ? _T_22 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_41 = _T_24 ? _T_28 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_42 = _T_35 ? io_mstatus : 2'h0; // @[Mux.scala 27:72]
|
|
wire _T_43 = _T_37 | _T_38; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_9 = {{1'd0}, _T_43}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_44 = _GEN_9 | _T_39; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_45 = _T_44 | _T_40; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_46 = _T_45 | _T_41; // @[Mux.scala 27:72]
|
|
wire _T_50 = ~io_dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 1545:51]
|
|
wire _T_52 = _T_50 | io_dcsr[11]; // @[el2_dec_tlu_ctl.scala 1545:82]
|
|
reg [1:0] _T_54; // @[el2_dec_tlu_ctl.scala 1547:12]
|
|
wire _T_56 = io_dec_csr_wraddr_r == 12'h305; // @[el2_dec_tlu_ctl.scala 1556:70]
|
|
reg [30:0] _T_60; // @[el2_lib.scala 514:16]
|
|
reg [31:0] mdccmect; // @[el2_lib.scala 514:16]
|
|
wire [62:0] _T_572 = 63'hffffffff << mdccmect[31:27]; // @[el2_dec_tlu_ctl.scala 1975:42]
|
|
wire [31:0] _T_574 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58]
|
|
wire [62:0] _GEN_10 = {{31'd0}, _T_574}; // @[el2_dec_tlu_ctl.scala 1975:62]
|
|
wire [62:0] _T_575 = _T_572 & _GEN_10; // @[el2_dec_tlu_ctl.scala 1975:62]
|
|
wire mdccme_ce_req = |_T_575; // @[el2_dec_tlu_ctl.scala 1975:95]
|
|
reg [31:0] miccmect; // @[el2_lib.scala 514:16]
|
|
wire [62:0] _T_552 = 63'hffffffff << miccmect[31:27]; // @[el2_dec_tlu_ctl.scala 1960:42]
|
|
wire [31:0] _T_554 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58]
|
|
wire [62:0] _GEN_11 = {{31'd0}, _T_554}; // @[el2_dec_tlu_ctl.scala 1960:62]
|
|
wire [62:0] _T_555 = _T_552 & _GEN_11; // @[el2_dec_tlu_ctl.scala 1960:62]
|
|
wire miccme_ce_req = |_T_555; // @[el2_dec_tlu_ctl.scala 1960:95]
|
|
wire _T_61 = mdccme_ce_req | miccme_ce_req; // @[el2_dec_tlu_ctl.scala 1570:31]
|
|
reg [31:0] micect; // @[el2_lib.scala 514:16]
|
|
wire [62:0] _T_530 = 63'hffffffff << micect[31:27]; // @[el2_dec_tlu_ctl.scala 1946:39]
|
|
wire _T_531 = |_T_530; // @[el2_dec_tlu_ctl.scala 1946:57]
|
|
wire [31:0] _T_533 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _GEN_12 = {{31'd0}, _T_531}; // @[el2_dec_tlu_ctl.scala 1946:61]
|
|
wire [31:0] _T_534 = _GEN_12 & _T_533; // @[el2_dec_tlu_ctl.scala 1946:61]
|
|
wire mice_ce_req = _T_534[0]; // @[el2_dec_tlu_ctl.scala 1946:15]
|
|
wire ce_int = _T_61 | mice_ce_req; // @[el2_dec_tlu_ctl.scala 1570:47]
|
|
wire [2:0] _T_63 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58]
|
|
wire [2:0] _T_65 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58]
|
|
reg [5:0] _T_66; // @[el2_dec_tlu_ctl.scala 1574:12]
|
|
wire _T_68 = io_dec_csr_wraddr_r == 12'h304; // @[el2_dec_tlu_ctl.scala 1586:68]
|
|
wire wr_mie_r = io_dec_csr_wen_r_mod & _T_68; // @[el2_dec_tlu_ctl.scala 1586:39]
|
|
wire [5:0] _T_76 = {io_dec_csr_wrdata_r[30:28],io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58]
|
|
reg [5:0] mie; // @[el2_dec_tlu_ctl.scala 1589:12]
|
|
wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[el2_dec_tlu_ctl.scala 1596:55]
|
|
wire _T_81 = io_dec_csr_wraddr_r == 12'hb00; // @[el2_dec_tlu_ctl.scala 1598:72]
|
|
wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_81; // @[el2_dec_tlu_ctl.scala 1598:43]
|
|
wire _T_83 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[el2_dec_tlu_ctl.scala 1600:72]
|
|
wire _T_84 = kill_ebreak_count_r | _T_83; // @[el2_dec_tlu_ctl.scala 1600:47]
|
|
wire _T_85 = _T_84 | io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 1600:95]
|
|
reg [4:0] temp_ncount6_2; // @[Reg.scala 27:20]
|
|
reg temp_ncount0; // @[Reg.scala 27:20]
|
|
wire [6:0] mcountinhibit = {temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58]
|
|
wire _T_87 = _T_85 | mcountinhibit[0]; // @[el2_dec_tlu_ctl.scala 1600:122]
|
|
wire mcyclel_cout_in = ~_T_87; // @[el2_dec_tlu_ctl.scala 1600:25]
|
|
wire [31:0] _T_88 = {31'h0,mcyclel_cout_in}; // @[Cat.scala 29:58]
|
|
reg [32:0] _T_95; // @[el2_lib.scala 514:16]
|
|
wire [31:0] mcyclel = _T_95[31:0]; // @[el2_dec_tlu_ctl.scala 1607:11]
|
|
wire [31:0] _T_90 = mcyclel + _T_88; // @[el2_dec_tlu_ctl.scala 1604:26]
|
|
wire [32:0] mcyclel_inc = {{1'd0}, _T_90}; // @[el2_dec_tlu_ctl.scala 1604:15]
|
|
wire mcyclel_cout = mcyclel_inc[32]; // @[el2_dec_tlu_ctl.scala 1606:33]
|
|
wire _T_99 = io_dec_csr_wraddr_r == 12'hb80; // @[el2_dec_tlu_ctl.scala 1614:69]
|
|
wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_99; // @[el2_dec_tlu_ctl.scala 1614:40]
|
|
wire _T_96 = ~wr_mcycleh_r; // @[el2_dec_tlu_ctl.scala 1608:72]
|
|
reg mcyclel_cout_f; // @[el2_dec_tlu_ctl.scala 1608:55]
|
|
wire [31:0] _T_101 = {31'h0,mcyclel_cout_f}; // @[Cat.scala 29:58]
|
|
reg [31:0] mcycleh; // @[el2_lib.scala 514:16]
|
|
wire [31:0] mcycleh_inc = mcycleh + _T_101; // @[el2_dec_tlu_ctl.scala 1616:29]
|
|
wire _T_107 = io_ebreak_r | io_ecall_r; // @[el2_dec_tlu_ctl.scala 1633:73]
|
|
wire _T_108 = _T_107 | io_ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 1633:86]
|
|
wire _T_109 = _T_108 | io_illegal_r; // @[el2_dec_tlu_ctl.scala 1633:114]
|
|
wire _T_111 = _T_109 | mcountinhibit[2]; // @[el2_dec_tlu_ctl.scala 1633:129]
|
|
wire _T_113 = ~_T_111; // @[el2_dec_tlu_ctl.scala 1633:59]
|
|
wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_113; // @[el2_dec_tlu_ctl.scala 1633:57]
|
|
wire _T_115 = io_dec_csr_wraddr_r == 12'hb02; // @[el2_dec_tlu_ctl.scala 1635:74]
|
|
wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_115; // @[el2_dec_tlu_ctl.scala 1635:45]
|
|
wire [31:0] _T_116 = {31'h0,i0_valid_no_ebreak_ecall_r}; // @[Cat.scala 29:58]
|
|
reg [32:0] _T_122; // @[el2_lib.scala 514:16]
|
|
wire [31:0] minstretl = _T_122[31:0]; // @[el2_dec_tlu_ctl.scala 1642:13]
|
|
wire [31:0] _T_118 = minstretl + _T_116; // @[el2_dec_tlu_ctl.scala 1637:30]
|
|
wire [32:0] minstretl_inc = {{1'd0}, _T_118}; // @[el2_dec_tlu_ctl.scala 1637:17]
|
|
wire minstretl_cout = minstretl_inc[32]; // @[el2_dec_tlu_ctl.scala 1638:37]
|
|
reg minstret_enable_f; // @[el2_dec_tlu_ctl.scala 1643:57]
|
|
wire _T_126 = io_dec_csr_wraddr_r == 12'hb82; // @[el2_dec_tlu_ctl.scala 1652:72]
|
|
wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_126; // @[el2_dec_tlu_ctl.scala 1652:43]
|
|
wire _T_123 = ~wr_minstreth_r; // @[el2_dec_tlu_ctl.scala 1644:76]
|
|
reg minstretl_cout_f; // @[el2_dec_tlu_ctl.scala 1644:57]
|
|
wire [31:0] _T_129 = {31'h0,minstretl_cout_f}; // @[Cat.scala 29:58]
|
|
reg [31:0] minstreth; // @[el2_lib.scala 514:16]
|
|
wire [31:0] minstreth_inc = minstreth + _T_129; // @[el2_dec_tlu_ctl.scala 1655:30]
|
|
wire _T_137 = io_dec_csr_wraddr_r == 12'h340; // @[el2_dec_tlu_ctl.scala 1666:73]
|
|
reg [31:0] mscratch; // @[el2_lib.scala 514:16]
|
|
wire _T_140 = ~io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 1677:23]
|
|
wire _T_141 = ~io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1677:48]
|
|
wire _T_142 = _T_140 & _T_141; // @[el2_dec_tlu_ctl.scala 1677:46]
|
|
wire sel_exu_npc_r = _T_142 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 1677:73]
|
|
wire _T_144 = _T_140 & io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1678:48]
|
|
wire _T_145 = ~io_dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 1678:76]
|
|
wire sel_flush_npc_r = _T_144 & _T_145; // @[el2_dec_tlu_ctl.scala 1678:74]
|
|
wire _T_146 = ~sel_exu_npc_r; // @[el2_dec_tlu_ctl.scala 1679:24]
|
|
wire _T_147 = ~sel_flush_npc_r; // @[el2_dec_tlu_ctl.scala 1679:41]
|
|
wire sel_hold_npc_r = _T_146 & _T_147; // @[el2_dec_tlu_ctl.scala 1679:39]
|
|
wire _T_149 = ~io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 1683:6]
|
|
wire _T_150 = _T_149 & io_reset_delayed; // @[el2_dec_tlu_ctl.scala 1683:28]
|
|
wire [30:0] _T_154 = sel_exu_npc_r ? io_exu_npc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_155 = _T_150 ? io_rst_vec : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_156 = sel_flush_npc_r ? io_tlu_flush_path_r_d1 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_157 = sel_hold_npc_r ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_158 = _T_154 | _T_155; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_159 = _T_158 | _T_156; // @[Mux.scala 27:72]
|
|
wire _T_162 = sel_exu_npc_r | sel_flush_npc_r; // @[el2_dec_tlu_ctl.scala 1687:49]
|
|
reg [30:0] _T_165; // @[el2_lib.scala 514:16]
|
|
wire pc0_valid_r = _T_140 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 1690:45]
|
|
wire _T_168 = ~pc0_valid_r; // @[el2_dec_tlu_ctl.scala 1694:5]
|
|
wire [30:0] _T_169 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72]
|
|
reg [30:0] pc_r_d1; // @[el2_lib.scala 514:16]
|
|
wire [30:0] _T_170 = _T_168 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] pc_r = _T_169 | _T_170; // @[Mux.scala 27:72]
|
|
wire _T_174 = io_dec_csr_wraddr_r == 12'h341; // @[el2_dec_tlu_ctl.scala 1698:69]
|
|
wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_174; // @[el2_dec_tlu_ctl.scala 1698:40]
|
|
wire _T_175 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 1701:30]
|
|
wire _T_176 = _T_175 | io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1701:51]
|
|
wire _T_180 = wr_mepc_r & _T_15; // @[el2_dec_tlu_ctl.scala 1703:16]
|
|
wire _T_183 = ~wr_mepc_r; // @[el2_dec_tlu_ctl.scala 1704:6]
|
|
wire _T_185 = _T_183 & _T_15; // @[el2_dec_tlu_ctl.scala 1704:17]
|
|
wire [30:0] _T_187 = _T_176 ? pc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_188 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_189 = _T_180 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_190 = _T_185 ? io_mepc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_191 = _T_187 | _T_188; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_192 = _T_191 | _T_189; // @[Mux.scala 27:72]
|
|
reg [30:0] _T_194; // @[el2_dec_tlu_ctl.scala 1706:48]
|
|
wire _T_196 = io_dec_csr_wraddr_r == 12'h342; // @[el2_dec_tlu_ctl.scala 1713:71]
|
|
wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_196; // @[el2_dec_tlu_ctl.scala 1713:42]
|
|
wire _T_197 = io_exc_or_int_valid_r & io_take_nmi; // @[el2_dec_tlu_ctl.scala 1714:52]
|
|
wire mcause_sel_nmi_store = _T_197 & io_nmi_lsu_store_type; // @[el2_dec_tlu_ctl.scala 1714:66]
|
|
wire mcause_sel_nmi_load = _T_197 & io_nmi_lsu_load_type; // @[el2_dec_tlu_ctl.scala 1715:65]
|
|
wire _T_200 = |io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1716:83]
|
|
wire mcause_sel_nmi_ext = _T_197 & _T_200; // @[el2_dec_tlu_ctl.scala 1716:64]
|
|
wire _T_201 = &io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1722:52]
|
|
wire _T_204 = ~io_lsu_fir_error[0]; // @[el2_dec_tlu_ctl.scala 1722:81]
|
|
wire _T_205 = io_lsu_fir_error[1] & _T_204; // @[el2_dec_tlu_ctl.scala 1722:79]
|
|
wire [31:0] _T_210 = {30'h3c000400,_T_201,_T_205}; // @[Cat.scala 29:58]
|
|
wire _T_211 = ~io_take_nmi; // @[el2_dec_tlu_ctl.scala 1728:30]
|
|
wire _T_212 = io_exc_or_int_valid_r & _T_211; // @[el2_dec_tlu_ctl.scala 1728:28]
|
|
wire [31:0] _T_215 = {io_interrupt_valid_r,26'h0,io_exc_cause_r}; // @[Cat.scala 29:58]
|
|
wire _T_217 = wr_mcause_r & _T_15; // @[el2_dec_tlu_ctl.scala 1729:18]
|
|
wire _T_219 = ~wr_mcause_r; // @[el2_dec_tlu_ctl.scala 1730:6]
|
|
wire _T_221 = _T_219 & _T_15; // @[el2_dec_tlu_ctl.scala 1730:19]
|
|
wire [31:0] _T_223 = mcause_sel_nmi_store ? 32'hf0000000 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_224 = mcause_sel_nmi_load ? 32'hf0000001 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_225 = mcause_sel_nmi_ext ? _T_210 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_226 = _T_212 ? _T_215 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_227 = _T_217 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] mcause; // @[el2_dec_tlu_ctl.scala 1732:47]
|
|
wire [31:0] _T_228 = _T_221 ? mcause : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_229 = _T_223 | _T_224; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_230 = _T_229 | _T_225; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_231 = _T_230 | _T_226; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_232 = _T_231 | _T_227; // @[Mux.scala 27:72]
|
|
wire _T_236 = io_dec_csr_wraddr_r == 12'h7ff; // @[el2_dec_tlu_ctl.scala 1739:72]
|
|
wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_236; // @[el2_dec_tlu_ctl.scala 1739:43]
|
|
wire _T_237 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[el2_dec_tlu_ctl.scala 1741:57]
|
|
wire [3:0] _T_238 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58]
|
|
wire [3:0] ifu_mscause = _T_237 ? 4'h9 : _T_238; // @[el2_dec_tlu_ctl.scala 1741:25]
|
|
wire [3:0] _T_243 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_245 = io_ebreak_r ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_246 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _GEN_13 = {{3'd0}, io_i0_trigger_hit_r}; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_247 = _T_243 | _GEN_13; // @[Mux.scala 27:72]
|
|
wire [3:0] _GEN_14 = {{2'd0}, _T_245}; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_248 = _T_247 | _GEN_14; // @[Mux.scala 27:72]
|
|
wire [3:0] mscause_type = _T_248 | _T_246; // @[Mux.scala 27:72]
|
|
wire _T_252 = wr_mscause_r & _T_15; // @[el2_dec_tlu_ctl.scala 1752:19]
|
|
wire _T_255 = ~wr_mscause_r; // @[el2_dec_tlu_ctl.scala 1753:6]
|
|
wire _T_257 = _T_255 & _T_15; // @[el2_dec_tlu_ctl.scala 1753:20]
|
|
wire [3:0] _T_259 = io_exc_or_int_valid_r ? mscause_type : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_260 = _T_252 ? io_dec_csr_wrdata_r[3:0] : 4'h0; // @[Mux.scala 27:72]
|
|
reg [3:0] mscause; // @[el2_dec_tlu_ctl.scala 1755:48]
|
|
wire [3:0] _T_261 = _T_257 ? mscause : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_262 = _T_259 | _T_260; // @[Mux.scala 27:72]
|
|
wire _T_266 = io_dec_csr_wraddr_r == 12'h343; // @[el2_dec_tlu_ctl.scala 1762:70]
|
|
wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_266; // @[el2_dec_tlu_ctl.scala 1762:41]
|
|
wire _T_267 = ~io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 1763:84]
|
|
wire _T_268 = io_inst_acc_r & _T_267; // @[el2_dec_tlu_ctl.scala 1763:82]
|
|
wire _T_269 = io_ebreak_r | _T_268; // @[el2_dec_tlu_ctl.scala 1763:65]
|
|
wire _T_270 = _T_269 | io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1763:107]
|
|
wire _T_271 = io_exc_or_int_valid_r & _T_270; // @[el2_dec_tlu_ctl.scala 1763:50]
|
|
wire mtval_capture_pc_r = _T_271 & _T_211; // @[el2_dec_tlu_ctl.scala 1763:139]
|
|
wire _T_273 = io_inst_acc_r & io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 1764:73]
|
|
wire _T_274 = io_exc_or_int_valid_r & _T_273; // @[el2_dec_tlu_ctl.scala 1764:56]
|
|
wire mtval_capture_pc_plus2_r = _T_274 & _T_211; // @[el2_dec_tlu_ctl.scala 1764:97]
|
|
wire _T_276 = io_exc_or_int_valid_r & io_illegal_r; // @[el2_dec_tlu_ctl.scala 1765:52]
|
|
wire mtval_capture_inst_r = _T_276 & _T_211; // @[el2_dec_tlu_ctl.scala 1765:67]
|
|
wire _T_278 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 1766:51]
|
|
wire mtval_capture_lsu_r = _T_278 & _T_211; // @[el2_dec_tlu_ctl.scala 1766:72]
|
|
wire _T_280 = ~mtval_capture_pc_r; // @[el2_dec_tlu_ctl.scala 1767:47]
|
|
wire _T_281 = io_exc_or_int_valid_r & _T_280; // @[el2_dec_tlu_ctl.scala 1767:45]
|
|
wire _T_282 = ~mtval_capture_inst_r; // @[el2_dec_tlu_ctl.scala 1767:69]
|
|
wire _T_283 = _T_281 & _T_282; // @[el2_dec_tlu_ctl.scala 1767:67]
|
|
wire _T_284 = ~mtval_capture_lsu_r; // @[el2_dec_tlu_ctl.scala 1767:93]
|
|
wire _T_285 = _T_283 & _T_284; // @[el2_dec_tlu_ctl.scala 1767:91]
|
|
wire _T_286 = ~io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1767:116]
|
|
wire mtval_clear_r = _T_285 & _T_286; // @[el2_dec_tlu_ctl.scala 1767:114]
|
|
wire [31:0] _T_288 = {pc_r,1'h0}; // @[Cat.scala 29:58]
|
|
wire [30:0] _T_291 = pc_r + 31'h1; // @[el2_dec_tlu_ctl.scala 1772:84]
|
|
wire [31:0] _T_292 = {_T_291,1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_295 = ~io_interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 1775:19]
|
|
wire _T_296 = wr_mtval_r & _T_295; // @[el2_dec_tlu_ctl.scala 1775:17]
|
|
wire _T_299 = ~wr_mtval_r; // @[el2_dec_tlu_ctl.scala 1776:21]
|
|
wire _T_300 = _T_211 & _T_299; // @[el2_dec_tlu_ctl.scala 1776:19]
|
|
wire _T_302 = _T_300 & _T_280; // @[el2_dec_tlu_ctl.scala 1776:33]
|
|
wire _T_304 = _T_302 & _T_282; // @[el2_dec_tlu_ctl.scala 1776:55]
|
|
wire _T_305 = ~mtval_clear_r; // @[el2_dec_tlu_ctl.scala 1776:81]
|
|
wire _T_306 = _T_304 & _T_305; // @[el2_dec_tlu_ctl.scala 1776:79]
|
|
wire _T_308 = _T_306 & _T_284; // @[el2_dec_tlu_ctl.scala 1776:96]
|
|
wire [31:0] _T_310 = mtval_capture_pc_r ? _T_288 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_311 = mtval_capture_pc_plus2_r ? _T_292 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_312 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_313 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_314 = _T_296 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] mtval; // @[el2_dec_tlu_ctl.scala 1778:47]
|
|
wire [31:0] _T_315 = _T_308 ? mtval : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_316 = _T_310 | _T_311; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_317 = _T_316 | _T_312; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_318 = _T_317 | _T_313; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_319 = _T_318 | _T_314; // @[Mux.scala 27:72]
|
|
wire _T_323 = io_dec_csr_wraddr_r == 12'h7f8; // @[el2_dec_tlu_ctl.scala 1793:69]
|
|
reg [8:0] mcgc; // @[el2_lib.scala 514:16]
|
|
wire _T_335 = io_dec_csr_wraddr_r == 12'h7f9; // @[el2_dec_tlu_ctl.scala 1823:69]
|
|
reg [14:0] mfdc_int; // @[el2_lib.scala 514:16]
|
|
wire [2:0] _T_339 = ~io_dec_csr_wrdata_r[18:16]; // @[el2_dec_tlu_ctl.scala 1832:20]
|
|
wire _T_342 = ~io_dec_csr_wrdata_r[6]; // @[el2_dec_tlu_ctl.scala 1832:75]
|
|
wire [6:0] _T_344 = {_T_342,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_345 = {_T_339,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58]
|
|
wire [2:0] _T_348 = ~mfdc_int[14:12]; // @[el2_dec_tlu_ctl.scala 1833:20]
|
|
wire _T_351 = ~mfdc_int[6]; // @[el2_dec_tlu_ctl.scala 1833:63]
|
|
wire [18:0] mfdc = {_T_348,4'h0,mfdc_int[11:7],_T_351,mfdc_int[5:0]}; // @[Cat.scala 29:58]
|
|
wire _T_365 = io_dec_csr_wraddr_r == 12'h7c2; // @[el2_dec_tlu_ctl.scala 1856:78]
|
|
wire _T_366 = io_dec_csr_wen_r_mod & _T_365; // @[el2_dec_tlu_ctl.scala 1856:49]
|
|
wire _T_368 = _T_366 & _T_295; // @[el2_dec_tlu_ctl.scala 1856:88]
|
|
wire _T_369 = ~io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 1856:114]
|
|
wire _T_372 = io_dec_csr_wraddr_r == 12'h7c0; // @[el2_dec_tlu_ctl.scala 1863:69]
|
|
wire _T_376 = ~io_dec_csr_wrdata_r[31]; // @[el2_dec_tlu_ctl.scala 1866:72]
|
|
wire _T_377 = io_dec_csr_wrdata_r[30] & _T_376; // @[el2_dec_tlu_ctl.scala 1866:70]
|
|
wire _T_381 = ~io_dec_csr_wrdata_r[29]; // @[el2_dec_tlu_ctl.scala 1867:56]
|
|
wire _T_382 = io_dec_csr_wrdata_r[28] & _T_381; // @[el2_dec_tlu_ctl.scala 1867:54]
|
|
wire _T_386 = ~io_dec_csr_wrdata_r[27]; // @[el2_dec_tlu_ctl.scala 1868:56]
|
|
wire _T_387 = io_dec_csr_wrdata_r[26] & _T_386; // @[el2_dec_tlu_ctl.scala 1868:54]
|
|
wire _T_391 = ~io_dec_csr_wrdata_r[25]; // @[el2_dec_tlu_ctl.scala 1869:56]
|
|
wire _T_392 = io_dec_csr_wrdata_r[24] & _T_391; // @[el2_dec_tlu_ctl.scala 1869:54]
|
|
wire _T_396 = ~io_dec_csr_wrdata_r[23]; // @[el2_dec_tlu_ctl.scala 1870:56]
|
|
wire _T_397 = io_dec_csr_wrdata_r[22] & _T_396; // @[el2_dec_tlu_ctl.scala 1870:54]
|
|
wire _T_401 = ~io_dec_csr_wrdata_r[21]; // @[el2_dec_tlu_ctl.scala 1871:56]
|
|
wire _T_402 = io_dec_csr_wrdata_r[20] & _T_401; // @[el2_dec_tlu_ctl.scala 1871:54]
|
|
wire _T_406 = ~io_dec_csr_wrdata_r[19]; // @[el2_dec_tlu_ctl.scala 1872:56]
|
|
wire _T_407 = io_dec_csr_wrdata_r[18] & _T_406; // @[el2_dec_tlu_ctl.scala 1872:54]
|
|
wire _T_411 = ~io_dec_csr_wrdata_r[17]; // @[el2_dec_tlu_ctl.scala 1873:56]
|
|
wire _T_412 = io_dec_csr_wrdata_r[16] & _T_411; // @[el2_dec_tlu_ctl.scala 1873:54]
|
|
wire _T_416 = ~io_dec_csr_wrdata_r[15]; // @[el2_dec_tlu_ctl.scala 1874:56]
|
|
wire _T_417 = io_dec_csr_wrdata_r[14] & _T_416; // @[el2_dec_tlu_ctl.scala 1874:54]
|
|
wire _T_421 = ~io_dec_csr_wrdata_r[13]; // @[el2_dec_tlu_ctl.scala 1875:56]
|
|
wire _T_422 = io_dec_csr_wrdata_r[12] & _T_421; // @[el2_dec_tlu_ctl.scala 1875:54]
|
|
wire _T_426 = ~io_dec_csr_wrdata_r[11]; // @[el2_dec_tlu_ctl.scala 1876:56]
|
|
wire _T_427 = io_dec_csr_wrdata_r[10] & _T_426; // @[el2_dec_tlu_ctl.scala 1876:54]
|
|
wire _T_431 = ~io_dec_csr_wrdata_r[9]; // @[el2_dec_tlu_ctl.scala 1877:56]
|
|
wire _T_432 = io_dec_csr_wrdata_r[8] & _T_431; // @[el2_dec_tlu_ctl.scala 1877:53]
|
|
wire _T_436 = ~io_dec_csr_wrdata_r[7]; // @[el2_dec_tlu_ctl.scala 1878:56]
|
|
wire _T_437 = io_dec_csr_wrdata_r[6] & _T_436; // @[el2_dec_tlu_ctl.scala 1878:53]
|
|
wire _T_441 = ~io_dec_csr_wrdata_r[5]; // @[el2_dec_tlu_ctl.scala 1879:56]
|
|
wire _T_442 = io_dec_csr_wrdata_r[4] & _T_441; // @[el2_dec_tlu_ctl.scala 1879:53]
|
|
wire _T_446 = ~io_dec_csr_wrdata_r[3]; // @[el2_dec_tlu_ctl.scala 1880:56]
|
|
wire _T_447 = io_dec_csr_wrdata_r[2] & _T_446; // @[el2_dec_tlu_ctl.scala 1880:53]
|
|
wire _T_452 = io_dec_csr_wrdata_r[0] & _T_507; // @[el2_dec_tlu_ctl.scala 1881:53]
|
|
wire [7:0] _T_459 = {io_dec_csr_wrdata_r[7],_T_437,io_dec_csr_wrdata_r[5],_T_442,io_dec_csr_wrdata_r[3],_T_447,io_dec_csr_wrdata_r[1],_T_452}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_467 = {io_dec_csr_wrdata_r[15],_T_417,io_dec_csr_wrdata_r[13],_T_422,io_dec_csr_wrdata_r[11],_T_427,io_dec_csr_wrdata_r[9],_T_432,_T_459}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_474 = {io_dec_csr_wrdata_r[23],_T_397,io_dec_csr_wrdata_r[21],_T_402,io_dec_csr_wrdata_r[19],_T_407,io_dec_csr_wrdata_r[17],_T_412}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_482 = {io_dec_csr_wrdata_r[31],_T_377,io_dec_csr_wrdata_r[29],_T_382,io_dec_csr_wrdata_r[27],_T_387,io_dec_csr_wrdata_r[25],_T_392,_T_474}; // @[Cat.scala 29:58]
|
|
reg [31:0] mrac; // @[el2_lib.scala 514:16]
|
|
wire _T_485 = io_dec_csr_wraddr_r == 12'hbc0; // @[el2_dec_tlu_ctl.scala 1894:70]
|
|
wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_485; // @[el2_dec_tlu_ctl.scala 1894:41]
|
|
wire _T_486 = ~wr_mdeau_r; // @[el2_dec_tlu_ctl.scala 1904:60]
|
|
wire _T_487 = io_mdseac_locked_f & _T_486; // @[el2_dec_tlu_ctl.scala 1904:58]
|
|
wire _T_489 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 1906:50]
|
|
wire _T_490 = ~io_nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 1906:87]
|
|
wire _T_491 = _T_489 & _T_490; // @[el2_dec_tlu_ctl.scala 1906:85]
|
|
wire _T_492 = ~io_mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 1906:112]
|
|
wire mdseac_en = _T_491 & _T_492; // @[el2_dec_tlu_ctl.scala 1906:110]
|
|
reg [31:0] mdseac; // @[el2_lib.scala 514:16]
|
|
wire _T_498 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[el2_dec_tlu_ctl.scala 1921:31]
|
|
wire _T_499 = ~io_internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 1921:58]
|
|
wire _T_500 = _T_498 & _T_499; // @[el2_dec_tlu_ctl.scala 1921:56]
|
|
wire _T_501 = ~io_ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 1921:90]
|
|
wire _T_514 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[el2_dec_tlu_ctl.scala 1938:49]
|
|
wire [4:0] csr_sat = _T_514 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[el2_dec_tlu_ctl.scala 1938:20]
|
|
wire _T_517 = io_dec_csr_wraddr_r == 12'h7f0; // @[el2_dec_tlu_ctl.scala 1940:71]
|
|
wire wr_micect_r = io_dec_csr_wen_r_mod & _T_517; // @[el2_dec_tlu_ctl.scala 1940:42]
|
|
wire [26:0] _T_518 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58]
|
|
wire [31:0] _GEN_15 = {{5'd0}, _T_518}; // @[el2_dec_tlu_ctl.scala 1941:24]
|
|
wire [31:0] _T_520 = micect + _GEN_15; // @[el2_dec_tlu_ctl.scala 1941:24]
|
|
wire [31:0] _T_523 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58]
|
|
wire [26:0] micect_inc = _T_520[26:0]; // @[el2_dec_tlu_ctl.scala 1941:14]
|
|
wire [31:0] _T_525 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58]
|
|
wire _T_536 = io_dec_csr_wraddr_r == 12'h7f1; // @[el2_dec_tlu_ctl.scala 1955:77]
|
|
wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_536; // @[el2_dec_tlu_ctl.scala 1955:48]
|
|
wire _T_538 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 1956:71]
|
|
wire [26:0] _T_539 = {26'h0,_T_538}; // @[Cat.scala 29:58]
|
|
wire [26:0] miccmect_inc = miccmect[26:0] + _T_539; // @[el2_dec_tlu_ctl.scala 1956:34]
|
|
wire [31:0] _T_546 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58]
|
|
wire _T_547 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 1959:49]
|
|
wire _T_558 = io_dec_csr_wraddr_r == 12'h7f2; // @[el2_dec_tlu_ctl.scala 1969:77]
|
|
wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_558; // @[el2_dec_tlu_ctl.scala 1969:48]
|
|
wire [26:0] _T_560 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58]
|
|
wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_560; // @[el2_dec_tlu_ctl.scala 1970:34]
|
|
wire [31:0] _T_567 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58]
|
|
wire _T_578 = io_dec_csr_wraddr_r == 12'h7ce; // @[el2_dec_tlu_ctl.scala 1985:70]
|
|
wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_578; // @[el2_dec_tlu_ctl.scala 1985:41]
|
|
reg [5:0] mfdht; // @[el2_dec_tlu_ctl.scala 1989:44]
|
|
wire _T_583 = io_dec_csr_wraddr_r == 12'h7cf; // @[el2_dec_tlu_ctl.scala 1998:70]
|
|
wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_583; // @[el2_dec_tlu_ctl.scala 1998:41]
|
|
wire _T_586 = ~io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2001:30]
|
|
wire _T_587 = io_dbg_tlu_halted & _T_586; // @[el2_dec_tlu_ctl.scala 2001:28]
|
|
wire _T_589 = ~io_lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 2001:65]
|
|
wire _T_590 = ~io_ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 2001:85]
|
|
wire [1:0] _T_591 = {_T_589,_T_590}; // @[Cat.scala 29:58]
|
|
reg [1:0] mfdhs; // @[Reg.scala 27:20]
|
|
wire _T_593 = wr_mfdhs_r | io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 2003:72]
|
|
reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_598 = force_halt_ctr_f + 32'h1; // @[el2_dec_tlu_ctl.scala 2005:75]
|
|
wire [62:0] _T_605 = 63'hffffffff << mfdht[5:1]; // @[el2_dec_tlu_ctl.scala 2010:72]
|
|
wire [62:0] _GEN_16 = {{31'd0}, force_halt_ctr_f}; // @[el2_dec_tlu_ctl.scala 2010:49]
|
|
wire [62:0] _T_606 = _GEN_16 & _T_605; // @[el2_dec_tlu_ctl.scala 2010:49]
|
|
wire _T_607 = |_T_606; // @[el2_dec_tlu_ctl.scala 2010:88]
|
|
wire _T_610 = io_dec_csr_wraddr_r == 12'hbc8; // @[el2_dec_tlu_ctl.scala 2018:70]
|
|
reg [21:0] meivt; // @[el2_lib.scala 514:16]
|
|
wire _T_630 = io_dec_csr_wraddr_r == 12'hbca; // @[el2_dec_tlu_ctl.scala 2069:70]
|
|
wire _T_631 = io_dec_csr_wen_r_mod & _T_630; // @[el2_dec_tlu_ctl.scala 2069:41]
|
|
wire wr_meicpct_r = _T_631 | io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 2069:84]
|
|
reg [7:0] meihap; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_615 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58]
|
|
wire _T_617 = io_dec_csr_wraddr_r == 12'hbcc; // @[el2_dec_tlu_ctl.scala 2042:73]
|
|
wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_617; // @[el2_dec_tlu_ctl.scala 2042:44]
|
|
reg [3:0] meicurpl; // @[el2_dec_tlu_ctl.scala 2045:47]
|
|
wire _T_622 = io_dec_csr_wraddr_r == 12'hbcb; // @[el2_dec_tlu_ctl.scala 2057:74]
|
|
wire _T_623 = io_dec_csr_wen_r_mod & _T_622; // @[el2_dec_tlu_ctl.scala 2057:45]
|
|
wire wr_meicidpl_r = _T_623 | io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 2057:89]
|
|
reg [3:0] meicidpl; // @[el2_dec_tlu_ctl.scala 2062:45]
|
|
wire _T_634 = io_dec_csr_wraddr_r == 12'hbc9; // @[el2_dec_tlu_ctl.scala 2078:70]
|
|
wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_634; // @[el2_dec_tlu_ctl.scala 2078:41]
|
|
reg [3:0] meipt; // @[el2_dec_tlu_ctl.scala 2081:44]
|
|
wire _T_638 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 2109:90]
|
|
wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_638; // @[el2_dec_tlu_ctl.scala 2109:67]
|
|
wire _T_639 = ~io_ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 2112:35]
|
|
wire _T_640 = io_dcsr_single_step_done_f & _T_639; // @[el2_dec_tlu_ctl.scala 2112:33]
|
|
wire _T_641 = ~trigger_hit_for_dscr_cause_r_d1; // @[el2_dec_tlu_ctl.scala 2112:67]
|
|
wire _T_642 = _T_640 & _T_641; // @[el2_dec_tlu_ctl.scala 2112:65]
|
|
wire _T_643 = ~io_debug_halt_req; // @[el2_dec_tlu_ctl.scala 2112:102]
|
|
wire _T_644 = _T_642 & _T_643; // @[el2_dec_tlu_ctl.scala 2112:100]
|
|
wire _T_647 = io_debug_halt_req & _T_639; // @[el2_dec_tlu_ctl.scala 2113:24]
|
|
wire _T_649 = _T_647 & _T_641; // @[el2_dec_tlu_ctl.scala 2113:56]
|
|
wire _T_652 = io_ebreak_to_debug_mode_r_d1 & _T_641; // @[el2_dec_tlu_ctl.scala 2114:35]
|
|
wire [2:0] _T_655 = _T_644 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_656 = _T_649 ? 3'h3 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_657 = _T_652 ? 3'h1 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_658 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_659 = _T_655 | _T_656; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_660 = _T_659 | _T_657; // @[Mux.scala 27:72]
|
|
wire [2:0] dcsr_cause = _T_660 | _T_658; // @[Mux.scala 27:72]
|
|
wire _T_662 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 2117:47]
|
|
wire _T_664 = io_dec_csr_wraddr_r == 12'h7b0; // @[el2_dec_tlu_ctl.scala 2117:99]
|
|
wire wr_dcsr_r = _T_662 & _T_664; // @[el2_dec_tlu_ctl.scala 2117:70]
|
|
wire _T_666 = io_dcsr[8:6] == 3'h3; // @[el2_dec_tlu_ctl.scala 2123:76]
|
|
wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_666; // @[el2_dec_tlu_ctl.scala 2123:60]
|
|
wire _T_667 = ~io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 2124:60]
|
|
wire _T_668 = _T_667 | dcsr_cause_upgradeable; // @[el2_dec_tlu_ctl.scala 2124:79]
|
|
wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_668; // @[el2_dec_tlu_ctl.scala 2124:57]
|
|
wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[el2_dec_tlu_ctl.scala 2126:49]
|
|
wire [15:0] _T_674 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58]
|
|
wire _T_680 = nmi_in_debug_mode | io_dcsr[3]; // @[el2_dec_tlu_ctl.scala 2128:146]
|
|
wire [15:0] _T_689 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_680,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_694 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58]
|
|
wire _T_696 = enter_debug_halt_req_le | wr_dcsr_r; // @[el2_dec_tlu_ctl.scala 2130:55]
|
|
wire _T_697 = _T_696 | io_internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 2130:67]
|
|
reg [15:0] _T_700; // @[el2_lib.scala 514:16]
|
|
wire _T_703 = io_dec_csr_wraddr_r == 12'h7b1; // @[el2_dec_tlu_ctl.scala 2138:98]
|
|
wire wr_dpc_r = _T_662 & _T_703; // @[el2_dec_tlu_ctl.scala 2138:69]
|
|
wire _T_706 = ~io_request_debug_mode_done; // @[el2_dec_tlu_ctl.scala 2139:68]
|
|
wire dpc_capture_npc = _T_587 & _T_706; // @[el2_dec_tlu_ctl.scala 2139:66]
|
|
wire _T_707 = ~io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 2143:6]
|
|
wire _T_708 = ~dpc_capture_npc; // @[el2_dec_tlu_ctl.scala 2143:24]
|
|
wire _T_709 = _T_707 & _T_708; // @[el2_dec_tlu_ctl.scala 2143:22]
|
|
wire _T_710 = _T_709 & wr_dpc_r; // @[el2_dec_tlu_ctl.scala 2143:41]
|
|
wire _T_715 = _T_707 & dpc_capture_npc; // @[el2_dec_tlu_ctl.scala 2145:22]
|
|
wire [30:0] _T_717 = _T_710 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_718 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_719 = _T_715 ? io_npc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_720 = _T_717 | _T_718; // @[Mux.scala 27:72]
|
|
wire _T_722 = wr_dpc_r | io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 2147:37]
|
|
reg [30:0] _T_725; // @[el2_lib.scala 514:16]
|
|
wire [2:0] _T_729 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58]
|
|
wire _T_732 = io_dec_csr_wraddr_r == 12'h7c8; // @[el2_dec_tlu_ctl.scala 2162:103]
|
|
reg [16:0] dicawics; // @[el2_lib.scala 514:16]
|
|
wire _T_736 = io_dec_csr_wraddr_r == 12'h7c9; // @[el2_dec_tlu_ctl.scala 2180:101]
|
|
wire wr_dicad0_r = _T_662 & _T_736; // @[el2_dec_tlu_ctl.scala 2180:72]
|
|
reg [70:0] dicad0; // @[el2_lib.scala 514:16]
|
|
wire _T_742 = io_dec_csr_wraddr_r == 12'h7cc; // @[el2_dec_tlu_ctl.scala 2193:102]
|
|
wire wr_dicad0h_r = _T_662 & _T_742; // @[el2_dec_tlu_ctl.scala 2193:73]
|
|
reg [31:0] dicad0h; // @[el2_lib.scala 514:16]
|
|
wire _T_750 = io_dec_csr_wraddr_r == 12'h7ca; // @[el2_dec_tlu_ctl.scala 2205:103]
|
|
wire _T_751 = _T_662 & _T_750; // @[el2_dec_tlu_ctl.scala 2205:74]
|
|
wire _T_755 = _T_751 | io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 2209:81]
|
|
reg [31:0] _T_757; // @[Reg.scala 27:20]
|
|
wire [31:0] dicad1 = {25'h0,_T_757[6:0]}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_762 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58]
|
|
wire _T_764 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 2237:53]
|
|
wire _T_765 = _T_764 & io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 2237:76]
|
|
wire _T_766 = ~io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 2237:99]
|
|
wire _T_767 = _T_765 & _T_766; // @[el2_dec_tlu_ctl.scala 2237:97]
|
|
wire _T_769 = io_dec_csr_rdaddr_d == 12'h7cb; // @[el2_dec_tlu_ctl.scala 2237:150]
|
|
wire _T_772 = io_dec_csr_wraddr_r == 12'h7cb; // @[el2_dec_tlu_ctl.scala 2238:105]
|
|
reg icache_rd_valid_f; // @[el2_dec_tlu_ctl.scala 2240:59]
|
|
reg icache_wr_valid_f; // @[el2_dec_tlu_ctl.scala 2241:59]
|
|
wire _T_774 = io_dec_csr_wraddr_r == 12'h7a0; // @[el2_dec_tlu_ctl.scala 2252:70]
|
|
wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_774; // @[el2_dec_tlu_ctl.scala 2252:41]
|
|
reg [1:0] mtsel; // @[el2_dec_tlu_ctl.scala 2255:44]
|
|
wire tdata_load = io_dec_csr_wrdata_r[0] & _T_406; // @[el2_dec_tlu_ctl.scala 2290:43]
|
|
wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_406; // @[el2_dec_tlu_ctl.scala 2292:45]
|
|
wire _T_785 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2294:47]
|
|
wire tdata_action = _T_785 & io_dec_csr_wrdata_r[12]; // @[el2_dec_tlu_ctl.scala 2294:70]
|
|
wire [9:0] tdata_wrdata_r = {_T_785,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58]
|
|
wire _T_800 = io_dec_csr_wraddr_r == 12'h7a1; // @[el2_dec_tlu_ctl.scala 2300:100]
|
|
wire _T_801 = io_dec_csr_wen_r_mod & _T_800; // @[el2_dec_tlu_ctl.scala 2300:71]
|
|
wire _T_802 = mtsel == 2'h0; // @[el2_dec_tlu_ctl.scala 2300:122]
|
|
wire _T_803 = _T_801 & _T_802; // @[el2_dec_tlu_ctl.scala 2300:113]
|
|
wire _T_805 = ~io_mtdata1_t_0[9]; // @[el2_dec_tlu_ctl.scala 2300:139]
|
|
wire _T_806 = _T_805 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171]
|
|
wire wr_mtdata1_t_r_0 = _T_803 & _T_806; // @[el2_dec_tlu_ctl.scala 2300:136]
|
|
wire _T_814 = ~io_mtdata1_t_1[9]; // @[el2_dec_tlu_ctl.scala 2300:139]
|
|
wire _T_815 = _T_814 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171]
|
|
wire wr_mtdata1_t_r_1 = _T_803 & _T_815; // @[el2_dec_tlu_ctl.scala 2300:136]
|
|
wire _T_823 = ~io_mtdata1_t_2[9]; // @[el2_dec_tlu_ctl.scala 2300:139]
|
|
wire _T_824 = _T_823 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171]
|
|
wire wr_mtdata1_t_r_2 = _T_803 & _T_824; // @[el2_dec_tlu_ctl.scala 2300:136]
|
|
wire _T_832 = ~io_mtdata1_t_3[9]; // @[el2_dec_tlu_ctl.scala 2300:139]
|
|
wire _T_833 = _T_832 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171]
|
|
wire wr_mtdata1_t_r_3 = _T_803 & _T_833; // @[el2_dec_tlu_ctl.scala 2300:136]
|
|
wire _T_839 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[el2_dec_tlu_ctl.scala 2301:140]
|
|
wire [9:0] _T_842 = {io_mtdata1_t_0[9],_T_839,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_848 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[el2_dec_tlu_ctl.scala 2301:140]
|
|
wire [9:0] _T_851 = {io_mtdata1_t_1[9],_T_848,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_857 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[el2_dec_tlu_ctl.scala 2301:140]
|
|
wire [9:0] _T_860 = {io_mtdata1_t_2[9],_T_857,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_866 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[el2_dec_tlu_ctl.scala 2301:140]
|
|
wire [9:0] _T_869 = {io_mtdata1_t_3[9],_T_866,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58]
|
|
reg [9:0] _T_871; // @[el2_dec_tlu_ctl.scala 2303:76]
|
|
reg [9:0] _T_872; // @[el2_dec_tlu_ctl.scala 2303:76]
|
|
reg [9:0] _T_873; // @[el2_dec_tlu_ctl.scala 2303:76]
|
|
reg [9:0] _T_874; // @[el2_dec_tlu_ctl.scala 2303:76]
|
|
wire [31:0] _T_889 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58]
|
|
wire _T_890 = mtsel == 2'h1; // @[el2_dec_tlu_ctl.scala 2306:60]
|
|
wire [31:0] _T_904 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58]
|
|
wire _T_905 = mtsel == 2'h2; // @[el2_dec_tlu_ctl.scala 2306:60]
|
|
wire [31:0] _T_919 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58]
|
|
wire _T_920 = mtsel == 2'h3; // @[el2_dec_tlu_ctl.scala 2306:60]
|
|
wire [31:0] _T_934 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_935 = _T_802 ? _T_889 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_936 = _T_890 ? _T_904 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_937 = _T_905 ? _T_919 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_938 = _T_920 ? _T_934 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_939 = _T_935 | _T_936; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_940 = _T_939 | _T_937; // @[Mux.scala 27:72]
|
|
wire [31:0] mtdata1_tsel_out = _T_940 | _T_938; // @[Mux.scala 27:72]
|
|
wire _T_967 = io_dec_csr_wraddr_r == 12'h7a2; // @[el2_dec_tlu_ctl.scala 2320:99]
|
|
wire _T_968 = io_dec_csr_wen_r_mod & _T_967; // @[el2_dec_tlu_ctl.scala 2320:70]
|
|
wire _T_970 = _T_968 & _T_802; // @[el2_dec_tlu_ctl.scala 2320:112]
|
|
wire _T_979 = _T_968 & _T_890; // @[el2_dec_tlu_ctl.scala 2320:112]
|
|
wire _T_988 = _T_968 & _T_905; // @[el2_dec_tlu_ctl.scala 2320:112]
|
|
wire _T_997 = _T_968 & _T_920; // @[el2_dec_tlu_ctl.scala 2320:112]
|
|
reg [31:0] mtdata2_t_0; // @[el2_lib.scala 514:16]
|
|
reg [31:0] mtdata2_t_1; // @[el2_lib.scala 514:16]
|
|
reg [31:0] mtdata2_t_2; // @[el2_lib.scala 514:16]
|
|
reg [31:0] mtdata2_t_3; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_1014 = _T_802 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1015 = _T_890 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1016 = _T_905 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1017 = _T_920 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1018 = _T_1014 | _T_1015; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1019 = _T_1018 | _T_1016; // @[Mux.scala 27:72]
|
|
wire [31:0] mtdata2_tsel_out = _T_1019 | _T_1017; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1022 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1022; // @[el2_dec_tlu_ctl.scala 2345:60]
|
|
wire _T_1024 = ~mcountinhibit[3]; // @[el2_dec_tlu_ctl.scala 2351:25]
|
|
reg [9:0] mhpme3; // @[Reg.scala 27:20]
|
|
wire _T_1025 = mhpme3 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21]
|
|
wire _T_1027 = mhpme3 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21]
|
|
wire _T_1029 = mhpme3 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21]
|
|
wire _T_1031 = mhpme3 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21]
|
|
wire _T_1033 = ~io_illegal_r; // @[el2_dec_tlu_ctl.scala 2355:83]
|
|
wire _T_1034 = io_tlu_i0_commit_cmt & _T_1033; // @[el2_dec_tlu_ctl.scala 2355:81]
|
|
wire _T_1035 = mhpme3 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21]
|
|
wire _T_1037 = ~io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 2356:83]
|
|
wire _T_1038 = io_tlu_i0_commit_cmt & _T_1037; // @[el2_dec_tlu_ctl.scala 2356:81]
|
|
wire _T_1040 = _T_1038 & _T_1033; // @[el2_dec_tlu_ctl.scala 2356:102]
|
|
wire _T_1041 = mhpme3 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21]
|
|
wire _T_1043 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 2357:81]
|
|
wire _T_1045 = _T_1043 & _T_1033; // @[el2_dec_tlu_ctl.scala 2357:102]
|
|
wire _T_1046 = mhpme3 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21]
|
|
wire _T_1048 = mhpme3 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21]
|
|
wire _T_1050 = mhpme3 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21]
|
|
wire _T_1052 = mhpme3 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21]
|
|
wire _T_1054 = pmu_i0_itype_qual == 4'h1; // @[el2_dec_tlu_ctl.scala 2361:78]
|
|
wire _T_1055 = mhpme3 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21]
|
|
wire _T_1057 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2362:92]
|
|
wire _T_1058 = mhpme3 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21]
|
|
wire _T_1060 = pmu_i0_itype_qual == 4'h2; // @[el2_dec_tlu_ctl.scala 2363:78]
|
|
wire _T_1061 = mhpme3 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21]
|
|
wire _T_1063 = pmu_i0_itype_qual == 4'h3; // @[el2_dec_tlu_ctl.scala 2364:78]
|
|
wire _T_1064 = mhpme3 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21]
|
|
wire _T_1067 = mhpme3 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21]
|
|
wire _T_1068 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1067; // @[el2_dec_tlu_ctl.scala 2366:7]
|
|
wire _T_1070 = _T_1060 & _T_1068; // @[el2_dec_tlu_ctl.scala 2365:89]
|
|
wire _T_1072 = _T_1070 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45]
|
|
wire _T_1074 = _T_1072 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77]
|
|
wire _T_1075 = mhpme3 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21]
|
|
wire _T_1077 = pmu_i0_itype_qual == 4'h4; // @[el2_dec_tlu_ctl.scala 2368:76]
|
|
wire _T_1078 = mhpme3 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21]
|
|
wire _T_1080 = pmu_i0_itype_qual == 4'h5; // @[el2_dec_tlu_ctl.scala 2369:76]
|
|
wire _T_1081 = mhpme3 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21]
|
|
wire _T_1083 = pmu_i0_itype_qual == 4'h6; // @[el2_dec_tlu_ctl.scala 2370:76]
|
|
wire _T_1084 = mhpme3 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21]
|
|
wire _T_1086 = pmu_i0_itype_qual == 4'h7; // @[el2_dec_tlu_ctl.scala 2371:76]
|
|
wire _T_1087 = mhpme3 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21]
|
|
wire _T_1089 = pmu_i0_itype_qual == 4'h8; // @[el2_dec_tlu_ctl.scala 2372:76]
|
|
wire _T_1090 = mhpme3 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21]
|
|
wire _T_1092 = pmu_i0_itype_qual == 4'h9; // @[el2_dec_tlu_ctl.scala 2373:76]
|
|
wire _T_1093 = mhpme3 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21]
|
|
wire _T_1095 = pmu_i0_itype_qual == 4'ha; // @[el2_dec_tlu_ctl.scala 2374:76]
|
|
wire _T_1096 = mhpme3 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21]
|
|
wire _T_1098 = pmu_i0_itype_qual == 4'hb; // @[el2_dec_tlu_ctl.scala 2375:76]
|
|
wire _T_1099 = mhpme3 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21]
|
|
wire _T_1101 = pmu_i0_itype_qual == 4'hc; // @[el2_dec_tlu_ctl.scala 2376:76]
|
|
wire _T_1102 = mhpme3 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21]
|
|
wire _T_1104 = pmu_i0_itype_qual == 4'hd; // @[el2_dec_tlu_ctl.scala 2377:76]
|
|
wire _T_1105 = pmu_i0_itype_qual == 4'he; // @[el2_dec_tlu_ctl.scala 2377:109]
|
|
wire _T_1106 = _T_1104 | _T_1105; // @[el2_dec_tlu_ctl.scala 2377:88]
|
|
wire _T_1107 = mhpme3 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21]
|
|
wire _T_1109 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2378:82]
|
|
wire _T_1110 = mhpme3 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21]
|
|
wire _T_1112 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2379:84]
|
|
wire _T_1113 = mhpme3 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21]
|
|
wire _T_1115 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2380:97]
|
|
wire _T_1116 = mhpme3 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21]
|
|
wire _T_1120 = mhpme3 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21]
|
|
wire _T_1122 = mhpme3 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21]
|
|
wire _T_1124 = mhpme3 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21]
|
|
wire _T_1126 = mhpme3 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21]
|
|
wire _T_1128 = mhpme3 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21]
|
|
wire _T_1130 = mhpme3 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21]
|
|
wire _T_1132 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 2388:85]
|
|
wire _T_1133 = _T_1132 | io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 2388:107]
|
|
wire _T_1134 = mhpme3 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21]
|
|
wire _T_1136 = io_take_timer_int | io_take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 2389:79]
|
|
wire _T_1137 = _T_1136 | io_take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 2389:104]
|
|
wire _T_1138 = mhpme3 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21]
|
|
wire _T_1140 = mhpme3 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21]
|
|
wire _T_1142 = mhpme3 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21]
|
|
wire _T_1144 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[el2_dec_tlu_ctl.scala 2392:84]
|
|
wire _T_1145 = _T_1144 & io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 2392:116]
|
|
wire _T_1146 = mhpme3 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21]
|
|
wire _T_1148 = mhpme3 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21]
|
|
wire _T_1150 = mhpme3 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21]
|
|
wire _T_1152 = mhpme3 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21]
|
|
wire _T_1154 = mhpme3 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21]
|
|
wire _T_1156 = mhpme3 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21]
|
|
wire _T_1158 = mhpme3 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21]
|
|
wire _T_1160 = mhpme3 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21]
|
|
wire _T_1164 = ~io_mstatus[0]; // @[el2_dec_tlu_ctl.scala 2400:60]
|
|
wire _T_1165 = mhpme3 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21]
|
|
wire [5:0] _T_1172 = io_mip & mie; // @[el2_dec_tlu_ctl.scala 2401:100]
|
|
wire [5:0] _GEN_17 = {{5'd0}, _T_1164}; // @[el2_dec_tlu_ctl.scala 2401:85]
|
|
wire [5:0] _T_1173 = _GEN_17 & _T_1172; // @[el2_dec_tlu_ctl.scala 2401:85]
|
|
wire _T_1174 = mhpme3 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21]
|
|
wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[el2_dec_tlu_ctl.scala 2402:78]
|
|
wire _T_1177 = mhpme3 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21]
|
|
wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 2403:81]
|
|
wire _T_1180 = mhpme3 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21]
|
|
wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 2404:81]
|
|
wire _T_1183 = mhpme3 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21]
|
|
wire _T_1185 = mhpme3 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21]
|
|
wire _T_1187 = mhpme3 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21]
|
|
wire _T_1189 = mhpme3 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21]
|
|
wire _T_1191 = mhpme3 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21]
|
|
wire _T_1194 = _T_1027 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
|
|
wire _T_1195 = _T_1029 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
|
|
wire _T_1196 = _T_1031 & _T_1034; // @[Mux.scala 27:72]
|
|
wire _T_1197 = _T_1035 & _T_1040; // @[Mux.scala 27:72]
|
|
wire _T_1198 = _T_1041 & _T_1045; // @[Mux.scala 27:72]
|
|
wire _T_1199 = _T_1046 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
|
|
wire _T_1200 = _T_1048 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
|
|
wire _T_1201 = _T_1050 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
|
|
wire _T_1202 = _T_1052 & _T_1054; // @[Mux.scala 27:72]
|
|
wire _T_1203 = _T_1055 & _T_1057; // @[Mux.scala 27:72]
|
|
wire _T_1204 = _T_1058 & _T_1060; // @[Mux.scala 27:72]
|
|
wire _T_1205 = _T_1061 & _T_1063; // @[Mux.scala 27:72]
|
|
wire _T_1206 = _T_1064 & _T_1074; // @[Mux.scala 27:72]
|
|
wire _T_1207 = _T_1075 & _T_1077; // @[Mux.scala 27:72]
|
|
wire _T_1208 = _T_1078 & _T_1080; // @[Mux.scala 27:72]
|
|
wire _T_1209 = _T_1081 & _T_1083; // @[Mux.scala 27:72]
|
|
wire _T_1210 = _T_1084 & _T_1086; // @[Mux.scala 27:72]
|
|
wire _T_1211 = _T_1087 & _T_1089; // @[Mux.scala 27:72]
|
|
wire _T_1212 = _T_1090 & _T_1092; // @[Mux.scala 27:72]
|
|
wire _T_1213 = _T_1093 & _T_1095; // @[Mux.scala 27:72]
|
|
wire _T_1214 = _T_1096 & _T_1098; // @[Mux.scala 27:72]
|
|
wire _T_1215 = _T_1099 & _T_1101; // @[Mux.scala 27:72]
|
|
wire _T_1216 = _T_1102 & _T_1106; // @[Mux.scala 27:72]
|
|
wire _T_1217 = _T_1107 & _T_1109; // @[Mux.scala 27:72]
|
|
wire _T_1218 = _T_1110 & _T_1112; // @[Mux.scala 27:72]
|
|
wire _T_1219 = _T_1113 & _T_1115; // @[Mux.scala 27:72]
|
|
wire _T_1220 = _T_1116 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
|
|
wire _T_1222 = _T_1120 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
|
|
wire _T_1223 = _T_1122 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
|
|
wire _T_1224 = _T_1124 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1225 = _T_1126 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1226 = _T_1128 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1227 = _T_1130 & _T_1133; // @[Mux.scala 27:72]
|
|
wire _T_1228 = _T_1134 & _T_1137; // @[Mux.scala 27:72]
|
|
wire _T_1229 = _T_1138 & io_take_ext_int; // @[Mux.scala 27:72]
|
|
wire _T_1230 = _T_1140 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
|
|
wire _T_1231 = _T_1142 & _T_1145; // @[Mux.scala 27:72]
|
|
wire _T_1232 = _T_1146 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_1233 = _T_1148 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_1234 = _T_1150 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
|
|
wire _T_1235 = _T_1152 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_1236 = _T_1154 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_1237 = _T_1156 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_1238 = _T_1158 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_1239 = _T_1160 & _T_1164; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1240 = _T_1165 ? _T_1173 : 6'h0; // @[Mux.scala 27:72]
|
|
wire _T_1241 = _T_1174 & _T_1176; // @[Mux.scala 27:72]
|
|
wire _T_1242 = _T_1177 & _T_1179; // @[Mux.scala 27:72]
|
|
wire _T_1243 = _T_1180 & _T_1182; // @[Mux.scala 27:72]
|
|
wire _T_1244 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
|
|
wire _T_1245 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
|
|
wire _T_1246 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
|
|
wire _T_1247 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
|
|
wire _T_1248 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
|
|
wire _T_1249 = _T_1025 | _T_1194; // @[Mux.scala 27:72]
|
|
wire _T_1250 = _T_1249 | _T_1195; // @[Mux.scala 27:72]
|
|
wire _T_1251 = _T_1250 | _T_1196; // @[Mux.scala 27:72]
|
|
wire _T_1252 = _T_1251 | _T_1197; // @[Mux.scala 27:72]
|
|
wire _T_1253 = _T_1252 | _T_1198; // @[Mux.scala 27:72]
|
|
wire _T_1254 = _T_1253 | _T_1199; // @[Mux.scala 27:72]
|
|
wire _T_1255 = _T_1254 | _T_1200; // @[Mux.scala 27:72]
|
|
wire _T_1256 = _T_1255 | _T_1201; // @[Mux.scala 27:72]
|
|
wire _T_1257 = _T_1256 | _T_1202; // @[Mux.scala 27:72]
|
|
wire _T_1258 = _T_1257 | _T_1203; // @[Mux.scala 27:72]
|
|
wire _T_1259 = _T_1258 | _T_1204; // @[Mux.scala 27:72]
|
|
wire _T_1260 = _T_1259 | _T_1205; // @[Mux.scala 27:72]
|
|
wire _T_1261 = _T_1260 | _T_1206; // @[Mux.scala 27:72]
|
|
wire _T_1262 = _T_1261 | _T_1207; // @[Mux.scala 27:72]
|
|
wire _T_1263 = _T_1262 | _T_1208; // @[Mux.scala 27:72]
|
|
wire _T_1264 = _T_1263 | _T_1209; // @[Mux.scala 27:72]
|
|
wire _T_1265 = _T_1264 | _T_1210; // @[Mux.scala 27:72]
|
|
wire _T_1266 = _T_1265 | _T_1211; // @[Mux.scala 27:72]
|
|
wire _T_1267 = _T_1266 | _T_1212; // @[Mux.scala 27:72]
|
|
wire _T_1268 = _T_1267 | _T_1213; // @[Mux.scala 27:72]
|
|
wire _T_1269 = _T_1268 | _T_1214; // @[Mux.scala 27:72]
|
|
wire _T_1270 = _T_1269 | _T_1215; // @[Mux.scala 27:72]
|
|
wire _T_1271 = _T_1270 | _T_1216; // @[Mux.scala 27:72]
|
|
wire _T_1272 = _T_1271 | _T_1217; // @[Mux.scala 27:72]
|
|
wire _T_1273 = _T_1272 | _T_1218; // @[Mux.scala 27:72]
|
|
wire _T_1274 = _T_1273 | _T_1219; // @[Mux.scala 27:72]
|
|
wire _T_1275 = _T_1274 | _T_1220; // @[Mux.scala 27:72]
|
|
wire _T_1276 = _T_1275 | _T_1201; // @[Mux.scala 27:72]
|
|
wire _T_1277 = _T_1276 | _T_1222; // @[Mux.scala 27:72]
|
|
wire _T_1278 = _T_1277 | _T_1223; // @[Mux.scala 27:72]
|
|
wire _T_1279 = _T_1278 | _T_1224; // @[Mux.scala 27:72]
|
|
wire _T_1280 = _T_1279 | _T_1225; // @[Mux.scala 27:72]
|
|
wire _T_1281 = _T_1280 | _T_1226; // @[Mux.scala 27:72]
|
|
wire _T_1282 = _T_1281 | _T_1227; // @[Mux.scala 27:72]
|
|
wire _T_1283 = _T_1282 | _T_1228; // @[Mux.scala 27:72]
|
|
wire _T_1284 = _T_1283 | _T_1229; // @[Mux.scala 27:72]
|
|
wire _T_1285 = _T_1284 | _T_1230; // @[Mux.scala 27:72]
|
|
wire _T_1286 = _T_1285 | _T_1231; // @[Mux.scala 27:72]
|
|
wire _T_1287 = _T_1286 | _T_1232; // @[Mux.scala 27:72]
|
|
wire _T_1288 = _T_1287 | _T_1233; // @[Mux.scala 27:72]
|
|
wire _T_1289 = _T_1288 | _T_1234; // @[Mux.scala 27:72]
|
|
wire _T_1290 = _T_1289 | _T_1235; // @[Mux.scala 27:72]
|
|
wire _T_1291 = _T_1290 | _T_1236; // @[Mux.scala 27:72]
|
|
wire _T_1292 = _T_1291 | _T_1237; // @[Mux.scala 27:72]
|
|
wire _T_1293 = _T_1292 | _T_1238; // @[Mux.scala 27:72]
|
|
wire _T_1294 = _T_1293 | _T_1239; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_18 = {{5'd0}, _T_1294}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1295 = _GEN_18 | _T_1240; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_19 = {{5'd0}, _T_1241}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1296 = _T_1295 | _GEN_19; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_20 = {{5'd0}, _T_1242}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1297 = _T_1296 | _GEN_20; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_21 = {{5'd0}, _T_1243}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1298 = _T_1297 | _GEN_21; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_22 = {{5'd0}, _T_1244}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1299 = _T_1298 | _GEN_22; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_23 = {{5'd0}, _T_1245}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1300 = _T_1299 | _GEN_23; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_24 = {{5'd0}, _T_1246}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1301 = _T_1300 | _GEN_24; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_25 = {{5'd0}, _T_1247}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1302 = _T_1301 | _GEN_25; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_26 = {{5'd0}, _T_1248}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1303 = _T_1302 | _GEN_26; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_27 = {{5'd0}, _T_1024}; // @[el2_dec_tlu_ctl.scala 2351:45]
|
|
wire [5:0] _T_1305 = _GEN_27 & _T_1303; // @[el2_dec_tlu_ctl.scala 2351:45]
|
|
wire _T_1307 = ~mcountinhibit[4]; // @[el2_dec_tlu_ctl.scala 2351:25]
|
|
reg [9:0] mhpme4; // @[Reg.scala 27:20]
|
|
wire _T_1308 = mhpme4 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21]
|
|
wire _T_1310 = mhpme4 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21]
|
|
wire _T_1312 = mhpme4 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21]
|
|
wire _T_1314 = mhpme4 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21]
|
|
wire _T_1318 = mhpme4 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21]
|
|
wire _T_1324 = mhpme4 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21]
|
|
wire _T_1329 = mhpme4 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21]
|
|
wire _T_1331 = mhpme4 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21]
|
|
wire _T_1333 = mhpme4 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21]
|
|
wire _T_1335 = mhpme4 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21]
|
|
wire _T_1338 = mhpme4 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21]
|
|
wire _T_1341 = mhpme4 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21]
|
|
wire _T_1344 = mhpme4 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21]
|
|
wire _T_1347 = mhpme4 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21]
|
|
wire _T_1350 = mhpme4 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21]
|
|
wire _T_1351 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1350; // @[el2_dec_tlu_ctl.scala 2366:7]
|
|
wire _T_1353 = _T_1060 & _T_1351; // @[el2_dec_tlu_ctl.scala 2365:89]
|
|
wire _T_1355 = _T_1353 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45]
|
|
wire _T_1357 = _T_1355 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77]
|
|
wire _T_1358 = mhpme4 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21]
|
|
wire _T_1361 = mhpme4 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21]
|
|
wire _T_1364 = mhpme4 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21]
|
|
wire _T_1367 = mhpme4 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21]
|
|
wire _T_1370 = mhpme4 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21]
|
|
wire _T_1373 = mhpme4 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21]
|
|
wire _T_1376 = mhpme4 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21]
|
|
wire _T_1379 = mhpme4 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21]
|
|
wire _T_1382 = mhpme4 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21]
|
|
wire _T_1385 = mhpme4 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21]
|
|
wire _T_1390 = mhpme4 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21]
|
|
wire _T_1393 = mhpme4 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21]
|
|
wire _T_1396 = mhpme4 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21]
|
|
wire _T_1399 = mhpme4 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21]
|
|
wire _T_1403 = mhpme4 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21]
|
|
wire _T_1405 = mhpme4 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21]
|
|
wire _T_1407 = mhpme4 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21]
|
|
wire _T_1409 = mhpme4 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21]
|
|
wire _T_1411 = mhpme4 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21]
|
|
wire _T_1413 = mhpme4 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21]
|
|
wire _T_1417 = mhpme4 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21]
|
|
wire _T_1421 = mhpme4 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21]
|
|
wire _T_1423 = mhpme4 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21]
|
|
wire _T_1425 = mhpme4 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21]
|
|
wire _T_1429 = mhpme4 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21]
|
|
wire _T_1431 = mhpme4 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21]
|
|
wire _T_1433 = mhpme4 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21]
|
|
wire _T_1435 = mhpme4 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21]
|
|
wire _T_1437 = mhpme4 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21]
|
|
wire _T_1439 = mhpme4 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21]
|
|
wire _T_1441 = mhpme4 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21]
|
|
wire _T_1443 = mhpme4 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21]
|
|
wire _T_1448 = mhpme4 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21]
|
|
wire _T_1457 = mhpme4 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21]
|
|
wire _T_1460 = mhpme4 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21]
|
|
wire _T_1463 = mhpme4 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21]
|
|
wire _T_1466 = mhpme4 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21]
|
|
wire _T_1468 = mhpme4 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21]
|
|
wire _T_1470 = mhpme4 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21]
|
|
wire _T_1472 = mhpme4 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21]
|
|
wire _T_1474 = mhpme4 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21]
|
|
wire _T_1477 = _T_1310 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
|
|
wire _T_1478 = _T_1312 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
|
|
wire _T_1479 = _T_1314 & _T_1034; // @[Mux.scala 27:72]
|
|
wire _T_1480 = _T_1318 & _T_1040; // @[Mux.scala 27:72]
|
|
wire _T_1481 = _T_1324 & _T_1045; // @[Mux.scala 27:72]
|
|
wire _T_1482 = _T_1329 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
|
|
wire _T_1483 = _T_1331 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
|
|
wire _T_1484 = _T_1333 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
|
|
wire _T_1485 = _T_1335 & _T_1054; // @[Mux.scala 27:72]
|
|
wire _T_1486 = _T_1338 & _T_1057; // @[Mux.scala 27:72]
|
|
wire _T_1487 = _T_1341 & _T_1060; // @[Mux.scala 27:72]
|
|
wire _T_1488 = _T_1344 & _T_1063; // @[Mux.scala 27:72]
|
|
wire _T_1489 = _T_1347 & _T_1357; // @[Mux.scala 27:72]
|
|
wire _T_1490 = _T_1358 & _T_1077; // @[Mux.scala 27:72]
|
|
wire _T_1491 = _T_1361 & _T_1080; // @[Mux.scala 27:72]
|
|
wire _T_1492 = _T_1364 & _T_1083; // @[Mux.scala 27:72]
|
|
wire _T_1493 = _T_1367 & _T_1086; // @[Mux.scala 27:72]
|
|
wire _T_1494 = _T_1370 & _T_1089; // @[Mux.scala 27:72]
|
|
wire _T_1495 = _T_1373 & _T_1092; // @[Mux.scala 27:72]
|
|
wire _T_1496 = _T_1376 & _T_1095; // @[Mux.scala 27:72]
|
|
wire _T_1497 = _T_1379 & _T_1098; // @[Mux.scala 27:72]
|
|
wire _T_1498 = _T_1382 & _T_1101; // @[Mux.scala 27:72]
|
|
wire _T_1499 = _T_1385 & _T_1106; // @[Mux.scala 27:72]
|
|
wire _T_1500 = _T_1390 & _T_1109; // @[Mux.scala 27:72]
|
|
wire _T_1501 = _T_1393 & _T_1112; // @[Mux.scala 27:72]
|
|
wire _T_1502 = _T_1396 & _T_1115; // @[Mux.scala 27:72]
|
|
wire _T_1503 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
|
|
wire _T_1505 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
|
|
wire _T_1506 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
|
|
wire _T_1507 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1508 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1509 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1510 = _T_1413 & _T_1133; // @[Mux.scala 27:72]
|
|
wire _T_1511 = _T_1417 & _T_1137; // @[Mux.scala 27:72]
|
|
wire _T_1512 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72]
|
|
wire _T_1513 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
|
|
wire _T_1514 = _T_1425 & _T_1145; // @[Mux.scala 27:72]
|
|
wire _T_1515 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_1516 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_1517 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
|
|
wire _T_1518 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_1519 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_1520 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_1521 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_1522 = _T_1443 & _T_1164; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1523 = _T_1448 ? _T_1173 : 6'h0; // @[Mux.scala 27:72]
|
|
wire _T_1524 = _T_1457 & _T_1176; // @[Mux.scala 27:72]
|
|
wire _T_1525 = _T_1460 & _T_1179; // @[Mux.scala 27:72]
|
|
wire _T_1526 = _T_1463 & _T_1182; // @[Mux.scala 27:72]
|
|
wire _T_1527 = _T_1466 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
|
|
wire _T_1528 = _T_1468 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
|
|
wire _T_1529 = _T_1470 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
|
|
wire _T_1530 = _T_1472 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
|
|
wire _T_1531 = _T_1474 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
|
|
wire _T_1532 = _T_1308 | _T_1477; // @[Mux.scala 27:72]
|
|
wire _T_1533 = _T_1532 | _T_1478; // @[Mux.scala 27:72]
|
|
wire _T_1534 = _T_1533 | _T_1479; // @[Mux.scala 27:72]
|
|
wire _T_1535 = _T_1534 | _T_1480; // @[Mux.scala 27:72]
|
|
wire _T_1536 = _T_1535 | _T_1481; // @[Mux.scala 27:72]
|
|
wire _T_1537 = _T_1536 | _T_1482; // @[Mux.scala 27:72]
|
|
wire _T_1538 = _T_1537 | _T_1483; // @[Mux.scala 27:72]
|
|
wire _T_1539 = _T_1538 | _T_1484; // @[Mux.scala 27:72]
|
|
wire _T_1540 = _T_1539 | _T_1485; // @[Mux.scala 27:72]
|
|
wire _T_1541 = _T_1540 | _T_1486; // @[Mux.scala 27:72]
|
|
wire _T_1542 = _T_1541 | _T_1487; // @[Mux.scala 27:72]
|
|
wire _T_1543 = _T_1542 | _T_1488; // @[Mux.scala 27:72]
|
|
wire _T_1544 = _T_1543 | _T_1489; // @[Mux.scala 27:72]
|
|
wire _T_1545 = _T_1544 | _T_1490; // @[Mux.scala 27:72]
|
|
wire _T_1546 = _T_1545 | _T_1491; // @[Mux.scala 27:72]
|
|
wire _T_1547 = _T_1546 | _T_1492; // @[Mux.scala 27:72]
|
|
wire _T_1548 = _T_1547 | _T_1493; // @[Mux.scala 27:72]
|
|
wire _T_1549 = _T_1548 | _T_1494; // @[Mux.scala 27:72]
|
|
wire _T_1550 = _T_1549 | _T_1495; // @[Mux.scala 27:72]
|
|
wire _T_1551 = _T_1550 | _T_1496; // @[Mux.scala 27:72]
|
|
wire _T_1552 = _T_1551 | _T_1497; // @[Mux.scala 27:72]
|
|
wire _T_1553 = _T_1552 | _T_1498; // @[Mux.scala 27:72]
|
|
wire _T_1554 = _T_1553 | _T_1499; // @[Mux.scala 27:72]
|
|
wire _T_1555 = _T_1554 | _T_1500; // @[Mux.scala 27:72]
|
|
wire _T_1556 = _T_1555 | _T_1501; // @[Mux.scala 27:72]
|
|
wire _T_1557 = _T_1556 | _T_1502; // @[Mux.scala 27:72]
|
|
wire _T_1558 = _T_1557 | _T_1503; // @[Mux.scala 27:72]
|
|
wire _T_1559 = _T_1558 | _T_1484; // @[Mux.scala 27:72]
|
|
wire _T_1560 = _T_1559 | _T_1505; // @[Mux.scala 27:72]
|
|
wire _T_1561 = _T_1560 | _T_1506; // @[Mux.scala 27:72]
|
|
wire _T_1562 = _T_1561 | _T_1507; // @[Mux.scala 27:72]
|
|
wire _T_1563 = _T_1562 | _T_1508; // @[Mux.scala 27:72]
|
|
wire _T_1564 = _T_1563 | _T_1509; // @[Mux.scala 27:72]
|
|
wire _T_1565 = _T_1564 | _T_1510; // @[Mux.scala 27:72]
|
|
wire _T_1566 = _T_1565 | _T_1511; // @[Mux.scala 27:72]
|
|
wire _T_1567 = _T_1566 | _T_1512; // @[Mux.scala 27:72]
|
|
wire _T_1568 = _T_1567 | _T_1513; // @[Mux.scala 27:72]
|
|
wire _T_1569 = _T_1568 | _T_1514; // @[Mux.scala 27:72]
|
|
wire _T_1570 = _T_1569 | _T_1515; // @[Mux.scala 27:72]
|
|
wire _T_1571 = _T_1570 | _T_1516; // @[Mux.scala 27:72]
|
|
wire _T_1572 = _T_1571 | _T_1517; // @[Mux.scala 27:72]
|
|
wire _T_1573 = _T_1572 | _T_1518; // @[Mux.scala 27:72]
|
|
wire _T_1574 = _T_1573 | _T_1519; // @[Mux.scala 27:72]
|
|
wire _T_1575 = _T_1574 | _T_1520; // @[Mux.scala 27:72]
|
|
wire _T_1576 = _T_1575 | _T_1521; // @[Mux.scala 27:72]
|
|
wire _T_1577 = _T_1576 | _T_1522; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_29 = {{5'd0}, _T_1577}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1578 = _GEN_29 | _T_1523; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_30 = {{5'd0}, _T_1524}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1579 = _T_1578 | _GEN_30; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_31 = {{5'd0}, _T_1525}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1580 = _T_1579 | _GEN_31; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_32 = {{5'd0}, _T_1526}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1581 = _T_1580 | _GEN_32; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_33 = {{5'd0}, _T_1527}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1582 = _T_1581 | _GEN_33; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_34 = {{5'd0}, _T_1528}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1583 = _T_1582 | _GEN_34; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_35 = {{5'd0}, _T_1529}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1584 = _T_1583 | _GEN_35; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_36 = {{5'd0}, _T_1530}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1585 = _T_1584 | _GEN_36; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_37 = {{5'd0}, _T_1531}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1586 = _T_1585 | _GEN_37; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_38 = {{5'd0}, _T_1307}; // @[el2_dec_tlu_ctl.scala 2351:45]
|
|
wire [5:0] _T_1588 = _GEN_38 & _T_1586; // @[el2_dec_tlu_ctl.scala 2351:45]
|
|
wire _T_1590 = ~mcountinhibit[5]; // @[el2_dec_tlu_ctl.scala 2351:25]
|
|
reg [9:0] mhpme5; // @[Reg.scala 27:20]
|
|
wire _T_1591 = mhpme5 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21]
|
|
wire _T_1593 = mhpme5 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21]
|
|
wire _T_1595 = mhpme5 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21]
|
|
wire _T_1597 = mhpme5 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21]
|
|
wire _T_1601 = mhpme5 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21]
|
|
wire _T_1607 = mhpme5 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21]
|
|
wire _T_1612 = mhpme5 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21]
|
|
wire _T_1614 = mhpme5 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21]
|
|
wire _T_1616 = mhpme5 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21]
|
|
wire _T_1618 = mhpme5 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21]
|
|
wire _T_1621 = mhpme5 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21]
|
|
wire _T_1624 = mhpme5 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21]
|
|
wire _T_1627 = mhpme5 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21]
|
|
wire _T_1630 = mhpme5 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21]
|
|
wire _T_1633 = mhpme5 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21]
|
|
wire _T_1634 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1633; // @[el2_dec_tlu_ctl.scala 2366:7]
|
|
wire _T_1636 = _T_1060 & _T_1634; // @[el2_dec_tlu_ctl.scala 2365:89]
|
|
wire _T_1638 = _T_1636 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45]
|
|
wire _T_1640 = _T_1638 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77]
|
|
wire _T_1641 = mhpme5 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21]
|
|
wire _T_1644 = mhpme5 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21]
|
|
wire _T_1647 = mhpme5 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21]
|
|
wire _T_1650 = mhpme5 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21]
|
|
wire _T_1653 = mhpme5 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21]
|
|
wire _T_1656 = mhpme5 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21]
|
|
wire _T_1659 = mhpme5 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21]
|
|
wire _T_1662 = mhpme5 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21]
|
|
wire _T_1665 = mhpme5 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21]
|
|
wire _T_1668 = mhpme5 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21]
|
|
wire _T_1673 = mhpme5 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21]
|
|
wire _T_1676 = mhpme5 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21]
|
|
wire _T_1679 = mhpme5 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21]
|
|
wire _T_1682 = mhpme5 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21]
|
|
wire _T_1686 = mhpme5 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21]
|
|
wire _T_1688 = mhpme5 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21]
|
|
wire _T_1690 = mhpme5 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21]
|
|
wire _T_1692 = mhpme5 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21]
|
|
wire _T_1694 = mhpme5 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21]
|
|
wire _T_1696 = mhpme5 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21]
|
|
wire _T_1700 = mhpme5 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21]
|
|
wire _T_1704 = mhpme5 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21]
|
|
wire _T_1706 = mhpme5 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21]
|
|
wire _T_1708 = mhpme5 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21]
|
|
wire _T_1712 = mhpme5 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21]
|
|
wire _T_1714 = mhpme5 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21]
|
|
wire _T_1716 = mhpme5 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21]
|
|
wire _T_1718 = mhpme5 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21]
|
|
wire _T_1720 = mhpme5 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21]
|
|
wire _T_1722 = mhpme5 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21]
|
|
wire _T_1724 = mhpme5 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21]
|
|
wire _T_1726 = mhpme5 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21]
|
|
wire _T_1731 = mhpme5 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21]
|
|
wire _T_1740 = mhpme5 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21]
|
|
wire _T_1743 = mhpme5 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21]
|
|
wire _T_1746 = mhpme5 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21]
|
|
wire _T_1749 = mhpme5 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21]
|
|
wire _T_1751 = mhpme5 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21]
|
|
wire _T_1753 = mhpme5 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21]
|
|
wire _T_1755 = mhpme5 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21]
|
|
wire _T_1757 = mhpme5 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21]
|
|
wire _T_1760 = _T_1593 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
|
|
wire _T_1761 = _T_1595 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
|
|
wire _T_1762 = _T_1597 & _T_1034; // @[Mux.scala 27:72]
|
|
wire _T_1763 = _T_1601 & _T_1040; // @[Mux.scala 27:72]
|
|
wire _T_1764 = _T_1607 & _T_1045; // @[Mux.scala 27:72]
|
|
wire _T_1765 = _T_1612 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
|
|
wire _T_1766 = _T_1614 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
|
|
wire _T_1767 = _T_1616 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
|
|
wire _T_1768 = _T_1618 & _T_1054; // @[Mux.scala 27:72]
|
|
wire _T_1769 = _T_1621 & _T_1057; // @[Mux.scala 27:72]
|
|
wire _T_1770 = _T_1624 & _T_1060; // @[Mux.scala 27:72]
|
|
wire _T_1771 = _T_1627 & _T_1063; // @[Mux.scala 27:72]
|
|
wire _T_1772 = _T_1630 & _T_1640; // @[Mux.scala 27:72]
|
|
wire _T_1773 = _T_1641 & _T_1077; // @[Mux.scala 27:72]
|
|
wire _T_1774 = _T_1644 & _T_1080; // @[Mux.scala 27:72]
|
|
wire _T_1775 = _T_1647 & _T_1083; // @[Mux.scala 27:72]
|
|
wire _T_1776 = _T_1650 & _T_1086; // @[Mux.scala 27:72]
|
|
wire _T_1777 = _T_1653 & _T_1089; // @[Mux.scala 27:72]
|
|
wire _T_1778 = _T_1656 & _T_1092; // @[Mux.scala 27:72]
|
|
wire _T_1779 = _T_1659 & _T_1095; // @[Mux.scala 27:72]
|
|
wire _T_1780 = _T_1662 & _T_1098; // @[Mux.scala 27:72]
|
|
wire _T_1781 = _T_1665 & _T_1101; // @[Mux.scala 27:72]
|
|
wire _T_1782 = _T_1668 & _T_1106; // @[Mux.scala 27:72]
|
|
wire _T_1783 = _T_1673 & _T_1109; // @[Mux.scala 27:72]
|
|
wire _T_1784 = _T_1676 & _T_1112; // @[Mux.scala 27:72]
|
|
wire _T_1785 = _T_1679 & _T_1115; // @[Mux.scala 27:72]
|
|
wire _T_1786 = _T_1682 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
|
|
wire _T_1788 = _T_1686 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
|
|
wire _T_1789 = _T_1688 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
|
|
wire _T_1790 = _T_1690 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1791 = _T_1692 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1792 = _T_1694 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1793 = _T_1696 & _T_1133; // @[Mux.scala 27:72]
|
|
wire _T_1794 = _T_1700 & _T_1137; // @[Mux.scala 27:72]
|
|
wire _T_1795 = _T_1704 & io_take_ext_int; // @[Mux.scala 27:72]
|
|
wire _T_1796 = _T_1706 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
|
|
wire _T_1797 = _T_1708 & _T_1145; // @[Mux.scala 27:72]
|
|
wire _T_1798 = _T_1712 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_1799 = _T_1714 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_1800 = _T_1716 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
|
|
wire _T_1801 = _T_1718 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_1802 = _T_1720 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_1803 = _T_1722 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_1804 = _T_1724 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_1805 = _T_1726 & _T_1164; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1806 = _T_1731 ? _T_1173 : 6'h0; // @[Mux.scala 27:72]
|
|
wire _T_1807 = _T_1740 & _T_1176; // @[Mux.scala 27:72]
|
|
wire _T_1808 = _T_1743 & _T_1179; // @[Mux.scala 27:72]
|
|
wire _T_1809 = _T_1746 & _T_1182; // @[Mux.scala 27:72]
|
|
wire _T_1810 = _T_1749 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
|
|
wire _T_1811 = _T_1751 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
|
|
wire _T_1812 = _T_1753 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
|
|
wire _T_1813 = _T_1755 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
|
|
wire _T_1814 = _T_1757 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
|
|
wire _T_1815 = _T_1591 | _T_1760; // @[Mux.scala 27:72]
|
|
wire _T_1816 = _T_1815 | _T_1761; // @[Mux.scala 27:72]
|
|
wire _T_1817 = _T_1816 | _T_1762; // @[Mux.scala 27:72]
|
|
wire _T_1818 = _T_1817 | _T_1763; // @[Mux.scala 27:72]
|
|
wire _T_1819 = _T_1818 | _T_1764; // @[Mux.scala 27:72]
|
|
wire _T_1820 = _T_1819 | _T_1765; // @[Mux.scala 27:72]
|
|
wire _T_1821 = _T_1820 | _T_1766; // @[Mux.scala 27:72]
|
|
wire _T_1822 = _T_1821 | _T_1767; // @[Mux.scala 27:72]
|
|
wire _T_1823 = _T_1822 | _T_1768; // @[Mux.scala 27:72]
|
|
wire _T_1824 = _T_1823 | _T_1769; // @[Mux.scala 27:72]
|
|
wire _T_1825 = _T_1824 | _T_1770; // @[Mux.scala 27:72]
|
|
wire _T_1826 = _T_1825 | _T_1771; // @[Mux.scala 27:72]
|
|
wire _T_1827 = _T_1826 | _T_1772; // @[Mux.scala 27:72]
|
|
wire _T_1828 = _T_1827 | _T_1773; // @[Mux.scala 27:72]
|
|
wire _T_1829 = _T_1828 | _T_1774; // @[Mux.scala 27:72]
|
|
wire _T_1830 = _T_1829 | _T_1775; // @[Mux.scala 27:72]
|
|
wire _T_1831 = _T_1830 | _T_1776; // @[Mux.scala 27:72]
|
|
wire _T_1832 = _T_1831 | _T_1777; // @[Mux.scala 27:72]
|
|
wire _T_1833 = _T_1832 | _T_1778; // @[Mux.scala 27:72]
|
|
wire _T_1834 = _T_1833 | _T_1779; // @[Mux.scala 27:72]
|
|
wire _T_1835 = _T_1834 | _T_1780; // @[Mux.scala 27:72]
|
|
wire _T_1836 = _T_1835 | _T_1781; // @[Mux.scala 27:72]
|
|
wire _T_1837 = _T_1836 | _T_1782; // @[Mux.scala 27:72]
|
|
wire _T_1838 = _T_1837 | _T_1783; // @[Mux.scala 27:72]
|
|
wire _T_1839 = _T_1838 | _T_1784; // @[Mux.scala 27:72]
|
|
wire _T_1840 = _T_1839 | _T_1785; // @[Mux.scala 27:72]
|
|
wire _T_1841 = _T_1840 | _T_1786; // @[Mux.scala 27:72]
|
|
wire _T_1842 = _T_1841 | _T_1767; // @[Mux.scala 27:72]
|
|
wire _T_1843 = _T_1842 | _T_1788; // @[Mux.scala 27:72]
|
|
wire _T_1844 = _T_1843 | _T_1789; // @[Mux.scala 27:72]
|
|
wire _T_1845 = _T_1844 | _T_1790; // @[Mux.scala 27:72]
|
|
wire _T_1846 = _T_1845 | _T_1791; // @[Mux.scala 27:72]
|
|
wire _T_1847 = _T_1846 | _T_1792; // @[Mux.scala 27:72]
|
|
wire _T_1848 = _T_1847 | _T_1793; // @[Mux.scala 27:72]
|
|
wire _T_1849 = _T_1848 | _T_1794; // @[Mux.scala 27:72]
|
|
wire _T_1850 = _T_1849 | _T_1795; // @[Mux.scala 27:72]
|
|
wire _T_1851 = _T_1850 | _T_1796; // @[Mux.scala 27:72]
|
|
wire _T_1852 = _T_1851 | _T_1797; // @[Mux.scala 27:72]
|
|
wire _T_1853 = _T_1852 | _T_1798; // @[Mux.scala 27:72]
|
|
wire _T_1854 = _T_1853 | _T_1799; // @[Mux.scala 27:72]
|
|
wire _T_1855 = _T_1854 | _T_1800; // @[Mux.scala 27:72]
|
|
wire _T_1856 = _T_1855 | _T_1801; // @[Mux.scala 27:72]
|
|
wire _T_1857 = _T_1856 | _T_1802; // @[Mux.scala 27:72]
|
|
wire _T_1858 = _T_1857 | _T_1803; // @[Mux.scala 27:72]
|
|
wire _T_1859 = _T_1858 | _T_1804; // @[Mux.scala 27:72]
|
|
wire _T_1860 = _T_1859 | _T_1805; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_40 = {{5'd0}, _T_1860}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1861 = _GEN_40 | _T_1806; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_41 = {{5'd0}, _T_1807}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1862 = _T_1861 | _GEN_41; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_42 = {{5'd0}, _T_1808}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1863 = _T_1862 | _GEN_42; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_43 = {{5'd0}, _T_1809}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1864 = _T_1863 | _GEN_43; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_44 = {{5'd0}, _T_1810}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1865 = _T_1864 | _GEN_44; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_45 = {{5'd0}, _T_1811}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1866 = _T_1865 | _GEN_45; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_46 = {{5'd0}, _T_1812}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1867 = _T_1866 | _GEN_46; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_47 = {{5'd0}, _T_1813}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1868 = _T_1867 | _GEN_47; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_48 = {{5'd0}, _T_1814}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_1869 = _T_1868 | _GEN_48; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_49 = {{5'd0}, _T_1590}; // @[el2_dec_tlu_ctl.scala 2351:45]
|
|
wire [5:0] _T_1871 = _GEN_49 & _T_1869; // @[el2_dec_tlu_ctl.scala 2351:45]
|
|
wire _T_1873 = ~mcountinhibit[6]; // @[el2_dec_tlu_ctl.scala 2351:25]
|
|
reg [9:0] mhpme6; // @[Reg.scala 27:20]
|
|
wire _T_1874 = mhpme6 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21]
|
|
wire _T_1876 = mhpme6 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21]
|
|
wire _T_1878 = mhpme6 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21]
|
|
wire _T_1880 = mhpme6 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21]
|
|
wire _T_1884 = mhpme6 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21]
|
|
wire _T_1890 = mhpme6 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21]
|
|
wire _T_1895 = mhpme6 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21]
|
|
wire _T_1897 = mhpme6 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21]
|
|
wire _T_1899 = mhpme6 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21]
|
|
wire _T_1901 = mhpme6 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21]
|
|
wire _T_1904 = mhpme6 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21]
|
|
wire _T_1907 = mhpme6 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21]
|
|
wire _T_1910 = mhpme6 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21]
|
|
wire _T_1913 = mhpme6 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21]
|
|
wire _T_1916 = mhpme6 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21]
|
|
wire _T_1917 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1916; // @[el2_dec_tlu_ctl.scala 2366:7]
|
|
wire _T_1919 = _T_1060 & _T_1917; // @[el2_dec_tlu_ctl.scala 2365:89]
|
|
wire _T_1921 = _T_1919 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45]
|
|
wire _T_1923 = _T_1921 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77]
|
|
wire _T_1924 = mhpme6 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21]
|
|
wire _T_1927 = mhpme6 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21]
|
|
wire _T_1930 = mhpme6 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21]
|
|
wire _T_1933 = mhpme6 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21]
|
|
wire _T_1936 = mhpme6 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21]
|
|
wire _T_1939 = mhpme6 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21]
|
|
wire _T_1942 = mhpme6 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21]
|
|
wire _T_1945 = mhpme6 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21]
|
|
wire _T_1948 = mhpme6 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21]
|
|
wire _T_1951 = mhpme6 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21]
|
|
wire _T_1956 = mhpme6 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21]
|
|
wire _T_1959 = mhpme6 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21]
|
|
wire _T_1962 = mhpme6 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21]
|
|
wire _T_1965 = mhpme6 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21]
|
|
wire _T_1969 = mhpme6 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21]
|
|
wire _T_1971 = mhpme6 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21]
|
|
wire _T_1973 = mhpme6 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21]
|
|
wire _T_1975 = mhpme6 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21]
|
|
wire _T_1977 = mhpme6 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21]
|
|
wire _T_1979 = mhpme6 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21]
|
|
wire _T_1983 = mhpme6 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21]
|
|
wire _T_1987 = mhpme6 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21]
|
|
wire _T_1989 = mhpme6 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21]
|
|
wire _T_1991 = mhpme6 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21]
|
|
wire _T_1995 = mhpme6 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21]
|
|
wire _T_1997 = mhpme6 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21]
|
|
wire _T_1999 = mhpme6 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21]
|
|
wire _T_2001 = mhpme6 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21]
|
|
wire _T_2003 = mhpme6 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21]
|
|
wire _T_2005 = mhpme6 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21]
|
|
wire _T_2007 = mhpme6 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21]
|
|
wire _T_2009 = mhpme6 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21]
|
|
wire _T_2014 = mhpme6 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21]
|
|
wire _T_2023 = mhpme6 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21]
|
|
wire _T_2026 = mhpme6 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21]
|
|
wire _T_2029 = mhpme6 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21]
|
|
wire _T_2032 = mhpme6 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21]
|
|
wire _T_2034 = mhpme6 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21]
|
|
wire _T_2036 = mhpme6 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21]
|
|
wire _T_2038 = mhpme6 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21]
|
|
wire _T_2040 = mhpme6 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21]
|
|
wire _T_2043 = _T_1876 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
|
|
wire _T_2044 = _T_1878 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
|
|
wire _T_2045 = _T_1880 & _T_1034; // @[Mux.scala 27:72]
|
|
wire _T_2046 = _T_1884 & _T_1040; // @[Mux.scala 27:72]
|
|
wire _T_2047 = _T_1890 & _T_1045; // @[Mux.scala 27:72]
|
|
wire _T_2048 = _T_1895 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
|
|
wire _T_2049 = _T_1897 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
|
|
wire _T_2050 = _T_1899 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
|
|
wire _T_2051 = _T_1901 & _T_1054; // @[Mux.scala 27:72]
|
|
wire _T_2052 = _T_1904 & _T_1057; // @[Mux.scala 27:72]
|
|
wire _T_2053 = _T_1907 & _T_1060; // @[Mux.scala 27:72]
|
|
wire _T_2054 = _T_1910 & _T_1063; // @[Mux.scala 27:72]
|
|
wire _T_2055 = _T_1913 & _T_1923; // @[Mux.scala 27:72]
|
|
wire _T_2056 = _T_1924 & _T_1077; // @[Mux.scala 27:72]
|
|
wire _T_2057 = _T_1927 & _T_1080; // @[Mux.scala 27:72]
|
|
wire _T_2058 = _T_1930 & _T_1083; // @[Mux.scala 27:72]
|
|
wire _T_2059 = _T_1933 & _T_1086; // @[Mux.scala 27:72]
|
|
wire _T_2060 = _T_1936 & _T_1089; // @[Mux.scala 27:72]
|
|
wire _T_2061 = _T_1939 & _T_1092; // @[Mux.scala 27:72]
|
|
wire _T_2062 = _T_1942 & _T_1095; // @[Mux.scala 27:72]
|
|
wire _T_2063 = _T_1945 & _T_1098; // @[Mux.scala 27:72]
|
|
wire _T_2064 = _T_1948 & _T_1101; // @[Mux.scala 27:72]
|
|
wire _T_2065 = _T_1951 & _T_1106; // @[Mux.scala 27:72]
|
|
wire _T_2066 = _T_1956 & _T_1109; // @[Mux.scala 27:72]
|
|
wire _T_2067 = _T_1959 & _T_1112; // @[Mux.scala 27:72]
|
|
wire _T_2068 = _T_1962 & _T_1115; // @[Mux.scala 27:72]
|
|
wire _T_2069 = _T_1965 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
|
|
wire _T_2071 = _T_1969 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
|
|
wire _T_2072 = _T_1971 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
|
|
wire _T_2073 = _T_1973 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_2074 = _T_1975 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_2075 = _T_1977 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_2076 = _T_1979 & _T_1133; // @[Mux.scala 27:72]
|
|
wire _T_2077 = _T_1983 & _T_1137; // @[Mux.scala 27:72]
|
|
wire _T_2078 = _T_1987 & io_take_ext_int; // @[Mux.scala 27:72]
|
|
wire _T_2079 = _T_1989 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
|
|
wire _T_2080 = _T_1991 & _T_1145; // @[Mux.scala 27:72]
|
|
wire _T_2081 = _T_1995 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_2082 = _T_1997 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_2083 = _T_1999 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
|
|
wire _T_2084 = _T_2001 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_2085 = _T_2003 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_2086 = _T_2005 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_2087 = _T_2007 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_2088 = _T_2009 & _T_1164; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_2089 = _T_2014 ? _T_1173 : 6'h0; // @[Mux.scala 27:72]
|
|
wire _T_2090 = _T_2023 & _T_1176; // @[Mux.scala 27:72]
|
|
wire _T_2091 = _T_2026 & _T_1179; // @[Mux.scala 27:72]
|
|
wire _T_2092 = _T_2029 & _T_1182; // @[Mux.scala 27:72]
|
|
wire _T_2093 = _T_2032 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
|
|
wire _T_2094 = _T_2034 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
|
|
wire _T_2095 = _T_2036 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
|
|
wire _T_2096 = _T_2038 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
|
|
wire _T_2097 = _T_2040 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
|
|
wire _T_2098 = _T_1874 | _T_2043; // @[Mux.scala 27:72]
|
|
wire _T_2099 = _T_2098 | _T_2044; // @[Mux.scala 27:72]
|
|
wire _T_2100 = _T_2099 | _T_2045; // @[Mux.scala 27:72]
|
|
wire _T_2101 = _T_2100 | _T_2046; // @[Mux.scala 27:72]
|
|
wire _T_2102 = _T_2101 | _T_2047; // @[Mux.scala 27:72]
|
|
wire _T_2103 = _T_2102 | _T_2048; // @[Mux.scala 27:72]
|
|
wire _T_2104 = _T_2103 | _T_2049; // @[Mux.scala 27:72]
|
|
wire _T_2105 = _T_2104 | _T_2050; // @[Mux.scala 27:72]
|
|
wire _T_2106 = _T_2105 | _T_2051; // @[Mux.scala 27:72]
|
|
wire _T_2107 = _T_2106 | _T_2052; // @[Mux.scala 27:72]
|
|
wire _T_2108 = _T_2107 | _T_2053; // @[Mux.scala 27:72]
|
|
wire _T_2109 = _T_2108 | _T_2054; // @[Mux.scala 27:72]
|
|
wire _T_2110 = _T_2109 | _T_2055; // @[Mux.scala 27:72]
|
|
wire _T_2111 = _T_2110 | _T_2056; // @[Mux.scala 27:72]
|
|
wire _T_2112 = _T_2111 | _T_2057; // @[Mux.scala 27:72]
|
|
wire _T_2113 = _T_2112 | _T_2058; // @[Mux.scala 27:72]
|
|
wire _T_2114 = _T_2113 | _T_2059; // @[Mux.scala 27:72]
|
|
wire _T_2115 = _T_2114 | _T_2060; // @[Mux.scala 27:72]
|
|
wire _T_2116 = _T_2115 | _T_2061; // @[Mux.scala 27:72]
|
|
wire _T_2117 = _T_2116 | _T_2062; // @[Mux.scala 27:72]
|
|
wire _T_2118 = _T_2117 | _T_2063; // @[Mux.scala 27:72]
|
|
wire _T_2119 = _T_2118 | _T_2064; // @[Mux.scala 27:72]
|
|
wire _T_2120 = _T_2119 | _T_2065; // @[Mux.scala 27:72]
|
|
wire _T_2121 = _T_2120 | _T_2066; // @[Mux.scala 27:72]
|
|
wire _T_2122 = _T_2121 | _T_2067; // @[Mux.scala 27:72]
|
|
wire _T_2123 = _T_2122 | _T_2068; // @[Mux.scala 27:72]
|
|
wire _T_2124 = _T_2123 | _T_2069; // @[Mux.scala 27:72]
|
|
wire _T_2125 = _T_2124 | _T_2050; // @[Mux.scala 27:72]
|
|
wire _T_2126 = _T_2125 | _T_2071; // @[Mux.scala 27:72]
|
|
wire _T_2127 = _T_2126 | _T_2072; // @[Mux.scala 27:72]
|
|
wire _T_2128 = _T_2127 | _T_2073; // @[Mux.scala 27:72]
|
|
wire _T_2129 = _T_2128 | _T_2074; // @[Mux.scala 27:72]
|
|
wire _T_2130 = _T_2129 | _T_2075; // @[Mux.scala 27:72]
|
|
wire _T_2131 = _T_2130 | _T_2076; // @[Mux.scala 27:72]
|
|
wire _T_2132 = _T_2131 | _T_2077; // @[Mux.scala 27:72]
|
|
wire _T_2133 = _T_2132 | _T_2078; // @[Mux.scala 27:72]
|
|
wire _T_2134 = _T_2133 | _T_2079; // @[Mux.scala 27:72]
|
|
wire _T_2135 = _T_2134 | _T_2080; // @[Mux.scala 27:72]
|
|
wire _T_2136 = _T_2135 | _T_2081; // @[Mux.scala 27:72]
|
|
wire _T_2137 = _T_2136 | _T_2082; // @[Mux.scala 27:72]
|
|
wire _T_2138 = _T_2137 | _T_2083; // @[Mux.scala 27:72]
|
|
wire _T_2139 = _T_2138 | _T_2084; // @[Mux.scala 27:72]
|
|
wire _T_2140 = _T_2139 | _T_2085; // @[Mux.scala 27:72]
|
|
wire _T_2141 = _T_2140 | _T_2086; // @[Mux.scala 27:72]
|
|
wire _T_2142 = _T_2141 | _T_2087; // @[Mux.scala 27:72]
|
|
wire _T_2143 = _T_2142 | _T_2088; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_51 = {{5'd0}, _T_2143}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_2144 = _GEN_51 | _T_2089; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_52 = {{5'd0}, _T_2090}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_2145 = _T_2144 | _GEN_52; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_53 = {{5'd0}, _T_2091}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_2146 = _T_2145 | _GEN_53; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_54 = {{5'd0}, _T_2092}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_2147 = _T_2146 | _GEN_54; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_55 = {{5'd0}, _T_2093}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_2148 = _T_2147 | _GEN_55; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_56 = {{5'd0}, _T_2094}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_2149 = _T_2148 | _GEN_56; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_57 = {{5'd0}, _T_2095}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_2150 = _T_2149 | _GEN_57; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_58 = {{5'd0}, _T_2096}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_2151 = _T_2150 | _GEN_58; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_59 = {{5'd0}, _T_2097}; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_2152 = _T_2151 | _GEN_59; // @[Mux.scala 27:72]
|
|
wire [5:0] _GEN_60 = {{5'd0}, _T_1873}; // @[el2_dec_tlu_ctl.scala 2351:45]
|
|
wire [5:0] _T_2154 = _GEN_60 & _T_2152; // @[el2_dec_tlu_ctl.scala 2351:45]
|
|
reg mhpmc_inc_r_d1_0; // @[el2_dec_tlu_ctl.scala 2413:54]
|
|
reg mhpmc_inc_r_d1_1; // @[el2_dec_tlu_ctl.scala 2414:54]
|
|
reg mhpmc_inc_r_d1_2; // @[el2_dec_tlu_ctl.scala 2415:54]
|
|
reg mhpmc_inc_r_d1_3; // @[el2_dec_tlu_ctl.scala 2416:54]
|
|
reg perfcnt_halted_d1; // @[el2_dec_tlu_ctl.scala 2417:57]
|
|
wire perfcnt_halted = _T_83 | io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 2420:68]
|
|
wire _T_2164 = ~_T_83; // @[el2_dec_tlu_ctl.scala 2421:38]
|
|
wire [3:0] _T_2166 = _T_2164 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_2173 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58]
|
|
wire [3:0] perfcnt_during_sleep = _T_2166 & _T_2173; // @[el2_dec_tlu_ctl.scala 2421:87]
|
|
wire _T_2175 = ~perfcnt_during_sleep[0]; // @[el2_dec_tlu_ctl.scala 2423:68]
|
|
wire _T_2176 = perfcnt_halted_d1 & _T_2175; // @[el2_dec_tlu_ctl.scala 2423:66]
|
|
wire _T_2177 = ~_T_2176; // @[el2_dec_tlu_ctl.scala 2423:46]
|
|
wire _T_2180 = ~perfcnt_during_sleep[1]; // @[el2_dec_tlu_ctl.scala 2424:68]
|
|
wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[el2_dec_tlu_ctl.scala 2424:66]
|
|
wire _T_2182 = ~_T_2181; // @[el2_dec_tlu_ctl.scala 2424:46]
|
|
wire _T_2185 = ~perfcnt_during_sleep[2]; // @[el2_dec_tlu_ctl.scala 2425:68]
|
|
wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[el2_dec_tlu_ctl.scala 2425:66]
|
|
wire _T_2187 = ~_T_2186; // @[el2_dec_tlu_ctl.scala 2425:46]
|
|
wire _T_2190 = ~perfcnt_during_sleep[3]; // @[el2_dec_tlu_ctl.scala 2426:68]
|
|
wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[el2_dec_tlu_ctl.scala 2426:66]
|
|
wire _T_2192 = ~_T_2191; // @[el2_dec_tlu_ctl.scala 2426:46]
|
|
wire _T_2195 = io_dec_csr_wraddr_r == 12'hb03; // @[el2_dec_tlu_ctl.scala 2432:73]
|
|
wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2195; // @[el2_dec_tlu_ctl.scala 2432:44]
|
|
wire _T_2196 = ~perfcnt_halted; // @[el2_dec_tlu_ctl.scala 2433:24]
|
|
wire _T_2198 = _T_2196 | perfcnt_during_sleep[0]; // @[el2_dec_tlu_ctl.scala 2433:40]
|
|
wire mhpmc_inc_r_0 = _T_1305[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20]
|
|
wire _T_2199 = |mhpmc_inc_r_0; // @[el2_dec_tlu_ctl.scala 2433:87]
|
|
wire mhpmc3_wr_en1 = _T_2198 & _T_2199; // @[el2_dec_tlu_ctl.scala 2433:67]
|
|
reg [31:0] mhpmc3h; // @[el2_lib.scala 514:16]
|
|
reg [31:0] mhpmc3; // @[el2_lib.scala 514:16]
|
|
wire [63:0] _T_2202 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_2203 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58]
|
|
wire [63:0] mhpmc3_incr = _T_2202 + _T_2203; // @[el2_dec_tlu_ctl.scala 2437:50]
|
|
wire _T_2211 = io_dec_csr_wraddr_r == 12'hb83; // @[el2_dec_tlu_ctl.scala 2442:74]
|
|
wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2211; // @[el2_dec_tlu_ctl.scala 2442:45]
|
|
wire _T_2217 = io_dec_csr_wraddr_r == 12'hb04; // @[el2_dec_tlu_ctl.scala 2451:73]
|
|
wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2217; // @[el2_dec_tlu_ctl.scala 2451:44]
|
|
wire _T_2220 = _T_2196 | perfcnt_during_sleep[1]; // @[el2_dec_tlu_ctl.scala 2452:40]
|
|
wire mhpmc_inc_r_1 = _T_1588[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20]
|
|
wire _T_2221 = |mhpmc_inc_r_1; // @[el2_dec_tlu_ctl.scala 2452:87]
|
|
wire mhpmc4_wr_en1 = _T_2220 & _T_2221; // @[el2_dec_tlu_ctl.scala 2452:67]
|
|
reg [31:0] mhpmc4h; // @[el2_lib.scala 514:16]
|
|
reg [31:0] mhpmc4; // @[el2_lib.scala 514:16]
|
|
wire [63:0] _T_2224 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_2225 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58]
|
|
wire [63:0] mhpmc4_incr = _T_2224 + _T_2225; // @[el2_dec_tlu_ctl.scala 2457:50]
|
|
wire _T_2234 = io_dec_csr_wraddr_r == 12'hb84; // @[el2_dec_tlu_ctl.scala 2461:74]
|
|
wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2234; // @[el2_dec_tlu_ctl.scala 2461:45]
|
|
wire _T_2240 = io_dec_csr_wraddr_r == 12'hb05; // @[el2_dec_tlu_ctl.scala 2470:73]
|
|
wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2240; // @[el2_dec_tlu_ctl.scala 2470:44]
|
|
wire _T_2243 = _T_2196 | perfcnt_during_sleep[2]; // @[el2_dec_tlu_ctl.scala 2471:40]
|
|
wire mhpmc_inc_r_2 = _T_1871[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20]
|
|
wire _T_2244 = |mhpmc_inc_r_2; // @[el2_dec_tlu_ctl.scala 2471:87]
|
|
wire mhpmc5_wr_en1 = _T_2243 & _T_2244; // @[el2_dec_tlu_ctl.scala 2471:67]
|
|
reg [31:0] mhpmc5h; // @[el2_lib.scala 514:16]
|
|
reg [31:0] mhpmc5; // @[el2_lib.scala 514:16]
|
|
wire [63:0] _T_2247 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_2248 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58]
|
|
wire [63:0] mhpmc5_incr = _T_2247 + _T_2248; // @[el2_dec_tlu_ctl.scala 2474:50]
|
|
wire _T_2256 = io_dec_csr_wraddr_r == 12'hb85; // @[el2_dec_tlu_ctl.scala 2479:74]
|
|
wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2256; // @[el2_dec_tlu_ctl.scala 2479:45]
|
|
wire _T_2262 = io_dec_csr_wraddr_r == 12'hb06; // @[el2_dec_tlu_ctl.scala 2488:73]
|
|
wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2262; // @[el2_dec_tlu_ctl.scala 2488:44]
|
|
wire _T_2265 = _T_2196 | perfcnt_during_sleep[3]; // @[el2_dec_tlu_ctl.scala 2489:40]
|
|
wire mhpmc_inc_r_3 = _T_2154[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20]
|
|
wire _T_2266 = |mhpmc_inc_r_3; // @[el2_dec_tlu_ctl.scala 2489:87]
|
|
wire mhpmc6_wr_en1 = _T_2265 & _T_2266; // @[el2_dec_tlu_ctl.scala 2489:67]
|
|
reg [31:0] mhpmc6h; // @[el2_lib.scala 514:16]
|
|
reg [31:0] mhpmc6; // @[el2_lib.scala 514:16]
|
|
wire [63:0] _T_2269 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_2270 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58]
|
|
wire [63:0] mhpmc6_incr = _T_2269 + _T_2270; // @[el2_dec_tlu_ctl.scala 2492:50]
|
|
wire _T_2278 = io_dec_csr_wraddr_r == 12'hb86; // @[el2_dec_tlu_ctl.scala 2497:74]
|
|
wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2278; // @[el2_dec_tlu_ctl.scala 2497:45]
|
|
wire _T_2284 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[el2_dec_tlu_ctl.scala 2508:57]
|
|
wire _T_2286 = |io_dec_csr_wrdata_r[31:10]; // @[el2_dec_tlu_ctl.scala 2508:103]
|
|
wire _T_2287 = _T_2284 | _T_2286; // @[el2_dec_tlu_ctl.scala 2508:72]
|
|
wire _T_2290 = io_dec_csr_wraddr_r == 12'h323; // @[el2_dec_tlu_ctl.scala 2510:71]
|
|
wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2290; // @[el2_dec_tlu_ctl.scala 2510:42]
|
|
wire _T_2294 = io_dec_csr_wraddr_r == 12'h324; // @[el2_dec_tlu_ctl.scala 2517:71]
|
|
wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2294; // @[el2_dec_tlu_ctl.scala 2517:42]
|
|
wire _T_2298 = io_dec_csr_wraddr_r == 12'h325; // @[el2_dec_tlu_ctl.scala 2524:71]
|
|
wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2298; // @[el2_dec_tlu_ctl.scala 2524:42]
|
|
wire _T_2302 = io_dec_csr_wraddr_r == 12'h326; // @[el2_dec_tlu_ctl.scala 2531:71]
|
|
wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2302; // @[el2_dec_tlu_ctl.scala 2531:42]
|
|
wire _T_2306 = io_dec_csr_wraddr_r == 12'h320; // @[el2_dec_tlu_ctl.scala 2548:78]
|
|
wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2306; // @[el2_dec_tlu_ctl.scala 2548:49]
|
|
wire _T_2318 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 2563:52]
|
|
wire _T_2319 = _T_2318 | io_interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 2563:79]
|
|
wire _T_2320 = _T_2319 | io_dec_tlu_i0_valid_wb1; // @[el2_dec_tlu_ctl.scala 2563:105]
|
|
wire _T_2321 = _T_2320 | io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec_tlu_ctl.scala 2563:131]
|
|
wire _T_2322 = _T_2321 | io_dec_tlu_int_valid_wb1; // @[el2_dec_tlu_ctl.scala 2564:33]
|
|
reg _T_2325; // @[el2_dec_tlu_ctl.scala 2566:63]
|
|
wire _T_2326 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 2567:92]
|
|
wire _T_2327 = ~io_trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 2567:138]
|
|
wire _T_2328 = io_trigger_hit_r_d1 & _T_2327; // @[el2_dec_tlu_ctl.scala 2567:136]
|
|
reg _T_2330; // @[el2_dec_tlu_ctl.scala 2567:63]
|
|
reg [4:0] _T_2331; // @[el2_dec_tlu_ctl.scala 2568:63]
|
|
reg _T_2332; // @[el2_dec_tlu_ctl.scala 2569:63]
|
|
wire [31:0] _T_2338 = {io_core_id,4'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2347 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2352 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2365 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2378 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2390 = {io_mepc,1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2395 = {28'h0,mscause}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2403 = {meivt,10'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2409 = {28'h0,meicurpl}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2412 = {28'h0,meicidpl}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2415 = {28'h0,meipt}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2418 = {23'h0,mcgc}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2421 = {13'h0,_T_348,4'h0,mfdc_int[11:7],_T_351,mfdc_int[5:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2425 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2427 = {io_dpc,1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2443 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2446 = {30'h0,mtsel}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2475 = {26'h0,mfdht}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2478 = {30'h0,mfdhs}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2481 = {22'h0,mhpme3}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2484 = {22'h0,mhpme4}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2487 = {22'h0,mhpme5}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2490 = {22'h0,mhpme6}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2493 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2496 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2499 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2500 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2501 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2502 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2503 = io_csr_pkt_csr_mhartid ? _T_2338 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2504 = io_csr_pkt_csr_mstatus ? _T_2347 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2505 = io_csr_pkt_csr_mtvec ? _T_2352 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2506 = io_csr_pkt_csr_mip ? _T_2365 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2507 = io_csr_pkt_csr_mie ? _T_2378 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2508 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2509 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2510 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2511 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2512 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2513 = io_csr_pkt_csr_mepc ? _T_2390 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2514 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2515 = io_csr_pkt_csr_mscause ? _T_2395 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2516 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2517 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2518 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2519 = io_csr_pkt_csr_meivt ? _T_2403 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2520 = io_csr_pkt_csr_meihap ? _T_615 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2521 = io_csr_pkt_csr_meicurpl ? _T_2409 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2522 = io_csr_pkt_csr_meicidpl ? _T_2412 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2523 = io_csr_pkt_csr_meipt ? _T_2415 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2524 = io_csr_pkt_csr_mcgc ? _T_2418 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2525 = io_csr_pkt_csr_mfdc ? _T_2421 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2526 = io_csr_pkt_csr_dcsr ? _T_2425 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2527 = io_csr_pkt_csr_dpc ? _T_2427 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2528 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2529 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2530 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2531 = io_csr_pkt_csr_dicawics ? _T_2443 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2532 = io_csr_pkt_csr_mtsel ? _T_2446 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2533 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2534 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2535 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2536 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2537 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2541 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2542 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2546 = io_csr_pkt_csr_mfdht ? _T_2475 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2547 = io_csr_pkt_csr_mfdhs ? _T_2478 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2548 = io_csr_pkt_csr_mhpme3 ? _T_2481 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2549 = io_csr_pkt_csr_mhpme4 ? _T_2484 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2550 = io_csr_pkt_csr_mhpme5 ? _T_2487 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2551 = io_csr_pkt_csr_mhpme6 ? _T_2490 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2552 = io_csr_pkt_csr_mcountinhibit ? _T_2493 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2553 = io_csr_pkt_csr_mpmc ? _T_2496 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2554 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2555 = _T_2499 | _T_2500; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2564 = _T_2563 | _T_2509; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2565 = _T_2564 | _T_2510; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2566 = _T_2565 | _T_2511; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2567 = _T_2566 | _T_2512; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2568 = _T_2567 | _T_2513; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2569 = _T_2568 | _T_2514; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2570 = _T_2569 | _T_2515; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2571 = _T_2570 | _T_2516; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2572 = _T_2571 | _T_2517; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2573 = _T_2572 | _T_2518; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2574 = _T_2573 | _T_2519; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2575 = _T_2574 | _T_2520; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2576 = _T_2575 | _T_2521; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2577 = _T_2576 | _T_2522; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2578 = _T_2577 | _T_2523; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2579 = _T_2578 | _T_2524; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2580 = _T_2579 | _T_2525; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2581 = _T_2580 | _T_2526; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2582 = _T_2581 | _T_2527; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2583 = _T_2582 | _T_2528; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2584 = _T_2583 | _T_2529; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2585 = _T_2584 | _T_2530; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2586 = _T_2585 | _T_2531; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2587 = _T_2586 | _T_2532; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2588 = _T_2587 | _T_2533; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2589 = _T_2588 | _T_2534; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2590 = _T_2589 | _T_2535; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2591 = _T_2590 | _T_2536; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2592 = _T_2591 | _T_2537; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2593 = _T_2592 | _T_2538; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2594 = _T_2593 | _T_2539; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2595 = _T_2594 | _T_2540; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2596 = _T_2595 | _T_2541; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2597 = _T_2596 | _T_2542; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2598 = _T_2597 | _T_2543; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2599 = _T_2598 | _T_2544; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2600 = _T_2599 | _T_2545; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2601 = _T_2600 | _T_2546; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2602 = _T_2601 | _T_2547; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en),
|
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en),
|
|
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_8_io_l1clk),
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en),
|
|
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_9_io_l1clk),
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en),
|
|
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_10_io_l1clk),
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en),
|
|
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_11_io_l1clk),
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en),
|
|
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_12_io_l1clk),
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en),
|
|
.io_scan_mode(rvclkhdr_12_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_13_io_l1clk),
|
|
.io_clk(rvclkhdr_13_io_clk),
|
|
.io_en(rvclkhdr_13_io_en),
|
|
.io_scan_mode(rvclkhdr_13_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_14_io_l1clk),
|
|
.io_clk(rvclkhdr_14_io_clk),
|
|
.io_en(rvclkhdr_14_io_en),
|
|
.io_scan_mode(rvclkhdr_14_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_15_io_l1clk),
|
|
.io_clk(rvclkhdr_15_io_clk),
|
|
.io_en(rvclkhdr_15_io_en),
|
|
.io_scan_mode(rvclkhdr_15_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_16_io_l1clk),
|
|
.io_clk(rvclkhdr_16_io_clk),
|
|
.io_en(rvclkhdr_16_io_en),
|
|
.io_scan_mode(rvclkhdr_16_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_17_io_l1clk),
|
|
.io_clk(rvclkhdr_17_io_clk),
|
|
.io_en(rvclkhdr_17_io_en),
|
|
.io_scan_mode(rvclkhdr_17_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_18_io_l1clk),
|
|
.io_clk(rvclkhdr_18_io_clk),
|
|
.io_en(rvclkhdr_18_io_en),
|
|
.io_scan_mode(rvclkhdr_18_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_19_io_l1clk),
|
|
.io_clk(rvclkhdr_19_io_clk),
|
|
.io_en(rvclkhdr_19_io_en),
|
|
.io_scan_mode(rvclkhdr_19_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_20_io_l1clk),
|
|
.io_clk(rvclkhdr_20_io_clk),
|
|
.io_en(rvclkhdr_20_io_en),
|
|
.io_scan_mode(rvclkhdr_20_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_21_io_l1clk),
|
|
.io_clk(rvclkhdr_21_io_clk),
|
|
.io_en(rvclkhdr_21_io_en),
|
|
.io_scan_mode(rvclkhdr_21_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_22_io_l1clk),
|
|
.io_clk(rvclkhdr_22_io_clk),
|
|
.io_en(rvclkhdr_22_io_en),
|
|
.io_scan_mode(rvclkhdr_22_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_23_io_l1clk),
|
|
.io_clk(rvclkhdr_23_io_clk),
|
|
.io_en(rvclkhdr_23_io_en),
|
|
.io_scan_mode(rvclkhdr_23_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_24_io_l1clk),
|
|
.io_clk(rvclkhdr_24_io_clk),
|
|
.io_en(rvclkhdr_24_io_en),
|
|
.io_scan_mode(rvclkhdr_24_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_25_io_l1clk),
|
|
.io_clk(rvclkhdr_25_io_clk),
|
|
.io_en(rvclkhdr_25_io_en),
|
|
.io_scan_mode(rvclkhdr_25_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_26_io_l1clk),
|
|
.io_clk(rvclkhdr_26_io_clk),
|
|
.io_en(rvclkhdr_26_io_en),
|
|
.io_scan_mode(rvclkhdr_26_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_27_io_l1clk),
|
|
.io_clk(rvclkhdr_27_io_clk),
|
|
.io_en(rvclkhdr_27_io_en),
|
|
.io_scan_mode(rvclkhdr_27_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_28_io_l1clk),
|
|
.io_clk(rvclkhdr_28_io_clk),
|
|
.io_en(rvclkhdr_28_io_en),
|
|
.io_scan_mode(rvclkhdr_28_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_29_io_l1clk),
|
|
.io_clk(rvclkhdr_29_io_clk),
|
|
.io_en(rvclkhdr_29_io_en),
|
|
.io_scan_mode(rvclkhdr_29_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_30_io_l1clk),
|
|
.io_clk(rvclkhdr_30_io_clk),
|
|
.io_en(rvclkhdr_30_io_en),
|
|
.io_scan_mode(rvclkhdr_30_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_31 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_31_io_l1clk),
|
|
.io_clk(rvclkhdr_31_io_clk),
|
|
.io_en(rvclkhdr_31_io_en),
|
|
.io_scan_mode(rvclkhdr_31_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_32 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_32_io_l1clk),
|
|
.io_clk(rvclkhdr_32_io_clk),
|
|
.io_en(rvclkhdr_32_io_en),
|
|
.io_scan_mode(rvclkhdr_32_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_33 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_33_io_l1clk),
|
|
.io_clk(rvclkhdr_33_io_clk),
|
|
.io_en(rvclkhdr_33_io_en),
|
|
.io_scan_mode(rvclkhdr_33_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_34 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_34_io_l1clk),
|
|
.io_clk(rvclkhdr_34_io_clk),
|
|
.io_en(rvclkhdr_34_io_en),
|
|
.io_scan_mode(rvclkhdr_34_io_scan_mode)
|
|
);
|
|
assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_762,dicad0[31:0]}; // @[el2_dec_tlu_ctl.scala 2232:65]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[el2_dec_tlu_ctl.scala 2235:42]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[el2_dec_tlu_ctl.scala 2243:42]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[el2_dec_tlu_ctl.scala 2244:42]
|
|
assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[el2_dec_tlu_ctl.scala 2308:36]
|
|
assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[el2_dec_tlu_ctl.scala 2309:39]
|
|
assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[el2_dec_tlu_ctl.scala 2310:36]
|
|
assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[el2_dec_tlu_ctl.scala 2311:36]
|
|
assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[el2_dec_tlu_ctl.scala 2312:36]
|
|
assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[el2_dec_tlu_ctl.scala 2313:36]
|
|
assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[el2_dec_tlu_ctl.scala 2326:53]
|
|
assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[el2_dec_tlu_ctl.scala 2308:36]
|
|
assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[el2_dec_tlu_ctl.scala 2309:39]
|
|
assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[el2_dec_tlu_ctl.scala 2310:36]
|
|
assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[el2_dec_tlu_ctl.scala 2311:36]
|
|
assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[el2_dec_tlu_ctl.scala 2312:36]
|
|
assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[el2_dec_tlu_ctl.scala 2313:36]
|
|
assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[el2_dec_tlu_ctl.scala 2326:53]
|
|
assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[el2_dec_tlu_ctl.scala 2308:36]
|
|
assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[el2_dec_tlu_ctl.scala 2309:39]
|
|
assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[el2_dec_tlu_ctl.scala 2310:36]
|
|
assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[el2_dec_tlu_ctl.scala 2311:36]
|
|
assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[el2_dec_tlu_ctl.scala 2312:36]
|
|
assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[el2_dec_tlu_ctl.scala 2313:36]
|
|
assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[el2_dec_tlu_ctl.scala 2326:53]
|
|
assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[el2_dec_tlu_ctl.scala 2308:36]
|
|
assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[el2_dec_tlu_ctl.scala 2309:39]
|
|
assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[el2_dec_tlu_ctl.scala 2310:36]
|
|
assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[el2_dec_tlu_ctl.scala 2311:36]
|
|
assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[el2_dec_tlu_ctl.scala 2312:36]
|
|
assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[el2_dec_tlu_ctl.scala 2313:36]
|
|
assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[el2_dec_tlu_ctl.scala 2326:53]
|
|
assign io_dec_tlu_int_valid_wb1 = _T_2332; // @[el2_dec_tlu_ctl.scala 2569:31]
|
|
assign io_dec_tlu_i0_exc_valid_wb1 = _T_2330; // @[el2_dec_tlu_ctl.scala 2567:31]
|
|
assign io_dec_tlu_i0_valid_wb1 = _T_2325; // @[el2_dec_tlu_ctl.scala 2566:31]
|
|
assign io_dec_tlu_mtval_wb1 = mtval; // @[el2_dec_tlu_ctl.scala 2571:25]
|
|
assign io_dec_tlu_exc_cause_wb1 = _T_2331; // @[el2_dec_tlu_ctl.scala 2568:31]
|
|
assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2177; // @[el2_dec_tlu_ctl.scala 2423:23]
|
|
assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2182; // @[el2_dec_tlu_ctl.scala 2424:23]
|
|
assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2187; // @[el2_dec_tlu_ctl.scala 2425:23]
|
|
assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2192; // @[el2_dec_tlu_ctl.scala 2426:23]
|
|
assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[el2_dec_tlu_ctl.scala 1797:32]
|
|
assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[el2_dec_tlu_ctl.scala 1798:32]
|
|
assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[el2_dec_tlu_ctl.scala 1800:32]
|
|
assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[el2_dec_tlu_ctl.scala 1802:32]
|
|
assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[el2_dec_tlu_ctl.scala 1803:32]
|
|
assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[el2_dec_tlu_ctl.scala 1804:32]
|
|
assign io_dec_csr_rddata_d = _T_2608 | _T_2554; // @[el2_dec_tlu_ctl.scala 2576:22]
|
|
assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[el2_dec_tlu_ctl.scala 1847:40]
|
|
assign io_dec_tlu_wr_pause_r = _T_368 & _T_369; // @[el2_dec_tlu_ctl.scala 1856:25]
|
|
assign io_dec_tlu_meipt = meipt; // @[el2_dec_tlu_ctl.scala 2083:20]
|
|
assign io_dec_tlu_meicurpl = meicurpl; // @[el2_dec_tlu_ctl.scala 2047:23]
|
|
assign io_dec_tlu_meihap = _T_615[29:0]; // @[el2_dec_tlu_ctl.scala 2033:21]
|
|
assign io_dec_tlu_mrac_ff = mrac; // @[el2_dec_tlu_ctl.scala 1886:22]
|
|
assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[el2_dec_tlu_ctl.scala 1846:40]
|
|
assign io_dec_tlu_bpred_disable = mfdc[3]; // @[el2_dec_tlu_ctl.scala 1845:40]
|
|
assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[el2_dec_tlu_ctl.scala 1844:40]
|
|
assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[el2_dec_tlu_ctl.scala 1843:40]
|
|
assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[el2_dec_tlu_ctl.scala 1842:40]
|
|
assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[el2_dec_tlu_ctl.scala 1841:40]
|
|
assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[el2_dec_tlu_ctl.scala 1530:24]
|
|
assign io_fw_halt_req = _T_500 & _T_501; // @[el2_dec_tlu_ctl.scala 1921:18]
|
|
assign io_mstatus = _T_54; // @[el2_dec_tlu_ctl.scala 1546:14]
|
|
assign io_mstatus_mie_ns = io_mstatus[0] & _T_52; // @[el2_dec_tlu_ctl.scala 1545:21]
|
|
assign io_dcsr = _T_700; // @[el2_dec_tlu_ctl.scala 2130:11]
|
|
assign io_mtvec = _T_60; // @[el2_dec_tlu_ctl.scala 1558:12]
|
|
assign io_mip = _T_66; // @[el2_dec_tlu_ctl.scala 1573:10]
|
|
assign io_mie_ns = wr_mie_r ? _T_76 : mie; // @[el2_dec_tlu_ctl.scala 1587:13]
|
|
assign io_npc_r = _T_159 | _T_157; // @[el2_dec_tlu_ctl.scala 1681:12]
|
|
assign io_npc_r_d1 = _T_165; // @[el2_dec_tlu_ctl.scala 1687:15]
|
|
assign io_mepc = _T_194; // @[el2_dec_tlu_ctl.scala 1706:11]
|
|
assign io_mdseac_locked_ns = mdseac_en | _T_487; // @[el2_dec_tlu_ctl.scala 1904:23]
|
|
assign io_force_halt = mfdht[0] & _T_607; // @[el2_dec_tlu_ctl.scala 2010:17]
|
|
assign io_dpc = _T_725; // @[el2_dec_tlu_ctl.scala 2147:10]
|
|
assign io_mtdata1_t_0 = _T_871; // @[el2_dec_tlu_ctl.scala 2303:41]
|
|
assign io_mtdata1_t_1 = _T_872; // @[el2_dec_tlu_ctl.scala 2303:41]
|
|
assign io_mtdata1_t_2 = _T_873; // @[el2_dec_tlu_ctl.scala 2303:41]
|
|
assign io_mtdata1_t_3 = _T_874; // @[el2_dec_tlu_ctl.scala 2303:41]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_56; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = wr_mcyclel_r | mcyclel_cout_in; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_2_io_en = wr_mcycleh_r | mcyclel_cout_f; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = i0_valid_no_ebreak_ecall_r | wr_minstretl_r; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_4_io_en = minstret_enable_f | wr_minstreth_r; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_5_io_en = io_dec_csr_wen_r_mod & _T_137; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_6_io_en = _T_162 | io_reset_delayed; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_7_io_en = _T_140 & io_dec_tlu_i0_valid_r; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_8_io_en = io_dec_csr_wen_r_mod & _T_323; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_335; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_372; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_11_io_en = _T_491 & _T_492; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_13_io_en = _T_547 | io_iccm_dma_sb_error; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_610; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_16_io_en = _T_631 | io_take_ext_int_start; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_17_io_en = _T_697 | io_take_nmi; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_18_io_en = _T_722 | dpc_capture_npc; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_19_io_en = _T_662 & _T_732; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_22_io_en = _T_970 & _T_806; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_23_io_en = _T_979 & _T_815; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_24_io_en = _T_988 & _T_824; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_25_io_en = _T_997 & _T_833; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_27_io_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_28_io_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_29_io_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_30_io_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_31_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_31_io_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_32_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_32_io_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_33_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_34_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_34_io_en = _T_2322 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
mpmc_b = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_54 = _RAND_1[1:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
_T_60 = _RAND_2[30:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
mdccmect = _RAND_3[31:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
miccmect = _RAND_4[31:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
micect = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_66 = _RAND_6[5:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
mie = _RAND_7[5:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
temp_ncount6_2 = _RAND_8[4:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
temp_ncount0 = _RAND_9[0:0];
|
|
_RAND_10 = {2{`RANDOM}};
|
|
_T_95 = _RAND_10[32:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
mcyclel_cout_f = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
mcycleh = _RAND_12[31:0];
|
|
_RAND_13 = {2{`RANDOM}};
|
|
_T_122 = _RAND_13[32:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
minstret_enable_f = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
minstretl_cout_f = _RAND_15[0:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
minstreth = _RAND_16[31:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
mscratch = _RAND_17[31:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
_T_165 = _RAND_18[30:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
pc_r_d1 = _RAND_19[30:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
_T_194 = _RAND_20[30:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
mcause = _RAND_21[31:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
mscause = _RAND_22[3:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
mtval = _RAND_23[31:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
mcgc = _RAND_24[8:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
mfdc_int = _RAND_25[14:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
mrac = _RAND_26[31:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
mdseac = _RAND_27[31:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
mfdht = _RAND_28[5:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
mfdhs = _RAND_29[1:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
force_halt_ctr_f = _RAND_30[31:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
meivt = _RAND_31[21:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
meihap = _RAND_32[7:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
meicurpl = _RAND_33[3:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
meicidpl = _RAND_34[3:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
meipt = _RAND_35[3:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
_T_700 = _RAND_36[15:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
_T_725 = _RAND_37[30:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
dicawics = _RAND_38[16:0];
|
|
_RAND_39 = {3{`RANDOM}};
|
|
dicad0 = _RAND_39[70:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
dicad0h = _RAND_40[31:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
_T_757 = _RAND_41[31:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
icache_rd_valid_f = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
icache_wr_valid_f = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
mtsel = _RAND_44[1:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
_T_871 = _RAND_45[9:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
_T_872 = _RAND_46[9:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
_T_873 = _RAND_47[9:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
_T_874 = _RAND_48[9:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
mtdata2_t_0 = _RAND_49[31:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
mtdata2_t_1 = _RAND_50[31:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
mtdata2_t_2 = _RAND_51[31:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
mtdata2_t_3 = _RAND_52[31:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
mhpme3 = _RAND_53[9:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
mhpme4 = _RAND_54[9:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
mhpme5 = _RAND_55[9:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
mhpme6 = _RAND_56[9:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
mhpmc_inc_r_d1_0 = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
mhpmc_inc_r_d1_1 = _RAND_58[0:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
mhpmc_inc_r_d1_2 = _RAND_59[0:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
mhpmc_inc_r_d1_3 = _RAND_60[0:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
perfcnt_halted_d1 = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
mhpmc3h = _RAND_62[31:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
mhpmc3 = _RAND_63[31:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
mhpmc4h = _RAND_64[31:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
mhpmc4 = _RAND_65[31:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
mhpmc5h = _RAND_66[31:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
mhpmc5 = _RAND_67[31:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
mhpmc6h = _RAND_68[31:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
mhpmc6 = _RAND_69[31:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
_T_2325 = _RAND_70[0:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
_T_2330 = _RAND_71[0:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
_T_2331 = _RAND_72[4:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
_T_2332 = _RAND_73[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
mpmc_b = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_54 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_60 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
mdccmect = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
miccmect = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
micect = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_66 = 6'h0;
|
|
end
|
|
if (reset) begin
|
|
mie = 6'h0;
|
|
end
|
|
if (reset) begin
|
|
temp_ncount6_2 = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
temp_ncount0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_95 = 33'h0;
|
|
end
|
|
if (reset) begin
|
|
mcyclel_cout_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mcycleh = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_122 = 33'h0;
|
|
end
|
|
if (reset) begin
|
|
minstret_enable_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
minstretl_cout_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
minstreth = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mscratch = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_165 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
pc_r_d1 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_194 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
mcause = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mscause = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
mtval = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mcgc = 9'h0;
|
|
end
|
|
if (reset) begin
|
|
mfdc_int = 15'h0;
|
|
end
|
|
if (reset) begin
|
|
mrac = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mdseac = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mfdht = 6'h0;
|
|
end
|
|
if (reset) begin
|
|
mfdhs = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
force_halt_ctr_f = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
meivt = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
meihap = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
meicurpl = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
meicidpl = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
meipt = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_700 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_725 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
dicawics = 17'h0;
|
|
end
|
|
if (reset) begin
|
|
dicad0 = 71'h0;
|
|
end
|
|
if (reset) begin
|
|
dicad0h = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_757 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
icache_rd_valid_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
icache_wr_valid_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mtsel = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_871 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_872 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_873 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_874 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
mtdata2_t_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mtdata2_t_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mtdata2_t_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mtdata2_t_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpme3 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpme4 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpme5 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpme6 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc_inc_r_d1_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc_inc_r_d1_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc_inc_r_d1_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc_inc_r_d1_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
perfcnt_halted_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc3h = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc4h = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc4 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc5h = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc5 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc6h = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mhpmc6 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_2325 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_2330 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_2331 = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_2332 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpmc_b <= 1'h0;
|
|
end else if (wr_mpmc_r) begin
|
|
mpmc_b <= _T_507;
|
|
end else begin
|
|
mpmc_b <= _T_508;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_54 <= 2'h0;
|
|
end else begin
|
|
_T_54 <= _T_46 | _T_42;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_60 <= 31'h0;
|
|
end else begin
|
|
_T_60 <= {io_dec_csr_wrdata_r[31:2],io_dec_csr_wrdata_r[0]};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mdccmect <= 32'h0;
|
|
end else if (wr_mdccmect_r) begin
|
|
mdccmect <= _T_523;
|
|
end else begin
|
|
mdccmect <= _T_567;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
miccmect <= 32'h0;
|
|
end else if (wr_miccmect_r) begin
|
|
miccmect <= _T_523;
|
|
end else begin
|
|
miccmect <= _T_546;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
micect <= 32'h0;
|
|
end else if (wr_micect_r) begin
|
|
micect <= _T_523;
|
|
end else begin
|
|
micect <= _T_525;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_66 <= 6'h0;
|
|
end else begin
|
|
_T_66 <= {_T_65,_T_63};
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mie <= 6'h0;
|
|
end else begin
|
|
mie <= io_mie_ns;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
temp_ncount6_2 <= 5'h0;
|
|
end else if (wr_mcountinhibit_r) begin
|
|
temp_ncount6_2 <= io_dec_csr_wrdata_r[6:2];
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
temp_ncount0 <= 1'h0;
|
|
end else if (wr_mcountinhibit_r) begin
|
|
temp_ncount0 <= io_dec_csr_wrdata_r[0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_95 <= 33'h0;
|
|
end else if (wr_mcyclel_r) begin
|
|
_T_95 <= {{1'd0}, io_dec_csr_wrdata_r};
|
|
end else begin
|
|
_T_95 <= mcyclel_inc;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mcyclel_cout_f <= 1'h0;
|
|
end else begin
|
|
mcyclel_cout_f <= mcyclel_cout & _T_96;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mcycleh <= 32'h0;
|
|
end else if (wr_mcycleh_r) begin
|
|
mcycleh <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mcycleh <= mcycleh_inc;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_122 <= 33'h0;
|
|
end else if (wr_minstretl_r) begin
|
|
_T_122 <= {{1'd0}, io_dec_csr_wrdata_r};
|
|
end else begin
|
|
_T_122 <= minstretl_inc;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
minstret_enable_f <= 1'h0;
|
|
end else begin
|
|
minstret_enable_f <= i0_valid_no_ebreak_ecall_r | wr_minstretl_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
minstretl_cout_f <= 1'h0;
|
|
end else begin
|
|
minstretl_cout_f <= minstretl_cout & _T_123;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
minstreth <= 32'h0;
|
|
end else if (wr_minstreth_r) begin
|
|
minstreth <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
minstreth <= minstreth_inc;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mscratch <= 32'h0;
|
|
end else begin
|
|
mscratch <= io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_165 <= 31'h0;
|
|
end else begin
|
|
_T_165 <= io_npc_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
pc_r_d1 <= 31'h0;
|
|
end else begin
|
|
pc_r_d1 <= _T_169 | _T_170;
|
|
end
|
|
end
|
|
always @(posedge io_e4e5_int_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_194 <= 31'h0;
|
|
end else begin
|
|
_T_194 <= _T_192 | _T_190;
|
|
end
|
|
end
|
|
always @(posedge io_e4e5_int_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mcause <= 32'h0;
|
|
end else begin
|
|
mcause <= _T_232 | _T_228;
|
|
end
|
|
end
|
|
always @(posedge io_e4e5_int_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mscause <= 4'h0;
|
|
end else begin
|
|
mscause <= _T_262 | _T_261;
|
|
end
|
|
end
|
|
always @(posedge io_e4e5_int_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mtval <= 32'h0;
|
|
end else begin
|
|
mtval <= _T_319 | _T_315;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mcgc <= 9'h0;
|
|
end else begin
|
|
mcgc <= io_dec_csr_wrdata_r[8:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mfdc_int <= 15'h0;
|
|
end else begin
|
|
mfdc_int <= {_T_345,_T_344};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mrac <= 32'h0;
|
|
end else begin
|
|
mrac <= {_T_482,_T_467};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mdseac <= 32'h0;
|
|
end else begin
|
|
mdseac <= io_lsu_imprecise_error_addr_any;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mfdht <= 6'h0;
|
|
end else if (wr_mfdht_r) begin
|
|
mfdht <= io_dec_csr_wrdata_r[5:0];
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mfdhs <= 2'h0;
|
|
end else if (_T_593) begin
|
|
if (wr_mfdhs_r) begin
|
|
mfdhs <= io_dec_csr_wrdata_r[1:0];
|
|
end else if (_T_587) begin
|
|
mfdhs <= _T_591;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
force_halt_ctr_f <= 32'h0;
|
|
end else if (mfdht[0]) begin
|
|
if (io_debug_halt_req_f) begin
|
|
force_halt_ctr_f <= _T_598;
|
|
end else if (io_dbg_tlu_halted_f) begin
|
|
force_halt_ctr_f <= 32'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
meivt <= 22'h0;
|
|
end else begin
|
|
meivt <= io_dec_csr_wrdata_r[31:10];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
meihap <= 8'h0;
|
|
end else begin
|
|
meihap <= io_pic_claimid;
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
meicurpl <= 4'h0;
|
|
end else if (wr_meicurpl_r) begin
|
|
meicurpl <= io_dec_csr_wrdata_r[3:0];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
meicidpl <= 4'h0;
|
|
end else if (wr_meicpct_r) begin
|
|
meicidpl <= io_pic_pl;
|
|
end else if (wr_meicidpl_r) begin
|
|
meicidpl <= io_dec_csr_wrdata_r[3:0];
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
meipt <= 4'h0;
|
|
end else if (wr_meipt_r) begin
|
|
meipt <= io_dec_csr_wrdata_r[3:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_700 <= 16'h0;
|
|
end else if (enter_debug_halt_req_le) begin
|
|
_T_700 <= _T_674;
|
|
end else if (wr_dcsr_r) begin
|
|
_T_700 <= _T_689;
|
|
end else begin
|
|
_T_700 <= _T_694;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_725 <= 31'h0;
|
|
end else begin
|
|
_T_725 <= _T_720 | _T_719;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
dicawics <= 17'h0;
|
|
end else begin
|
|
dicawics <= {_T_729,io_dec_csr_wrdata_r[16:3]};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
dicad0 <= 71'h0;
|
|
end else if (wr_dicad0_r) begin
|
|
dicad0 <= {{39'd0}, io_dec_csr_wrdata_r};
|
|
end else begin
|
|
dicad0 <= io_ifu_ic_debug_rd_data;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
dicad0h <= 32'h0;
|
|
end else if (wr_dicad0h_r) begin
|
|
dicad0h <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
dicad0h <= io_ifu_ic_debug_rd_data[63:32];
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_757 <= 32'h0;
|
|
end else if (_T_755) begin
|
|
if (_T_751) begin
|
|
_T_757 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
_T_757 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]};
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
icache_rd_valid_f <= 1'h0;
|
|
end else begin
|
|
icache_rd_valid_f <= _T_767 & _T_769;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
icache_wr_valid_f <= 1'h0;
|
|
end else begin
|
|
icache_wr_valid_f <= _T_662 & _T_772;
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mtsel <= 2'h0;
|
|
end else if (wr_mtsel_r) begin
|
|
mtsel <= io_dec_csr_wrdata_r[1:0];
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_871 <= 10'h0;
|
|
end else if (wr_mtdata1_t_r_0) begin
|
|
_T_871 <= tdata_wrdata_r;
|
|
end else begin
|
|
_T_871 <= _T_842;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_872 <= 10'h0;
|
|
end else if (wr_mtdata1_t_r_1) begin
|
|
_T_872 <= tdata_wrdata_r;
|
|
end else begin
|
|
_T_872 <= _T_851;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_873 <= 10'h0;
|
|
end else if (wr_mtdata1_t_r_2) begin
|
|
_T_873 <= tdata_wrdata_r;
|
|
end else begin
|
|
_T_873 <= _T_860;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_874 <= 10'h0;
|
|
end else if (wr_mtdata1_t_r_3) begin
|
|
_T_874 <= tdata_wrdata_r;
|
|
end else begin
|
|
_T_874 <= _T_869;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mtdata2_t_0 <= 32'h0;
|
|
end else begin
|
|
mtdata2_t_0 <= io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mtdata2_t_1 <= 32'h0;
|
|
end else begin
|
|
mtdata2_t_1 <= io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mtdata2_t_2 <= 32'h0;
|
|
end else begin
|
|
mtdata2_t_2 <= io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mtdata2_t_3 <= 32'h0;
|
|
end else begin
|
|
mtdata2_t_3 <= io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpme3 <= 10'h0;
|
|
end else if (wr_mhpme3_r) begin
|
|
if (_T_2287) begin
|
|
mhpme3 <= 10'h204;
|
|
end else begin
|
|
mhpme3 <= io_dec_csr_wrdata_r[9:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpme4 <= 10'h0;
|
|
end else if (wr_mhpme4_r) begin
|
|
if (_T_2287) begin
|
|
mhpme4 <= 10'h204;
|
|
end else begin
|
|
mhpme4 <= io_dec_csr_wrdata_r[9:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpme5 <= 10'h0;
|
|
end else if (wr_mhpme5_r) begin
|
|
if (_T_2287) begin
|
|
mhpme5 <= 10'h204;
|
|
end else begin
|
|
mhpme5 <= io_dec_csr_wrdata_r[9:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpme6 <= 10'h0;
|
|
end else if (wr_mhpme6_r) begin
|
|
if (_T_2287) begin
|
|
mhpme6 <= 10'h204;
|
|
end else begin
|
|
mhpme6 <= io_dec_csr_wrdata_r[9:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc_inc_r_d1_0 <= 1'h0;
|
|
end else begin
|
|
mhpmc_inc_r_d1_0 <= _T_1305[0];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc_inc_r_d1_1 <= 1'h0;
|
|
end else begin
|
|
mhpmc_inc_r_d1_1 <= _T_1588[0];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc_inc_r_d1_2 <= 1'h0;
|
|
end else begin
|
|
mhpmc_inc_r_d1_2 <= _T_1871[0];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc_inc_r_d1_3 <= 1'h0;
|
|
end else begin
|
|
mhpmc_inc_r_d1_3 <= _T_2154[0];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
perfcnt_halted_d1 <= 1'h0;
|
|
end else begin
|
|
perfcnt_halted_d1 <= _T_83 | io_dec_tlu_pmu_fw_halted;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc3h <= 32'h0;
|
|
end else if (mhpmc3h_wr_en0) begin
|
|
mhpmc3h <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mhpmc3h <= mhpmc3_incr[63:32];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc3 <= 32'h0;
|
|
end else if (mhpmc3_wr_en0) begin
|
|
mhpmc3 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mhpmc3 <= mhpmc3_incr[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc4h <= 32'h0;
|
|
end else if (mhpmc4h_wr_en0) begin
|
|
mhpmc4h <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mhpmc4h <= mhpmc4_incr[63:32];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc4 <= 32'h0;
|
|
end else if (mhpmc4_wr_en0) begin
|
|
mhpmc4 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mhpmc4 <= mhpmc4_incr[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc5h <= 32'h0;
|
|
end else if (mhpmc5h_wr_en0) begin
|
|
mhpmc5h <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mhpmc5h <= mhpmc5_incr[63:32];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc5 <= 32'h0;
|
|
end else if (mhpmc5_wr_en0) begin
|
|
mhpmc5 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mhpmc5 <= mhpmc5_incr[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_33_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc6h <= 32'h0;
|
|
end else if (mhpmc6h_wr_en0) begin
|
|
mhpmc6h <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mhpmc6h <= mhpmc6_incr[63:32];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_32_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mhpmc6 <= 32'h0;
|
|
end else if (mhpmc6_wr_en0) begin
|
|
mhpmc6 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mhpmc6 <= mhpmc6_incr[31:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_2325 <= 1'h0;
|
|
end else begin
|
|
_T_2325 <= io_i0_valid_wb;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_2330 <= 1'h0;
|
|
end else begin
|
|
_T_2330 <= _T_2326 | _T_2328;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_2331 <= 5'h0;
|
|
end else begin
|
|
_T_2331 <= io_exc_cause_wb;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_2332 <= 1'h0;
|
|
end else begin
|
|
_T_2332 <= io_interrupt_valid_r_d1;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_dec_decode_csr_read(
|
|
input [11:0] io_dec_csr_rdaddr_d,
|
|
output io_csr_pkt_csr_misa,
|
|
output io_csr_pkt_csr_mvendorid,
|
|
output io_csr_pkt_csr_marchid,
|
|
output io_csr_pkt_csr_mimpid,
|
|
output io_csr_pkt_csr_mhartid,
|
|
output io_csr_pkt_csr_mstatus,
|
|
output io_csr_pkt_csr_mtvec,
|
|
output io_csr_pkt_csr_mip,
|
|
output io_csr_pkt_csr_mie,
|
|
output io_csr_pkt_csr_mcyclel,
|
|
output io_csr_pkt_csr_mcycleh,
|
|
output io_csr_pkt_csr_minstretl,
|
|
output io_csr_pkt_csr_minstreth,
|
|
output io_csr_pkt_csr_mscratch,
|
|
output io_csr_pkt_csr_mepc,
|
|
output io_csr_pkt_csr_mcause,
|
|
output io_csr_pkt_csr_mscause,
|
|
output io_csr_pkt_csr_mtval,
|
|
output io_csr_pkt_csr_mrac,
|
|
output io_csr_pkt_csr_dmst,
|
|
output io_csr_pkt_csr_mdseac,
|
|
output io_csr_pkt_csr_meihap,
|
|
output io_csr_pkt_csr_meivt,
|
|
output io_csr_pkt_csr_meipt,
|
|
output io_csr_pkt_csr_meicurpl,
|
|
output io_csr_pkt_csr_meicidpl,
|
|
output io_csr_pkt_csr_dcsr,
|
|
output io_csr_pkt_csr_mcgc,
|
|
output io_csr_pkt_csr_mfdc,
|
|
output io_csr_pkt_csr_dpc,
|
|
output io_csr_pkt_csr_mtsel,
|
|
output io_csr_pkt_csr_mtdata1,
|
|
output io_csr_pkt_csr_mtdata2,
|
|
output io_csr_pkt_csr_mhpmc3,
|
|
output io_csr_pkt_csr_mhpmc4,
|
|
output io_csr_pkt_csr_mhpmc5,
|
|
output io_csr_pkt_csr_mhpmc6,
|
|
output io_csr_pkt_csr_mhpmc3h,
|
|
output io_csr_pkt_csr_mhpmc4h,
|
|
output io_csr_pkt_csr_mhpmc5h,
|
|
output io_csr_pkt_csr_mhpmc6h,
|
|
output io_csr_pkt_csr_mhpme3,
|
|
output io_csr_pkt_csr_mhpme4,
|
|
output io_csr_pkt_csr_mhpme5,
|
|
output io_csr_pkt_csr_mhpme6,
|
|
output io_csr_pkt_csr_mcountinhibit,
|
|
output io_csr_pkt_csr_mitctl0,
|
|
output io_csr_pkt_csr_mitctl1,
|
|
output io_csr_pkt_csr_mitb0,
|
|
output io_csr_pkt_csr_mitb1,
|
|
output io_csr_pkt_csr_mitcnt0,
|
|
output io_csr_pkt_csr_mitcnt1,
|
|
output io_csr_pkt_csr_mpmc,
|
|
output io_csr_pkt_csr_meicpct,
|
|
output io_csr_pkt_csr_micect,
|
|
output io_csr_pkt_csr_miccmect,
|
|
output io_csr_pkt_csr_mdccmect,
|
|
output io_csr_pkt_csr_mfdht,
|
|
output io_csr_pkt_csr_mfdhs,
|
|
output io_csr_pkt_csr_dicawics,
|
|
output io_csr_pkt_csr_dicad0h,
|
|
output io_csr_pkt_csr_dicad0,
|
|
output io_csr_pkt_csr_dicad1,
|
|
output io_csr_pkt_csr_dicago,
|
|
output io_csr_pkt_presync,
|
|
output io_csr_pkt_postsync,
|
|
output io_csr_pkt_legal
|
|
);
|
|
wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[el2_dec_tlu_ctl.scala 2648:123]
|
|
wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:123]
|
|
wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:123]
|
|
wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:123]
|
|
wire _T_9 = _T_1 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_10 = _T_9 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_11 = _T_10 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:123]
|
|
wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:123]
|
|
wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_20 = _T_19 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:159]
|
|
wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:123]
|
|
wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:123]
|
|
wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_102 = _T_101 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_103 = _T_102 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_104 = _T_103 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_120 = _T_119 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_121 = _T_120 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_122 = _T_121 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_123 = _T_122 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_138 = _T_15 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_139 = _T_138 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_140 = _T_139 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_141 = _T_140 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:123]
|
|
wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_157 = _T_156 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_158 = _T_157 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_159 = _T_158 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_172 = _T_75 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_173 = _T_172 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_182 = _T_75 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_218 = _T_217 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_219 = _T_218 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_220 = _T_219 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_231 = _T_230 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_241 = _T_240 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_260 = _T_259 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_261 = _T_260 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_269 = _T_268 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_310 = _T_300 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_331 = _T_330 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_332 = _T_331 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_382 = _T_381 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_397 = _T_103 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_411 = _T_15 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_412 = _T_411 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_413 = _T_412 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_427 = _T_426 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_428 = _T_427 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_444 = _T_119 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_445 = _T_444 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_447 = _T_446 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_461 = _T_460 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_491 = _T_490 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_492 = _T_491 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_493 = _T_492 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_506 = _T_505 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_508 = _T_507 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_553 = _T_493 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_564 = _T_563 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_585 = _T_563 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_615 = _T_614 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_625 = _T_624 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_668 = _T_196 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_669 = _T_668 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_716 = _T_1 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_718 = _T_717 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_719 = _T_718 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_738 = _T_737 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_748 = _T_726 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_787 = _T_311 | _T_553; // @[el2_dec_tlu_ctl.scala 2716:73]
|
|
wire _T_799 = _T_3 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_800 = _T_799 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_801 = _T_800 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_802 = _T_801 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_804 = _T_787 | _T_803; // @[el2_dec_tlu_ctl.scala 2716:113]
|
|
wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_814 = _T_813 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_816 = _T_815 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_817 = _T_804 | _T_816; // @[el2_dec_tlu_ctl.scala 2716:147]
|
|
wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_829 = _T_828 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_830 = _T_817 | _T_829; // @[el2_dec_tlu_ctl.scala 2717:41]
|
|
wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_842 = _T_841 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_843 = _T_842 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_844 = _T_843 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_869 = _T_311 | _T_70; // @[el2_dec_tlu_ctl.scala 2718:73]
|
|
wire _T_879 = _T_869 | _T_183; // @[el2_dec_tlu_ctl.scala 2718:113]
|
|
wire _T_889 = _T_879 | _T_342; // @[el2_dec_tlu_ctl.scala 2718:154]
|
|
wire _T_904 = _T_1 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_905 = _T_904 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_906 = _T_905 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_907 = _T_906 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_908 = _T_907 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_909 = _T_908 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_910 = _T_889 | _T_909; // @[el2_dec_tlu_ctl.scala 2719:41]
|
|
wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_923 = _T_922 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_924 = _T_923 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_925 = _T_924 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_926 = _T_910 | _T_925; // @[el2_dec_tlu_ctl.scala 2719:81]
|
|
wire _T_937 = _T_231 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_961 = _T_960 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_962 = _T_961 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_964 = _T_963 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_983 = _T_1 & _T_145; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_986 = _T_985 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_987 = _T_986 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_988 = _T_987 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_989 = _T_988 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_990 = _T_989 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_991 = _T_990 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_992 = _T_964 | _T_991; // @[el2_dec_tlu_ctl.scala 2721:73]
|
|
wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1014 = _T_1013 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1015 = _T_1014 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1016 = _T_992 | _T_1015; // @[el2_dec_tlu_ctl.scala 2721:121]
|
|
wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1036 = _T_1035 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1037 = _T_1036 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1038 = _T_1037 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1039 = _T_1038 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1040 = _T_1039 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1041 = _T_1016 | _T_1040; // @[el2_dec_tlu_ctl.scala 2722:57]
|
|
wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1056 = _T_1055 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1057 = _T_1056 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1058 = _T_1057 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1059 = _T_1041 | _T_1058; // @[el2_dec_tlu_ctl.scala 2722:105]
|
|
wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1084 = _T_1059 | _T_1083; // @[el2_dec_tlu_ctl.scala 2723:65]
|
|
wire _T_1105 = _T_1079 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1106 = _T_1105 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1107 = _T_1084 | _T_1106; // @[el2_dec_tlu_ctl.scala 2723:113]
|
|
wire _T_1125 = _T_1033 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1126 = _T_1125 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1127 = _T_1126 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1129 = _T_1128 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1130 = _T_1129 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1132 = _T_1107 | _T_1131; // @[el2_dec_tlu_ctl.scala 2724:57]
|
|
wire _T_1152 = _T_958 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1154 = _T_1153 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1155 = _T_1154 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1156 = _T_1155 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1157 = _T_1132 | _T_1156; // @[el2_dec_tlu_ctl.scala 2724:113]
|
|
wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1177 = _T_1157 | _T_1176; // @[el2_dec_tlu_ctl.scala 2725:57]
|
|
wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1203 = _T_1202 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1204 = _T_1203 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1205 = _T_1177 | _T_1204; // @[el2_dec_tlu_ctl.scala 2725:113]
|
|
wire _T_1224 = _T_959 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1225 = _T_1224 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1228 = _T_1205 | _T_1227; // @[el2_dec_tlu_ctl.scala 2726:57]
|
|
wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1249 = _T_1248 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1251 = _T_1228 | _T_1250; // @[el2_dec_tlu_ctl.scala 2726:113]
|
|
wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1276 = _T_1251 | _T_1275; // @[el2_dec_tlu_ctl.scala 2727:57]
|
|
wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1298 = _T_1276 | _T_1297; // @[el2_dec_tlu_ctl.scala 2727:113]
|
|
wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1316 = _T_1315 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1317 = _T_1316 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1319 = _T_1318 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1320 = _T_1298 | _T_1319; // @[el2_dec_tlu_ctl.scala 2728:65]
|
|
wire _T_1343 = _T_1318 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1344 = _T_1343 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1345 = _T_1320 | _T_1344; // @[el2_dec_tlu_ctl.scala 2728:121]
|
|
wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1362 = _T_1345 | _T_1361; // @[el2_dec_tlu_ctl.scala 2729:57]
|
|
wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1385 = _T_1362 | _T_1384; // @[el2_dec_tlu_ctl.scala 2729:113]
|
|
wire _T_1406 = _T_1225 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1407 = _T_1385 | _T_1406; // @[el2_dec_tlu_ctl.scala 2730:57]
|
|
wire _T_1430 = _T_1226 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1431 = _T_1407 | _T_1430; // @[el2_dec_tlu_ctl.scala 2730:113]
|
|
wire _T_1455 = _T_1153 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1456 = _T_1455 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1457 = _T_1456 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1458 = _T_1457 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1459 = _T_1431 | _T_1458; // @[el2_dec_tlu_ctl.scala 2731:57]
|
|
wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1476 = _T_1459 | _T_1475; // @[el2_dec_tlu_ctl.scala 2731:105]
|
|
wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1499 = _T_1498 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1500 = _T_1499 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1501 = _T_1500 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1502 = _T_1501 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1503 = _T_1476 | _T_1502; // @[el2_dec_tlu_ctl.scala 2732:65]
|
|
wire _T_1526 = _T_986 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1527 = _T_1526 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1528 = _T_1527 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1529 = _T_1528 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1530 = _T_1529 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1531 = _T_1503 | _T_1530; // @[el2_dec_tlu_ctl.scala 2732:113]
|
|
wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1551 = _T_1531 | _T_1550; // @[el2_dec_tlu_ctl.scala 2733:57]
|
|
wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1568 = _T_1551 | _T_1567; // @[el2_dec_tlu_ctl.scala 2733:113]
|
|
wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
wire _T_1588 = _T_1568 | _T_1587; // @[el2_dec_tlu_ctl.scala 2734:65]
|
|
wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192]
|
|
assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2650:49]
|
|
assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2651:49]
|
|
assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[el2_dec_tlu_ctl.scala 2652:57]
|
|
assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2653:57]
|
|
assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2654:57]
|
|
assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[el2_dec_tlu_ctl.scala 2655:57]
|
|
assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2656:49]
|
|
assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2657:57]
|
|
assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[el2_dec_tlu_ctl.scala 2658:57]
|
|
assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[el2_dec_tlu_ctl.scala 2659:57]
|
|
assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[el2_dec_tlu_ctl.scala 2660:57]
|
|
assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[el2_dec_tlu_ctl.scala 2661:49]
|
|
assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[el2_dec_tlu_ctl.scala 2662:49]
|
|
assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[el2_dec_tlu_ctl.scala 2663:49]
|
|
assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2664:49]
|
|
assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[el2_dec_tlu_ctl.scala 2665:57]
|
|
assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2666:57]
|
|
assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2667:49]
|
|
assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[el2_dec_tlu_ctl.scala 2668:49]
|
|
assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[el2_dec_tlu_ctl.scala 2669:49]
|
|
assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[el2_dec_tlu_ctl.scala 2670:57]
|
|
assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2671:57]
|
|
assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[el2_dec_tlu_ctl.scala 2672:49]
|
|
assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2673:49]
|
|
assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2674:49]
|
|
assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2675:49]
|
|
assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[el2_dec_tlu_ctl.scala 2676:49]
|
|
assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[el2_dec_tlu_ctl.scala 2677:49]
|
|
assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2678:49]
|
|
assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2679:57]
|
|
assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[el2_dec_tlu_ctl.scala 2680:49]
|
|
assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2681:57]
|
|
assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2682:57]
|
|
assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2683:57]
|
|
assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[el2_dec_tlu_ctl.scala 2684:57]
|
|
assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2685:57]
|
|
assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[el2_dec_tlu_ctl.scala 2686:57]
|
|
assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2687:57]
|
|
assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[el2_dec_tlu_ctl.scala 2688:57]
|
|
assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2689:57]
|
|
assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[el2_dec_tlu_ctl.scala 2690:57]
|
|
assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2691:57]
|
|
assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[el2_dec_tlu_ctl.scala 2692:57]
|
|
assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2693:57]
|
|
assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[el2_dec_tlu_ctl.scala 2694:57]
|
|
assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[el2_dec_tlu_ctl.scala 2695:41]
|
|
assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[el2_dec_tlu_ctl.scala 2696:57]
|
|
assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2697:57]
|
|
assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2698:49]
|
|
assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[el2_dec_tlu_ctl.scala 2699:49]
|
|
assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[el2_dec_tlu_ctl.scala 2700:57]
|
|
assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2701:57]
|
|
assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2702:49]
|
|
assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[el2_dec_tlu_ctl.scala 2704:57]
|
|
assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[el2_dec_tlu_ctl.scala 2706:57]
|
|
assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2707:49]
|
|
assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[el2_dec_tlu_ctl.scala 2708:49]
|
|
assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[el2_dec_tlu_ctl.scala 2709:49]
|
|
assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2710:49]
|
|
assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[el2_dec_tlu_ctl.scala 2711:49]
|
|
assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[el2_dec_tlu_ctl.scala 2712:57]
|
|
assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2713:57]
|
|
assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[el2_dec_tlu_ctl.scala 2714:57]
|
|
assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2715:57]
|
|
assign io_csr_pkt_presync = _T_830 | _T_845; // @[el2_dec_tlu_ctl.scala 2716:26]
|
|
assign io_csr_pkt_postsync = _T_926 | _T_938; // @[el2_dec_tlu_ctl.scala 2718:24]
|
|
assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[el2_dec_tlu_ctl.scala 2721:20]
|
|
endmodule
|
|
module el2_dec_tlu_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_active_clk,
|
|
input io_free_clk,
|
|
input io_scan_mode,
|
|
input [30:0] io_rst_vec,
|
|
input io_nmi_int,
|
|
input [30:0] io_nmi_vec,
|
|
input io_i_cpu_halt_req,
|
|
input io_i_cpu_run_req,
|
|
input io_lsu_fastint_stall_any,
|
|
input io_ifu_pmu_instr_aligned,
|
|
input io_ifu_pmu_fetch_stall,
|
|
input io_ifu_pmu_ic_miss,
|
|
input io_ifu_pmu_ic_hit,
|
|
input io_ifu_pmu_bus_error,
|
|
input io_ifu_pmu_bus_busy,
|
|
input io_ifu_pmu_bus_trxn,
|
|
input io_dec_pmu_instr_decoded,
|
|
input io_dec_pmu_decode_stall,
|
|
input io_dec_pmu_presync_stall,
|
|
input io_dec_pmu_postsync_stall,
|
|
input io_lsu_store_stall_any,
|
|
input io_dma_dccm_stall_any,
|
|
input io_dma_iccm_stall_any,
|
|
input io_exu_pmu_i0_br_misp,
|
|
input io_exu_pmu_i0_br_ataken,
|
|
input io_exu_pmu_i0_pc4,
|
|
input io_lsu_pmu_bus_trxn,
|
|
input io_lsu_pmu_bus_misaligned,
|
|
input io_lsu_pmu_bus_error,
|
|
input io_lsu_pmu_bus_busy,
|
|
input io_lsu_pmu_load_external_m,
|
|
input io_lsu_pmu_store_external_m,
|
|
input io_dma_pmu_dccm_read,
|
|
input io_dma_pmu_dccm_write,
|
|
input io_dma_pmu_any_read,
|
|
input io_dma_pmu_any_write,
|
|
input [30:0] io_lsu_fir_addr,
|
|
input [1:0] io_lsu_fir_error,
|
|
input io_iccm_dma_sb_error,
|
|
input io_lsu_error_pkt_r_valid,
|
|
input io_lsu_error_pkt_r_bits_single_ecc_error,
|
|
input io_lsu_error_pkt_r_bits_inst_type,
|
|
input io_lsu_error_pkt_r_bits_exc_type,
|
|
input [3:0] io_lsu_error_pkt_r_bits_mscause,
|
|
input [31:0] io_lsu_error_pkt_r_bits_addr,
|
|
input io_lsu_single_ecc_error_incr,
|
|
input io_dec_pause_state,
|
|
input io_lsu_imprecise_error_store_any,
|
|
input io_lsu_imprecise_error_load_any,
|
|
input [31:0] io_lsu_imprecise_error_addr_any,
|
|
input io_dec_csr_wen_unq_d,
|
|
input io_dec_csr_any_unq_d,
|
|
input [11:0] io_dec_csr_rdaddr_d,
|
|
input io_dec_csr_wen_r,
|
|
input [11:0] io_dec_csr_wraddr_r,
|
|
input [31:0] io_dec_csr_wrdata_r,
|
|
input io_dec_csr_stall_int_ff,
|
|
input io_dec_tlu_i0_valid_r,
|
|
input [30:0] io_exu_npc_r,
|
|
input [30:0] io_dec_tlu_i0_pc_r,
|
|
input io_dec_tlu_packet_r_legal,
|
|
input io_dec_tlu_packet_r_icaf,
|
|
input io_dec_tlu_packet_r_icaf_f1,
|
|
input [1:0] io_dec_tlu_packet_r_icaf_type,
|
|
input io_dec_tlu_packet_r_fence_i,
|
|
input [3:0] io_dec_tlu_packet_r_i0trigger,
|
|
input [3:0] io_dec_tlu_packet_r_pmu_i0_itype,
|
|
input io_dec_tlu_packet_r_pmu_i0_br_unpred,
|
|
input io_dec_tlu_packet_r_pmu_divide,
|
|
input io_dec_tlu_packet_r_pmu_lsu_misaligned,
|
|
input [31:0] io_dec_illegal_inst,
|
|
input io_dec_i0_decode_d,
|
|
input [1:0] io_exu_i0_br_hist_r,
|
|
input io_exu_i0_br_error_r,
|
|
input io_exu_i0_br_start_error_r,
|
|
input io_exu_i0_br_valid_r,
|
|
input io_exu_i0_br_mp_r,
|
|
input io_exu_i0_br_middle_r,
|
|
input io_exu_i0_br_way_r,
|
|
output io_dec_dbg_cmd_done,
|
|
output io_dec_dbg_cmd_fail,
|
|
output io_dec_tlu_dbg_halted,
|
|
output io_dec_tlu_debug_mode,
|
|
output io_dec_tlu_resume_ack,
|
|
output io_dec_tlu_debug_stall,
|
|
output io_dec_tlu_flush_noredir_r,
|
|
output io_dec_tlu_mpc_halted_only,
|
|
output io_dec_tlu_flush_leak_one_r,
|
|
output io_dec_tlu_flush_err_r,
|
|
output io_dec_tlu_flush_extint,
|
|
output [29:0] io_dec_tlu_meihap,
|
|
input io_dbg_halt_req,
|
|
input io_dbg_resume_req,
|
|
input io_ifu_miss_state_idle,
|
|
input io_lsu_idle_any,
|
|
input io_dec_div_active,
|
|
output io_trigger_pkt_any_0_select,
|
|
output io_trigger_pkt_any_0_match_pkt,
|
|
output io_trigger_pkt_any_0_store,
|
|
output io_trigger_pkt_any_0_load,
|
|
output io_trigger_pkt_any_0_execute,
|
|
output io_trigger_pkt_any_0_m,
|
|
output [31:0] io_trigger_pkt_any_0_tdata2,
|
|
output io_trigger_pkt_any_1_select,
|
|
output io_trigger_pkt_any_1_match_pkt,
|
|
output io_trigger_pkt_any_1_store,
|
|
output io_trigger_pkt_any_1_load,
|
|
output io_trigger_pkt_any_1_execute,
|
|
output io_trigger_pkt_any_1_m,
|
|
output [31:0] io_trigger_pkt_any_1_tdata2,
|
|
output io_trigger_pkt_any_2_select,
|
|
output io_trigger_pkt_any_2_match_pkt,
|
|
output io_trigger_pkt_any_2_store,
|
|
output io_trigger_pkt_any_2_load,
|
|
output io_trigger_pkt_any_2_execute,
|
|
output io_trigger_pkt_any_2_m,
|
|
output [31:0] io_trigger_pkt_any_2_tdata2,
|
|
output io_trigger_pkt_any_3_select,
|
|
output io_trigger_pkt_any_3_match_pkt,
|
|
output io_trigger_pkt_any_3_store,
|
|
output io_trigger_pkt_any_3_load,
|
|
output io_trigger_pkt_any_3_execute,
|
|
output io_trigger_pkt_any_3_m,
|
|
output [31:0] io_trigger_pkt_any_3_tdata2,
|
|
input io_ifu_ic_error_start,
|
|
input io_ifu_iccm_rd_ecc_single_err,
|
|
input [70:0] io_ifu_ic_debug_rd_data,
|
|
input io_ifu_ic_debug_rd_data_valid,
|
|
output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata,
|
|
output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics,
|
|
output io_dec_tlu_ic_diag_pkt_icache_rd_valid,
|
|
output io_dec_tlu_ic_diag_pkt_icache_wr_valid,
|
|
input [7:0] io_pic_claimid,
|
|
input [3:0] io_pic_pl,
|
|
input io_mhwakeup,
|
|
input io_mexintpend,
|
|
input io_timer_int,
|
|
input io_soft_int,
|
|
output io_o_cpu_halt_status,
|
|
output io_o_cpu_halt_ack,
|
|
output io_o_cpu_run_ack,
|
|
output io_o_debug_mode_status,
|
|
input [27:0] io_core_id,
|
|
input io_mpc_debug_halt_req,
|
|
input io_mpc_debug_run_req,
|
|
input io_mpc_reset_run_req,
|
|
output io_mpc_debug_halt_ack,
|
|
output io_mpc_debug_run_ack,
|
|
output io_debug_brkpt_status,
|
|
output [3:0] io_dec_tlu_meicurpl,
|
|
output [3:0] io_dec_tlu_meipt,
|
|
output [31:0] io_dec_csr_rddata_d,
|
|
output io_dec_csr_legal_d,
|
|
output io_dec_tlu_br0_r_pkt_valid,
|
|
output [1:0] io_dec_tlu_br0_r_pkt_hist,
|
|
output io_dec_tlu_br0_r_pkt_br_error,
|
|
output io_dec_tlu_br0_r_pkt_br_start_error,
|
|
output io_dec_tlu_br0_r_pkt_way,
|
|
output io_dec_tlu_br0_r_pkt_middle,
|
|
output io_dec_tlu_i0_kill_writeb_wb,
|
|
output io_dec_tlu_flush_lower_wb,
|
|
output io_dec_tlu_i0_commit_cmt,
|
|
output io_dec_tlu_i0_kill_writeb_r,
|
|
output io_dec_tlu_flush_lower_r,
|
|
output [30:0] io_dec_tlu_flush_path_r,
|
|
output io_dec_tlu_fence_i_r,
|
|
output io_dec_tlu_wr_pause_r,
|
|
output io_dec_tlu_flush_pause_r,
|
|
output io_dec_tlu_presync_d,
|
|
output io_dec_tlu_postsync_d,
|
|
output [31:0] io_dec_tlu_mrac_ff,
|
|
output io_dec_tlu_force_halt,
|
|
output io_dec_tlu_perfcnt0,
|
|
output io_dec_tlu_perfcnt1,
|
|
output io_dec_tlu_perfcnt2,
|
|
output io_dec_tlu_perfcnt3,
|
|
output io_dec_tlu_i0_exc_valid_wb1,
|
|
output io_dec_tlu_i0_valid_wb1,
|
|
output io_dec_tlu_int_valid_wb1,
|
|
output [4:0] io_dec_tlu_exc_cause_wb1,
|
|
output [31:0] io_dec_tlu_mtval_wb1,
|
|
output io_dec_tlu_external_ldfwd_disable,
|
|
output io_dec_tlu_sideeffect_posted_disable,
|
|
output io_dec_tlu_core_ecc_disable,
|
|
output io_dec_tlu_bpred_disable,
|
|
output io_dec_tlu_wb_coalescing_disable,
|
|
output io_dec_tlu_pipelining_disable,
|
|
output [2:0] io_dec_tlu_dma_qos_prty,
|
|
output io_dec_tlu_misc_clk_override,
|
|
output io_dec_tlu_dec_clk_override,
|
|
output io_dec_tlu_lsu_clk_override,
|
|
output io_dec_tlu_pic_clk_override,
|
|
output io_dec_tlu_dccm_clk_override,
|
|
output io_dec_tlu_icm_clk_override
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire int_timers_clock; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_reset; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_free_clk; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_scan_mode; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_csr_mitb0; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_csr_mitb1; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_internal_dbg_halt_timers; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire [31:0] int_timers_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire int_timers_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 355:24]
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire csr_clock; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_reset; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_free_clk; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_active_clk; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_scan_mode; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [11:0] csr_io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [11:0] csr_io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_0_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_1_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_2_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_3_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_pkt_any_3_m; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ifu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dma_iccm_stall_any; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dma_dccm_stall_any; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_store_stall_any; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_pmu_presync_stall; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_pmu_postsync_stall; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_pmu_decode_stall; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ifu_pmu_fetch_stall; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_exu_pmu_i0_br_misp; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_pmu_instr_decoded; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ifu_pmu_instr_aligned; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ifu_pmu_ic_miss; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ifu_pmu_ic_hit; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_int_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_i0_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_csr_wen_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_perfcnt0; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_perfcnt1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_perfcnt2; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_perfcnt3; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dma_pmu_dccm_write; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dma_pmu_dccm_read; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_misc_clk_override; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_lsu_clk_override; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_pic_clk_override; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_dccm_clk_override; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_icm_clk_override; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_pipelining_disable; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_wr_pause_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ifu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ifu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_pmu_bus_misaligned; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [3:0] csr_io_dec_tlu_meipt; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [3:0] csr_io_pic_pl; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [3:0] csr_io_dec_tlu_meicurpl; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [29:0] csr_io_dec_tlu_meihap; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [7:0] csr_io_pic_claimid; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_dec_tlu_mrac_ff; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_wb_coalescing_disable; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_bpred_disable; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_core_ecc_disable; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_external_ldfwd_disable; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_dec_illegal_inst; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_mexintpend; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [30:0] csr_io_exu_npc_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [30:0] csr_io_rst_vec; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [27:0] csr_io_core_id; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [1:0] csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_mret_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [15:0] csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [30:0] csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [5:0] csr_io_mip; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_timer_int_sync; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_soft_int_sync; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [5:0] csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_wr_clk; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [1:0] csr_io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [30:0] csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [30:0] csr_io_tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [30:0] csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_reset_delayed; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [30:0] csr_io_mepc; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_i0_exception_valid_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_e4e5_int_clk; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_i0_exc_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_inst_acc_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_take_nmi; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [4:0] csr_io_exc_cause_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_i0_valid_wb; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_clk_override; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [4:0] csr_io_exc_cause_wb; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_nmi_lsu_store_type; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_nmi_lsu_load_type; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ebreak_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ecall_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_illegal_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_mdseac_locked_ns; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_debug_halt_req; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_allow_dbg_halt_csr_write; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_internal_dbg_halt_mode_f; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_enter_debug_halt_req; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_request_debug_mode_done; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [30:0] csr_io_dpc; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [3:0] csr_io_update_hit_bit_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_take_timer_int; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_take_ext_int; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_tlu_flush_lower_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_br0_error_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_dec_tlu_br0_start_error_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire csr_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [9:0] csr_io_mtdata1_t_0; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [9:0] csr_io_mtdata1_t_1; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [9:0] csr_io_mtdata1_t_2; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [9:0] csr_io_mtdata1_t_3; // @[el2_dec_tlu_ctl.scala 897:17]
|
|
wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mitb0; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mitb1; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_meicpct; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_presync; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_postsync; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
wire csr_read_io_csr_pkt_legal; // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
reg dbg_halt_state_f; // @[el2_dec_tlu_ctl.scala 447:81]
|
|
wire _T = ~dbg_halt_state_f; // @[el2_dec_tlu_ctl.scala 354:33]
|
|
reg mpc_halt_state_f; // @[el2_dec_tlu_ctl.scala 442:81]
|
|
wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58]
|
|
reg [6:0] _T_8; // @[el2_lib.scala 177:81]
|
|
reg [6:0] syncro_ff; // @[el2_lib.scala 177:58]
|
|
wire nmi_int_sync = syncro_ff[6]; // @[el2_dec_tlu_ctl.scala 382:67]
|
|
wire i_cpu_halt_req_sync = syncro_ff[3]; // @[el2_dec_tlu_ctl.scala 385:59]
|
|
wire i_cpu_run_req_sync = syncro_ff[2]; // @[el2_dec_tlu_ctl.scala 386:59]
|
|
wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[el2_dec_tlu_ctl.scala 387:51]
|
|
wire mpc_debug_run_req_sync = syncro_ff[0]; // @[el2_dec_tlu_ctl.scala 388:51]
|
|
wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 1083:31]
|
|
reg lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 693:74]
|
|
wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 392:61]
|
|
reg e5_valid; // @[el2_dec_tlu_ctl.scala 404:89]
|
|
wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[el2_dec_tlu_ctl.scala 395:29]
|
|
reg debug_mode_status; // @[el2_dec_tlu_ctl.scala 405:73]
|
|
reg i_cpu_run_req_d1_raw; // @[el2_dec_tlu_ctl.scala 653:72]
|
|
reg nmi_int_delayed; // @[el2_dec_tlu_ctl.scala 420:64]
|
|
wire _T_37 = ~nmi_int_delayed; // @[el2_dec_tlu_ctl.scala 429:39]
|
|
wire _T_38 = nmi_int_sync & _T_37; // @[el2_dec_tlu_ctl.scala 429:37]
|
|
reg mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 686:89]
|
|
wire _T_35 = ~mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 427:26]
|
|
wire _T_36 = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 427:78]
|
|
wire nmi_lsu_detected = _T_35 & _T_36; // @[el2_dec_tlu_ctl.scala 427:43]
|
|
wire _T_39 = _T_38 | nmi_lsu_detected; // @[el2_dec_tlu_ctl.scala 429:57]
|
|
reg nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 421:72]
|
|
reg take_nmi_r_d1; // @[el2_dec_tlu_ctl.scala 894:90]
|
|
wire _T_40 = ~take_nmi_r_d1; // @[el2_dec_tlu_ctl.scala 429:100]
|
|
wire _T_41 = nmi_int_detected_f & _T_40; // @[el2_dec_tlu_ctl.scala 429:98]
|
|
wire _T_42 = _T_39 | _T_41; // @[el2_dec_tlu_ctl.scala 429:76]
|
|
reg take_ext_int_start_d3; // @[el2_dec_tlu_ctl.scala 826:58]
|
|
wire _T_43 = |io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 429:159]
|
|
wire _T_44 = take_ext_int_start_d3 & _T_43; // @[el2_dec_tlu_ctl.scala 429:140]
|
|
wire nmi_int_detected = _T_42 | _T_44; // @[el2_dec_tlu_ctl.scala 429:116]
|
|
wire _T_631 = ~io_dec_csr_stall_int_ff; // @[el2_dec_tlu_ctl.scala 803:22]
|
|
wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 1082:31]
|
|
wire _T_632 = _T_631 & mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 803:47]
|
|
wire [5:0] mip = csr_io_mip; // @[el2_dec_tlu_ctl.scala 1088:31]
|
|
wire _T_634 = _T_632 & mip[1]; // @[el2_dec_tlu_ctl.scala 803:64]
|
|
wire [5:0] mie_ns = csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 1077:31]
|
|
wire timer_int_ready = _T_634 & mie_ns[1]; // @[el2_dec_tlu_ctl.scala 803:82]
|
|
wire _T_391 = nmi_int_detected | timer_int_ready; // @[el2_dec_tlu_ctl.scala 680:65]
|
|
wire _T_628 = _T_632 & mip[0]; // @[el2_dec_tlu_ctl.scala 802:64]
|
|
wire soft_int_ready = _T_628 & mie_ns[0]; // @[el2_dec_tlu_ctl.scala 802:82]
|
|
wire _T_392 = _T_391 | soft_int_ready; // @[el2_dec_tlu_ctl.scala 680:83]
|
|
reg int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 660:65]
|
|
wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 680:100]
|
|
reg int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 661:65]
|
|
wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 680:124]
|
|
wire _T_608 = _T_632 & mip[2]; // @[el2_dec_tlu_ctl.scala 799:65]
|
|
wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[el2_dec_tlu_ctl.scala 799:83]
|
|
wire _T_395 = io_mhwakeup & mhwakeup_ready; // @[el2_dec_tlu_ctl.scala 680:163]
|
|
wire _T_396 = _T_394 | _T_395; // @[el2_dec_tlu_ctl.scala 680:148]
|
|
wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[el2_dec_tlu_ctl.scala 680:182]
|
|
reg i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 652:80]
|
|
wire _T_398 = ~i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 680:207]
|
|
wire _T_399 = _T_397 & _T_398; // @[el2_dec_tlu_ctl.scala 680:205]
|
|
wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[el2_dec_tlu_ctl.scala 680:44]
|
|
wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[el2_dec_tlu_ctl.scala 396:49]
|
|
wire _T_685 = ~_T_43; // @[el2_dec_tlu_ctl.scala 831:45]
|
|
wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[el2_dec_tlu_ctl.scala 831:43]
|
|
wire _T_698 = ~soft_int_ready; // @[el2_dec_tlu_ctl.scala 848:39]
|
|
wire _T_699 = timer_int_ready & _T_698; // @[el2_dec_tlu_ctl.scala 848:37]
|
|
wire _T_617 = ~io_lsu_fastint_stall_any; // @[el2_dec_tlu_ctl.scala 800:103]
|
|
wire ext_int_ready = mhwakeup_ready & _T_617; // @[el2_dec_tlu_ctl.scala 800:101]
|
|
wire _T_700 = ~ext_int_ready; // @[el2_dec_tlu_ctl.scala 848:57]
|
|
wire _T_701 = _T_699 & _T_700; // @[el2_dec_tlu_ctl.scala 848:55]
|
|
wire _T_622 = _T_632 & mip[5]; // @[el2_dec_tlu_ctl.scala 801:64]
|
|
wire ce_int_ready = _T_622 & mie_ns[5]; // @[el2_dec_tlu_ctl.scala 801:82]
|
|
wire _T_702 = ~ce_int_ready; // @[el2_dec_tlu_ctl.scala 848:74]
|
|
wire _T_703 = _T_701 & _T_702; // @[el2_dec_tlu_ctl.scala 848:72]
|
|
wire _T_152 = ~debug_mode_status; // @[el2_dec_tlu_ctl.scala 503:31]
|
|
reg dbg_halt_req_held; // @[el2_dec_tlu_ctl.scala 546:81]
|
|
wire _T_106 = io_dbg_halt_req | dbg_halt_req_held; // @[el2_dec_tlu_ctl.scala 480:42]
|
|
reg ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 827:58]
|
|
wire _T_107 = ~ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 480:65]
|
|
wire dbg_halt_req_final = _T_106 & _T_107; // @[el2_dec_tlu_ctl.scala 480:63]
|
|
wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[el2_dec_tlu_ctl.scala 439:61]
|
|
wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 483:44]
|
|
reg reset_detect; // @[el2_dec_tlu_ctl.scala 416:80]
|
|
reg reset_detected; // @[el2_dec_tlu_ctl.scala 417:80]
|
|
wire reset_delayed = reset_detect ^ reset_detected; // @[el2_dec_tlu_ctl.scala 418:64]
|
|
wire _T_110 = ~io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 483:89]
|
|
wire _T_111 = reset_delayed & _T_110; // @[el2_dec_tlu_ctl.scala 483:87]
|
|
wire _T_112 = _T_109 | _T_111; // @[el2_dec_tlu_ctl.scala 483:70]
|
|
wire _T_114 = _T_112 & _T_152; // @[el2_dec_tlu_ctl.scala 483:113]
|
|
wire debug_halt_req = _T_114 & _T_107; // @[el2_dec_tlu_ctl.scala 483:141]
|
|
wire _T_153 = _T_152 & debug_halt_req; // @[el2_dec_tlu_ctl.scala 503:57]
|
|
reg dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 538:81]
|
|
wire _T_154 = _T_153 | dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 503:75]
|
|
reg trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 537:81]
|
|
wire _T_155 = _T_154 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 503:101]
|
|
reg ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 752:58]
|
|
wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 503:126]
|
|
reg debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 535:81]
|
|
wire force_halt = csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 1080:31]
|
|
reg lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 531:89]
|
|
wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 497:47]
|
|
wire _T_143 = _T_142 & io_ifu_miss_state_idle; // @[el2_dec_tlu_ctl.scala 497:64]
|
|
reg ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 532:73]
|
|
wire _T_144 = _T_143 & ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 497:89]
|
|
wire _T_145 = ~debug_halt_req; // @[el2_dec_tlu_ctl.scala 497:115]
|
|
wire _T_146 = _T_144 & _T_145; // @[el2_dec_tlu_ctl.scala 497:113]
|
|
reg debug_halt_req_d1; // @[el2_dec_tlu_ctl.scala 539:81]
|
|
wire _T_147 = ~debug_halt_req_d1; // @[el2_dec_tlu_ctl.scala 497:133]
|
|
wire _T_148 = _T_146 & _T_147; // @[el2_dec_tlu_ctl.scala 497:131]
|
|
wire _T_149 = ~io_dec_div_active; // @[el2_dec_tlu_ctl.scala 497:154]
|
|
wire _T_150 = _T_148 & _T_149; // @[el2_dec_tlu_ctl.scala 497:152]
|
|
wire core_empty = force_halt | _T_150; // @[el2_dec_tlu_ctl.scala 497:28]
|
|
wire _T_163 = debug_halt_req_f & core_empty; // @[el2_dec_tlu_ctl.scala 513:42]
|
|
reg dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 529:73]
|
|
reg dec_tlu_flush_pause_r_d1; // @[el2_dec_tlu_ctl.scala 545:73]
|
|
wire _T_132 = ~dec_tlu_flush_pause_r_d1; // @[el2_dec_tlu_ctl.scala 493:50]
|
|
wire _T_133 = dec_tlu_flush_noredir_r_d1 & _T_132; // @[el2_dec_tlu_ctl.scala 493:48]
|
|
reg take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 824:58]
|
|
wire _T_134 = ~take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 493:78]
|
|
wire _T_135 = _T_133 & _T_134; // @[el2_dec_tlu_ctl.scala 493:76]
|
|
reg halt_taken_f; // @[el2_dec_tlu_ctl.scala 530:81]
|
|
reg dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 533:81]
|
|
wire _T_136 = ~dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 493:120]
|
|
wire _T_137 = halt_taken_f & _T_136; // @[el2_dec_tlu_ctl.scala 493:118]
|
|
reg pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 659:73]
|
|
wire _T_138 = ~pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 493:140]
|
|
wire _T_139 = _T_137 & _T_138; // @[el2_dec_tlu_ctl.scala 493:138]
|
|
reg interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 888:82]
|
|
wire _T_140 = ~interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 493:163]
|
|
wire _T_141 = _T_139 & _T_140; // @[el2_dec_tlu_ctl.scala 493:161]
|
|
wire halt_taken = _T_135 | _T_141; // @[el2_dec_tlu_ctl.scala 493:102]
|
|
wire _T_164 = _T_163 & halt_taken; // @[el2_dec_tlu_ctl.scala 513:55]
|
|
reg debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 536:81]
|
|
wire _T_165 = ~debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 513:91]
|
|
wire _T_166 = dbg_tlu_halted_f & _T_165; // @[el2_dec_tlu_ctl.scala 513:89]
|
|
wire dbg_tlu_halted = _T_164 | _T_166; // @[el2_dec_tlu_ctl.scala 513:69]
|
|
wire _T_167 = ~dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 514:67]
|
|
wire _T_168 = debug_halt_req_f & _T_167; // @[el2_dec_tlu_ctl.scala 514:65]
|
|
wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[el2_dec_tlu_ctl.scala 514:45]
|
|
wire [15:0] dcsr = csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 1086:31]
|
|
wire _T_157 = ~dcsr[2]; // @[el2_dec_tlu_ctl.scala 506:100]
|
|
wire _T_158 = debug_resume_req_f & _T_157; // @[el2_dec_tlu_ctl.scala 506:98]
|
|
wire _T_159 = ~_T_158; // @[el2_dec_tlu_ctl.scala 506:77]
|
|
wire _T_160 = debug_mode_status & _T_159; // @[el2_dec_tlu_ctl.scala 506:75]
|
|
wire internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[el2_dec_tlu_ctl.scala 506:47]
|
|
wire _T_177 = debug_resume_req_f & dcsr[2]; // @[el2_dec_tlu_ctl.scala 519:54]
|
|
reg dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 544:73]
|
|
wire _T_178 = ~dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 519:105]
|
|
wire _T_179 = dcsr_single_step_running_f & _T_178; // @[el2_dec_tlu_ctl.scala 519:103]
|
|
wire dcsr_single_step_running = _T_177 | _T_179; // @[el2_dec_tlu_ctl.scala 519:73]
|
|
wire _T_665 = ~dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 820:54]
|
|
wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 820:80]
|
|
wire _T_667 = internal_dbg_halt_mode & _T_666; // @[el2_dec_tlu_ctl.scala 820:51]
|
|
wire _T_346 = ~io_dec_tlu_debug_mode; // @[el2_dec_tlu_ctl.scala 649:56]
|
|
wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[el2_dec_tlu_ctl.scala 649:54]
|
|
wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[el2_dec_tlu_ctl.scala 649:79]
|
|
wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[el2_dec_tlu_ctl.scala 665:49]
|
|
wire fw_halt_req = csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 1084:31]
|
|
wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[el2_dec_tlu_ctl.scala 666:47]
|
|
reg pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 658:73]
|
|
wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[el2_dec_tlu_ctl.scala 671:44]
|
|
wire _T_372 = _T_371 & halt_taken; // @[el2_dec_tlu_ctl.scala 671:57]
|
|
wire _T_373 = ~enter_debug_halt_req; // @[el2_dec_tlu_ctl.scala 671:72]
|
|
wire _T_374 = _T_372 & _T_373; // @[el2_dec_tlu_ctl.scala 671:70]
|
|
wire _T_375 = ~i_cpu_run_req_d1; // @[el2_dec_tlu_ctl.scala 671:120]
|
|
wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[el2_dec_tlu_ctl.scala 671:118]
|
|
wire _T_377 = _T_374 | _T_376; // @[el2_dec_tlu_ctl.scala 671:95]
|
|
wire _T_378 = ~debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 671:142]
|
|
wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[el2_dec_tlu_ctl.scala 671:140]
|
|
wire _T_361 = ~pmu_fw_tlu_halted; // @[el2_dec_tlu_ctl.scala 667:71]
|
|
wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[el2_dec_tlu_ctl.scala 667:69]
|
|
wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[el2_dec_tlu_ctl.scala 667:48]
|
|
wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[el2_dec_tlu_ctl.scala 667:92]
|
|
reg internal_pmu_fw_halt_mode_f; // @[el2_dec_tlu_ctl.scala 657:66]
|
|
wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[el2_dec_tlu_ctl.scala 668:82]
|
|
wire _T_369 = _T_367 & _T_378; // @[el2_dec_tlu_ctl.scala 668:102]
|
|
wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[el2_dec_tlu_ctl.scala 668:51]
|
|
wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[el2_dec_tlu_ctl.scala 820:106]
|
|
wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 820:134]
|
|
wire _T_738 = ~internal_pmu_fw_halt_mode; // @[el2_dec_tlu_ctl.scala 852:34]
|
|
wire _T_739 = nmi_int_detected & _T_738; // @[el2_dec_tlu_ctl.scala 852:32]
|
|
wire _T_740 = ~internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 852:64]
|
|
wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[el2_dec_tlu_ctl.scala 852:118]
|
|
wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 852:140]
|
|
wire _T_744 = _T_742 & _T_743; // @[el2_dec_tlu_ctl.scala 852:138]
|
|
wire _T_746 = _T_744 & _T_178; // @[el2_dec_tlu_ctl.scala 852:163]
|
|
wire _T_747 = _T_740 | _T_746; // @[el2_dec_tlu_ctl.scala 852:88]
|
|
wire _T_748 = _T_739 & _T_747; // @[el2_dec_tlu_ctl.scala 852:61]
|
|
wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[el2_dec_tlu_ctl.scala 738:51]
|
|
wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 738:64]
|
|
wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 600:57]
|
|
wire [3:0] _T_299 = _T_297 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_300 = ~_T_299; // @[el2_dec_tlu_ctl.scala 600:22]
|
|
wire [3:0] _T_292 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[el2_dec_tlu_ctl.scala 598:52]
|
|
wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33]
|
|
wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33]
|
|
wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33]
|
|
wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33]
|
|
wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58]
|
|
wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_279 = trigger_execute & trigger_data; // @[el2_dec_tlu_ctl.scala 590:56]
|
|
wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 746:48]
|
|
wire [3:0] _T_281 = inst_acc_r_raw ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_282 = _T_279 & _T_281; // @[el2_dec_tlu_ctl.scala 590:71]
|
|
wire _T_283 = io_exu_i0_br_error_r | io_exu_i0_br_start_error_r; // @[el2_dec_tlu_ctl.scala 590:128]
|
|
wire [3:0] _T_285 = _T_283 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_286 = _T_282 | _T_285; // @[el2_dec_tlu_ctl.scala 590:97]
|
|
wire [3:0] i0_iside_trigger_has_pri_r = ~_T_286; // @[el2_dec_tlu_ctl.scala 590:37]
|
|
wire [3:0] _T_295 = _T_294 & i0_iside_trigger_has_pri_r; // @[el2_dec_tlu_ctl.scala 598:89]
|
|
wire [3:0] trigger_store = {mtdata1_t_3[1],mtdata1_t_2[1],mtdata1_t_1[1],mtdata1_t_0[1]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_287 = trigger_store & trigger_data; // @[el2_dec_tlu_ctl.scala 593:50]
|
|
wire [3:0] _T_289 = io_lsu_error_pkt_r_valid ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_290 = _T_287 & _T_289; // @[el2_dec_tlu_ctl.scala 593:65]
|
|
wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[el2_dec_tlu_ctl.scala 593:34]
|
|
wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[el2_dec_tlu_ctl.scala 598:118]
|
|
wire [1:0] mstatus = csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 1085:31]
|
|
wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:62]
|
|
wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[el2_dec_tlu_ctl.scala 587:86]
|
|
wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:150]
|
|
wire _T_266 = _T_264 & mtdata1_t_2[3]; // @[el2_dec_tlu_ctl.scala 587:174]
|
|
wire _T_269 = mtdata1_t_1[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:239]
|
|
wire _T_271 = _T_269 & mtdata1_t_1[3]; // @[el2_dec_tlu_ctl.scala 587:263]
|
|
wire _T_274 = mtdata1_t_0[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:328]
|
|
wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[el2_dec_tlu_ctl.scala 587:352]
|
|
wire [3:0] trigger_enabled = {_T_261,_T_266,_T_271,_T_276}; // @[Cat.scala 29:58]
|
|
wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[el2_dec_tlu_ctl.scala 598:145]
|
|
wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[el2_dec_tlu_ctl.scala 600:83]
|
|
wire _T_303 = ~mtdata1_t_2[5]; // @[el2_dec_tlu_ctl.scala 603:59]
|
|
wire _T_305 = _T_303 | i0_trigger_r[2]; // @[el2_dec_tlu_ctl.scala 603:88]
|
|
wire _T_306 = i0_trigger_r[3] & _T_305; // @[el2_dec_tlu_ctl.scala 603:56]
|
|
wire _T_311 = _T_303 | i0_trigger_r[3]; // @[el2_dec_tlu_ctl.scala 603:156]
|
|
wire _T_312 = i0_trigger_r[2] & _T_311; // @[el2_dec_tlu_ctl.scala 603:124]
|
|
wire _T_315 = ~mtdata1_t_0[5]; // @[el2_dec_tlu_ctl.scala 603:195]
|
|
wire _T_317 = _T_315 | i0_trigger_r[0]; // @[el2_dec_tlu_ctl.scala 603:224]
|
|
wire _T_318 = i0_trigger_r[1] & _T_317; // @[el2_dec_tlu_ctl.scala 603:192]
|
|
wire _T_323 = _T_315 | i0_trigger_r[1]; // @[el2_dec_tlu_ctl.scala 603:292]
|
|
wire _T_324 = i0_trigger_r[0] & _T_323; // @[el2_dec_tlu_ctl.scala 603:260]
|
|
wire [3:0] i0_trigger_chain_masked_r = {_T_306,_T_312,_T_318,_T_324}; // @[Cat.scala 29:58]
|
|
wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 606:56]
|
|
wire _T_465 = ~i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 738:90]
|
|
wire _T_466 = _T_464 & _T_465; // @[el2_dec_tlu_ctl.scala 738:88]
|
|
wire _T_468 = ~dcsr[15]; // @[el2_dec_tlu_ctl.scala 738:110]
|
|
wire _T_469 = _T_466 & _T_468; // @[el2_dec_tlu_ctl.scala 738:108]
|
|
reg tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 408:72]
|
|
wire _T_429 = ~tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 713:43]
|
|
wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[el2_dec_tlu_ctl.scala 713:41]
|
|
wire _T_432 = _T_430 & _T_283; // @[el2_dec_tlu_ctl.scala 713:65]
|
|
reg ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 402:81]
|
|
reg iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 403:89]
|
|
wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 713:137]
|
|
wire _T_435 = _T_433 & _T_107; // @[el2_dec_tlu_ctl.scala 713:156]
|
|
wire _T_436 = _T_432 | _T_435; // @[el2_dec_tlu_ctl.scala 713:120]
|
|
wire _T_438 = _T_436 & _T_465; // @[el2_dec_tlu_ctl.scala 713:179]
|
|
wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[el2_dec_tlu_ctl.scala 701:46]
|
|
wire _T_411 = ~io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec_tlu_ctl.scala 701:69]
|
|
wire _T_412 = _T_411 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec_tlu_ctl.scala 701:104]
|
|
wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[el2_dec_tlu_ctl.scala 701:66]
|
|
wire _T_439 = ~lsu_i0_rfnpc_r; // @[el2_dec_tlu_ctl.scala 713:203]
|
|
wire rfpc_i0_r = _T_438 & _T_439; // @[el2_dec_tlu_ctl.scala 713:200]
|
|
wire _T_470 = ~rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 738:132]
|
|
wire ebreak_r = _T_469 & _T_470; // @[el2_dec_tlu_ctl.scala 738:130]
|
|
wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[el2_dec_tlu_ctl.scala 739:51]
|
|
wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 739:64]
|
|
wire _T_475 = _T_473 & _T_465; // @[el2_dec_tlu_ctl.scala 739:88]
|
|
wire ecall_r = _T_475 & _T_470; // @[el2_dec_tlu_ctl.scala 739:108]
|
|
wire _T_523 = ebreak_r | ecall_r; // @[el2_dec_tlu_ctl.scala 766:40]
|
|
wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[el2_dec_tlu_ctl.scala 740:17]
|
|
wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 740:46]
|
|
wire _T_481 = _T_479 & _T_465; // @[el2_dec_tlu_ctl.scala 740:70]
|
|
wire illegal_r = _T_481 & _T_470; // @[el2_dec_tlu_ctl.scala 740:90]
|
|
wire _T_524 = _T_523 | illegal_r; // @[el2_dec_tlu_ctl.scala 766:50]
|
|
wire _T_511 = inst_acc_r_raw & _T_470; // @[el2_dec_tlu_ctl.scala 747:32]
|
|
wire inst_acc_r = _T_511 & _T_465; // @[el2_dec_tlu_ctl.scala 747:45]
|
|
wire _T_525 = _T_524 | inst_acc_r; // @[el2_dec_tlu_ctl.scala 766:62]
|
|
wire _T_527 = _T_525 & _T_470; // @[el2_dec_tlu_ctl.scala 766:76]
|
|
wire _T_528 = ~io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 766:91]
|
|
wire i0_exception_valid_r = _T_527 & _T_528; // @[el2_dec_tlu_ctl.scala 766:89]
|
|
wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 865:48]
|
|
wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_tlu_ctl.scala 689:56]
|
|
wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[el2_dec_tlu_ctl.scala 689:54]
|
|
wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[el2_dec_tlu_ctl.scala 691:39]
|
|
wire _T_405 = _T_403 & _T_465; // @[el2_dec_tlu_ctl.scala 691:61]
|
|
wire lsu_exc_valid_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 691:81]
|
|
wire _T_790 = _T_789 | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 865:60]
|
|
wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 743:49]
|
|
wire _T_492 = _T_490 & _T_465; // @[el2_dec_tlu_ctl.scala 743:73]
|
|
wire fence_i_r = _T_492 & _T_470; // @[el2_dec_tlu_ctl.scala 743:94]
|
|
wire _T_791 = _T_790 | fence_i_r; // @[el2_dec_tlu_ctl.scala 865:78]
|
|
wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[el2_dec_tlu_ctl.scala 865:90]
|
|
wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[el2_dec_tlu_ctl.scala 704:49]
|
|
wire _T_415 = ~lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 704:64]
|
|
wire _T_416 = _T_414 & _T_415; // @[el2_dec_tlu_ctl.scala 704:62]
|
|
wire _T_417 = ~inst_acc_r; // @[el2_dec_tlu_ctl.scala 704:81]
|
|
wire _T_418 = _T_416 & _T_417; // @[el2_dec_tlu_ctl.scala 704:78]
|
|
wire _T_420 = _T_418 & _T_528; // @[el2_dec_tlu_ctl.scala 704:93]
|
|
reg request_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 542:81]
|
|
wire _T_421 = ~request_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 704:120]
|
|
wire _T_422 = _T_420 & _T_421; // @[el2_dec_tlu_ctl.scala 704:118]
|
|
wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 704:145]
|
|
reg iccm_repair_state_d1; // @[el2_dec_tlu_ctl.scala 401:72]
|
|
wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[el2_dec_tlu_ctl.scala 722:51]
|
|
wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[el2_dec_tlu_ctl.scala 741:51]
|
|
wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 741:64]
|
|
wire _T_487 = _T_485 & _T_465; // @[el2_dec_tlu_ctl.scala 741:88]
|
|
wire mret_r = _T_487 & _T_470; // @[el2_dec_tlu_ctl.scala 741:108]
|
|
wire _T_446 = _T_523 | mret_r; // @[el2_dec_tlu_ctl.scala 722:97]
|
|
wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 851:31]
|
|
wire _T_447 = _T_446 | take_reset; // @[el2_dec_tlu_ctl.scala 722:106]
|
|
wire _T_448 = _T_447 | illegal_r; // @[el2_dec_tlu_ctl.scala 722:119]
|
|
wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[el2_dec_tlu_ctl.scala 722:175]
|
|
wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[el2_dec_tlu_ctl.scala 722:152]
|
|
wire _T_451 = _T_448 | _T_450; // @[el2_dec_tlu_ctl.scala 722:131]
|
|
wire _T_452 = ~_T_451; // @[el2_dec_tlu_ctl.scala 722:76]
|
|
wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[el2_dec_tlu_ctl.scala 722:74]
|
|
wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[el2_dec_tlu_ctl.scala 865:107]
|
|
wire _T_794 = _T_793 | debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 865:134]
|
|
wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 863:42]
|
|
wire _T_211 = ~io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 562:22]
|
|
reg dec_pause_state_f; // @[el2_dec_tlu_ctl.scala 541:73]
|
|
wire _T_212 = _T_211 & dec_pause_state_f; // @[el2_dec_tlu_ctl.scala 562:42]
|
|
wire _T_213 = ext_int_ready | ce_int_ready; // @[el2_dec_tlu_ctl.scala 562:80]
|
|
wire _T_214 = _T_213 | timer_int_ready; // @[el2_dec_tlu_ctl.scala 562:95]
|
|
wire _T_215 = _T_214 | soft_int_ready; // @[el2_dec_tlu_ctl.scala 562:113]
|
|
wire _T_216 = _T_215 | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 562:130]
|
|
wire _T_217 = _T_216 | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 562:154]
|
|
wire _T_218 = _T_217 | nmi_int_detected; // @[el2_dec_tlu_ctl.scala 562:178]
|
|
wire _T_219 = _T_218 | ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 562:197]
|
|
wire _T_220 = ~_T_219; // @[el2_dec_tlu_ctl.scala 562:64]
|
|
wire _T_221 = _T_212 & _T_220; // @[el2_dec_tlu_ctl.scala 562:62]
|
|
wire _T_223 = _T_221 & _T_140; // @[el2_dec_tlu_ctl.scala 562:218]
|
|
wire _T_225 = _T_223 & _T_378; // @[el2_dec_tlu_ctl.scala 562:242]
|
|
wire _T_226 = ~pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 562:264]
|
|
wire _T_227 = _T_225 & _T_226; // @[el2_dec_tlu_ctl.scala 562:262]
|
|
wire _T_228 = ~halt_taken_f; // @[el2_dec_tlu_ctl.scala 562:285]
|
|
wire pause_expired_r = _T_227 & _T_228; // @[el2_dec_tlu_ctl.scala 562:283]
|
|
wire sel_npc_resume = _T_786 | pause_expired_r; // @[el2_dec_tlu_ctl.scala 863:65]
|
|
wire _T_795 = _T_794 | sel_npc_resume; // @[el2_dec_tlu_ctl.scala 865:156]
|
|
reg dec_tlu_wr_pause_r_d1; // @[el2_dec_tlu_ctl.scala 540:73]
|
|
wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[el2_dec_tlu_ctl.scala 865:174]
|
|
wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 865:200]
|
|
wire _T_749 = ~synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 852:194]
|
|
wire _T_750 = _T_748 & _T_749; // @[el2_dec_tlu_ctl.scala 852:192]
|
|
wire _T_751 = ~mret_r; // @[el2_dec_tlu_ctl.scala 852:217]
|
|
wire _T_752 = _T_750 & _T_751; // @[el2_dec_tlu_ctl.scala 852:215]
|
|
wire _T_753 = ~take_reset; // @[el2_dec_tlu_ctl.scala 852:227]
|
|
wire _T_754 = _T_752 & _T_753; // @[el2_dec_tlu_ctl.scala 852:225]
|
|
wire _T_519 = _T_466 & dcsr[15]; // @[el2_dec_tlu_ctl.scala 750:120]
|
|
wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[el2_dec_tlu_ctl.scala 750:141]
|
|
wire _T_755 = ~ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 852:241]
|
|
wire _T_756 = _T_754 & _T_755; // @[el2_dec_tlu_ctl.scala 852:239]
|
|
wire _T_760 = _T_107 | _T_44; // @[el2_dec_tlu_ctl.scala 852:287]
|
|
wire take_nmi = _T_756 & _T_760; // @[el2_dec_tlu_ctl.scala 852:265]
|
|
wire _T_670 = _T_669 | take_nmi; // @[el2_dec_tlu_ctl.scala 820:154]
|
|
wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 820:165]
|
|
wire _T_672 = _T_671 | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 820:190]
|
|
reg exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 890:82]
|
|
wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 820:213]
|
|
wire _T_674 = _T_673 | mret_r; // @[el2_dec_tlu_ctl.scala 820:237]
|
|
wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 820:246]
|
|
wire _T_704 = ~block_interrupts; // @[el2_dec_tlu_ctl.scala 848:90]
|
|
wire take_timer_int = _T_703 & _T_704; // @[el2_dec_tlu_ctl.scala 848:88]
|
|
wire _T_762 = take_ext_int | take_timer_int; // @[el2_dec_tlu_ctl.scala 855:37]
|
|
wire _T_693 = soft_int_ready & _T_700; // @[el2_dec_tlu_ctl.scala 847:35]
|
|
wire _T_695 = _T_693 & _T_702; // @[el2_dec_tlu_ctl.scala 847:52]
|
|
wire take_soft_int = _T_695 & _T_704; // @[el2_dec_tlu_ctl.scala 847:68]
|
|
wire _T_763 = _T_762 | take_soft_int; // @[el2_dec_tlu_ctl.scala 855:54]
|
|
wire _T_764 = _T_763 | take_nmi; // @[el2_dec_tlu_ctl.scala 855:70]
|
|
wire _T_689 = ce_int_ready & _T_700; // @[el2_dec_tlu_ctl.scala 846:32]
|
|
wire take_ce_int = _T_689 & _T_704; // @[el2_dec_tlu_ctl.scala 846:49]
|
|
wire _T_765 = _T_764 | take_ce_int; // @[el2_dec_tlu_ctl.scala 855:81]
|
|
wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[el2_dec_tlu_ctl.scala 806:48]
|
|
wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[el2_dec_tlu_ctl.scala 807:46]
|
|
wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 849:48]
|
|
wire _T_707 = _T_706 & int_timer0_int_possible; // @[el2_dec_tlu_ctl.scala 849:73]
|
|
wire _T_709 = _T_707 & _T_631; // @[el2_dec_tlu_ctl.scala 849:99]
|
|
wire _T_710 = ~timer_int_ready; // @[el2_dec_tlu_ctl.scala 849:128]
|
|
wire _T_711 = _T_709 & _T_710; // @[el2_dec_tlu_ctl.scala 849:126]
|
|
wire _T_713 = _T_711 & _T_698; // @[el2_dec_tlu_ctl.scala 849:145]
|
|
wire _T_715 = _T_713 & _T_700; // @[el2_dec_tlu_ctl.scala 849:163]
|
|
wire _T_717 = _T_715 & _T_702; // @[el2_dec_tlu_ctl.scala 849:180]
|
|
wire take_int_timer0_int = _T_717 & _T_704; // @[el2_dec_tlu_ctl.scala 849:196]
|
|
wire _T_766 = _T_765 | take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 855:95]
|
|
wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[el2_dec_tlu_ctl.scala 808:48]
|
|
wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[el2_dec_tlu_ctl.scala 809:46]
|
|
wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 850:48]
|
|
wire _T_721 = _T_720 & int_timer1_int_possible; // @[el2_dec_tlu_ctl.scala 850:73]
|
|
wire _T_723 = _T_721 & _T_631; // @[el2_dec_tlu_ctl.scala 850:99]
|
|
wire _T_725 = ~_T_706; // @[el2_dec_tlu_ctl.scala 850:128]
|
|
wire _T_726 = _T_723 & _T_725; // @[el2_dec_tlu_ctl.scala 850:126]
|
|
wire _T_728 = _T_726 & _T_710; // @[el2_dec_tlu_ctl.scala 850:176]
|
|
wire _T_730 = _T_728 & _T_698; // @[el2_dec_tlu_ctl.scala 850:195]
|
|
wire _T_732 = _T_730 & _T_700; // @[el2_dec_tlu_ctl.scala 850:213]
|
|
wire _T_734 = _T_732 & _T_702; // @[el2_dec_tlu_ctl.scala 850:230]
|
|
wire take_int_timer1_int = _T_734 & _T_704; // @[el2_dec_tlu_ctl.scala 850:246]
|
|
wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 855:117]
|
|
wire _T_15 = _T_14 | interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 396:68]
|
|
wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 396:88]
|
|
wire _T_17 = _T_16 | reset_delayed; // @[el2_dec_tlu_ctl.scala 396:111]
|
|
wire _T_18 = _T_17 | pause_expired_r; // @[el2_dec_tlu_ctl.scala 396:127]
|
|
reg pause_expired_wb; // @[el2_dec_tlu_ctl.scala 895:90]
|
|
wire _T_19 = _T_18 | pause_expired_wb; // @[el2_dec_tlu_ctl.scala 396:145]
|
|
wire _T_496 = io_ifu_ic_error_start & _T_107; // @[el2_dec_tlu_ctl.scala 744:42]
|
|
wire _T_498 = _T_152 | dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 744:92]
|
|
wire _T_499 = _T_496 & _T_498; // @[el2_dec_tlu_ctl.scala 744:63]
|
|
wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[el2_dec_tlu_ctl.scala 744:122]
|
|
wire ic_perr_r = _T_499 & _T_500; // @[el2_dec_tlu_ctl.scala 744:120]
|
|
wire _T_20 = _T_19 | ic_perr_r; // @[el2_dec_tlu_ctl.scala 396:164]
|
|
wire _T_21 = _T_20 | ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 396:176]
|
|
wire _T_503 = io_ifu_iccm_rd_ecc_single_err & _T_107; // @[el2_dec_tlu_ctl.scala 745:50]
|
|
wire _T_506 = _T_503 & _T_498; // @[el2_dec_tlu_ctl.scala 745:71]
|
|
wire iccm_sbecc_r = _T_506 & _T_500; // @[el2_dec_tlu_ctl.scala 745:128]
|
|
wire _T_22 = _T_21 | iccm_sbecc_r; // @[el2_dec_tlu_ctl.scala 396:191]
|
|
wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 396:206]
|
|
wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 396:224]
|
|
reg lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 406:72]
|
|
reg lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 407:64]
|
|
reg _T_32; // @[el2_dec_tlu_ctl.scala 409:65]
|
|
reg internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 410:64]
|
|
reg _T_33; // @[el2_dec_tlu_ctl.scala 411:73]
|
|
reg nmi_lsu_load_type_f; // @[el2_dec_tlu_ctl.scala 422:72]
|
|
reg nmi_lsu_store_type_f; // @[el2_dec_tlu_ctl.scala 423:64]
|
|
wire _T_46 = nmi_lsu_detected & io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 431:42]
|
|
wire _T_49 = ~_T_41; // @[el2_dec_tlu_ctl.scala 431:78]
|
|
wire _T_50 = _T_46 & _T_49; // @[el2_dec_tlu_ctl.scala 431:76]
|
|
wire _T_52 = nmi_lsu_load_type_f & _T_40; // @[el2_dec_tlu_ctl.scala 431:141]
|
|
wire _T_54 = nmi_lsu_detected & io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 432:43]
|
|
wire _T_58 = _T_54 & _T_49; // @[el2_dec_tlu_ctl.scala 432:78]
|
|
wire _T_60 = nmi_lsu_store_type_f & _T_40; // @[el2_dec_tlu_ctl.scala 432:144]
|
|
reg mpc_debug_halt_req_sync_f; // @[el2_dec_tlu_ctl.scala 440:64]
|
|
reg mpc_debug_run_req_sync_f; // @[el2_dec_tlu_ctl.scala 441:64]
|
|
reg mpc_run_state_f; // @[el2_dec_tlu_ctl.scala 443:80]
|
|
reg debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 444:72]
|
|
reg mpc_debug_halt_ack_f; // @[el2_dec_tlu_ctl.scala 445:72]
|
|
reg mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 446:80]
|
|
reg dbg_run_state_f; // @[el2_dec_tlu_ctl.scala 448:80]
|
|
reg _T_65; // @[el2_dec_tlu_ctl.scala 449:73]
|
|
wire _T_66 = ~mpc_debug_halt_req_sync_f; // @[el2_dec_tlu_ctl.scala 453:65]
|
|
wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_66; // @[el2_dec_tlu_ctl.scala 453:63]
|
|
wire _T_67 = ~mpc_debug_run_req_sync_f; // @[el2_dec_tlu_ctl.scala 454:64]
|
|
wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_67; // @[el2_dec_tlu_ctl.scala 454:62]
|
|
wire _T_68 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[el2_dec_tlu_ctl.scala 456:42]
|
|
wire _T_71 = _T_68 | _T_111; // @[el2_dec_tlu_ctl.scala 456:74]
|
|
wire _T_72 = ~mpc_debug_run_req_sync; // @[el2_dec_tlu_ctl.scala 456:119]
|
|
wire mpc_halt_state_ns = _T_71 & _T_72; // @[el2_dec_tlu_ctl.scala 456:117]
|
|
wire _T_74 = ~mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 457:74]
|
|
wire _T_75 = mpc_debug_run_req_sync_pulse & _T_74; // @[el2_dec_tlu_ctl.scala 457:72]
|
|
wire _T_76 = mpc_run_state_f | _T_75; // @[el2_dec_tlu_ctl.scala 457:40]
|
|
wire _T_77 = ~dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 457:127]
|
|
wire _T_78 = debug_mode_status & _T_77; // @[el2_dec_tlu_ctl.scala 457:125]
|
|
wire mpc_run_state_ns = _T_76 & _T_78; // @[el2_dec_tlu_ctl.scala 457:97]
|
|
wire _T_80 = dbg_halt_req_final | dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 459:64]
|
|
wire _T_81 = _T_80 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 459:90]
|
|
wire _T_82 = _T_81 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 459:115]
|
|
wire _T_83 = dbg_halt_state_f | _T_82; // @[el2_dec_tlu_ctl.scala 459:42]
|
|
wire _T_84 = ~io_dbg_resume_req; // @[el2_dec_tlu_ctl.scala 459:147]
|
|
wire dbg_halt_state_ns = _T_83 & _T_84; // @[el2_dec_tlu_ctl.scala 459:145]
|
|
wire _T_86 = dbg_run_state_f | io_dbg_resume_req; // @[el2_dec_tlu_ctl.scala 460:40]
|
|
wire dbg_run_state_ns = _T_86 & _T_78; // @[el2_dec_tlu_ctl.scala 460:61]
|
|
wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 466:53]
|
|
wire _T_92 = debug_brkpt_valid | debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 467:47]
|
|
wire _T_94 = internal_dbg_halt_mode & _T_77; // @[el2_dec_tlu_ctl.scala 467:97]
|
|
wire _T_96 = mpc_halt_state_f & debug_mode_status; // @[el2_dec_tlu_ctl.scala 470:45]
|
|
wire _T_97 = _T_96 & mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 470:72]
|
|
wire _T_99 = ~dbg_halt_state_ns; // @[el2_dec_tlu_ctl.scala 471:53]
|
|
wire _T_100 = mpc_debug_run_req_sync & _T_99; // @[el2_dec_tlu_ctl.scala 471:51]
|
|
wire _T_101 = ~mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 471:74]
|
|
wire _T_102 = _T_100 & _T_101; // @[el2_dec_tlu_ctl.scala 471:72]
|
|
wire _T_103 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[el2_dec_tlu_ctl.scala 471:123]
|
|
wire _T_118 = mpc_run_state_ns & _T_99; // @[el2_dec_tlu_ctl.scala 485:67]
|
|
wire _T_119 = ~mpc_halt_state_ns; // @[el2_dec_tlu_ctl.scala 485:111]
|
|
wire _T_120 = dbg_run_state_ns & _T_119; // @[el2_dec_tlu_ctl.scala 485:109]
|
|
wire _T_121 = _T_118 | _T_120; // @[el2_dec_tlu_ctl.scala 485:89]
|
|
wire _T_122 = debug_halt_req_f | pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 490:37]
|
|
wire _T_124 = _T_122 & _T_749; // @[el2_dec_tlu_ctl.scala 490:58]
|
|
wire _T_126 = _T_124 & _T_751; // @[el2_dec_tlu_ctl.scala 490:81]
|
|
wire _T_128 = _T_126 & _T_228; // @[el2_dec_tlu_ctl.scala 490:91]
|
|
wire _T_129 = ~dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 490:109]
|
|
wire _T_130 = _T_128 & _T_129; // @[el2_dec_tlu_ctl.scala 490:107]
|
|
wire take_halt = _T_130 & _T_753; // @[el2_dec_tlu_ctl.scala 490:137]
|
|
wire _T_170 = debug_resume_req_f & dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 515:43]
|
|
wire _T_172 = io_dec_tlu_i0_valid_r & _T_528; // @[el2_dec_tlu_ctl.scala 517:53]
|
|
wire _T_174 = _T_172 & dcsr[2]; // @[el2_dec_tlu_ctl.scala 517:78]
|
|
wire _T_329 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[el2_dec_tlu_ctl.scala 612:61]
|
|
wire _T_332 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[el2_dec_tlu_ctl.scala 612:121]
|
|
wire _T_335 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[el2_dec_tlu_ctl.scala 612:181]
|
|
wire _T_338 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[el2_dec_tlu_ctl.scala 612:241]
|
|
wire [3:0] trigger_action = {_T_329,_T_332,_T_335,_T_338}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_343 = i0_trigger_chain_masked_r & trigger_action; // @[el2_dec_tlu_ctl.scala 618:56]
|
|
wire i0_trigger_action_r = |_T_343; // @[el2_dec_tlu_ctl.scala 618:74]
|
|
wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[el2_dec_tlu_ctl.scala 620:44]
|
|
wire _T_180 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 524:51]
|
|
wire _T_182 = request_debug_mode_r_d1 & _T_402; // @[el2_dec_tlu_ctl.scala 524:104]
|
|
reg request_debug_mode_done_f; // @[el2_dec_tlu_ctl.scala 543:73]
|
|
wire _T_183 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[el2_dec_tlu_ctl.scala 526:58]
|
|
reg _T_190; // @[el2_dec_tlu_ctl.scala 534:73]
|
|
wire _T_201 = fence_i_r & internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 555:56]
|
|
wire _T_202 = take_halt | _T_201; // @[el2_dec_tlu_ctl.scala 555:43]
|
|
wire _T_203 = _T_202 | io_dec_tlu_flush_pause_r; // @[el2_dec_tlu_ctl.scala 555:82]
|
|
wire _T_204 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[el2_dec_tlu_ctl.scala 555:129]
|
|
wire _T_205 = _T_203 | _T_204; // @[el2_dec_tlu_ctl.scala 555:109]
|
|
wire take_ext_int_start = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 828:41]
|
|
wire _T_207 = ~interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 560:55]
|
|
wire _T_208 = dec_tlu_wr_pause_r_d1 & _T_207; // @[el2_dec_tlu_ctl.scala 560:53]
|
|
wire _T_209 = ~take_ext_int_start; // @[el2_dec_tlu_ctl.scala 560:76]
|
|
wire _T_231 = io_dec_tlu_flush_lower_r & dcsr[2]; // @[el2_dec_tlu_ctl.scala 564:60]
|
|
wire _T_232 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 564:103]
|
|
wire _T_233 = _T_231 & _T_232; // @[el2_dec_tlu_ctl.scala 564:78]
|
|
wire _T_234 = ~io_dec_tlu_flush_noredir_r; // @[el2_dec_tlu_ctl.scala 564:133]
|
|
wire [3:0] _T_342 = i0_trigger_hit_raw_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_345 = ~trigger_hit_dmode_r; // @[el2_dec_tlu_ctl.scala 622:54]
|
|
wire mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[el2_dec_tlu_ctl.scala 622:52]
|
|
wire _T_350 = i_cpu_run_req_sync & _T_346; // @[el2_dec_tlu_ctl.scala 650:52]
|
|
wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 650:77]
|
|
wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[el2_dec_tlu_ctl.scala 650:99]
|
|
reg _T_353; // @[el2_dec_tlu_ctl.scala 654:73]
|
|
reg _T_354; // @[el2_dec_tlu_ctl.scala 655:81]
|
|
reg _T_355; // @[el2_dec_tlu_ctl.scala 656:81]
|
|
wire _T_384 = io_o_cpu_halt_status & _T_375; // @[el2_dec_tlu_ctl.scala 674:88]
|
|
wire _T_386 = _T_384 & _T_152; // @[el2_dec_tlu_ctl.scala 674:108]
|
|
wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[el2_dec_tlu_ctl.scala 675:40]
|
|
wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[el2_dec_tlu_ctl.scala 675:87]
|
|
reg lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 687:64]
|
|
reg lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 694:73]
|
|
wire _T_408 = ~io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec_tlu_ctl.scala 695:39]
|
|
wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[el2_dec_tlu_ctl.scala 695:37]
|
|
wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec_tlu_ctl.scala 696:37]
|
|
wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec_tlu_ctl.scala 697:37]
|
|
wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 707:37]
|
|
wire _T_425 = _T_424 | inst_acc_r; // @[el2_dec_tlu_ctl.scala 707:52]
|
|
wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 707:78]
|
|
wire _T_427 = _T_425 | _T_426; // @[el2_dec_tlu_ctl.scala 707:65]
|
|
wire _T_441 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_tlu_ctl.scala 716:69]
|
|
wire _T_442 = iccm_repair_state_d1 & _T_441; // @[el2_dec_tlu_ctl.scala 716:67]
|
|
wire _T_453 = io_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 725:50]
|
|
wire _T_455 = io_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 726:62]
|
|
wire _T_457 = io_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 727:46]
|
|
wire _T_459 = _T_457 & _T_429; // @[el2_dec_tlu_ctl.scala 727:70]
|
|
wire _T_460 = ~io_exu_i0_br_mp_r; // @[el2_dec_tlu_ctl.scala 727:97]
|
|
wire _T_461 = ~io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 727:118]
|
|
wire _T_462 = _T_460 | _T_461; // @[el2_dec_tlu_ctl.scala 727:116]
|
|
wire _T_529 = ~take_nmi; // @[el2_dec_tlu_ctl.scala 775:21]
|
|
wire _T_530 = take_ext_int & _T_529; // @[el2_dec_tlu_ctl.scala 775:19]
|
|
wire _T_533 = take_timer_int & _T_529; // @[el2_dec_tlu_ctl.scala 776:21]
|
|
wire _T_536 = take_soft_int & _T_529; // @[el2_dec_tlu_ctl.scala 777:20]
|
|
wire _T_539 = take_int_timer0_int & _T_529; // @[el2_dec_tlu_ctl.scala 778:26]
|
|
wire _T_542 = take_int_timer1_int & _T_529; // @[el2_dec_tlu_ctl.scala 779:26]
|
|
wire _T_545 = take_ce_int & _T_529; // @[el2_dec_tlu_ctl.scala 780:18]
|
|
wire _T_548 = illegal_r & _T_529; // @[el2_dec_tlu_ctl.scala 781:16]
|
|
wire _T_551 = ecall_r & _T_529; // @[el2_dec_tlu_ctl.scala 782:15]
|
|
wire _T_554 = inst_acc_r & _T_529; // @[el2_dec_tlu_ctl.scala 783:18]
|
|
wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 784:16]
|
|
wire _T_558 = _T_556 & _T_529; // @[el2_dec_tlu_ctl.scala 784:36]
|
|
wire _T_560 = ~lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 785:21]
|
|
wire _T_561 = lsu_exc_ma_r & _T_560; // @[el2_dec_tlu_ctl.scala 785:19]
|
|
wire _T_563 = _T_561 & _T_529; // @[el2_dec_tlu_ctl.scala 785:35]
|
|
wire _T_566 = lsu_exc_acc_r & _T_560; // @[el2_dec_tlu_ctl.scala 786:20]
|
|
wire _T_568 = _T_566 & _T_529; // @[el2_dec_tlu_ctl.scala 786:36]
|
|
wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 787:19]
|
|
wire _T_572 = _T_570 & _T_529; // @[el2_dec_tlu_ctl.scala 787:34]
|
|
wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 788:20]
|
|
wire _T_576 = _T_574 & _T_529; // @[el2_dec_tlu_ctl.scala 788:35]
|
|
wire [4:0] _T_578 = _T_530 ? 5'hb : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_579 = _T_533 ? 5'h7 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_580 = _T_536 ? 5'h3 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_581 = _T_539 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_582 = _T_542 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_583 = _T_545 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_584 = _T_548 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_585 = _T_551 ? 5'hb : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_586 = _T_554 ? 5'h1 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_587 = _T_558 ? 5'h3 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_588 = _T_563 ? 5'h4 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_589 = _T_568 ? 5'h5 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_590 = _T_572 ? 5'h6 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_591 = _T_576 ? 5'h7 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_592 = _T_578 | _T_579; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_593 = _T_592 | _T_580; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_594 = _T_593 | _T_581; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_595 = _T_594 | _T_582; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_596 = _T_595 | _T_583; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_597 = _T_596 | _T_584; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_598 = _T_597 | _T_585; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_599 = _T_598 | _T_586; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_600 = _T_599 | _T_587; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_601 = _T_600 | _T_588; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_602 = _T_601 | _T_589; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_603 = _T_602 | _T_590; // @[Mux.scala 27:72]
|
|
wire [4:0] exc_cause_r = _T_603 | _T_591; // @[Mux.scala 27:72]
|
|
wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 813:51]
|
|
wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 813:73]
|
|
wire int_timer_stalled = _T_642 | mret_r; // @[el2_dec_tlu_ctl.scala 813:97]
|
|
wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[el2_dec_tlu_ctl.scala 815:71]
|
|
wire _T_644 = int_timer0_int_ready & _T_643; // @[el2_dec_tlu_ctl.scala 815:48]
|
|
wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 815:120]
|
|
wire _T_647 = _T_645 & _T_207; // @[el2_dec_tlu_ctl.scala 815:144]
|
|
wire _T_649 = _T_647 & _T_209; // @[el2_dec_tlu_ctl.scala 815:165]
|
|
wire _T_651 = _T_649 & _T_152; // @[el2_dec_tlu_ctl.scala 815:187]
|
|
wire _T_654 = int_timer1_int_ready & _T_643; // @[el2_dec_tlu_ctl.scala 816:48]
|
|
wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 816:120]
|
|
wire _T_657 = _T_655 & _T_207; // @[el2_dec_tlu_ctl.scala 816:144]
|
|
wire _T_659 = _T_657 & _T_209; // @[el2_dec_tlu_ctl.scala 816:165]
|
|
wire _T_661 = _T_659 & _T_152; // @[el2_dec_tlu_ctl.scala 816:187]
|
|
reg take_ext_int_start_d2; // @[el2_dec_tlu_ctl.scala 825:58]
|
|
wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 830:42]
|
|
wire _T_682 = _T_681 | take_ext_int_start_d2; // @[el2_dec_tlu_ctl.scala 830:66]
|
|
wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 832:45]
|
|
wire [30:0] mtvec = csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 1087:31]
|
|
wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58]
|
|
wire [30:0] _T_771 = {25'h0,exc_cause_r,1'h0}; // @[Cat.scala 29:58]
|
|
wire [30:0] vectored_path = _T_769 + _T_771; // @[el2_dec_tlu_ctl.scala 860:50]
|
|
wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[el2_dec_tlu_ctl.scala 861:60]
|
|
wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[el2_dec_tlu_ctl.scala 861:27]
|
|
wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[el2_dec_tlu_ctl.scala 862:35]
|
|
wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[el2_dec_tlu_ctl.scala 862:47]
|
|
wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[el2_dec_tlu_ctl.scala 862:93]
|
|
wire _T_783 = _T_780 | _T_782; // @[el2_dec_tlu_ctl.scala 862:73]
|
|
wire _T_785 = rfpc_i0_r & _T_743; // @[el2_dec_tlu_ctl.scala 862:128]
|
|
wire sel_npc_r = _T_783 | _T_785; // @[el2_dec_tlu_ctl.scala 862:115]
|
|
wire _T_798 = interrupt_valid_r | mret_r; // @[el2_dec_tlu_ctl.scala 866:42]
|
|
wire _T_799 = _T_798 | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 866:51]
|
|
wire _T_800 = _T_799 | take_halt; // @[el2_dec_tlu_ctl.scala 866:73]
|
|
wire _T_801 = _T_800 | take_reset; // @[el2_dec_tlu_ctl.scala 866:85]
|
|
wire _T_807 = _T_529 & sel_npc_r; // @[el2_dec_tlu_ctl.scala 870:21]
|
|
wire _T_810 = _T_529 & rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 871:21]
|
|
wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 871:39]
|
|
wire _T_813 = ~sel_npc_r; // @[el2_dec_tlu_ctl.scala 871:80]
|
|
wire _T_814 = _T_812 & _T_813; // @[el2_dec_tlu_ctl.scala 871:69]
|
|
wire _T_816 = ~take_ext_int; // @[el2_dec_tlu_ctl.scala 872:44]
|
|
wire _T_817 = interrupt_valid_r & _T_816; // @[el2_dec_tlu_ctl.scala 872:30]
|
|
wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 873:28]
|
|
wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 873:46]
|
|
wire _T_823 = _T_821 & _T_207; // @[el2_dec_tlu_ctl.scala 873:91]
|
|
wire _T_825 = _T_823 & _T_816; // @[el2_dec_tlu_ctl.scala 873:112]
|
|
wire _T_830 = _T_529 & mret_r; // @[el2_dec_tlu_ctl.scala 874:16]
|
|
wire _T_833 = _T_529 & debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 875:16]
|
|
wire _T_836 = _T_529 & sel_npc_resume; // @[el2_dec_tlu_ctl.scala 876:16]
|
|
wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] npc_r = csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 1075:31]
|
|
wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] mepc = csr_io_mepc; // @[el2_dec_tlu_ctl.scala 1078:31]
|
|
wire [30:0] _T_843 = _T_830 ? mepc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] dpc = csr_io_dpc; // @[el2_dec_tlu_ctl.scala 1081:31]
|
|
wire [30:0] _T_844 = _T_833 ? dpc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 1076:31]
|
|
wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_848 = _T_847 | _T_841; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_849 = _T_848 | _T_842; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_850 = _T_849 | _T_843; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_851 = _T_850 | _T_844; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_852 = _T_851 | _T_845; // @[Mux.scala 27:72]
|
|
reg [30:0] tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 879:58]
|
|
wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[el2_dec_tlu_ctl.scala 886:44]
|
|
wire _T_855 = _T_854 | interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 886:67]
|
|
reg i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 889:81]
|
|
reg [4:0] exc_cause_wb; // @[el2_dec_tlu_ctl.scala 891:89]
|
|
wire _T_860 = ~illegal_r; // @[el2_dec_tlu_ctl.scala 892:119]
|
|
reg i0_valid_wb; // @[el2_dec_tlu_ctl.scala 892:97]
|
|
reg trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 893:81]
|
|
wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 1094:44]
|
|
wire _T_865 = ~io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 1094:69]
|
|
wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1099:57]
|
|
wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 1099:75]
|
|
wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1099:94]
|
|
wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1099:117]
|
|
wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1099:138]
|
|
wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1099:160]
|
|
wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 1099:181]
|
|
wire _T_881 = ~_T_880; // @[el2_dec_tlu_ctl.scala 1099:38]
|
|
wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1099:203]
|
|
wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_883 = csr_pkt_legal & _T_882; // @[el2_dec_tlu_ctl.scala 1099:35]
|
|
wire _T_884 = ~fast_int_meicpct; // @[el2_dec_tlu_ctl.scala 1099:225]
|
|
wire valid_csr = _T_883 & _T_884; // @[el2_dec_tlu_ctl.scala 1099:223]
|
|
wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[el2_dec_tlu_ctl.scala 1101:48]
|
|
wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1101:109]
|
|
wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1101:131]
|
|
wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1101:152]
|
|
wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1101:174]
|
|
wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10]
|
|
wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1101:195]
|
|
wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[el2_dec_tlu_ctl.scala 1101:84]
|
|
wire _T_894 = ~_T_893; // @[el2_dec_tlu_ctl.scala 1101:61]
|
|
el2_dec_timer_ctl int_timers ( // @[el2_dec_tlu_ctl.scala 355:24]
|
|
.clock(int_timers_clock),
|
|
.reset(int_timers_reset),
|
|
.io_free_clk(int_timers_io_free_clk),
|
|
.io_scan_mode(int_timers_io_scan_mode),
|
|
.io_dec_csr_wen_r_mod(int_timers_io_dec_csr_wen_r_mod),
|
|
.io_dec_csr_wraddr_r(int_timers_io_dec_csr_wraddr_r),
|
|
.io_dec_csr_wrdata_r(int_timers_io_dec_csr_wrdata_r),
|
|
.io_csr_mitctl0(int_timers_io_csr_mitctl0),
|
|
.io_csr_mitctl1(int_timers_io_csr_mitctl1),
|
|
.io_csr_mitb0(int_timers_io_csr_mitb0),
|
|
.io_csr_mitb1(int_timers_io_csr_mitb1),
|
|
.io_csr_mitcnt0(int_timers_io_csr_mitcnt0),
|
|
.io_csr_mitcnt1(int_timers_io_csr_mitcnt1),
|
|
.io_dec_pause_state(int_timers_io_dec_pause_state),
|
|
.io_dec_tlu_pmu_fw_halted(int_timers_io_dec_tlu_pmu_fw_halted),
|
|
.io_internal_dbg_halt_timers(int_timers_io_internal_dbg_halt_timers),
|
|
.io_dec_timer_rddata_d(int_timers_io_dec_timer_rddata_d),
|
|
.io_dec_timer_read_d(int_timers_io_dec_timer_read_d),
|
|
.io_dec_timer_t0_pulse(int_timers_io_dec_timer_t0_pulse),
|
|
.io_dec_timer_t1_pulse(int_timers_io_dec_timer_t1_pulse)
|
|
);
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
csr_tlu csr ( // @[el2_dec_tlu_ctl.scala 897:17]
|
|
.clock(csr_clock),
|
|
.reset(csr_reset),
|
|
.io_free_clk(csr_io_free_clk),
|
|
.io_active_clk(csr_io_active_clk),
|
|
.io_scan_mode(csr_io_scan_mode),
|
|
.io_dec_csr_wrdata_r(csr_io_dec_csr_wrdata_r),
|
|
.io_dec_csr_wraddr_r(csr_io_dec_csr_wraddr_r),
|
|
.io_dec_csr_rdaddr_d(csr_io_dec_csr_rdaddr_d),
|
|
.io_dec_csr_wen_unq_d(csr_io_dec_csr_wen_unq_d),
|
|
.io_dec_i0_decode_d(csr_io_dec_i0_decode_d),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wrdata(csr_io_dec_tlu_ic_diag_pkt_icache_wrdata),
|
|
.io_dec_tlu_ic_diag_pkt_icache_dicawics(csr_io_dec_tlu_ic_diag_pkt_icache_dicawics),
|
|
.io_dec_tlu_ic_diag_pkt_icache_rd_valid(csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wr_valid(csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid),
|
|
.io_ifu_ic_debug_rd_data_valid(csr_io_ifu_ic_debug_rd_data_valid),
|
|
.io_trigger_pkt_any_0_select(csr_io_trigger_pkt_any_0_select),
|
|
.io_trigger_pkt_any_0_match_pkt(csr_io_trigger_pkt_any_0_match_pkt),
|
|
.io_trigger_pkt_any_0_store(csr_io_trigger_pkt_any_0_store),
|
|
.io_trigger_pkt_any_0_load(csr_io_trigger_pkt_any_0_load),
|
|
.io_trigger_pkt_any_0_execute(csr_io_trigger_pkt_any_0_execute),
|
|
.io_trigger_pkt_any_0_m(csr_io_trigger_pkt_any_0_m),
|
|
.io_trigger_pkt_any_0_tdata2(csr_io_trigger_pkt_any_0_tdata2),
|
|
.io_trigger_pkt_any_1_select(csr_io_trigger_pkt_any_1_select),
|
|
.io_trigger_pkt_any_1_match_pkt(csr_io_trigger_pkt_any_1_match_pkt),
|
|
.io_trigger_pkt_any_1_store(csr_io_trigger_pkt_any_1_store),
|
|
.io_trigger_pkt_any_1_load(csr_io_trigger_pkt_any_1_load),
|
|
.io_trigger_pkt_any_1_execute(csr_io_trigger_pkt_any_1_execute),
|
|
.io_trigger_pkt_any_1_m(csr_io_trigger_pkt_any_1_m),
|
|
.io_trigger_pkt_any_1_tdata2(csr_io_trigger_pkt_any_1_tdata2),
|
|
.io_trigger_pkt_any_2_select(csr_io_trigger_pkt_any_2_select),
|
|
.io_trigger_pkt_any_2_match_pkt(csr_io_trigger_pkt_any_2_match_pkt),
|
|
.io_trigger_pkt_any_2_store(csr_io_trigger_pkt_any_2_store),
|
|
.io_trigger_pkt_any_2_load(csr_io_trigger_pkt_any_2_load),
|
|
.io_trigger_pkt_any_2_execute(csr_io_trigger_pkt_any_2_execute),
|
|
.io_trigger_pkt_any_2_m(csr_io_trigger_pkt_any_2_m),
|
|
.io_trigger_pkt_any_2_tdata2(csr_io_trigger_pkt_any_2_tdata2),
|
|
.io_trigger_pkt_any_3_select(csr_io_trigger_pkt_any_3_select),
|
|
.io_trigger_pkt_any_3_match_pkt(csr_io_trigger_pkt_any_3_match_pkt),
|
|
.io_trigger_pkt_any_3_store(csr_io_trigger_pkt_any_3_store),
|
|
.io_trigger_pkt_any_3_load(csr_io_trigger_pkt_any_3_load),
|
|
.io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute),
|
|
.io_trigger_pkt_any_3_m(csr_io_trigger_pkt_any_3_m),
|
|
.io_trigger_pkt_any_3_tdata2(csr_io_trigger_pkt_any_3_tdata2),
|
|
.io_ifu_pmu_bus_trxn(csr_io_ifu_pmu_bus_trxn),
|
|
.io_dma_iccm_stall_any(csr_io_dma_iccm_stall_any),
|
|
.io_dma_dccm_stall_any(csr_io_dma_dccm_stall_any),
|
|
.io_lsu_store_stall_any(csr_io_lsu_store_stall_any),
|
|
.io_dec_pmu_presync_stall(csr_io_dec_pmu_presync_stall),
|
|
.io_dec_pmu_postsync_stall(csr_io_dec_pmu_postsync_stall),
|
|
.io_dec_pmu_decode_stall(csr_io_dec_pmu_decode_stall),
|
|
.io_ifu_pmu_fetch_stall(csr_io_ifu_pmu_fetch_stall),
|
|
.io_dec_tlu_packet_r_icaf_type(csr_io_dec_tlu_packet_r_icaf_type),
|
|
.io_dec_tlu_packet_r_pmu_i0_itype(csr_io_dec_tlu_packet_r_pmu_i0_itype),
|
|
.io_dec_tlu_packet_r_pmu_i0_br_unpred(csr_io_dec_tlu_packet_r_pmu_i0_br_unpred),
|
|
.io_dec_tlu_packet_r_pmu_divide(csr_io_dec_tlu_packet_r_pmu_divide),
|
|
.io_dec_tlu_packet_r_pmu_lsu_misaligned(csr_io_dec_tlu_packet_r_pmu_lsu_misaligned),
|
|
.io_exu_pmu_i0_br_ataken(csr_io_exu_pmu_i0_br_ataken),
|
|
.io_exu_pmu_i0_br_misp(csr_io_exu_pmu_i0_br_misp),
|
|
.io_dec_pmu_instr_decoded(csr_io_dec_pmu_instr_decoded),
|
|
.io_ifu_pmu_instr_aligned(csr_io_ifu_pmu_instr_aligned),
|
|
.io_exu_pmu_i0_pc4(csr_io_exu_pmu_i0_pc4),
|
|
.io_ifu_pmu_ic_miss(csr_io_ifu_pmu_ic_miss),
|
|
.io_ifu_pmu_ic_hit(csr_io_ifu_pmu_ic_hit),
|
|
.io_dec_tlu_int_valid_wb1(csr_io_dec_tlu_int_valid_wb1),
|
|
.io_dec_tlu_i0_exc_valid_wb1(csr_io_dec_tlu_i0_exc_valid_wb1),
|
|
.io_dec_tlu_i0_valid_wb1(csr_io_dec_tlu_i0_valid_wb1),
|
|
.io_dec_csr_wen_r(csr_io_dec_csr_wen_r),
|
|
.io_dec_tlu_mtval_wb1(csr_io_dec_tlu_mtval_wb1),
|
|
.io_dec_tlu_exc_cause_wb1(csr_io_dec_tlu_exc_cause_wb1),
|
|
.io_dec_tlu_perfcnt0(csr_io_dec_tlu_perfcnt0),
|
|
.io_dec_tlu_perfcnt1(csr_io_dec_tlu_perfcnt1),
|
|
.io_dec_tlu_perfcnt2(csr_io_dec_tlu_perfcnt2),
|
|
.io_dec_tlu_perfcnt3(csr_io_dec_tlu_perfcnt3),
|
|
.io_dec_tlu_dbg_halted(csr_io_dec_tlu_dbg_halted),
|
|
.io_dma_pmu_dccm_write(csr_io_dma_pmu_dccm_write),
|
|
.io_dma_pmu_dccm_read(csr_io_dma_pmu_dccm_read),
|
|
.io_dma_pmu_any_write(csr_io_dma_pmu_any_write),
|
|
.io_dma_pmu_any_read(csr_io_dma_pmu_any_read),
|
|
.io_lsu_pmu_bus_busy(csr_io_lsu_pmu_bus_busy),
|
|
.io_dec_tlu_i0_pc_r(csr_io_dec_tlu_i0_pc_r),
|
|
.io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r),
|
|
.io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d),
|
|
.io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override),
|
|
.io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override),
|
|
.io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override),
|
|
.io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override),
|
|
.io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override),
|
|
.io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override),
|
|
.io_dec_csr_rddata_d(csr_io_dec_csr_rddata_d),
|
|
.io_dec_tlu_pipelining_disable(csr_io_dec_tlu_pipelining_disable),
|
|
.io_dec_tlu_wr_pause_r(csr_io_dec_tlu_wr_pause_r),
|
|
.io_ifu_pmu_bus_busy(csr_io_ifu_pmu_bus_busy),
|
|
.io_lsu_pmu_bus_error(csr_io_lsu_pmu_bus_error),
|
|
.io_ifu_pmu_bus_error(csr_io_ifu_pmu_bus_error),
|
|
.io_lsu_pmu_bus_misaligned(csr_io_lsu_pmu_bus_misaligned),
|
|
.io_lsu_pmu_bus_trxn(csr_io_lsu_pmu_bus_trxn),
|
|
.io_ifu_ic_debug_rd_data(csr_io_ifu_ic_debug_rd_data),
|
|
.io_dec_tlu_meipt(csr_io_dec_tlu_meipt),
|
|
.io_pic_pl(csr_io_pic_pl),
|
|
.io_dec_tlu_meicurpl(csr_io_dec_tlu_meicurpl),
|
|
.io_dec_tlu_meihap(csr_io_dec_tlu_meihap),
|
|
.io_pic_claimid(csr_io_pic_claimid),
|
|
.io_iccm_dma_sb_error(csr_io_iccm_dma_sb_error),
|
|
.io_lsu_imprecise_error_addr_any(csr_io_lsu_imprecise_error_addr_any),
|
|
.io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any),
|
|
.io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any),
|
|
.io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff),
|
|
.io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable),
|
|
.io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable),
|
|
.io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable),
|
|
.io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable),
|
|
.io_dec_tlu_external_ldfwd_disable(csr_io_dec_tlu_external_ldfwd_disable),
|
|
.io_dec_tlu_dma_qos_prty(csr_io_dec_tlu_dma_qos_prty),
|
|
.io_dec_illegal_inst(csr_io_dec_illegal_inst),
|
|
.io_lsu_error_pkt_r_bits_mscause(csr_io_lsu_error_pkt_r_bits_mscause),
|
|
.io_mexintpend(csr_io_mexintpend),
|
|
.io_exu_npc_r(csr_io_exu_npc_r),
|
|
.io_mpc_reset_run_req(csr_io_mpc_reset_run_req),
|
|
.io_rst_vec(csr_io_rst_vec),
|
|
.io_core_id(csr_io_core_id),
|
|
.io_dec_timer_rddata_d(csr_io_dec_timer_rddata_d),
|
|
.io_dec_timer_read_d(csr_io_dec_timer_read_d),
|
|
.io_dec_csr_wen_r_mod(csr_io_dec_csr_wen_r_mod),
|
|
.io_rfpc_i0_r(csr_io_rfpc_i0_r),
|
|
.io_i0_trigger_hit_r(csr_io_i0_trigger_hit_r),
|
|
.io_fw_halt_req(csr_io_fw_halt_req),
|
|
.io_mstatus(csr_io_mstatus),
|
|
.io_exc_or_int_valid_r(csr_io_exc_or_int_valid_r),
|
|
.io_mret_r(csr_io_mret_r),
|
|
.io_mstatus_mie_ns(csr_io_mstatus_mie_ns),
|
|
.io_dcsr_single_step_running_f(csr_io_dcsr_single_step_running_f),
|
|
.io_dcsr(csr_io_dcsr),
|
|
.io_mtvec(csr_io_mtvec),
|
|
.io_mip(csr_io_mip),
|
|
.io_dec_timer_t0_pulse(csr_io_dec_timer_t0_pulse),
|
|
.io_dec_timer_t1_pulse(csr_io_dec_timer_t1_pulse),
|
|
.io_timer_int_sync(csr_io_timer_int_sync),
|
|
.io_soft_int_sync(csr_io_soft_int_sync),
|
|
.io_mie_ns(csr_io_mie_ns),
|
|
.io_csr_wr_clk(csr_io_csr_wr_clk),
|
|
.io_ebreak_to_debug_mode_r(csr_io_ebreak_to_debug_mode_r),
|
|
.io_dec_tlu_pmu_fw_halted(csr_io_dec_tlu_pmu_fw_halted),
|
|
.io_lsu_fir_error(csr_io_lsu_fir_error),
|
|
.io_npc_r(csr_io_npc_r),
|
|
.io_tlu_flush_lower_r_d1(csr_io_tlu_flush_lower_r_d1),
|
|
.io_dec_tlu_flush_noredir_r_d1(csr_io_dec_tlu_flush_noredir_r_d1),
|
|
.io_tlu_flush_path_r_d1(csr_io_tlu_flush_path_r_d1),
|
|
.io_npc_r_d1(csr_io_npc_r_d1),
|
|
.io_reset_delayed(csr_io_reset_delayed),
|
|
.io_mepc(csr_io_mepc),
|
|
.io_interrupt_valid_r(csr_io_interrupt_valid_r),
|
|
.io_i0_exception_valid_r(csr_io_i0_exception_valid_r),
|
|
.io_lsu_exc_valid_r(csr_io_lsu_exc_valid_r),
|
|
.io_mepc_trigger_hit_sel_pc_r(csr_io_mepc_trigger_hit_sel_pc_r),
|
|
.io_e4e5_int_clk(csr_io_e4e5_int_clk),
|
|
.io_lsu_i0_exc_r(csr_io_lsu_i0_exc_r),
|
|
.io_inst_acc_r(csr_io_inst_acc_r),
|
|
.io_inst_acc_second_r(csr_io_inst_acc_second_r),
|
|
.io_take_nmi(csr_io_take_nmi),
|
|
.io_lsu_error_pkt_addr_r(csr_io_lsu_error_pkt_addr_r),
|
|
.io_exc_cause_r(csr_io_exc_cause_r),
|
|
.io_i0_valid_wb(csr_io_i0_valid_wb),
|
|
.io_exc_or_int_valid_r_d1(csr_io_exc_or_int_valid_r_d1),
|
|
.io_interrupt_valid_r_d1(csr_io_interrupt_valid_r_d1),
|
|
.io_clk_override(csr_io_clk_override),
|
|
.io_i0_exception_valid_r_d1(csr_io_i0_exception_valid_r_d1),
|
|
.io_lsu_i0_exc_r_d1(csr_io_lsu_i0_exc_r_d1),
|
|
.io_exc_cause_wb(csr_io_exc_cause_wb),
|
|
.io_nmi_lsu_store_type(csr_io_nmi_lsu_store_type),
|
|
.io_nmi_lsu_load_type(csr_io_nmi_lsu_load_type),
|
|
.io_tlu_i0_commit_cmt(csr_io_tlu_i0_commit_cmt),
|
|
.io_ebreak_r(csr_io_ebreak_r),
|
|
.io_ecall_r(csr_io_ecall_r),
|
|
.io_illegal_r(csr_io_illegal_r),
|
|
.io_mdseac_locked_ns(csr_io_mdseac_locked_ns),
|
|
.io_mdseac_locked_f(csr_io_mdseac_locked_f),
|
|
.io_nmi_int_detected_f(csr_io_nmi_int_detected_f),
|
|
.io_internal_dbg_halt_mode_f2(csr_io_internal_dbg_halt_mode_f2),
|
|
.io_ext_int_freeze_d1(csr_io_ext_int_freeze_d1),
|
|
.io_ic_perr_r_d1(csr_io_ic_perr_r_d1),
|
|
.io_iccm_sbecc_r_d1(csr_io_iccm_sbecc_r_d1),
|
|
.io_lsu_single_ecc_error_r_d1(csr_io_lsu_single_ecc_error_r_d1),
|
|
.io_ifu_miss_state_idle_f(csr_io_ifu_miss_state_idle_f),
|
|
.io_lsu_idle_any_f(csr_io_lsu_idle_any_f),
|
|
.io_dbg_tlu_halted_f(csr_io_dbg_tlu_halted_f),
|
|
.io_dbg_tlu_halted(csr_io_dbg_tlu_halted),
|
|
.io_debug_halt_req_f(csr_io_debug_halt_req_f),
|
|
.io_force_halt(csr_io_force_halt),
|
|
.io_take_ext_int_start(csr_io_take_ext_int_start),
|
|
.io_trigger_hit_dmode_r_d1(csr_io_trigger_hit_dmode_r_d1),
|
|
.io_trigger_hit_r_d1(csr_io_trigger_hit_r_d1),
|
|
.io_dcsr_single_step_done_f(csr_io_dcsr_single_step_done_f),
|
|
.io_ebreak_to_debug_mode_r_d1(csr_io_ebreak_to_debug_mode_r_d1),
|
|
.io_debug_halt_req(csr_io_debug_halt_req),
|
|
.io_allow_dbg_halt_csr_write(csr_io_allow_dbg_halt_csr_write),
|
|
.io_internal_dbg_halt_mode_f(csr_io_internal_dbg_halt_mode_f),
|
|
.io_enter_debug_halt_req(csr_io_enter_debug_halt_req),
|
|
.io_internal_dbg_halt_mode(csr_io_internal_dbg_halt_mode),
|
|
.io_request_debug_mode_done(csr_io_request_debug_mode_done),
|
|
.io_request_debug_mode_r(csr_io_request_debug_mode_r),
|
|
.io_dpc(csr_io_dpc),
|
|
.io_update_hit_bit_r(csr_io_update_hit_bit_r),
|
|
.io_take_timer_int(csr_io_take_timer_int),
|
|
.io_take_int_timer0_int(csr_io_take_int_timer0_int),
|
|
.io_take_int_timer1_int(csr_io_take_int_timer1_int),
|
|
.io_take_ext_int(csr_io_take_ext_int),
|
|
.io_tlu_flush_lower_r(csr_io_tlu_flush_lower_r),
|
|
.io_dec_tlu_br0_error_r(csr_io_dec_tlu_br0_error_r),
|
|
.io_dec_tlu_br0_start_error_r(csr_io_dec_tlu_br0_start_error_r),
|
|
.io_lsu_pmu_load_external_r(csr_io_lsu_pmu_load_external_r),
|
|
.io_lsu_pmu_store_external_r(csr_io_lsu_pmu_store_external_r),
|
|
.io_csr_pkt_csr_misa(csr_io_csr_pkt_csr_misa),
|
|
.io_csr_pkt_csr_mvendorid(csr_io_csr_pkt_csr_mvendorid),
|
|
.io_csr_pkt_csr_marchid(csr_io_csr_pkt_csr_marchid),
|
|
.io_csr_pkt_csr_mimpid(csr_io_csr_pkt_csr_mimpid),
|
|
.io_csr_pkt_csr_mhartid(csr_io_csr_pkt_csr_mhartid),
|
|
.io_csr_pkt_csr_mstatus(csr_io_csr_pkt_csr_mstatus),
|
|
.io_csr_pkt_csr_mtvec(csr_io_csr_pkt_csr_mtvec),
|
|
.io_csr_pkt_csr_mip(csr_io_csr_pkt_csr_mip),
|
|
.io_csr_pkt_csr_mie(csr_io_csr_pkt_csr_mie),
|
|
.io_csr_pkt_csr_mcyclel(csr_io_csr_pkt_csr_mcyclel),
|
|
.io_csr_pkt_csr_mcycleh(csr_io_csr_pkt_csr_mcycleh),
|
|
.io_csr_pkt_csr_minstretl(csr_io_csr_pkt_csr_minstretl),
|
|
.io_csr_pkt_csr_minstreth(csr_io_csr_pkt_csr_minstreth),
|
|
.io_csr_pkt_csr_mscratch(csr_io_csr_pkt_csr_mscratch),
|
|
.io_csr_pkt_csr_mepc(csr_io_csr_pkt_csr_mepc),
|
|
.io_csr_pkt_csr_mcause(csr_io_csr_pkt_csr_mcause),
|
|
.io_csr_pkt_csr_mscause(csr_io_csr_pkt_csr_mscause),
|
|
.io_csr_pkt_csr_mtval(csr_io_csr_pkt_csr_mtval),
|
|
.io_csr_pkt_csr_mrac(csr_io_csr_pkt_csr_mrac),
|
|
.io_csr_pkt_csr_mdseac(csr_io_csr_pkt_csr_mdseac),
|
|
.io_csr_pkt_csr_meihap(csr_io_csr_pkt_csr_meihap),
|
|
.io_csr_pkt_csr_meivt(csr_io_csr_pkt_csr_meivt),
|
|
.io_csr_pkt_csr_meipt(csr_io_csr_pkt_csr_meipt),
|
|
.io_csr_pkt_csr_meicurpl(csr_io_csr_pkt_csr_meicurpl),
|
|
.io_csr_pkt_csr_meicidpl(csr_io_csr_pkt_csr_meicidpl),
|
|
.io_csr_pkt_csr_dcsr(csr_io_csr_pkt_csr_dcsr),
|
|
.io_csr_pkt_csr_mcgc(csr_io_csr_pkt_csr_mcgc),
|
|
.io_csr_pkt_csr_mfdc(csr_io_csr_pkt_csr_mfdc),
|
|
.io_csr_pkt_csr_dpc(csr_io_csr_pkt_csr_dpc),
|
|
.io_csr_pkt_csr_mtsel(csr_io_csr_pkt_csr_mtsel),
|
|
.io_csr_pkt_csr_mtdata1(csr_io_csr_pkt_csr_mtdata1),
|
|
.io_csr_pkt_csr_mtdata2(csr_io_csr_pkt_csr_mtdata2),
|
|
.io_csr_pkt_csr_mhpmc3(csr_io_csr_pkt_csr_mhpmc3),
|
|
.io_csr_pkt_csr_mhpmc4(csr_io_csr_pkt_csr_mhpmc4),
|
|
.io_csr_pkt_csr_mhpmc5(csr_io_csr_pkt_csr_mhpmc5),
|
|
.io_csr_pkt_csr_mhpmc6(csr_io_csr_pkt_csr_mhpmc6),
|
|
.io_csr_pkt_csr_mhpmc3h(csr_io_csr_pkt_csr_mhpmc3h),
|
|
.io_csr_pkt_csr_mhpmc4h(csr_io_csr_pkt_csr_mhpmc4h),
|
|
.io_csr_pkt_csr_mhpmc5h(csr_io_csr_pkt_csr_mhpmc5h),
|
|
.io_csr_pkt_csr_mhpmc6h(csr_io_csr_pkt_csr_mhpmc6h),
|
|
.io_csr_pkt_csr_mhpme3(csr_io_csr_pkt_csr_mhpme3),
|
|
.io_csr_pkt_csr_mhpme4(csr_io_csr_pkt_csr_mhpme4),
|
|
.io_csr_pkt_csr_mhpme5(csr_io_csr_pkt_csr_mhpme5),
|
|
.io_csr_pkt_csr_mhpme6(csr_io_csr_pkt_csr_mhpme6),
|
|
.io_csr_pkt_csr_mcountinhibit(csr_io_csr_pkt_csr_mcountinhibit),
|
|
.io_csr_pkt_csr_mpmc(csr_io_csr_pkt_csr_mpmc),
|
|
.io_csr_pkt_csr_micect(csr_io_csr_pkt_csr_micect),
|
|
.io_csr_pkt_csr_miccmect(csr_io_csr_pkt_csr_miccmect),
|
|
.io_csr_pkt_csr_mdccmect(csr_io_csr_pkt_csr_mdccmect),
|
|
.io_csr_pkt_csr_mfdht(csr_io_csr_pkt_csr_mfdht),
|
|
.io_csr_pkt_csr_mfdhs(csr_io_csr_pkt_csr_mfdhs),
|
|
.io_csr_pkt_csr_dicawics(csr_io_csr_pkt_csr_dicawics),
|
|
.io_csr_pkt_csr_dicad0h(csr_io_csr_pkt_csr_dicad0h),
|
|
.io_csr_pkt_csr_dicad0(csr_io_csr_pkt_csr_dicad0),
|
|
.io_csr_pkt_csr_dicad1(csr_io_csr_pkt_csr_dicad1),
|
|
.io_mtdata1_t_0(csr_io_mtdata1_t_0),
|
|
.io_mtdata1_t_1(csr_io_mtdata1_t_1),
|
|
.io_mtdata1_t_2(csr_io_mtdata1_t_2),
|
|
.io_mtdata1_t_3(csr_io_mtdata1_t_3)
|
|
);
|
|
el2_dec_decode_csr_read csr_read ( // @[el2_dec_tlu_ctl.scala 1090:22]
|
|
.io_dec_csr_rdaddr_d(csr_read_io_dec_csr_rdaddr_d),
|
|
.io_csr_pkt_csr_misa(csr_read_io_csr_pkt_csr_misa),
|
|
.io_csr_pkt_csr_mvendorid(csr_read_io_csr_pkt_csr_mvendorid),
|
|
.io_csr_pkt_csr_marchid(csr_read_io_csr_pkt_csr_marchid),
|
|
.io_csr_pkt_csr_mimpid(csr_read_io_csr_pkt_csr_mimpid),
|
|
.io_csr_pkt_csr_mhartid(csr_read_io_csr_pkt_csr_mhartid),
|
|
.io_csr_pkt_csr_mstatus(csr_read_io_csr_pkt_csr_mstatus),
|
|
.io_csr_pkt_csr_mtvec(csr_read_io_csr_pkt_csr_mtvec),
|
|
.io_csr_pkt_csr_mip(csr_read_io_csr_pkt_csr_mip),
|
|
.io_csr_pkt_csr_mie(csr_read_io_csr_pkt_csr_mie),
|
|
.io_csr_pkt_csr_mcyclel(csr_read_io_csr_pkt_csr_mcyclel),
|
|
.io_csr_pkt_csr_mcycleh(csr_read_io_csr_pkt_csr_mcycleh),
|
|
.io_csr_pkt_csr_minstretl(csr_read_io_csr_pkt_csr_minstretl),
|
|
.io_csr_pkt_csr_minstreth(csr_read_io_csr_pkt_csr_minstreth),
|
|
.io_csr_pkt_csr_mscratch(csr_read_io_csr_pkt_csr_mscratch),
|
|
.io_csr_pkt_csr_mepc(csr_read_io_csr_pkt_csr_mepc),
|
|
.io_csr_pkt_csr_mcause(csr_read_io_csr_pkt_csr_mcause),
|
|
.io_csr_pkt_csr_mscause(csr_read_io_csr_pkt_csr_mscause),
|
|
.io_csr_pkt_csr_mtval(csr_read_io_csr_pkt_csr_mtval),
|
|
.io_csr_pkt_csr_mrac(csr_read_io_csr_pkt_csr_mrac),
|
|
.io_csr_pkt_csr_dmst(csr_read_io_csr_pkt_csr_dmst),
|
|
.io_csr_pkt_csr_mdseac(csr_read_io_csr_pkt_csr_mdseac),
|
|
.io_csr_pkt_csr_meihap(csr_read_io_csr_pkt_csr_meihap),
|
|
.io_csr_pkt_csr_meivt(csr_read_io_csr_pkt_csr_meivt),
|
|
.io_csr_pkt_csr_meipt(csr_read_io_csr_pkt_csr_meipt),
|
|
.io_csr_pkt_csr_meicurpl(csr_read_io_csr_pkt_csr_meicurpl),
|
|
.io_csr_pkt_csr_meicidpl(csr_read_io_csr_pkt_csr_meicidpl),
|
|
.io_csr_pkt_csr_dcsr(csr_read_io_csr_pkt_csr_dcsr),
|
|
.io_csr_pkt_csr_mcgc(csr_read_io_csr_pkt_csr_mcgc),
|
|
.io_csr_pkt_csr_mfdc(csr_read_io_csr_pkt_csr_mfdc),
|
|
.io_csr_pkt_csr_dpc(csr_read_io_csr_pkt_csr_dpc),
|
|
.io_csr_pkt_csr_mtsel(csr_read_io_csr_pkt_csr_mtsel),
|
|
.io_csr_pkt_csr_mtdata1(csr_read_io_csr_pkt_csr_mtdata1),
|
|
.io_csr_pkt_csr_mtdata2(csr_read_io_csr_pkt_csr_mtdata2),
|
|
.io_csr_pkt_csr_mhpmc3(csr_read_io_csr_pkt_csr_mhpmc3),
|
|
.io_csr_pkt_csr_mhpmc4(csr_read_io_csr_pkt_csr_mhpmc4),
|
|
.io_csr_pkt_csr_mhpmc5(csr_read_io_csr_pkt_csr_mhpmc5),
|
|
.io_csr_pkt_csr_mhpmc6(csr_read_io_csr_pkt_csr_mhpmc6),
|
|
.io_csr_pkt_csr_mhpmc3h(csr_read_io_csr_pkt_csr_mhpmc3h),
|
|
.io_csr_pkt_csr_mhpmc4h(csr_read_io_csr_pkt_csr_mhpmc4h),
|
|
.io_csr_pkt_csr_mhpmc5h(csr_read_io_csr_pkt_csr_mhpmc5h),
|
|
.io_csr_pkt_csr_mhpmc6h(csr_read_io_csr_pkt_csr_mhpmc6h),
|
|
.io_csr_pkt_csr_mhpme3(csr_read_io_csr_pkt_csr_mhpme3),
|
|
.io_csr_pkt_csr_mhpme4(csr_read_io_csr_pkt_csr_mhpme4),
|
|
.io_csr_pkt_csr_mhpme5(csr_read_io_csr_pkt_csr_mhpme5),
|
|
.io_csr_pkt_csr_mhpme6(csr_read_io_csr_pkt_csr_mhpme6),
|
|
.io_csr_pkt_csr_mcountinhibit(csr_read_io_csr_pkt_csr_mcountinhibit),
|
|
.io_csr_pkt_csr_mitctl0(csr_read_io_csr_pkt_csr_mitctl0),
|
|
.io_csr_pkt_csr_mitctl1(csr_read_io_csr_pkt_csr_mitctl1),
|
|
.io_csr_pkt_csr_mitb0(csr_read_io_csr_pkt_csr_mitb0),
|
|
.io_csr_pkt_csr_mitb1(csr_read_io_csr_pkt_csr_mitb1),
|
|
.io_csr_pkt_csr_mitcnt0(csr_read_io_csr_pkt_csr_mitcnt0),
|
|
.io_csr_pkt_csr_mitcnt1(csr_read_io_csr_pkt_csr_mitcnt1),
|
|
.io_csr_pkt_csr_mpmc(csr_read_io_csr_pkt_csr_mpmc),
|
|
.io_csr_pkt_csr_meicpct(csr_read_io_csr_pkt_csr_meicpct),
|
|
.io_csr_pkt_csr_micect(csr_read_io_csr_pkt_csr_micect),
|
|
.io_csr_pkt_csr_miccmect(csr_read_io_csr_pkt_csr_miccmect),
|
|
.io_csr_pkt_csr_mdccmect(csr_read_io_csr_pkt_csr_mdccmect),
|
|
.io_csr_pkt_csr_mfdht(csr_read_io_csr_pkt_csr_mfdht),
|
|
.io_csr_pkt_csr_mfdhs(csr_read_io_csr_pkt_csr_mfdhs),
|
|
.io_csr_pkt_csr_dicawics(csr_read_io_csr_pkt_csr_dicawics),
|
|
.io_csr_pkt_csr_dicad0h(csr_read_io_csr_pkt_csr_dicad0h),
|
|
.io_csr_pkt_csr_dicad0(csr_read_io_csr_pkt_csr_dicad0),
|
|
.io_csr_pkt_csr_dicad1(csr_read_io_csr_pkt_csr_dicad1),
|
|
.io_csr_pkt_csr_dicago(csr_read_io_csr_pkt_csr_dicago),
|
|
.io_csr_pkt_presync(csr_read_io_csr_pkt_presync),
|
|
.io_csr_pkt_postsync(csr_read_io_csr_pkt_postsync),
|
|
.io_csr_pkt_legal(csr_read_io_csr_pkt_legal)
|
|
);
|
|
assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 568:23]
|
|
assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[el2_dec_tlu_ctl.scala 569:23]
|
|
assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 550:41]
|
|
assign io_dec_tlu_debug_mode = debug_mode_status; // @[el2_dec_tlu_ctl.scala 551:41]
|
|
assign io_dec_tlu_resume_ack = _T_190; // @[el2_dec_tlu_ctl.scala 534:41]
|
|
assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 549:41]
|
|
assign io_dec_tlu_flush_noredir_r = _T_205 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 555:30]
|
|
assign io_dec_tlu_mpc_halted_only = _T_65; // @[el2_dec_tlu_ctl.scala 449:41]
|
|
assign io_dec_tlu_flush_leak_one_r = _T_233 & _T_234; // @[el2_dec_tlu_ctl.scala 564:31]
|
|
assign io_dec_tlu_flush_err_r = io_dec_tlu_flush_lower_r & _T_433; // @[el2_dec_tlu_ctl.scala 565:26]
|
|
assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 557:27]
|
|
assign io_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[el2_dec_tlu_ctl.scala 956:44]
|
|
assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[el2_dec_tlu_ctl.scala 962:40]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec_tlu_ctl.scala 961:44]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec_tlu_ctl.scala 961:44]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec_tlu_ctl.scala 961:44]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec_tlu_ctl.scala 961:44]
|
|
assign io_o_cpu_halt_status = _T_353; // @[el2_dec_tlu_ctl.scala 654:41]
|
|
assign io_o_cpu_halt_ack = _T_354; // @[el2_dec_tlu_ctl.scala 655:49]
|
|
assign io_o_cpu_run_ack = _T_355; // @[el2_dec_tlu_ctl.scala 656:49]
|
|
assign io_o_debug_mode_status = debug_mode_status; // @[el2_dec_tlu_ctl.scala 677:26]
|
|
assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[el2_dec_tlu_ctl.scala 474:25]
|
|
assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 475:25]
|
|
assign io_debug_brkpt_status = debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 476:25]
|
|
assign io_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[el2_dec_tlu_ctl.scala 955:44]
|
|
assign io_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[el2_dec_tlu_ctl.scala 957:44]
|
|
assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 977:40]
|
|
assign io_dec_csr_legal_d = _T_887 & _T_894; // @[el2_dec_tlu_ctl.scala 1101:22]
|
|
assign io_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[el2_dec_tlu_ctl.scala 733:49]
|
|
assign io_dec_tlu_br0_r_pkt_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:49]
|
|
assign io_dec_tlu_br0_r_pkt_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49]
|
|
assign io_dec_tlu_br0_r_pkt_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:41]
|
|
assign io_dec_tlu_br0_r_pkt_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:49]
|
|
assign io_dec_tlu_br0_r_pkt_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:49]
|
|
assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[el2_dec_tlu_ctl.scala 409:33]
|
|
assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 881:33]
|
|
assign io_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 708:28]
|
|
assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 415:33]
|
|
assign io_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 882:33]
|
|
assign io_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[el2_dec_tlu_ctl.scala 883:33]
|
|
assign io_dec_tlu_fence_i_r = _T_492 & _T_470; // @[el2_dec_tlu_ctl.scala 753:24]
|
|
assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[el2_dec_tlu_ctl.scala 979:40]
|
|
assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[el2_dec_tlu_ctl.scala 560:28]
|
|
assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[el2_dec_tlu_ctl.scala 1094:25]
|
|
assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 1095:25]
|
|
assign io_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[el2_dec_tlu_ctl.scala 980:40]
|
|
assign io_dec_tlu_force_halt = _T_33; // @[el2_dec_tlu_ctl.scala 411:41]
|
|
assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[el2_dec_tlu_ctl.scala 965:40]
|
|
assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[el2_dec_tlu_ctl.scala 966:40]
|
|
assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[el2_dec_tlu_ctl.scala 967:40]
|
|
assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[el2_dec_tlu_ctl.scala 968:40]
|
|
assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec_tlu_ctl.scala 959:44]
|
|
assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[el2_dec_tlu_ctl.scala 960:44]
|
|
assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[el2_dec_tlu_ctl.scala 958:44]
|
|
assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[el2_dec_tlu_ctl.scala 964:40]
|
|
assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[el2_dec_tlu_ctl.scala 963:40]
|
|
assign io_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[el2_dec_tlu_ctl.scala 985:40]
|
|
assign io_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec_tlu_ctl.scala 983:40]
|
|
assign io_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[el2_dec_tlu_ctl.scala 984:40]
|
|
assign io_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[el2_dec_tlu_ctl.scala 982:40]
|
|
assign io_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[el2_dec_tlu_ctl.scala 981:40]
|
|
assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[el2_dec_tlu_ctl.scala 978:40]
|
|
assign io_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[el2_dec_tlu_ctl.scala 986:40]
|
|
assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[el2_dec_tlu_ctl.scala 969:40]
|
|
assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 970:40]
|
|
assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[el2_dec_tlu_ctl.scala 972:40]
|
|
assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[el2_dec_tlu_ctl.scala 974:40]
|
|
assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[el2_dec_tlu_ctl.scala 975:40]
|
|
assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[el2_dec_tlu_ctl.scala 976:40]
|
|
assign int_timers_clock = clock;
|
|
assign int_timers_reset = reset;
|
|
assign int_timers_io_free_clk = io_free_clk; // @[el2_dec_tlu_ctl.scala 356:57]
|
|
assign int_timers_io_scan_mode = io_scan_mode; // @[el2_dec_tlu_ctl.scala 357:57]
|
|
assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 358:49]
|
|
assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 360:49]
|
|
assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 361:49]
|
|
assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 362:49]
|
|
assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 363:49]
|
|
assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[el2_dec_tlu_ctl.scala 364:57]
|
|
assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[el2_dec_tlu_ctl.scala 365:57]
|
|
assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 366:49]
|
|
assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 367:49]
|
|
assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 368:41]
|
|
assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 369:41]
|
|
assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[el2_dec_tlu_ctl.scala 370:41]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_io_en = dec_csr_wen_r_mod | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_1_io_en = _T_11 | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_2_io_en = e4e5_valid | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_3_io_en = e4e5_valid | flush_clkvalid; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign csr_clock = clock;
|
|
assign csr_reset = reset;
|
|
assign csr_io_free_clk = io_free_clk; // @[el2_dec_tlu_ctl.scala 898:44]
|
|
assign csr_io_active_clk = io_active_clk; // @[el2_dec_tlu_ctl.scala 899:44]
|
|
assign csr_io_scan_mode = io_scan_mode; // @[el2_dec_tlu_ctl.scala 900:44]
|
|
assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 901:44]
|
|
assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 902:44]
|
|
assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 903:44]
|
|
assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 904:44]
|
|
assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 905:44]
|
|
assign csr_io_ifu_ic_debug_rd_data_valid = io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 906:44]
|
|
assign csr_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 907:44]
|
|
assign csr_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[el2_dec_tlu_ctl.scala 908:44]
|
|
assign csr_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec_tlu_ctl.scala 909:44]
|
|
assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec_tlu_ctl.scala 910:44]
|
|
assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[el2_dec_tlu_ctl.scala 911:44]
|
|
assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[el2_dec_tlu_ctl.scala 912:44]
|
|
assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[el2_dec_tlu_ctl.scala 913:44]
|
|
assign csr_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[el2_dec_tlu_ctl.scala 914:44]
|
|
assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[el2_dec_tlu_ctl.scala 915:44]
|
|
assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec_tlu_ctl.scala 915:44]
|
|
assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec_tlu_ctl.scala 915:44]
|
|
assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[el2_dec_tlu_ctl.scala 915:44]
|
|
assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 915:44]
|
|
assign csr_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 916:44]
|
|
assign csr_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[el2_dec_tlu_ctl.scala 917:44]
|
|
assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[el2_dec_tlu_ctl.scala 918:44]
|
|
assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[el2_dec_tlu_ctl.scala 919:44]
|
|
assign csr_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 920:44]
|
|
assign csr_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[el2_dec_tlu_ctl.scala 921:44]
|
|
assign csr_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[el2_dec_tlu_ctl.scala 922:44]
|
|
assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[el2_dec_tlu_ctl.scala 923:44]
|
|
assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 924:44]
|
|
assign csr_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[el2_dec_tlu_ctl.scala 925:44]
|
|
assign csr_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[el2_dec_tlu_ctl.scala 926:44]
|
|
assign csr_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 927:44]
|
|
assign csr_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 928:44]
|
|
assign csr_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 929:44]
|
|
assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 930:44]
|
|
assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 931:44]
|
|
assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 933:44]
|
|
assign csr_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 934:44]
|
|
assign csr_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 935:44]
|
|
assign csr_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 936:44]
|
|
assign csr_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[el2_dec_tlu_ctl.scala 937:44]
|
|
assign csr_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 938:44]
|
|
assign csr_io_ifu_ic_debug_rd_data = io_ifu_ic_debug_rd_data; // @[el2_dec_tlu_ctl.scala 939:44]
|
|
assign csr_io_pic_pl = io_pic_pl; // @[el2_dec_tlu_ctl.scala 940:44]
|
|
assign csr_io_pic_claimid = io_pic_claimid; // @[el2_dec_tlu_ctl.scala 941:44]
|
|
assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 942:44]
|
|
assign csr_io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_addr_any; // @[el2_dec_tlu_ctl.scala 943:44]
|
|
assign csr_io_lsu_imprecise_error_load_any = io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 944:44]
|
|
assign csr_io_lsu_imprecise_error_store_any = io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 945:44]
|
|
assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[el2_dec_tlu_ctl.scala 946:44 el2_dec_tlu_ctl.scala 987:44]
|
|
assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[el2_dec_tlu_ctl.scala 947:44 el2_dec_tlu_ctl.scala 988:44]
|
|
assign csr_io_mexintpend = io_mexintpend; // @[el2_dec_tlu_ctl.scala 948:44 el2_dec_tlu_ctl.scala 989:44]
|
|
assign csr_io_exu_npc_r = io_exu_npc_r; // @[el2_dec_tlu_ctl.scala 949:44 el2_dec_tlu_ctl.scala 990:44]
|
|
assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 950:44 el2_dec_tlu_ctl.scala 991:44]
|
|
assign csr_io_rst_vec = io_rst_vec; // @[el2_dec_tlu_ctl.scala 951:44 el2_dec_tlu_ctl.scala 992:44]
|
|
assign csr_io_core_id = io_core_id; // @[el2_dec_tlu_ctl.scala 952:44 el2_dec_tlu_ctl.scala 993:44]
|
|
assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 953:44 el2_dec_tlu_ctl.scala 994:44]
|
|
assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 954:44 el2_dec_tlu_ctl.scala 995:44]
|
|
assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[el2_dec_tlu_ctl.scala 998:39]
|
|
assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 999:39]
|
|
assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1000:39]
|
|
assign csr_io_mret_r = _T_487 & _T_470; // @[el2_dec_tlu_ctl.scala 1001:39]
|
|
assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 1002:39]
|
|
assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 1003:39]
|
|
assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 1004:39]
|
|
assign csr_io_timer_int_sync = syncro_ff[5]; // @[el2_dec_tlu_ctl.scala 1005:39]
|
|
assign csr_io_soft_int_sync = syncro_ff[4]; // @[el2_dec_tlu_ctl.scala 1006:39]
|
|
assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[el2_dec_tlu_ctl.scala 1007:39]
|
|
assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[el2_dec_tlu_ctl.scala 1008:39]
|
|
assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1009:39]
|
|
assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1010:39]
|
|
assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1011:39]
|
|
assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 1012:39]
|
|
assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 1013:39]
|
|
assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[el2_dec_tlu_ctl.scala 1014:39]
|
|
assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 1015:39]
|
|
assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[el2_dec_tlu_ctl.scala 1016:39]
|
|
assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 1017:39]
|
|
assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[el2_dec_tlu_ctl.scala 1018:39]
|
|
assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[el2_dec_tlu_ctl.scala 1019:39]
|
|
assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 1020:39]
|
|
assign csr_io_inst_acc_r = _T_511 & _T_465; // @[el2_dec_tlu_ctl.scala 1021:39]
|
|
assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[el2_dec_tlu_ctl.scala 1022:39]
|
|
assign csr_io_take_nmi = _T_756 & _T_760; // @[el2_dec_tlu_ctl.scala 1023:39]
|
|
assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[el2_dec_tlu_ctl.scala 1024:39]
|
|
assign csr_io_exc_cause_r = _T_603 | _T_591; // @[el2_dec_tlu_ctl.scala 1025:39]
|
|
assign csr_io_i0_valid_wb = i0_valid_wb; // @[el2_dec_tlu_ctl.scala 1026:39]
|
|
assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1027:39]
|
|
assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1028:39]
|
|
assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 1029:39]
|
|
assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1030:39]
|
|
assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 1031:39]
|
|
assign csr_io_exc_cause_wb = exc_cause_wb; // @[el2_dec_tlu_ctl.scala 1032:39]
|
|
assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[el2_dec_tlu_ctl.scala 1033:39]
|
|
assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[el2_dec_tlu_ctl.scala 1034:39]
|
|
assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 1035:39]
|
|
assign csr_io_ebreak_r = _T_469 & _T_470; // @[el2_dec_tlu_ctl.scala 1036:39]
|
|
assign csr_io_ecall_r = _T_475 & _T_470; // @[el2_dec_tlu_ctl.scala 1037:39]
|
|
assign csr_io_illegal_r = _T_481 & _T_470; // @[el2_dec_tlu_ctl.scala 1038:39]
|
|
assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 1039:39]
|
|
assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 1040:39]
|
|
assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 1041:39]
|
|
assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 1042:39]
|
|
assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 1043:39]
|
|
assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 1044:39]
|
|
assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 1045:39]
|
|
assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 1046:39]
|
|
assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 1047:39]
|
|
assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1048:39]
|
|
assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[el2_dec_tlu_ctl.scala 1049:39]
|
|
assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 1050:51]
|
|
assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 1051:47]
|
|
assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 1052:43]
|
|
assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 1053:43]
|
|
assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 1054:43]
|
|
assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 1055:39]
|
|
assign csr_io_debug_halt_req = _T_114 & _T_107; // @[el2_dec_tlu_ctl.scala 1056:51]
|
|
assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[el2_dec_tlu_ctl.scala 1057:39]
|
|
assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[el2_dec_tlu_ctl.scala 1058:39]
|
|
assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 1059:39]
|
|
assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[el2_dec_tlu_ctl.scala 1060:39]
|
|
assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[el2_dec_tlu_ctl.scala 1061:39]
|
|
assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[el2_dec_tlu_ctl.scala 1062:39]
|
|
assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 1063:39]
|
|
assign csr_io_take_timer_int = _T_703 & _T_704; // @[el2_dec_tlu_ctl.scala 1064:39]
|
|
assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[el2_dec_tlu_ctl.scala 1065:39]
|
|
assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[el2_dec_tlu_ctl.scala 1066:39]
|
|
assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[el2_dec_tlu_ctl.scala 1067:39]
|
|
assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 1068:39]
|
|
assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 1069:39]
|
|
assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 1070:39]
|
|
assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 1071:39]
|
|
assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 1072:39]
|
|
assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1073:39]
|
|
assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 1091:31]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
dbg_halt_state_f = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
mpc_halt_state_f = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
_T_8 = _RAND_2[6:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
syncro_ff = _RAND_3[6:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
lsu_exc_valid_r_d1 = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
e5_valid = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
debug_mode_status = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
i_cpu_run_req_d1_raw = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
nmi_int_delayed = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
mdseac_locked_f = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
nmi_int_detected_f = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
take_nmi_r_d1 = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
take_ext_int_start_d3 = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
int_timer0_int_hold_f = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
int_timer1_int_hold_f = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
i_cpu_halt_req_d1 = _RAND_15[0:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
dbg_halt_req_held = _RAND_16[0:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
ext_int_freeze_d1 = _RAND_17[0:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
reset_detect = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
reset_detected = _RAND_19[0:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
dcsr_single_step_done_f = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
trigger_hit_dmode_r_d1 = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
ebreak_to_debug_mode_r_d1 = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
debug_halt_req_f = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
lsu_idle_any_f = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
ifu_miss_state_idle_f = _RAND_25[0:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
debug_halt_req_d1 = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
dec_tlu_flush_noredir_r_d1 = _RAND_27[0:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
dec_tlu_flush_pause_r_d1 = _RAND_28[0:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
take_ext_int_start_d1 = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
halt_taken_f = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
dbg_tlu_halted_f = _RAND_31[0:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
pmu_fw_tlu_halted_f = _RAND_32[0:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
interrupt_valid_r_d1 = _RAND_33[0:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
debug_resume_req_f = _RAND_34[0:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
dcsr_single_step_running_f = _RAND_35[0:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
pmu_fw_halt_req_f = _RAND_36[0:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
internal_pmu_fw_halt_mode_f = _RAND_37[0:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
tlu_flush_lower_r_d1 = _RAND_38[0:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
ic_perr_r_d1 = _RAND_39[0:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
iccm_sbecc_r_d1 = _RAND_40[0:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
request_debug_mode_r_d1 = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
iccm_repair_state_d1 = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
dec_pause_state_f = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
dec_tlu_wr_pause_r_d1 = _RAND_44[0:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
exc_or_int_valid_r_d1 = _RAND_45[0:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
pause_expired_wb = _RAND_46[0:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
lsu_pmu_load_external_r = _RAND_47[0:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
lsu_pmu_store_external_r = _RAND_48[0:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
_T_32 = _RAND_49[0:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
internal_dbg_halt_mode_f2 = _RAND_50[0:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
_T_33 = _RAND_51[0:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
nmi_lsu_load_type_f = _RAND_52[0:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
nmi_lsu_store_type_f = _RAND_53[0:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
mpc_debug_halt_req_sync_f = _RAND_54[0:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
mpc_debug_run_req_sync_f = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
mpc_run_state_f = _RAND_56[0:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
debug_brkpt_status_f = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
mpc_debug_halt_ack_f = _RAND_58[0:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
mpc_debug_run_ack_f = _RAND_59[0:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
dbg_run_state_f = _RAND_60[0:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
_T_65 = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
request_debug_mode_done_f = _RAND_62[0:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
_T_190 = _RAND_63[0:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
_T_353 = _RAND_64[0:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
_T_354 = _RAND_65[0:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
_T_355 = _RAND_66[0:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
lsu_single_ecc_error_r_d1 = _RAND_67[0:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
lsu_i0_exc_r_d1 = _RAND_68[0:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
take_ext_int_start_d2 = _RAND_69[0:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
tlu_flush_path_r_d1 = _RAND_70[30:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
i0_exception_valid_r_d1 = _RAND_71[0:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
exc_cause_wb = _RAND_72[4:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
i0_valid_wb = _RAND_73[0:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
trigger_hit_r_d1 = _RAND_74[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
dbg_halt_state_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_halt_state_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_8 = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
syncro_ff = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_exc_valid_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
e5_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
debug_mode_status = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i_cpu_run_req_d1_raw = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
nmi_int_delayed = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mdseac_locked_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
nmi_int_detected_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
take_nmi_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
take_ext_int_start_d3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
int_timer0_int_hold_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
int_timer1_int_hold_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i_cpu_halt_req_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dbg_halt_req_held = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ext_int_freeze_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
reset_detect = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
reset_detected = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dcsr_single_step_done_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
trigger_hit_dmode_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ebreak_to_debug_mode_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
debug_halt_req_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_idle_any_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_miss_state_idle_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
debug_halt_req_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_tlu_flush_noredir_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_tlu_flush_pause_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
take_ext_int_start_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
halt_taken_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dbg_tlu_halted_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
pmu_fw_tlu_halted_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
interrupt_valid_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
debug_resume_req_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dcsr_single_step_running_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
pmu_fw_halt_req_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
internal_pmu_fw_halt_mode_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
tlu_flush_lower_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_perr_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_sbecc_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
request_debug_mode_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_repair_state_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_pause_state_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_tlu_wr_pause_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
exc_or_int_valid_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
pause_expired_wb = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_pmu_load_external_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_pmu_store_external_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_32 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
internal_dbg_halt_mode_f2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_33 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
nmi_lsu_load_type_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
nmi_lsu_store_type_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_debug_halt_req_sync_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_debug_run_req_sync_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_run_state_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
debug_brkpt_status_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_debug_halt_ack_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_debug_run_ack_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dbg_run_state_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_65 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
request_debug_mode_done_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_190 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_353 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_354 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_355 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_single_ecc_error_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_i0_exc_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
take_ext_int_start_d2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
tlu_flush_path_r_d1 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_exception_valid_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
exc_cause_wb = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_valid_wb = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
trigger_hit_r_d1 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dbg_halt_state_f <= 1'h0;
|
|
end else begin
|
|
dbg_halt_state_f <= _T_83 & _T_84;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_halt_state_f <= 1'h0;
|
|
end else begin
|
|
mpc_halt_state_f <= _T_71 & _T_72;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_8 <= 7'h0;
|
|
end else begin
|
|
_T_8 <= {_T_6,_T_3};
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
syncro_ff <= 7'h0;
|
|
end else begin
|
|
syncro_ff <= _T_8;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_exc_valid_r_d1 <= 1'h0;
|
|
end else begin
|
|
lsu_exc_valid_r_d1 <= _T_405 & _T_470;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
e5_valid <= 1'h0;
|
|
end else begin
|
|
e5_valid <= io_dec_tlu_i0_valid_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
debug_mode_status <= 1'h0;
|
|
end else begin
|
|
debug_mode_status <= debug_halt_req_ns | _T_160;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
i_cpu_run_req_d1_raw <= 1'h0;
|
|
end else begin
|
|
i_cpu_run_req_d1_raw <= _T_351 & _T_107;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
nmi_int_delayed <= 1'h0;
|
|
end else begin
|
|
nmi_int_delayed <= syncro_ff[6];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mdseac_locked_f <= 1'h0;
|
|
end else begin
|
|
mdseac_locked_f <= csr_io_mdseac_locked_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
nmi_int_detected_f <= 1'h0;
|
|
end else begin
|
|
nmi_int_detected_f <= _T_42 | _T_44;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
take_nmi_r_d1 <= 1'h0;
|
|
end else begin
|
|
take_nmi_r_d1 <= _T_756 & _T_760;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
take_ext_int_start_d3 <= 1'h0;
|
|
end else begin
|
|
take_ext_int_start_d3 <= take_ext_int_start_d2;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
int_timer0_int_hold_f <= 1'h0;
|
|
end else begin
|
|
int_timer0_int_hold_f <= _T_644 | _T_651;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
int_timer1_int_hold_f <= 1'h0;
|
|
end else begin
|
|
int_timer1_int_hold_f <= _T_654 | _T_661;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
i_cpu_halt_req_d1 <= 1'h0;
|
|
end else begin
|
|
i_cpu_halt_req_d1 <= _T_347 & _T_107;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dbg_halt_req_held <= 1'h0;
|
|
end else begin
|
|
dbg_halt_req_held <= _T_106 & ext_int_freeze_d1;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ext_int_freeze_d1 <= 1'h0;
|
|
end else begin
|
|
ext_int_freeze_d1 <= _T_682 | take_ext_int_start_d3;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
reset_detect <= 1'h0;
|
|
end else begin
|
|
reset_detect <= 1'h1;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
reset_detected <= 1'h0;
|
|
end else begin
|
|
reset_detected <= reset_detect;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dcsr_single_step_done_f <= 1'h0;
|
|
end else begin
|
|
dcsr_single_step_done_f <= _T_174 & _T_470;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
trigger_hit_dmode_r_d1 <= 1'h0;
|
|
end else begin
|
|
trigger_hit_dmode_r_d1 <= i0_trigger_hit_raw_r & i0_trigger_action_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ebreak_to_debug_mode_r_d1 <= 1'h0;
|
|
end else begin
|
|
ebreak_to_debug_mode_r_d1 <= _T_519 & _T_470;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
debug_halt_req_f <= 1'h0;
|
|
end else begin
|
|
debug_halt_req_f <= enter_debug_halt_req | _T_168;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_idle_any_f <= 1'h0;
|
|
end else begin
|
|
lsu_idle_any_f <= io_lsu_idle_any;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_miss_state_idle_f <= 1'h0;
|
|
end else begin
|
|
ifu_miss_state_idle_f <= io_ifu_miss_state_idle;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
debug_halt_req_d1 <= 1'h0;
|
|
end else begin
|
|
debug_halt_req_d1 <= _T_114 & _T_107;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dec_tlu_flush_noredir_r_d1 <= 1'h0;
|
|
end else begin
|
|
dec_tlu_flush_noredir_r_d1 <= io_dec_tlu_flush_noredir_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dec_tlu_flush_pause_r_d1 <= 1'h0;
|
|
end else begin
|
|
dec_tlu_flush_pause_r_d1 <= io_dec_tlu_flush_pause_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
take_ext_int_start_d1 <= 1'h0;
|
|
end else begin
|
|
take_ext_int_start_d1 <= ext_int_ready & _T_704;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
halt_taken_f <= 1'h0;
|
|
end else begin
|
|
halt_taken_f <= _T_135 | _T_141;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dbg_tlu_halted_f <= 1'h0;
|
|
end else begin
|
|
dbg_tlu_halted_f <= _T_164 | _T_166;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
pmu_fw_tlu_halted_f <= 1'h0;
|
|
end else begin
|
|
pmu_fw_tlu_halted_f <= _T_377 & _T_378;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
interrupt_valid_r_d1 <= 1'h0;
|
|
end else begin
|
|
interrupt_valid_r_d1 <= _T_766 | take_int_timer1_int;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
debug_resume_req_f <= 1'h0;
|
|
end else begin
|
|
debug_resume_req_f <= _T_165 & _T_121;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dcsr_single_step_running_f <= 1'h0;
|
|
end else begin
|
|
dcsr_single_step_running_f <= _T_177 | _T_179;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
pmu_fw_halt_req_f <= 1'h0;
|
|
end else begin
|
|
pmu_fw_halt_req_f <= _T_363 & _T_378;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
internal_pmu_fw_halt_mode_f <= 1'h0;
|
|
end else begin
|
|
internal_pmu_fw_halt_mode_f <= pmu_fw_halt_req_ns | _T_369;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
tlu_flush_lower_r_d1 <= 1'h0;
|
|
end else begin
|
|
tlu_flush_lower_r_d1 <= _T_801 | take_ext_int_start;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_perr_r_d1 <= 1'h0;
|
|
end else begin
|
|
ic_perr_r_d1 <= _T_499 & _T_500;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_sbecc_r_d1 <= 1'h0;
|
|
end else begin
|
|
iccm_sbecc_r_d1 <= _T_506 & _T_500;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
request_debug_mode_r_d1 <= 1'h0;
|
|
end else begin
|
|
request_debug_mode_r_d1 <= _T_180 | _T_182;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_repair_state_d1 <= 1'h0;
|
|
end else begin
|
|
iccm_repair_state_d1 <= iccm_sbecc_r_d1 | _T_442;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dec_pause_state_f <= 1'h0;
|
|
end else begin
|
|
dec_pause_state_f <= io_dec_pause_state;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dec_tlu_wr_pause_r_d1 <= 1'h0;
|
|
end else begin
|
|
dec_tlu_wr_pause_r_d1 <= io_dec_tlu_wr_pause_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
exc_or_int_valid_r_d1 <= 1'h0;
|
|
end else begin
|
|
exc_or_int_valid_r_d1 <= _T_855 | mepc_trigger_hit_sel_pc_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
pause_expired_wb <= 1'h0;
|
|
end else begin
|
|
pause_expired_wb <= _T_227 & _T_228;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_pmu_load_external_r <= 1'h0;
|
|
end else begin
|
|
lsu_pmu_load_external_r <= io_lsu_pmu_load_external_m;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_pmu_store_external_r <= 1'h0;
|
|
end else begin
|
|
lsu_pmu_store_external_r <= io_lsu_pmu_store_external_m;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_32 <= 1'h0;
|
|
end else begin
|
|
_T_32 <= _T_427 | i0_trigger_hit_raw_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
internal_dbg_halt_mode_f2 <= 1'h0;
|
|
end else begin
|
|
internal_dbg_halt_mode_f2 <= debug_mode_status;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_33 <= 1'h0;
|
|
end else begin
|
|
_T_33 <= csr_io_force_halt;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
nmi_lsu_load_type_f <= 1'h0;
|
|
end else begin
|
|
nmi_lsu_load_type_f <= _T_50 | _T_52;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
nmi_lsu_store_type_f <= 1'h0;
|
|
end else begin
|
|
nmi_lsu_store_type_f <= _T_58 | _T_60;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_debug_halt_req_sync_f <= 1'h0;
|
|
end else begin
|
|
mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync_raw & _T_107;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_debug_run_req_sync_f <= 1'h0;
|
|
end else begin
|
|
mpc_debug_run_req_sync_f <= syncro_ff[0];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_run_state_f <= 1'h0;
|
|
end else begin
|
|
mpc_run_state_f <= _T_76 & _T_78;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
debug_brkpt_status_f <= 1'h0;
|
|
end else begin
|
|
debug_brkpt_status_f <= _T_92 & _T_94;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_debug_halt_ack_f <= 1'h0;
|
|
end else begin
|
|
mpc_debug_halt_ack_f <= _T_97 & core_empty;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_debug_run_ack_f <= 1'h0;
|
|
end else begin
|
|
mpc_debug_run_ack_f <= _T_102 | _T_103;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dbg_run_state_f <= 1'h0;
|
|
end else begin
|
|
dbg_run_state_f <= _T_86 & _T_78;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_65 <= 1'h0;
|
|
end else begin
|
|
_T_65 <= _T & mpc_halt_state_f;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
request_debug_mode_done_f <= 1'h0;
|
|
end else begin
|
|
request_debug_mode_done_f <= _T_183 & _T_136;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_190 <= 1'h0;
|
|
end else begin
|
|
_T_190 <= _T_170 & dbg_run_state_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_353 <= 1'h0;
|
|
end else begin
|
|
_T_353 <= _T_376 | _T_386;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_354 <= 1'h0;
|
|
end else begin
|
|
_T_354 <= i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_355 <= 1'h0;
|
|
end else begin
|
|
_T_355 <= _T_388 | _T_389;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_single_ecc_error_r_d1 <= 1'h0;
|
|
end else begin
|
|
lsu_single_ecc_error_r_d1 <= io_lsu_single_ecc_error_incr;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_i0_exc_r_d1 <= 1'h0;
|
|
end else begin
|
|
lsu_i0_exc_r_d1 <= _T_405 & _T_470;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
take_ext_int_start_d2 <= 1'h0;
|
|
end else begin
|
|
take_ext_int_start_d2 <= take_ext_int_start_d1;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
tlu_flush_path_r_d1 <= 31'h0;
|
|
end else if (take_reset) begin
|
|
tlu_flush_path_r_d1 <= io_rst_vec;
|
|
end else begin
|
|
tlu_flush_path_r_d1 <= _T_852;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_exception_valid_r_d1 <= 1'h0;
|
|
end else begin
|
|
i0_exception_valid_r_d1 <= _T_527 & _T_528;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
exc_cause_wb <= 5'h0;
|
|
end else begin
|
|
exc_cause_wb <= _T_603 | _T_591;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_valid_wb <= 1'h0;
|
|
end else begin
|
|
i0_valid_wb <= tlu_i0_commit_cmt & _T_860;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
trigger_hit_r_d1 <= 1'h0;
|
|
end else begin
|
|
trigger_hit_r_d1 <= |i0_trigger_chain_masked_r;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_dec_trigger(
|
|
input io_trigger_pkt_any_0_select,
|
|
input io_trigger_pkt_any_0_match_pkt,
|
|
input io_trigger_pkt_any_0_execute,
|
|
input io_trigger_pkt_any_0_m,
|
|
input [31:0] io_trigger_pkt_any_0_tdata2,
|
|
input io_trigger_pkt_any_1_select,
|
|
input io_trigger_pkt_any_1_match_pkt,
|
|
input io_trigger_pkt_any_1_execute,
|
|
input io_trigger_pkt_any_1_m,
|
|
input [31:0] io_trigger_pkt_any_1_tdata2,
|
|
input io_trigger_pkt_any_2_select,
|
|
input io_trigger_pkt_any_2_match_pkt,
|
|
input io_trigger_pkt_any_2_execute,
|
|
input io_trigger_pkt_any_2_m,
|
|
input [31:0] io_trigger_pkt_any_2_tdata2,
|
|
input io_trigger_pkt_any_3_select,
|
|
input io_trigger_pkt_any_3_match_pkt,
|
|
input io_trigger_pkt_any_3_execute,
|
|
input io_trigger_pkt_any_3_m,
|
|
input [31:0] io_trigger_pkt_any_3_tdata2,
|
|
input [30:0] io_dec_i0_pc_d,
|
|
output [3:0] io_dec_i0_trigger_match_d
|
|
);
|
|
wire _T = ~io_trigger_pkt_any_0_select; // @[el2_dec_trigger.scala 14:63]
|
|
wire _T_1 = _T & io_trigger_pkt_any_0_execute; // @[el2_dec_trigger.scala 14:93]
|
|
wire [9:0] _T_11 = {_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_20 = {_T_11,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_29 = {_T_20,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_33 = {_T_29,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_35 = {io_dec_i0_pc_d,io_trigger_pkt_any_0_tdata2[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] dec_i0_match_data_0 = _T_33 & _T_35; // @[el2_dec_trigger.scala 14:127]
|
|
wire _T_37 = ~io_trigger_pkt_any_1_select; // @[el2_dec_trigger.scala 14:63]
|
|
wire _T_38 = _T_37 & io_trigger_pkt_any_1_execute; // @[el2_dec_trigger.scala 14:93]
|
|
wire [9:0] _T_48 = {_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_57 = {_T_48,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_66 = {_T_57,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_70 = {_T_66,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_72 = {io_dec_i0_pc_d,io_trigger_pkt_any_1_tdata2[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] dec_i0_match_data_1 = _T_70 & _T_72; // @[el2_dec_trigger.scala 14:127]
|
|
wire _T_74 = ~io_trigger_pkt_any_2_select; // @[el2_dec_trigger.scala 14:63]
|
|
wire _T_75 = _T_74 & io_trigger_pkt_any_2_execute; // @[el2_dec_trigger.scala 14:93]
|
|
wire [9:0] _T_85 = {_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_94 = {_T_85,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_103 = {_T_94,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_107 = {_T_103,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_109 = {io_dec_i0_pc_d,io_trigger_pkt_any_2_tdata2[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] dec_i0_match_data_2 = _T_107 & _T_109; // @[el2_dec_trigger.scala 14:127]
|
|
wire _T_111 = ~io_trigger_pkt_any_3_select; // @[el2_dec_trigger.scala 14:63]
|
|
wire _T_112 = _T_111 & io_trigger_pkt_any_3_execute; // @[el2_dec_trigger.scala 14:93]
|
|
wire [9:0] _T_122 = {_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_131 = {_T_122,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_140 = {_T_131,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_144 = {_T_140,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_146 = {io_dec_i0_pc_d,io_trigger_pkt_any_3_tdata2[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[el2_dec_trigger.scala 14:127]
|
|
wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_dec_trigger.scala 15:83]
|
|
wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45]
|
|
wire _T_152 = ~_T_151; // @[el2_lib.scala 241:39]
|
|
wire _T_153 = io_trigger_pkt_any_0_match_pkt & _T_152; // @[el2_lib.scala 241:37]
|
|
wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 242:52]
|
|
wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 242:41]
|
|
wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36]
|
|
wire _T_160 = _T_159 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[el2_lib.scala 244:78]
|
|
wire _T_164 = _T_160 | _T_163; // @[el2_lib.scala 244:23]
|
|
wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_167 = _T_166 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[el2_lib.scala 244:78]
|
|
wire _T_171 = _T_167 | _T_170; // @[el2_lib.scala 244:23]
|
|
wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_174 = _T_173 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[el2_lib.scala 244:78]
|
|
wire _T_178 = _T_174 | _T_177; // @[el2_lib.scala 244:23]
|
|
wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_181 = _T_180 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[el2_lib.scala 244:78]
|
|
wire _T_185 = _T_181 | _T_184; // @[el2_lib.scala 244:23]
|
|
wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_188 = _T_187 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[el2_lib.scala 244:78]
|
|
wire _T_192 = _T_188 | _T_191; // @[el2_lib.scala 244:23]
|
|
wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_195 = _T_194 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[el2_lib.scala 244:78]
|
|
wire _T_199 = _T_195 | _T_198; // @[el2_lib.scala 244:23]
|
|
wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_202 = _T_201 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[el2_lib.scala 244:78]
|
|
wire _T_206 = _T_202 | _T_205; // @[el2_lib.scala 244:23]
|
|
wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_209 = _T_208 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[el2_lib.scala 244:78]
|
|
wire _T_213 = _T_209 | _T_212; // @[el2_lib.scala 244:23]
|
|
wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_216 = _T_215 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[el2_lib.scala 244:78]
|
|
wire _T_220 = _T_216 | _T_219; // @[el2_lib.scala 244:23]
|
|
wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_223 = _T_222 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[el2_lib.scala 244:78]
|
|
wire _T_227 = _T_223 | _T_226; // @[el2_lib.scala 244:23]
|
|
wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_230 = _T_229 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[el2_lib.scala 244:78]
|
|
wire _T_234 = _T_230 | _T_233; // @[el2_lib.scala 244:23]
|
|
wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_237 = _T_236 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[el2_lib.scala 244:78]
|
|
wire _T_241 = _T_237 | _T_240; // @[el2_lib.scala 244:23]
|
|
wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_244 = _T_243 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[el2_lib.scala 244:78]
|
|
wire _T_248 = _T_244 | _T_247; // @[el2_lib.scala 244:23]
|
|
wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_251 = _T_250 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[el2_lib.scala 244:78]
|
|
wire _T_255 = _T_251 | _T_254; // @[el2_lib.scala 244:23]
|
|
wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_258 = _T_257 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[el2_lib.scala 244:78]
|
|
wire _T_262 = _T_258 | _T_261; // @[el2_lib.scala 244:23]
|
|
wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_265 = _T_264 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[el2_lib.scala 244:78]
|
|
wire _T_269 = _T_265 | _T_268; // @[el2_lib.scala 244:23]
|
|
wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_272 = _T_271 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[el2_lib.scala 244:78]
|
|
wire _T_276 = _T_272 | _T_275; // @[el2_lib.scala 244:23]
|
|
wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_279 = _T_278 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[el2_lib.scala 244:78]
|
|
wire _T_283 = _T_279 | _T_282; // @[el2_lib.scala 244:23]
|
|
wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_286 = _T_285 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[el2_lib.scala 244:78]
|
|
wire _T_290 = _T_286 | _T_289; // @[el2_lib.scala 244:23]
|
|
wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_293 = _T_292 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[el2_lib.scala 244:78]
|
|
wire _T_297 = _T_293 | _T_296; // @[el2_lib.scala 244:23]
|
|
wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_300 = _T_299 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[el2_lib.scala 244:78]
|
|
wire _T_304 = _T_300 | _T_303; // @[el2_lib.scala 244:23]
|
|
wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_307 = _T_306 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[el2_lib.scala 244:78]
|
|
wire _T_311 = _T_307 | _T_310; // @[el2_lib.scala 244:23]
|
|
wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_314 = _T_313 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[el2_lib.scala 244:78]
|
|
wire _T_318 = _T_314 | _T_317; // @[el2_lib.scala 244:23]
|
|
wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_321 = _T_320 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[el2_lib.scala 244:78]
|
|
wire _T_325 = _T_321 | _T_324; // @[el2_lib.scala 244:23]
|
|
wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_328 = _T_327 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[el2_lib.scala 244:78]
|
|
wire _T_332 = _T_328 | _T_331; // @[el2_lib.scala 244:23]
|
|
wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_335 = _T_334 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[el2_lib.scala 244:78]
|
|
wire _T_339 = _T_335 | _T_338; // @[el2_lib.scala 244:23]
|
|
wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_342 = _T_341 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[el2_lib.scala 244:78]
|
|
wire _T_346 = _T_342 | _T_345; // @[el2_lib.scala 244:23]
|
|
wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_349 = _T_348 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[el2_lib.scala 244:78]
|
|
wire _T_353 = _T_349 | _T_352; // @[el2_lib.scala 244:23]
|
|
wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_356 = _T_355 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[el2_lib.scala 244:78]
|
|
wire _T_360 = _T_356 | _T_359; // @[el2_lib.scala 244:23]
|
|
wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_363 = _T_362 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[el2_lib.scala 244:78]
|
|
wire _T_367 = _T_363 | _T_366; // @[el2_lib.scala 244:23]
|
|
wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_370 = _T_369 & _T_153; // @[el2_lib.scala 244:41]
|
|
wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[el2_lib.scala 244:78]
|
|
wire _T_374 = _T_370 | _T_373; // @[el2_lib.scala 244:23]
|
|
wire [7:0] _T_381 = {_T_206,_T_199,_T_192,_T_185,_T_178,_T_171,_T_164,_T_157}; // @[el2_lib.scala 245:14]
|
|
wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[el2_lib.scala 245:14]
|
|
wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _GEN_0 = {{31'd0}, _T_148}; // @[el2_dec_trigger.scala 15:109]
|
|
wire [31:0] _T_406 = _GEN_0 & _T_405; // @[el2_dec_trigger.scala 15:109]
|
|
wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_dec_trigger.scala 15:83]
|
|
wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45]
|
|
wire _T_411 = ~_T_410; // @[el2_lib.scala 241:39]
|
|
wire _T_412 = io_trigger_pkt_any_1_match_pkt & _T_411; // @[el2_lib.scala 241:37]
|
|
wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 242:52]
|
|
wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 242:41]
|
|
wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36]
|
|
wire _T_419 = _T_418 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_422 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[el2_lib.scala 244:78]
|
|
wire _T_423 = _T_419 | _T_422; // @[el2_lib.scala 244:23]
|
|
wire _T_425 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_426 = _T_425 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_429 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[el2_lib.scala 244:78]
|
|
wire _T_430 = _T_426 | _T_429; // @[el2_lib.scala 244:23]
|
|
wire _T_432 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_433 = _T_432 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_436 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[el2_lib.scala 244:78]
|
|
wire _T_437 = _T_433 | _T_436; // @[el2_lib.scala 244:23]
|
|
wire _T_439 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_440 = _T_439 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_443 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[el2_lib.scala 244:78]
|
|
wire _T_444 = _T_440 | _T_443; // @[el2_lib.scala 244:23]
|
|
wire _T_446 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_447 = _T_446 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_450 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[el2_lib.scala 244:78]
|
|
wire _T_451 = _T_447 | _T_450; // @[el2_lib.scala 244:23]
|
|
wire _T_453 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_454 = _T_453 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_457 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[el2_lib.scala 244:78]
|
|
wire _T_458 = _T_454 | _T_457; // @[el2_lib.scala 244:23]
|
|
wire _T_460 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_461 = _T_460 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_464 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[el2_lib.scala 244:78]
|
|
wire _T_465 = _T_461 | _T_464; // @[el2_lib.scala 244:23]
|
|
wire _T_467 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_468 = _T_467 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_471 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[el2_lib.scala 244:78]
|
|
wire _T_472 = _T_468 | _T_471; // @[el2_lib.scala 244:23]
|
|
wire _T_474 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_475 = _T_474 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_478 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[el2_lib.scala 244:78]
|
|
wire _T_479 = _T_475 | _T_478; // @[el2_lib.scala 244:23]
|
|
wire _T_481 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_482 = _T_481 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_485 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[el2_lib.scala 244:78]
|
|
wire _T_486 = _T_482 | _T_485; // @[el2_lib.scala 244:23]
|
|
wire _T_488 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_489 = _T_488 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_492 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[el2_lib.scala 244:78]
|
|
wire _T_493 = _T_489 | _T_492; // @[el2_lib.scala 244:23]
|
|
wire _T_495 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_496 = _T_495 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_499 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[el2_lib.scala 244:78]
|
|
wire _T_500 = _T_496 | _T_499; // @[el2_lib.scala 244:23]
|
|
wire _T_502 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_503 = _T_502 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_506 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[el2_lib.scala 244:78]
|
|
wire _T_507 = _T_503 | _T_506; // @[el2_lib.scala 244:23]
|
|
wire _T_509 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_510 = _T_509 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_513 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[el2_lib.scala 244:78]
|
|
wire _T_514 = _T_510 | _T_513; // @[el2_lib.scala 244:23]
|
|
wire _T_516 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_517 = _T_516 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_520 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[el2_lib.scala 244:78]
|
|
wire _T_521 = _T_517 | _T_520; // @[el2_lib.scala 244:23]
|
|
wire _T_523 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_524 = _T_523 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_527 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[el2_lib.scala 244:78]
|
|
wire _T_528 = _T_524 | _T_527; // @[el2_lib.scala 244:23]
|
|
wire _T_530 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_531 = _T_530 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_534 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[el2_lib.scala 244:78]
|
|
wire _T_535 = _T_531 | _T_534; // @[el2_lib.scala 244:23]
|
|
wire _T_537 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_538 = _T_537 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_541 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[el2_lib.scala 244:78]
|
|
wire _T_542 = _T_538 | _T_541; // @[el2_lib.scala 244:23]
|
|
wire _T_544 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_545 = _T_544 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_548 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[el2_lib.scala 244:78]
|
|
wire _T_549 = _T_545 | _T_548; // @[el2_lib.scala 244:23]
|
|
wire _T_551 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_552 = _T_551 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_555 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[el2_lib.scala 244:78]
|
|
wire _T_556 = _T_552 | _T_555; // @[el2_lib.scala 244:23]
|
|
wire _T_558 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_559 = _T_558 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_562 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[el2_lib.scala 244:78]
|
|
wire _T_563 = _T_559 | _T_562; // @[el2_lib.scala 244:23]
|
|
wire _T_565 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_566 = _T_565 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_569 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[el2_lib.scala 244:78]
|
|
wire _T_570 = _T_566 | _T_569; // @[el2_lib.scala 244:23]
|
|
wire _T_572 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_573 = _T_572 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_576 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[el2_lib.scala 244:78]
|
|
wire _T_577 = _T_573 | _T_576; // @[el2_lib.scala 244:23]
|
|
wire _T_579 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_580 = _T_579 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_583 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[el2_lib.scala 244:78]
|
|
wire _T_584 = _T_580 | _T_583; // @[el2_lib.scala 244:23]
|
|
wire _T_586 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_587 = _T_586 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_590 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[el2_lib.scala 244:78]
|
|
wire _T_591 = _T_587 | _T_590; // @[el2_lib.scala 244:23]
|
|
wire _T_593 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_594 = _T_593 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_597 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[el2_lib.scala 244:78]
|
|
wire _T_598 = _T_594 | _T_597; // @[el2_lib.scala 244:23]
|
|
wire _T_600 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_601 = _T_600 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_604 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[el2_lib.scala 244:78]
|
|
wire _T_605 = _T_601 | _T_604; // @[el2_lib.scala 244:23]
|
|
wire _T_607 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_608 = _T_607 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_611 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[el2_lib.scala 244:78]
|
|
wire _T_612 = _T_608 | _T_611; // @[el2_lib.scala 244:23]
|
|
wire _T_614 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_615 = _T_614 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_618 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[el2_lib.scala 244:78]
|
|
wire _T_619 = _T_615 | _T_618; // @[el2_lib.scala 244:23]
|
|
wire _T_621 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_622 = _T_621 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_625 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[el2_lib.scala 244:78]
|
|
wire _T_626 = _T_622 | _T_625; // @[el2_lib.scala 244:23]
|
|
wire _T_628 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_629 = _T_628 & _T_412; // @[el2_lib.scala 244:41]
|
|
wire _T_632 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[el2_lib.scala 244:78]
|
|
wire _T_633 = _T_629 | _T_632; // @[el2_lib.scala 244:23]
|
|
wire [7:0] _T_640 = {_T_465,_T_458,_T_451,_T_444,_T_437,_T_430,_T_423,_T_416}; // @[el2_lib.scala 245:14]
|
|
wire [15:0] _T_648 = {_T_521,_T_514,_T_507,_T_500,_T_493,_T_486,_T_479,_T_472,_T_640}; // @[el2_lib.scala 245:14]
|
|
wire [7:0] _T_655 = {_T_577,_T_570,_T_563,_T_556,_T_549,_T_542,_T_535,_T_528}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _T_664 = {_T_633,_T_626,_T_619,_T_612,_T_605,_T_598,_T_591,_T_584,_T_655,_T_648}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _GEN_1 = {{31'd0}, _T_407}; // @[el2_dec_trigger.scala 15:109]
|
|
wire [31:0] _T_665 = _GEN_1 & _T_664; // @[el2_dec_trigger.scala 15:109]
|
|
wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_dec_trigger.scala 15:83]
|
|
wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45]
|
|
wire _T_670 = ~_T_669; // @[el2_lib.scala 241:39]
|
|
wire _T_671 = io_trigger_pkt_any_2_match_pkt & _T_670; // @[el2_lib.scala 241:37]
|
|
wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 242:52]
|
|
wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 242:41]
|
|
wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36]
|
|
wire _T_678 = _T_677 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_681 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[el2_lib.scala 244:78]
|
|
wire _T_682 = _T_678 | _T_681; // @[el2_lib.scala 244:23]
|
|
wire _T_684 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_685 = _T_684 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_688 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[el2_lib.scala 244:78]
|
|
wire _T_689 = _T_685 | _T_688; // @[el2_lib.scala 244:23]
|
|
wire _T_691 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_692 = _T_691 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_695 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[el2_lib.scala 244:78]
|
|
wire _T_696 = _T_692 | _T_695; // @[el2_lib.scala 244:23]
|
|
wire _T_698 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_699 = _T_698 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_702 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[el2_lib.scala 244:78]
|
|
wire _T_703 = _T_699 | _T_702; // @[el2_lib.scala 244:23]
|
|
wire _T_705 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_706 = _T_705 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_709 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[el2_lib.scala 244:78]
|
|
wire _T_710 = _T_706 | _T_709; // @[el2_lib.scala 244:23]
|
|
wire _T_712 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_713 = _T_712 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_716 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[el2_lib.scala 244:78]
|
|
wire _T_717 = _T_713 | _T_716; // @[el2_lib.scala 244:23]
|
|
wire _T_719 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_720 = _T_719 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_723 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[el2_lib.scala 244:78]
|
|
wire _T_724 = _T_720 | _T_723; // @[el2_lib.scala 244:23]
|
|
wire _T_726 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_727 = _T_726 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_730 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[el2_lib.scala 244:78]
|
|
wire _T_731 = _T_727 | _T_730; // @[el2_lib.scala 244:23]
|
|
wire _T_733 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_734 = _T_733 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_737 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[el2_lib.scala 244:78]
|
|
wire _T_738 = _T_734 | _T_737; // @[el2_lib.scala 244:23]
|
|
wire _T_740 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_741 = _T_740 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_744 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[el2_lib.scala 244:78]
|
|
wire _T_745 = _T_741 | _T_744; // @[el2_lib.scala 244:23]
|
|
wire _T_747 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_748 = _T_747 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_751 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[el2_lib.scala 244:78]
|
|
wire _T_752 = _T_748 | _T_751; // @[el2_lib.scala 244:23]
|
|
wire _T_754 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_755 = _T_754 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_758 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[el2_lib.scala 244:78]
|
|
wire _T_759 = _T_755 | _T_758; // @[el2_lib.scala 244:23]
|
|
wire _T_761 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_762 = _T_761 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_765 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[el2_lib.scala 244:78]
|
|
wire _T_766 = _T_762 | _T_765; // @[el2_lib.scala 244:23]
|
|
wire _T_768 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_769 = _T_768 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_772 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[el2_lib.scala 244:78]
|
|
wire _T_773 = _T_769 | _T_772; // @[el2_lib.scala 244:23]
|
|
wire _T_775 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_776 = _T_775 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_779 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[el2_lib.scala 244:78]
|
|
wire _T_780 = _T_776 | _T_779; // @[el2_lib.scala 244:23]
|
|
wire _T_782 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_783 = _T_782 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_786 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[el2_lib.scala 244:78]
|
|
wire _T_787 = _T_783 | _T_786; // @[el2_lib.scala 244:23]
|
|
wire _T_789 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_790 = _T_789 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_793 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[el2_lib.scala 244:78]
|
|
wire _T_794 = _T_790 | _T_793; // @[el2_lib.scala 244:23]
|
|
wire _T_796 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_797 = _T_796 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_800 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[el2_lib.scala 244:78]
|
|
wire _T_801 = _T_797 | _T_800; // @[el2_lib.scala 244:23]
|
|
wire _T_803 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_804 = _T_803 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_807 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[el2_lib.scala 244:78]
|
|
wire _T_808 = _T_804 | _T_807; // @[el2_lib.scala 244:23]
|
|
wire _T_810 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_811 = _T_810 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_814 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[el2_lib.scala 244:78]
|
|
wire _T_815 = _T_811 | _T_814; // @[el2_lib.scala 244:23]
|
|
wire _T_817 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_818 = _T_817 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_821 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[el2_lib.scala 244:78]
|
|
wire _T_822 = _T_818 | _T_821; // @[el2_lib.scala 244:23]
|
|
wire _T_824 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_825 = _T_824 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_828 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[el2_lib.scala 244:78]
|
|
wire _T_829 = _T_825 | _T_828; // @[el2_lib.scala 244:23]
|
|
wire _T_831 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_832 = _T_831 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_835 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[el2_lib.scala 244:78]
|
|
wire _T_836 = _T_832 | _T_835; // @[el2_lib.scala 244:23]
|
|
wire _T_838 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_839 = _T_838 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_842 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[el2_lib.scala 244:78]
|
|
wire _T_843 = _T_839 | _T_842; // @[el2_lib.scala 244:23]
|
|
wire _T_845 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_846 = _T_845 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_849 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[el2_lib.scala 244:78]
|
|
wire _T_850 = _T_846 | _T_849; // @[el2_lib.scala 244:23]
|
|
wire _T_852 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_853 = _T_852 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_856 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[el2_lib.scala 244:78]
|
|
wire _T_857 = _T_853 | _T_856; // @[el2_lib.scala 244:23]
|
|
wire _T_859 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_860 = _T_859 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_863 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[el2_lib.scala 244:78]
|
|
wire _T_864 = _T_860 | _T_863; // @[el2_lib.scala 244:23]
|
|
wire _T_866 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_867 = _T_866 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_870 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[el2_lib.scala 244:78]
|
|
wire _T_871 = _T_867 | _T_870; // @[el2_lib.scala 244:23]
|
|
wire _T_873 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_874 = _T_873 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_877 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[el2_lib.scala 244:78]
|
|
wire _T_878 = _T_874 | _T_877; // @[el2_lib.scala 244:23]
|
|
wire _T_880 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_881 = _T_880 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_884 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[el2_lib.scala 244:78]
|
|
wire _T_885 = _T_881 | _T_884; // @[el2_lib.scala 244:23]
|
|
wire _T_887 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_888 = _T_887 & _T_671; // @[el2_lib.scala 244:41]
|
|
wire _T_891 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[el2_lib.scala 244:78]
|
|
wire _T_892 = _T_888 | _T_891; // @[el2_lib.scala 244:23]
|
|
wire [7:0] _T_899 = {_T_724,_T_717,_T_710,_T_703,_T_696,_T_689,_T_682,_T_675}; // @[el2_lib.scala 245:14]
|
|
wire [15:0] _T_907 = {_T_780,_T_773,_T_766,_T_759,_T_752,_T_745,_T_738,_T_731,_T_899}; // @[el2_lib.scala 245:14]
|
|
wire [7:0] _T_914 = {_T_836,_T_829,_T_822,_T_815,_T_808,_T_801,_T_794,_T_787}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _T_923 = {_T_892,_T_885,_T_878,_T_871,_T_864,_T_857,_T_850,_T_843,_T_914,_T_907}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _GEN_2 = {{31'd0}, _T_666}; // @[el2_dec_trigger.scala 15:109]
|
|
wire [31:0] _T_924 = _GEN_2 & _T_923; // @[el2_dec_trigger.scala 15:109]
|
|
wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_dec_trigger.scala 15:83]
|
|
wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45]
|
|
wire _T_929 = ~_T_928; // @[el2_lib.scala 241:39]
|
|
wire _T_930 = io_trigger_pkt_any_3_match_pkt & _T_929; // @[el2_lib.scala 241:37]
|
|
wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 242:52]
|
|
wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 242:41]
|
|
wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36]
|
|
wire _T_937 = _T_936 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_940 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[el2_lib.scala 244:78]
|
|
wire _T_941 = _T_937 | _T_940; // @[el2_lib.scala 244:23]
|
|
wire _T_943 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_944 = _T_943 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_947 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[el2_lib.scala 244:78]
|
|
wire _T_948 = _T_944 | _T_947; // @[el2_lib.scala 244:23]
|
|
wire _T_950 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_951 = _T_950 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_954 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[el2_lib.scala 244:78]
|
|
wire _T_955 = _T_951 | _T_954; // @[el2_lib.scala 244:23]
|
|
wire _T_957 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_958 = _T_957 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_961 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[el2_lib.scala 244:78]
|
|
wire _T_962 = _T_958 | _T_961; // @[el2_lib.scala 244:23]
|
|
wire _T_964 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_965 = _T_964 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_968 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[el2_lib.scala 244:78]
|
|
wire _T_969 = _T_965 | _T_968; // @[el2_lib.scala 244:23]
|
|
wire _T_971 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_972 = _T_971 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_975 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[el2_lib.scala 244:78]
|
|
wire _T_976 = _T_972 | _T_975; // @[el2_lib.scala 244:23]
|
|
wire _T_978 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_979 = _T_978 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_982 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[el2_lib.scala 244:78]
|
|
wire _T_983 = _T_979 | _T_982; // @[el2_lib.scala 244:23]
|
|
wire _T_985 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_986 = _T_985 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_989 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[el2_lib.scala 244:78]
|
|
wire _T_990 = _T_986 | _T_989; // @[el2_lib.scala 244:23]
|
|
wire _T_992 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_993 = _T_992 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_996 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[el2_lib.scala 244:78]
|
|
wire _T_997 = _T_993 | _T_996; // @[el2_lib.scala 244:23]
|
|
wire _T_999 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1000 = _T_999 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1003 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[el2_lib.scala 244:78]
|
|
wire _T_1004 = _T_1000 | _T_1003; // @[el2_lib.scala 244:23]
|
|
wire _T_1006 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1007 = _T_1006 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1010 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[el2_lib.scala 244:78]
|
|
wire _T_1011 = _T_1007 | _T_1010; // @[el2_lib.scala 244:23]
|
|
wire _T_1013 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1014 = _T_1013 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1017 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[el2_lib.scala 244:78]
|
|
wire _T_1018 = _T_1014 | _T_1017; // @[el2_lib.scala 244:23]
|
|
wire _T_1020 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1021 = _T_1020 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1024 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[el2_lib.scala 244:78]
|
|
wire _T_1025 = _T_1021 | _T_1024; // @[el2_lib.scala 244:23]
|
|
wire _T_1027 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1028 = _T_1027 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1031 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[el2_lib.scala 244:78]
|
|
wire _T_1032 = _T_1028 | _T_1031; // @[el2_lib.scala 244:23]
|
|
wire _T_1034 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1035 = _T_1034 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1038 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[el2_lib.scala 244:78]
|
|
wire _T_1039 = _T_1035 | _T_1038; // @[el2_lib.scala 244:23]
|
|
wire _T_1041 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1042 = _T_1041 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1045 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[el2_lib.scala 244:78]
|
|
wire _T_1046 = _T_1042 | _T_1045; // @[el2_lib.scala 244:23]
|
|
wire _T_1048 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1049 = _T_1048 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1052 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[el2_lib.scala 244:78]
|
|
wire _T_1053 = _T_1049 | _T_1052; // @[el2_lib.scala 244:23]
|
|
wire _T_1055 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1056 = _T_1055 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1059 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[el2_lib.scala 244:78]
|
|
wire _T_1060 = _T_1056 | _T_1059; // @[el2_lib.scala 244:23]
|
|
wire _T_1062 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1063 = _T_1062 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1066 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[el2_lib.scala 244:78]
|
|
wire _T_1067 = _T_1063 | _T_1066; // @[el2_lib.scala 244:23]
|
|
wire _T_1069 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1070 = _T_1069 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1073 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[el2_lib.scala 244:78]
|
|
wire _T_1074 = _T_1070 | _T_1073; // @[el2_lib.scala 244:23]
|
|
wire _T_1076 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1077 = _T_1076 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1080 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[el2_lib.scala 244:78]
|
|
wire _T_1081 = _T_1077 | _T_1080; // @[el2_lib.scala 244:23]
|
|
wire _T_1083 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1084 = _T_1083 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1087 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[el2_lib.scala 244:78]
|
|
wire _T_1088 = _T_1084 | _T_1087; // @[el2_lib.scala 244:23]
|
|
wire _T_1090 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1091 = _T_1090 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1094 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[el2_lib.scala 244:78]
|
|
wire _T_1095 = _T_1091 | _T_1094; // @[el2_lib.scala 244:23]
|
|
wire _T_1097 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1098 = _T_1097 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1101 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[el2_lib.scala 244:78]
|
|
wire _T_1102 = _T_1098 | _T_1101; // @[el2_lib.scala 244:23]
|
|
wire _T_1104 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1105 = _T_1104 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1108 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[el2_lib.scala 244:78]
|
|
wire _T_1109 = _T_1105 | _T_1108; // @[el2_lib.scala 244:23]
|
|
wire _T_1111 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1112 = _T_1111 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1115 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[el2_lib.scala 244:78]
|
|
wire _T_1116 = _T_1112 | _T_1115; // @[el2_lib.scala 244:23]
|
|
wire _T_1118 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1119 = _T_1118 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1122 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[el2_lib.scala 244:78]
|
|
wire _T_1123 = _T_1119 | _T_1122; // @[el2_lib.scala 244:23]
|
|
wire _T_1125 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1126 = _T_1125 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1129 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[el2_lib.scala 244:78]
|
|
wire _T_1130 = _T_1126 | _T_1129; // @[el2_lib.scala 244:23]
|
|
wire _T_1132 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1133 = _T_1132 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1136 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[el2_lib.scala 244:78]
|
|
wire _T_1137 = _T_1133 | _T_1136; // @[el2_lib.scala 244:23]
|
|
wire _T_1139 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1140 = _T_1139 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1143 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[el2_lib.scala 244:78]
|
|
wire _T_1144 = _T_1140 | _T_1143; // @[el2_lib.scala 244:23]
|
|
wire _T_1146 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1147 = _T_1146 & _T_930; // @[el2_lib.scala 244:41]
|
|
wire _T_1150 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[el2_lib.scala 244:78]
|
|
wire _T_1151 = _T_1147 | _T_1150; // @[el2_lib.scala 244:23]
|
|
wire [7:0] _T_1158 = {_T_983,_T_976,_T_969,_T_962,_T_955,_T_948,_T_941,_T_934}; // @[el2_lib.scala 245:14]
|
|
wire [15:0] _T_1166 = {_T_1039,_T_1032,_T_1025,_T_1018,_T_1011,_T_1004,_T_997,_T_990,_T_1158}; // @[el2_lib.scala 245:14]
|
|
wire [7:0] _T_1173 = {_T_1095,_T_1088,_T_1081,_T_1074,_T_1067,_T_1060,_T_1053,_T_1046}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _T_1182 = {_T_1151,_T_1144,_T_1137,_T_1130,_T_1123,_T_1116,_T_1109,_T_1102,_T_1173,_T_1166}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _GEN_3 = {{31'd0}, _T_925}; // @[el2_dec_trigger.scala 15:109]
|
|
wire [31:0] _T_1183 = _GEN_3 & _T_1182; // @[el2_dec_trigger.scala 15:109]
|
|
wire [127:0] _T_1186 = {_T_1183,_T_924,_T_665,_T_406}; // @[Cat.scala 29:58]
|
|
assign io_dec_i0_trigger_match_d = _T_1186[3:0]; // @[el2_dec_trigger.scala 15:29]
|
|
endmodule
|
|
module el2_dec(
|
|
input clock,
|
|
input reset,
|
|
input io_free_clk,
|
|
input io_active_clk,
|
|
input io_lsu_fastint_stall_any,
|
|
output io_dec_extint_stall,
|
|
output io_dec_i0_decode_d,
|
|
output io_dec_pause_state_cg,
|
|
input [30:0] io_rst_vec,
|
|
input io_nmi_int,
|
|
input [30:0] io_nmi_vec,
|
|
input io_i_cpu_halt_req,
|
|
input io_i_cpu_run_req,
|
|
output io_o_cpu_halt_status,
|
|
output io_o_cpu_halt_ack,
|
|
output io_o_cpu_run_ack,
|
|
output io_o_debug_mode_status,
|
|
input [27:0] io_core_id,
|
|
input io_mpc_debug_halt_req,
|
|
input io_mpc_debug_run_req,
|
|
input io_mpc_reset_run_req,
|
|
output io_mpc_debug_halt_ack,
|
|
output io_mpc_debug_run_ack,
|
|
output io_debug_brkpt_status,
|
|
input io_exu_pmu_i0_br_misp,
|
|
input io_exu_pmu_i0_br_ataken,
|
|
input io_exu_pmu_i0_pc4,
|
|
input io_lsu_nonblock_load_valid_m,
|
|
input [1:0] io_lsu_nonblock_load_tag_m,
|
|
input io_lsu_nonblock_load_inv_r,
|
|
input [1:0] io_lsu_nonblock_load_inv_tag_r,
|
|
input io_lsu_nonblock_load_data_valid,
|
|
input io_lsu_nonblock_load_data_error,
|
|
input [1:0] io_lsu_nonblock_load_data_tag,
|
|
input [31:0] io_lsu_nonblock_load_data,
|
|
input io_lsu_pmu_bus_trxn,
|
|
input io_lsu_pmu_bus_misaligned,
|
|
input io_lsu_pmu_bus_error,
|
|
input io_lsu_pmu_bus_busy,
|
|
input io_lsu_pmu_load_external_m,
|
|
input io_lsu_pmu_store_external_m,
|
|
input io_dma_pmu_dccm_read,
|
|
input io_dma_pmu_dccm_write,
|
|
input io_dma_pmu_any_read,
|
|
input io_dma_pmu_any_write,
|
|
input [30:0] io_lsu_fir_addr,
|
|
input [1:0] io_lsu_fir_error,
|
|
input io_ifu_pmu_instr_aligned,
|
|
input io_ifu_pmu_fetch_stall,
|
|
input io_ifu_pmu_ic_miss,
|
|
input io_ifu_pmu_ic_hit,
|
|
input io_ifu_pmu_bus_error,
|
|
input io_ifu_pmu_bus_busy,
|
|
input io_ifu_pmu_bus_trxn,
|
|
input io_ifu_ic_error_start,
|
|
input io_ifu_iccm_rd_ecc_single_err,
|
|
input [3:0] io_lsu_trigger_match_m,
|
|
input io_dbg_cmd_valid,
|
|
input io_dbg_cmd_write,
|
|
input [1:0] io_dbg_cmd_type,
|
|
input [31:0] io_dbg_cmd_addr,
|
|
input [1:0] io_dbg_cmd_wrdata,
|
|
input io_ifu_i0_icaf,
|
|
input [1:0] io_ifu_i0_icaf_type,
|
|
input io_ifu_i0_icaf_f1,
|
|
input io_ifu_i0_dbecc,
|
|
input io_lsu_idle_any,
|
|
input io_i0_brp_valid,
|
|
input [11:0] io_i0_brp_toffset,
|
|
input [1:0] io_i0_brp_hist,
|
|
input io_i0_brp_br_error,
|
|
input io_i0_brp_br_start_error,
|
|
input [30:0] io_i0_brp_prett,
|
|
input io_i0_brp_way,
|
|
input io_i0_brp_ret,
|
|
input [7:0] io_ifu_i0_bp_index,
|
|
input [7:0] io_ifu_i0_bp_fghr,
|
|
input [4:0] io_ifu_i0_bp_btag,
|
|
input io_lsu_error_pkt_r_valid,
|
|
input io_lsu_error_pkt_r_bits_single_ecc_error,
|
|
input io_lsu_error_pkt_r_bits_inst_type,
|
|
input io_lsu_error_pkt_r_bits_exc_type,
|
|
input [3:0] io_lsu_error_pkt_r_bits_mscause,
|
|
input [31:0] io_lsu_error_pkt_r_bits_addr,
|
|
input io_lsu_single_ecc_error_incr,
|
|
input io_lsu_imprecise_error_load_any,
|
|
input io_lsu_imprecise_error_store_any,
|
|
input [31:0] io_lsu_imprecise_error_addr_any,
|
|
input [31:0] io_exu_div_result,
|
|
input io_exu_div_wren,
|
|
input [31:0] io_exu_csr_rs1_x,
|
|
input [31:0] io_lsu_result_m,
|
|
input [31:0] io_lsu_result_corr_r,
|
|
input io_lsu_load_stall_any,
|
|
input io_lsu_store_stall_any,
|
|
input io_dma_dccm_stall_any,
|
|
input io_dma_iccm_stall_any,
|
|
input io_iccm_dma_sb_error,
|
|
input io_exu_flush_final,
|
|
input [30:0] io_exu_npc_r,
|
|
input [31:0] io_exu_i0_result_x,
|
|
input io_ifu_i0_valid,
|
|
input [31:0] io_ifu_i0_instr,
|
|
input [30:0] io_ifu_i0_pc,
|
|
input io_ifu_i0_pc4,
|
|
input [30:0] io_exu_i0_pc_x,
|
|
input io_mexintpend,
|
|
input io_timer_int,
|
|
input io_soft_int,
|
|
input [7:0] io_pic_claimid,
|
|
input [3:0] io_pic_pl,
|
|
input io_mhwakeup,
|
|
output [3:0] io_dec_tlu_meicurpl,
|
|
output [3:0] io_dec_tlu_meipt,
|
|
input [70:0] io_ifu_ic_debug_rd_data,
|
|
input io_ifu_ic_debug_rd_data_valid,
|
|
output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata,
|
|
output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics,
|
|
output io_dec_tlu_ic_diag_pkt_icache_rd_valid,
|
|
output io_dec_tlu_ic_diag_pkt_icache_wr_valid,
|
|
input io_dbg_halt_req,
|
|
input io_dbg_resume_req,
|
|
input io_ifu_miss_state_idle,
|
|
output io_dec_tlu_dbg_halted,
|
|
output io_dec_tlu_debug_mode,
|
|
output io_dec_tlu_resume_ack,
|
|
output io_dec_tlu_flush_noredir_r,
|
|
output io_dec_tlu_mpc_halted_only,
|
|
output io_dec_tlu_flush_leak_one_r,
|
|
output io_dec_tlu_flush_err_r,
|
|
output [29:0] io_dec_tlu_meihap,
|
|
output io_dec_debug_wdata_rs1_d,
|
|
output [31:0] io_dec_dbg_rddata,
|
|
output io_dec_dbg_cmd_done,
|
|
output io_dec_dbg_cmd_fail,
|
|
output io_trigger_pkt_any_0_select,
|
|
output io_trigger_pkt_any_0_match_pkt,
|
|
output io_trigger_pkt_any_0_store,
|
|
output io_trigger_pkt_any_0_load,
|
|
output [31:0] io_trigger_pkt_any_0_tdata2,
|
|
output io_trigger_pkt_any_1_select,
|
|
output io_trigger_pkt_any_1_match_pkt,
|
|
output io_trigger_pkt_any_1_store,
|
|
output io_trigger_pkt_any_1_load,
|
|
output [31:0] io_trigger_pkt_any_1_tdata2,
|
|
output io_trigger_pkt_any_2_select,
|
|
output io_trigger_pkt_any_2_match_pkt,
|
|
output io_trigger_pkt_any_2_store,
|
|
output io_trigger_pkt_any_2_load,
|
|
output [31:0] io_trigger_pkt_any_2_tdata2,
|
|
output io_trigger_pkt_any_3_select,
|
|
output io_trigger_pkt_any_3_match_pkt,
|
|
output io_trigger_pkt_any_3_store,
|
|
output io_trigger_pkt_any_3_load,
|
|
output [31:0] io_trigger_pkt_any_3_tdata2,
|
|
output io_dec_tlu_force_halt,
|
|
input [1:0] io_exu_i0_br_hist_r,
|
|
input io_exu_i0_br_error_r,
|
|
input io_exu_i0_br_start_error_r,
|
|
input io_exu_i0_br_valid_r,
|
|
input io_exu_i0_br_mp_r,
|
|
input io_exu_i0_br_middle_r,
|
|
input io_exu_i0_br_way_r,
|
|
output io_dec_i0_rs1_en_d,
|
|
output io_dec_i0_rs2_en_d,
|
|
output [31:0] io_gpr_i0_rs1_d,
|
|
output [31:0] io_gpr_i0_rs2_d,
|
|
output [31:0] io_dec_i0_immed_d,
|
|
output [11:0] io_dec_i0_br_immed_d,
|
|
output io_i0_ap_land,
|
|
output io_i0_ap_lor,
|
|
output io_i0_ap_lxor,
|
|
output io_i0_ap_sll,
|
|
output io_i0_ap_srl,
|
|
output io_i0_ap_sra,
|
|
output io_i0_ap_beq,
|
|
output io_i0_ap_bne,
|
|
output io_i0_ap_blt,
|
|
output io_i0_ap_bge,
|
|
output io_i0_ap_add,
|
|
output io_i0_ap_sub,
|
|
output io_i0_ap_slt,
|
|
output io_i0_ap_unsign,
|
|
output io_i0_ap_jal,
|
|
output io_i0_ap_predict_t,
|
|
output io_i0_ap_predict_nt,
|
|
output io_i0_ap_csr_write,
|
|
output io_i0_ap_csr_imm,
|
|
output io_dec_i0_alu_decode_d,
|
|
output io_dec_i0_select_pc_d,
|
|
output [30:0] io_dec_i0_pc_d,
|
|
output [1:0] io_dec_i0_rs1_bypass_en_d,
|
|
output [1:0] io_dec_i0_rs2_bypass_en_d,
|
|
output [31:0] io_dec_i0_rs1_bypass_data_d,
|
|
output [31:0] io_dec_i0_rs2_bypass_data_d,
|
|
output io_lsu_p_valid,
|
|
output io_lsu_p_bits_fast_int,
|
|
output io_lsu_p_bits_by,
|
|
output io_lsu_p_bits_half,
|
|
output io_lsu_p_bits_word,
|
|
output io_lsu_p_bits_load,
|
|
output io_lsu_p_bits_store,
|
|
output io_lsu_p_bits_unsign,
|
|
output io_lsu_p_bits_store_data_bypass_d,
|
|
output io_lsu_p_bits_load_ldst_bypass_d,
|
|
output io_mul_p_valid,
|
|
output io_mul_p_bits_rs1_sign,
|
|
output io_mul_p_bits_rs2_sign,
|
|
output io_mul_p_bits_low,
|
|
output io_div_p_valid,
|
|
output io_div_p_bits_unsign,
|
|
output io_div_p_bits_rem,
|
|
output io_dec_div_cancel,
|
|
output [11:0] io_dec_lsu_offset_d,
|
|
output io_dec_csr_ren_d,
|
|
output io_dec_tlu_flush_lower_r,
|
|
output [30:0] io_dec_tlu_flush_path_r,
|
|
output io_dec_tlu_i0_kill_writeb_r,
|
|
output io_dec_tlu_fence_i_r,
|
|
output [30:0] io_pred_correct_npc_x,
|
|
output io_dec_tlu_br0_r_pkt_valid,
|
|
output [1:0] io_dec_tlu_br0_r_pkt_hist,
|
|
output io_dec_tlu_br0_r_pkt_br_error,
|
|
output io_dec_tlu_br0_r_pkt_br_start_error,
|
|
output io_dec_tlu_br0_r_pkt_way,
|
|
output io_dec_tlu_br0_r_pkt_middle,
|
|
output io_dec_tlu_perfcnt0,
|
|
output io_dec_tlu_perfcnt1,
|
|
output io_dec_tlu_perfcnt2,
|
|
output io_dec_tlu_perfcnt3,
|
|
output io_dec_i0_predict_p_d_valid,
|
|
output io_dec_i0_predict_p_d_bits_pc4,
|
|
output [1:0] io_dec_i0_predict_p_d_bits_hist,
|
|
output [11:0] io_dec_i0_predict_p_d_bits_toffset,
|
|
output io_dec_i0_predict_p_d_bits_br_error,
|
|
output io_dec_i0_predict_p_d_bits_br_start_error,
|
|
output [30:0] io_dec_i0_predict_p_d_bits_prett,
|
|
output io_dec_i0_predict_p_d_bits_pcall,
|
|
output io_dec_i0_predict_p_d_bits_pret,
|
|
output io_dec_i0_predict_p_d_bits_pja,
|
|
output io_dec_i0_predict_p_d_bits_way,
|
|
output [7:0] io_i0_predict_fghr_d,
|
|
output [7:0] io_i0_predict_index_d,
|
|
output [4:0] io_i0_predict_btag_d,
|
|
output io_dec_lsu_valid_raw_d,
|
|
output [31:0] io_dec_tlu_mrac_ff,
|
|
output [1:0] io_dec_data_en,
|
|
output [1:0] io_dec_ctl_en,
|
|
input [15:0] io_ifu_i0_cinst,
|
|
output [1:0] io_rv_trace_pkt_rv_i_valid_ip,
|
|
output [31:0] io_rv_trace_pkt_rv_i_insn_ip,
|
|
output [31:0] io_rv_trace_pkt_rv_i_address_ip,
|
|
output [1:0] io_rv_trace_pkt_rv_i_exception_ip,
|
|
output [4:0] io_rv_trace_pkt_rv_i_ecause_ip,
|
|
output [1:0] io_rv_trace_pkt_rv_i_interrupt_ip,
|
|
output [31:0] io_rv_trace_pkt_rv_i_tval_ip,
|
|
output io_dec_tlu_external_ldfwd_disable,
|
|
output io_dec_tlu_sideeffect_posted_disable,
|
|
output io_dec_tlu_core_ecc_disable,
|
|
output io_dec_tlu_bpred_disable,
|
|
output io_dec_tlu_wb_coalescing_disable,
|
|
output [2:0] io_dec_tlu_dma_qos_prty,
|
|
output io_dec_tlu_misc_clk_override,
|
|
output io_dec_tlu_lsu_clk_override,
|
|
output io_dec_tlu_pic_clk_override,
|
|
output io_dec_tlu_dccm_clk_override,
|
|
output io_dec_tlu_icm_clk_override,
|
|
output io_dec_tlu_i0_commit_cmt,
|
|
input io_scan_mode
|
|
);
|
|
wire instbuff_io_dbg_cmd_valid; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dbg_cmd_write; // @[el2_dec.scala 285:24]
|
|
wire [1:0] instbuff_io_dbg_cmd_type; // @[el2_dec.scala 285:24]
|
|
wire [31:0] instbuff_io_dbg_cmd_addr; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_i0_brp_valid; // @[el2_dec.scala 285:24]
|
|
wire [11:0] instbuff_io_i0_brp_toffset; // @[el2_dec.scala 285:24]
|
|
wire [1:0] instbuff_io_i0_brp_hist; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_i0_brp_br_error; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_i0_brp_br_start_error; // @[el2_dec.scala 285:24]
|
|
wire [30:0] instbuff_io_i0_brp_prett; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_i0_brp_way; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_i0_brp_ret; // @[el2_dec.scala 285:24]
|
|
wire [7:0] instbuff_io_ifu_i0_bp_index; // @[el2_dec.scala 285:24]
|
|
wire [7:0] instbuff_io_ifu_i0_bp_fghr; // @[el2_dec.scala 285:24]
|
|
wire [4:0] instbuff_io_ifu_i0_bp_btag; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_ifu_i0_pc4; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_ifu_i0_valid; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_ifu_i0_icaf; // @[el2_dec.scala 285:24]
|
|
wire [1:0] instbuff_io_ifu_i0_icaf_type; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_ifu_i0_icaf_f1; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_ifu_i0_dbecc; // @[el2_dec.scala 285:24]
|
|
wire [31:0] instbuff_io_ifu_i0_instr; // @[el2_dec.scala 285:24]
|
|
wire [30:0] instbuff_io_ifu_i0_pc; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 285:24]
|
|
wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 285:24]
|
|
wire [31:0] instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 285:24]
|
|
wire [30:0] instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_i0_pc4_d; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 285:24]
|
|
wire [11:0] instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 285:24]
|
|
wire [1:0] instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 285:24]
|
|
wire [30:0] instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 285:24]
|
|
wire [7:0] instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 285:24]
|
|
wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 285:24]
|
|
wire [4:0] instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 285:24]
|
|
wire instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 285:24]
|
|
wire decode_clock; // @[el2_dec.scala 286:22]
|
|
wire decode_reset; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_flush_extint; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_force_halt; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_extint_stall; // @[el2_dec.scala 286:22]
|
|
wire [15:0] decode_io_ifu_i0_cinst; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_dec_i0_inst_wb1; // @[el2_dec.scala 286:22]
|
|
wire [30:0] decode_io_dec_i0_pc_wb1; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_nonblock_load_data_error; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_lsu_nonblock_load_data; // @[el2_dec.scala 286:22]
|
|
wire [3:0] decode_io_dec_i0_trigger_match_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 286:22]
|
|
wire [3:0] decode_io_lsu_trigger_match_m; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_pmu_misaligned_m; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_debug_stall; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_debug_fence_d; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_dbg_cmd_wrdata; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_icaf_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_dec_i0_icaf_type_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_dbecc_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_brp_valid; // @[el2_dec.scala 286:22]
|
|
wire [11:0] decode_io_dec_i0_brp_toffset; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_dec_i0_brp_hist; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_brp_br_error; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 286:22]
|
|
wire [30:0] decode_io_dec_i0_brp_prett; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_brp_way; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_brp_ret; // @[el2_dec.scala 286:22]
|
|
wire [7:0] decode_io_dec_i0_bp_index; // @[el2_dec.scala 286:22]
|
|
wire [7:0] decode_io_dec_i0_bp_fghr; // @[el2_dec.scala 286:22]
|
|
wire [4:0] decode_io_dec_i0_bp_btag; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_idle_any; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_load_stall_any; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_store_stall_any; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dma_dccm_stall_any; // @[el2_dec.scala 286:22]
|
|
wire decode_io_exu_div_wren; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_presync_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_postsync_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_pc4_d; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_dec_csr_rddata_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_csr_legal_d; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_exu_csr_rs1_x; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_lsu_result_m; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_lsu_result_corr_r; // @[el2_dec.scala 286:22]
|
|
wire decode_io_exu_flush_final; // @[el2_dec.scala 286:22]
|
|
wire [30:0] decode_io_exu_i0_pc_x; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_dec_i0_instr_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_ib0_valid_d; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_exu_i0_result_x; // @[el2_dec.scala 286:22]
|
|
wire decode_io_free_clk; // @[el2_dec.scala 286:22]
|
|
wire decode_io_active_clk; // @[el2_dec.scala 286:22]
|
|
wire decode_io_clk_override; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 286:22]
|
|
wire [4:0] decode_io_dec_i0_rs1_d; // @[el2_dec.scala 286:22]
|
|
wire [4:0] decode_io_dec_i0_rs2_d; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_dec_i0_immed_d; // @[el2_dec.scala 286:22]
|
|
wire [11:0] decode_io_dec_i0_br_immed_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_land; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_lor; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_lxor; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_sll; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_srl; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_sra; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_beq; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_bne; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_blt; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_bge; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_add; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_sub; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_slt; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_unsign; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_jal; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_predict_t; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_predict_nt; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_csr_write; // @[el2_dec.scala 286:22]
|
|
wire decode_io_i0_ap_csr_imm; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_decode_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 286:22]
|
|
wire [4:0] decode_io_dec_i0_waddr_r; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_wen_r; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_dec_i0_wdata_r; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_select_pc_d; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_p_valid; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_p_bits_fast_int; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_p_bits_by; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_p_bits_half; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_p_bits_word; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_p_bits_load; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_p_bits_store; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_p_bits_unsign; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_p_bits_store_data_bypass_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_mul_p_valid; // @[el2_dec.scala 286:22]
|
|
wire decode_io_mul_p_bits_rs1_sign; // @[el2_dec.scala 286:22]
|
|
wire decode_io_mul_p_bits_rs2_sign; // @[el2_dec.scala 286:22]
|
|
wire decode_io_mul_p_bits_low; // @[el2_dec.scala 286:22]
|
|
wire decode_io_div_p_valid; // @[el2_dec.scala 286:22]
|
|
wire decode_io_div_p_bits_unsign; // @[el2_dec.scala 286:22]
|
|
wire decode_io_div_p_bits_rem; // @[el2_dec.scala 286:22]
|
|
wire [4:0] decode_io_div_waddr_wb; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_div_cancel; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 286:22]
|
|
wire [11:0] decode_io_dec_lsu_offset_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_csr_ren_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 286:22]
|
|
wire [11:0] decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_csr_wen_r; // @[el2_dec.scala 286:22]
|
|
wire [11:0] decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 286:22]
|
|
wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 286:22]
|
|
wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 286:22]
|
|
wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 286:22]
|
|
wire [31:0] decode_io_dec_illegal_inst; // @[el2_dec.scala 286:22]
|
|
wire [30:0] decode_io_pred_correct_npc_x; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_predict_p_d_bits_pc4; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_dec_i0_predict_p_d_bits_hist; // @[el2_dec.scala 286:22]
|
|
wire [11:0] decode_io_dec_i0_predict_p_d_bits_toffset; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_predict_p_d_bits_br_error; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_dec.scala 286:22]
|
|
wire [30:0] decode_io_dec_i0_predict_p_d_bits_prett; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_predict_p_d_bits_pcall; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_predict_p_d_bits_pret; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_predict_p_d_bits_pja; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_i0_predict_p_d_bits_way; // @[el2_dec.scala 286:22]
|
|
wire [7:0] decode_io_i0_predict_fghr_d; // @[el2_dec.scala 286:22]
|
|
wire [7:0] decode_io_i0_predict_index_d; // @[el2_dec.scala 286:22]
|
|
wire [4:0] decode_io_i0_predict_btag_d; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_dec_data_en; // @[el2_dec.scala 286:22]
|
|
wire [1:0] decode_io_dec_ctl_en; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 286:22]
|
|
wire [4:0] decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_pause_state; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_pause_state_cg; // @[el2_dec.scala 286:22]
|
|
wire decode_io_dec_div_active; // @[el2_dec.scala 286:22]
|
|
wire decode_io_scan_mode; // @[el2_dec.scala 286:22]
|
|
wire gpr_clock; // @[el2_dec.scala 287:19]
|
|
wire gpr_reset; // @[el2_dec.scala 287:19]
|
|
wire [4:0] gpr_io_raddr0; // @[el2_dec.scala 287:19]
|
|
wire [4:0] gpr_io_raddr1; // @[el2_dec.scala 287:19]
|
|
wire gpr_io_wen0; // @[el2_dec.scala 287:19]
|
|
wire [4:0] gpr_io_waddr0; // @[el2_dec.scala 287:19]
|
|
wire [31:0] gpr_io_wd0; // @[el2_dec.scala 287:19]
|
|
wire gpr_io_wen1; // @[el2_dec.scala 287:19]
|
|
wire [4:0] gpr_io_waddr1; // @[el2_dec.scala 287:19]
|
|
wire [31:0] gpr_io_wd1; // @[el2_dec.scala 287:19]
|
|
wire gpr_io_wen2; // @[el2_dec.scala 287:19]
|
|
wire [4:0] gpr_io_waddr2; // @[el2_dec.scala 287:19]
|
|
wire [31:0] gpr_io_wd2; // @[el2_dec.scala 287:19]
|
|
wire [31:0] gpr_io_rd0; // @[el2_dec.scala 287:19]
|
|
wire [31:0] gpr_io_rd1; // @[el2_dec.scala 287:19]
|
|
wire gpr_io_scan_mode; // @[el2_dec.scala 287:19]
|
|
wire tlu_clock; // @[el2_dec.scala 288:19]
|
|
wire tlu_reset; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_active_clk; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_free_clk; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_scan_mode; // @[el2_dec.scala 288:19]
|
|
wire [30:0] tlu_io_rst_vec; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_nmi_int; // @[el2_dec.scala 288:19]
|
|
wire [30:0] tlu_io_nmi_vec; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_i_cpu_halt_req; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_i_cpu_run_req; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_fastint_stall_any; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_ifu_pmu_instr_aligned; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_ifu_pmu_fetch_stall; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_ifu_pmu_ic_miss; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_ifu_pmu_ic_hit; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_ifu_pmu_bus_error; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_ifu_pmu_bus_busy; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_ifu_pmu_bus_trxn; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_pmu_instr_decoded; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_pmu_decode_stall; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_pmu_presync_stall; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_pmu_postsync_stall; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_store_stall_any; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dma_dccm_stall_any; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dma_iccm_stall_any; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_exu_pmu_i0_br_misp; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_exu_pmu_i0_pc4; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_pmu_bus_trxn; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_pmu_bus_error; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_pmu_bus_busy; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_pmu_load_external_m; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_pmu_store_external_m; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dma_pmu_dccm_read; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dma_pmu_dccm_write; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dma_pmu_any_read; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dma_pmu_any_write; // @[el2_dec.scala 288:19]
|
|
wire [30:0] tlu_io_lsu_fir_addr; // @[el2_dec.scala 288:19]
|
|
wire [1:0] tlu_io_lsu_fir_error; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_iccm_dma_sb_error; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_error_pkt_r_valid; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 288:19]
|
|
wire [3:0] tlu_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 288:19]
|
|
wire [31:0] tlu_io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_single_ecc_error_incr; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_pause_state; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_imprecise_error_store_any; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_imprecise_error_load_any; // @[el2_dec.scala 288:19]
|
|
wire [31:0] tlu_io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_csr_wen_unq_d; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_csr_any_unq_d; // @[el2_dec.scala 288:19]
|
|
wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_csr_wen_r; // @[el2_dec.scala 288:19]
|
|
wire [11:0] tlu_io_dec_csr_wraddr_r; // @[el2_dec.scala 288:19]
|
|
wire [31:0] tlu_io_dec_csr_wrdata_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_csr_stall_int_ff; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 288:19]
|
|
wire [30:0] tlu_io_exu_npc_r; // @[el2_dec.scala 288:19]
|
|
wire [30:0] tlu_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 288:19]
|
|
wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 288:19]
|
|
wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 288:19]
|
|
wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 288:19]
|
|
wire [31:0] tlu_io_dec_illegal_inst; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_i0_decode_d; // @[el2_dec.scala 288:19]
|
|
wire [1:0] tlu_io_exu_i0_br_hist_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_exu_i0_br_error_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_exu_i0_br_start_error_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_exu_i0_br_valid_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_exu_i0_br_mp_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_exu_i0_br_middle_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_exu_i0_br_way_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 288:19]
|
|
wire [29:0] tlu_io_dec_tlu_meihap; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dbg_halt_req; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dbg_resume_req; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_ifu_miss_state_idle; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_lsu_idle_any; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_div_active; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 288:19]
|
|
wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 288:19]
|
|
wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 288:19]
|
|
wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 288:19]
|
|
wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_ifu_ic_error_start; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 288:19]
|
|
wire [70:0] tlu_io_ifu_ic_debug_rd_data; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 288:19]
|
|
wire [70:0] tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 288:19]
|
|
wire [16:0] tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 288:19]
|
|
wire [7:0] tlu_io_pic_claimid; // @[el2_dec.scala 288:19]
|
|
wire [3:0] tlu_io_pic_pl; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_mhwakeup; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_mexintpend; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_timer_int; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_soft_int; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_o_cpu_halt_status; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_o_cpu_run_ack; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_o_debug_mode_status; // @[el2_dec.scala 288:19]
|
|
wire [27:0] tlu_io_core_id; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_mpc_debug_halt_req; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_mpc_debug_run_req; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_mpc_reset_run_req; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_debug_brkpt_status; // @[el2_dec.scala 288:19]
|
|
wire [3:0] tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 288:19]
|
|
wire [3:0] tlu_io_dec_tlu_meipt; // @[el2_dec.scala 288:19]
|
|
wire [31:0] tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_csr_legal_d; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 288:19]
|
|
wire [1:0] tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 288:19]
|
|
wire [30:0] tlu_io_dec_tlu_flush_path_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 288:19]
|
|
wire [31:0] tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_i0_valid_wb1; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_int_valid_wb1; // @[el2_dec.scala 288:19]
|
|
wire [4:0] tlu_io_dec_tlu_exc_cause_wb1; // @[el2_dec.scala 288:19]
|
|
wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 288:19]
|
|
wire [2:0] tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 288:19]
|
|
wire tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 288:19]
|
|
wire dec_trigger_io_trigger_pkt_any_0_select; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_0_m; // @[el2_dec.scala 289:27]
|
|
wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_1_select; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_1_m; // @[el2_dec.scala 289:27]
|
|
wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_2_select; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_2_m; // @[el2_dec.scala 289:27]
|
|
wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_3_select; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 289:27]
|
|
wire dec_trigger_io_trigger_pkt_any_3_m; // @[el2_dec.scala 289:27]
|
|
wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 289:27]
|
|
wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[el2_dec.scala 289:27]
|
|
wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 289:27]
|
|
wire _T_1 = tlu_io_dec_tlu_i0_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec.scala 592:98]
|
|
el2_dec_ib_ctl instbuff ( // @[el2_dec.scala 285:24]
|
|
.io_dbg_cmd_valid(instbuff_io_dbg_cmd_valid),
|
|
.io_dbg_cmd_write(instbuff_io_dbg_cmd_write),
|
|
.io_dbg_cmd_type(instbuff_io_dbg_cmd_type),
|
|
.io_dbg_cmd_addr(instbuff_io_dbg_cmd_addr),
|
|
.io_i0_brp_valid(instbuff_io_i0_brp_valid),
|
|
.io_i0_brp_toffset(instbuff_io_i0_brp_toffset),
|
|
.io_i0_brp_hist(instbuff_io_i0_brp_hist),
|
|
.io_i0_brp_br_error(instbuff_io_i0_brp_br_error),
|
|
.io_i0_brp_br_start_error(instbuff_io_i0_brp_br_start_error),
|
|
.io_i0_brp_prett(instbuff_io_i0_brp_prett),
|
|
.io_i0_brp_way(instbuff_io_i0_brp_way),
|
|
.io_i0_brp_ret(instbuff_io_i0_brp_ret),
|
|
.io_ifu_i0_bp_index(instbuff_io_ifu_i0_bp_index),
|
|
.io_ifu_i0_bp_fghr(instbuff_io_ifu_i0_bp_fghr),
|
|
.io_ifu_i0_bp_btag(instbuff_io_ifu_i0_bp_btag),
|
|
.io_ifu_i0_pc4(instbuff_io_ifu_i0_pc4),
|
|
.io_ifu_i0_valid(instbuff_io_ifu_i0_valid),
|
|
.io_ifu_i0_icaf(instbuff_io_ifu_i0_icaf),
|
|
.io_ifu_i0_icaf_type(instbuff_io_ifu_i0_icaf_type),
|
|
.io_ifu_i0_icaf_f1(instbuff_io_ifu_i0_icaf_f1),
|
|
.io_ifu_i0_dbecc(instbuff_io_ifu_i0_dbecc),
|
|
.io_ifu_i0_instr(instbuff_io_ifu_i0_instr),
|
|
.io_ifu_i0_pc(instbuff_io_ifu_i0_pc),
|
|
.io_dec_ib0_valid_d(instbuff_io_dec_ib0_valid_d),
|
|
.io_dec_i0_icaf_type_d(instbuff_io_dec_i0_icaf_type_d),
|
|
.io_dec_i0_instr_d(instbuff_io_dec_i0_instr_d),
|
|
.io_dec_i0_pc_d(instbuff_io_dec_i0_pc_d),
|
|
.io_dec_i0_pc4_d(instbuff_io_dec_i0_pc4_d),
|
|
.io_dec_i0_brp_valid(instbuff_io_dec_i0_brp_valid),
|
|
.io_dec_i0_brp_toffset(instbuff_io_dec_i0_brp_toffset),
|
|
.io_dec_i0_brp_hist(instbuff_io_dec_i0_brp_hist),
|
|
.io_dec_i0_brp_br_error(instbuff_io_dec_i0_brp_br_error),
|
|
.io_dec_i0_brp_br_start_error(instbuff_io_dec_i0_brp_br_start_error),
|
|
.io_dec_i0_brp_prett(instbuff_io_dec_i0_brp_prett),
|
|
.io_dec_i0_brp_way(instbuff_io_dec_i0_brp_way),
|
|
.io_dec_i0_brp_ret(instbuff_io_dec_i0_brp_ret),
|
|
.io_dec_i0_bp_index(instbuff_io_dec_i0_bp_index),
|
|
.io_dec_i0_bp_fghr(instbuff_io_dec_i0_bp_fghr),
|
|
.io_dec_i0_bp_btag(instbuff_io_dec_i0_bp_btag),
|
|
.io_dec_i0_icaf_d(instbuff_io_dec_i0_icaf_d),
|
|
.io_dec_i0_icaf_f1_d(instbuff_io_dec_i0_icaf_f1_d),
|
|
.io_dec_i0_dbecc_d(instbuff_io_dec_i0_dbecc_d),
|
|
.io_dec_debug_wdata_rs1_d(instbuff_io_dec_debug_wdata_rs1_d),
|
|
.io_dec_debug_fence_d(instbuff_io_dec_debug_fence_d)
|
|
);
|
|
el2_dec_decode_ctl decode ( // @[el2_dec.scala 286:22]
|
|
.clock(decode_clock),
|
|
.reset(decode_reset),
|
|
.io_dec_tlu_flush_extint(decode_io_dec_tlu_flush_extint),
|
|
.io_dec_tlu_force_halt(decode_io_dec_tlu_force_halt),
|
|
.io_dec_extint_stall(decode_io_dec_extint_stall),
|
|
.io_ifu_i0_cinst(decode_io_ifu_i0_cinst),
|
|
.io_dec_i0_inst_wb1(decode_io_dec_i0_inst_wb1),
|
|
.io_dec_i0_pc_wb1(decode_io_dec_i0_pc_wb1),
|
|
.io_lsu_nonblock_load_valid_m(decode_io_lsu_nonblock_load_valid_m),
|
|
.io_lsu_nonblock_load_tag_m(decode_io_lsu_nonblock_load_tag_m),
|
|
.io_lsu_nonblock_load_inv_r(decode_io_lsu_nonblock_load_inv_r),
|
|
.io_lsu_nonblock_load_inv_tag_r(decode_io_lsu_nonblock_load_inv_tag_r),
|
|
.io_lsu_nonblock_load_data_valid(decode_io_lsu_nonblock_load_data_valid),
|
|
.io_lsu_nonblock_load_data_error(decode_io_lsu_nonblock_load_data_error),
|
|
.io_lsu_nonblock_load_data_tag(decode_io_lsu_nonblock_load_data_tag),
|
|
.io_lsu_nonblock_load_data(decode_io_lsu_nonblock_load_data),
|
|
.io_dec_i0_trigger_match_d(decode_io_dec_i0_trigger_match_d),
|
|
.io_dec_tlu_wr_pause_r(decode_io_dec_tlu_wr_pause_r),
|
|
.io_dec_tlu_pipelining_disable(decode_io_dec_tlu_pipelining_disable),
|
|
.io_lsu_trigger_match_m(decode_io_lsu_trigger_match_m),
|
|
.io_lsu_pmu_misaligned_m(decode_io_lsu_pmu_misaligned_m),
|
|
.io_dec_tlu_debug_stall(decode_io_dec_tlu_debug_stall),
|
|
.io_dec_tlu_flush_leak_one_r(decode_io_dec_tlu_flush_leak_one_r),
|
|
.io_dec_debug_fence_d(decode_io_dec_debug_fence_d),
|
|
.io_dbg_cmd_wrdata(decode_io_dbg_cmd_wrdata),
|
|
.io_dec_i0_icaf_d(decode_io_dec_i0_icaf_d),
|
|
.io_dec_i0_icaf_f1_d(decode_io_dec_i0_icaf_f1_d),
|
|
.io_dec_i0_icaf_type_d(decode_io_dec_i0_icaf_type_d),
|
|
.io_dec_i0_dbecc_d(decode_io_dec_i0_dbecc_d),
|
|
.io_dec_i0_brp_valid(decode_io_dec_i0_brp_valid),
|
|
.io_dec_i0_brp_toffset(decode_io_dec_i0_brp_toffset),
|
|
.io_dec_i0_brp_hist(decode_io_dec_i0_brp_hist),
|
|
.io_dec_i0_brp_br_error(decode_io_dec_i0_brp_br_error),
|
|
.io_dec_i0_brp_br_start_error(decode_io_dec_i0_brp_br_start_error),
|
|
.io_dec_i0_brp_prett(decode_io_dec_i0_brp_prett),
|
|
.io_dec_i0_brp_way(decode_io_dec_i0_brp_way),
|
|
.io_dec_i0_brp_ret(decode_io_dec_i0_brp_ret),
|
|
.io_dec_i0_bp_index(decode_io_dec_i0_bp_index),
|
|
.io_dec_i0_bp_fghr(decode_io_dec_i0_bp_fghr),
|
|
.io_dec_i0_bp_btag(decode_io_dec_i0_bp_btag),
|
|
.io_lsu_idle_any(decode_io_lsu_idle_any),
|
|
.io_lsu_load_stall_any(decode_io_lsu_load_stall_any),
|
|
.io_lsu_store_stall_any(decode_io_lsu_store_stall_any),
|
|
.io_dma_dccm_stall_any(decode_io_dma_dccm_stall_any),
|
|
.io_exu_div_wren(decode_io_exu_div_wren),
|
|
.io_dec_tlu_i0_kill_writeb_wb(decode_io_dec_tlu_i0_kill_writeb_wb),
|
|
.io_dec_tlu_flush_lower_wb(decode_io_dec_tlu_flush_lower_wb),
|
|
.io_dec_tlu_i0_kill_writeb_r(decode_io_dec_tlu_i0_kill_writeb_r),
|
|
.io_dec_tlu_flush_lower_r(decode_io_dec_tlu_flush_lower_r),
|
|
.io_dec_tlu_flush_pause_r(decode_io_dec_tlu_flush_pause_r),
|
|
.io_dec_tlu_presync_d(decode_io_dec_tlu_presync_d),
|
|
.io_dec_tlu_postsync_d(decode_io_dec_tlu_postsync_d),
|
|
.io_dec_i0_pc4_d(decode_io_dec_i0_pc4_d),
|
|
.io_dec_csr_rddata_d(decode_io_dec_csr_rddata_d),
|
|
.io_dec_csr_legal_d(decode_io_dec_csr_legal_d),
|
|
.io_exu_csr_rs1_x(decode_io_exu_csr_rs1_x),
|
|
.io_lsu_result_m(decode_io_lsu_result_m),
|
|
.io_lsu_result_corr_r(decode_io_lsu_result_corr_r),
|
|
.io_exu_flush_final(decode_io_exu_flush_final),
|
|
.io_exu_i0_pc_x(decode_io_exu_i0_pc_x),
|
|
.io_dec_i0_instr_d(decode_io_dec_i0_instr_d),
|
|
.io_dec_ib0_valid_d(decode_io_dec_ib0_valid_d),
|
|
.io_exu_i0_result_x(decode_io_exu_i0_result_x),
|
|
.io_free_clk(decode_io_free_clk),
|
|
.io_active_clk(decode_io_active_clk),
|
|
.io_clk_override(decode_io_clk_override),
|
|
.io_dec_i0_rs1_en_d(decode_io_dec_i0_rs1_en_d),
|
|
.io_dec_i0_rs2_en_d(decode_io_dec_i0_rs2_en_d),
|
|
.io_dec_i0_rs1_d(decode_io_dec_i0_rs1_d),
|
|
.io_dec_i0_rs2_d(decode_io_dec_i0_rs2_d),
|
|
.io_dec_i0_immed_d(decode_io_dec_i0_immed_d),
|
|
.io_dec_i0_br_immed_d(decode_io_dec_i0_br_immed_d),
|
|
.io_i0_ap_land(decode_io_i0_ap_land),
|
|
.io_i0_ap_lor(decode_io_i0_ap_lor),
|
|
.io_i0_ap_lxor(decode_io_i0_ap_lxor),
|
|
.io_i0_ap_sll(decode_io_i0_ap_sll),
|
|
.io_i0_ap_srl(decode_io_i0_ap_srl),
|
|
.io_i0_ap_sra(decode_io_i0_ap_sra),
|
|
.io_i0_ap_beq(decode_io_i0_ap_beq),
|
|
.io_i0_ap_bne(decode_io_i0_ap_bne),
|
|
.io_i0_ap_blt(decode_io_i0_ap_blt),
|
|
.io_i0_ap_bge(decode_io_i0_ap_bge),
|
|
.io_i0_ap_add(decode_io_i0_ap_add),
|
|
.io_i0_ap_sub(decode_io_i0_ap_sub),
|
|
.io_i0_ap_slt(decode_io_i0_ap_slt),
|
|
.io_i0_ap_unsign(decode_io_i0_ap_unsign),
|
|
.io_i0_ap_jal(decode_io_i0_ap_jal),
|
|
.io_i0_ap_predict_t(decode_io_i0_ap_predict_t),
|
|
.io_i0_ap_predict_nt(decode_io_i0_ap_predict_nt),
|
|
.io_i0_ap_csr_write(decode_io_i0_ap_csr_write),
|
|
.io_i0_ap_csr_imm(decode_io_i0_ap_csr_imm),
|
|
.io_dec_i0_decode_d(decode_io_dec_i0_decode_d),
|
|
.io_dec_i0_alu_decode_d(decode_io_dec_i0_alu_decode_d),
|
|
.io_dec_i0_rs1_bypass_data_d(decode_io_dec_i0_rs1_bypass_data_d),
|
|
.io_dec_i0_rs2_bypass_data_d(decode_io_dec_i0_rs2_bypass_data_d),
|
|
.io_dec_i0_waddr_r(decode_io_dec_i0_waddr_r),
|
|
.io_dec_i0_wen_r(decode_io_dec_i0_wen_r),
|
|
.io_dec_i0_wdata_r(decode_io_dec_i0_wdata_r),
|
|
.io_dec_i0_select_pc_d(decode_io_dec_i0_select_pc_d),
|
|
.io_dec_i0_rs1_bypass_en_d(decode_io_dec_i0_rs1_bypass_en_d),
|
|
.io_dec_i0_rs2_bypass_en_d(decode_io_dec_i0_rs2_bypass_en_d),
|
|
.io_lsu_p_valid(decode_io_lsu_p_valid),
|
|
.io_lsu_p_bits_fast_int(decode_io_lsu_p_bits_fast_int),
|
|
.io_lsu_p_bits_by(decode_io_lsu_p_bits_by),
|
|
.io_lsu_p_bits_half(decode_io_lsu_p_bits_half),
|
|
.io_lsu_p_bits_word(decode_io_lsu_p_bits_word),
|
|
.io_lsu_p_bits_load(decode_io_lsu_p_bits_load),
|
|
.io_lsu_p_bits_store(decode_io_lsu_p_bits_store),
|
|
.io_lsu_p_bits_unsign(decode_io_lsu_p_bits_unsign),
|
|
.io_lsu_p_bits_store_data_bypass_d(decode_io_lsu_p_bits_store_data_bypass_d),
|
|
.io_lsu_p_bits_load_ldst_bypass_d(decode_io_lsu_p_bits_load_ldst_bypass_d),
|
|
.io_mul_p_valid(decode_io_mul_p_valid),
|
|
.io_mul_p_bits_rs1_sign(decode_io_mul_p_bits_rs1_sign),
|
|
.io_mul_p_bits_rs2_sign(decode_io_mul_p_bits_rs2_sign),
|
|
.io_mul_p_bits_low(decode_io_mul_p_bits_low),
|
|
.io_div_p_valid(decode_io_div_p_valid),
|
|
.io_div_p_bits_unsign(decode_io_div_p_bits_unsign),
|
|
.io_div_p_bits_rem(decode_io_div_p_bits_rem),
|
|
.io_div_waddr_wb(decode_io_div_waddr_wb),
|
|
.io_dec_div_cancel(decode_io_dec_div_cancel),
|
|
.io_dec_lsu_valid_raw_d(decode_io_dec_lsu_valid_raw_d),
|
|
.io_dec_lsu_offset_d(decode_io_dec_lsu_offset_d),
|
|
.io_dec_csr_ren_d(decode_io_dec_csr_ren_d),
|
|
.io_dec_csr_wen_unq_d(decode_io_dec_csr_wen_unq_d),
|
|
.io_dec_csr_any_unq_d(decode_io_dec_csr_any_unq_d),
|
|
.io_dec_csr_rdaddr_d(decode_io_dec_csr_rdaddr_d),
|
|
.io_dec_csr_wen_r(decode_io_dec_csr_wen_r),
|
|
.io_dec_csr_wraddr_r(decode_io_dec_csr_wraddr_r),
|
|
.io_dec_csr_wrdata_r(decode_io_dec_csr_wrdata_r),
|
|
.io_dec_csr_stall_int_ff(decode_io_dec_csr_stall_int_ff),
|
|
.io_dec_tlu_i0_valid_r(decode_io_dec_tlu_i0_valid_r),
|
|
.io_dec_tlu_packet_r_legal(decode_io_dec_tlu_packet_r_legal),
|
|
.io_dec_tlu_packet_r_icaf(decode_io_dec_tlu_packet_r_icaf),
|
|
.io_dec_tlu_packet_r_icaf_f1(decode_io_dec_tlu_packet_r_icaf_f1),
|
|
.io_dec_tlu_packet_r_icaf_type(decode_io_dec_tlu_packet_r_icaf_type),
|
|
.io_dec_tlu_packet_r_fence_i(decode_io_dec_tlu_packet_r_fence_i),
|
|
.io_dec_tlu_packet_r_i0trigger(decode_io_dec_tlu_packet_r_i0trigger),
|
|
.io_dec_tlu_packet_r_pmu_i0_itype(decode_io_dec_tlu_packet_r_pmu_i0_itype),
|
|
.io_dec_tlu_packet_r_pmu_i0_br_unpred(decode_io_dec_tlu_packet_r_pmu_i0_br_unpred),
|
|
.io_dec_tlu_packet_r_pmu_divide(decode_io_dec_tlu_packet_r_pmu_divide),
|
|
.io_dec_tlu_packet_r_pmu_lsu_misaligned(decode_io_dec_tlu_packet_r_pmu_lsu_misaligned),
|
|
.io_dec_tlu_i0_pc_r(decode_io_dec_tlu_i0_pc_r),
|
|
.io_dec_illegal_inst(decode_io_dec_illegal_inst),
|
|
.io_pred_correct_npc_x(decode_io_pred_correct_npc_x),
|
|
.io_dec_i0_predict_p_d_valid(decode_io_dec_i0_predict_p_d_valid),
|
|
.io_dec_i0_predict_p_d_bits_pc4(decode_io_dec_i0_predict_p_d_bits_pc4),
|
|
.io_dec_i0_predict_p_d_bits_hist(decode_io_dec_i0_predict_p_d_bits_hist),
|
|
.io_dec_i0_predict_p_d_bits_toffset(decode_io_dec_i0_predict_p_d_bits_toffset),
|
|
.io_dec_i0_predict_p_d_bits_br_error(decode_io_dec_i0_predict_p_d_bits_br_error),
|
|
.io_dec_i0_predict_p_d_bits_br_start_error(decode_io_dec_i0_predict_p_d_bits_br_start_error),
|
|
.io_dec_i0_predict_p_d_bits_prett(decode_io_dec_i0_predict_p_d_bits_prett),
|
|
.io_dec_i0_predict_p_d_bits_pcall(decode_io_dec_i0_predict_p_d_bits_pcall),
|
|
.io_dec_i0_predict_p_d_bits_pret(decode_io_dec_i0_predict_p_d_bits_pret),
|
|
.io_dec_i0_predict_p_d_bits_pja(decode_io_dec_i0_predict_p_d_bits_pja),
|
|
.io_dec_i0_predict_p_d_bits_way(decode_io_dec_i0_predict_p_d_bits_way),
|
|
.io_i0_predict_fghr_d(decode_io_i0_predict_fghr_d),
|
|
.io_i0_predict_index_d(decode_io_i0_predict_index_d),
|
|
.io_i0_predict_btag_d(decode_io_i0_predict_btag_d),
|
|
.io_dec_data_en(decode_io_dec_data_en),
|
|
.io_dec_ctl_en(decode_io_dec_ctl_en),
|
|
.io_dec_pmu_instr_decoded(decode_io_dec_pmu_instr_decoded),
|
|
.io_dec_pmu_decode_stall(decode_io_dec_pmu_decode_stall),
|
|
.io_dec_pmu_presync_stall(decode_io_dec_pmu_presync_stall),
|
|
.io_dec_pmu_postsync_stall(decode_io_dec_pmu_postsync_stall),
|
|
.io_dec_nonblock_load_wen(decode_io_dec_nonblock_load_wen),
|
|
.io_dec_nonblock_load_waddr(decode_io_dec_nonblock_load_waddr),
|
|
.io_dec_pause_state(decode_io_dec_pause_state),
|
|
.io_dec_pause_state_cg(decode_io_dec_pause_state_cg),
|
|
.io_dec_div_active(decode_io_dec_div_active),
|
|
.io_scan_mode(decode_io_scan_mode)
|
|
);
|
|
el2_dec_gpr_ctl gpr ( // @[el2_dec.scala 287:19]
|
|
.clock(gpr_clock),
|
|
.reset(gpr_reset),
|
|
.io_raddr0(gpr_io_raddr0),
|
|
.io_raddr1(gpr_io_raddr1),
|
|
.io_wen0(gpr_io_wen0),
|
|
.io_waddr0(gpr_io_waddr0),
|
|
.io_wd0(gpr_io_wd0),
|
|
.io_wen1(gpr_io_wen1),
|
|
.io_waddr1(gpr_io_waddr1),
|
|
.io_wd1(gpr_io_wd1),
|
|
.io_wen2(gpr_io_wen2),
|
|
.io_waddr2(gpr_io_waddr2),
|
|
.io_wd2(gpr_io_wd2),
|
|
.io_rd0(gpr_io_rd0),
|
|
.io_rd1(gpr_io_rd1),
|
|
.io_scan_mode(gpr_io_scan_mode)
|
|
);
|
|
el2_dec_tlu_ctl tlu ( // @[el2_dec.scala 288:19]
|
|
.clock(tlu_clock),
|
|
.reset(tlu_reset),
|
|
.io_active_clk(tlu_io_active_clk),
|
|
.io_free_clk(tlu_io_free_clk),
|
|
.io_scan_mode(tlu_io_scan_mode),
|
|
.io_rst_vec(tlu_io_rst_vec),
|
|
.io_nmi_int(tlu_io_nmi_int),
|
|
.io_nmi_vec(tlu_io_nmi_vec),
|
|
.io_i_cpu_halt_req(tlu_io_i_cpu_halt_req),
|
|
.io_i_cpu_run_req(tlu_io_i_cpu_run_req),
|
|
.io_lsu_fastint_stall_any(tlu_io_lsu_fastint_stall_any),
|
|
.io_ifu_pmu_instr_aligned(tlu_io_ifu_pmu_instr_aligned),
|
|
.io_ifu_pmu_fetch_stall(tlu_io_ifu_pmu_fetch_stall),
|
|
.io_ifu_pmu_ic_miss(tlu_io_ifu_pmu_ic_miss),
|
|
.io_ifu_pmu_ic_hit(tlu_io_ifu_pmu_ic_hit),
|
|
.io_ifu_pmu_bus_error(tlu_io_ifu_pmu_bus_error),
|
|
.io_ifu_pmu_bus_busy(tlu_io_ifu_pmu_bus_busy),
|
|
.io_ifu_pmu_bus_trxn(tlu_io_ifu_pmu_bus_trxn),
|
|
.io_dec_pmu_instr_decoded(tlu_io_dec_pmu_instr_decoded),
|
|
.io_dec_pmu_decode_stall(tlu_io_dec_pmu_decode_stall),
|
|
.io_dec_pmu_presync_stall(tlu_io_dec_pmu_presync_stall),
|
|
.io_dec_pmu_postsync_stall(tlu_io_dec_pmu_postsync_stall),
|
|
.io_lsu_store_stall_any(tlu_io_lsu_store_stall_any),
|
|
.io_dma_dccm_stall_any(tlu_io_dma_dccm_stall_any),
|
|
.io_dma_iccm_stall_any(tlu_io_dma_iccm_stall_any),
|
|
.io_exu_pmu_i0_br_misp(tlu_io_exu_pmu_i0_br_misp),
|
|
.io_exu_pmu_i0_br_ataken(tlu_io_exu_pmu_i0_br_ataken),
|
|
.io_exu_pmu_i0_pc4(tlu_io_exu_pmu_i0_pc4),
|
|
.io_lsu_pmu_bus_trxn(tlu_io_lsu_pmu_bus_trxn),
|
|
.io_lsu_pmu_bus_misaligned(tlu_io_lsu_pmu_bus_misaligned),
|
|
.io_lsu_pmu_bus_error(tlu_io_lsu_pmu_bus_error),
|
|
.io_lsu_pmu_bus_busy(tlu_io_lsu_pmu_bus_busy),
|
|
.io_lsu_pmu_load_external_m(tlu_io_lsu_pmu_load_external_m),
|
|
.io_lsu_pmu_store_external_m(tlu_io_lsu_pmu_store_external_m),
|
|
.io_dma_pmu_dccm_read(tlu_io_dma_pmu_dccm_read),
|
|
.io_dma_pmu_dccm_write(tlu_io_dma_pmu_dccm_write),
|
|
.io_dma_pmu_any_read(tlu_io_dma_pmu_any_read),
|
|
.io_dma_pmu_any_write(tlu_io_dma_pmu_any_write),
|
|
.io_lsu_fir_addr(tlu_io_lsu_fir_addr),
|
|
.io_lsu_fir_error(tlu_io_lsu_fir_error),
|
|
.io_iccm_dma_sb_error(tlu_io_iccm_dma_sb_error),
|
|
.io_lsu_error_pkt_r_valid(tlu_io_lsu_error_pkt_r_valid),
|
|
.io_lsu_error_pkt_r_bits_single_ecc_error(tlu_io_lsu_error_pkt_r_bits_single_ecc_error),
|
|
.io_lsu_error_pkt_r_bits_inst_type(tlu_io_lsu_error_pkt_r_bits_inst_type),
|
|
.io_lsu_error_pkt_r_bits_exc_type(tlu_io_lsu_error_pkt_r_bits_exc_type),
|
|
.io_lsu_error_pkt_r_bits_mscause(tlu_io_lsu_error_pkt_r_bits_mscause),
|
|
.io_lsu_error_pkt_r_bits_addr(tlu_io_lsu_error_pkt_r_bits_addr),
|
|
.io_lsu_single_ecc_error_incr(tlu_io_lsu_single_ecc_error_incr),
|
|
.io_dec_pause_state(tlu_io_dec_pause_state),
|
|
.io_lsu_imprecise_error_store_any(tlu_io_lsu_imprecise_error_store_any),
|
|
.io_lsu_imprecise_error_load_any(tlu_io_lsu_imprecise_error_load_any),
|
|
.io_lsu_imprecise_error_addr_any(tlu_io_lsu_imprecise_error_addr_any),
|
|
.io_dec_csr_wen_unq_d(tlu_io_dec_csr_wen_unq_d),
|
|
.io_dec_csr_any_unq_d(tlu_io_dec_csr_any_unq_d),
|
|
.io_dec_csr_rdaddr_d(tlu_io_dec_csr_rdaddr_d),
|
|
.io_dec_csr_wen_r(tlu_io_dec_csr_wen_r),
|
|
.io_dec_csr_wraddr_r(tlu_io_dec_csr_wraddr_r),
|
|
.io_dec_csr_wrdata_r(tlu_io_dec_csr_wrdata_r),
|
|
.io_dec_csr_stall_int_ff(tlu_io_dec_csr_stall_int_ff),
|
|
.io_dec_tlu_i0_valid_r(tlu_io_dec_tlu_i0_valid_r),
|
|
.io_exu_npc_r(tlu_io_exu_npc_r),
|
|
.io_dec_tlu_i0_pc_r(tlu_io_dec_tlu_i0_pc_r),
|
|
.io_dec_tlu_packet_r_legal(tlu_io_dec_tlu_packet_r_legal),
|
|
.io_dec_tlu_packet_r_icaf(tlu_io_dec_tlu_packet_r_icaf),
|
|
.io_dec_tlu_packet_r_icaf_f1(tlu_io_dec_tlu_packet_r_icaf_f1),
|
|
.io_dec_tlu_packet_r_icaf_type(tlu_io_dec_tlu_packet_r_icaf_type),
|
|
.io_dec_tlu_packet_r_fence_i(tlu_io_dec_tlu_packet_r_fence_i),
|
|
.io_dec_tlu_packet_r_i0trigger(tlu_io_dec_tlu_packet_r_i0trigger),
|
|
.io_dec_tlu_packet_r_pmu_i0_itype(tlu_io_dec_tlu_packet_r_pmu_i0_itype),
|
|
.io_dec_tlu_packet_r_pmu_i0_br_unpred(tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred),
|
|
.io_dec_tlu_packet_r_pmu_divide(tlu_io_dec_tlu_packet_r_pmu_divide),
|
|
.io_dec_tlu_packet_r_pmu_lsu_misaligned(tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned),
|
|
.io_dec_illegal_inst(tlu_io_dec_illegal_inst),
|
|
.io_dec_i0_decode_d(tlu_io_dec_i0_decode_d),
|
|
.io_exu_i0_br_hist_r(tlu_io_exu_i0_br_hist_r),
|
|
.io_exu_i0_br_error_r(tlu_io_exu_i0_br_error_r),
|
|
.io_exu_i0_br_start_error_r(tlu_io_exu_i0_br_start_error_r),
|
|
.io_exu_i0_br_valid_r(tlu_io_exu_i0_br_valid_r),
|
|
.io_exu_i0_br_mp_r(tlu_io_exu_i0_br_mp_r),
|
|
.io_exu_i0_br_middle_r(tlu_io_exu_i0_br_middle_r),
|
|
.io_exu_i0_br_way_r(tlu_io_exu_i0_br_way_r),
|
|
.io_dec_dbg_cmd_done(tlu_io_dec_dbg_cmd_done),
|
|
.io_dec_dbg_cmd_fail(tlu_io_dec_dbg_cmd_fail),
|
|
.io_dec_tlu_dbg_halted(tlu_io_dec_tlu_dbg_halted),
|
|
.io_dec_tlu_debug_mode(tlu_io_dec_tlu_debug_mode),
|
|
.io_dec_tlu_resume_ack(tlu_io_dec_tlu_resume_ack),
|
|
.io_dec_tlu_debug_stall(tlu_io_dec_tlu_debug_stall),
|
|
.io_dec_tlu_flush_noredir_r(tlu_io_dec_tlu_flush_noredir_r),
|
|
.io_dec_tlu_mpc_halted_only(tlu_io_dec_tlu_mpc_halted_only),
|
|
.io_dec_tlu_flush_leak_one_r(tlu_io_dec_tlu_flush_leak_one_r),
|
|
.io_dec_tlu_flush_err_r(tlu_io_dec_tlu_flush_err_r),
|
|
.io_dec_tlu_flush_extint(tlu_io_dec_tlu_flush_extint),
|
|
.io_dec_tlu_meihap(tlu_io_dec_tlu_meihap),
|
|
.io_dbg_halt_req(tlu_io_dbg_halt_req),
|
|
.io_dbg_resume_req(tlu_io_dbg_resume_req),
|
|
.io_ifu_miss_state_idle(tlu_io_ifu_miss_state_idle),
|
|
.io_lsu_idle_any(tlu_io_lsu_idle_any),
|
|
.io_dec_div_active(tlu_io_dec_div_active),
|
|
.io_trigger_pkt_any_0_select(tlu_io_trigger_pkt_any_0_select),
|
|
.io_trigger_pkt_any_0_match_pkt(tlu_io_trigger_pkt_any_0_match_pkt),
|
|
.io_trigger_pkt_any_0_store(tlu_io_trigger_pkt_any_0_store),
|
|
.io_trigger_pkt_any_0_load(tlu_io_trigger_pkt_any_0_load),
|
|
.io_trigger_pkt_any_0_execute(tlu_io_trigger_pkt_any_0_execute),
|
|
.io_trigger_pkt_any_0_m(tlu_io_trigger_pkt_any_0_m),
|
|
.io_trigger_pkt_any_0_tdata2(tlu_io_trigger_pkt_any_0_tdata2),
|
|
.io_trigger_pkt_any_1_select(tlu_io_trigger_pkt_any_1_select),
|
|
.io_trigger_pkt_any_1_match_pkt(tlu_io_trigger_pkt_any_1_match_pkt),
|
|
.io_trigger_pkt_any_1_store(tlu_io_trigger_pkt_any_1_store),
|
|
.io_trigger_pkt_any_1_load(tlu_io_trigger_pkt_any_1_load),
|
|
.io_trigger_pkt_any_1_execute(tlu_io_trigger_pkt_any_1_execute),
|
|
.io_trigger_pkt_any_1_m(tlu_io_trigger_pkt_any_1_m),
|
|
.io_trigger_pkt_any_1_tdata2(tlu_io_trigger_pkt_any_1_tdata2),
|
|
.io_trigger_pkt_any_2_select(tlu_io_trigger_pkt_any_2_select),
|
|
.io_trigger_pkt_any_2_match_pkt(tlu_io_trigger_pkt_any_2_match_pkt),
|
|
.io_trigger_pkt_any_2_store(tlu_io_trigger_pkt_any_2_store),
|
|
.io_trigger_pkt_any_2_load(tlu_io_trigger_pkt_any_2_load),
|
|
.io_trigger_pkt_any_2_execute(tlu_io_trigger_pkt_any_2_execute),
|
|
.io_trigger_pkt_any_2_m(tlu_io_trigger_pkt_any_2_m),
|
|
.io_trigger_pkt_any_2_tdata2(tlu_io_trigger_pkt_any_2_tdata2),
|
|
.io_trigger_pkt_any_3_select(tlu_io_trigger_pkt_any_3_select),
|
|
.io_trigger_pkt_any_3_match_pkt(tlu_io_trigger_pkt_any_3_match_pkt),
|
|
.io_trigger_pkt_any_3_store(tlu_io_trigger_pkt_any_3_store),
|
|
.io_trigger_pkt_any_3_load(tlu_io_trigger_pkt_any_3_load),
|
|
.io_trigger_pkt_any_3_execute(tlu_io_trigger_pkt_any_3_execute),
|
|
.io_trigger_pkt_any_3_m(tlu_io_trigger_pkt_any_3_m),
|
|
.io_trigger_pkt_any_3_tdata2(tlu_io_trigger_pkt_any_3_tdata2),
|
|
.io_ifu_ic_error_start(tlu_io_ifu_ic_error_start),
|
|
.io_ifu_iccm_rd_ecc_single_err(tlu_io_ifu_iccm_rd_ecc_single_err),
|
|
.io_ifu_ic_debug_rd_data(tlu_io_ifu_ic_debug_rd_data),
|
|
.io_ifu_ic_debug_rd_data_valid(tlu_io_ifu_ic_debug_rd_data_valid),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wrdata(tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata),
|
|
.io_dec_tlu_ic_diag_pkt_icache_dicawics(tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics),
|
|
.io_dec_tlu_ic_diag_pkt_icache_rd_valid(tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wr_valid(tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid),
|
|
.io_pic_claimid(tlu_io_pic_claimid),
|
|
.io_pic_pl(tlu_io_pic_pl),
|
|
.io_mhwakeup(tlu_io_mhwakeup),
|
|
.io_mexintpend(tlu_io_mexintpend),
|
|
.io_timer_int(tlu_io_timer_int),
|
|
.io_soft_int(tlu_io_soft_int),
|
|
.io_o_cpu_halt_status(tlu_io_o_cpu_halt_status),
|
|
.io_o_cpu_halt_ack(tlu_io_o_cpu_halt_ack),
|
|
.io_o_cpu_run_ack(tlu_io_o_cpu_run_ack),
|
|
.io_o_debug_mode_status(tlu_io_o_debug_mode_status),
|
|
.io_core_id(tlu_io_core_id),
|
|
.io_mpc_debug_halt_req(tlu_io_mpc_debug_halt_req),
|
|
.io_mpc_debug_run_req(tlu_io_mpc_debug_run_req),
|
|
.io_mpc_reset_run_req(tlu_io_mpc_reset_run_req),
|
|
.io_mpc_debug_halt_ack(tlu_io_mpc_debug_halt_ack),
|
|
.io_mpc_debug_run_ack(tlu_io_mpc_debug_run_ack),
|
|
.io_debug_brkpt_status(tlu_io_debug_brkpt_status),
|
|
.io_dec_tlu_meicurpl(tlu_io_dec_tlu_meicurpl),
|
|
.io_dec_tlu_meipt(tlu_io_dec_tlu_meipt),
|
|
.io_dec_csr_rddata_d(tlu_io_dec_csr_rddata_d),
|
|
.io_dec_csr_legal_d(tlu_io_dec_csr_legal_d),
|
|
.io_dec_tlu_br0_r_pkt_valid(tlu_io_dec_tlu_br0_r_pkt_valid),
|
|
.io_dec_tlu_br0_r_pkt_hist(tlu_io_dec_tlu_br0_r_pkt_hist),
|
|
.io_dec_tlu_br0_r_pkt_br_error(tlu_io_dec_tlu_br0_r_pkt_br_error),
|
|
.io_dec_tlu_br0_r_pkt_br_start_error(tlu_io_dec_tlu_br0_r_pkt_br_start_error),
|
|
.io_dec_tlu_br0_r_pkt_way(tlu_io_dec_tlu_br0_r_pkt_way),
|
|
.io_dec_tlu_br0_r_pkt_middle(tlu_io_dec_tlu_br0_r_pkt_middle),
|
|
.io_dec_tlu_i0_kill_writeb_wb(tlu_io_dec_tlu_i0_kill_writeb_wb),
|
|
.io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb),
|
|
.io_dec_tlu_i0_commit_cmt(tlu_io_dec_tlu_i0_commit_cmt),
|
|
.io_dec_tlu_i0_kill_writeb_r(tlu_io_dec_tlu_i0_kill_writeb_r),
|
|
.io_dec_tlu_flush_lower_r(tlu_io_dec_tlu_flush_lower_r),
|
|
.io_dec_tlu_flush_path_r(tlu_io_dec_tlu_flush_path_r),
|
|
.io_dec_tlu_fence_i_r(tlu_io_dec_tlu_fence_i_r),
|
|
.io_dec_tlu_wr_pause_r(tlu_io_dec_tlu_wr_pause_r),
|
|
.io_dec_tlu_flush_pause_r(tlu_io_dec_tlu_flush_pause_r),
|
|
.io_dec_tlu_presync_d(tlu_io_dec_tlu_presync_d),
|
|
.io_dec_tlu_postsync_d(tlu_io_dec_tlu_postsync_d),
|
|
.io_dec_tlu_mrac_ff(tlu_io_dec_tlu_mrac_ff),
|
|
.io_dec_tlu_force_halt(tlu_io_dec_tlu_force_halt),
|
|
.io_dec_tlu_perfcnt0(tlu_io_dec_tlu_perfcnt0),
|
|
.io_dec_tlu_perfcnt1(tlu_io_dec_tlu_perfcnt1),
|
|
.io_dec_tlu_perfcnt2(tlu_io_dec_tlu_perfcnt2),
|
|
.io_dec_tlu_perfcnt3(tlu_io_dec_tlu_perfcnt3),
|
|
.io_dec_tlu_i0_exc_valid_wb1(tlu_io_dec_tlu_i0_exc_valid_wb1),
|
|
.io_dec_tlu_i0_valid_wb1(tlu_io_dec_tlu_i0_valid_wb1),
|
|
.io_dec_tlu_int_valid_wb1(tlu_io_dec_tlu_int_valid_wb1),
|
|
.io_dec_tlu_exc_cause_wb1(tlu_io_dec_tlu_exc_cause_wb1),
|
|
.io_dec_tlu_mtval_wb1(tlu_io_dec_tlu_mtval_wb1),
|
|
.io_dec_tlu_external_ldfwd_disable(tlu_io_dec_tlu_external_ldfwd_disable),
|
|
.io_dec_tlu_sideeffect_posted_disable(tlu_io_dec_tlu_sideeffect_posted_disable),
|
|
.io_dec_tlu_core_ecc_disable(tlu_io_dec_tlu_core_ecc_disable),
|
|
.io_dec_tlu_bpred_disable(tlu_io_dec_tlu_bpred_disable),
|
|
.io_dec_tlu_wb_coalescing_disable(tlu_io_dec_tlu_wb_coalescing_disable),
|
|
.io_dec_tlu_pipelining_disable(tlu_io_dec_tlu_pipelining_disable),
|
|
.io_dec_tlu_dma_qos_prty(tlu_io_dec_tlu_dma_qos_prty),
|
|
.io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override),
|
|
.io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override),
|
|
.io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override),
|
|
.io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override),
|
|
.io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override),
|
|
.io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override)
|
|
);
|
|
el2_dec_trigger dec_trigger ( // @[el2_dec.scala 289:27]
|
|
.io_trigger_pkt_any_0_select(dec_trigger_io_trigger_pkt_any_0_select),
|
|
.io_trigger_pkt_any_0_match_pkt(dec_trigger_io_trigger_pkt_any_0_match_pkt),
|
|
.io_trigger_pkt_any_0_execute(dec_trigger_io_trigger_pkt_any_0_execute),
|
|
.io_trigger_pkt_any_0_m(dec_trigger_io_trigger_pkt_any_0_m),
|
|
.io_trigger_pkt_any_0_tdata2(dec_trigger_io_trigger_pkt_any_0_tdata2),
|
|
.io_trigger_pkt_any_1_select(dec_trigger_io_trigger_pkt_any_1_select),
|
|
.io_trigger_pkt_any_1_match_pkt(dec_trigger_io_trigger_pkt_any_1_match_pkt),
|
|
.io_trigger_pkt_any_1_execute(dec_trigger_io_trigger_pkt_any_1_execute),
|
|
.io_trigger_pkt_any_1_m(dec_trigger_io_trigger_pkt_any_1_m),
|
|
.io_trigger_pkt_any_1_tdata2(dec_trigger_io_trigger_pkt_any_1_tdata2),
|
|
.io_trigger_pkt_any_2_select(dec_trigger_io_trigger_pkt_any_2_select),
|
|
.io_trigger_pkt_any_2_match_pkt(dec_trigger_io_trigger_pkt_any_2_match_pkt),
|
|
.io_trigger_pkt_any_2_execute(dec_trigger_io_trigger_pkt_any_2_execute),
|
|
.io_trigger_pkt_any_2_m(dec_trigger_io_trigger_pkt_any_2_m),
|
|
.io_trigger_pkt_any_2_tdata2(dec_trigger_io_trigger_pkt_any_2_tdata2),
|
|
.io_trigger_pkt_any_3_select(dec_trigger_io_trigger_pkt_any_3_select),
|
|
.io_trigger_pkt_any_3_match_pkt(dec_trigger_io_trigger_pkt_any_3_match_pkt),
|
|
.io_trigger_pkt_any_3_execute(dec_trigger_io_trigger_pkt_any_3_execute),
|
|
.io_trigger_pkt_any_3_m(dec_trigger_io_trigger_pkt_any_3_m),
|
|
.io_trigger_pkt_any_3_tdata2(dec_trigger_io_trigger_pkt_any_3_tdata2),
|
|
.io_dec_i0_pc_d(dec_trigger_io_dec_i0_pc_d),
|
|
.io_dec_i0_trigger_match_d(dec_trigger_io_dec_i0_trigger_match_d)
|
|
);
|
|
assign io_dec_extint_stall = decode_io_dec_extint_stall; // @[el2_dec.scala 389:40]
|
|
assign io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 397:40]
|
|
assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[el2_dec.scala 418:40]
|
|
assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[el2_dec.scala 548:29]
|
|
assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 549:29]
|
|
assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[el2_dec.scala 550:29]
|
|
assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[el2_dec.scala 551:29]
|
|
assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 552:29]
|
|
assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 553:29]
|
|
assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[el2_dec.scala 554:29]
|
|
assign io_dec_tlu_meicurpl = tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 555:29]
|
|
assign io_dec_tlu_meipt = tlu_io_dec_tlu_meipt; // @[el2_dec.scala 556:29]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 547:29]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 547:29]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 547:29]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 547:29]
|
|
assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 538:28]
|
|
assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 539:28]
|
|
assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 540:28]
|
|
assign io_dec_tlu_flush_noredir_r = tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 541:34]
|
|
assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 542:34]
|
|
assign io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 543:34]
|
|
assign io_dec_tlu_flush_err_r = tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 544:34]
|
|
assign io_dec_tlu_meihap = tlu_io_dec_tlu_meihap; // @[el2_dec.scala 545:29]
|
|
assign io_dec_debug_wdata_rs1_d = instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 314:38]
|
|
assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 600:21]
|
|
assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 536:28]
|
|
assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 537:28]
|
|
assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 546:29]
|
|
assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 546:29]
|
|
assign io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 564:29]
|
|
assign io_dec_i0_rs1_en_d = decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 392:40]
|
|
assign io_dec_i0_rs2_en_d = decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 393:40]
|
|
assign io_gpr_i0_rs1_d = gpr_io_rd0; // @[el2_dec.scala 440:19]
|
|
assign io_gpr_i0_rs2_d = gpr_io_rd1; // @[el2_dec.scala 441:19]
|
|
assign io_dec_i0_immed_d = decode_io_dec_i0_immed_d; // @[el2_dec.scala 394:40]
|
|
assign io_dec_i0_br_immed_d = decode_io_dec_i0_br_immed_d; // @[el2_dec.scala 395:40]
|
|
assign io_i0_ap_land = decode_io_i0_ap_land; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_lor = decode_io_i0_ap_lor; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_lxor = decode_io_i0_ap_lxor; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_sll = decode_io_i0_ap_sll; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_srl = decode_io_i0_ap_srl; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_sra = decode_io_i0_ap_sra; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_beq = decode_io_i0_ap_beq; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_bne = decode_io_i0_ap_bne; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_blt = decode_io_i0_ap_blt; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_bge = decode_io_i0_ap_bge; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_add = decode_io_i0_ap_add; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_sub = decode_io_i0_ap_sub; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_slt = decode_io_i0_ap_slt; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_unsign = decode_io_i0_ap_unsign; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_jal = decode_io_i0_ap_jal; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_predict_t = decode_io_i0_ap_predict_t; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_predict_nt = decode_io_i0_ap_predict_nt; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_csr_write = decode_io_i0_ap_csr_write; // @[el2_dec.scala 396:40]
|
|
assign io_i0_ap_csr_imm = decode_io_i0_ap_csr_imm; // @[el2_dec.scala 396:40]
|
|
assign io_dec_i0_alu_decode_d = decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 398:40]
|
|
assign io_dec_i0_select_pc_d = decode_io_dec_i0_select_pc_d; // @[el2_dec.scala 401:40]
|
|
assign io_dec_i0_pc_d = instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 291:18]
|
|
assign io_dec_i0_rs1_bypass_en_d = decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 402:40]
|
|
assign io_dec_i0_rs2_bypass_en_d = decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 403:40]
|
|
assign io_dec_i0_rs1_bypass_data_d = decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 399:40]
|
|
assign io_dec_i0_rs2_bypass_data_d = decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 400:40]
|
|
assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[el2_dec.scala 404:40]
|
|
assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[el2_dec.scala 404:40]
|
|
assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[el2_dec.scala 404:40]
|
|
assign io_lsu_p_bits_half = decode_io_lsu_p_bits_half; // @[el2_dec.scala 404:40]
|
|
assign io_lsu_p_bits_word = decode_io_lsu_p_bits_word; // @[el2_dec.scala 404:40]
|
|
assign io_lsu_p_bits_load = decode_io_lsu_p_bits_load; // @[el2_dec.scala 404:40]
|
|
assign io_lsu_p_bits_store = decode_io_lsu_p_bits_store; // @[el2_dec.scala 404:40]
|
|
assign io_lsu_p_bits_unsign = decode_io_lsu_p_bits_unsign; // @[el2_dec.scala 404:40]
|
|
assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[el2_dec.scala 404:40]
|
|
assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_dec.scala 404:40]
|
|
assign io_mul_p_valid = decode_io_mul_p_valid; // @[el2_dec.scala 405:40]
|
|
assign io_mul_p_bits_rs1_sign = decode_io_mul_p_bits_rs1_sign; // @[el2_dec.scala 405:40]
|
|
assign io_mul_p_bits_rs2_sign = decode_io_mul_p_bits_rs2_sign; // @[el2_dec.scala 405:40]
|
|
assign io_mul_p_bits_low = decode_io_mul_p_bits_low; // @[el2_dec.scala 405:40]
|
|
assign io_div_p_valid = decode_io_div_p_valid; // @[el2_dec.scala 406:40]
|
|
assign io_div_p_bits_unsign = decode_io_div_p_bits_unsign; // @[el2_dec.scala 406:40]
|
|
assign io_div_p_bits_rem = decode_io_div_p_bits_rem; // @[el2_dec.scala 406:40]
|
|
assign io_dec_div_cancel = decode_io_dec_div_cancel; // @[el2_dec.scala 407:40]
|
|
assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[el2_dec.scala 409:40]
|
|
assign io_dec_csr_ren_d = decode_io_dec_csr_ren_d; // @[el2_dec.scala 410:40]
|
|
assign io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 560:34]
|
|
assign io_dec_tlu_flush_path_r = tlu_io_dec_tlu_flush_path_r; // @[el2_dec.scala 561:34]
|
|
assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 559:34]
|
|
assign io_dec_tlu_fence_i_r = tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 562:34]
|
|
assign io_pred_correct_npc_x = decode_io_pred_correct_npc_x; // @[el2_dec.scala 411:40]
|
|
assign io_dec_tlu_br0_r_pkt_valid = tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 557:42]
|
|
assign io_dec_tlu_br0_r_pkt_hist = tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 557:42]
|
|
assign io_dec_tlu_br0_r_pkt_br_error = tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 557:42]
|
|
assign io_dec_tlu_br0_r_pkt_br_start_error = tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 557:42]
|
|
assign io_dec_tlu_br0_r_pkt_way = tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 557:42]
|
|
assign io_dec_tlu_br0_r_pkt_middle = tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 557:42]
|
|
assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 565:29]
|
|
assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 566:29]
|
|
assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 567:29]
|
|
assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 568:29]
|
|
assign io_dec_i0_predict_p_d_valid = decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 412:40]
|
|
assign io_dec_i0_predict_p_d_bits_pc4 = decode_io_dec_i0_predict_p_d_bits_pc4; // @[el2_dec.scala 412:40]
|
|
assign io_dec_i0_predict_p_d_bits_hist = decode_io_dec_i0_predict_p_d_bits_hist; // @[el2_dec.scala 412:40]
|
|
assign io_dec_i0_predict_p_d_bits_toffset = decode_io_dec_i0_predict_p_d_bits_toffset; // @[el2_dec.scala 412:40]
|
|
assign io_dec_i0_predict_p_d_bits_br_error = decode_io_dec_i0_predict_p_d_bits_br_error; // @[el2_dec.scala 412:40]
|
|
assign io_dec_i0_predict_p_d_bits_br_start_error = decode_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_dec.scala 412:40]
|
|
assign io_dec_i0_predict_p_d_bits_prett = decode_io_dec_i0_predict_p_d_bits_prett; // @[el2_dec.scala 412:40]
|
|
assign io_dec_i0_predict_p_d_bits_pcall = decode_io_dec_i0_predict_p_d_bits_pcall; // @[el2_dec.scala 412:40]
|
|
assign io_dec_i0_predict_p_d_bits_pret = decode_io_dec_i0_predict_p_d_bits_pret; // @[el2_dec.scala 412:40]
|
|
assign io_dec_i0_predict_p_d_bits_pja = decode_io_dec_i0_predict_p_d_bits_pja; // @[el2_dec.scala 412:40]
|
|
assign io_dec_i0_predict_p_d_bits_way = decode_io_dec_i0_predict_p_d_bits_way; // @[el2_dec.scala 412:40]
|
|
assign io_i0_predict_fghr_d = decode_io_i0_predict_fghr_d; // @[el2_dec.scala 413:40]
|
|
assign io_i0_predict_index_d = decode_io_i0_predict_index_d; // @[el2_dec.scala 414:40]
|
|
assign io_i0_predict_btag_d = decode_io_i0_predict_btag_d; // @[el2_dec.scala 415:40]
|
|
assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 408:40]
|
|
assign io_dec_tlu_mrac_ff = tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 563:29]
|
|
assign io_dec_data_en = decode_io_dec_data_en; // @[el2_dec.scala 416:40]
|
|
assign io_dec_ctl_en = decode_io_dec_ctl_en; // @[el2_dec.scala 417:40]
|
|
assign io_rv_trace_pkt_rv_i_valid_ip = {tlu_io_dec_tlu_int_valid_wb1,_T_1}; // @[el2_dec.scala 592:33]
|
|
assign io_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb1; // @[el2_dec.scala 590:32]
|
|
assign io_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb1,1'h0}; // @[el2_dec.scala 591:35]
|
|
assign io_rv_trace_pkt_rv_i_exception_ip = {tlu_io_dec_tlu_int_valid_wb1,tlu_io_dec_tlu_i0_exc_valid_wb1}; // @[el2_dec.scala 593:37]
|
|
assign io_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[el2_dec.scala 594:34]
|
|
assign io_rv_trace_pkt_rv_i_interrupt_ip = {tlu_io_dec_tlu_int_valid_wb1,1'h0}; // @[el2_dec.scala 595:37]
|
|
assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[el2_dec.scala 596:32]
|
|
assign io_dec_tlu_external_ldfwd_disable = tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 574:43]
|
|
assign io_dec_tlu_sideeffect_posted_disable = tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 575:43]
|
|
assign io_dec_tlu_core_ecc_disable = tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 576:43]
|
|
assign io_dec_tlu_bpred_disable = tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 577:43]
|
|
assign io_dec_tlu_wb_coalescing_disable = tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 578:43]
|
|
assign io_dec_tlu_dma_qos_prty = tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 579:35]
|
|
assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 580:35]
|
|
assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 582:36]
|
|
assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 584:36]
|
|
assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 585:36]
|
|
assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 586:36]
|
|
assign io_dec_tlu_i0_commit_cmt = tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 558:34]
|
|
assign instbuff_io_dbg_cmd_valid = io_dbg_cmd_valid; // @[el2_dec.scala 297:45]
|
|
assign instbuff_io_dbg_cmd_write = io_dbg_cmd_write; // @[el2_dec.scala 298:45]
|
|
assign instbuff_io_dbg_cmd_type = io_dbg_cmd_type; // @[el2_dec.scala 299:45]
|
|
assign instbuff_io_dbg_cmd_addr = io_dbg_cmd_addr; // @[el2_dec.scala 300:45]
|
|
assign instbuff_io_i0_brp_valid = io_i0_brp_valid; // @[el2_dec.scala 301:55]
|
|
assign instbuff_io_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec.scala 301:55]
|
|
assign instbuff_io_i0_brp_hist = io_i0_brp_hist; // @[el2_dec.scala 301:55]
|
|
assign instbuff_io_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec.scala 301:55]
|
|
assign instbuff_io_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec.scala 301:55]
|
|
assign instbuff_io_i0_brp_prett = io_i0_brp_prett; // @[el2_dec.scala 301:55]
|
|
assign instbuff_io_i0_brp_way = io_i0_brp_way; // @[el2_dec.scala 301:55]
|
|
assign instbuff_io_i0_brp_ret = io_i0_brp_ret; // @[el2_dec.scala 301:55]
|
|
assign instbuff_io_ifu_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec.scala 302:35]
|
|
assign instbuff_io_ifu_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec.scala 303:35]
|
|
assign instbuff_io_ifu_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec.scala 304:35]
|
|
assign instbuff_io_ifu_i0_pc4 = io_ifu_i0_pc4; // @[el2_dec.scala 305:35]
|
|
assign instbuff_io_ifu_i0_valid = io_ifu_i0_valid; // @[el2_dec.scala 306:35]
|
|
assign instbuff_io_ifu_i0_icaf = io_ifu_i0_icaf; // @[el2_dec.scala 307:35]
|
|
assign instbuff_io_ifu_i0_icaf_type = io_ifu_i0_icaf_type; // @[el2_dec.scala 308:35]
|
|
assign instbuff_io_ifu_i0_icaf_f1 = io_ifu_i0_icaf_f1; // @[el2_dec.scala 309:35]
|
|
assign instbuff_io_ifu_i0_dbecc = io_ifu_i0_dbecc; // @[el2_dec.scala 310:35]
|
|
assign instbuff_io_ifu_i0_instr = io_ifu_i0_instr; // @[el2_dec.scala 311:35]
|
|
assign instbuff_io_ifu_i0_pc = io_ifu_i0_pc; // @[el2_dec.scala 312:35]
|
|
assign decode_clock = clock;
|
|
assign decode_reset = reset;
|
|
assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 330:48]
|
|
assign decode_io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 331:48]
|
|
assign decode_io_ifu_i0_cinst = io_ifu_i0_cinst; // @[el2_dec.scala 332:48]
|
|
assign decode_io_lsu_nonblock_load_valid_m = io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 333:48]
|
|
assign decode_io_lsu_nonblock_load_tag_m = io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 334:48]
|
|
assign decode_io_lsu_nonblock_load_inv_r = io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 335:48]
|
|
assign decode_io_lsu_nonblock_load_inv_tag_r = io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 336:48]
|
|
assign decode_io_lsu_nonblock_load_data_valid = io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 337:48]
|
|
assign decode_io_lsu_nonblock_load_data_error = io_lsu_nonblock_load_data_error; // @[el2_dec.scala 338:48]
|
|
assign decode_io_lsu_nonblock_load_data_tag = io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 339:48]
|
|
assign decode_io_lsu_nonblock_load_data = io_lsu_nonblock_load_data; // @[el2_dec.scala 340:48]
|
|
assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 341:48]
|
|
assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 342:48]
|
|
assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 343:48]
|
|
assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[el2_dec.scala 344:48]
|
|
assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 345:48]
|
|
assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 346:48]
|
|
assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 347:48]
|
|
assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 348:48]
|
|
assign decode_io_dbg_cmd_wrdata = io_dbg_cmd_wrdata; // @[el2_dec.scala 349:48]
|
|
assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 350:48]
|
|
assign decode_io_dec_i0_icaf_f1_d = instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 351:48]
|
|
assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 352:48]
|
|
assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 353:48]
|
|
assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 354:48]
|
|
assign decode_io_dec_i0_brp_toffset = instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 354:48]
|
|
assign decode_io_dec_i0_brp_hist = instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 354:48]
|
|
assign decode_io_dec_i0_brp_br_error = instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 354:48]
|
|
assign decode_io_dec_i0_brp_br_start_error = instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 354:48]
|
|
assign decode_io_dec_i0_brp_prett = instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 354:48]
|
|
assign decode_io_dec_i0_brp_way = instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 354:48]
|
|
assign decode_io_dec_i0_brp_ret = instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 354:48]
|
|
assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 355:48]
|
|
assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 356:48]
|
|
assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 357:48]
|
|
assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 359:48]
|
|
assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[el2_dec.scala 360:48]
|
|
assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 361:48]
|
|
assign decode_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 362:48]
|
|
assign decode_io_exu_div_wren = io_exu_div_wren; // @[el2_dec.scala 363:48]
|
|
assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 364:48]
|
|
assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 365:48]
|
|
assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 366:48]
|
|
assign decode_io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 367:48]
|
|
assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 368:48]
|
|
assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 369:48]
|
|
assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 370:48]
|
|
assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc4_d; // @[el2_dec.scala 371:48]
|
|
assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 372:48]
|
|
assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[el2_dec.scala 373:48]
|
|
assign decode_io_exu_csr_rs1_x = io_exu_csr_rs1_x; // @[el2_dec.scala 374:48]
|
|
assign decode_io_lsu_result_m = io_lsu_result_m; // @[el2_dec.scala 375:48]
|
|
assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[el2_dec.scala 376:48]
|
|
assign decode_io_exu_flush_final = io_exu_flush_final; // @[el2_dec.scala 377:48]
|
|
assign decode_io_exu_i0_pc_x = io_exu_i0_pc_x; // @[el2_dec.scala 378:48]
|
|
assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 379:48]
|
|
assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 380:48]
|
|
assign decode_io_exu_i0_result_x = io_exu_i0_result_x; // @[el2_dec.scala 381:48]
|
|
assign decode_io_free_clk = io_free_clk; // @[el2_dec.scala 383:48]
|
|
assign decode_io_active_clk = io_active_clk; // @[el2_dec.scala 384:48]
|
|
assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 385:48]
|
|
assign decode_io_scan_mode = io_scan_mode; // @[el2_dec.scala 387:48]
|
|
assign gpr_clock = clock;
|
|
assign gpr_reset = reset;
|
|
assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[el2_dec.scala 425:23]
|
|
assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[el2_dec.scala 426:23]
|
|
assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[el2_dec.scala 427:23]
|
|
assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[el2_dec.scala 428:23]
|
|
assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 429:23]
|
|
assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 430:23]
|
|
assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 431:23]
|
|
assign gpr_io_wd1 = io_lsu_nonblock_load_data; // @[el2_dec.scala 432:23]
|
|
assign gpr_io_wen2 = io_exu_div_wren; // @[el2_dec.scala 433:23]
|
|
assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[el2_dec.scala 434:23]
|
|
assign gpr_io_wd2 = io_exu_div_result; // @[el2_dec.scala 435:23]
|
|
assign gpr_io_scan_mode = io_scan_mode; // @[el2_dec.scala 438:23]
|
|
assign tlu_clock = clock;
|
|
assign tlu_reset = reset;
|
|
assign tlu_io_active_clk = io_active_clk; // @[el2_dec.scala 450:45]
|
|
assign tlu_io_free_clk = io_free_clk; // @[el2_dec.scala 451:45]
|
|
assign tlu_io_scan_mode = io_scan_mode; // @[el2_dec.scala 453:45]
|
|
assign tlu_io_rst_vec = io_rst_vec; // @[el2_dec.scala 454:45]
|
|
assign tlu_io_nmi_int = io_nmi_int; // @[el2_dec.scala 455:45]
|
|
assign tlu_io_nmi_vec = io_nmi_vec; // @[el2_dec.scala 456:45]
|
|
assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_dec.scala 457:45]
|
|
assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_dec.scala 458:45]
|
|
assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[el2_dec.scala 459:45]
|
|
assign tlu_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[el2_dec.scala 460:45]
|
|
assign tlu_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[el2_dec.scala 461:45]
|
|
assign tlu_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[el2_dec.scala 462:45]
|
|
assign tlu_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[el2_dec.scala 463:45]
|
|
assign tlu_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[el2_dec.scala 464:45]
|
|
assign tlu_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec.scala 465:45]
|
|
assign tlu_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[el2_dec.scala 466:45]
|
|
assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 467:45]
|
|
assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 468:45]
|
|
assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 469:45]
|
|
assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 470:45]
|
|
assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 471:45]
|
|
assign tlu_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 472:45]
|
|
assign tlu_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[el2_dec.scala 473:45]
|
|
assign tlu_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[el2_dec.scala 474:45]
|
|
assign tlu_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 475:45]
|
|
assign tlu_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[el2_dec.scala 476:45]
|
|
assign tlu_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[el2_dec.scala 477:45]
|
|
assign tlu_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 478:45]
|
|
assign tlu_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[el2_dec.scala 479:45]
|
|
assign tlu_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec.scala 480:45]
|
|
assign tlu_io_lsu_pmu_load_external_m = io_lsu_pmu_load_external_m; // @[el2_dec.scala 481:45]
|
|
assign tlu_io_lsu_pmu_store_external_m = io_lsu_pmu_store_external_m; // @[el2_dec.scala 482:45]
|
|
assign tlu_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[el2_dec.scala 483:45]
|
|
assign tlu_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[el2_dec.scala 484:45]
|
|
assign tlu_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec.scala 485:45]
|
|
assign tlu_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec.scala 486:45]
|
|
assign tlu_io_lsu_fir_addr = io_lsu_fir_addr; // @[el2_dec.scala 487:45]
|
|
assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[el2_dec.scala 488:45]
|
|
assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[el2_dec.scala 489:45]
|
|
assign tlu_io_lsu_error_pkt_r_valid = io_lsu_error_pkt_r_valid; // @[el2_dec.scala 490:45]
|
|
assign tlu_io_lsu_error_pkt_r_bits_single_ecc_error = io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 490:45]
|
|
assign tlu_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 490:45]
|
|
assign tlu_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 490:45]
|
|
assign tlu_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 490:45]
|
|
assign tlu_io_lsu_error_pkt_r_bits_addr = io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 490:45]
|
|
assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[el2_dec.scala 491:45]
|
|
assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[el2_dec.scala 492:45]
|
|
assign tlu_io_lsu_imprecise_error_store_any = io_lsu_imprecise_error_store_any; // @[el2_dec.scala 493:45]
|
|
assign tlu_io_lsu_imprecise_error_load_any = io_lsu_imprecise_error_load_any; // @[el2_dec.scala 494:45]
|
|
assign tlu_io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 495:45]
|
|
assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 496:45]
|
|
assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 497:45]
|
|
assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 498:45]
|
|
assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[el2_dec.scala 499:45]
|
|
assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 500:45]
|
|
assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 501:45]
|
|
assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 502:45]
|
|
assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 503:45]
|
|
assign tlu_io_exu_npc_r = io_exu_npc_r; // @[el2_dec.scala 504:45]
|
|
assign tlu_io_dec_tlu_i0_pc_r = decode_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 505:45]
|
|
assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 506:45]
|
|
assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 506:45]
|
|
assign tlu_io_dec_tlu_packet_r_icaf_f1 = decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 506:45]
|
|
assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 506:45]
|
|
assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 506:45]
|
|
assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 506:45]
|
|
assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 506:45]
|
|
assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 506:45]
|
|
assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 506:45]
|
|
assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 506:45]
|
|
assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[el2_dec.scala 507:45]
|
|
assign tlu_io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 508:45]
|
|
assign tlu_io_exu_i0_br_hist_r = io_exu_i0_br_hist_r; // @[el2_dec.scala 509:45]
|
|
assign tlu_io_exu_i0_br_error_r = io_exu_i0_br_error_r; // @[el2_dec.scala 510:45]
|
|
assign tlu_io_exu_i0_br_start_error_r = io_exu_i0_br_start_error_r; // @[el2_dec.scala 511:45]
|
|
assign tlu_io_exu_i0_br_valid_r = io_exu_i0_br_valid_r; // @[el2_dec.scala 512:45]
|
|
assign tlu_io_exu_i0_br_mp_r = io_exu_i0_br_mp_r; // @[el2_dec.scala 513:45]
|
|
assign tlu_io_exu_i0_br_middle_r = io_exu_i0_br_middle_r; // @[el2_dec.scala 514:45]
|
|
assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[el2_dec.scala 515:45]
|
|
assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[el2_dec.scala 516:45]
|
|
assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[el2_dec.scala 517:45]
|
|
assign tlu_io_ifu_miss_state_idle = io_ifu_miss_state_idle; // @[el2_dec.scala 518:45]
|
|
assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 519:45]
|
|
assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[el2_dec.scala 520:45]
|
|
assign tlu_io_ifu_ic_error_start = io_ifu_ic_error_start; // @[el2_dec.scala 521:45]
|
|
assign tlu_io_ifu_iccm_rd_ecc_single_err = io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 522:45]
|
|
assign tlu_io_ifu_ic_debug_rd_data = io_ifu_ic_debug_rd_data; // @[el2_dec.scala 523:45]
|
|
assign tlu_io_ifu_ic_debug_rd_data_valid = io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 524:45]
|
|
assign tlu_io_pic_claimid = io_pic_claimid; // @[el2_dec.scala 525:45]
|
|
assign tlu_io_pic_pl = io_pic_pl; // @[el2_dec.scala 526:45]
|
|
assign tlu_io_mhwakeup = io_mhwakeup; // @[el2_dec.scala 527:45]
|
|
assign tlu_io_mexintpend = io_mexintpend; // @[el2_dec.scala 528:45]
|
|
assign tlu_io_timer_int = io_timer_int; // @[el2_dec.scala 529:45]
|
|
assign tlu_io_soft_int = io_soft_int; // @[el2_dec.scala 530:45]
|
|
assign tlu_io_core_id = io_core_id; // @[el2_dec.scala 531:45]
|
|
assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_dec.scala 532:45]
|
|
assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_dec.scala 533:45]
|
|
assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec.scala 534:45]
|
|
assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 321:34]
|
|
assign dec_trigger_io_dec_i0_pc_d = instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 320:30]
|
|
endmodule
|
|
module rvclkhdr_757(
|
|
output io_l1clk,
|
|
input io_clk,
|
|
input io_en,
|
|
input io_scan_mode
|
|
);
|
|
wire clkhdr_Q; // @[el2_lib.scala 474:26]
|
|
wire clkhdr_CK; // @[el2_lib.scala 474:26]
|
|
wire clkhdr_EN; // @[el2_lib.scala 474:26]
|
|
wire clkhdr_SE; // @[el2_lib.scala 474:26]
|
|
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
|
|
.Q(clkhdr_Q),
|
|
.CK(clkhdr_CK),
|
|
.EN(clkhdr_EN),
|
|
.SE(clkhdr_SE)
|
|
);
|
|
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
|
|
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
|
|
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
|
|
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
|
|
endmodule
|
|
module el2_dbg(
|
|
input clock,
|
|
input reset,
|
|
output [31:0] io_dbg_cmd_addr,
|
|
output [31:0] io_dbg_cmd_wrdata,
|
|
output io_dbg_cmd_valid,
|
|
output io_dbg_cmd_write,
|
|
output [1:0] io_dbg_cmd_type,
|
|
output [1:0] io_dbg_cmd_size,
|
|
output io_dbg_core_rst_l,
|
|
input [31:0] io_core_dbg_rddata,
|
|
input io_core_dbg_cmd_done,
|
|
input io_core_dbg_cmd_fail,
|
|
output io_dbg_dma_bubble,
|
|
input io_dma_dbg_ready,
|
|
output io_dbg_halt_req,
|
|
output io_dbg_resume_req,
|
|
input io_dec_tlu_debug_mode,
|
|
input io_dec_tlu_dbg_halted,
|
|
input io_dec_tlu_mpc_halted_only,
|
|
input io_dec_tlu_resume_ack,
|
|
input io_dmi_reg_en,
|
|
input [6:0] io_dmi_reg_addr,
|
|
input io_dmi_reg_wr_en,
|
|
input [31:0] io_dmi_reg_wdata,
|
|
output io_sb_axi_awvalid,
|
|
input io_sb_axi_awready,
|
|
output [31:0] io_sb_axi_awaddr,
|
|
output [3:0] io_sb_axi_awregion,
|
|
output [2:0] io_sb_axi_awsize,
|
|
output io_sb_axi_wvalid,
|
|
input io_sb_axi_wready,
|
|
output [63:0] io_sb_axi_wdata,
|
|
output [7:0] io_sb_axi_wstrb,
|
|
input io_sb_axi_bvalid,
|
|
output io_sb_axi_bready,
|
|
input [1:0] io_sb_axi_bresp,
|
|
output io_sb_axi_arvalid,
|
|
input io_sb_axi_arready,
|
|
output [31:0] io_sb_axi_araddr,
|
|
output [3:0] io_sb_axi_arregion,
|
|
output [2:0] io_sb_axi_arsize,
|
|
input io_sb_axi_rvalid,
|
|
output io_sb_axi_rready,
|
|
input [63:0] io_sb_axi_rdata,
|
|
input [1:0] io_sb_axi_rresp,
|
|
input io_dbg_bus_clk_en,
|
|
input io_dbg_rst_l,
|
|
input io_clk_override,
|
|
input io_scan_mode
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
reg [2:0] dbg_state; // @[Reg.scala 27:20]
|
|
wire _T = dbg_state != 3'h0; // @[el2_dbg.scala 126:51]
|
|
wire _T_1 = io_dmi_reg_en | _T; // @[el2_dbg.scala 126:38]
|
|
wire _T_309 = 3'h0 == dbg_state; // @[Conditional.scala 37:30]
|
|
reg [3:0] dm_temp; // @[Reg.scala 27:20]
|
|
reg dm_temp_0; // @[Reg.scala 27:20]
|
|
wire [31:0] temp = {dm_temp[3:2],1'h0,dm_temp[1],26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58]
|
|
wire _T_314 = ~io_dec_tlu_debug_mode; // @[el2_dbg.scala 297:45]
|
|
wire _T_315 = temp[31] & _T_314; // @[el2_dbg.scala 297:43]
|
|
reg dmstatus_havereset; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_150 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
reg dmstatus_resumeack; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_152 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_183 = ~reset; // @[el2_dbg.scala 222:43]
|
|
wire dmstatus_unavail = temp[1] | _T_183; // @[el2_dbg.scala 222:41]
|
|
wire [1:0] _T_154 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
reg dmstatus_halted; // @[el2_dbg.scala 229:12]
|
|
wire _T_186 = dmstatus_unavail | dmstatus_halted; // @[el2_dbg.scala 223:42]
|
|
wire dmstatus_running = ~_T_186; // @[el2_dbg.scala 223:23]
|
|
wire [1:0] _T_156 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_158 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] dmstatus_reg = {12'h0,_T_150,_T_152,2'h0,_T_154,_T_156,_T_158,1'h1,7'h2}; // @[Cat.scala 29:58]
|
|
wire _T_317 = _T_315 | dmstatus_reg[9]; // @[el2_dbg.scala 297:69]
|
|
wire _T_318 = _T_317 | io_dec_tlu_mpc_halted_only; // @[el2_dbg.scala 297:87]
|
|
wire _T_320 = ~temp[1]; // @[el2_dbg.scala 297:119]
|
|
wire _T_321 = _T_318 & _T_320; // @[el2_dbg.scala 297:117]
|
|
wire _T_327 = 3'h1 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_332 = dmstatus_reg[9] | temp[1]; // @[el2_dbg.scala 302:39]
|
|
wire _T_339 = 3'h2 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_354 = dmstatus_reg[9] & temp[30]; // @[el2_dbg.scala 309:39]
|
|
wire _T_356 = ~temp[31]; // @[el2_dbg.scala 309:61]
|
|
wire _T_357 = _T_354 & _T_356; // @[el2_dbg.scala 309:59]
|
|
reg dmcontrol_wren_Q; // @[el2_dbg.scala 212:12]
|
|
wire _T_358 = _T_357 & dmcontrol_wren_Q; // @[el2_dbg.scala 309:80]
|
|
wire _T_275 = io_dmi_reg_addr == 7'h17; // @[el2_dbg.scala 266:39]
|
|
wire _T_276 = _T_275 & io_dmi_reg_en; // @[el2_dbg.scala 266:52]
|
|
wire _T_277 = _T_276 & io_dmi_reg_wr_en; // @[el2_dbg.scala 266:68]
|
|
wire _T_278 = dbg_state == 3'h2; // @[el2_dbg.scala 266:100]
|
|
wire command_wren = _T_277 & _T_278; // @[el2_dbg.scala 266:87]
|
|
wire _T_359 = _T_358 | command_wren; // @[el2_dbg.scala 309:99]
|
|
wire _T_361 = _T_359 | temp[1]; // @[el2_dbg.scala 309:114]
|
|
wire _T_363 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[el2_dbg.scala 310:46]
|
|
wire _T_364 = ~_T_363; // @[el2_dbg.scala 310:28]
|
|
wire _T_365 = _T_361 | _T_364; // @[el2_dbg.scala 310:26]
|
|
wire _T_377 = 3'h3 == dbg_state; // @[Conditional.scala 37:30]
|
|
reg abs_temp_12; // @[Reg.scala 27:20]
|
|
reg [2:0] abs_temp_10_8; // @[el2_dbg.scala 261:12]
|
|
wire [31:0] abstractcs_reg = {19'h0,abs_temp_12,1'h0,abs_temp_10_8,8'h2}; // @[Cat.scala 29:58]
|
|
wire _T_384 = |abstractcs_reg[10:8]; // @[el2_dbg.scala 318:64]
|
|
wire _T_385 = io_dbg_cmd_valid | _T_384; // @[el2_dbg.scala 318:40]
|
|
wire _T_387 = _T_385 | temp[1]; // @[el2_dbg.scala 318:68]
|
|
wire _T_394 = 3'h4 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_398 = io_core_dbg_cmd_done | temp[1]; // @[el2_dbg.scala 323:44]
|
|
wire _T_405 = 3'h5 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_414 = 3'h6 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_417 = dmstatus_reg[17] | temp[1]; // @[el2_dbg.scala 335:40]
|
|
wire _GEN_13 = _T_414 & _T_417; // @[Conditional.scala 39:67]
|
|
wire _GEN_16 = _T_405 | _GEN_13; // @[Conditional.scala 39:67]
|
|
wire _GEN_21 = _T_394 ? _T_398 : _GEN_16; // @[Conditional.scala 39:67]
|
|
wire _GEN_26 = _T_377 ? _T_387 : _GEN_21; // @[Conditional.scala 39:67]
|
|
wire _GEN_31 = _T_339 ? _T_365 : _GEN_26; // @[Conditional.scala 39:67]
|
|
wire _GEN_37 = _T_327 ? _T_332 : _GEN_31; // @[Conditional.scala 39:67]
|
|
wire dbg_state_en = _T_309 ? _T_321 : _GEN_37; // @[Conditional.scala 40:58]
|
|
wire _T_2 = _T_1 | dbg_state_en; // @[el2_dbg.scala 126:69]
|
|
wire _T_3 = _T_2 | io_dec_tlu_dbg_halted; // @[el2_dbg.scala 126:84]
|
|
reg [3:0] sb_state; // @[Reg.scala 27:20]
|
|
wire sbcs_sbbusy_din = 4'h0 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_130 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[el2_dbg.scala 196:40]
|
|
wire _T_131 = io_dmi_reg_addr == 7'h3c; // @[el2_dbg.scala 196:78]
|
|
wire sbdata0wr_access = _T_130 & _T_131; // @[el2_dbg.scala 196:59]
|
|
wire _T_125 = ~io_dmi_reg_wr_en; // @[el2_dbg.scala 195:45]
|
|
wire _T_126 = io_dmi_reg_en & _T_125; // @[el2_dbg.scala 195:43]
|
|
wire _T_128 = _T_126 & _T_131; // @[el2_dbg.scala 195:63]
|
|
reg temp_sbcs_22; // @[Reg.scala 27:20]
|
|
reg temp_sbcs_21; // @[Reg.scala 27:20]
|
|
reg temp_sbcs_20; // @[Reg.scala 27:20]
|
|
reg [4:0] temp_sbcs_19_15; // @[Reg.scala 27:20]
|
|
reg [2:0] temp_sbcs_14_12; // @[Reg.scala 27:20]
|
|
wire [31:0] sbcs_reg = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20,temp_sbcs_19_15,temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58]
|
|
wire sbreadondata_access = _T_128 & sbcs_reg[15]; // @[el2_dbg.scala 195:95]
|
|
wire _T_516 = sbdata0wr_access | sbreadondata_access; // @[el2_dbg.scala 374:39]
|
|
wire _T_122 = io_dmi_reg_addr == 7'h39; // @[el2_dbg.scala 194:81]
|
|
wire _T_123 = _T_130 & _T_122; // @[el2_dbg.scala 194:62]
|
|
wire sbreadonaddr_access = _T_123 & sbcs_reg[20]; // @[el2_dbg.scala 194:94]
|
|
wire _T_517 = _T_516 | sbreadonaddr_access; // @[el2_dbg.scala 374:61]
|
|
wire _T_525 = 4'h1 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_46 = sbcs_reg[19:17] == 3'h1; // @[el2_dbg.scala 158:42]
|
|
reg [31:0] sbaddress0_reg; // @[el2_lib.scala 514:16]
|
|
wire _T_48 = _T_46 & sbaddress0_reg[0]; // @[el2_dbg.scala 158:56]
|
|
wire _T_50 = sbcs_reg[19:17] == 3'h2; // @[el2_dbg.scala 159:23]
|
|
wire _T_52 = |sbaddress0_reg[1:0]; // @[el2_dbg.scala 159:60]
|
|
wire _T_53 = _T_50 & _T_52; // @[el2_dbg.scala 159:37]
|
|
wire _T_54 = _T_48 | _T_53; // @[el2_dbg.scala 158:76]
|
|
wire _T_56 = sbcs_reg[19:17] == 3'h3; // @[el2_dbg.scala 160:23]
|
|
wire _T_58 = |sbaddress0_reg[2:0]; // @[el2_dbg.scala 160:60]
|
|
wire _T_59 = _T_56 & _T_58; // @[el2_dbg.scala 160:37]
|
|
wire sbcs_unaligned = _T_54 | _T_59; // @[el2_dbg.scala 159:64]
|
|
wire _T_528 = io_dbg_bus_clk_en | sbcs_unaligned; // @[el2_dbg.scala 382:40]
|
|
wire sbcs_illegal_size = sbcs_reg[19]; // @[el2_dbg.scala 162:35]
|
|
wire _T_529 = _T_528 | sbcs_illegal_size; // @[el2_dbg.scala 382:57]
|
|
wire _T_532 = 4'h2 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_539 = 4'h3 == sb_state; // @[Conditional.scala 37:30]
|
|
wire sb_bus_cmd_read = io_sb_axi_arvalid & io_sb_axi_arready; // @[el2_dbg.scala 432:40]
|
|
wire _T_540 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[el2_dbg.scala 394:38]
|
|
wire _T_541 = 4'h4 == sb_state; // @[Conditional.scala 37:30]
|
|
wire sb_bus_cmd_write_addr = io_sb_axi_awvalid & io_sb_axi_awready; // @[el2_dbg.scala 433:46]
|
|
wire sb_bus_cmd_write_data = io_sb_axi_wvalid & io_sb_axi_wready; // @[el2_dbg.scala 434:45]
|
|
wire _T_545 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[el2_dbg.scala 398:45]
|
|
wire _T_546 = _T_545 & io_dbg_bus_clk_en; // @[el2_dbg.scala 398:70]
|
|
wire _T_547 = 4'h5 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_548 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[el2_dbg.scala 402:44]
|
|
wire _T_549 = 4'h6 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_550 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[el2_dbg.scala 406:44]
|
|
wire _T_551 = 4'h7 == sb_state; // @[Conditional.scala 37:30]
|
|
wire sb_bus_rsp_read = io_sb_axi_rvalid & io_sb_axi_rready; // @[el2_dbg.scala 435:39]
|
|
wire _T_552 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[el2_dbg.scala 410:38]
|
|
wire _T_554 = 4'h8 == sb_state; // @[Conditional.scala 37:30]
|
|
wire sb_bus_rsp_write = io_sb_axi_bvalid & io_sb_axi_bready; // @[el2_dbg.scala 436:40]
|
|
wire _T_555 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[el2_dbg.scala 416:39]
|
|
wire _T_557 = 4'h9 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _GEN_55 = _T_554 ? _T_555 : _T_557; // @[Conditional.scala 39:67]
|
|
wire _GEN_62 = _T_551 ? _T_552 : _GEN_55; // @[Conditional.scala 39:67]
|
|
wire _GEN_69 = _T_549 ? _T_550 : _GEN_62; // @[Conditional.scala 39:67]
|
|
wire _GEN_76 = _T_547 ? _T_548 : _GEN_69; // @[Conditional.scala 39:67]
|
|
wire _GEN_83 = _T_541 ? _T_546 : _GEN_76; // @[Conditional.scala 39:67]
|
|
wire _GEN_90 = _T_539 ? _T_540 : _GEN_83; // @[Conditional.scala 39:67]
|
|
wire _GEN_97 = _T_532 ? _T_529 : _GEN_90; // @[Conditional.scala 39:67]
|
|
wire _GEN_104 = _T_525 ? _T_529 : _GEN_97; // @[Conditional.scala 39:67]
|
|
wire sb_state_en = sbcs_sbbusy_din ? _T_517 : _GEN_104; // @[Conditional.scala 40:58]
|
|
wire _T_4 = io_dmi_reg_en | sb_state_en; // @[el2_dbg.scala 127:37]
|
|
wire _T_5 = sb_state != 4'h0; // @[el2_dbg.scala 127:63]
|
|
wire _T_6 = _T_4 | _T_5; // @[el2_dbg.scala 127:51]
|
|
wire _T_9 = temp[0] | io_scan_mode; // @[el2_dbg.scala 130:64]
|
|
wire dbg_dm_rst_l = io_dbg_rst_l & _T_9; // @[el2_dbg.scala 130:44]
|
|
wire _T_13 = io_dmi_reg_addr == 7'h38; // @[el2_dbg.scala 132:36]
|
|
wire _T_14 = _T_13 & io_dmi_reg_en; // @[el2_dbg.scala 132:49]
|
|
wire _T_15 = _T_14 & io_dmi_reg_wr_en; // @[el2_dbg.scala 132:65]
|
|
wire _T_16 = sb_state == 4'h0; // @[el2_dbg.scala 132:96]
|
|
wire sbcs_wren = _T_15 & _T_16; // @[el2_dbg.scala 132:84]
|
|
wire _T_18 = sbcs_wren & io_dmi_reg_wdata[22]; // @[el2_dbg.scala 133:42]
|
|
wire _T_20 = _T_5 & io_dmi_reg_en; // @[el2_dbg.scala 133:102]
|
|
wire _T_23 = _T_122 | _T_131; // @[el2_dbg.scala 134:36]
|
|
wire _T_24 = io_dmi_reg_addr == 7'h3d; // @[el2_dbg.scala 134:87]
|
|
wire _T_25 = _T_23 | _T_24; // @[el2_dbg.scala 134:68]
|
|
wire _T_26 = _T_20 & _T_25; // @[el2_dbg.scala 133:118]
|
|
wire sbcs_sbbusyerror_wren = _T_18 | _T_26; // @[el2_dbg.scala 133:66]
|
|
wire sbcs_sbbusyerror_din = ~_T_18; // @[el2_dbg.scala 136:31]
|
|
wire _T_29 = ~dbg_dm_rst_l; // @[el2_dbg.scala 137:53]
|
|
wire _GEN_58 = _T_554 ? 1'h0 : _T_557; // @[Conditional.scala 39:67]
|
|
wire _GEN_65 = _T_551 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67]
|
|
wire _GEN_72 = _T_549 ? 1'h0 : _GEN_65; // @[Conditional.scala 39:67]
|
|
wire _GEN_79 = _T_547 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
|
|
wire _GEN_86 = _T_541 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
|
|
wire _GEN_93 = _T_539 ? 1'h0 : _GEN_86; // @[Conditional.scala 39:67]
|
|
wire _GEN_100 = _T_532 ? 1'h0 : _GEN_93; // @[Conditional.scala 39:67]
|
|
wire _GEN_107 = _T_525 ? 1'h0 : _GEN_100; // @[Conditional.scala 39:67]
|
|
wire sbcs_sbbusy_wren = sbcs_sbbusy_din ? sb_state_en : _GEN_107; // @[Conditional.scala 40:58]
|
|
wire _T_522 = io_dmi_reg_wdata[14:12] == 3'h0; // @[el2_dbg.scala 378:27]
|
|
wire [2:0] _GEN_118 = {{2'd0}, _T_522}; // @[el2_dbg.scala 378:53]
|
|
wire [2:0] _T_524 = _GEN_118 & sbcs_reg[14:12]; // @[el2_dbg.scala 378:53]
|
|
wire _T_519 = |io_dmi_reg_wdata[14:12]; // @[el2_dbg.scala 377:65]
|
|
wire _T_520 = sbcs_wren & _T_519; // @[el2_dbg.scala 377:38]
|
|
wire _T_530 = sbcs_unaligned | sbcs_illegal_size; // @[el2_dbg.scala 383:43]
|
|
wire _T_567 = |io_sb_axi_rresp; // @[el2_dbg.scala 437:63]
|
|
wire _T_568 = sb_bus_rsp_read & _T_567; // @[el2_dbg.scala 437:39]
|
|
wire _T_570 = |io_sb_axi_bresp; // @[el2_dbg.scala 437:110]
|
|
wire _T_571 = sb_bus_rsp_write & _T_570; // @[el2_dbg.scala 437:86]
|
|
wire sb_bus_rsp_error = _T_568 | _T_571; // @[el2_dbg.scala 437:67]
|
|
wire _T_553 = sb_state_en & sb_bus_rsp_error; // @[el2_dbg.scala 411:40]
|
|
wire _GEN_56 = _T_554 & _T_553; // @[Conditional.scala 39:67]
|
|
wire _GEN_63 = _T_551 ? _T_553 : _GEN_56; // @[Conditional.scala 39:67]
|
|
wire _GEN_70 = _T_549 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
|
|
wire _GEN_77 = _T_547 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67]
|
|
wire _GEN_84 = _T_541 ? 1'h0 : _GEN_77; // @[Conditional.scala 39:67]
|
|
wire _GEN_91 = _T_539 ? 1'h0 : _GEN_84; // @[Conditional.scala 39:67]
|
|
wire _GEN_98 = _T_532 ? _T_530 : _GEN_91; // @[Conditional.scala 39:67]
|
|
wire _GEN_105 = _T_525 ? _T_530 : _GEN_98; // @[Conditional.scala 39:67]
|
|
wire sbcs_sberror_wren = sbcs_sbbusy_din ? _T_520 : _GEN_105; // @[Conditional.scala 40:58]
|
|
wire _T_61 = sbcs_reg[19:17] == 3'h0; // @[el2_dbg.scala 163:51]
|
|
wire [3:0] _T_63 = _T_61 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_64 = _T_63 & 4'h1; // @[el2_dbg.scala 163:64]
|
|
wire [3:0] _T_68 = _T_46 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_69 = _T_68 & 4'h2; // @[el2_dbg.scala 163:117]
|
|
wire [3:0] _T_70 = _T_64 | _T_69; // @[el2_dbg.scala 163:76]
|
|
wire [3:0] _T_74 = _T_50 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_75 = _T_74 & 4'h4; // @[el2_dbg.scala 164:44]
|
|
wire [3:0] _T_76 = _T_70 | _T_75; // @[el2_dbg.scala 163:129]
|
|
wire [3:0] _T_80 = _T_56 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_81 = _T_80 & 4'h8; // @[el2_dbg.scala 164:97]
|
|
wire [3:0] sbaddress0_incr = _T_76 | _T_81; // @[el2_dbg.scala 164:56]
|
|
wire _T_84 = sb_state == 4'h7; // @[el2_dbg.scala 167:37]
|
|
wire _T_85 = _T_84 & sb_state_en; // @[el2_dbg.scala 167:60]
|
|
wire _T_86 = ~sbcs_sberror_wren; // @[el2_dbg.scala 167:76]
|
|
wire sbdata0_reg_wren1 = _T_85 & _T_86; // @[el2_dbg.scala 167:74]
|
|
wire sbdata1_reg_wren0 = _T_130 & _T_24; // @[el2_dbg.scala 169:60]
|
|
wire [31:0] _T_93 = sbdata0wr_access ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_94 = _T_93 & io_dmi_reg_wdata; // @[el2_dbg.scala 172:49]
|
|
wire [31:0] _T_96 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [63:0] _T_656 = _T_61 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[el2_dbg.scala 472:93]
|
|
wire [6:0] _T_659 = 4'h8 * _GEN_119; // @[el2_dbg.scala 472:93]
|
|
wire [63:0] _T_660 = io_sb_axi_rdata >> _T_659; // @[el2_dbg.scala 472:86]
|
|
wire [63:0] _T_661 = _T_660 & 64'hff; // @[el2_dbg.scala 472:117]
|
|
wire [63:0] _T_662 = _T_656 & _T_661; // @[el2_dbg.scala 472:59]
|
|
wire [63:0] _T_666 = _T_46 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire [4:0] _GEN_120 = {{3'd0}, sbaddress0_reg[2:1]}; // @[el2_dbg.scala 473:80]
|
|
wire [6:0] _T_669 = 5'h10 * _GEN_120; // @[el2_dbg.scala 473:80]
|
|
wire [63:0] _T_670 = io_sb_axi_rdata >> _T_669; // @[el2_dbg.scala 473:72]
|
|
wire [63:0] _T_671 = _T_670 & 64'hffff; // @[el2_dbg.scala 473:104]
|
|
wire [63:0] _T_672 = _T_666 & _T_671; // @[el2_dbg.scala 473:45]
|
|
wire [63:0] _T_673 = _T_662 | _T_672; // @[el2_dbg.scala 472:134]
|
|
wire [63:0] _T_677 = _T_50 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire [5:0] _GEN_121 = {{5'd0}, sbaddress0_reg[2]}; // @[el2_dbg.scala 474:80]
|
|
wire [6:0] _T_680 = 6'h20 * _GEN_121; // @[el2_dbg.scala 474:80]
|
|
wire [63:0] _T_681 = io_sb_axi_rdata >> _T_680; // @[el2_dbg.scala 474:72]
|
|
wire [63:0] _T_682 = _T_681 & 64'hffffffff; // @[el2_dbg.scala 474:101]
|
|
wire [63:0] _T_683 = _T_677 & _T_682; // @[el2_dbg.scala 474:45]
|
|
wire [63:0] _T_684 = _T_673 | _T_683; // @[el2_dbg.scala 473:123]
|
|
wire [63:0] _T_688 = _T_56 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire [63:0] _T_690 = _T_688 & io_sb_axi_rdata; // @[el2_dbg.scala 475:45]
|
|
wire [63:0] sb_bus_rdata = _T_684 | _T_690; // @[el2_dbg.scala 474:125]
|
|
wire [31:0] _T_98 = _T_96 & sb_bus_rdata[31:0]; // @[el2_dbg.scala 173:33]
|
|
wire [31:0] sbdata0_din = _T_94 | _T_98; // @[el2_dbg.scala 172:68]
|
|
wire [31:0] _T_100 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_101 = _T_100 & io_dmi_reg_wdata; // @[el2_dbg.scala 175:49]
|
|
wire [31:0] _T_105 = _T_96 & sb_bus_rdata[63:32]; // @[el2_dbg.scala 176:33]
|
|
wire [31:0] sbdata1_din = _T_101 | _T_105; // @[el2_dbg.scala 175:68]
|
|
reg [31:0] sbdata0_reg; // @[el2_lib.scala 514:16]
|
|
reg [31:0] sbdata1_reg; // @[el2_lib.scala 514:16]
|
|
wire _GEN_53 = _T_557 & sbcs_reg[16]; // @[Conditional.scala 39:67]
|
|
wire _GEN_60 = _T_554 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
|
|
wire _GEN_67 = _T_551 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
|
|
wire _GEN_74 = _T_549 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67]
|
|
wire _GEN_81 = _T_547 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67]
|
|
wire _GEN_88 = _T_541 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
|
|
wire _GEN_95 = _T_539 ? 1'h0 : _GEN_88; // @[Conditional.scala 39:67]
|
|
wire _GEN_102 = _T_532 ? 1'h0 : _GEN_95; // @[Conditional.scala 39:67]
|
|
wire _GEN_109 = _T_525 ? 1'h0 : _GEN_102; // @[Conditional.scala 39:67]
|
|
wire sbaddress0_reg_wren1 = sbcs_sbbusy_din ? 1'h0 : _GEN_109; // @[Conditional.scala 40:58]
|
|
wire [31:0] _T_111 = _T_123 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_112 = _T_111 & io_dmi_reg_wdata; // @[el2_dbg.scala 188:59]
|
|
wire [31:0] _T_114 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_115 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_117 = sbaddress0_reg + _T_115; // @[el2_dbg.scala 189:54]
|
|
wire [31:0] _T_118 = _T_114 & _T_117; // @[el2_dbg.scala 189:36]
|
|
wire [31:0] sbaddress0_reg_din = _T_112 | _T_118; // @[el2_dbg.scala 188:78]
|
|
wire _T_132 = io_dmi_reg_addr == 7'h10; // @[el2_dbg.scala 197:41]
|
|
wire _T_133 = _T_132 & io_dmi_reg_en; // @[el2_dbg.scala 197:54]
|
|
wire dmcontrol_wren = _T_133 & io_dmi_reg_wr_en; // @[el2_dbg.scala 197:70]
|
|
wire [3:0] _T_139 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58]
|
|
wire _T_168 = dbg_state == 3'h6; // @[el2_dbg.scala 217:44]
|
|
wire _T_169 = _T_168 & io_dec_tlu_resume_ack; // @[el2_dbg.scala 217:66]
|
|
wire _T_171 = ~temp[30]; // @[el2_dbg.scala 217:113]
|
|
wire _T_172 = dmstatus_resumeack & _T_171; // @[el2_dbg.scala 217:111]
|
|
wire dmstatus_resumeack_wren = _T_169 | _T_172; // @[el2_dbg.scala 217:90]
|
|
wire _T_176 = _T_132 & io_dmi_reg_wdata[1]; // @[el2_dbg.scala 219:63]
|
|
wire _T_177 = _T_176 & io_dmi_reg_en; // @[el2_dbg.scala 219:85]
|
|
wire dmstatus_havereset_wren = _T_177 & io_dmi_reg_wr_en; // @[el2_dbg.scala 219:101]
|
|
wire _T_180 = _T_132 & io_dmi_reg_wdata[28]; // @[el2_dbg.scala 220:62]
|
|
wire _T_181 = _T_180 & io_dmi_reg_en; // @[el2_dbg.scala 220:85]
|
|
wire dmstatus_havereset_rst = _T_181 & io_dmi_reg_wr_en; // @[el2_dbg.scala 220:101]
|
|
wire _T_191 = ~io_dec_tlu_mpc_halted_only; // @[el2_dbg.scala 229:37]
|
|
wire _T_192 = io_dec_tlu_dbg_halted & _T_191; // @[el2_dbg.scala 229:35]
|
|
wire _T_195 = ~dmstatus_havereset_rst; // @[el2_dbg.scala 233:15]
|
|
wire _T_198 = abstractcs_reg[12] & io_dmi_reg_en; // @[el2_dbg.scala 239:50]
|
|
wire _T_199 = io_dmi_reg_addr == 7'h16; // @[el2_dbg.scala 239:106]
|
|
wire _T_201 = _T_199 | _T_275; // @[el2_dbg.scala 239:119]
|
|
wire _T_202 = io_dmi_reg_wr_en & _T_201; // @[el2_dbg.scala 239:86]
|
|
wire _T_203 = io_dmi_reg_addr == 7'h4; // @[el2_dbg.scala 239:171]
|
|
wire _T_204 = _T_202 | _T_203; // @[el2_dbg.scala 239:152]
|
|
wire abstractcs_error_sel0 = _T_198 & _T_204; // @[el2_dbg.scala 239:66]
|
|
wire _T_207 = _T_130 & _T_275; // @[el2_dbg.scala 240:64]
|
|
wire _T_209 = io_dmi_reg_wdata[31:24] == 8'h0; // @[el2_dbg.scala 240:126]
|
|
wire _T_211 = io_dmi_reg_wdata[31:24] == 8'h2; // @[el2_dbg.scala 240:163]
|
|
wire _T_212 = _T_209 | _T_211; // @[el2_dbg.scala 240:135]
|
|
wire _T_213 = ~_T_212; // @[el2_dbg.scala 240:98]
|
|
wire abstractcs_error_sel1 = _T_207 & _T_213; // @[el2_dbg.scala 240:96]
|
|
wire abstractcs_error_sel2 = io_core_dbg_cmd_done & io_core_dbg_cmd_fail; // @[el2_dbg.scala 241:52]
|
|
wire _T_218 = ~dmstatus_reg[9]; // @[el2_dbg.scala 242:98]
|
|
wire abstractcs_error_sel3 = _T_207 & _T_218; // @[el2_dbg.scala 242:96]
|
|
wire _T_223 = io_dmi_reg_wdata[22:20] != 3'h2; // @[el2_dbg.scala 244:32]
|
|
reg [31:0] data1_reg; // @[el2_lib.scala 514:16]
|
|
wire _T_227 = |data1_reg[1:0]; // @[el2_dbg.scala 244:106]
|
|
wire _T_228 = _T_211 & _T_227; // @[el2_dbg.scala 244:87]
|
|
wire _T_229 = _T_223 | _T_228; // @[el2_dbg.scala 244:46]
|
|
wire abstractcs_error_sel4 = _T_277 & _T_229; // @[el2_dbg.scala 243:96]
|
|
wire _T_231 = _T_199 & io_dmi_reg_en; // @[el2_dbg.scala 246:61]
|
|
wire abstractcs_error_sel5 = _T_231 & io_dmi_reg_wr_en; // @[el2_dbg.scala 246:77]
|
|
wire _T_232 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[el2_dbg.scala 247:54]
|
|
wire _T_233 = _T_232 | abstractcs_error_sel2; // @[el2_dbg.scala 247:78]
|
|
wire _T_234 = _T_233 | abstractcs_error_sel3; // @[el2_dbg.scala 247:102]
|
|
wire _T_235 = _T_234 | abstractcs_error_sel4; // @[el2_dbg.scala 247:126]
|
|
wire abstractcs_error_selor = _T_235 | abstractcs_error_sel5; // @[el2_dbg.scala 247:150]
|
|
wire [2:0] _T_237 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_238 = _T_237 & 3'h1; // @[el2_dbg.scala 248:62]
|
|
wire [2:0] _T_240 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_241 = _T_240 & 3'h2; // @[el2_dbg.scala 249:37]
|
|
wire [2:0] _T_242 = _T_238 | _T_241; // @[el2_dbg.scala 248:74]
|
|
wire [2:0] _T_244 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_245 = _T_244 & 3'h3; // @[el2_dbg.scala 250:37]
|
|
wire [2:0] _T_246 = _T_242 | _T_245; // @[el2_dbg.scala 249:49]
|
|
wire [2:0] _T_248 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_249 = _T_248 & 3'h4; // @[el2_dbg.scala 251:37]
|
|
wire [2:0] _T_250 = _T_246 | _T_249; // @[el2_dbg.scala 250:49]
|
|
wire [2:0] _T_252 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_254 = _T_250 | _T_252; // @[el2_dbg.scala 251:49]
|
|
wire [2:0] _T_256 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_258 = ~io_dmi_reg_wdata[10:8]; // @[el2_dbg.scala 253:40]
|
|
wire [2:0] _T_259 = _T_256 & _T_258; // @[el2_dbg.scala 253:37]
|
|
wire [2:0] _T_261 = _T_259 & abstractcs_reg[10:8]; // @[el2_dbg.scala 253:75]
|
|
wire [2:0] _T_262 = _T_254 | _T_261; // @[el2_dbg.scala 252:49]
|
|
wire _T_263 = ~abstractcs_error_selor; // @[el2_dbg.scala 254:15]
|
|
wire [2:0] _T_265 = _T_263 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_267 = _T_265 & abstractcs_reg[10:8]; // @[el2_dbg.scala 254:50]
|
|
wire [2:0] abstractcs_error_din = _T_262 | _T_267; // @[el2_dbg.scala 253:100]
|
|
wire [2:0] _T_312 = _T_363 ? 3'h2 : 3'h1; // @[el2_dbg.scala 296:26]
|
|
wire [2:0] _T_329 = temp[1] ? 3'h0 : 3'h2; // @[el2_dbg.scala 301:26]
|
|
wire _T_343 = dmstatus_reg[9] & _T_320; // @[el2_dbg.scala 306:43]
|
|
wire _T_346 = ~temp[3]; // @[el2_dbg.scala 307:33]
|
|
wire _T_347 = temp[30] & _T_346; // @[el2_dbg.scala 307:31]
|
|
wire [2:0] _T_348 = _T_347 ? 3'h6 : 3'h3; // @[el2_dbg.scala 307:12]
|
|
wire [2:0] _T_350 = temp[31] ? 3'h1 : 3'h0; // @[el2_dbg.scala 308:12]
|
|
wire [2:0] _T_351 = _T_343 ? _T_348 : _T_350; // @[el2_dbg.scala 306:26]
|
|
wire [2:0] _T_381 = _T_384 ? 3'h5 : 3'h4; // @[el2_dbg.scala 317:62]
|
|
wire [2:0] _T_382 = temp[1] ? 3'h0 : _T_381; // @[el2_dbg.scala 317:26]
|
|
wire [2:0] _T_396 = temp[1] ? 3'h0 : 3'h5; // @[el2_dbg.scala 322:26]
|
|
wire [2:0] _GEN_15 = _T_405 ? _T_329 : 3'h0; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_20 = _T_394 ? _T_396 : _GEN_15; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_25 = _T_377 ? _T_382 : _GEN_20; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_30 = _T_339 ? _T_351 : _GEN_25; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_36 = _T_327 ? _T_329 : _GEN_30; // @[Conditional.scala 39:67]
|
|
wire [2:0] dbg_nxtstate = _T_309 ? _T_312 : _GEN_36; // @[Conditional.scala 40:58]
|
|
wire _T_366 = dbg_nxtstate == 3'h3; // @[el2_dbg.scala 311:60]
|
|
wire _T_367 = dbg_state_en & _T_366; // @[el2_dbg.scala 311:44]
|
|
wire _GEN_17 = _T_405 & dbg_state_en; // @[Conditional.scala 39:67]
|
|
wire _GEN_23 = _T_394 ? 1'h0 : _GEN_17; // @[Conditional.scala 39:67]
|
|
wire _GEN_28 = _T_377 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67]
|
|
wire _GEN_32 = _T_339 ? _T_367 : _GEN_28; // @[Conditional.scala 39:67]
|
|
wire _GEN_39 = _T_327 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
|
|
wire abstractcs_busy_wren = _T_309 ? 1'h0 : _GEN_39; // @[Conditional.scala 40:58]
|
|
wire [31:0] command_din = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20],3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58]
|
|
reg [31:0] command_reg; // @[Reg.scala 27:20]
|
|
wire _T_288 = _T_130 & _T_203; // @[el2_dbg.scala 272:58]
|
|
wire data0_reg_wren0 = _T_288 & _T_278; // @[el2_dbg.scala 272:89]
|
|
wire _T_290 = dbg_state == 3'h4; // @[el2_dbg.scala 273:59]
|
|
wire _T_291 = io_core_dbg_cmd_done & _T_290; // @[el2_dbg.scala 273:46]
|
|
wire _T_293 = ~command_reg[16]; // @[el2_dbg.scala 273:83]
|
|
wire data0_reg_wren1 = _T_291 & _T_293; // @[el2_dbg.scala 273:81]
|
|
wire data0_reg_wren = data0_reg_wren0 | data0_reg_wren1; // @[el2_dbg.scala 275:40]
|
|
wire [31:0] _T_295 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_296 = _T_295 & io_dmi_reg_wdata; // @[el2_dbg.scala 276:45]
|
|
wire [31:0] _T_298 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_299 = _T_298 & io_core_dbg_rddata; // @[el2_dbg.scala 276:92]
|
|
wire [31:0] data0_din = _T_296 | _T_299; // @[el2_dbg.scala 276:64]
|
|
reg [31:0] data0_reg; // @[Reg.scala 27:20]
|
|
wire _T_302 = io_dmi_reg_addr == 7'h5; // @[el2_dbg.scala 281:77]
|
|
wire _T_303 = _T_130 & _T_302; // @[el2_dbg.scala 281:58]
|
|
wire data1_reg_wren = _T_303 & _T_278; // @[el2_dbg.scala 281:89]
|
|
wire [31:0] _T_306 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] data1_din = _T_306 & io_dmi_reg_wdata; // @[el2_dbg.scala 282:44]
|
|
wire _T_325 = temp[31] & _T_320; // @[el2_dbg.scala 298:45]
|
|
wire _T_334 = dmcontrol_wren_Q & temp[31]; // @[el2_dbg.scala 303:44]
|
|
wire _T_337 = _T_334 & _T_320; // @[el2_dbg.scala 303:64]
|
|
wire _T_368 = dbg_nxtstate == 3'h6; // @[el2_dbg.scala 313:58]
|
|
wire _T_369 = dbg_state_en & _T_368; // @[el2_dbg.scala 313:42]
|
|
wire _GEN_14 = _T_414 & _T_337; // @[Conditional.scala 39:67]
|
|
wire _GEN_19 = _T_405 ? _T_337 : _GEN_14; // @[Conditional.scala 39:67]
|
|
wire _GEN_22 = _T_394 ? _T_337 : _GEN_19; // @[Conditional.scala 39:67]
|
|
wire _GEN_27 = _T_377 ? _T_337 : _GEN_22; // @[Conditional.scala 39:67]
|
|
wire _GEN_34 = _T_339 & _T_369; // @[Conditional.scala 39:67]
|
|
wire _GEN_35 = _T_339 ? _T_337 : _GEN_27; // @[Conditional.scala 39:67]
|
|
wire _GEN_38 = _T_327 ? _T_337 : _GEN_35; // @[Conditional.scala 39:67]
|
|
wire _GEN_41 = _T_327 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67]
|
|
wire _T_478 = _T_29 & reset; // @[el2_dbg.scala 346:62]
|
|
wire _T_483 = command_reg[31:24] == 8'h2; // @[el2_dbg.scala 355:47]
|
|
wire [30:0] _T_485 = {data1_reg[31:2],1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_487 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58]
|
|
wire _T_490 = dbg_state == 3'h3; // @[el2_dbg.scala 357:35]
|
|
wire _T_493 = ~_T_384; // @[el2_dbg.scala 357:60]
|
|
wire _T_494 = _T_490 & _T_493; // @[el2_dbg.scala 357:58]
|
|
wire _T_502 = command_reg[15:12] == 4'h0; // @[el2_dbg.scala 359:102]
|
|
wire [1:0] _T_503 = {1'h0,_T_502}; // @[Cat.scala 29:58]
|
|
wire _T_542 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[el2_dbg.scala 397:48]
|
|
wire _T_573 = sb_state == 4'h4; // @[el2_dbg.scala 438:35]
|
|
wire _T_574 = sb_state == 4'h5; // @[el2_dbg.scala 438:70]
|
|
wire _T_580 = sb_state == 4'h6; // @[el2_dbg.scala 449:69]
|
|
wire [63:0] _T_590 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_591 = _T_656 & _T_590; // @[el2_dbg.scala 450:59]
|
|
wire [63:0] _T_598 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_599 = _T_666 & _T_598; // @[el2_dbg.scala 450:132]
|
|
wire [63:0] _T_600 = _T_591 | _T_599; // @[el2_dbg.scala 450:90]
|
|
wire [63:0] _T_606 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_607 = _T_677 & _T_606; // @[el2_dbg.scala 451:45]
|
|
wire [63:0] _T_608 = _T_600 | _T_607; // @[el2_dbg.scala 450:162]
|
|
wire [63:0] _T_615 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_616 = _T_688 & _T_615; // @[el2_dbg.scala 451:119]
|
|
wire [7:0] _T_621 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [14:0] _T_623 = 15'h1 << sbaddress0_reg[2:0]; // @[el2_dbg.scala 453:76]
|
|
wire [14:0] _GEN_122 = {{7'd0}, _T_621}; // @[el2_dbg.scala 453:61]
|
|
wire [14:0] _T_624 = _GEN_122 & _T_623; // @[el2_dbg.scala 453:61]
|
|
wire [7:0] _T_628 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_630 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58]
|
|
wire [14:0] _T_631 = 15'h3 << _T_630; // @[el2_dbg.scala 454:59]
|
|
wire [14:0] _GEN_123 = {{7'd0}, _T_628}; // @[el2_dbg.scala 454:44]
|
|
wire [14:0] _T_632 = _GEN_123 & _T_631; // @[el2_dbg.scala 454:44]
|
|
wire [14:0] _T_633 = _T_624 | _T_632; // @[el2_dbg.scala 453:101]
|
|
wire [7:0] _T_637 = _T_50 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_639 = {sbaddress0_reg[2],1'h0}; // @[Cat.scala 29:58]
|
|
wire [10:0] _T_640 = 11'hf << _T_639; // @[el2_dbg.scala 455:59]
|
|
wire [10:0] _GEN_124 = {{3'd0}, _T_637}; // @[el2_dbg.scala 455:44]
|
|
wire [10:0] _T_641 = _GEN_124 & _T_640; // @[el2_dbg.scala 455:44]
|
|
wire [14:0] _GEN_125 = {{4'd0}, _T_641}; // @[el2_dbg.scala 454:97]
|
|
wire [14:0] _T_642 = _T_633 | _GEN_125; // @[el2_dbg.scala 454:97]
|
|
wire [7:0] _T_646 = _T_56 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [14:0] _GEN_126 = {{7'd0}, _T_646}; // @[el2_dbg.scala 455:95]
|
|
wire [14:0] _T_648 = _T_642 | _GEN_126; // @[el2_dbg.scala 455:95]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr_757 rvclkhdr_2 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr_757 rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr_757 rvclkhdr_4 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr_757 rvclkhdr_5 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
assign io_dbg_cmd_addr = _T_483 ? {{1'd0}, _T_485} : _T_487; // @[el2_dbg.scala 355:19]
|
|
assign io_dbg_cmd_wrdata = data0_reg; // @[el2_dbg.scala 356:21]
|
|
assign io_dbg_cmd_valid = _T_494 & io_dma_dbg_ready; // @[el2_dbg.scala 357:20]
|
|
assign io_dbg_cmd_write = command_reg[16]; // @[el2_dbg.scala 358:20]
|
|
assign io_dbg_cmd_type = _T_483 ? 2'h2 : _T_503; // @[el2_dbg.scala 359:19]
|
|
assign io_dbg_cmd_size = command_reg[21:20]; // @[el2_dbg.scala 360:19]
|
|
assign io_dbg_core_rst_l = ~temp[1]; // @[el2_dbg.scala 131:21]
|
|
assign io_dbg_dma_bubble = _T_494 | _T_290; // @[el2_dbg.scala 361:21]
|
|
assign io_dbg_halt_req = _T_309 ? _T_325 : _GEN_38; // @[el2_dbg.scala 292:19 el2_dbg.scala 298:23 el2_dbg.scala 303:23 el2_dbg.scala 314:23 el2_dbg.scala 319:23 el2_dbg.scala 324:23 el2_dbg.scala 331:23 el2_dbg.scala 336:23]
|
|
assign io_dbg_resume_req = _T_309 ? 1'h0 : _GEN_41; // @[el2_dbg.scala 293:21 el2_dbg.scala 313:25]
|
|
assign io_sb_axi_awvalid = _T_573 | _T_574; // @[el2_dbg.scala 438:21]
|
|
assign io_sb_axi_awaddr = sbaddress0_reg; // @[el2_dbg.scala 439:20]
|
|
assign io_sb_axi_awregion = sbaddress0_reg[31:28]; // @[el2_dbg.scala 444:22]
|
|
assign io_sb_axi_awsize = sbcs_reg[19:17]; // @[el2_dbg.scala 441:20]
|
|
assign io_sb_axi_wvalid = _T_573 | _T_580; // @[el2_dbg.scala 449:20]
|
|
assign io_sb_axi_wdata = _T_608 | _T_616; // @[el2_dbg.scala 450:19]
|
|
assign io_sb_axi_wstrb = _T_648[7:0]; // @[el2_dbg.scala 453:19]
|
|
assign io_sb_axi_bready = 1'h1; // @[el2_dbg.scala 470:20]
|
|
assign io_sb_axi_arvalid = sb_state == 4'h3; // @[el2_dbg.scala 459:21]
|
|
assign io_sb_axi_araddr = sbaddress0_reg; // @[el2_dbg.scala 460:20]
|
|
assign io_sb_axi_arregion = sbaddress0_reg[31:28]; // @[el2_dbg.scala 465:22]
|
|
assign io_sb_axi_arsize = sbcs_reg[19:17]; // @[el2_dbg.scala 462:20]
|
|
assign io_sb_axi_rready = 1'h1; // @[el2_dbg.scala 471:20]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_io_en = _T_3 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_1_io_en = _T_6 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_2_io_en = sbdata0wr_access | sbdata0_reg_wren1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_4_io_en = _T_123 | sbaddress0_reg_wren1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_5_io_en = _T_303 & _T_278; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
dbg_state = _RAND_0[2:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
dm_temp = _RAND_1[3:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
dm_temp_0 = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
dmstatus_havereset = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
dmstatus_resumeack = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
dmstatus_halted = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
dmcontrol_wren_Q = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
abs_temp_12 = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
abs_temp_10_8 = _RAND_8[2:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
sb_state = _RAND_9[3:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
temp_sbcs_22 = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
temp_sbcs_21 = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
temp_sbcs_20 = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
temp_sbcs_19_15 = _RAND_13[4:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
temp_sbcs_14_12 = _RAND_14[2:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
sbaddress0_reg = _RAND_15[31:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
sbdata0_reg = _RAND_16[31:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
sbdata1_reg = _RAND_17[31:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
data1_reg = _RAND_18[31:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
command_reg = _RAND_19[31:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
data0_reg = _RAND_20[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge rvclkhdr_io_l1clk) begin
|
|
if (_T_478) begin
|
|
dbg_state <= 3'h0;
|
|
end else if (dbg_state_en) begin
|
|
if (_T_309) begin
|
|
if (_T_363) begin
|
|
dbg_state <= 3'h2;
|
|
end else begin
|
|
dbg_state <= 3'h1;
|
|
end
|
|
end else if (_T_327) begin
|
|
if (temp[1]) begin
|
|
dbg_state <= 3'h0;
|
|
end else begin
|
|
dbg_state <= 3'h2;
|
|
end
|
|
end else if (_T_339) begin
|
|
if (_T_343) begin
|
|
if (_T_347) begin
|
|
dbg_state <= 3'h6;
|
|
end else begin
|
|
dbg_state <= 3'h3;
|
|
end
|
|
end else if (temp[31]) begin
|
|
dbg_state <= 3'h1;
|
|
end else begin
|
|
dbg_state <= 3'h0;
|
|
end
|
|
end else if (_T_377) begin
|
|
if (temp[1]) begin
|
|
dbg_state <= 3'h0;
|
|
end else if (_T_384) begin
|
|
dbg_state <= 3'h5;
|
|
end else begin
|
|
dbg_state <= 3'h4;
|
|
end
|
|
end else if (_T_394) begin
|
|
if (temp[1]) begin
|
|
dbg_state <= 3'h0;
|
|
end else begin
|
|
dbg_state <= 3'h5;
|
|
end
|
|
end else if (_T_405) begin
|
|
if (temp[1]) begin
|
|
dbg_state <= 3'h0;
|
|
end else begin
|
|
dbg_state <= 3'h2;
|
|
end
|
|
end else begin
|
|
dbg_state <= 3'h0;
|
|
end
|
|
end
|
|
if (_T_29) begin
|
|
dm_temp <= 4'h0;
|
|
end else if (dmcontrol_wren) begin
|
|
dm_temp <= _T_139;
|
|
end
|
|
if (io_dbg_rst_l) begin
|
|
dm_temp_0 <= 1'h0;
|
|
end else if (dmcontrol_wren) begin
|
|
dm_temp_0 <= io_dmi_reg_wdata[0];
|
|
end
|
|
if (_T_29) begin
|
|
dmstatus_havereset <= 1'h0;
|
|
end else if (dmstatus_havereset_wren) begin
|
|
dmstatus_havereset <= _T_195;
|
|
end
|
|
if (_T_29) begin
|
|
dmstatus_resumeack <= 1'h0;
|
|
end else if (dmstatus_resumeack_wren) begin
|
|
dmstatus_resumeack <= _T_169;
|
|
end
|
|
if (_T_29) begin
|
|
dmstatus_halted <= 1'h0;
|
|
end else begin
|
|
dmstatus_halted <= _T_192;
|
|
end
|
|
if (_T_29) begin
|
|
dmcontrol_wren_Q <= 1'h0;
|
|
end else begin
|
|
dmcontrol_wren_Q <= dmcontrol_wren;
|
|
end
|
|
if (_T_29) begin
|
|
abs_temp_12 <= 1'h0;
|
|
end else if (abstractcs_busy_wren) begin
|
|
if (_T_309) begin
|
|
abs_temp_12 <= 1'h0;
|
|
end else if (_T_327) begin
|
|
abs_temp_12 <= 1'h0;
|
|
end else begin
|
|
abs_temp_12 <= _T_339;
|
|
end
|
|
end
|
|
if (_T_29) begin
|
|
abs_temp_10_8 <= 3'h0;
|
|
end else begin
|
|
abs_temp_10_8 <= abstractcs_error_din;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk) begin
|
|
if (_T_29) begin
|
|
sb_state <= 4'h0;
|
|
end else if (sb_state_en) begin
|
|
if (sbcs_sbbusy_din) begin
|
|
if (sbdata0wr_access) begin
|
|
sb_state <= 4'h2;
|
|
end else begin
|
|
sb_state <= 4'h1;
|
|
end
|
|
end else if (_T_525) begin
|
|
if (_T_530) begin
|
|
sb_state <= 4'h9;
|
|
end else begin
|
|
sb_state <= 4'h3;
|
|
end
|
|
end else if (_T_532) begin
|
|
if (_T_530) begin
|
|
sb_state <= 4'h9;
|
|
end else begin
|
|
sb_state <= 4'h4;
|
|
end
|
|
end else if (_T_539) begin
|
|
sb_state <= 4'h7;
|
|
end else if (_T_541) begin
|
|
if (_T_542) begin
|
|
sb_state <= 4'h8;
|
|
end else if (sb_bus_cmd_write_data) begin
|
|
sb_state <= 4'h5;
|
|
end else begin
|
|
sb_state <= 4'h6;
|
|
end
|
|
end else if (_T_547) begin
|
|
sb_state <= 4'h8;
|
|
end else if (_T_549) begin
|
|
sb_state <= 4'h8;
|
|
end else if (_T_551) begin
|
|
sb_state <= 4'h9;
|
|
end else if (_T_554) begin
|
|
sb_state <= 4'h9;
|
|
end else begin
|
|
sb_state <= 4'h0;
|
|
end
|
|
end
|
|
if (_T_29) begin
|
|
temp_sbcs_22 <= 1'h0;
|
|
end else if (sbcs_sbbusyerror_wren) begin
|
|
temp_sbcs_22 <= sbcs_sbbusyerror_din;
|
|
end
|
|
if (_T_29) begin
|
|
temp_sbcs_21 <= 1'h0;
|
|
end else if (sbcs_sbbusy_wren) begin
|
|
temp_sbcs_21 <= sbcs_sbbusy_din;
|
|
end
|
|
if (_T_29) begin
|
|
temp_sbcs_20 <= 1'h0;
|
|
end else if (sbcs_wren) begin
|
|
temp_sbcs_20 <= io_dmi_reg_wdata[20];
|
|
end
|
|
if (_T_29) begin
|
|
temp_sbcs_19_15 <= 5'h0;
|
|
end else if (sbcs_wren) begin
|
|
temp_sbcs_19_15 <= io_dmi_reg_wdata[19:15];
|
|
end
|
|
if (_T_29) begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end else if (sbcs_sberror_wren) begin
|
|
if (sbcs_sbbusy_din) begin
|
|
temp_sbcs_14_12 <= _T_524;
|
|
end else if (_T_525) begin
|
|
if (sbcs_unaligned) begin
|
|
temp_sbcs_14_12 <= 3'h3;
|
|
end else begin
|
|
temp_sbcs_14_12 <= 3'h4;
|
|
end
|
|
end else if (_T_532) begin
|
|
if (sbcs_unaligned) begin
|
|
temp_sbcs_14_12 <= 3'h3;
|
|
end else begin
|
|
temp_sbcs_14_12 <= 3'h4;
|
|
end
|
|
end else if (_T_539) begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end else if (_T_541) begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end else if (_T_547) begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end else if (_T_549) begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end else if (_T_551) begin
|
|
temp_sbcs_14_12 <= 3'h2;
|
|
end else if (_T_554) begin
|
|
temp_sbcs_14_12 <= 3'h2;
|
|
end else begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_4_io_l1clk) begin
|
|
if (_T_29) begin
|
|
sbaddress0_reg <= 32'h0;
|
|
end else begin
|
|
sbaddress0_reg <= sbaddress0_reg_din;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk) begin
|
|
if (_T_29) begin
|
|
sbdata0_reg <= 32'h0;
|
|
end else begin
|
|
sbdata0_reg <= sbdata0_din;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk) begin
|
|
if (_T_29) begin
|
|
sbdata1_reg <= 32'h0;
|
|
end else begin
|
|
sbdata1_reg <= sbdata1_din;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk) begin
|
|
if (_T_29) begin
|
|
data1_reg <= 32'h0;
|
|
end else begin
|
|
data1_reg <= data1_din;
|
|
end
|
|
end
|
|
always @(posedge clock) begin
|
|
if (_T_29) begin
|
|
command_reg <= 32'h0;
|
|
end else if (command_wren) begin
|
|
command_reg <= command_din;
|
|
end
|
|
if (_T_29) begin
|
|
data0_reg <= 32'h0;
|
|
end else if (data0_reg_wren) begin
|
|
data0_reg <= data0_din;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_exu_alu_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_scan_mode,
|
|
input io_flush_upper_x,
|
|
input io_flush_lower_r,
|
|
input io_enable,
|
|
input io_valid_in,
|
|
input io_ap_land,
|
|
input io_ap_lor,
|
|
input io_ap_lxor,
|
|
input io_ap_sll,
|
|
input io_ap_srl,
|
|
input io_ap_sra,
|
|
input io_ap_beq,
|
|
input io_ap_bne,
|
|
input io_ap_blt,
|
|
input io_ap_bge,
|
|
input io_ap_add,
|
|
input io_ap_sub,
|
|
input io_ap_slt,
|
|
input io_ap_unsign,
|
|
input io_ap_jal,
|
|
input io_ap_predict_t,
|
|
input io_ap_predict_nt,
|
|
input io_ap_csr_write,
|
|
input io_ap_csr_imm,
|
|
input io_csr_ren_in,
|
|
input [31:0] io_a_in,
|
|
input [31:0] io_b_in,
|
|
input [30:0] io_pc_in,
|
|
input io_pp_in_valid,
|
|
input io_pp_in_bits_boffset,
|
|
input io_pp_in_bits_pc4,
|
|
input [1:0] io_pp_in_bits_hist,
|
|
input [11:0] io_pp_in_bits_toffset,
|
|
input io_pp_in_bits_br_error,
|
|
input io_pp_in_bits_br_start_error,
|
|
input [30:0] io_pp_in_bits_prett,
|
|
input io_pp_in_bits_pcall,
|
|
input io_pp_in_bits_pret,
|
|
input io_pp_in_bits_pja,
|
|
input io_pp_in_bits_way,
|
|
input [11:0] io_brimm_in,
|
|
output [31:0] io_result_ff,
|
|
output io_flush_upper_out,
|
|
output io_flush_final_out,
|
|
output [30:0] io_flush_path_out,
|
|
output [30:0] io_pc_ff,
|
|
output io_pred_correct_out,
|
|
output io_predict_p_out_valid,
|
|
output io_predict_p_out_bits_misp,
|
|
output io_predict_p_out_bits_ataken,
|
|
output io_predict_p_out_bits_boffset,
|
|
output io_predict_p_out_bits_pc4,
|
|
output [1:0] io_predict_p_out_bits_hist,
|
|
output [11:0] io_predict_p_out_bits_toffset,
|
|
output io_predict_p_out_bits_br_error,
|
|
output io_predict_p_out_bits_br_start_error,
|
|
output io_predict_p_out_bits_pcall,
|
|
output io_predict_p_out_bits_pret,
|
|
output io_predict_p_out_bits_pja,
|
|
output io_predict_p_out_bits_way
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
reg [30:0] _T_1; // @[el2_lib.scala 514:16]
|
|
reg [31:0] _T_3; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_5 = ~io_b_in; // @[el2_exu_alu_ctl.scala 39:37]
|
|
wire [31:0] bm = io_ap_sub ? _T_5 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17]
|
|
wire [32:0] _T_8 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_10 = {1'h0,_T_5}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_12 = _T_8 + _T_10; // @[el2_exu_alu_ctl.scala 42:55]
|
|
wire [32:0] _T_13 = {32'h0,io_ap_sub}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_15 = _T_12 + _T_13; // @[el2_exu_alu_ctl.scala 42:80]
|
|
wire [32:0] _T_18 = {1'h0,io_b_in}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_20 = _T_8 + _T_18; // @[el2_exu_alu_ctl.scala 42:132]
|
|
wire [32:0] _T_23 = _T_20 + _T_13; // @[el2_exu_alu_ctl.scala 42:157]
|
|
wire [32:0] aout = io_ap_sub ? _T_15 : _T_23; // @[el2_exu_alu_ctl.scala 42:14]
|
|
wire cout = aout[32]; // @[el2_exu_alu_ctl.scala 43:18]
|
|
wire _T_26 = ~io_a_in[31]; // @[el2_exu_alu_ctl.scala 45:14]
|
|
wire _T_28 = ~bm[31]; // @[el2_exu_alu_ctl.scala 45:29]
|
|
wire _T_29 = _T_26 & _T_28; // @[el2_exu_alu_ctl.scala 45:27]
|
|
wire _T_31 = _T_29 & aout[31]; // @[el2_exu_alu_ctl.scala 45:37]
|
|
wire _T_34 = io_a_in[31] & bm[31]; // @[el2_exu_alu_ctl.scala 45:66]
|
|
wire _T_36 = ~aout[31]; // @[el2_exu_alu_ctl.scala 45:78]
|
|
wire _T_37 = _T_34 & _T_36; // @[el2_exu_alu_ctl.scala 45:76]
|
|
wire ov = _T_31 | _T_37; // @[el2_exu_alu_ctl.scala 45:50]
|
|
wire eq = $signed(io_a_in) == $signed(io_b_in); // @[el2_exu_alu_ctl.scala 47:38]
|
|
wire ne = ~eq; // @[el2_exu_alu_ctl.scala 48:29]
|
|
wire _T_39 = ~io_ap_unsign; // @[el2_exu_alu_ctl.scala 50:30]
|
|
wire _T_40 = aout[31] ^ ov; // @[el2_exu_alu_ctl.scala 50:51]
|
|
wire _T_41 = _T_39 & _T_40; // @[el2_exu_alu_ctl.scala 50:44]
|
|
wire _T_42 = ~cout; // @[el2_exu_alu_ctl.scala 50:78]
|
|
wire _T_43 = io_ap_unsign & _T_42; // @[el2_exu_alu_ctl.scala 50:76]
|
|
wire lt = _T_41 | _T_43; // @[el2_exu_alu_ctl.scala 50:58]
|
|
wire ge = ~lt; // @[el2_exu_alu_ctl.scala 51:29]
|
|
wire [31:0] _T_63 = $signed(io_a_in) & $signed(io_b_in); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_66 = $signed(io_a_in) | $signed(io_b_in); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_69 = $signed(io_a_in) ^ $signed(io_b_in); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_70 = io_csr_ren_in ? $signed(io_b_in) : $signed(32'sh0); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_71 = io_ap_land ? $signed(_T_63) : $signed(32'sh0); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_72 = io_ap_lor ? $signed(_T_66) : $signed(32'sh0); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_73 = io_ap_lxor ? $signed(_T_69) : $signed(32'sh0); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_75 = $signed(_T_70) | $signed(_T_71); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_77 = $signed(_T_75) | $signed(_T_72); // @[Mux.scala 27:72]
|
|
wire [5:0] _T_84 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58]
|
|
wire [5:0] _T_86 = 6'h20 - _T_84; // @[el2_exu_alu_ctl.scala 61:38]
|
|
wire [5:0] _T_93 = io_ap_sll ? _T_86 : 6'h0; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_94 = io_ap_srl ? _T_84 : 6'h0; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_95 = io_ap_sra ? _T_84 : 6'h0; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_96 = _T_93 | _T_94; // @[Mux.scala 27:72]
|
|
wire [5:0] shift_amount = _T_96 | _T_95; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_102 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
|
|
wire [4:0] _T_104 = _T_102 & io_b_in[4:0]; // @[el2_exu_alu_ctl.scala 66:61]
|
|
wire [62:0] _T_105 = 63'hffffffff << _T_104; // @[el2_exu_alu_ctl.scala 66:39]
|
|
wire [9:0] _T_115 = {io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_124 = {_T_115,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_133 = {_T_124,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
|
|
wire [30:0] _T_136 = {_T_133,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_147 = {io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_156 = {_T_147,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_165 = {_T_156,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
|
|
wire [30:0] _T_168 = {_T_165,io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
|
|
wire [30:0] _T_169 = _T_136 & _T_168; // @[el2_exu_alu_ctl.scala 69:44]
|
|
wire [9:0] _T_179 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_188 = {_T_179,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_197 = {_T_188,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
|
|
wire [30:0] _T_200 = {_T_197,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
|
|
wire [30:0] _T_202 = _T_200 & io_a_in[30:0]; // @[el2_exu_alu_ctl.scala 69:90]
|
|
wire [30:0] _T_203 = _T_169 | _T_202; // @[el2_exu_alu_ctl.scala 69:68]
|
|
wire [62:0] shift_extend = {_T_203,io_a_in}; // @[Cat.scala 29:58]
|
|
wire [62:0] shift_long = shift_extend >> shift_amount[4:0]; // @[el2_exu_alu_ctl.scala 72:32]
|
|
wire [31:0] shift_mask = _T_105[31:0]; // @[el2_exu_alu_ctl.scala 66:14]
|
|
wire [31:0] sout = shift_long[31:0] & shift_mask; // @[el2_exu_alu_ctl.scala 74:34]
|
|
wire _T_210 = io_ap_sll | io_ap_srl; // @[el2_exu_alu_ctl.scala 77:41]
|
|
wire sel_shift = _T_210 | io_ap_sra; // @[el2_exu_alu_ctl.scala 77:53]
|
|
wire _T_211 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 78:41]
|
|
wire _T_212 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 78:56]
|
|
wire sel_adder = _T_211 & _T_212; // @[el2_exu_alu_ctl.scala 78:54]
|
|
wire _T_213 = io_ap_jal | io_pp_in_bits_pcall; // @[el2_exu_alu_ctl.scala 79:41]
|
|
wire _T_214 = _T_213 | io_pp_in_bits_pja; // @[el2_exu_alu_ctl.scala 79:63]
|
|
wire sel_pc = _T_214 | io_pp_in_bits_pret; // @[el2_exu_alu_ctl.scala 79:83]
|
|
wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40]
|
|
wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[el2_lib.scala 208:31]
|
|
wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[el2_lib.scala 209:27]
|
|
wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27]
|
|
wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28]
|
|
wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26]
|
|
wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:20]
|
|
wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:26]
|
|
wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:26]
|
|
wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_245 = _T_242 | _T_243; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_246 = _T_245 | _T_244; // @[Mux.scala 27:72]
|
|
wire [31:0] pcout = {_T_246,_T_221[11:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_250 = $signed(_T_77) | $signed(_T_73); // @[el2_exu_alu_ctl.scala 88:24]
|
|
wire [31:0] _T_251 = {31'h0,slt_one}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_252 = _T_250 | _T_251; // @[el2_exu_alu_ctl.scala 88:31]
|
|
wire [31:0] _T_259 = io_ap_csr_imm ? $signed(io_b_in) : $signed(io_a_in); // @[el2_exu_alu_ctl.scala 92:51]
|
|
wire [31:0] _T_260 = sel_shift ? sout : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_261 = sel_adder ? aout[31:0] : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_262 = sel_pc ? pcout : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_263 = io_ap_csr_write ? _T_259 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_264 = _T_260 | _T_261; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_265 = _T_264 | _T_262; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_266 = _T_265 | _T_263; // @[Mux.scala 27:72]
|
|
wire _T_271 = io_ap_beq & eq; // @[el2_exu_alu_ctl.scala 101:40]
|
|
wire _T_272 = io_ap_bne & ne; // @[el2_exu_alu_ctl.scala 101:59]
|
|
wire _T_273 = _T_271 | _T_272; // @[el2_exu_alu_ctl.scala 101:46]
|
|
wire _T_274 = io_ap_blt & lt; // @[el2_exu_alu_ctl.scala 101:85]
|
|
wire _T_275 = _T_273 | _T_274; // @[el2_exu_alu_ctl.scala 101:72]
|
|
wire _T_276 = io_ap_bge & ge; // @[el2_exu_alu_ctl.scala 101:104]
|
|
wire _T_277 = _T_275 | _T_276; // @[el2_exu_alu_ctl.scala 101:91]
|
|
wire actual_taken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 101:110]
|
|
wire _T_278 = io_valid_in & io_ap_predict_nt; // @[el2_exu_alu_ctl.scala 106:42]
|
|
wire _T_279 = ~actual_taken; // @[el2_exu_alu_ctl.scala 106:63]
|
|
wire _T_280 = _T_278 & _T_279; // @[el2_exu_alu_ctl.scala 106:61]
|
|
wire _T_281 = ~sel_pc; // @[el2_exu_alu_ctl.scala 106:79]
|
|
wire _T_282 = _T_280 & _T_281; // @[el2_exu_alu_ctl.scala 106:77]
|
|
wire _T_283 = io_valid_in & io_ap_predict_t; // @[el2_exu_alu_ctl.scala 106:104]
|
|
wire _T_284 = _T_283 & actual_taken; // @[el2_exu_alu_ctl.scala 106:123]
|
|
wire _T_286 = _T_284 & _T_281; // @[el2_exu_alu_ctl.scala 106:139]
|
|
wire _T_293 = io_ap_predict_t & _T_279; // @[el2_exu_alu_ctl.scala 111:45]
|
|
wire _T_294 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 111:82]
|
|
wire cond_mispredict = _T_293 | _T_294; // @[el2_exu_alu_ctl.scala 111:62]
|
|
wire _T_296 = io_pp_in_bits_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:72]
|
|
wire target_mispredict = io_pp_in_bits_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:49]
|
|
wire _T_297 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 116:42]
|
|
wire _T_298 = _T_297 | target_mispredict; // @[el2_exu_alu_ctl.scala 116:60]
|
|
wire _T_299 = _T_298 & io_valid_in; // @[el2_exu_alu_ctl.scala 116:81]
|
|
wire _T_300 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 116:97]
|
|
wire _T_301 = _T_299 & _T_300; // @[el2_exu_alu_ctl.scala 116:95]
|
|
wire _T_302 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 116:119]
|
|
wire _T_312 = io_pp_in_bits_hist[1] & io_pp_in_bits_hist[0]; // @[el2_exu_alu_ctl.scala 122:44]
|
|
wire _T_314 = ~io_pp_in_bits_hist[0]; // @[el2_exu_alu_ctl.scala 122:73]
|
|
wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:96]
|
|
wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:70]
|
|
wire _T_318 = ~io_pp_in_bits_hist[1]; // @[el2_exu_alu_ctl.scala 123:6]
|
|
wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:29]
|
|
wire _T_322 = io_pp_in_bits_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:72]
|
|
wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:47]
|
|
wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:56]
|
|
wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:95]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
assign io_result_ff = _T_3; // @[el2_exu_alu_ctl.scala 37:16]
|
|
assign io_flush_upper_out = _T_301 & _T_302; // @[el2_exu_alu_ctl.scala 116:26]
|
|
assign io_flush_final_out = _T_301 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 118:26]
|
|
assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22]
|
|
assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12]
|
|
assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26]
|
|
assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30]
|
|
assign io_predict_p_out_bits_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:35]
|
|
assign io_predict_p_out_bits_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:35]
|
|
assign io_predict_p_out_bits_boffset = io_pp_in_bits_boffset; // @[el2_exu_alu_ctl.scala 125:30]
|
|
assign io_predict_p_out_bits_pc4 = io_pp_in_bits_pc4; // @[el2_exu_alu_ctl.scala 125:30]
|
|
assign io_predict_p_out_bits_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:35]
|
|
assign io_predict_p_out_bits_toffset = io_pp_in_bits_toffset; // @[el2_exu_alu_ctl.scala 125:30]
|
|
assign io_predict_p_out_bits_br_error = io_pp_in_bits_br_error; // @[el2_exu_alu_ctl.scala 125:30]
|
|
assign io_predict_p_out_bits_br_start_error = io_pp_in_bits_br_start_error; // @[el2_exu_alu_ctl.scala 125:30]
|
|
assign io_predict_p_out_bits_pcall = io_pp_in_bits_pcall; // @[el2_exu_alu_ctl.scala 125:30]
|
|
assign io_predict_p_out_bits_pret = io_pp_in_bits_pret; // @[el2_exu_alu_ctl.scala 125:30]
|
|
assign io_predict_p_out_bits_pja = io_pp_in_bits_pja; // @[el2_exu_alu_ctl.scala 125:30]
|
|
assign io_predict_p_out_bits_way = io_pp_in_bits_way; // @[el2_exu_alu_ctl.scala 125:30]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = io_enable; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
_T_1 = _RAND_0[30:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_3 = _RAND_1[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_1 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_3 = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1 <= 31'h0;
|
|
end else begin
|
|
_T_1 <= io_pc_in;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_3 <= 32'h0;
|
|
end else begin
|
|
_T_3 <= _T_252 | _T_266;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_exu_mul_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_scan_mode,
|
|
input io_mul_p_valid,
|
|
input io_mul_p_bits_rs1_sign,
|
|
input io_mul_p_bits_rs2_sign,
|
|
input io_mul_p_bits_low,
|
|
input [31:0] io_rs1_in,
|
|
input [31:0] io_rs2_in,
|
|
output [31:0] io_result_x
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [63:0] _RAND_1;
|
|
reg [63:0] _RAND_2;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 528:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 528:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 528:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 528:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 528:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 528:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 528:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 528:23]
|
|
wire _T_1 = io_mul_p_bits_rs1_sign & io_rs1_in[31]; // @[el2_exu_mul_ctl.scala 26:44]
|
|
wire _T_5 = io_mul_p_bits_rs2_sign & io_rs2_in[31]; // @[el2_exu_mul_ctl.scala 27:44]
|
|
reg low_x; // @[el2_lib.scala 514:16]
|
|
reg [32:0] rs1_x; // @[el2_lib.scala 534:16]
|
|
reg [32:0] rs2_x; // @[el2_lib.scala 534:16]
|
|
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 33:20]
|
|
wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 34:29]
|
|
wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 528:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 528:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 34:15]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = io_mul_p_valid; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 530:18]
|
|
assign rvclkhdr_1_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 530:18]
|
|
assign rvclkhdr_2_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
low_x = _RAND_0[0:0];
|
|
_RAND_1 = {2{`RANDOM}};
|
|
rs1_x = _RAND_1[32:0];
|
|
_RAND_2 = {2{`RANDOM}};
|
|
rs2_x = _RAND_2[32:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
low_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
rs1_x = 33'sh0;
|
|
end
|
|
if (reset) begin
|
|
rs2_x = 33'sh0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
low_x <= 1'h0;
|
|
end else begin
|
|
low_x <= io_mul_p_bits_low;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rs1_x <= 33'sh0;
|
|
end else begin
|
|
rs1_x <= {_T_1,io_rs1_in};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rs2_x <= 33'sh0;
|
|
end else begin
|
|
rs2_x <= {_T_5,io_rs2_in};
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_exu_div_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_scan_mode,
|
|
input io_dp_valid,
|
|
input io_dp_bits_unsign,
|
|
input io_dp_bits_rem,
|
|
input [31:0] io_dividend,
|
|
input [31:0] io_divisor,
|
|
input io_cancel,
|
|
output [31:0] io_out,
|
|
output io_finish_dly
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [63:0] _RAND_1;
|
|
reg [63:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [63:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire _T = ~io_cancel; // @[el2_exu_div_ctl.scala 54:30]
|
|
reg valid_ff_x; // @[el2_exu_div_ctl.scala 204:26]
|
|
wire valid_x = valid_ff_x & _T; // @[el2_exu_div_ctl.scala 54:28]
|
|
reg [32:0] q_ff; // @[el2_lib.scala 514:16]
|
|
wire _T_2 = q_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:34]
|
|
reg [32:0] m_ff; // @[el2_lib.scala 514:16]
|
|
wire _T_4 = m_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:57]
|
|
wire _T_5 = _T_2 & _T_4; // @[el2_exu_div_ctl.scala 60:43]
|
|
wire _T_7 = m_ff[31:0] != 32'h0; // @[el2_exu_div_ctl.scala 60:80]
|
|
wire _T_8 = _T_5 & _T_7; // @[el2_exu_div_ctl.scala 60:66]
|
|
reg rem_ff; // @[Reg.scala 27:20]
|
|
wire _T_9 = ~rem_ff; // @[el2_exu_div_ctl.scala 60:91]
|
|
wire _T_10 = _T_8 & _T_9; // @[el2_exu_div_ctl.scala 60:89]
|
|
wire _T_11 = _T_10 & valid_x; // @[el2_exu_div_ctl.scala 60:99]
|
|
wire _T_13 = q_ff[31:0] == 32'h0; // @[el2_exu_div_ctl.scala 61:18]
|
|
wire _T_16 = _T_13 & _T_7; // @[el2_exu_div_ctl.scala 61:27]
|
|
wire _T_18 = _T_16 & _T_9; // @[el2_exu_div_ctl.scala 61:50]
|
|
wire _T_19 = _T_18 & valid_x; // @[el2_exu_div_ctl.scala 61:60]
|
|
wire smallnum_case = _T_11 | _T_19; // @[el2_exu_div_ctl.scala 60:110]
|
|
wire _T_23 = ~m_ff[3]; // @[el2_exu_div_ctl.scala 65:69]
|
|
wire _T_25 = ~m_ff[2]; // @[el2_exu_div_ctl.scala 65:69]
|
|
wire _T_27 = ~m_ff[1]; // @[el2_exu_div_ctl.scala 65:69]
|
|
wire _T_28 = _T_23 & _T_25; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_29 = _T_28 & _T_27; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_30 = q_ff[3] & _T_29; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_37 = q_ff[3] & _T_28; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_39 = ~m_ff[0]; // @[el2_exu_div_ctl.scala 72:32]
|
|
wire _T_40 = _T_37 & _T_39; // @[el2_exu_div_ctl.scala 72:30]
|
|
wire _T_50 = q_ff[2] & _T_29; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_51 = _T_40 | _T_50; // @[el2_exu_div_ctl.scala 72:41]
|
|
wire _T_54 = q_ff[3] & q_ff[2]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_60 = _T_54 & _T_28; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_61 = _T_51 | _T_60; // @[el2_exu_div_ctl.scala 72:73]
|
|
wire _T_68 = q_ff[2] & _T_28; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_71 = _T_68 & _T_39; // @[el2_exu_div_ctl.scala 74:30]
|
|
wire _T_81 = q_ff[1] & _T_29; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_82 = _T_71 | _T_81; // @[el2_exu_div_ctl.scala 74:41]
|
|
wire _T_88 = _T_23 & _T_27; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_89 = q_ff[3] & _T_88; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_92 = _T_89 & _T_39; // @[el2_exu_div_ctl.scala 74:103]
|
|
wire _T_93 = _T_82 | _T_92; // @[el2_exu_div_ctl.scala 74:76]
|
|
wire _T_96 = ~q_ff[2]; // @[el2_exu_div_ctl.scala 64:69]
|
|
wire _T_97 = q_ff[3] & _T_96; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_105 = _T_28 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_106 = _T_105 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_107 = _T_97 & _T_106; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_108 = _T_93 | _T_107; // @[el2_exu_div_ctl.scala 74:114]
|
|
wire _T_110 = ~q_ff[3]; // @[el2_exu_div_ctl.scala 64:69]
|
|
wire _T_113 = _T_110 & q_ff[2]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_114 = _T_113 & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_120 = _T_114 & _T_28; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_121 = _T_108 | _T_120; // @[el2_exu_div_ctl.scala 75:43]
|
|
wire _T_127 = _T_54 & _T_23; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_130 = _T_127 & _T_39; // @[el2_exu_div_ctl.scala 75:104]
|
|
wire _T_131 = _T_121 | _T_130; // @[el2_exu_div_ctl.scala 75:78]
|
|
wire _T_140 = _T_23 & m_ff[2]; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_141 = _T_140 & _T_27; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_142 = _T_54 & _T_141; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_143 = _T_131 | _T_142; // @[el2_exu_div_ctl.scala 75:116]
|
|
wire _T_146 = q_ff[3] & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_152 = _T_146 & _T_88; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_153 = _T_143 | _T_152; // @[el2_exu_div_ctl.scala 76:43]
|
|
wire _T_158 = _T_54 & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_163 = _T_158 & _T_140; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_164 = _T_153 | _T_163; // @[el2_exu_div_ctl.scala 76:77]
|
|
wire _T_168 = q_ff[2] & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_169 = _T_168 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_175 = _T_169 & _T_88; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_181 = _T_97 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_186 = _T_23 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_187 = _T_186 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_188 = _T_181 & _T_187; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_189 = _T_175 | _T_188; // @[el2_exu_div_ctl.scala 78:44]
|
|
wire _T_196 = q_ff[2] & _T_88; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_199 = _T_196 & _T_39; // @[el2_exu_div_ctl.scala 78:111]
|
|
wire _T_200 = _T_189 | _T_199; // @[el2_exu_div_ctl.scala 78:84]
|
|
wire _T_207 = q_ff[1] & _T_28; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_210 = _T_207 & _T_39; // @[el2_exu_div_ctl.scala 79:32]
|
|
wire _T_211 = _T_200 | _T_210; // @[el2_exu_div_ctl.scala 78:126]
|
|
wire _T_221 = q_ff[0] & _T_29; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_222 = _T_211 | _T_221; // @[el2_exu_div_ctl.scala 79:46]
|
|
wire _T_227 = ~q_ff[1]; // @[el2_exu_div_ctl.scala 64:69]
|
|
wire _T_229 = _T_113 & _T_227; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_239 = _T_229 & _T_106; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_240 = _T_222 | _T_239; // @[el2_exu_div_ctl.scala 79:86]
|
|
wire _T_249 = _T_114 & _T_23; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_252 = _T_249 & _T_39; // @[el2_exu_div_ctl.scala 80:35]
|
|
wire _T_253 = _T_240 | _T_252; // @[el2_exu_div_ctl.scala 79:128]
|
|
wire _T_259 = _T_25 & _T_27; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_260 = q_ff[3] & _T_259; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_263 = _T_260 & _T_39; // @[el2_exu_div_ctl.scala 80:74]
|
|
wire _T_264 = _T_253 | _T_263; // @[el2_exu_div_ctl.scala 80:46]
|
|
wire _T_274 = _T_140 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_275 = _T_97 & _T_274; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_276 = _T_264 | _T_275; // @[el2_exu_div_ctl.scala 80:86]
|
|
wire _T_290 = _T_114 & _T_141; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_291 = _T_276 | _T_290; // @[el2_exu_div_ctl.scala 80:128]
|
|
wire _T_297 = _T_113 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_303 = _T_297 & _T_88; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_304 = _T_291 | _T_303; // @[el2_exu_div_ctl.scala 81:46]
|
|
wire _T_311 = _T_97 & _T_227; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_317 = _T_140 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_318 = _T_311 & _T_317; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_319 = _T_304 | _T_318; // @[el2_exu_div_ctl.scala 81:86]
|
|
wire _T_324 = _T_96 & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_325 = _T_324 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_331 = _T_325 & _T_28; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_332 = _T_319 | _T_331; // @[el2_exu_div_ctl.scala 81:128]
|
|
wire _T_338 = _T_54 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_341 = _T_338 & _T_39; // @[el2_exu_div_ctl.scala 82:73]
|
|
wire _T_342 = _T_332 | _T_341; // @[el2_exu_div_ctl.scala 82:46]
|
|
wire _T_350 = _T_114 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_355 = _T_350 & _T_140; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_356 = _T_342 | _T_355; // @[el2_exu_div_ctl.scala 82:86]
|
|
wire _T_363 = m_ff[3] & _T_25; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_364 = _T_54 & _T_363; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_365 = _T_356 | _T_364; // @[el2_exu_div_ctl.scala 82:128]
|
|
wire _T_375 = _T_363 & _T_27; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_376 = _T_146 & _T_375; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_377 = _T_365 | _T_376; // @[el2_exu_div_ctl.scala 83:46]
|
|
wire _T_380 = q_ff[3] & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_386 = _T_380 & _T_259; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_387 = _T_377 | _T_386; // @[el2_exu_div_ctl.scala 83:86]
|
|
wire _T_391 = q_ff[3] & _T_227; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_399 = _T_274 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_400 = _T_391 & _T_399; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_401 = _T_387 | _T_400; // @[el2_exu_div_ctl.scala 83:128]
|
|
wire _T_408 = _T_158 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_411 = _T_408 & _T_39; // @[el2_exu_div_ctl.scala 84:75]
|
|
wire _T_412 = _T_401 | _T_411; // @[el2_exu_div_ctl.scala 84:46]
|
|
wire _T_421 = m_ff[3] & _T_27; // @[el2_exu_div_ctl.scala 65:94]
|
|
wire _T_422 = _T_158 & _T_421; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_423 = _T_412 | _T_422; // @[el2_exu_div_ctl.scala 84:86]
|
|
wire _T_428 = _T_54 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_433 = _T_428 & _T_421; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_434 = _T_423 | _T_433; // @[el2_exu_div_ctl.scala 84:128]
|
|
wire _T_440 = _T_97 & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_445 = _T_440 & _T_186; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_446 = _T_434 | _T_445; // @[el2_exu_div_ctl.scala 85:46]
|
|
wire _T_451 = _T_146 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_454 = _T_451 & _T_25; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_455 = _T_446 | _T_454; // @[el2_exu_div_ctl.scala 85:86]
|
|
wire _T_462 = _T_158 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
|
wire _T_464 = _T_462 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_465 = _T_455 | _T_464; // @[el2_exu_div_ctl.scala 85:128]
|
|
wire _T_471 = _T_146 & _T_25; // @[el2_exu_div_ctl.scala 66:10]
|
|
wire _T_474 = _T_471 & _T_39; // @[el2_exu_div_ctl.scala 86:72]
|
|
wire _T_475 = _T_465 | _T_474; // @[el2_exu_div_ctl.scala 86:46]
|
|
wire [1:0] _T_476 = {_T_164,_T_475}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_477 = {_T_30,_T_61}; // @[Cat.scala 29:58]
|
|
reg sign_ff; // @[Reg.scala 27:20]
|
|
wire _T_479 = sign_ff & q_ff[31]; // @[el2_exu_div_ctl.scala 96:34]
|
|
wire [32:0] short_dividend = {_T_479,q_ff[31:0]}; // @[Cat.scala 29:58]
|
|
wire _T_484 = ~short_dividend[32]; // @[el2_exu_div_ctl.scala 101:7]
|
|
wire _T_487 = short_dividend[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 101:60]
|
|
wire _T_492 = short_dividend[31:23] != 9'h1ff; // @[el2_exu_div_ctl.scala 102:59]
|
|
wire _T_493 = _T_484 & _T_487; // @[Mux.scala 27:72]
|
|
wire _T_494 = short_dividend[32] & _T_492; // @[Mux.scala 27:72]
|
|
wire _T_495 = _T_493 | _T_494; // @[Mux.scala 27:72]
|
|
wire _T_502 = short_dividend[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 105:60]
|
|
wire _T_507 = short_dividend[22:15] != 8'hff; // @[el2_exu_div_ctl.scala 106:59]
|
|
wire _T_508 = _T_484 & _T_502; // @[Mux.scala 27:72]
|
|
wire _T_509 = short_dividend[32] & _T_507; // @[Mux.scala 27:72]
|
|
wire _T_510 = _T_508 | _T_509; // @[Mux.scala 27:72]
|
|
wire _T_517 = short_dividend[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 109:59]
|
|
wire _T_522 = short_dividend[14:7] != 8'hff; // @[el2_exu_div_ctl.scala 110:58]
|
|
wire _T_523 = _T_484 & _T_517; // @[Mux.scala 27:72]
|
|
wire _T_524 = short_dividend[32] & _T_522; // @[Mux.scala 27:72]
|
|
wire _T_525 = _T_523 | _T_524; // @[Mux.scala 27:72]
|
|
wire [2:0] a_cls = {_T_495,_T_510,_T_525}; // @[Cat.scala 29:58]
|
|
wire _T_530 = ~m_ff[32]; // @[el2_exu_div_ctl.scala 115:7]
|
|
wire _T_533 = m_ff[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 115:40]
|
|
wire _T_538 = m_ff[31:24] != 8'hff; // @[el2_exu_div_ctl.scala 116:39]
|
|
wire _T_539 = _T_530 & _T_533; // @[Mux.scala 27:72]
|
|
wire _T_540 = m_ff[32] & _T_538; // @[Mux.scala 27:72]
|
|
wire _T_541 = _T_539 | _T_540; // @[Mux.scala 27:72]
|
|
wire _T_548 = m_ff[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 119:40]
|
|
wire _T_553 = m_ff[23:16] != 8'hff; // @[el2_exu_div_ctl.scala 120:39]
|
|
wire _T_554 = _T_530 & _T_548; // @[Mux.scala 27:72]
|
|
wire _T_555 = m_ff[32] & _T_553; // @[Mux.scala 27:72]
|
|
wire _T_556 = _T_554 | _T_555; // @[Mux.scala 27:72]
|
|
wire _T_563 = m_ff[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 123:39]
|
|
wire _T_568 = m_ff[15:8] != 8'hff; // @[el2_exu_div_ctl.scala 124:38]
|
|
wire _T_569 = _T_530 & _T_563; // @[Mux.scala 27:72]
|
|
wire _T_570 = m_ff[32] & _T_568; // @[Mux.scala 27:72]
|
|
wire _T_571 = _T_569 | _T_570; // @[Mux.scala 27:72]
|
|
wire [2:0] b_cls = {_T_541,_T_556,_T_571}; // @[Cat.scala 29:58]
|
|
wire _T_575 = a_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 128:19]
|
|
wire _T_578 = _T_575 & b_cls[2]; // @[el2_exu_div_ctl.scala 128:34]
|
|
wire _T_580 = a_cls == 3'h1; // @[el2_exu_div_ctl.scala 129:21]
|
|
wire _T_583 = _T_580 & b_cls[2]; // @[el2_exu_div_ctl.scala 129:36]
|
|
wire _T_584 = _T_578 | _T_583; // @[el2_exu_div_ctl.scala 128:65]
|
|
wire _T_586 = a_cls == 3'h0; // @[el2_exu_div_ctl.scala 130:21]
|
|
wire _T_589 = _T_586 & b_cls[2]; // @[el2_exu_div_ctl.scala 130:36]
|
|
wire _T_590 = _T_584 | _T_589; // @[el2_exu_div_ctl.scala 129:67]
|
|
wire _T_594 = b_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 131:50]
|
|
wire _T_595 = _T_580 & _T_594; // @[el2_exu_div_ctl.scala 131:36]
|
|
wire _T_596 = _T_590 | _T_595; // @[el2_exu_div_ctl.scala 130:67]
|
|
wire _T_601 = _T_586 & _T_594; // @[el2_exu_div_ctl.scala 132:36]
|
|
wire _T_602 = _T_596 | _T_601; // @[el2_exu_div_ctl.scala 131:67]
|
|
wire _T_606 = b_cls == 3'h1; // @[el2_exu_div_ctl.scala 133:50]
|
|
wire _T_607 = _T_586 & _T_606; // @[el2_exu_div_ctl.scala 133:36]
|
|
wire _T_608 = _T_602 | _T_607; // @[el2_exu_div_ctl.scala 132:67]
|
|
wire _T_613 = a_cls[2] & b_cls[2]; // @[el2_exu_div_ctl.scala 135:34]
|
|
wire _T_618 = _T_575 & _T_594; // @[el2_exu_div_ctl.scala 136:36]
|
|
wire _T_619 = _T_613 | _T_618; // @[el2_exu_div_ctl.scala 135:65]
|
|
wire _T_624 = _T_580 & _T_606; // @[el2_exu_div_ctl.scala 137:36]
|
|
wire _T_625 = _T_619 | _T_624; // @[el2_exu_div_ctl.scala 136:67]
|
|
wire _T_629 = b_cls == 3'h0; // @[el2_exu_div_ctl.scala 138:50]
|
|
wire _T_630 = _T_586 & _T_629; // @[el2_exu_div_ctl.scala 138:36]
|
|
wire _T_631 = _T_625 | _T_630; // @[el2_exu_div_ctl.scala 137:67]
|
|
wire _T_636 = a_cls[2] & _T_594; // @[el2_exu_div_ctl.scala 140:34]
|
|
wire _T_641 = _T_575 & _T_606; // @[el2_exu_div_ctl.scala 141:36]
|
|
wire _T_642 = _T_636 | _T_641; // @[el2_exu_div_ctl.scala 140:65]
|
|
wire _T_647 = _T_580 & _T_629; // @[el2_exu_div_ctl.scala 142:36]
|
|
wire _T_648 = _T_642 | _T_647; // @[el2_exu_div_ctl.scala 141:67]
|
|
wire _T_653 = a_cls[2] & _T_606; // @[el2_exu_div_ctl.scala 144:34]
|
|
wire _T_658 = _T_575 & _T_629; // @[el2_exu_div_ctl.scala 145:36]
|
|
wire _T_659 = _T_653 | _T_658; // @[el2_exu_div_ctl.scala 144:65]
|
|
wire [3:0] shortq_raw = {_T_608,_T_631,_T_648,_T_659}; // @[Cat.scala 29:58]
|
|
wire _T_664 = valid_ff_x & _T_7; // @[el2_exu_div_ctl.scala 148:35]
|
|
wire _T_665 = shortq_raw != 4'h0; // @[el2_exu_div_ctl.scala 148:78]
|
|
wire shortq_enable = _T_664 & _T_665; // @[el2_exu_div_ctl.scala 148:64]
|
|
wire [3:0] _T_667 = shortq_enable ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
reg [3:0] shortq_shift_xx; // @[el2_exu_div_ctl.scala 215:31]
|
|
wire [4:0] _T_676 = shortq_shift_xx[3] ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_677 = shortq_shift_xx[2] ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_678 = shortq_shift_xx[1] ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_679 = shortq_shift_xx[0] ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_680 = _T_676 | _T_677; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_681 = _T_680 | _T_678; // @[Mux.scala 27:72]
|
|
wire [4:0] _GEN_4 = {{1'd0}, _T_679}; // @[Mux.scala 27:72]
|
|
wire [4:0] shortq_shift_ff = _T_681 | _GEN_4; // @[Mux.scala 27:72]
|
|
reg [5:0] count; // @[el2_exu_div_ctl.scala 207:21]
|
|
wire _T_684 = count == 6'h20; // @[el2_exu_div_ctl.scala 159:55]
|
|
wire _T_685 = count == 6'h21; // @[el2_exu_div_ctl.scala 159:76]
|
|
wire _T_686 = _T_9 ? _T_684 : _T_685; // @[el2_exu_div_ctl.scala 159:39]
|
|
wire finish = smallnum_case | _T_686; // @[el2_exu_div_ctl.scala 159:34]
|
|
reg run_state; // @[el2_exu_div_ctl.scala 206:25]
|
|
wire _T_687 = io_dp_valid | run_state; // @[el2_exu_div_ctl.scala 160:32]
|
|
wire _T_688 = _T_687 | finish; // @[el2_exu_div_ctl.scala 160:44]
|
|
reg finish_ff; // @[el2_exu_div_ctl.scala 205:25]
|
|
wire _T_690 = ~finish; // @[el2_exu_div_ctl.scala 161:48]
|
|
wire _T_691 = _T_687 & _T_690; // @[el2_exu_div_ctl.scala 161:46]
|
|
wire _T_694 = run_state & _T_690; // @[el2_exu_div_ctl.scala 162:35]
|
|
wire _T_696 = _T_694 & _T; // @[el2_exu_div_ctl.scala 162:45]
|
|
wire _T_697 = ~shortq_enable; // @[el2_exu_div_ctl.scala 162:60]
|
|
wire _T_698 = _T_696 & _T_697; // @[el2_exu_div_ctl.scala 162:58]
|
|
wire [5:0] _T_700 = _T_698 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
|
|
wire [5:0] _T_701 = {1'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
|
|
wire [5:0] _T_703 = count + _T_701; // @[el2_exu_div_ctl.scala 162:86]
|
|
wire [5:0] _T_705 = _T_703 + 6'h1; // @[el2_exu_div_ctl.scala 162:113]
|
|
wire _T_709 = ~io_dp_bits_unsign; // @[el2_exu_div_ctl.scala 166:20]
|
|
wire _T_710 = io_divisor != 32'h0; // @[el2_exu_div_ctl.scala 166:53]
|
|
wire sign_eff = _T_709 & _T_710; // @[el2_exu_div_ctl.scala 166:39]
|
|
wire _T_711 = ~run_state; // @[el2_exu_div_ctl.scala 170:6]
|
|
wire [32:0] _T_713 = {1'h0,io_dividend}; // @[Cat.scala 29:58]
|
|
reg shortq_enable_ff; // @[el2_exu_div_ctl.scala 214:32]
|
|
wire _T_714 = valid_ff_x | shortq_enable_ff; // @[el2_exu_div_ctl.scala 171:30]
|
|
wire _T_715 = run_state & _T_714; // @[el2_exu_div_ctl.scala 171:16]
|
|
reg dividend_neg_ff; // @[Reg.scala 27:20]
|
|
wire _T_738 = sign_ff & dividend_neg_ff; // @[el2_exu_div_ctl.scala 175:32]
|
|
wire _T_923 = |q_ff[30:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_925 = ~q_ff[31]; // @[el2_lib.scala 543:40]
|
|
wire _T_927 = _T_923 ? _T_925 : q_ff[31]; // @[el2_lib.scala 543:23]
|
|
wire _T_917 = |q_ff[29:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_919 = ~q_ff[30]; // @[el2_lib.scala 543:40]
|
|
wire _T_921 = _T_917 ? _T_919 : q_ff[30]; // @[el2_lib.scala 543:23]
|
|
wire _T_911 = |q_ff[28:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_913 = ~q_ff[29]; // @[el2_lib.scala 543:40]
|
|
wire _T_915 = _T_911 ? _T_913 : q_ff[29]; // @[el2_lib.scala 543:23]
|
|
wire _T_905 = |q_ff[27:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_907 = ~q_ff[28]; // @[el2_lib.scala 543:40]
|
|
wire _T_909 = _T_905 ? _T_907 : q_ff[28]; // @[el2_lib.scala 543:23]
|
|
wire _T_899 = |q_ff[26:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_901 = ~q_ff[27]; // @[el2_lib.scala 543:40]
|
|
wire _T_903 = _T_899 ? _T_901 : q_ff[27]; // @[el2_lib.scala 543:23]
|
|
wire _T_893 = |q_ff[25:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_895 = ~q_ff[26]; // @[el2_lib.scala 543:40]
|
|
wire _T_897 = _T_893 ? _T_895 : q_ff[26]; // @[el2_lib.scala 543:23]
|
|
wire _T_887 = |q_ff[24:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_889 = ~q_ff[25]; // @[el2_lib.scala 543:40]
|
|
wire _T_891 = _T_887 ? _T_889 : q_ff[25]; // @[el2_lib.scala 543:23]
|
|
wire _T_881 = |q_ff[23:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_883 = ~q_ff[24]; // @[el2_lib.scala 543:40]
|
|
wire _T_885 = _T_881 ? _T_883 : q_ff[24]; // @[el2_lib.scala 543:23]
|
|
wire _T_875 = |q_ff[22:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_877 = ~q_ff[23]; // @[el2_lib.scala 543:40]
|
|
wire _T_879 = _T_875 ? _T_877 : q_ff[23]; // @[el2_lib.scala 543:23]
|
|
wire _T_869 = |q_ff[21:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_871 = ~q_ff[22]; // @[el2_lib.scala 543:40]
|
|
wire _T_873 = _T_869 ? _T_871 : q_ff[22]; // @[el2_lib.scala 543:23]
|
|
wire _T_863 = |q_ff[20:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_865 = ~q_ff[21]; // @[el2_lib.scala 543:40]
|
|
wire _T_867 = _T_863 ? _T_865 : q_ff[21]; // @[el2_lib.scala 543:23]
|
|
wire _T_857 = |q_ff[19:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_859 = ~q_ff[20]; // @[el2_lib.scala 543:40]
|
|
wire _T_861 = _T_857 ? _T_859 : q_ff[20]; // @[el2_lib.scala 543:23]
|
|
wire _T_851 = |q_ff[18:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_853 = ~q_ff[19]; // @[el2_lib.scala 543:40]
|
|
wire _T_855 = _T_851 ? _T_853 : q_ff[19]; // @[el2_lib.scala 543:23]
|
|
wire _T_845 = |q_ff[17:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_847 = ~q_ff[18]; // @[el2_lib.scala 543:40]
|
|
wire _T_849 = _T_845 ? _T_847 : q_ff[18]; // @[el2_lib.scala 543:23]
|
|
wire _T_839 = |q_ff[16:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_841 = ~q_ff[17]; // @[el2_lib.scala 543:40]
|
|
wire _T_843 = _T_839 ? _T_841 : q_ff[17]; // @[el2_lib.scala 543:23]
|
|
wire _T_833 = |q_ff[15:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_835 = ~q_ff[16]; // @[el2_lib.scala 543:40]
|
|
wire _T_837 = _T_833 ? _T_835 : q_ff[16]; // @[el2_lib.scala 543:23]
|
|
wire [7:0] _T_948 = {_T_879,_T_873,_T_867,_T_861,_T_855,_T_849,_T_843,_T_837}; // @[el2_lib.scala 545:14]
|
|
wire _T_827 = |q_ff[14:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_829 = ~q_ff[15]; // @[el2_lib.scala 543:40]
|
|
wire _T_831 = _T_827 ? _T_829 : q_ff[15]; // @[el2_lib.scala 543:23]
|
|
wire _T_821 = |q_ff[13:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_823 = ~q_ff[14]; // @[el2_lib.scala 543:40]
|
|
wire _T_825 = _T_821 ? _T_823 : q_ff[14]; // @[el2_lib.scala 543:23]
|
|
wire _T_815 = |q_ff[12:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_817 = ~q_ff[13]; // @[el2_lib.scala 543:40]
|
|
wire _T_819 = _T_815 ? _T_817 : q_ff[13]; // @[el2_lib.scala 543:23]
|
|
wire _T_809 = |q_ff[11:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_811 = ~q_ff[12]; // @[el2_lib.scala 543:40]
|
|
wire _T_813 = _T_809 ? _T_811 : q_ff[12]; // @[el2_lib.scala 543:23]
|
|
wire _T_803 = |q_ff[10:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_805 = ~q_ff[11]; // @[el2_lib.scala 543:40]
|
|
wire _T_807 = _T_803 ? _T_805 : q_ff[11]; // @[el2_lib.scala 543:23]
|
|
wire _T_797 = |q_ff[9:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_799 = ~q_ff[10]; // @[el2_lib.scala 543:40]
|
|
wire _T_801 = _T_797 ? _T_799 : q_ff[10]; // @[el2_lib.scala 543:23]
|
|
wire _T_791 = |q_ff[8:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_793 = ~q_ff[9]; // @[el2_lib.scala 543:40]
|
|
wire _T_795 = _T_791 ? _T_793 : q_ff[9]; // @[el2_lib.scala 543:23]
|
|
wire _T_785 = |q_ff[7:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_787 = ~q_ff[8]; // @[el2_lib.scala 543:40]
|
|
wire _T_789 = _T_785 ? _T_787 : q_ff[8]; // @[el2_lib.scala 543:23]
|
|
wire _T_779 = |q_ff[6:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_781 = ~q_ff[7]; // @[el2_lib.scala 543:40]
|
|
wire _T_783 = _T_779 ? _T_781 : q_ff[7]; // @[el2_lib.scala 543:23]
|
|
wire _T_773 = |q_ff[5:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_775 = ~q_ff[6]; // @[el2_lib.scala 543:40]
|
|
wire _T_777 = _T_773 ? _T_775 : q_ff[6]; // @[el2_lib.scala 543:23]
|
|
wire _T_767 = |q_ff[4:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_769 = ~q_ff[5]; // @[el2_lib.scala 543:40]
|
|
wire _T_771 = _T_767 ? _T_769 : q_ff[5]; // @[el2_lib.scala 543:23]
|
|
wire _T_761 = |q_ff[3:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_763 = ~q_ff[4]; // @[el2_lib.scala 543:40]
|
|
wire _T_765 = _T_761 ? _T_763 : q_ff[4]; // @[el2_lib.scala 543:23]
|
|
wire _T_755 = |q_ff[2:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_757 = ~q_ff[3]; // @[el2_lib.scala 543:40]
|
|
wire _T_759 = _T_755 ? _T_757 : q_ff[3]; // @[el2_lib.scala 543:23]
|
|
wire _T_749 = |q_ff[1:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_751 = ~q_ff[2]; // @[el2_lib.scala 543:40]
|
|
wire _T_753 = _T_749 ? _T_751 : q_ff[2]; // @[el2_lib.scala 543:23]
|
|
wire _T_743 = |q_ff[0]; // @[el2_lib.scala 543:35]
|
|
wire _T_745 = ~q_ff[1]; // @[el2_lib.scala 543:40]
|
|
wire _T_747 = _T_743 ? _T_745 : q_ff[1]; // @[el2_lib.scala 543:23]
|
|
wire [6:0] _T_933 = {_T_783,_T_777,_T_771,_T_765,_T_759,_T_753,_T_747}; // @[el2_lib.scala 545:14]
|
|
wire [14:0] _T_941 = {_T_831,_T_825,_T_819,_T_813,_T_807,_T_801,_T_795,_T_789,_T_933}; // @[el2_lib.scala 545:14]
|
|
wire [30:0] _T_957 = {_T_927,_T_921,_T_915,_T_909,_T_903,_T_897,_T_891,_T_885,_T_948,_T_941}; // @[el2_lib.scala 545:14]
|
|
wire [31:0] _T_959 = {_T_957,q_ff[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] dividend_eff = _T_738 ? _T_959 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 175:22]
|
|
wire [32:0] _T_995 = run_state ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_1007 = _T_685 & rem_ff; // @[el2_exu_div_ctl.scala 191:41]
|
|
reg [32:0] a_ff; // @[el2_lib.scala 514:16]
|
|
wire rem_correct = _T_1007 & a_ff[32]; // @[el2_exu_div_ctl.scala 191:50]
|
|
wire [32:0] _T_980 = rem_correct ? a_ff : 33'h0; // @[Mux.scala 27:72]
|
|
wire _T_968 = ~rem_correct; // @[el2_exu_div_ctl.scala 182:6]
|
|
wire _T_969 = ~shortq_enable_ff; // @[el2_exu_div_ctl.scala 182:21]
|
|
wire _T_970 = _T_968 & _T_969; // @[el2_exu_div_ctl.scala 182:19]
|
|
wire [32:0] _T_974 = {a_ff[31:0],q_ff[32]}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_981 = _T_970 ? _T_974 : 33'h0; // @[Mux.scala 27:72]
|
|
wire [32:0] _T_983 = _T_980 | _T_981; // @[Mux.scala 27:72]
|
|
wire _T_976 = _T_968 & shortq_enable_ff; // @[el2_exu_div_ctl.scala 183:19]
|
|
wire [55:0] _T_965 = {24'h0,dividend_eff}; // @[Cat.scala 29:58]
|
|
wire [86:0] _GEN_5 = {{31'd0}, _T_965}; // @[el2_exu_div_ctl.scala 179:47]
|
|
wire [86:0] _T_966 = _GEN_5 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 179:47]
|
|
wire [55:0] a_eff_shift = _T_966[55:0]; // @[el2_exu_div_ctl.scala 179:15]
|
|
wire [32:0] _T_979 = {9'h0,a_eff_shift[55:32]}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_982 = _T_976 ? _T_979 : 33'h0; // @[Mux.scala 27:72]
|
|
wire [32:0] a_eff = _T_983 | _T_982; // @[Mux.scala 27:72]
|
|
wire [32:0] a_shift = _T_995 & a_eff; // @[el2_exu_div_ctl.scala 186:33]
|
|
wire _T_1004 = a_ff[32] | rem_correct; // @[el2_exu_div_ctl.scala 190:21]
|
|
reg divisor_neg_ff; // @[Reg.scala 27:20]
|
|
wire m_already_comp = divisor_neg_ff & sign_ff; // @[el2_exu_div_ctl.scala 188:48]
|
|
wire add = _T_1004 ^ m_already_comp; // @[el2_exu_div_ctl.scala 190:36]
|
|
wire [32:0] _T_963 = ~m_ff; // @[el2_exu_div_ctl.scala 178:35]
|
|
wire [32:0] m_eff = add ? m_ff : _T_963; // @[el2_exu_div_ctl.scala 178:15]
|
|
wire [32:0] _T_997 = a_shift + m_eff; // @[el2_exu_div_ctl.scala 187:41]
|
|
wire _T_998 = ~add; // @[el2_exu_div_ctl.scala 187:65]
|
|
wire [32:0] _T_999 = {32'h0,_T_998}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_1001 = _T_997 + _T_999; // @[el2_exu_div_ctl.scala 187:49]
|
|
wire [32:0] a_in = _T_995 & _T_1001; // @[el2_exu_div_ctl.scala 187:30]
|
|
wire _T_719 = ~a_in[32]; // @[el2_exu_div_ctl.scala 171:85]
|
|
wire [32:0] _T_720 = {dividend_eff,_T_719}; // @[Cat.scala 29:58]
|
|
wire [63:0] _GEN_6 = {{31'd0}, _T_720}; // @[el2_exu_div_ctl.scala 171:96]
|
|
wire [63:0] _T_721 = _GEN_6 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 171:96]
|
|
wire _T_723 = ~_T_714; // @[el2_exu_div_ctl.scala 172:18]
|
|
wire _T_724 = run_state & _T_723; // @[el2_exu_div_ctl.scala 172:16]
|
|
wire [32:0] _T_729 = {q_ff[31:0],_T_719}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_730 = _T_711 ? _T_713 : 33'h0; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_731 = _T_715 ? _T_721 : 64'h0; // @[Mux.scala 27:72]
|
|
wire [32:0] _T_732 = _T_724 ? _T_729 : 33'h0; // @[Mux.scala 27:72]
|
|
wire [63:0] _GEN_7 = {{31'd0}, _T_730}; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_733 = _GEN_7 | _T_731; // @[Mux.scala 27:72]
|
|
wire [63:0] _GEN_8 = {{31'd0}, _T_732}; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_734 = _T_733 | _GEN_8; // @[Mux.scala 27:72]
|
|
wire _T_737 = run_state & _T_697; // @[el2_exu_div_ctl.scala 174:48]
|
|
wire _T_988 = count != 6'h21; // @[el2_exu_div_ctl.scala 185:73]
|
|
wire _T_989 = _T_737 & _T_988; // @[el2_exu_div_ctl.scala 185:64]
|
|
wire _T_990 = io_dp_valid | _T_989; // @[el2_exu_div_ctl.scala 185:34]
|
|
wire _T_1010 = dividend_neg_ff ^ divisor_neg_ff; // @[el2_exu_div_ctl.scala 192:50]
|
|
wire _T_1011 = sign_ff & _T_1010; // @[el2_exu_div_ctl.scala 192:31]
|
|
wire [31:0] q_ff_eff = _T_1011 ? _T_959 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 192:21]
|
|
wire _T_1239 = |a_ff[0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1241 = ~a_ff[1]; // @[el2_lib.scala 543:40]
|
|
wire _T_1243 = _T_1239 ? _T_1241 : a_ff[1]; // @[el2_lib.scala 543:23]
|
|
wire _T_1245 = |a_ff[1:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1247 = ~a_ff[2]; // @[el2_lib.scala 543:40]
|
|
wire _T_1249 = _T_1245 ? _T_1247 : a_ff[2]; // @[el2_lib.scala 543:23]
|
|
wire _T_1251 = |a_ff[2:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1253 = ~a_ff[3]; // @[el2_lib.scala 543:40]
|
|
wire _T_1255 = _T_1251 ? _T_1253 : a_ff[3]; // @[el2_lib.scala 543:23]
|
|
wire _T_1257 = |a_ff[3:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1259 = ~a_ff[4]; // @[el2_lib.scala 543:40]
|
|
wire _T_1261 = _T_1257 ? _T_1259 : a_ff[4]; // @[el2_lib.scala 543:23]
|
|
wire _T_1263 = |a_ff[4:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1265 = ~a_ff[5]; // @[el2_lib.scala 543:40]
|
|
wire _T_1267 = _T_1263 ? _T_1265 : a_ff[5]; // @[el2_lib.scala 543:23]
|
|
wire _T_1269 = |a_ff[5:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1271 = ~a_ff[6]; // @[el2_lib.scala 543:40]
|
|
wire _T_1273 = _T_1269 ? _T_1271 : a_ff[6]; // @[el2_lib.scala 543:23]
|
|
wire _T_1275 = |a_ff[6:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1277 = ~a_ff[7]; // @[el2_lib.scala 543:40]
|
|
wire _T_1279 = _T_1275 ? _T_1277 : a_ff[7]; // @[el2_lib.scala 543:23]
|
|
wire _T_1281 = |a_ff[7:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1283 = ~a_ff[8]; // @[el2_lib.scala 543:40]
|
|
wire _T_1285 = _T_1281 ? _T_1283 : a_ff[8]; // @[el2_lib.scala 543:23]
|
|
wire _T_1287 = |a_ff[8:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1289 = ~a_ff[9]; // @[el2_lib.scala 543:40]
|
|
wire _T_1291 = _T_1287 ? _T_1289 : a_ff[9]; // @[el2_lib.scala 543:23]
|
|
wire _T_1293 = |a_ff[9:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1295 = ~a_ff[10]; // @[el2_lib.scala 543:40]
|
|
wire _T_1297 = _T_1293 ? _T_1295 : a_ff[10]; // @[el2_lib.scala 543:23]
|
|
wire _T_1299 = |a_ff[10:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1301 = ~a_ff[11]; // @[el2_lib.scala 543:40]
|
|
wire _T_1303 = _T_1299 ? _T_1301 : a_ff[11]; // @[el2_lib.scala 543:23]
|
|
wire _T_1305 = |a_ff[11:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1307 = ~a_ff[12]; // @[el2_lib.scala 543:40]
|
|
wire _T_1309 = _T_1305 ? _T_1307 : a_ff[12]; // @[el2_lib.scala 543:23]
|
|
wire _T_1311 = |a_ff[12:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1313 = ~a_ff[13]; // @[el2_lib.scala 543:40]
|
|
wire _T_1315 = _T_1311 ? _T_1313 : a_ff[13]; // @[el2_lib.scala 543:23]
|
|
wire _T_1317 = |a_ff[13:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1319 = ~a_ff[14]; // @[el2_lib.scala 543:40]
|
|
wire _T_1321 = _T_1317 ? _T_1319 : a_ff[14]; // @[el2_lib.scala 543:23]
|
|
wire _T_1323 = |a_ff[14:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1325 = ~a_ff[15]; // @[el2_lib.scala 543:40]
|
|
wire _T_1327 = _T_1323 ? _T_1325 : a_ff[15]; // @[el2_lib.scala 543:23]
|
|
wire _T_1329 = |a_ff[15:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1331 = ~a_ff[16]; // @[el2_lib.scala 543:40]
|
|
wire _T_1333 = _T_1329 ? _T_1331 : a_ff[16]; // @[el2_lib.scala 543:23]
|
|
wire _T_1335 = |a_ff[16:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1337 = ~a_ff[17]; // @[el2_lib.scala 543:40]
|
|
wire _T_1339 = _T_1335 ? _T_1337 : a_ff[17]; // @[el2_lib.scala 543:23]
|
|
wire _T_1341 = |a_ff[17:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1343 = ~a_ff[18]; // @[el2_lib.scala 543:40]
|
|
wire _T_1345 = _T_1341 ? _T_1343 : a_ff[18]; // @[el2_lib.scala 543:23]
|
|
wire _T_1347 = |a_ff[18:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1349 = ~a_ff[19]; // @[el2_lib.scala 543:40]
|
|
wire _T_1351 = _T_1347 ? _T_1349 : a_ff[19]; // @[el2_lib.scala 543:23]
|
|
wire _T_1353 = |a_ff[19:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1355 = ~a_ff[20]; // @[el2_lib.scala 543:40]
|
|
wire _T_1357 = _T_1353 ? _T_1355 : a_ff[20]; // @[el2_lib.scala 543:23]
|
|
wire _T_1359 = |a_ff[20:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1361 = ~a_ff[21]; // @[el2_lib.scala 543:40]
|
|
wire _T_1363 = _T_1359 ? _T_1361 : a_ff[21]; // @[el2_lib.scala 543:23]
|
|
wire _T_1365 = |a_ff[21:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1367 = ~a_ff[22]; // @[el2_lib.scala 543:40]
|
|
wire _T_1369 = _T_1365 ? _T_1367 : a_ff[22]; // @[el2_lib.scala 543:23]
|
|
wire _T_1371 = |a_ff[22:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1373 = ~a_ff[23]; // @[el2_lib.scala 543:40]
|
|
wire _T_1375 = _T_1371 ? _T_1373 : a_ff[23]; // @[el2_lib.scala 543:23]
|
|
wire _T_1377 = |a_ff[23:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1379 = ~a_ff[24]; // @[el2_lib.scala 543:40]
|
|
wire _T_1381 = _T_1377 ? _T_1379 : a_ff[24]; // @[el2_lib.scala 543:23]
|
|
wire _T_1383 = |a_ff[24:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1385 = ~a_ff[25]; // @[el2_lib.scala 543:40]
|
|
wire _T_1387 = _T_1383 ? _T_1385 : a_ff[25]; // @[el2_lib.scala 543:23]
|
|
wire _T_1389 = |a_ff[25:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1391 = ~a_ff[26]; // @[el2_lib.scala 543:40]
|
|
wire _T_1393 = _T_1389 ? _T_1391 : a_ff[26]; // @[el2_lib.scala 543:23]
|
|
wire _T_1395 = |a_ff[26:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1397 = ~a_ff[27]; // @[el2_lib.scala 543:40]
|
|
wire _T_1399 = _T_1395 ? _T_1397 : a_ff[27]; // @[el2_lib.scala 543:23]
|
|
wire _T_1401 = |a_ff[27:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1403 = ~a_ff[28]; // @[el2_lib.scala 543:40]
|
|
wire _T_1405 = _T_1401 ? _T_1403 : a_ff[28]; // @[el2_lib.scala 543:23]
|
|
wire _T_1407 = |a_ff[28:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1409 = ~a_ff[29]; // @[el2_lib.scala 543:40]
|
|
wire _T_1411 = _T_1407 ? _T_1409 : a_ff[29]; // @[el2_lib.scala 543:23]
|
|
wire _T_1413 = |a_ff[29:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1415 = ~a_ff[30]; // @[el2_lib.scala 543:40]
|
|
wire _T_1417 = _T_1413 ? _T_1415 : a_ff[30]; // @[el2_lib.scala 543:23]
|
|
wire _T_1419 = |a_ff[30:0]; // @[el2_lib.scala 543:35]
|
|
wire _T_1421 = ~a_ff[31]; // @[el2_lib.scala 543:40]
|
|
wire _T_1423 = _T_1419 ? _T_1421 : a_ff[31]; // @[el2_lib.scala 543:23]
|
|
wire [6:0] _T_1429 = {_T_1279,_T_1273,_T_1267,_T_1261,_T_1255,_T_1249,_T_1243}; // @[el2_lib.scala 545:14]
|
|
wire [14:0] _T_1437 = {_T_1327,_T_1321,_T_1315,_T_1309,_T_1303,_T_1297,_T_1291,_T_1285,_T_1429}; // @[el2_lib.scala 545:14]
|
|
wire [7:0] _T_1444 = {_T_1375,_T_1369,_T_1363,_T_1357,_T_1351,_T_1345,_T_1339,_T_1333}; // @[el2_lib.scala 545:14]
|
|
wire [30:0] _T_1453 = {_T_1423,_T_1417,_T_1411,_T_1405,_T_1399,_T_1393,_T_1387,_T_1381,_T_1444,_T_1437}; // @[el2_lib.scala 545:14]
|
|
wire [31:0] _T_1455 = {_T_1453,a_ff[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] a_ff_eff = _T_738 ? _T_1455 : a_ff[31:0]; // @[el2_exu_div_ctl.scala 193:21]
|
|
reg smallnum_case_ff; // @[el2_exu_div_ctl.scala 212:32]
|
|
reg [3:0] smallnum_ff; // @[el2_exu_div_ctl.scala 213:27]
|
|
wire [31:0] _T_1458 = {28'h0,smallnum_ff}; // @[Cat.scala 29:58]
|
|
wire _T_1460 = ~smallnum_case_ff; // @[el2_exu_div_ctl.scala 198:6]
|
|
wire _T_1462 = _T_1460 & _T_9; // @[el2_exu_div_ctl.scala 198:24]
|
|
wire [31:0] _T_1464 = smallnum_case_ff ? _T_1458 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1465 = rem_ff ? a_ff_eff : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1466 = _T_1462 ? q_ff_eff : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1467 = _T_1464 | _T_1465; // @[Mux.scala 27:72]
|
|
wire _T_1499 = _T_709 & io_divisor[31]; // @[el2_exu_div_ctl.scala 219:41]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
assign io_out = _T_1467 | _T_1466; // @[el2_exu_div_ctl.scala 50:10 el2_exu_div_ctl.scala 195:10]
|
|
assign io_finish_dly = finish_ff & _T; // @[el2_exu_div_ctl.scala 51:17 el2_exu_div_ctl.scala 165:18]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_io_en = _T_688 | finish_ff; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = io_dp_valid | _T_737; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_2_io_en = _T_990 | rem_correct; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = io_dp_valid; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
valid_ff_x = _RAND_0[0:0];
|
|
_RAND_1 = {2{`RANDOM}};
|
|
q_ff = _RAND_1[32:0];
|
|
_RAND_2 = {2{`RANDOM}};
|
|
m_ff = _RAND_2[32:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
rem_ff = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
sign_ff = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
shortq_shift_xx = _RAND_5[3:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
count = _RAND_6[5:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
run_state = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
finish_ff = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
shortq_enable_ff = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
dividend_neg_ff = _RAND_10[0:0];
|
|
_RAND_11 = {2{`RANDOM}};
|
|
a_ff = _RAND_11[32:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
divisor_neg_ff = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
smallnum_case_ff = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
smallnum_ff = _RAND_14[3:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
valid_ff_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
q_ff = 33'h0;
|
|
end
|
|
if (reset) begin
|
|
m_ff = 33'h0;
|
|
end
|
|
if (reset) begin
|
|
rem_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
sign_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
shortq_shift_xx = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
count = 6'h0;
|
|
end
|
|
if (reset) begin
|
|
run_state = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
finish_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
shortq_enable_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dividend_neg_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
a_ff = 33'h0;
|
|
end
|
|
if (reset) begin
|
|
divisor_neg_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
smallnum_case_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
smallnum_ff = 4'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
valid_ff_x <= 1'h0;
|
|
end else begin
|
|
valid_ff_x <= io_dp_valid & _T;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
q_ff <= 33'h0;
|
|
end else begin
|
|
q_ff <= _T_734[32:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
m_ff <= 33'h0;
|
|
end else begin
|
|
m_ff <= {_T_1499,io_divisor};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rem_ff <= 1'h0;
|
|
end else if (io_dp_valid) begin
|
|
rem_ff <= io_dp_bits_rem;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
sign_ff <= 1'h0;
|
|
end else if (io_dp_valid) begin
|
|
sign_ff <= sign_eff;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
shortq_shift_xx <= 4'h0;
|
|
end else begin
|
|
shortq_shift_xx <= _T_667 & shortq_raw;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
count <= 6'h0;
|
|
end else begin
|
|
count <= _T_700 & _T_705;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
run_state <= 1'h0;
|
|
end else begin
|
|
run_state <= _T_691 & _T;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
finish_ff <= 1'h0;
|
|
end else begin
|
|
finish_ff <= finish & _T;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
shortq_enable_ff <= 1'h0;
|
|
end else begin
|
|
shortq_enable_ff <= _T_664 & _T_665;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
dividend_neg_ff <= 1'h0;
|
|
end else if (io_dp_valid) begin
|
|
dividend_neg_ff <= io_dividend[31];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
a_ff <= 33'h0;
|
|
end else begin
|
|
a_ff <= _T_995 & _T_1001;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
divisor_neg_ff <= 1'h0;
|
|
end else if (io_dp_valid) begin
|
|
divisor_neg_ff <= io_divisor[31];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
smallnum_case_ff <= 1'h0;
|
|
end else begin
|
|
smallnum_case_ff <= _T_11 | _T_19;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
smallnum_ff <= 4'h0;
|
|
end else begin
|
|
smallnum_ff <= {_T_477,_T_476};
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_exu(
|
|
input clock,
|
|
input reset,
|
|
input io_scan_mode,
|
|
input [1:0] io_dec_data_en,
|
|
input [1:0] io_dec_ctl_en,
|
|
input [31:0] io_dbg_cmd_wrdata,
|
|
input io_i0_ap_land,
|
|
input io_i0_ap_lor,
|
|
input io_i0_ap_lxor,
|
|
input io_i0_ap_sll,
|
|
input io_i0_ap_srl,
|
|
input io_i0_ap_sra,
|
|
input io_i0_ap_beq,
|
|
input io_i0_ap_bne,
|
|
input io_i0_ap_blt,
|
|
input io_i0_ap_bge,
|
|
input io_i0_ap_add,
|
|
input io_i0_ap_sub,
|
|
input io_i0_ap_slt,
|
|
input io_i0_ap_unsign,
|
|
input io_i0_ap_jal,
|
|
input io_i0_ap_predict_t,
|
|
input io_i0_ap_predict_nt,
|
|
input io_i0_ap_csr_write,
|
|
input io_i0_ap_csr_imm,
|
|
input io_dec_debug_wdata_rs1_d,
|
|
input io_dec_i0_predict_p_d_valid,
|
|
input io_dec_i0_predict_p_d_bits_pc4,
|
|
input [1:0] io_dec_i0_predict_p_d_bits_hist,
|
|
input [11:0] io_dec_i0_predict_p_d_bits_toffset,
|
|
input io_dec_i0_predict_p_d_bits_br_error,
|
|
input io_dec_i0_predict_p_d_bits_br_start_error,
|
|
input [30:0] io_dec_i0_predict_p_d_bits_prett,
|
|
input io_dec_i0_predict_p_d_bits_pcall,
|
|
input io_dec_i0_predict_p_d_bits_pret,
|
|
input io_dec_i0_predict_p_d_bits_pja,
|
|
input io_dec_i0_predict_p_d_bits_way,
|
|
input [7:0] io_i0_predict_fghr_d,
|
|
input [7:0] io_i0_predict_index_d,
|
|
input [4:0] io_i0_predict_btag_d,
|
|
input io_dec_i0_rs1_en_d,
|
|
input io_dec_i0_rs2_en_d,
|
|
input [31:0] io_gpr_i0_rs1_d,
|
|
input [31:0] io_gpr_i0_rs2_d,
|
|
input [31:0] io_dec_i0_immed_d,
|
|
input [31:0] io_dec_i0_rs1_bypass_data_d,
|
|
input [31:0] io_dec_i0_rs2_bypass_data_d,
|
|
input [11:0] io_dec_i0_br_immed_d,
|
|
input io_dec_i0_alu_decode_d,
|
|
input io_dec_i0_select_pc_d,
|
|
input [30:0] io_dec_i0_pc_d,
|
|
input [1:0] io_dec_i0_rs1_bypass_en_d,
|
|
input [1:0] io_dec_i0_rs2_bypass_en_d,
|
|
input io_dec_csr_ren_d,
|
|
input io_mul_p_valid,
|
|
input io_mul_p_bits_rs1_sign,
|
|
input io_mul_p_bits_rs2_sign,
|
|
input io_mul_p_bits_low,
|
|
input io_div_p_valid,
|
|
input io_div_p_bits_unsign,
|
|
input io_div_p_bits_rem,
|
|
input io_dec_div_cancel,
|
|
input [30:0] io_pred_correct_npc_x,
|
|
input io_dec_tlu_flush_lower_r,
|
|
input [30:0] io_dec_tlu_flush_path_r,
|
|
input io_dec_extint_stall,
|
|
input [29:0] io_dec_tlu_meihap,
|
|
output [31:0] io_exu_lsu_rs1_d,
|
|
output [31:0] io_exu_lsu_rs2_d,
|
|
output io_exu_flush_final,
|
|
output [30:0] io_exu_flush_path_final,
|
|
output [31:0] io_exu_i0_result_x,
|
|
output [30:0] io_exu_i0_pc_x,
|
|
output [31:0] io_exu_csr_rs1_x,
|
|
output [30:0] io_exu_npc_r,
|
|
output [1:0] io_exu_i0_br_hist_r,
|
|
output io_exu_i0_br_error_r,
|
|
output io_exu_i0_br_start_error_r,
|
|
output [7:0] io_exu_i0_br_index_r,
|
|
output io_exu_i0_br_valid_r,
|
|
output io_exu_i0_br_mp_r,
|
|
output io_exu_i0_br_middle_r,
|
|
output [7:0] io_exu_i0_br_fghr_r,
|
|
output io_exu_i0_br_way_r,
|
|
output io_exu_mp_pkt_bits_misp,
|
|
output io_exu_mp_pkt_bits_ataken,
|
|
output io_exu_mp_pkt_bits_boffset,
|
|
output io_exu_mp_pkt_bits_pc4,
|
|
output [1:0] io_exu_mp_pkt_bits_hist,
|
|
output [11:0] io_exu_mp_pkt_bits_toffset,
|
|
output io_exu_mp_pkt_bits_pcall,
|
|
output io_exu_mp_pkt_bits_pret,
|
|
output io_exu_mp_pkt_bits_pja,
|
|
output io_exu_mp_pkt_bits_way,
|
|
output [7:0] io_exu_mp_eghr,
|
|
output [7:0] io_exu_mp_fghr,
|
|
output [7:0] io_exu_mp_index,
|
|
output [4:0] io_exu_mp_btag,
|
|
output io_exu_pmu_i0_br_misp,
|
|
output io_exu_pmu_i0_br_ataken,
|
|
output io_exu_pmu_i0_pc4,
|
|
output [31:0] io_exu_div_result,
|
|
output io_exu_div_wren
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_10_io_en; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 518:23]
|
|
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire i_alu_clock; // @[el2_exu.scala 187:19]
|
|
wire i_alu_reset; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_scan_mode; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_flush_upper_x; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_flush_lower_r; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_enable; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_valid_in; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_land; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_lor; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_lxor; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_sll; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_srl; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_sra; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_beq; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_bne; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_blt; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_bge; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_add; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_sub; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_slt; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_unsign; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_jal; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_predict_t; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_predict_nt; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_csr_write; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_ap_csr_imm; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_csr_ren_in; // @[el2_exu.scala 187:19]
|
|
wire [31:0] i_alu_io_a_in; // @[el2_exu.scala 187:19]
|
|
wire [31:0] i_alu_io_b_in; // @[el2_exu.scala 187:19]
|
|
wire [30:0] i_alu_io_pc_in; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_pp_in_valid; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_pp_in_bits_boffset; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_pp_in_bits_pc4; // @[el2_exu.scala 187:19]
|
|
wire [1:0] i_alu_io_pp_in_bits_hist; // @[el2_exu.scala 187:19]
|
|
wire [11:0] i_alu_io_pp_in_bits_toffset; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_pp_in_bits_br_error; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_pp_in_bits_br_start_error; // @[el2_exu.scala 187:19]
|
|
wire [30:0] i_alu_io_pp_in_bits_prett; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_pp_in_bits_pcall; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_pp_in_bits_pret; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_pp_in_bits_pja; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_pp_in_bits_way; // @[el2_exu.scala 187:19]
|
|
wire [11:0] i_alu_io_brimm_in; // @[el2_exu.scala 187:19]
|
|
wire [31:0] i_alu_io_result_ff; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_flush_upper_out; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_flush_final_out; // @[el2_exu.scala 187:19]
|
|
wire [30:0] i_alu_io_flush_path_out; // @[el2_exu.scala 187:19]
|
|
wire [30:0] i_alu_io_pc_ff; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_pred_correct_out; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_predict_p_out_valid; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_predict_p_out_bits_misp; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_predict_p_out_bits_ataken; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_predict_p_out_bits_boffset; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_predict_p_out_bits_pc4; // @[el2_exu.scala 187:19]
|
|
wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[el2_exu.scala 187:19]
|
|
wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_predict_p_out_bits_br_error; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_predict_p_out_bits_br_start_error; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_predict_p_out_bits_pcall; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_predict_p_out_bits_pret; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_predict_p_out_bits_pja; // @[el2_exu.scala 187:19]
|
|
wire i_alu_io_predict_p_out_bits_way; // @[el2_exu.scala 187:19]
|
|
wire i_mul_clock; // @[el2_exu.scala 208:19]
|
|
wire i_mul_reset; // @[el2_exu.scala 208:19]
|
|
wire i_mul_io_scan_mode; // @[el2_exu.scala 208:19]
|
|
wire i_mul_io_mul_p_valid; // @[el2_exu.scala 208:19]
|
|
wire i_mul_io_mul_p_bits_rs1_sign; // @[el2_exu.scala 208:19]
|
|
wire i_mul_io_mul_p_bits_rs2_sign; // @[el2_exu.scala 208:19]
|
|
wire i_mul_io_mul_p_bits_low; // @[el2_exu.scala 208:19]
|
|
wire [31:0] i_mul_io_rs1_in; // @[el2_exu.scala 208:19]
|
|
wire [31:0] i_mul_io_rs2_in; // @[el2_exu.scala 208:19]
|
|
wire [31:0] i_mul_io_result_x; // @[el2_exu.scala 208:19]
|
|
wire i_div_clock; // @[el2_exu.scala 215:19]
|
|
wire i_div_reset; // @[el2_exu.scala 215:19]
|
|
wire i_div_io_scan_mode; // @[el2_exu.scala 215:19]
|
|
wire i_div_io_dp_valid; // @[el2_exu.scala 215:19]
|
|
wire i_div_io_dp_bits_unsign; // @[el2_exu.scala 215:19]
|
|
wire i_div_io_dp_bits_rem; // @[el2_exu.scala 215:19]
|
|
wire [31:0] i_div_io_dividend; // @[el2_exu.scala 215:19]
|
|
wire [31:0] i_div_io_divisor; // @[el2_exu.scala 215:19]
|
|
wire i_div_io_cancel; // @[el2_exu.scala 215:19]
|
|
wire [31:0] i_div_io_out; // @[el2_exu.scala 215:19]
|
|
wire i_div_io_finish_dly; // @[el2_exu.scala 215:19]
|
|
wire [15:0] _T = {io_i0_predict_fghr_d,io_i0_predict_index_d}; // @[Cat.scala 29:58]
|
|
reg [30:0] i0_flush_path_x; // @[el2_lib.scala 514:16]
|
|
reg [31:0] _T_3; // @[el2_lib.scala 514:16]
|
|
reg i0_predict_p_x_valid; // @[el2_lib.scala 524:16]
|
|
reg i0_predict_p_x_bits_misp; // @[el2_lib.scala 524:16]
|
|
reg i0_predict_p_x_bits_ataken; // @[el2_lib.scala 524:16]
|
|
reg i0_predict_p_x_bits_boffset; // @[el2_lib.scala 524:16]
|
|
reg i0_predict_p_x_bits_pc4; // @[el2_lib.scala 524:16]
|
|
reg [1:0] i0_predict_p_x_bits_hist; // @[el2_lib.scala 524:16]
|
|
reg [11:0] i0_predict_p_x_bits_toffset; // @[el2_lib.scala 524:16]
|
|
reg i0_predict_p_x_bits_br_error; // @[el2_lib.scala 524:16]
|
|
reg i0_predict_p_x_bits_br_start_error; // @[el2_lib.scala 524:16]
|
|
reg i0_predict_p_x_bits_pcall; // @[el2_lib.scala 524:16]
|
|
reg i0_predict_p_x_bits_pret; // @[el2_lib.scala 524:16]
|
|
reg i0_predict_p_x_bits_pja; // @[el2_lib.scala 524:16]
|
|
reg i0_predict_p_x_bits_way; // @[el2_lib.scala 524:16]
|
|
reg [20:0] predpipe_x; // @[el2_lib.scala 514:16]
|
|
reg [20:0] predpipe_r; // @[el2_lib.scala 514:16]
|
|
reg [7:0] ghr_x; // @[el2_lib.scala 514:16]
|
|
reg i0_pred_correct_upper_x; // @[el2_lib.scala 514:16]
|
|
reg i0_flush_upper_x; // @[el2_lib.scala 514:16]
|
|
reg i0_taken_x; // @[el2_lib.scala 514:16]
|
|
reg i0_valid_x; // @[el2_lib.scala 514:16]
|
|
reg i0_pp_r_valid; // @[el2_lib.scala 524:16]
|
|
reg i0_pp_r_bits_misp; // @[el2_lib.scala 524:16]
|
|
reg i0_pp_r_bits_ataken; // @[el2_lib.scala 524:16]
|
|
reg i0_pp_r_bits_boffset; // @[el2_lib.scala 524:16]
|
|
reg i0_pp_r_bits_pc4; // @[el2_lib.scala 524:16]
|
|
reg [1:0] i0_pp_r_bits_hist; // @[el2_lib.scala 524:16]
|
|
reg i0_pp_r_bits_br_error; // @[el2_lib.scala 524:16]
|
|
reg i0_pp_r_bits_br_start_error; // @[el2_lib.scala 524:16]
|
|
reg i0_pp_r_bits_way; // @[el2_lib.scala 524:16]
|
|
reg [5:0] pred_temp1; // @[el2_lib.scala 514:16]
|
|
reg i0_pred_correct_upper_r; // @[el2_lib.scala 514:16]
|
|
reg [30:0] i0_flush_path_upper_r; // @[el2_lib.scala 514:16]
|
|
reg [24:0] pred_temp2; // @[el2_lib.scala 514:16]
|
|
wire [30:0] _T_23 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58]
|
|
wire _T_149 = ~io_dec_tlu_flush_lower_r; // @[el2_exu.scala 240:6]
|
|
wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[el2_exu.scala 86:52 el2_exu.scala 204:41]
|
|
wire _T_145 = i0_predict_p_d_valid & io_dec_i0_alu_decode_d; // @[el2_exu.scala 233:54]
|
|
wire i0_valid_d = _T_145 & _T_149; // @[el2_exu.scala 233:79]
|
|
wire _T_150 = _T_149 & i0_valid_d; // @[el2_exu.scala 240:32]
|
|
reg [7:0] ghr_d; // @[el2_lib.scala 514:16]
|
|
wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[el2_exu.scala 86:52 el2_exu.scala 204:41]
|
|
wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_i0_alu_decode_d; // @[el2_exu.scala 234:59]
|
|
wire [7:0] _T_153 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_159 = _T_150 ? _T_153 : 8'h0; // @[Mux.scala 27:72]
|
|
wire _T_155 = ~i0_valid_d; // @[el2_exu.scala 241:34]
|
|
wire _T_156 = _T_149 & _T_155; // @[el2_exu.scala 241:32]
|
|
wire [7:0] _T_160 = _T_156 ? ghr_d : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_162 = _T_159 | _T_160; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_161 = io_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] ghr_d_ns = _T_162 | _T_161; // @[Mux.scala 27:72]
|
|
wire _T_39 = ghr_d_ns != ghr_d; // @[el2_exu.scala 134:39]
|
|
reg mul_valid_x; // @[el2_lib.scala 514:16]
|
|
wire _T_40 = io_mul_p_valid != mul_valid_x; // @[el2_exu.scala 134:70]
|
|
wire _T_41 = _T_39 | _T_40; // @[el2_exu.scala 134:50]
|
|
reg flush_lower_ff; // @[el2_lib.scala 514:16]
|
|
wire _T_42 = io_dec_tlu_flush_lower_r != flush_lower_ff; // @[el2_exu.scala 134:116]
|
|
wire i0_rs1_bypass_en_d = io_dec_i0_rs1_bypass_en_d[0] | io_dec_i0_rs1_bypass_en_d[1]; // @[el2_exu.scala 135:65]
|
|
wire i0_rs2_bypass_en_d = io_dec_i0_rs2_bypass_en_d[0] | io_dec_i0_rs2_bypass_en_d[1]; // @[el2_exu.scala 136:65]
|
|
wire [31:0] _T_52 = io_dec_i0_rs1_bypass_en_d[0] ? io_dec_i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_53 = io_dec_i0_rs1_bypass_en_d[1] ? io_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] i0_rs1_bypass_data_d = _T_52 | _T_53; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_59 = io_dec_i0_rs2_bypass_en_d[0] ? io_dec_i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_60 = io_dec_i0_rs2_bypass_en_d[1] ? io_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] i0_rs2_bypass_data_d = _T_59 | _T_60; // @[Mux.scala 27:72]
|
|
wire _T_63 = ~i0_rs1_bypass_en_d; // @[el2_exu.scala 150:6]
|
|
wire _T_64 = _T_63 & io_dec_i0_select_pc_d; // @[el2_exu.scala 150:26]
|
|
wire [31:0] _T_66 = {io_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_68 = _T_63 & io_dec_debug_wdata_rs1_d; // @[el2_exu.scala 151:26]
|
|
wire _T_71 = ~io_dec_debug_wdata_rs1_d; // @[el2_exu.scala 152:28]
|
|
wire _T_72 = _T_63 & _T_71; // @[el2_exu.scala 152:26]
|
|
wire _T_73 = _T_72 & io_dec_i0_rs1_en_d; // @[el2_exu.scala 152:54]
|
|
wire [31:0] _T_75 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_76 = _T_64 ? _T_66 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_77 = _T_68 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_78 = _T_73 ? io_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_79 = _T_75 | _T_76; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_80 = _T_79 | _T_77; // @[Mux.scala 27:72]
|
|
wire [31:0] i0_rs1_d = _T_80 | _T_78; // @[Mux.scala 27:72]
|
|
wire _T_82 = ~i0_rs2_bypass_en_d; // @[el2_exu.scala 156:6]
|
|
wire _T_83 = _T_82 & io_dec_i0_rs2_en_d; // @[el2_exu.scala 156:26]
|
|
wire [31:0] _T_88 = _T_83 ? io_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_89 = _T_82 ? io_dec_i0_immed_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_90 = i0_rs2_bypass_en_d ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_91 = _T_88 | _T_89; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_92 = _T_91 | _T_90; // @[Mux.scala 27:72]
|
|
wire _T_94 = ~io_dec_extint_stall; // @[el2_exu.scala 163:28]
|
|
wire _T_95 = _T_63 & _T_94; // @[el2_exu.scala 163:26]
|
|
wire _T_96 = _T_95 & io_dec_i0_rs1_en_d; // @[el2_exu.scala 163:49]
|
|
wire _T_99 = i0_rs1_bypass_en_d & _T_94; // @[el2_exu.scala 164:25]
|
|
wire [31:0] _T_102 = {io_dec_tlu_meihap,2'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_103 = _T_96 ? io_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_104 = _T_99 ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_105 = io_dec_extint_stall ? _T_102 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_106 = _T_103 | _T_104; // @[Mux.scala 27:72]
|
|
wire _T_111 = _T_82 & _T_94; // @[el2_exu.scala 169:26]
|
|
wire _T_112 = _T_111 & io_dec_i0_rs2_en_d; // @[el2_exu.scala 169:49]
|
|
wire _T_115 = i0_rs2_bypass_en_d & _T_94; // @[el2_exu.scala 170:25]
|
|
wire [31:0] _T_117 = _T_112 ? io_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_118 = _T_115 ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_122 = _T_63 & io_dec_i0_rs1_en_d; // @[el2_exu.scala 174:26]
|
|
wire [31:0] _T_125 = _T_122 ? io_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_167 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58]
|
|
wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[el2_exu.scala 258:49]
|
|
wire _T_179 = i0_flush_upper_x & _T_149; // @[el2_exu.scala 260:67]
|
|
wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[el2_exu.scala 85:52 el2_exu.scala 203:41]
|
|
wire [31:0] pred_correct_npc_r = {{1'd0}, _T_23}; // @[el2_exu.scala 90:50 el2_exu.scala 121:41]
|
|
wire [31:0] _T_188 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[el2_exu.scala 278:56]
|
|
wire [31:0] i0_rs2_d = _T_92; // @[Mux.scala 27:72 Mux.scala 27:72]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 518:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en),
|
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en),
|
|
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_8_io_l1clk),
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en),
|
|
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_9_io_l1clk),
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en),
|
|
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 518:23]
|
|
.io_l1clk(rvclkhdr_10_io_l1clk),
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en),
|
|
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_11_io_l1clk),
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en),
|
|
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_12_io_l1clk),
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en),
|
|
.io_scan_mode(rvclkhdr_12_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_13_io_l1clk),
|
|
.io_clk(rvclkhdr_13_io_clk),
|
|
.io_en(rvclkhdr_13_io_en),
|
|
.io_scan_mode(rvclkhdr_13_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_14_io_l1clk),
|
|
.io_clk(rvclkhdr_14_io_clk),
|
|
.io_en(rvclkhdr_14_io_en),
|
|
.io_scan_mode(rvclkhdr_14_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_15_io_l1clk),
|
|
.io_clk(rvclkhdr_15_io_clk),
|
|
.io_en(rvclkhdr_15_io_en),
|
|
.io_scan_mode(rvclkhdr_15_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_16_io_l1clk),
|
|
.io_clk(rvclkhdr_16_io_clk),
|
|
.io_en(rvclkhdr_16_io_en),
|
|
.io_scan_mode(rvclkhdr_16_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_17_io_l1clk),
|
|
.io_clk(rvclkhdr_17_io_clk),
|
|
.io_en(rvclkhdr_17_io_en),
|
|
.io_scan_mode(rvclkhdr_17_io_scan_mode)
|
|
);
|
|
el2_exu_alu_ctl i_alu ( // @[el2_exu.scala 187:19]
|
|
.clock(i_alu_clock),
|
|
.reset(i_alu_reset),
|
|
.io_scan_mode(i_alu_io_scan_mode),
|
|
.io_flush_upper_x(i_alu_io_flush_upper_x),
|
|
.io_flush_lower_r(i_alu_io_flush_lower_r),
|
|
.io_enable(i_alu_io_enable),
|
|
.io_valid_in(i_alu_io_valid_in),
|
|
.io_ap_land(i_alu_io_ap_land),
|
|
.io_ap_lor(i_alu_io_ap_lor),
|
|
.io_ap_lxor(i_alu_io_ap_lxor),
|
|
.io_ap_sll(i_alu_io_ap_sll),
|
|
.io_ap_srl(i_alu_io_ap_srl),
|
|
.io_ap_sra(i_alu_io_ap_sra),
|
|
.io_ap_beq(i_alu_io_ap_beq),
|
|
.io_ap_bne(i_alu_io_ap_bne),
|
|
.io_ap_blt(i_alu_io_ap_blt),
|
|
.io_ap_bge(i_alu_io_ap_bge),
|
|
.io_ap_add(i_alu_io_ap_add),
|
|
.io_ap_sub(i_alu_io_ap_sub),
|
|
.io_ap_slt(i_alu_io_ap_slt),
|
|
.io_ap_unsign(i_alu_io_ap_unsign),
|
|
.io_ap_jal(i_alu_io_ap_jal),
|
|
.io_ap_predict_t(i_alu_io_ap_predict_t),
|
|
.io_ap_predict_nt(i_alu_io_ap_predict_nt),
|
|
.io_ap_csr_write(i_alu_io_ap_csr_write),
|
|
.io_ap_csr_imm(i_alu_io_ap_csr_imm),
|
|
.io_csr_ren_in(i_alu_io_csr_ren_in),
|
|
.io_a_in(i_alu_io_a_in),
|
|
.io_b_in(i_alu_io_b_in),
|
|
.io_pc_in(i_alu_io_pc_in),
|
|
.io_pp_in_valid(i_alu_io_pp_in_valid),
|
|
.io_pp_in_bits_boffset(i_alu_io_pp_in_bits_boffset),
|
|
.io_pp_in_bits_pc4(i_alu_io_pp_in_bits_pc4),
|
|
.io_pp_in_bits_hist(i_alu_io_pp_in_bits_hist),
|
|
.io_pp_in_bits_toffset(i_alu_io_pp_in_bits_toffset),
|
|
.io_pp_in_bits_br_error(i_alu_io_pp_in_bits_br_error),
|
|
.io_pp_in_bits_br_start_error(i_alu_io_pp_in_bits_br_start_error),
|
|
.io_pp_in_bits_prett(i_alu_io_pp_in_bits_prett),
|
|
.io_pp_in_bits_pcall(i_alu_io_pp_in_bits_pcall),
|
|
.io_pp_in_bits_pret(i_alu_io_pp_in_bits_pret),
|
|
.io_pp_in_bits_pja(i_alu_io_pp_in_bits_pja),
|
|
.io_pp_in_bits_way(i_alu_io_pp_in_bits_way),
|
|
.io_brimm_in(i_alu_io_brimm_in),
|
|
.io_result_ff(i_alu_io_result_ff),
|
|
.io_flush_upper_out(i_alu_io_flush_upper_out),
|
|
.io_flush_final_out(i_alu_io_flush_final_out),
|
|
.io_flush_path_out(i_alu_io_flush_path_out),
|
|
.io_pc_ff(i_alu_io_pc_ff),
|
|
.io_pred_correct_out(i_alu_io_pred_correct_out),
|
|
.io_predict_p_out_valid(i_alu_io_predict_p_out_valid),
|
|
.io_predict_p_out_bits_misp(i_alu_io_predict_p_out_bits_misp),
|
|
.io_predict_p_out_bits_ataken(i_alu_io_predict_p_out_bits_ataken),
|
|
.io_predict_p_out_bits_boffset(i_alu_io_predict_p_out_bits_boffset),
|
|
.io_predict_p_out_bits_pc4(i_alu_io_predict_p_out_bits_pc4),
|
|
.io_predict_p_out_bits_hist(i_alu_io_predict_p_out_bits_hist),
|
|
.io_predict_p_out_bits_toffset(i_alu_io_predict_p_out_bits_toffset),
|
|
.io_predict_p_out_bits_br_error(i_alu_io_predict_p_out_bits_br_error),
|
|
.io_predict_p_out_bits_br_start_error(i_alu_io_predict_p_out_bits_br_start_error),
|
|
.io_predict_p_out_bits_pcall(i_alu_io_predict_p_out_bits_pcall),
|
|
.io_predict_p_out_bits_pret(i_alu_io_predict_p_out_bits_pret),
|
|
.io_predict_p_out_bits_pja(i_alu_io_predict_p_out_bits_pja),
|
|
.io_predict_p_out_bits_way(i_alu_io_predict_p_out_bits_way)
|
|
);
|
|
el2_exu_mul_ctl i_mul ( // @[el2_exu.scala 208:19]
|
|
.clock(i_mul_clock),
|
|
.reset(i_mul_reset),
|
|
.io_scan_mode(i_mul_io_scan_mode),
|
|
.io_mul_p_valid(i_mul_io_mul_p_valid),
|
|
.io_mul_p_bits_rs1_sign(i_mul_io_mul_p_bits_rs1_sign),
|
|
.io_mul_p_bits_rs2_sign(i_mul_io_mul_p_bits_rs2_sign),
|
|
.io_mul_p_bits_low(i_mul_io_mul_p_bits_low),
|
|
.io_rs1_in(i_mul_io_rs1_in),
|
|
.io_rs2_in(i_mul_io_rs2_in),
|
|
.io_result_x(i_mul_io_result_x)
|
|
);
|
|
el2_exu_div_ctl i_div ( // @[el2_exu.scala 215:19]
|
|
.clock(i_div_clock),
|
|
.reset(i_div_reset),
|
|
.io_scan_mode(i_div_io_scan_mode),
|
|
.io_dp_valid(i_div_io_dp_valid),
|
|
.io_dp_bits_unsign(i_div_io_dp_bits_unsign),
|
|
.io_dp_bits_rem(i_div_io_dp_bits_rem),
|
|
.io_dividend(i_div_io_dividend),
|
|
.io_divisor(i_div_io_divisor),
|
|
.io_cancel(i_div_io_cancel),
|
|
.io_out(i_div_io_out),
|
|
.io_finish_dly(i_div_io_finish_dly)
|
|
);
|
|
assign io_exu_lsu_rs1_d = _T_106 | _T_105; // @[el2_exu.scala 162:19]
|
|
assign io_exu_lsu_rs2_d = _T_117 | _T_118; // @[el2_exu.scala 168:19]
|
|
assign io_exu_flush_final = i_alu_io_flush_final_out; // @[el2_exu.scala 202:33]
|
|
assign io_exu_flush_path_final = io_dec_tlu_flush_lower_r ? io_dec_tlu_flush_path_r : i0_flush_path_d; // @[el2_exu.scala 277:50]
|
|
assign io_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[el2_exu.scala 224:42]
|
|
assign io_exu_i0_pc_x = i_alu_io_pc_ff; // @[el2_exu.scala 206:41]
|
|
assign io_exu_csr_rs1_x = _T_3; // @[el2_exu.scala 107:41]
|
|
assign io_exu_npc_r = _T_188[30:0]; // @[el2_exu.scala 278:50]
|
|
assign io_exu_i0_br_hist_r = i0_pp_r_bits_hist; // @[el2_exu.scala 251:50]
|
|
assign io_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[el2_exu.scala 252:42]
|
|
assign io_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[el2_exu.scala 254:36]
|
|
assign io_exu_i0_br_index_r = predpipe_r[12:5]; // @[el2_exu.scala 256:42]
|
|
assign io_exu_i0_br_valid_r = i0_pp_r_valid; // @[el2_exu.scala 248:36]
|
|
assign io_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[el2_exu.scala 249:36]
|
|
assign io_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[el2_exu.scala 253:36]
|
|
assign io_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[el2_exu.scala 255:50]
|
|
assign io_exu_i0_br_way_r = i0_pp_r_bits_way; // @[el2_exu.scala 250:36]
|
|
assign io_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[el2_exu.scala 264:41]
|
|
assign io_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[el2_exu.scala 268:41]
|
|
assign io_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[el2_exu.scala 269:41]
|
|
assign io_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[el2_exu.scala 270:41]
|
|
assign io_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[el2_exu.scala 271:58]
|
|
assign io_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[el2_exu.scala 272:50]
|
|
assign io_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[el2_exu.scala 265:41]
|
|
assign io_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[el2_exu.scala 267:41]
|
|
assign io_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[el2_exu.scala 266:41]
|
|
assign io_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[el2_exu.scala 263:41]
|
|
assign io_exu_mp_eghr = final_predpipe_mp[20:13]; // @[el2_exu.scala 276:36]
|
|
assign io_exu_mp_fghr = _T_179 ? ghr_d : ghr_x; // @[el2_exu.scala 273:36]
|
|
assign io_exu_mp_index = final_predpipe_mp[12:5]; // @[el2_exu.scala 274:58]
|
|
assign io_exu_mp_btag = final_predpipe_mp[4:0]; // @[el2_exu.scala 275:58]
|
|
assign io_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[el2_exu.scala 228:31]
|
|
assign io_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[el2_exu.scala 229:31]
|
|
assign io_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[el2_exu.scala 230:31]
|
|
assign io_exu_div_result = i_div_io_out; // @[el2_exu.scala 222:33]
|
|
assign io_exu_div_wren = i_div_io_finish_dly; // @[el2_exu.scala 221:41]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = io_dec_data_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = io_dec_data_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 520:18]
|
|
assign rvclkhdr_2_io_en = io_dec_data_en[1]; // @[el2_lib.scala 521:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = io_dec_data_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_4_io_en = io_dec_data_en[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_5_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_6_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_7_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_8_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_9_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 520:18]
|
|
assign rvclkhdr_10_io_en = io_dec_ctl_en[0]; // @[el2_lib.scala 521:17]
|
|
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24]
|
|
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_11_io_en = io_dec_ctl_en[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_12_io_en = io_dec_ctl_en[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_13_io_en = io_dec_data_en[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_14_io_en = io_dec_data_en[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_15_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_16_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_17_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign i_alu_clock = clock;
|
|
assign i_alu_reset = reset;
|
|
assign i_alu_io_scan_mode = io_scan_mode; // @[el2_exu.scala 188:33]
|
|
assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[el2_exu.scala 192:33]
|
|
assign i_alu_io_flush_lower_r = io_dec_tlu_flush_lower_r; // @[el2_exu.scala 193:33]
|
|
assign i_alu_io_enable = io_dec_ctl_en[1]; // @[el2_exu.scala 189:41]
|
|
assign i_alu_io_valid_in = io_dec_i0_alu_decode_d; // @[el2_exu.scala 191:33]
|
|
assign i_alu_io_ap_land = io_i0_ap_land; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_lor = io_i0_ap_lor; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_lxor = io_i0_ap_lxor; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_sll = io_i0_ap_sll; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_srl = io_i0_ap_srl; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_sra = io_i0_ap_sra; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_beq = io_i0_ap_beq; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_bne = io_i0_ap_bne; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_blt = io_i0_ap_blt; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_bge = io_i0_ap_bge; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_add = io_i0_ap_add; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_sub = io_i0_ap_sub; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_slt = io_i0_ap_slt; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_unsign = io_i0_ap_unsign; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_jal = io_i0_ap_jal; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_predict_t = io_i0_ap_predict_t; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_predict_nt = io_i0_ap_predict_nt; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_csr_write = io_i0_ap_csr_write; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_ap_csr_imm = io_i0_ap_csr_imm; // @[el2_exu.scala 198:41]
|
|
assign i_alu_io_csr_ren_in = io_dec_csr_ren_d; // @[el2_exu.scala 199:33]
|
|
assign i_alu_io_a_in = _T_80 | _T_78; // @[el2_exu.scala 194:33]
|
|
assign i_alu_io_b_in = i0_rs2_d; // @[el2_exu.scala 195:33]
|
|
assign i_alu_io_pc_in = io_dec_i0_pc_d; // @[el2_exu.scala 196:41]
|
|
assign i_alu_io_pp_in_valid = io_dec_i0_predict_p_d_valid; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_pp_in_bits_boffset = io_dec_i0_pc_d[0]; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_pp_in_bits_pc4 = io_dec_i0_predict_p_d_bits_pc4; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_pp_in_bits_hist = io_dec_i0_predict_p_d_bits_hist; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_pp_in_bits_toffset = io_dec_i0_predict_p_d_bits_toffset; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_pp_in_bits_br_error = io_dec_i0_predict_p_d_bits_br_error; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_pp_in_bits_br_start_error = io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_pp_in_bits_prett = io_dec_i0_predict_p_d_bits_prett; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_pp_in_bits_pcall = io_dec_i0_predict_p_d_bits_pcall; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_pp_in_bits_pret = io_dec_i0_predict_p_d_bits_pret; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_pp_in_bits_pja = io_dec_i0_predict_p_d_bits_pja; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_pp_in_bits_way = io_dec_i0_predict_p_d_bits_way; // @[el2_exu.scala 190:41]
|
|
assign i_alu_io_brimm_in = io_dec_i0_br_immed_d; // @[el2_exu.scala 197:33]
|
|
assign i_mul_clock = clock;
|
|
assign i_mul_reset = reset;
|
|
assign i_mul_io_scan_mode = io_scan_mode; // @[el2_exu.scala 209:33]
|
|
assign i_mul_io_mul_p_valid = io_mul_p_valid; // @[el2_exu.scala 210:41]
|
|
assign i_mul_io_mul_p_bits_rs1_sign = io_mul_p_bits_rs1_sign; // @[el2_exu.scala 210:41]
|
|
assign i_mul_io_mul_p_bits_rs2_sign = io_mul_p_bits_rs2_sign; // @[el2_exu.scala 210:41]
|
|
assign i_mul_io_mul_p_bits_low = io_mul_p_bits_low; // @[el2_exu.scala 210:41]
|
|
assign i_mul_io_rs1_in = _T_125 | _T_75; // @[el2_exu.scala 211:41]
|
|
assign i_mul_io_rs2_in = _T_91 | _T_90; // @[el2_exu.scala 212:41]
|
|
assign i_div_clock = clock;
|
|
assign i_div_reset = reset;
|
|
assign i_div_io_scan_mode = io_scan_mode; // @[el2_exu.scala 216:33]
|
|
assign i_div_io_dp_valid = io_div_p_valid; // @[el2_exu.scala 218:41]
|
|
assign i_div_io_dp_bits_unsign = io_div_p_bits_unsign; // @[el2_exu.scala 218:41]
|
|
assign i_div_io_dp_bits_rem = io_div_p_bits_rem; // @[el2_exu.scala 218:41]
|
|
assign i_div_io_dividend = _T_125 | _T_75; // @[el2_exu.scala 219:33]
|
|
assign i_div_io_divisor = _T_91 | _T_90; // @[el2_exu.scala 220:33]
|
|
assign i_div_io_cancel = io_dec_div_cancel; // @[el2_exu.scala 217:41]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
i0_flush_path_x = _RAND_0[30:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_3 = _RAND_1[31:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
i0_predict_p_x_valid = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_misp = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_ataken = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_boffset = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_pc4 = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_hist = _RAND_7[1:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_toffset = _RAND_8[11:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_br_error = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_br_start_error = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_pcall = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_pret = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_pja = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_way = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
predpipe_x = _RAND_15[20:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
predpipe_r = _RAND_16[20:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
ghr_x = _RAND_17[7:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
i0_pred_correct_upper_x = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
i0_flush_upper_x = _RAND_19[0:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
i0_taken_x = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
i0_valid_x = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
i0_pp_r_valid = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
i0_pp_r_bits_misp = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
i0_pp_r_bits_ataken = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
i0_pp_r_bits_boffset = _RAND_25[0:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
i0_pp_r_bits_pc4 = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
i0_pp_r_bits_hist = _RAND_27[1:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
i0_pp_r_bits_br_error = _RAND_28[0:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
i0_pp_r_bits_br_start_error = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
i0_pp_r_bits_way = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
pred_temp1 = _RAND_31[5:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
i0_pred_correct_upper_r = _RAND_32[0:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
i0_flush_path_upper_r = _RAND_33[30:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
pred_temp2 = _RAND_34[24:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
ghr_d = _RAND_35[7:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
mul_valid_x = _RAND_36[0:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
flush_lower_ff = _RAND_37[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
i0_flush_path_x = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_misp = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_ataken = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_boffset = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pc4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_hist = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_toffset = 12'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_br_error = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_br_start_error = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pcall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pret = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pja = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_way = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
predpipe_x = 21'h0;
|
|
end
|
|
if (reset) begin
|
|
predpipe_r = 21'h0;
|
|
end
|
|
if (reset) begin
|
|
ghr_x = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pred_correct_upper_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_flush_upper_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_taken_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_valid_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_misp = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_ataken = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_boffset = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_pc4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_hist = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_br_error = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_br_start_error = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_way = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
pred_temp1 = 6'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pred_correct_upper_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_flush_path_upper_r = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
pred_temp2 = 25'h0;
|
|
end
|
|
if (reset) begin
|
|
ghr_d = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
mul_valid_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
flush_lower_ff = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_flush_path_x <= 31'h0;
|
|
end else begin
|
|
i0_flush_path_x <= i_alu_io_flush_path_out;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_3 <= 32'h0;
|
|
end else if (io_dec_csr_ren_d) begin
|
|
_T_3 <= i0_rs1_d;
|
|
end else begin
|
|
_T_3 <= io_exu_csr_rs1_x;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_valid <= 1'h0;
|
|
end else begin
|
|
i0_predict_p_x_valid <= i_alu_io_predict_p_out_valid;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_misp <= 1'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_misp <= i_alu_io_predict_p_out_bits_misp;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_ataken <= 1'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_ataken <= i_alu_io_predict_p_out_bits_ataken;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_boffset <= 1'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_boffset <= i_alu_io_predict_p_out_bits_boffset;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pc4 <= 1'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_pc4 <= i_alu_io_predict_p_out_bits_pc4;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_hist <= 2'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_hist <= i_alu_io_predict_p_out_bits_hist;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_toffset <= 12'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_toffset <= i_alu_io_predict_p_out_bits_toffset;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_br_error <= 1'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_br_error <= i_alu_io_predict_p_out_bits_br_error;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_br_start_error <= 1'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_br_start_error <= i_alu_io_predict_p_out_bits_br_start_error;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pcall <= 1'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_pcall <= i_alu_io_predict_p_out_bits_pcall;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pret <= 1'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_pret <= i_alu_io_predict_p_out_bits_pret;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pja <= 1'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_pja <= i_alu_io_predict_p_out_bits_pja;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_way <= 1'h0;
|
|
end else begin
|
|
i0_predict_p_x_bits_way <= i_alu_io_predict_p_out_bits_way;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
predpipe_x <= 21'h0;
|
|
end else begin
|
|
predpipe_x <= {_T,io_i0_predict_btag_d};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
predpipe_r <= 21'h0;
|
|
end else begin
|
|
predpipe_r <= predpipe_x;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ghr_x <= 8'h0;
|
|
end else if (i0_valid_x) begin
|
|
ghr_x <= _T_167;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pred_correct_upper_x <= 1'h0;
|
|
end else begin
|
|
i0_pred_correct_upper_x <= i_alu_io_pred_correct_out;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_flush_upper_x <= 1'h0;
|
|
end else begin
|
|
i0_flush_upper_x <= i_alu_io_flush_upper_out;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_taken_x <= 1'h0;
|
|
end else begin
|
|
i0_taken_x <= i0_predict_p_d_bits_ataken & io_dec_i0_alu_decode_d;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_valid_x <= 1'h0;
|
|
end else begin
|
|
i0_valid_x <= _T_145 & _T_149;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_valid <= 1'h0;
|
|
end else begin
|
|
i0_pp_r_valid <= i0_predict_p_x_valid;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_misp <= 1'h0;
|
|
end else begin
|
|
i0_pp_r_bits_misp <= i0_predict_p_x_bits_misp;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_ataken <= 1'h0;
|
|
end else begin
|
|
i0_pp_r_bits_ataken <= i0_predict_p_x_bits_ataken;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_boffset <= 1'h0;
|
|
end else begin
|
|
i0_pp_r_bits_boffset <= i0_predict_p_x_bits_boffset;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_pc4 <= 1'h0;
|
|
end else begin
|
|
i0_pp_r_bits_pc4 <= i0_predict_p_x_bits_pc4;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_hist <= 2'h0;
|
|
end else begin
|
|
i0_pp_r_bits_hist <= i0_predict_p_x_bits_hist;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_br_error <= 1'h0;
|
|
end else begin
|
|
i0_pp_r_bits_br_error <= i0_predict_p_x_bits_br_error;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_br_start_error <= 1'h0;
|
|
end else begin
|
|
i0_pp_r_bits_br_start_error <= i0_predict_p_x_bits_br_start_error;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_way <= 1'h0;
|
|
end else begin
|
|
i0_pp_r_bits_way <= i0_predict_p_x_bits_way;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
pred_temp1 <= 6'h0;
|
|
end else begin
|
|
pred_temp1 <= io_pred_correct_npc_x[5:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pred_correct_upper_r <= 1'h0;
|
|
end else begin
|
|
i0_pred_correct_upper_r <= i0_pred_correct_upper_x;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_flush_path_upper_r <= 31'h0;
|
|
end else begin
|
|
i0_flush_path_upper_r <= i0_flush_path_x;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
pred_temp2 <= 25'h0;
|
|
end else begin
|
|
pred_temp2 <= io_pred_correct_npc_x[30:6];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ghr_d <= 8'h0;
|
|
end else begin
|
|
ghr_d <= _T_162 | _T_161;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
mul_valid_x <= 1'h0;
|
|
end else begin
|
|
mul_valid_x <= io_mul_p_valid;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
flush_lower_ff <= 1'h0;
|
|
end else begin
|
|
flush_lower_ff <= io_dec_tlu_flush_lower_r;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_lsu_addrcheck(
|
|
input reset,
|
|
input io_lsu_c2_m_clk,
|
|
input [31:0] io_start_addr_d,
|
|
input [31:0] io_end_addr_d,
|
|
input io_lsu_pkt_d_valid,
|
|
input io_lsu_pkt_d_bits_fast_int,
|
|
input io_lsu_pkt_d_bits_by,
|
|
input io_lsu_pkt_d_bits_half,
|
|
input io_lsu_pkt_d_bits_word,
|
|
input io_lsu_pkt_d_bits_load,
|
|
input io_lsu_pkt_d_bits_store,
|
|
input io_lsu_pkt_d_bits_dma,
|
|
input [31:0] io_dec_tlu_mrac_ff,
|
|
input [3:0] io_rs1_region_d,
|
|
output io_is_sideeffects_m,
|
|
output io_addr_in_dccm_d,
|
|
output io_addr_in_pic_d,
|
|
output io_addr_external_d,
|
|
output io_access_fault_d,
|
|
output io_misaligned_fault_d,
|
|
output [3:0] io_exc_mscause_d,
|
|
output io_fir_dccm_access_error_d,
|
|
output io_fir_nondccm_access_error_d
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[el2_lib.scala 496:49]
|
|
wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 501:39]
|
|
wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[el2_lib.scala 496:49]
|
|
wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 501:39]
|
|
wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[el2_lsu_addrcheck.scala 42:45]
|
|
wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 501:39]
|
|
wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 501:39]
|
|
wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 54:60]
|
|
wire _T_17 = io_rs1_region_d == 4'hf; // @[el2_lsu_addrcheck.scala 55:54]
|
|
wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[el2_lsu_addrcheck.scala 55:73]
|
|
wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_25 = io_dec_tlu_mrac_ff >> csr_idx; // @[el2_lsu_addrcheck.scala 61:50]
|
|
wire _T_28 = start_addr_dccm_or_pic | addr_in_iccm; // @[el2_lsu_addrcheck.scala 61:121]
|
|
wire _T_29 = ~_T_28; // @[el2_lsu_addrcheck.scala 61:62]
|
|
wire _T_30 = _T_25[0] & _T_29; // @[el2_lsu_addrcheck.scala 61:60]
|
|
wire _T_31 = _T_30 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 61:137]
|
|
wire _T_32 = io_lsu_pkt_d_bits_store | io_lsu_pkt_d_bits_load; // @[el2_lsu_addrcheck.scala 61:185]
|
|
wire is_sideeffects_d = _T_31 & _T_32; // @[el2_lsu_addrcheck.scala 61:158]
|
|
wire _T_34 = io_start_addr_d[1:0] == 2'h0; // @[el2_lsu_addrcheck.scala 62:80]
|
|
wire _T_35 = io_lsu_pkt_d_bits_word & _T_34; // @[el2_lsu_addrcheck.scala 62:56]
|
|
wire _T_37 = ~io_start_addr_d[0]; // @[el2_lsu_addrcheck.scala 62:138]
|
|
wire _T_38 = io_lsu_pkt_d_bits_half & _T_37; // @[el2_lsu_addrcheck.scala 62:116]
|
|
wire _T_39 = _T_35 | _T_38; // @[el2_lsu_addrcheck.scala 62:90]
|
|
wire is_aligned_d = _T_39 | io_lsu_pkt_d_bits_by; // @[el2_lsu_addrcheck.scala 62:148]
|
|
wire [31:0] _T_50 = io_start_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:56]
|
|
wire _T_52 = _T_50 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:88]
|
|
wire [31:0] _T_55 = io_start_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 68:56]
|
|
wire _T_57 = _T_55 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 68:88]
|
|
wire _T_59 = _T_52 | _T_57; // @[el2_lsu_addrcheck.scala 67:153]
|
|
wire [31:0] _T_61 = io_start_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 69:56]
|
|
wire _T_63 = _T_61 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 69:88]
|
|
wire _T_65 = _T_59 | _T_63; // @[el2_lsu_addrcheck.scala 68:153]
|
|
wire [31:0] _T_67 = io_start_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 70:56]
|
|
wire _T_69 = _T_67 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 70:88]
|
|
wire _T_71 = _T_65 | _T_69; // @[el2_lsu_addrcheck.scala 69:153]
|
|
wire [31:0] _T_97 = io_end_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:57]
|
|
wire _T_99 = _T_97 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:89]
|
|
wire [31:0] _T_102 = io_end_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 77:58]
|
|
wire _T_104 = _T_102 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 77:90]
|
|
wire _T_106 = _T_99 | _T_104; // @[el2_lsu_addrcheck.scala 76:154]
|
|
wire [31:0] _T_108 = io_end_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 78:58]
|
|
wire _T_110 = _T_108 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 78:90]
|
|
wire _T_112 = _T_106 | _T_110; // @[el2_lsu_addrcheck.scala 77:155]
|
|
wire [31:0] _T_114 = io_end_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 79:58]
|
|
wire _T_116 = _T_114 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 79:90]
|
|
wire _T_118 = _T_112 | _T_116; // @[el2_lsu_addrcheck.scala 78:155]
|
|
wire non_dccm_access_ok = _T_71 & _T_118; // @[el2_lsu_addrcheck.scala 75:7]
|
|
wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[el2_lsu_addrcheck.scala 85:57]
|
|
wire _T_145 = io_start_addr_d[1:0] != 2'h0; // @[el2_lsu_addrcheck.scala 86:76]
|
|
wire _T_146 = ~io_lsu_pkt_d_bits_word; // @[el2_lsu_addrcheck.scala 86:92]
|
|
wire _T_147 = _T_145 | _T_146; // @[el2_lsu_addrcheck.scala 86:90]
|
|
wire picm_access_fault_d = io_addr_in_pic_d & _T_147; // @[el2_lsu_addrcheck.scala 86:51]
|
|
wire _T_148 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 91:87]
|
|
wire _T_149 = ~_T_148; // @[el2_lsu_addrcheck.scala 91:64]
|
|
wire _T_150 = start_addr_in_dccm_region_d & _T_149; // @[el2_lsu_addrcheck.scala 91:62]
|
|
wire _T_151 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 93:57]
|
|
wire _T_152 = ~_T_151; // @[el2_lsu_addrcheck.scala 93:36]
|
|
wire _T_153 = end_addr_in_dccm_region_d & _T_152; // @[el2_lsu_addrcheck.scala 93:34]
|
|
wire _T_154 = _T_150 | _T_153; // @[el2_lsu_addrcheck.scala 91:112]
|
|
wire _T_155 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 95:29]
|
|
wire _T_156 = _T_154 | _T_155; // @[el2_lsu_addrcheck.scala 93:85]
|
|
wire _T_157 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 97:29]
|
|
wire unmapped_access_fault_d = _T_156 | _T_157; // @[el2_lsu_addrcheck.scala 95:85]
|
|
wire _T_159 = ~start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 99:33]
|
|
wire _T_160 = ~non_dccm_access_ok; // @[el2_lsu_addrcheck.scala 99:64]
|
|
wire mpu_access_fault_d = _T_159 & _T_160; // @[el2_lsu_addrcheck.scala 99:62]
|
|
wire _T_162 = unmapped_access_fault_d | mpu_access_fault_d; // @[el2_lsu_addrcheck.scala 111:49]
|
|
wire _T_163 = _T_162 | picm_access_fault_d; // @[el2_lsu_addrcheck.scala 111:70]
|
|
wire _T_164 = _T_163 | regpred_access_fault_d; // @[el2_lsu_addrcheck.scala 111:92]
|
|
wire _T_165 = _T_164 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 111:118]
|
|
wire _T_166 = ~io_lsu_pkt_d_bits_dma; // @[el2_lsu_addrcheck.scala 111:141]
|
|
wire [3:0] _T_172 = picm_access_fault_d ? 4'h6 : 4'h0; // @[el2_lsu_addrcheck.scala 112:164]
|
|
wire [3:0] _T_173 = regpred_access_fault_d ? 4'h5 : _T_172; // @[el2_lsu_addrcheck.scala 112:120]
|
|
wire [3:0] _T_174 = mpu_access_fault_d ? 4'h3 : _T_173; // @[el2_lsu_addrcheck.scala 112:80]
|
|
wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_174; // @[el2_lsu_addrcheck.scala 112:35]
|
|
wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[el2_lsu_addrcheck.scala 113:61]
|
|
wire _T_177 = ~is_aligned_d; // @[el2_lsu_addrcheck.scala 114:59]
|
|
wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_177; // @[el2_lsu_addrcheck.scala 114:57]
|
|
wire _T_178 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[el2_lsu_addrcheck.scala 115:90]
|
|
wire _T_179 = regcross_misaligned_fault_d | _T_178; // @[el2_lsu_addrcheck.scala 115:57]
|
|
wire _T_180 = _T_179 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 115:113]
|
|
wire [3:0] _T_184 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[el2_lsu_addrcheck.scala 116:80]
|
|
wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_184; // @[el2_lsu_addrcheck.scala 116:39]
|
|
wire _T_189 = ~start_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 118:66]
|
|
wire _T_190 = start_addr_in_dccm_region_d & _T_189; // @[el2_lsu_addrcheck.scala 118:64]
|
|
wire _T_191 = ~end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 118:120]
|
|
wire _T_192 = end_addr_in_dccm_region_d & _T_191; // @[el2_lsu_addrcheck.scala 118:118]
|
|
wire _T_193 = _T_190 | _T_192; // @[el2_lsu_addrcheck.scala 118:88]
|
|
wire _T_194 = _T_193 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 118:142]
|
|
wire _T_196 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 119:66]
|
|
wire _T_197 = ~_T_196; // @[el2_lsu_addrcheck.scala 119:36]
|
|
wire _T_198 = _T_197 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 119:95]
|
|
reg _T_200; // @[el2_lsu_addrcheck.scala 121:60]
|
|
assign io_is_sideeffects_m = _T_200; // @[el2_lsu_addrcheck.scala 121:50]
|
|
assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 56:32]
|
|
assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 57:32]
|
|
assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[el2_lsu_addrcheck.scala 59:30]
|
|
assign io_access_fault_d = _T_165 & _T_166; // @[el2_lsu_addrcheck.scala 111:21]
|
|
assign io_misaligned_fault_d = _T_180 & _T_166; // @[el2_lsu_addrcheck.scala 115:25]
|
|
assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[el2_lsu_addrcheck.scala 117:21]
|
|
assign io_fir_dccm_access_error_d = _T_194 & io_lsu_pkt_d_bits_fast_int; // @[el2_lsu_addrcheck.scala 118:31]
|
|
assign io_fir_nondccm_access_error_d = _T_198 & io_lsu_pkt_d_bits_fast_int; // @[el2_lsu_addrcheck.scala 119:33]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
_T_200 = _RAND_0[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_200 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_200 <= 1'h0;
|
|
end else begin
|
|
_T_200 <= _T_31 & _T_32;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_lsu_lsc_ctl(
|
|
input reset,
|
|
input io_lsu_c1_m_clk,
|
|
input io_lsu_c1_r_clk,
|
|
input io_lsu_c2_m_clk,
|
|
input io_lsu_c2_r_clk,
|
|
input io_lsu_store_c1_m_clk,
|
|
input [31:0] io_lsu_ld_data_corr_r,
|
|
input io_lsu_single_ecc_error_r,
|
|
input io_lsu_double_ecc_error_r,
|
|
input [31:0] io_lsu_ld_data_m,
|
|
input io_lsu_single_ecc_error_m,
|
|
input io_lsu_double_ecc_error_m,
|
|
input io_flush_m_up,
|
|
input io_flush_r,
|
|
input [31:0] io_exu_lsu_rs1_d,
|
|
input [31:0] io_exu_lsu_rs2_d,
|
|
input io_lsu_p_valid,
|
|
input io_lsu_p_bits_fast_int,
|
|
input io_lsu_p_bits_by,
|
|
input io_lsu_p_bits_half,
|
|
input io_lsu_p_bits_word,
|
|
input io_lsu_p_bits_load,
|
|
input io_lsu_p_bits_store,
|
|
input io_lsu_p_bits_unsign,
|
|
input io_lsu_p_bits_store_data_bypass_d,
|
|
input io_lsu_p_bits_load_ldst_bypass_d,
|
|
input io_dec_lsu_valid_raw_d,
|
|
input [11:0] io_dec_lsu_offset_d,
|
|
input [31:0] io_picm_mask_data_m,
|
|
input [31:0] io_bus_read_data_m,
|
|
output [31:0] io_lsu_result_m,
|
|
output [31:0] io_lsu_result_corr_r,
|
|
output [31:0] io_lsu_addr_d,
|
|
output [31:0] io_lsu_addr_m,
|
|
output [31:0] io_lsu_addr_r,
|
|
output [31:0] io_end_addr_d,
|
|
output [31:0] io_end_addr_m,
|
|
output [31:0] io_end_addr_r,
|
|
output [31:0] io_store_data_m,
|
|
input [31:0] io_dec_tlu_mrac_ff,
|
|
output io_lsu_exc_m,
|
|
output io_is_sideeffects_m,
|
|
output io_lsu_commit_r,
|
|
output io_lsu_single_ecc_error_incr,
|
|
output io_lsu_error_pkt_r_valid,
|
|
output io_lsu_error_pkt_r_bits_single_ecc_error,
|
|
output io_lsu_error_pkt_r_bits_inst_type,
|
|
output io_lsu_error_pkt_r_bits_exc_type,
|
|
output [3:0] io_lsu_error_pkt_r_bits_mscause,
|
|
output [31:0] io_lsu_error_pkt_r_bits_addr,
|
|
output [30:0] io_lsu_fir_addr,
|
|
output [1:0] io_lsu_fir_error,
|
|
output io_addr_in_dccm_d,
|
|
output io_addr_in_dccm_m,
|
|
output io_addr_in_dccm_r,
|
|
output io_addr_in_pic_d,
|
|
output io_addr_in_pic_m,
|
|
output io_addr_in_pic_r,
|
|
output io_addr_external_m,
|
|
input io_dma_dccm_req,
|
|
input [31:0] io_dma_mem_addr,
|
|
input [2:0] io_dma_mem_sz,
|
|
input io_dma_mem_write,
|
|
input [63:0] io_dma_mem_wdata,
|
|
output io_lsu_pkt_d_valid,
|
|
output io_lsu_pkt_d_bits_fast_int,
|
|
output io_lsu_pkt_d_bits_by,
|
|
output io_lsu_pkt_d_bits_half,
|
|
output io_lsu_pkt_d_bits_word,
|
|
output io_lsu_pkt_d_bits_dword,
|
|
output io_lsu_pkt_d_bits_load,
|
|
output io_lsu_pkt_d_bits_store,
|
|
output io_lsu_pkt_d_bits_unsign,
|
|
output io_lsu_pkt_d_bits_dma,
|
|
output io_lsu_pkt_d_bits_store_data_bypass_d,
|
|
output io_lsu_pkt_d_bits_load_ldst_bypass_d,
|
|
output io_lsu_pkt_d_bits_store_data_bypass_m,
|
|
output io_lsu_pkt_m_valid,
|
|
output io_lsu_pkt_m_bits_fast_int,
|
|
output io_lsu_pkt_m_bits_by,
|
|
output io_lsu_pkt_m_bits_half,
|
|
output io_lsu_pkt_m_bits_word,
|
|
output io_lsu_pkt_m_bits_dword,
|
|
output io_lsu_pkt_m_bits_load,
|
|
output io_lsu_pkt_m_bits_store,
|
|
output io_lsu_pkt_m_bits_unsign,
|
|
output io_lsu_pkt_m_bits_dma,
|
|
output io_lsu_pkt_m_bits_store_data_bypass_m,
|
|
output io_lsu_pkt_r_valid,
|
|
output io_lsu_pkt_r_bits_by,
|
|
output io_lsu_pkt_r_bits_half,
|
|
output io_lsu_pkt_r_bits_word,
|
|
output io_lsu_pkt_r_bits_dword,
|
|
output io_lsu_pkt_r_bits_load,
|
|
output io_lsu_pkt_r_bits_store,
|
|
output io_lsu_pkt_r_bits_unsign,
|
|
output io_lsu_pkt_r_bits_dma
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire addrcheck_reset; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_lsu_c2_m_clk; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire [31:0] addrcheck_io_start_addr_d; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire [31:0] addrcheck_io_end_addr_d; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_lsu_pkt_d_valid; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_by; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_half; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_word; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_load; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_store; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_dma; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire [3:0] addrcheck_io_rs1_region_d; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_is_sideeffects_m; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_addr_in_dccm_d; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_addr_in_pic_d; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_addr_external_d; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_access_fault_d; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_misaligned_fault_d; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire [3:0] addrcheck_io_exc_mscause_d; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_fir_dccm_access_error_d; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire addrcheck_io_fir_nondccm_access_error_d; // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_exu_lsu_rs1_d : io_dma_mem_addr; // @[el2_lsu_lsc_ctl.scala 101:28]
|
|
wire [11:0] _T_3 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12]
|
|
wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_3; // @[el2_lsu_lsc_ctl.scala 102:51]
|
|
wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[el2_lsu_lsc_ctl.scala 105:28]
|
|
wire [12:0] _T_6 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_8 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_10 = _T_6 + _T_8; // @[el2_lib.scala 232:39]
|
|
wire _T_13 = lsu_offset_d[11] ^ _T_10[12]; // @[el2_lib.scala 233:46]
|
|
wire _T_14 = ~_T_13; // @[el2_lib.scala 233:33]
|
|
wire [19:0] _T_16 = _T_14 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
|
|
wire [19:0] _T_18 = _T_16 & rs1_d[31:12]; // @[el2_lib.scala 233:58]
|
|
wire _T_20 = ~lsu_offset_d[11]; // @[el2_lib.scala 234:18]
|
|
wire _T_22 = _T_20 & _T_10[12]; // @[el2_lib.scala 234:30]
|
|
wire [19:0] _T_24 = _T_22 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
|
|
wire [19:0] _T_27 = rs1_d[31:12] + 20'h1; // @[el2_lib.scala 234:54]
|
|
wire [19:0] _T_28 = _T_24 & _T_27; // @[el2_lib.scala 234:41]
|
|
wire [19:0] _T_29 = _T_18 | _T_28; // @[el2_lib.scala 233:72]
|
|
wire _T_32 = ~_T_10[12]; // @[el2_lib.scala 235:31]
|
|
wire _T_33 = lsu_offset_d[11] & _T_32; // @[el2_lib.scala 235:29]
|
|
wire [19:0] _T_35 = _T_33 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
|
|
wire [19:0] _T_38 = rs1_d[31:12] - 20'h1; // @[el2_lib.scala 235:54]
|
|
wire [19:0] _T_39 = _T_35 & _T_38; // @[el2_lib.scala 235:41]
|
|
wire [19:0] _T_40 = _T_29 | _T_39; // @[el2_lib.scala 234:61]
|
|
wire [2:0] _T_43 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_44 = _T_43 & 3'h1; // @[el2_lsu_lsc_ctl.scala 110:58]
|
|
wire [2:0] _T_46 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_47 = _T_46 & 3'h3; // @[el2_lsu_lsc_ctl.scala 111:40]
|
|
wire [2:0] _T_48 = _T_44 | _T_47; // @[el2_lsu_lsc_ctl.scala 110:70]
|
|
wire [2:0] _T_50 = io_lsu_pkt_d_bits_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] addr_offset_d = _T_48 | _T_50; // @[el2_lsu_lsc_ctl.scala 111:52]
|
|
wire [12:0] _T_54 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_57 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58]
|
|
wire [12:0] _GEN_0 = {{1'd0}, _T_57}; // @[el2_lsu_lsc_ctl.scala 114:60]
|
|
wire [12:0] end_addr_offset_d = _T_54 + _GEN_0; // @[el2_lsu_lsc_ctl.scala 114:60]
|
|
wire [18:0] _T_62 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_64 = {_T_62,end_addr_offset_d}; // @[Cat.scala 29:58]
|
|
reg access_fault_m; // @[el2_lsu_lsc_ctl.scala 150:75]
|
|
reg misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 151:75]
|
|
reg [3:0] exc_mscause_m; // @[el2_lsu_lsc_ctl.scala 152:75]
|
|
reg fir_dccm_access_error_m; // @[el2_lsu_lsc_ctl.scala 153:75]
|
|
reg fir_nondccm_access_error_m; // @[el2_lsu_lsc_ctl.scala 154:75]
|
|
wire _T_69 = access_fault_m | misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 156:34]
|
|
wire _T_70 = ~io_lsu_double_ecc_error_r; // @[el2_lsu_lsc_ctl.scala 157:64]
|
|
wire _T_71 = io_lsu_single_ecc_error_r & _T_70; // @[el2_lsu_lsc_ctl.scala 157:62]
|
|
wire _T_72 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[el2_lsu_lsc_ctl.scala 157:111]
|
|
wire _T_73 = _T_71 & _T_72; // @[el2_lsu_lsc_ctl.scala 157:92]
|
|
wire _T_76 = _T_69 | io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 179:67]
|
|
wire _T_77 = _T_76 & io_lsu_pkt_m_valid; // @[el2_lsu_lsc_ctl.scala 179:96]
|
|
wire _T_78 = ~io_lsu_pkt_m_bits_dma; // @[el2_lsu_lsc_ctl.scala 179:119]
|
|
wire _T_79 = _T_77 & _T_78; // @[el2_lsu_lsc_ctl.scala 179:117]
|
|
wire _T_80 = ~io_lsu_pkt_m_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 179:144]
|
|
wire _T_81 = _T_79 & _T_80; // @[el2_lsu_lsc_ctl.scala 179:142]
|
|
wire _T_82 = ~io_flush_m_up; // @[el2_lsu_lsc_ctl.scala 179:174]
|
|
wire lsu_error_pkt_m_valid = _T_81 & _T_82; // @[el2_lsu_lsc_ctl.scala 179:172]
|
|
wire _T_84 = ~lsu_error_pkt_m_valid; // @[el2_lsu_lsc_ctl.scala 180:75]
|
|
wire _T_85 = io_lsu_single_ecc_error_m & _T_84; // @[el2_lsu_lsc_ctl.scala 180:73]
|
|
wire lsu_error_pkt_m_bits_exc_type = ~misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 182:46]
|
|
wire _T_90 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 183:78]
|
|
wire _T_91 = ~access_fault_m; // @[el2_lsu_lsc_ctl.scala 183:102]
|
|
wire _T_92 = _T_90 & _T_91; // @[el2_lsu_lsc_ctl.scala 183:100]
|
|
wire _T_99 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 185:166]
|
|
reg _T_105_valid; // @[el2_lsu_lsc_ctl.scala 186:75]
|
|
reg _T_105_bits_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:75]
|
|
reg _T_105_bits_inst_type; // @[el2_lsu_lsc_ctl.scala 186:75]
|
|
reg _T_105_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 186:75]
|
|
reg [3:0] _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:75]
|
|
reg [31:0] _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:75]
|
|
reg [1:0] _T_106; // @[el2_lsu_lsc_ctl.scala 187:75]
|
|
wire dma_pkt_d_bits_load = ~io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 194:30]
|
|
wire dma_pkt_d_bits_by = io_dma_mem_sz == 3'h0; // @[el2_lsu_lsc_ctl.scala 195:50]
|
|
wire dma_pkt_d_bits_half = io_dma_mem_sz == 3'h1; // @[el2_lsu_lsc_ctl.scala 196:50]
|
|
wire dma_pkt_d_bits_word = io_dma_mem_sz == 3'h2; // @[el2_lsu_lsc_ctl.scala 197:50]
|
|
wire dma_pkt_d_bits_dword = io_dma_mem_sz == 3'h3; // @[el2_lsu_lsc_ctl.scala 198:50]
|
|
wire _T_118 = ~io_lsu_p_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 211:64]
|
|
wire _T_119 = io_flush_m_up & _T_118; // @[el2_lsu_lsc_ctl.scala 211:61]
|
|
wire _T_120 = ~_T_119; // @[el2_lsu_lsc_ctl.scala 211:45]
|
|
wire _T_121 = io_lsu_p_valid & _T_120; // @[el2_lsu_lsc_ctl.scala 211:43]
|
|
wire _T_123 = ~io_lsu_pkt_d_bits_dma; // @[el2_lsu_lsc_ctl.scala 212:68]
|
|
wire _T_124 = io_flush_m_up & _T_123; // @[el2_lsu_lsc_ctl.scala 212:65]
|
|
wire _T_125 = ~_T_124; // @[el2_lsu_lsc_ctl.scala 212:49]
|
|
wire _T_128 = io_flush_m_up & _T_78; // @[el2_lsu_lsc_ctl.scala 213:65]
|
|
wire _T_129 = ~_T_128; // @[el2_lsu_lsc_ctl.scala 213:49]
|
|
reg _T_132_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 215:65]
|
|
reg _T_132_bits_by; // @[el2_lsu_lsc_ctl.scala 215:65]
|
|
reg _T_132_bits_half; // @[el2_lsu_lsc_ctl.scala 215:65]
|
|
reg _T_132_bits_word; // @[el2_lsu_lsc_ctl.scala 215:65]
|
|
reg _T_132_bits_dword; // @[el2_lsu_lsc_ctl.scala 215:65]
|
|
reg _T_132_bits_load; // @[el2_lsu_lsc_ctl.scala 215:65]
|
|
reg _T_132_bits_store; // @[el2_lsu_lsc_ctl.scala 215:65]
|
|
reg _T_132_bits_unsign; // @[el2_lsu_lsc_ctl.scala 215:65]
|
|
reg _T_132_bits_dma; // @[el2_lsu_lsc_ctl.scala 215:65]
|
|
reg _T_132_bits_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 215:65]
|
|
reg _T_134_bits_by; // @[el2_lsu_lsc_ctl.scala 216:65]
|
|
reg _T_134_bits_half; // @[el2_lsu_lsc_ctl.scala 216:65]
|
|
reg _T_134_bits_word; // @[el2_lsu_lsc_ctl.scala 216:65]
|
|
reg _T_134_bits_dword; // @[el2_lsu_lsc_ctl.scala 216:65]
|
|
reg _T_134_bits_load; // @[el2_lsu_lsc_ctl.scala 216:65]
|
|
reg _T_134_bits_store; // @[el2_lsu_lsc_ctl.scala 216:65]
|
|
reg _T_134_bits_unsign; // @[el2_lsu_lsc_ctl.scala 216:65]
|
|
reg _T_134_bits_dma; // @[el2_lsu_lsc_ctl.scala 216:65]
|
|
reg _T_135; // @[el2_lsu_lsc_ctl.scala 217:65]
|
|
reg _T_136; // @[el2_lsu_lsc_ctl.scala 218:65]
|
|
wire [5:0] _T_139 = {io_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] dma_mem_wdata_shifted = io_dma_mem_wdata >> _T_139; // @[el2_lsu_lsc_ctl.scala 220:54]
|
|
reg [31:0] store_data_pre_m; // @[el2_lsu_lsc_ctl.scala 224:72]
|
|
reg [31:0] _T_146; // @[el2_lsu_lsc_ctl.scala 225:62]
|
|
reg [31:0] _T_147; // @[el2_lsu_lsc_ctl.scala 226:62]
|
|
reg [31:0] _T_148; // @[el2_lsu_lsc_ctl.scala 227:62]
|
|
reg [31:0] _T_149; // @[el2_lsu_lsc_ctl.scala 228:62]
|
|
reg _T_150; // @[el2_lsu_lsc_ctl.scala 229:62]
|
|
reg _T_151; // @[el2_lsu_lsc_ctl.scala 230:62]
|
|
reg _T_152; // @[el2_lsu_lsc_ctl.scala 231:62]
|
|
reg _T_153; // @[el2_lsu_lsc_ctl.scala 232:62]
|
|
reg _T_154; // @[el2_lsu_lsc_ctl.scala 233:62]
|
|
reg addr_external_r; // @[el2_lsu_lsc_ctl.scala 234:66]
|
|
reg [31:0] bus_read_data_r; // @[el2_lsu_lsc_ctl.scala 235:66]
|
|
wire _T_156 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[el2_lsu_lsc_ctl.scala 241:68]
|
|
wire _T_157 = io_lsu_pkt_r_valid & _T_156; // @[el2_lsu_lsc_ctl.scala 241:41]
|
|
wire _T_158 = ~io_flush_r; // @[el2_lsu_lsc_ctl.scala 241:96]
|
|
wire _T_159 = _T_157 & _T_158; // @[el2_lsu_lsc_ctl.scala 241:94]
|
|
wire _T_160 = ~io_lsu_pkt_r_bits_dma; // @[el2_lsu_lsc_ctl.scala 241:110]
|
|
wire _T_163 = ~io_addr_in_pic_m; // @[el2_lsu_lsc_ctl.scala 242:69]
|
|
wire [31:0] _T_165 = _T_163 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_166 = io_picm_mask_data_m | _T_165; // @[el2_lsu_lsc_ctl.scala 242:59]
|
|
wire [31:0] _T_168 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[el2_lsu_lsc_ctl.scala 242:94]
|
|
wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[el2_lsu_lsc_ctl.scala 263:33]
|
|
wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[el2_lsu_lsc_ctl.scala 264:33]
|
|
wire _T_174 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[el2_lsu_lsc_ctl.scala 265:66]
|
|
wire [31:0] _T_176 = _T_174 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_178 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_179 = _T_176 & _T_178; // @[el2_lsu_lsc_ctl.scala 265:94]
|
|
wire _T_180 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[el2_lsu_lsc_ctl.scala 266:43]
|
|
wire [31:0] _T_182 = _T_180 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_184 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_185 = _T_182 & _T_184; // @[el2_lsu_lsc_ctl.scala 266:71]
|
|
wire [31:0] _T_186 = _T_179 | _T_185; // @[el2_lsu_lsc_ctl.scala 265:133]
|
|
wire _T_187 = ~io_lsu_pkt_m_bits_unsign; // @[el2_lsu_lsc_ctl.scala 267:17]
|
|
wire _T_188 = _T_187 & io_lsu_pkt_m_bits_by; // @[el2_lsu_lsc_ctl.scala 267:43]
|
|
wire [31:0] _T_190 = _T_188 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [23:0] _T_193 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_195 = {_T_193,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_196 = _T_190 & _T_195; // @[el2_lsu_lsc_ctl.scala 267:71]
|
|
wire [31:0] _T_197 = _T_186 | _T_196; // @[el2_lsu_lsc_ctl.scala 266:114]
|
|
wire _T_199 = _T_187 & io_lsu_pkt_m_bits_half; // @[el2_lsu_lsc_ctl.scala 268:43]
|
|
wire [31:0] _T_201 = _T_199 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [15:0] _T_204 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_206 = {_T_204,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_207 = _T_201 & _T_206; // @[el2_lsu_lsc_ctl.scala 268:71]
|
|
wire [31:0] _T_208 = _T_197 | _T_207; // @[el2_lsu_lsc_ctl.scala 267:134]
|
|
wire [31:0] _T_210 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_212 = _T_210 & lsu_ld_datafn_m; // @[el2_lsu_lsc_ctl.scala 269:43]
|
|
wire _T_214 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[el2_lsu_lsc_ctl.scala 270:66]
|
|
wire [31:0] _T_216 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_218 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_219 = _T_216 & _T_218; // @[el2_lsu_lsc_ctl.scala 270:94]
|
|
wire _T_220 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[el2_lsu_lsc_ctl.scala 271:43]
|
|
wire [31:0] _T_222 = _T_220 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_224 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_225 = _T_222 & _T_224; // @[el2_lsu_lsc_ctl.scala 271:71]
|
|
wire [31:0] _T_226 = _T_219 | _T_225; // @[el2_lsu_lsc_ctl.scala 270:138]
|
|
wire _T_227 = ~io_lsu_pkt_r_bits_unsign; // @[el2_lsu_lsc_ctl.scala 272:17]
|
|
wire _T_228 = _T_227 & io_lsu_pkt_r_bits_by; // @[el2_lsu_lsc_ctl.scala 272:43]
|
|
wire [31:0] _T_230 = _T_228 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [23:0] _T_233 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_235 = {_T_233,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_236 = _T_230 & _T_235; // @[el2_lsu_lsc_ctl.scala 272:71]
|
|
wire [31:0] _T_237 = _T_226 | _T_236; // @[el2_lsu_lsc_ctl.scala 271:119]
|
|
wire _T_239 = _T_227 & io_lsu_pkt_r_bits_half; // @[el2_lsu_lsc_ctl.scala 273:43]
|
|
wire [31:0] _T_241 = _T_239 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [15:0] _T_244 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_246 = {_T_244,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_247 = _T_241 & _T_246; // @[el2_lsu_lsc_ctl.scala 273:71]
|
|
wire [31:0] _T_248 = _T_237 | _T_247; // @[el2_lsu_lsc_ctl.scala 272:144]
|
|
wire [31:0] _T_250 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_252 = _T_250 & lsu_ld_datafn_corr_r; // @[el2_lsu_lsc_ctl.scala 274:43]
|
|
el2_lsu_addrcheck addrcheck ( // @[el2_lsu_lsc_ctl.scala 119:25]
|
|
.reset(addrcheck_reset),
|
|
.io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk),
|
|
.io_start_addr_d(addrcheck_io_start_addr_d),
|
|
.io_end_addr_d(addrcheck_io_end_addr_d),
|
|
.io_lsu_pkt_d_valid(addrcheck_io_lsu_pkt_d_valid),
|
|
.io_lsu_pkt_d_bits_fast_int(addrcheck_io_lsu_pkt_d_bits_fast_int),
|
|
.io_lsu_pkt_d_bits_by(addrcheck_io_lsu_pkt_d_bits_by),
|
|
.io_lsu_pkt_d_bits_half(addrcheck_io_lsu_pkt_d_bits_half),
|
|
.io_lsu_pkt_d_bits_word(addrcheck_io_lsu_pkt_d_bits_word),
|
|
.io_lsu_pkt_d_bits_load(addrcheck_io_lsu_pkt_d_bits_load),
|
|
.io_lsu_pkt_d_bits_store(addrcheck_io_lsu_pkt_d_bits_store),
|
|
.io_lsu_pkt_d_bits_dma(addrcheck_io_lsu_pkt_d_bits_dma),
|
|
.io_dec_tlu_mrac_ff(addrcheck_io_dec_tlu_mrac_ff),
|
|
.io_rs1_region_d(addrcheck_io_rs1_region_d),
|
|
.io_is_sideeffects_m(addrcheck_io_is_sideeffects_m),
|
|
.io_addr_in_dccm_d(addrcheck_io_addr_in_dccm_d),
|
|
.io_addr_in_pic_d(addrcheck_io_addr_in_pic_d),
|
|
.io_addr_external_d(addrcheck_io_addr_external_d),
|
|
.io_access_fault_d(addrcheck_io_access_fault_d),
|
|
.io_misaligned_fault_d(addrcheck_io_misaligned_fault_d),
|
|
.io_exc_mscause_d(addrcheck_io_exc_mscause_d),
|
|
.io_fir_dccm_access_error_d(addrcheck_io_fir_dccm_access_error_d),
|
|
.io_fir_nondccm_access_error_d(addrcheck_io_fir_nondccm_access_error_d)
|
|
);
|
|
assign io_lsu_result_m = _T_208 | _T_212; // @[el2_lsu_lsc_ctl.scala 265:27]
|
|
assign io_lsu_result_corr_r = _T_248 | _T_252; // @[el2_lsu_lsc_ctl.scala 270:27]
|
|
assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[el2_lsu_lsc_ctl.scala 239:28]
|
|
assign io_lsu_addr_m = _T_146; // @[el2_lsu_lsc_ctl.scala 225:24]
|
|
assign io_lsu_addr_r = _T_147; // @[el2_lsu_lsc_ctl.scala 226:24]
|
|
assign io_end_addr_d = rs1_d + _T_64; // @[el2_lsu_lsc_ctl.scala 116:24]
|
|
assign io_end_addr_m = _T_148; // @[el2_lsu_lsc_ctl.scala 227:24]
|
|
assign io_end_addr_r = _T_149; // @[el2_lsu_lsc_ctl.scala 228:24]
|
|
assign io_store_data_m = _T_166 & _T_168; // @[el2_lsu_lsc_ctl.scala 242:29]
|
|
assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 156:16]
|
|
assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[el2_lsu_lsc_ctl.scala 129:42]
|
|
assign io_lsu_commit_r = _T_159 & _T_160; // @[el2_lsu_lsc_ctl.scala 241:19]
|
|
assign io_lsu_single_ecc_error_incr = _T_73 & io_lsu_pkt_r_valid; // @[el2_lsu_lsc_ctl.scala 157:32]
|
|
assign io_lsu_error_pkt_r_valid = _T_105_valid; // @[el2_lsu_lsc_ctl.scala 186:38]
|
|
assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_105_bits_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:38]
|
|
assign io_lsu_error_pkt_r_bits_inst_type = _T_105_bits_inst_type; // @[el2_lsu_lsc_ctl.scala 186:38]
|
|
assign io_lsu_error_pkt_r_bits_exc_type = _T_105_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 186:38]
|
|
assign io_lsu_error_pkt_r_bits_mscause = _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:38]
|
|
assign io_lsu_error_pkt_r_bits_addr = _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:38]
|
|
assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[el2_lsu_lsc_ctl.scala 237:28]
|
|
assign io_lsu_fir_error = _T_106; // @[el2_lsu_lsc_ctl.scala 187:38]
|
|
assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[el2_lsu_lsc_ctl.scala 130:42]
|
|
assign io_addr_in_dccm_m = _T_150; // @[el2_lsu_lsc_ctl.scala 229:24]
|
|
assign io_addr_in_dccm_r = _T_151; // @[el2_lsu_lsc_ctl.scala 230:24]
|
|
assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[el2_lsu_lsc_ctl.scala 131:42]
|
|
assign io_addr_in_pic_m = _T_152; // @[el2_lsu_lsc_ctl.scala 231:24]
|
|
assign io_addr_in_pic_r = _T_153; // @[el2_lsu_lsc_ctl.scala 232:24]
|
|
assign io_addr_external_m = _T_154; // @[el2_lsu_lsc_ctl.scala 233:24]
|
|
assign io_lsu_pkt_d_valid = _T_121 | io_dma_dccm_req; // @[el2_lsu_lsc_ctl.scala 207:20 el2_lsu_lsc_ctl.scala 211:24]
|
|
assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? 1'h0 : dma_pkt_d_bits_dword; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? 1'h0 : 1'h1; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_d_bits_store_data_bypass_m = 1'h0; // @[el2_lsu_lsc_ctl.scala 207:20]
|
|
assign io_lsu_pkt_m_valid = _T_135; // @[el2_lsu_lsc_ctl.scala 215:28 el2_lsu_lsc_ctl.scala 217:28]
|
|
assign io_lsu_pkt_m_bits_fast_int = _T_132_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 215:28]
|
|
assign io_lsu_pkt_m_bits_by = _T_132_bits_by; // @[el2_lsu_lsc_ctl.scala 215:28]
|
|
assign io_lsu_pkt_m_bits_half = _T_132_bits_half; // @[el2_lsu_lsc_ctl.scala 215:28]
|
|
assign io_lsu_pkt_m_bits_word = _T_132_bits_word; // @[el2_lsu_lsc_ctl.scala 215:28]
|
|
assign io_lsu_pkt_m_bits_dword = _T_132_bits_dword; // @[el2_lsu_lsc_ctl.scala 215:28]
|
|
assign io_lsu_pkt_m_bits_load = _T_132_bits_load; // @[el2_lsu_lsc_ctl.scala 215:28]
|
|
assign io_lsu_pkt_m_bits_store = _T_132_bits_store; // @[el2_lsu_lsc_ctl.scala 215:28]
|
|
assign io_lsu_pkt_m_bits_unsign = _T_132_bits_unsign; // @[el2_lsu_lsc_ctl.scala 215:28]
|
|
assign io_lsu_pkt_m_bits_dma = _T_132_bits_dma; // @[el2_lsu_lsc_ctl.scala 215:28]
|
|
assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_132_bits_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 215:28]
|
|
assign io_lsu_pkt_r_valid = _T_136; // @[el2_lsu_lsc_ctl.scala 216:28 el2_lsu_lsc_ctl.scala 218:28]
|
|
assign io_lsu_pkt_r_bits_by = _T_134_bits_by; // @[el2_lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_r_bits_half = _T_134_bits_half; // @[el2_lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_r_bits_word = _T_134_bits_word; // @[el2_lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_r_bits_dword = _T_134_bits_dword; // @[el2_lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_r_bits_load = _T_134_bits_load; // @[el2_lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_r_bits_store = _T_134_bits_store; // @[el2_lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_r_bits_unsign = _T_134_bits_unsign; // @[el2_lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_r_bits_dma = _T_134_bits_dma; // @[el2_lsu_lsc_ctl.scala 216:28]
|
|
assign addrcheck_reset = reset;
|
|
assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[el2_lsu_lsc_ctl.scala 121:42]
|
|
assign addrcheck_io_start_addr_d = {_T_40,_T_10[11:0]}; // @[el2_lsu_lsc_ctl.scala 123:42]
|
|
assign addrcheck_io_end_addr_d = rs1_d + _T_64; // @[el2_lsu_lsc_ctl.scala 124:42]
|
|
assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[el2_lsu_lsc_ctl.scala 125:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_fast_int = io_lsu_pkt_d_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 125:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_by = io_lsu_pkt_d_bits_by; // @[el2_lsu_lsc_ctl.scala 125:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_half = io_lsu_pkt_d_bits_half; // @[el2_lsu_lsc_ctl.scala 125:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_word = io_lsu_pkt_d_bits_word; // @[el2_lsu_lsc_ctl.scala 125:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_load = io_lsu_pkt_d_bits_load; // @[el2_lsu_lsc_ctl.scala 125:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_store = io_lsu_pkt_d_bits_store; // @[el2_lsu_lsc_ctl.scala 125:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[el2_lsu_lsc_ctl.scala 125:42]
|
|
assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[el2_lsu_lsc_ctl.scala 126:42]
|
|
assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[el2_lsu_lsc_ctl.scala 127:42]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
access_fault_m = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
misaligned_fault_m = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
exc_mscause_m = _RAND_2[3:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
fir_dccm_access_error_m = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
fir_nondccm_access_error_m = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_105_valid = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_105_bits_single_ecc_error = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_105_bits_inst_type = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
_T_105_bits_exc_type = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
_T_105_bits_mscause = _RAND_9[3:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
_T_105_bits_addr = _RAND_10[31:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
_T_106 = _RAND_11[1:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
_T_132_bits_fast_int = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
_T_132_bits_by = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
_T_132_bits_half = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
_T_132_bits_word = _RAND_15[0:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
_T_132_bits_dword = _RAND_16[0:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
_T_132_bits_load = _RAND_17[0:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
_T_132_bits_store = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
_T_132_bits_unsign = _RAND_19[0:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
_T_132_bits_dma = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
_T_132_bits_store_data_bypass_m = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
_T_134_bits_by = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
_T_134_bits_half = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
_T_134_bits_word = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
_T_134_bits_dword = _RAND_25[0:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
_T_134_bits_load = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
_T_134_bits_store = _RAND_27[0:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
_T_134_bits_unsign = _RAND_28[0:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
_T_134_bits_dma = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
_T_135 = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
_T_136 = _RAND_31[0:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
store_data_pre_m = _RAND_32[31:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
_T_146 = _RAND_33[31:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
_T_147 = _RAND_34[31:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
_T_148 = _RAND_35[31:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
_T_149 = _RAND_36[31:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
_T_150 = _RAND_37[0:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
_T_151 = _RAND_38[0:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
_T_152 = _RAND_39[0:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
_T_153 = _RAND_40[0:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
_T_154 = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
addr_external_r = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
bus_read_data_r = _RAND_43[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
access_fault_m = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
misaligned_fault_m = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
exc_mscause_m = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
fir_dccm_access_error_m = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fir_nondccm_access_error_m = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_105_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_105_bits_single_ecc_error = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_105_bits_inst_type = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_105_bits_exc_type = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_105_bits_mscause = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_105_bits_addr = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_106 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_132_bits_fast_int = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_132_bits_by = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_132_bits_half = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_132_bits_word = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_132_bits_dword = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_132_bits_load = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_132_bits_store = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_132_bits_unsign = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_132_bits_dma = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_132_bits_store_data_bypass_m = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_134_bits_by = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_134_bits_half = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_134_bits_word = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_134_bits_dword = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_134_bits_load = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_134_bits_store = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_134_bits_unsign = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_134_bits_dma = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_135 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_136 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
store_data_pre_m = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_146 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_147 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_148 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_149 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_150 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_151 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_152 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_153 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_154 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
addr_external_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
bus_read_data_r = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
access_fault_m <= 1'h0;
|
|
end else begin
|
|
access_fault_m <= addrcheck_io_access_fault_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
misaligned_fault_m <= 1'h0;
|
|
end else begin
|
|
misaligned_fault_m <= addrcheck_io_misaligned_fault_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
exc_mscause_m <= 4'h0;
|
|
end else begin
|
|
exc_mscause_m <= addrcheck_io_exc_mscause_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fir_dccm_access_error_m <= 1'h0;
|
|
end else begin
|
|
fir_dccm_access_error_m <= addrcheck_io_fir_dccm_access_error_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fir_nondccm_access_error_m <= 1'h0;
|
|
end else begin
|
|
fir_nondccm_access_error_m <= addrcheck_io_fir_nondccm_access_error_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_105_valid <= 1'h0;
|
|
end else begin
|
|
_T_105_valid <= _T_81 & _T_82;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_105_bits_single_ecc_error <= 1'h0;
|
|
end else begin
|
|
_T_105_bits_single_ecc_error <= _T_85 & _T_78;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_105_bits_inst_type <= 1'h0;
|
|
end else begin
|
|
_T_105_bits_inst_type <= io_lsu_pkt_m_bits_store;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_105_bits_exc_type <= 1'h0;
|
|
end else begin
|
|
_T_105_bits_exc_type <= ~misaligned_fault_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_105_bits_mscause <= 4'h0;
|
|
end else if (_T_92) begin
|
|
_T_105_bits_mscause <= 4'h1;
|
|
end else begin
|
|
_T_105_bits_mscause <= exc_mscause_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_105_bits_addr <= 32'h0;
|
|
end else begin
|
|
_T_105_bits_addr <= io_lsu_addr_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_106 <= 2'h0;
|
|
end else if (fir_nondccm_access_error_m) begin
|
|
_T_106 <= 2'h3;
|
|
end else if (fir_dccm_access_error_m) begin
|
|
_T_106 <= 2'h2;
|
|
end else if (_T_99) begin
|
|
_T_106 <= 2'h1;
|
|
end else begin
|
|
_T_106 <= 2'h0;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_132_bits_fast_int <= 1'h0;
|
|
end else begin
|
|
_T_132_bits_fast_int <= io_lsu_pkt_d_bits_fast_int;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_132_bits_by <= 1'h0;
|
|
end else begin
|
|
_T_132_bits_by <= io_lsu_pkt_d_bits_by;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_132_bits_half <= 1'h0;
|
|
end else begin
|
|
_T_132_bits_half <= io_lsu_pkt_d_bits_half;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_132_bits_word <= 1'h0;
|
|
end else begin
|
|
_T_132_bits_word <= io_lsu_pkt_d_bits_word;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_132_bits_dword <= 1'h0;
|
|
end else begin
|
|
_T_132_bits_dword <= io_lsu_pkt_d_bits_dword;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_132_bits_load <= 1'h0;
|
|
end else begin
|
|
_T_132_bits_load <= io_lsu_pkt_d_bits_load;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_132_bits_store <= 1'h0;
|
|
end else begin
|
|
_T_132_bits_store <= io_lsu_pkt_d_bits_store;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_132_bits_unsign <= 1'h0;
|
|
end else begin
|
|
_T_132_bits_unsign <= io_lsu_pkt_d_bits_unsign;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_132_bits_dma <= 1'h0;
|
|
end else begin
|
|
_T_132_bits_dma <= io_lsu_pkt_d_bits_dma;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_132_bits_store_data_bypass_m <= 1'h0;
|
|
end else begin
|
|
_T_132_bits_store_data_bypass_m <= io_lsu_pkt_d_bits_store_data_bypass_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_134_bits_by <= 1'h0;
|
|
end else begin
|
|
_T_134_bits_by <= io_lsu_pkt_m_bits_by;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_134_bits_half <= 1'h0;
|
|
end else begin
|
|
_T_134_bits_half <= io_lsu_pkt_m_bits_half;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_134_bits_word <= 1'h0;
|
|
end else begin
|
|
_T_134_bits_word <= io_lsu_pkt_m_bits_word;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_134_bits_dword <= 1'h0;
|
|
end else begin
|
|
_T_134_bits_dword <= io_lsu_pkt_m_bits_dword;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_134_bits_load <= 1'h0;
|
|
end else begin
|
|
_T_134_bits_load <= io_lsu_pkt_m_bits_load;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_134_bits_store <= 1'h0;
|
|
end else begin
|
|
_T_134_bits_store <= io_lsu_pkt_m_bits_store;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_134_bits_unsign <= 1'h0;
|
|
end else begin
|
|
_T_134_bits_unsign <= io_lsu_pkt_m_bits_unsign;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_134_bits_dma <= 1'h0;
|
|
end else begin
|
|
_T_134_bits_dma <= io_lsu_pkt_m_bits_dma;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_135 <= 1'h0;
|
|
end else begin
|
|
_T_135 <= io_lsu_pkt_d_valid & _T_125;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_136 <= 1'h0;
|
|
end else begin
|
|
_T_136 <= io_lsu_pkt_m_valid & _T_129;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
store_data_pre_m <= 32'h0;
|
|
end else if (io_lsu_pkt_d_bits_store_data_bypass_d) begin
|
|
store_data_pre_m <= io_lsu_result_m;
|
|
end else if (io_dma_dccm_req) begin
|
|
store_data_pre_m <= dma_mem_wdata_shifted[31:0];
|
|
end else begin
|
|
store_data_pre_m <= io_exu_lsu_rs2_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_146 <= 32'h0;
|
|
end else begin
|
|
_T_146 <= io_lsu_addr_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_147 <= 32'h0;
|
|
end else begin
|
|
_T_147 <= io_lsu_addr_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_148 <= 32'h0;
|
|
end else begin
|
|
_T_148 <= io_end_addr_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_149 <= 32'h0;
|
|
end else begin
|
|
_T_149 <= io_end_addr_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_150 <= 1'h0;
|
|
end else begin
|
|
_T_150 <= io_addr_in_dccm_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_151 <= 1'h0;
|
|
end else begin
|
|
_T_151 <= io_addr_in_dccm_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_152 <= 1'h0;
|
|
end else begin
|
|
_T_152 <= io_addr_in_pic_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_153 <= 1'h0;
|
|
end else begin
|
|
_T_153 <= io_addr_in_pic_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_154 <= 1'h0;
|
|
end else begin
|
|
_T_154 <= addrcheck_io_addr_external_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
addr_external_r <= 1'h0;
|
|
end else begin
|
|
addr_external_r <= io_addr_external_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
bus_read_data_r <= 32'h0;
|
|
end else begin
|
|
bus_read_data_r <= io_bus_read_data_m;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_lsu_dccm_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_lsu_c2_m_clk,
|
|
input io_lsu_c2_r_clk,
|
|
input io_lsu_free_c2_clk,
|
|
input io_lsu_store_c1_r_clk,
|
|
input io_lsu_pkt_d_valid,
|
|
input io_lsu_pkt_d_bits_word,
|
|
input io_lsu_pkt_d_bits_dword,
|
|
input io_lsu_pkt_d_bits_load,
|
|
input io_lsu_pkt_d_bits_store,
|
|
input io_lsu_pkt_d_bits_dma,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_by,
|
|
input io_lsu_pkt_m_bits_half,
|
|
input io_lsu_pkt_m_bits_word,
|
|
input io_lsu_pkt_m_bits_load,
|
|
input io_lsu_pkt_m_bits_store,
|
|
input io_lsu_pkt_m_bits_dma,
|
|
input io_lsu_pkt_r_valid,
|
|
input io_lsu_pkt_r_bits_by,
|
|
input io_lsu_pkt_r_bits_half,
|
|
input io_lsu_pkt_r_bits_word,
|
|
input io_lsu_pkt_r_bits_load,
|
|
input io_lsu_pkt_r_bits_store,
|
|
input io_lsu_pkt_r_bits_dma,
|
|
input io_addr_in_dccm_d,
|
|
input io_addr_in_dccm_m,
|
|
input io_addr_in_dccm_r,
|
|
input io_addr_in_pic_d,
|
|
input io_addr_in_pic_m,
|
|
input io_addr_in_pic_r,
|
|
input io_lsu_raw_fwd_lo_r,
|
|
input io_lsu_raw_fwd_hi_r,
|
|
input io_lsu_commit_r,
|
|
input [31:0] io_lsu_addr_d,
|
|
input [15:0] io_lsu_addr_m,
|
|
input [31:0] io_lsu_addr_r,
|
|
input [15:0] io_end_addr_d,
|
|
input [15:0] io_end_addr_m,
|
|
input [15:0] io_end_addr_r,
|
|
input io_stbuf_reqvld_any,
|
|
input [15:0] io_stbuf_addr_any,
|
|
input [31:0] io_stbuf_data_any,
|
|
input [6:0] io_stbuf_ecc_any,
|
|
input [31:0] io_stbuf_fwddata_hi_m,
|
|
input [31:0] io_stbuf_fwddata_lo_m,
|
|
input [3:0] io_stbuf_fwdbyteen_lo_m,
|
|
input [3:0] io_stbuf_fwdbyteen_hi_m,
|
|
output [31:0] io_lsu_ld_data_corr_r,
|
|
input io_lsu_double_ecc_error_r,
|
|
input io_single_ecc_error_hi_r,
|
|
input io_single_ecc_error_lo_r,
|
|
input [31:0] io_sec_data_hi_r_ff,
|
|
input [31:0] io_sec_data_lo_r_ff,
|
|
input [6:0] io_sec_data_ecc_hi_r_ff,
|
|
input [6:0] io_sec_data_ecc_lo_r_ff,
|
|
output [31:0] io_dccm_rdata_hi_m,
|
|
output [31:0] io_dccm_rdata_lo_m,
|
|
output [6:0] io_dccm_data_ecc_hi_m,
|
|
output [6:0] io_dccm_data_ecc_lo_m,
|
|
output [31:0] io_lsu_ld_data_m,
|
|
input io_lsu_double_ecc_error_m,
|
|
input [31:0] io_sec_data_hi_m,
|
|
input [31:0] io_sec_data_lo_m,
|
|
input [31:0] io_store_data_m,
|
|
input io_dma_dccm_wen,
|
|
input io_dma_pic_wen,
|
|
input [2:0] io_dma_mem_tag_m,
|
|
input [31:0] io_dma_mem_addr,
|
|
input [63:0] io_dma_mem_wdata,
|
|
input [31:0] io_dma_dccm_wdata_lo,
|
|
input [31:0] io_dma_dccm_wdata_hi,
|
|
input [6:0] io_dma_dccm_wdata_ecc_hi,
|
|
input [6:0] io_dma_dccm_wdata_ecc_lo,
|
|
output [31:0] io_store_data_hi_r,
|
|
output [31:0] io_store_data_lo_r,
|
|
output [31:0] io_store_datafn_hi_r,
|
|
output [31:0] io_store_datafn_lo_r,
|
|
output [31:0] io_store_data_r,
|
|
output io_ld_single_ecc_error_r,
|
|
output io_ld_single_ecc_error_r_ff,
|
|
output [31:0] io_picm_mask_data_m,
|
|
output io_lsu_stbuf_commit_any,
|
|
output io_lsu_dccm_rden_m,
|
|
output io_dccm_dma_rvalid,
|
|
output io_dccm_dma_ecc_error,
|
|
output [2:0] io_dccm_dma_rtag,
|
|
output [63:0] io_dccm_dma_rdata,
|
|
output io_dccm_wren,
|
|
output io_dccm_rden,
|
|
output [15:0] io_dccm_wr_addr_lo,
|
|
output [38:0] io_dccm_wr_data_lo,
|
|
output [15:0] io_dccm_rd_addr_lo,
|
|
input [38:0] io_dccm_rd_data_lo,
|
|
output [15:0] io_dccm_wr_addr_hi,
|
|
output [38:0] io_dccm_wr_data_hi,
|
|
output [15:0] io_dccm_rd_addr_hi,
|
|
input [38:0] io_dccm_rd_data_hi,
|
|
output io_picm_wren,
|
|
output io_picm_rden,
|
|
output io_picm_mken,
|
|
output [31:0] io_picm_rdaddr,
|
|
output [31:0] io_picm_wraddr,
|
|
output [31:0] io_picm_wr_data,
|
|
input [31:0] io_picm_rd_data,
|
|
input io_scan_mode
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [63:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire [63:0] picm_rd_data_m = {io_picm_rd_data,io_picm_rd_data}; // @[Cat.scala 29:58]
|
|
wire [63:0] dccm_rdata_corr_m = {io_sec_data_hi_m,io_sec_data_lo_m}; // @[Cat.scala 29:58]
|
|
wire [63:0] dccm_rdata_m = {io_dccm_rdata_hi_m,io_dccm_rdata_lo_m}; // @[Cat.scala 29:58]
|
|
wire _T = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_load; // @[el2_lsu_dccm_ctl.scala 161:50]
|
|
reg [63:0] _T_2; // @[el2_lsu_dccm_ctl.scala 171:65]
|
|
wire [7:0] _T_3 = {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_6 = {io_stbuf_fwddata_hi_m,io_stbuf_fwddata_lo_m}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_11 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : dccm_rdata_corr_m[7:0]; // @[el2_lsu_dccm_ctl.scala 172:213]
|
|
wire [7:0] _T_12 = _T_3[0] ? _T_6[7:0] : _T_11; // @[el2_lsu_dccm_ctl.scala 172:78]
|
|
wire [7:0] _T_16 = {{4'd0}, _T_12[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_18 = {_T_12[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_20 = _T_18 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_21 = _T_16 | _T_20; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_0 = {{2'd0}, _T_21[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_26 = _GEN_0 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_28 = {_T_21[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_30 = _T_28 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_31 = _T_26 | _T_30; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_1 = {{1'd0}, _T_31[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_36 = _GEN_1 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_38 = {_T_31[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_40 = _T_38 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_41 = _T_36 | _T_40; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_50 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : dccm_rdata_corr_m[15:8]; // @[el2_lsu_dccm_ctl.scala 172:213]
|
|
wire [7:0] _T_51 = _T_3[1] ? _T_6[15:8] : _T_50; // @[el2_lsu_dccm_ctl.scala 172:78]
|
|
wire [7:0] _T_55 = {{4'd0}, _T_51[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_57 = {_T_51[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_59 = _T_57 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_60 = _T_55 | _T_59; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_2 = {{2'd0}, _T_60[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_65 = _GEN_2 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_67 = {_T_60[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_69 = _T_67 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_70 = _T_65 | _T_69; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_3 = {{1'd0}, _T_70[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_75 = _GEN_3 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_77 = {_T_70[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_79 = _T_77 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_80 = _T_75 | _T_79; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_89 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : dccm_rdata_corr_m[23:16]; // @[el2_lsu_dccm_ctl.scala 172:213]
|
|
wire [7:0] _T_90 = _T_3[2] ? _T_6[23:16] : _T_89; // @[el2_lsu_dccm_ctl.scala 172:78]
|
|
wire [7:0] _T_94 = {{4'd0}, _T_90[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_96 = {_T_90[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_98 = _T_96 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_99 = _T_94 | _T_98; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_4 = {{2'd0}, _T_99[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_104 = _GEN_4 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_106 = {_T_99[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_108 = _T_106 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_109 = _T_104 | _T_108; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_5 = {{1'd0}, _T_109[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_114 = _GEN_5 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_116 = {_T_109[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_118 = _T_116 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_119 = _T_114 | _T_118; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_128 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : dccm_rdata_corr_m[31:24]; // @[el2_lsu_dccm_ctl.scala 172:213]
|
|
wire [7:0] _T_129 = _T_3[3] ? _T_6[31:24] : _T_128; // @[el2_lsu_dccm_ctl.scala 172:78]
|
|
wire [7:0] _T_133 = {{4'd0}, _T_129[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_135 = {_T_129[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_137 = _T_135 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_138 = _T_133 | _T_137; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_6 = {{2'd0}, _T_138[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_143 = _GEN_6 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_145 = {_T_138[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_147 = _T_145 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_148 = _T_143 | _T_147; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_7 = {{1'd0}, _T_148[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_153 = _GEN_7 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_155 = {_T_148[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_157 = _T_155 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_158 = _T_153 | _T_157; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_167 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : dccm_rdata_corr_m[39:32]; // @[el2_lsu_dccm_ctl.scala 172:213]
|
|
wire [7:0] _T_168 = _T_3[4] ? _T_6[39:32] : _T_167; // @[el2_lsu_dccm_ctl.scala 172:78]
|
|
wire [7:0] _T_172 = {{4'd0}, _T_168[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_174 = {_T_168[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_176 = _T_174 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_177 = _T_172 | _T_176; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_8 = {{2'd0}, _T_177[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_182 = _GEN_8 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_184 = {_T_177[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_186 = _T_184 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_187 = _T_182 | _T_186; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_9 = {{1'd0}, _T_187[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_192 = _GEN_9 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_194 = {_T_187[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_196 = _T_194 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_197 = _T_192 | _T_196; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_206 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : dccm_rdata_corr_m[47:40]; // @[el2_lsu_dccm_ctl.scala 172:213]
|
|
wire [7:0] _T_207 = _T_3[5] ? _T_6[47:40] : _T_206; // @[el2_lsu_dccm_ctl.scala 172:78]
|
|
wire [7:0] _T_211 = {{4'd0}, _T_207[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_213 = {_T_207[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_215 = _T_213 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_216 = _T_211 | _T_215; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_10 = {{2'd0}, _T_216[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_221 = _GEN_10 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_223 = {_T_216[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_225 = _T_223 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_226 = _T_221 | _T_225; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_11 = {{1'd0}, _T_226[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_231 = _GEN_11 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_233 = {_T_226[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_235 = _T_233 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_236 = _T_231 | _T_235; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_245 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : dccm_rdata_corr_m[55:48]; // @[el2_lsu_dccm_ctl.scala 172:213]
|
|
wire [7:0] _T_246 = _T_3[6] ? _T_6[55:48] : _T_245; // @[el2_lsu_dccm_ctl.scala 172:78]
|
|
wire [7:0] _T_250 = {{4'd0}, _T_246[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_252 = {_T_246[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_254 = _T_252 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_255 = _T_250 | _T_254; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_12 = {{2'd0}, _T_255[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_260 = _GEN_12 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_262 = {_T_255[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_264 = _T_262 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_265 = _T_260 | _T_264; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_13 = {{1'd0}, _T_265[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_270 = _GEN_13 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_272 = {_T_265[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_274 = _T_272 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_275 = _T_270 | _T_274; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_284 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : dccm_rdata_corr_m[63:56]; // @[el2_lsu_dccm_ctl.scala 172:213]
|
|
wire [7:0] _T_285 = _T_3[7] ? _T_6[63:56] : _T_284; // @[el2_lsu_dccm_ctl.scala 172:78]
|
|
wire [7:0] _T_289 = {{4'd0}, _T_285[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_291 = {_T_285[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_293 = _T_291 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_294 = _T_289 | _T_293; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_14 = {{2'd0}, _T_294[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_299 = _GEN_14 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_301 = {_T_294[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_303 = _T_301 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_304 = _T_299 | _T_303; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_15 = {{1'd0}, _T_304[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_309 = _GEN_15 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_311 = {_T_304[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_313 = _T_311 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_314 = _T_309 | _T_313; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _T_322 = {_T_41,_T_80,_T_119,_T_158,_T_197,_T_236,_T_275,_T_314}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_326 = {{32'd0}, _T_322[63:32]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_328 = {_T_322[31:0], 32'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_330 = _T_328 & 64'hffffffff00000000; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_331 = _T_326 | _T_330; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_16 = {{16'd0}, _T_331[63:16]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_336 = _GEN_16 & 64'hffff0000ffff; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_338 = {_T_331[47:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_340 = _T_338 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_341 = _T_336 | _T_340; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_17 = {{8'd0}, _T_341[63:8]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_346 = _GEN_17 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_348 = {_T_341[55:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_350 = _T_348 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_351 = _T_346 | _T_350; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_18 = {{4'd0}, _T_351[63:4]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_356 = _GEN_18 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_358 = {_T_351[59:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_360 = _T_358 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_361 = _T_356 | _T_360; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_19 = {{2'd0}, _T_361[63:2]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_366 = _GEN_19 & 64'h3333333333333333; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_368 = {_T_361[61:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_370 = _T_368 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_371 = _T_366 | _T_370; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_20 = {{1'd0}, _T_371[63:1]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_376 = _GEN_20 & 64'h5555555555555555; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_378 = {_T_371[62:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_380 = _T_378 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75]
|
|
wire [63:0] lsu_rdata_corr_m = _T_376 | _T_380; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_390 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : dccm_rdata_m[7:0]; // @[el2_lsu_dccm_ctl.scala 173:213]
|
|
wire [7:0] _T_391 = _T_3[0] ? _T_6[7:0] : _T_390; // @[el2_lsu_dccm_ctl.scala 173:78]
|
|
wire [7:0] _T_395 = {{4'd0}, _T_391[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_397 = {_T_391[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_399 = _T_397 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_400 = _T_395 | _T_399; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_21 = {{2'd0}, _T_400[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_405 = _GEN_21 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_407 = {_T_400[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_409 = _T_407 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_410 = _T_405 | _T_409; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_22 = {{1'd0}, _T_410[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_415 = _GEN_22 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_417 = {_T_410[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_419 = _T_417 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_420 = _T_415 | _T_419; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_429 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : dccm_rdata_m[15:8]; // @[el2_lsu_dccm_ctl.scala 173:213]
|
|
wire [7:0] _T_430 = _T_3[1] ? _T_6[15:8] : _T_429; // @[el2_lsu_dccm_ctl.scala 173:78]
|
|
wire [7:0] _T_434 = {{4'd0}, _T_430[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_436 = {_T_430[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_438 = _T_436 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_439 = _T_434 | _T_438; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_23 = {{2'd0}, _T_439[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_444 = _GEN_23 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_446 = {_T_439[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_448 = _T_446 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_449 = _T_444 | _T_448; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_24 = {{1'd0}, _T_449[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_454 = _GEN_24 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_456 = {_T_449[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_458 = _T_456 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_459 = _T_454 | _T_458; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_468 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : dccm_rdata_m[23:16]; // @[el2_lsu_dccm_ctl.scala 173:213]
|
|
wire [7:0] _T_469 = _T_3[2] ? _T_6[23:16] : _T_468; // @[el2_lsu_dccm_ctl.scala 173:78]
|
|
wire [7:0] _T_473 = {{4'd0}, _T_469[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_475 = {_T_469[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_477 = _T_475 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_478 = _T_473 | _T_477; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_25 = {{2'd0}, _T_478[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_483 = _GEN_25 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_485 = {_T_478[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_487 = _T_485 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_488 = _T_483 | _T_487; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_26 = {{1'd0}, _T_488[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_493 = _GEN_26 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_495 = {_T_488[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_497 = _T_495 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_498 = _T_493 | _T_497; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_507 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : dccm_rdata_m[31:24]; // @[el2_lsu_dccm_ctl.scala 173:213]
|
|
wire [7:0] _T_508 = _T_3[3] ? _T_6[31:24] : _T_507; // @[el2_lsu_dccm_ctl.scala 173:78]
|
|
wire [7:0] _T_512 = {{4'd0}, _T_508[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_514 = {_T_508[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_516 = _T_514 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_517 = _T_512 | _T_516; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_27 = {{2'd0}, _T_517[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_522 = _GEN_27 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_524 = {_T_517[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_526 = _T_524 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_527 = _T_522 | _T_526; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_28 = {{1'd0}, _T_527[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_532 = _GEN_28 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_534 = {_T_527[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_536 = _T_534 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_537 = _T_532 | _T_536; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_546 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : dccm_rdata_m[39:32]; // @[el2_lsu_dccm_ctl.scala 173:213]
|
|
wire [7:0] _T_547 = _T_3[4] ? _T_6[39:32] : _T_546; // @[el2_lsu_dccm_ctl.scala 173:78]
|
|
wire [7:0] _T_551 = {{4'd0}, _T_547[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_553 = {_T_547[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_555 = _T_553 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_556 = _T_551 | _T_555; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_29 = {{2'd0}, _T_556[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_561 = _GEN_29 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_563 = {_T_556[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_565 = _T_563 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_566 = _T_561 | _T_565; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_30 = {{1'd0}, _T_566[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_571 = _GEN_30 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_573 = {_T_566[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_575 = _T_573 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_576 = _T_571 | _T_575; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_585 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : dccm_rdata_m[47:40]; // @[el2_lsu_dccm_ctl.scala 173:213]
|
|
wire [7:0] _T_586 = _T_3[5] ? _T_6[47:40] : _T_585; // @[el2_lsu_dccm_ctl.scala 173:78]
|
|
wire [7:0] _T_590 = {{4'd0}, _T_586[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_592 = {_T_586[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_594 = _T_592 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_595 = _T_590 | _T_594; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_31 = {{2'd0}, _T_595[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_600 = _GEN_31 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_602 = {_T_595[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_604 = _T_602 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_605 = _T_600 | _T_604; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_32 = {{1'd0}, _T_605[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_610 = _GEN_32 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_612 = {_T_605[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_614 = _T_612 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_615 = _T_610 | _T_614; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_624 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : dccm_rdata_m[55:48]; // @[el2_lsu_dccm_ctl.scala 173:213]
|
|
wire [7:0] _T_625 = _T_3[6] ? _T_6[55:48] : _T_624; // @[el2_lsu_dccm_ctl.scala 173:78]
|
|
wire [7:0] _T_629 = {{4'd0}, _T_625[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_631 = {_T_625[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_633 = _T_631 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_634 = _T_629 | _T_633; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_33 = {{2'd0}, _T_634[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_639 = _GEN_33 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_641 = {_T_634[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_643 = _T_641 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_644 = _T_639 | _T_643; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_34 = {{1'd0}, _T_644[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_649 = _GEN_34 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_651 = {_T_644[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_653 = _T_651 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_654 = _T_649 | _T_653; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_663 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : dccm_rdata_m[63:56]; // @[el2_lsu_dccm_ctl.scala 173:213]
|
|
wire [7:0] _T_664 = _T_3[7] ? _T_6[63:56] : _T_663; // @[el2_lsu_dccm_ctl.scala 173:78]
|
|
wire [7:0] _T_668 = {{4'd0}, _T_664[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_670 = {_T_664[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_672 = _T_670 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_673 = _T_668 | _T_672; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_35 = {{2'd0}, _T_673[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_678 = _GEN_35 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_680 = {_T_673[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_682 = _T_680 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_683 = _T_678 | _T_682; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_36 = {{1'd0}, _T_683[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_688 = _GEN_36 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_690 = {_T_683[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_692 = _T_690 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_693 = _T_688 | _T_692; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _T_701 = {_T_420,_T_459,_T_498,_T_537,_T_576,_T_615,_T_654,_T_693}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_705 = {{32'd0}, _T_701[63:32]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_707 = {_T_701[31:0], 32'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_709 = _T_707 & 64'hffffffff00000000; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_710 = _T_705 | _T_709; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_37 = {{16'd0}, _T_710[63:16]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_715 = _GEN_37 & 64'hffff0000ffff; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_717 = {_T_710[47:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_719 = _T_717 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_720 = _T_715 | _T_719; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_38 = {{8'd0}, _T_720[63:8]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_725 = _GEN_38 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_727 = {_T_720[55:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_729 = _T_727 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_730 = _T_725 | _T_729; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_39 = {{4'd0}, _T_730[63:4]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_735 = _GEN_39 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_737 = {_T_730[59:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_739 = _T_737 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_740 = _T_735 | _T_739; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_40 = {{2'd0}, _T_740[63:2]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_745 = _GEN_40 & 64'h3333333333333333; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_747 = {_T_740[61:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_749 = _T_747 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_750 = _T_745 | _T_749; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_41 = {{1'd0}, _T_750[63:1]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_755 = _GEN_41 & 64'h5555555555555555; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_757 = {_T_750[62:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_759 = _T_757 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75]
|
|
wire [63:0] lsu_rdata_m = _T_755 | _T_759; // @[Bitwise.scala 103:39]
|
|
wire [3:0] _GEN_42 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[el2_lsu_dccm_ctl.scala 174:49]
|
|
wire [5:0] _T_762 = 4'h8 * _GEN_42; // @[el2_lsu_dccm_ctl.scala 174:49]
|
|
wire [63:0] _T_763 = lsu_rdata_m >> _T_762; // @[el2_lsu_dccm_ctl.scala 174:43]
|
|
wire _T_769 = io_lsu_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 179:60]
|
|
wire _T_772 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 179:133]
|
|
wire _T_773 = _T_769 | _T_772; // @[el2_lsu_dccm_ctl.scala 179:101]
|
|
wire _T_774 = _T_773 & io_lsu_pkt_d_valid; // @[el2_lsu_dccm_ctl.scala 179:175]
|
|
wire _T_775 = _T_774 & io_lsu_pkt_d_bits_store; // @[el2_lsu_dccm_ctl.scala 179:196]
|
|
wire _T_776 = _T_775 & io_lsu_pkt_d_bits_dma; // @[el2_lsu_dccm_ctl.scala 179:222]
|
|
wire _T_777 = _T_776 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 179:246]
|
|
wire _T_780 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 180:37]
|
|
wire _T_783 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 180:110]
|
|
wire _T_784 = _T_780 | _T_783; // @[el2_lsu_dccm_ctl.scala 180:78]
|
|
wire _T_785 = _T_784 & io_lsu_pkt_m_valid; // @[el2_lsu_dccm_ctl.scala 180:152]
|
|
wire _T_786 = _T_785 & io_lsu_pkt_m_bits_store; // @[el2_lsu_dccm_ctl.scala 180:173]
|
|
wire _T_787 = _T_786 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_dccm_ctl.scala 180:199]
|
|
wire _T_788 = _T_787 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 180:223]
|
|
wire kill_ecc_corr_lo_r = _T_777 | _T_788; // @[el2_lsu_dccm_ctl.scala 179:267]
|
|
wire _T_791 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 182:60]
|
|
wire _T_794 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 182:133]
|
|
wire _T_795 = _T_791 | _T_794; // @[el2_lsu_dccm_ctl.scala 182:101]
|
|
wire _T_796 = _T_795 & io_lsu_pkt_d_valid; // @[el2_lsu_dccm_ctl.scala 182:175]
|
|
wire _T_797 = _T_796 & io_lsu_pkt_d_bits_store; // @[el2_lsu_dccm_ctl.scala 182:196]
|
|
wire _T_798 = _T_797 & io_lsu_pkt_d_bits_dma; // @[el2_lsu_dccm_ctl.scala 182:222]
|
|
wire _T_799 = _T_798 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 182:246]
|
|
wire _T_802 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 183:37]
|
|
wire _T_805 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 183:110]
|
|
wire _T_806 = _T_802 | _T_805; // @[el2_lsu_dccm_ctl.scala 183:78]
|
|
wire _T_807 = _T_806 & io_lsu_pkt_m_valid; // @[el2_lsu_dccm_ctl.scala 183:152]
|
|
wire _T_808 = _T_807 & io_lsu_pkt_m_bits_store; // @[el2_lsu_dccm_ctl.scala 183:173]
|
|
wire _T_809 = _T_808 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_dccm_ctl.scala 183:199]
|
|
wire _T_810 = _T_809 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 183:223]
|
|
wire kill_ecc_corr_hi_r = _T_799 | _T_810; // @[el2_lsu_dccm_ctl.scala 182:267]
|
|
wire _T_811 = io_lsu_pkt_r_bits_load & io_single_ecc_error_lo_r; // @[el2_lsu_dccm_ctl.scala 185:60]
|
|
wire _T_812 = ~io_lsu_raw_fwd_lo_r; // @[el2_lsu_dccm_ctl.scala 185:89]
|
|
wire ld_single_ecc_error_lo_r = _T_811 & _T_812; // @[el2_lsu_dccm_ctl.scala 185:87]
|
|
wire _T_813 = io_lsu_pkt_r_bits_load & io_single_ecc_error_hi_r; // @[el2_lsu_dccm_ctl.scala 186:60]
|
|
wire _T_814 = ~io_lsu_raw_fwd_hi_r; // @[el2_lsu_dccm_ctl.scala 186:89]
|
|
wire ld_single_ecc_error_hi_r = _T_813 & _T_814; // @[el2_lsu_dccm_ctl.scala 186:87]
|
|
wire _T_815 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[el2_lsu_dccm_ctl.scala 187:63]
|
|
wire _T_816 = ~io_lsu_double_ecc_error_r; // @[el2_lsu_dccm_ctl.scala 187:93]
|
|
wire _T_818 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[el2_lsu_dccm_ctl.scala 188:81]
|
|
wire _T_819 = ld_single_ecc_error_lo_r & _T_818; // @[el2_lsu_dccm_ctl.scala 188:62]
|
|
wire _T_820 = ~kill_ecc_corr_lo_r; // @[el2_lsu_dccm_ctl.scala 188:108]
|
|
wire _T_822 = ld_single_ecc_error_hi_r & _T_818; // @[el2_lsu_dccm_ctl.scala 189:62]
|
|
wire _T_823 = ~kill_ecc_corr_hi_r; // @[el2_lsu_dccm_ctl.scala 189:108]
|
|
reg lsu_double_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 191:74]
|
|
reg ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 192:74]
|
|
reg ld_single_ecc_error_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 193:74]
|
|
reg [15:0] ld_sec_addr_hi_r_ff; // @[el2_lib.scala 514:16]
|
|
reg [15:0] ld_sec_addr_lo_r_ff; // @[el2_lib.scala 514:16]
|
|
wire _T_830 = io_lsu_pkt_d_bits_word | io_lsu_pkt_d_bits_dword; // @[el2_lsu_dccm_ctl.scala 197:125]
|
|
wire _T_831 = ~_T_830; // @[el2_lsu_dccm_ctl.scala 197:100]
|
|
wire _T_833 = io_lsu_addr_d[1:0] != 2'h0; // @[el2_lsu_dccm_ctl.scala 197:174]
|
|
wire _T_834 = _T_831 | _T_833; // @[el2_lsu_dccm_ctl.scala 197:152]
|
|
wire _T_835 = io_lsu_pkt_d_bits_store & _T_834; // @[el2_lsu_dccm_ctl.scala 197:97]
|
|
wire _T_836 = io_lsu_pkt_d_bits_load | _T_835; // @[el2_lsu_dccm_ctl.scala 197:70]
|
|
wire _T_837 = io_lsu_pkt_d_valid & _T_836; // @[el2_lsu_dccm_ctl.scala 197:44]
|
|
wire lsu_dccm_rden_d = _T_837 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 197:191]
|
|
wire _T_838 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 200:63]
|
|
wire _T_839 = ~lsu_double_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 200:96]
|
|
wire _T_841 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[el2_lsu_dccm_ctl.scala 201:75]
|
|
wire _T_842 = _T_841 | io_ld_single_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 201:93]
|
|
wire _T_843 = ~_T_842; // @[el2_lsu_dccm_ctl.scala 201:57]
|
|
wire _T_846 = io_stbuf_addr_any[3:2] == io_lsu_addr_d[3:2]; // @[el2_lsu_dccm_ctl.scala 202:95]
|
|
wire _T_849 = io_stbuf_addr_any[3:2] == io_end_addr_d[3:2]; // @[el2_lsu_dccm_ctl.scala 203:76]
|
|
wire _T_850 = _T_846 | _T_849; // @[el2_lsu_dccm_ctl.scala 202:171]
|
|
wire _T_851 = ~_T_850; // @[el2_lsu_dccm_ctl.scala 202:24]
|
|
wire _T_852 = lsu_dccm_rden_d & _T_851; // @[el2_lsu_dccm_ctl.scala 202:22]
|
|
wire _T_853 = _T_843 | _T_852; // @[el2_lsu_dccm_ctl.scala 201:124]
|
|
wire _T_855 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[el2_lsu_dccm_ctl.scala 207:41]
|
|
wire [15:0] _T_862 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 211:8]
|
|
wire [15:0] _T_866 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[el2_lsu_dccm_ctl.scala 212:8]
|
|
wire [15:0] _T_872 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 215:8]
|
|
wire [15:0] _T_876 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[el2_lsu_dccm_ctl.scala 216:8]
|
|
wire [38:0] _T_884 = {io_sec_data_ecc_lo_r_ff,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_887 = {io_sec_data_ecc_hi_r_ff,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_888 = ld_single_ecc_error_lo_r_ff ? _T_884 : _T_887; // @[el2_lsu_dccm_ctl.scala 222:8]
|
|
wire [38:0] _T_892 = {io_dma_dccm_wdata_ecc_lo,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_895 = {io_stbuf_ecc_any,io_stbuf_data_any}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_896 = io_dma_dccm_wen ? _T_892 : _T_895; // @[el2_lsu_dccm_ctl.scala 224:8]
|
|
wire [38:0] _T_906 = ld_single_ecc_error_hi_r_ff ? _T_887 : _T_884; // @[el2_lsu_dccm_ctl.scala 228:8]
|
|
wire [38:0] _T_910 = {io_dma_dccm_wdata_ecc_hi,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_914 = io_dma_dccm_wen ? _T_910 : _T_895; // @[el2_lsu_dccm_ctl.scala 230:8]
|
|
wire [3:0] _T_917 = io_lsu_pkt_m_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_919 = io_lsu_pkt_m_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_920 = _T_919 & 4'h1; // @[el2_lsu_dccm_ctl.scala 234:94]
|
|
wire [3:0] _T_922 = io_lsu_pkt_m_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_923 = _T_922 & 4'h3; // @[el2_lsu_dccm_ctl.scala 235:38]
|
|
wire [3:0] _T_924 = _T_920 | _T_923; // @[el2_lsu_dccm_ctl.scala 234:107]
|
|
wire [3:0] _T_926 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_928 = _T_924 | _T_926; // @[el2_lsu_dccm_ctl.scala 235:51]
|
|
wire [3:0] store_byteen_m = _T_917 & _T_928; // @[el2_lsu_dccm_ctl.scala 234:58]
|
|
wire [3:0] _T_930 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_932 = io_lsu_pkt_r_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_933 = _T_932 & 4'h1; // @[el2_lsu_dccm_ctl.scala 238:94]
|
|
wire [3:0] _T_935 = io_lsu_pkt_r_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_936 = _T_935 & 4'h3; // @[el2_lsu_dccm_ctl.scala 239:38]
|
|
wire [3:0] _T_937 = _T_933 | _T_936; // @[el2_lsu_dccm_ctl.scala 238:107]
|
|
wire [3:0] _T_939 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_941 = _T_937 | _T_939; // @[el2_lsu_dccm_ctl.scala 239:51]
|
|
wire [3:0] store_byteen_r = _T_930 & _T_941; // @[el2_lsu_dccm_ctl.scala 238:58]
|
|
wire [6:0] _GEN_44 = {{3'd0}, store_byteen_m}; // @[el2_lsu_dccm_ctl.scala 242:45]
|
|
wire [6:0] _T_944 = _GEN_44 << io_lsu_addr_m[1:0]; // @[el2_lsu_dccm_ctl.scala 242:45]
|
|
wire [6:0] _GEN_45 = {{3'd0}, store_byteen_r}; // @[el2_lsu_dccm_ctl.scala 244:45]
|
|
wire [6:0] _T_947 = _GEN_45 << io_lsu_addr_r[1:0]; // @[el2_lsu_dccm_ctl.scala 244:45]
|
|
wire _T_950 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[el2_lsu_dccm_ctl.scala 247:67]
|
|
wire dccm_wr_bypass_d_m_lo = _T_950 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 247:101]
|
|
wire _T_953 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[el2_lsu_dccm_ctl.scala 248:67]
|
|
wire dccm_wr_bypass_d_m_hi = _T_953 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 248:101]
|
|
wire _T_956 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 250:67]
|
|
wire dccm_wr_bypass_d_r_lo = _T_956 & io_addr_in_dccm_r; // @[el2_lsu_dccm_ctl.scala 250:101]
|
|
wire _T_959 = io_stbuf_addr_any[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 251:67]
|
|
wire dccm_wr_bypass_d_r_hi = _T_959 & io_addr_in_dccm_r; // @[el2_lsu_dccm_ctl.scala 251:101]
|
|
wire [63:0] _T_962 = {32'h0,io_store_data_m}; // @[Cat.scala 29:58]
|
|
wire [126:0] _GEN_47 = {{63'd0}, _T_962}; // @[el2_lsu_dccm_ctl.scala 280:72]
|
|
wire [126:0] _T_965 = _GEN_47 << _T_762; // @[el2_lsu_dccm_ctl.scala 280:72]
|
|
wire [63:0] store_data_pre_m = _T_965[63:0]; // @[el2_lsu_dccm_ctl.scala 280:29]
|
|
wire [31:0] store_data_hi_m = store_data_pre_m[63:32]; // @[el2_lsu_dccm_ctl.scala 281:48]
|
|
wire [31:0] store_data_lo_m = store_data_pre_m[31:0]; // @[el2_lsu_dccm_ctl.scala 282:48]
|
|
wire [7:0] store_byteen_ext_m = {{1'd0}, _T_944}; // @[el2_lsu_dccm_ctl.scala 242:22]
|
|
wire _T_971 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo; // @[el2_lsu_dccm_ctl.scala 283:211]
|
|
wire [7:0] _T_975 = _T_971 ? io_stbuf_data_any[7:0] : io_sec_data_lo_m[7:0]; // @[el2_lsu_dccm_ctl.scala 283:185]
|
|
wire [7:0] _T_976 = store_byteen_ext_m[0] ? store_data_lo_m[7:0] : _T_975; // @[el2_lsu_dccm_ctl.scala 283:120]
|
|
wire [7:0] _T_980 = {{4'd0}, _T_976[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_982 = {_T_976[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_984 = _T_982 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_985 = _T_980 | _T_984; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_48 = {{2'd0}, _T_985[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_990 = _GEN_48 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_992 = {_T_985[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_994 = _T_992 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_995 = _T_990 | _T_994; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_49 = {{1'd0}, _T_995[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1000 = _GEN_49 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1002 = {_T_995[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1004 = _T_1002 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1005 = _T_1000 | _T_1004; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_1013 = _T_971 ? io_stbuf_data_any[15:8] : io_sec_data_lo_m[15:8]; // @[el2_lsu_dccm_ctl.scala 283:185]
|
|
wire [7:0] _T_1014 = store_byteen_ext_m[1] ? store_data_lo_m[15:8] : _T_1013; // @[el2_lsu_dccm_ctl.scala 283:120]
|
|
wire [7:0] _T_1018 = {{4'd0}, _T_1014[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1020 = {_T_1014[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1022 = _T_1020 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1023 = _T_1018 | _T_1022; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_50 = {{2'd0}, _T_1023[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1028 = _GEN_50 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1030 = {_T_1023[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1032 = _T_1030 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1033 = _T_1028 | _T_1032; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_51 = {{1'd0}, _T_1033[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1038 = _GEN_51 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1040 = {_T_1033[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1042 = _T_1040 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1043 = _T_1038 | _T_1042; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_1051 = _T_971 ? io_stbuf_data_any[23:16] : io_sec_data_lo_m[23:16]; // @[el2_lsu_dccm_ctl.scala 283:185]
|
|
wire [7:0] _T_1052 = store_byteen_ext_m[2] ? store_data_lo_m[23:16] : _T_1051; // @[el2_lsu_dccm_ctl.scala 283:120]
|
|
wire [7:0] _T_1056 = {{4'd0}, _T_1052[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1058 = {_T_1052[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1060 = _T_1058 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1061 = _T_1056 | _T_1060; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_52 = {{2'd0}, _T_1061[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1066 = _GEN_52 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1068 = {_T_1061[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1070 = _T_1068 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1071 = _T_1066 | _T_1070; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_53 = {{1'd0}, _T_1071[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1076 = _GEN_53 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1078 = {_T_1071[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1080 = _T_1078 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1081 = _T_1076 | _T_1080; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_1089 = _T_971 ? io_stbuf_data_any[31:24] : io_sec_data_lo_m[31:24]; // @[el2_lsu_dccm_ctl.scala 283:185]
|
|
wire [7:0] _T_1090 = store_byteen_ext_m[3] ? store_data_lo_m[31:24] : _T_1089; // @[el2_lsu_dccm_ctl.scala 283:120]
|
|
wire [7:0] _T_1094 = {{4'd0}, _T_1090[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1096 = {_T_1090[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1098 = _T_1096 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1099 = _T_1094 | _T_1098; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_54 = {{2'd0}, _T_1099[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1104 = _GEN_54 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1106 = {_T_1099[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1108 = _T_1106 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1109 = _T_1104 | _T_1108; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_55 = {{1'd0}, _T_1109[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1114 = _GEN_55 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1116 = {_T_1109[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1118 = _T_1116 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1119 = _T_1114 | _T_1118; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _T_1123 = {_T_1005,_T_1043,_T_1081,_T_1119}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1127 = {{16'd0}, _T_1123[31:16]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1129 = {_T_1123[15:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1131 = _T_1129 & 32'hffff0000; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1132 = _T_1127 | _T_1131; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_56 = {{8'd0}, _T_1132[31:8]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1137 = _GEN_56 & 32'hff00ff; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1139 = {_T_1132[23:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1141 = _T_1139 & 32'hff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1142 = _T_1137 | _T_1141; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_57 = {{4'd0}, _T_1142[31:4]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1147 = _GEN_57 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1149 = {_T_1142[27:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1151 = _T_1149 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1152 = _T_1147 | _T_1151; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_58 = {{2'd0}, _T_1152[31:2]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1157 = _GEN_58 & 32'h33333333; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1159 = {_T_1152[29:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1161 = _T_1159 & 32'hcccccccc; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1162 = _T_1157 | _T_1161; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_59 = {{1'd0}, _T_1162[31:1]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1167 = _GEN_59 & 32'h55555555; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1169 = {_T_1162[30:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1171 = _T_1169 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
|
|
reg [31:0] _T_1173; // @[el2_lsu_dccm_ctl.scala 283:72]
|
|
wire _T_1177 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi; // @[el2_lsu_dccm_ctl.scala 284:211]
|
|
wire [7:0] _T_1181 = _T_1177 ? io_stbuf_data_any[7:0] : io_sec_data_hi_m[7:0]; // @[el2_lsu_dccm_ctl.scala 284:185]
|
|
wire [7:0] _T_1182 = store_byteen_ext_m[4] ? store_data_hi_m[7:0] : _T_1181; // @[el2_lsu_dccm_ctl.scala 284:120]
|
|
wire [7:0] _T_1186 = {{4'd0}, _T_1182[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1188 = {_T_1182[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1190 = _T_1188 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1191 = _T_1186 | _T_1190; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_60 = {{2'd0}, _T_1191[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1196 = _GEN_60 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1198 = {_T_1191[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1200 = _T_1198 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1201 = _T_1196 | _T_1200; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_61 = {{1'd0}, _T_1201[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1206 = _GEN_61 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1208 = {_T_1201[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1210 = _T_1208 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1211 = _T_1206 | _T_1210; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_1219 = _T_1177 ? io_stbuf_data_any[15:8] : io_sec_data_hi_m[15:8]; // @[el2_lsu_dccm_ctl.scala 284:185]
|
|
wire [7:0] _T_1220 = store_byteen_ext_m[5] ? store_data_hi_m[15:8] : _T_1219; // @[el2_lsu_dccm_ctl.scala 284:120]
|
|
wire [7:0] _T_1224 = {{4'd0}, _T_1220[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1226 = {_T_1220[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1228 = _T_1226 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1229 = _T_1224 | _T_1228; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_62 = {{2'd0}, _T_1229[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1234 = _GEN_62 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1236 = {_T_1229[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1238 = _T_1236 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1239 = _T_1234 | _T_1238; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_63 = {{1'd0}, _T_1239[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1244 = _GEN_63 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1246 = {_T_1239[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1248 = _T_1246 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1249 = _T_1244 | _T_1248; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_1257 = _T_1177 ? io_stbuf_data_any[23:16] : io_sec_data_hi_m[23:16]; // @[el2_lsu_dccm_ctl.scala 284:185]
|
|
wire [7:0] _T_1258 = store_byteen_ext_m[6] ? store_data_hi_m[23:16] : _T_1257; // @[el2_lsu_dccm_ctl.scala 284:120]
|
|
wire [7:0] _T_1262 = {{4'd0}, _T_1258[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1264 = {_T_1258[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1266 = _T_1264 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1267 = _T_1262 | _T_1266; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_64 = {{2'd0}, _T_1267[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1272 = _GEN_64 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1274 = {_T_1267[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1276 = _T_1274 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1277 = _T_1272 | _T_1276; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_65 = {{1'd0}, _T_1277[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1282 = _GEN_65 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1284 = {_T_1277[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1286 = _T_1284 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1287 = _T_1282 | _T_1286; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_1295 = _T_1177 ? io_stbuf_data_any[31:24] : io_sec_data_hi_m[31:24]; // @[el2_lsu_dccm_ctl.scala 284:185]
|
|
wire [7:0] _T_1296 = store_byteen_ext_m[7] ? store_data_hi_m[31:24] : _T_1295; // @[el2_lsu_dccm_ctl.scala 284:120]
|
|
wire [7:0] _T_1300 = {{4'd0}, _T_1296[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1302 = {_T_1296[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1304 = _T_1302 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1305 = _T_1300 | _T_1304; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_66 = {{2'd0}, _T_1305[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1310 = _GEN_66 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1312 = {_T_1305[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1314 = _T_1312 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1315 = _T_1310 | _T_1314; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_67 = {{1'd0}, _T_1315[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1320 = _GEN_67 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1322 = {_T_1315[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1324 = _T_1322 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1325 = _T_1320 | _T_1324; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _T_1329 = {_T_1211,_T_1249,_T_1287,_T_1325}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1333 = {{16'd0}, _T_1329[31:16]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1335 = {_T_1329[15:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1337 = _T_1335 & 32'hffff0000; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1338 = _T_1333 | _T_1337; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_68 = {{8'd0}, _T_1338[31:8]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1343 = _GEN_68 & 32'hff00ff; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1345 = {_T_1338[23:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1347 = _T_1345 & 32'hff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1348 = _T_1343 | _T_1347; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_69 = {{4'd0}, _T_1348[31:4]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1353 = _GEN_69 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1355 = {_T_1348[27:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1357 = _T_1355 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1358 = _T_1353 | _T_1357; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_70 = {{2'd0}, _T_1358[31:2]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1363 = _GEN_70 & 32'h33333333; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1365 = {_T_1358[29:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1367 = _T_1365 & 32'hcccccccc; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1368 = _T_1363 | _T_1367; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_71 = {{1'd0}, _T_1368[31:1]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1373 = _GEN_71 & 32'h55555555; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1375 = {_T_1368[30:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1377 = _T_1375 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
|
|
reg [31:0] _T_1379; // @[el2_lsu_dccm_ctl.scala 284:72]
|
|
wire _T_1380 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[el2_lsu_dccm_ctl.scala 285:105]
|
|
wire [7:0] store_byteen_ext_r = {{1'd0}, _T_947}; // @[el2_lsu_dccm_ctl.scala 244:22]
|
|
wire _T_1382 = ~store_byteen_ext_r[0]; // @[el2_lsu_dccm_ctl.scala 285:131]
|
|
wire _T_1383 = _T_1380 & _T_1382; // @[el2_lsu_dccm_ctl.scala 285:129]
|
|
wire [7:0] _T_1387 = _T_1383 ? io_stbuf_data_any[7:0] : io_store_data_lo_r[7:0]; // @[el2_lsu_dccm_ctl.scala 285:79]
|
|
wire [7:0] _T_1391 = {{4'd0}, _T_1387[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1393 = {_T_1387[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1395 = _T_1393 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1396 = _T_1391 | _T_1395; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_72 = {{2'd0}, _T_1396[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1401 = _GEN_72 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1403 = {_T_1396[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1405 = _T_1403 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1406 = _T_1401 | _T_1405; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_73 = {{1'd0}, _T_1406[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1411 = _GEN_73 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1413 = {_T_1406[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1415 = _T_1413 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1416 = _T_1411 | _T_1415; // @[Bitwise.scala 103:39]
|
|
wire _T_1419 = ~store_byteen_ext_r[1]; // @[el2_lsu_dccm_ctl.scala 285:131]
|
|
wire _T_1420 = _T_1380 & _T_1419; // @[el2_lsu_dccm_ctl.scala 285:129]
|
|
wire [7:0] _T_1424 = _T_1420 ? io_stbuf_data_any[15:8] : io_store_data_lo_r[15:8]; // @[el2_lsu_dccm_ctl.scala 285:79]
|
|
wire [7:0] _T_1428 = {{4'd0}, _T_1424[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1430 = {_T_1424[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1432 = _T_1430 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1433 = _T_1428 | _T_1432; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_74 = {{2'd0}, _T_1433[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1438 = _GEN_74 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1440 = {_T_1433[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1442 = _T_1440 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1443 = _T_1438 | _T_1442; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_75 = {{1'd0}, _T_1443[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1448 = _GEN_75 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1450 = {_T_1443[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1452 = _T_1450 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1453 = _T_1448 | _T_1452; // @[Bitwise.scala 103:39]
|
|
wire _T_1456 = ~store_byteen_ext_r[2]; // @[el2_lsu_dccm_ctl.scala 285:131]
|
|
wire _T_1457 = _T_1380 & _T_1456; // @[el2_lsu_dccm_ctl.scala 285:129]
|
|
wire [7:0] _T_1461 = _T_1457 ? io_stbuf_data_any[23:16] : io_store_data_lo_r[23:16]; // @[el2_lsu_dccm_ctl.scala 285:79]
|
|
wire [7:0] _T_1465 = {{4'd0}, _T_1461[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1467 = {_T_1461[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1469 = _T_1467 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1470 = _T_1465 | _T_1469; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_76 = {{2'd0}, _T_1470[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1475 = _GEN_76 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1477 = {_T_1470[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1479 = _T_1477 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1480 = _T_1475 | _T_1479; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_77 = {{1'd0}, _T_1480[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1485 = _GEN_77 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1487 = {_T_1480[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1489 = _T_1487 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1490 = _T_1485 | _T_1489; // @[Bitwise.scala 103:39]
|
|
wire _T_1493 = ~store_byteen_ext_r[3]; // @[el2_lsu_dccm_ctl.scala 285:131]
|
|
wire _T_1494 = _T_1380 & _T_1493; // @[el2_lsu_dccm_ctl.scala 285:129]
|
|
wire [7:0] _T_1498 = _T_1494 ? io_stbuf_data_any[31:24] : io_store_data_lo_r[31:24]; // @[el2_lsu_dccm_ctl.scala 285:79]
|
|
wire [7:0] _T_1502 = {{4'd0}, _T_1498[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1504 = {_T_1498[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1506 = _T_1504 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1507 = _T_1502 | _T_1506; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_78 = {{2'd0}, _T_1507[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1512 = _GEN_78 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1514 = {_T_1507[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1516 = _T_1514 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1517 = _T_1512 | _T_1516; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_79 = {{1'd0}, _T_1517[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1522 = _GEN_79 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1524 = {_T_1517[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1526 = _T_1524 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1527 = _T_1522 | _T_1526; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _T_1531 = {_T_1416,_T_1453,_T_1490,_T_1527}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1535 = {{16'd0}, _T_1531[31:16]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1537 = {_T_1531[15:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1539 = _T_1537 & 32'hffff0000; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1540 = _T_1535 | _T_1539; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_80 = {{8'd0}, _T_1540[31:8]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1545 = _GEN_80 & 32'hff00ff; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1547 = {_T_1540[23:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1549 = _T_1547 & 32'hff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1550 = _T_1545 | _T_1549; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_81 = {{4'd0}, _T_1550[31:4]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1555 = _GEN_81 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1557 = {_T_1550[27:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1559 = _T_1557 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1560 = _T_1555 | _T_1559; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_82 = {{2'd0}, _T_1560[31:2]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1565 = _GEN_82 & 32'h33333333; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1567 = {_T_1560[29:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1569 = _T_1567 & 32'hcccccccc; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1570 = _T_1565 | _T_1569; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_83 = {{1'd0}, _T_1570[31:1]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1575 = _GEN_83 & 32'h55555555; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1577 = {_T_1570[30:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1579 = _T_1577 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
|
|
wire _T_1581 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi; // @[el2_lsu_dccm_ctl.scala 286:105]
|
|
wire _T_1583 = ~store_byteen_ext_r[4]; // @[el2_lsu_dccm_ctl.scala 286:131]
|
|
wire _T_1584 = _T_1581 & _T_1583; // @[el2_lsu_dccm_ctl.scala 286:129]
|
|
wire [7:0] _T_1588 = _T_1584 ? io_stbuf_data_any[7:0] : io_store_data_hi_r[7:0]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
|
wire [7:0] _T_1592 = {{4'd0}, _T_1588[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1594 = {_T_1588[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1596 = _T_1594 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1597 = _T_1592 | _T_1596; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_84 = {{2'd0}, _T_1597[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1602 = _GEN_84 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1604 = {_T_1597[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1606 = _T_1604 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1607 = _T_1602 | _T_1606; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_85 = {{1'd0}, _T_1607[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1612 = _GEN_85 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1614 = {_T_1607[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1616 = _T_1614 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1617 = _T_1612 | _T_1616; // @[Bitwise.scala 103:39]
|
|
wire _T_1620 = ~store_byteen_ext_r[5]; // @[el2_lsu_dccm_ctl.scala 286:131]
|
|
wire _T_1621 = _T_1581 & _T_1620; // @[el2_lsu_dccm_ctl.scala 286:129]
|
|
wire [7:0] _T_1625 = _T_1621 ? io_stbuf_data_any[15:8] : io_store_data_hi_r[15:8]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
|
wire [7:0] _T_1629 = {{4'd0}, _T_1625[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1631 = {_T_1625[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1633 = _T_1631 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1634 = _T_1629 | _T_1633; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_86 = {{2'd0}, _T_1634[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1639 = _GEN_86 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1641 = {_T_1634[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1643 = _T_1641 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1644 = _T_1639 | _T_1643; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_87 = {{1'd0}, _T_1644[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1649 = _GEN_87 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1651 = {_T_1644[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1653 = _T_1651 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1654 = _T_1649 | _T_1653; // @[Bitwise.scala 103:39]
|
|
wire _T_1657 = ~store_byteen_ext_r[6]; // @[el2_lsu_dccm_ctl.scala 286:131]
|
|
wire _T_1658 = _T_1581 & _T_1657; // @[el2_lsu_dccm_ctl.scala 286:129]
|
|
wire [7:0] _T_1662 = _T_1658 ? io_stbuf_data_any[23:16] : io_store_data_hi_r[23:16]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
|
wire [7:0] _T_1666 = {{4'd0}, _T_1662[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1668 = {_T_1662[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1670 = _T_1668 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1671 = _T_1666 | _T_1670; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_88 = {{2'd0}, _T_1671[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1676 = _GEN_88 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1678 = {_T_1671[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1680 = _T_1678 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1681 = _T_1676 | _T_1680; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_89 = {{1'd0}, _T_1681[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1686 = _GEN_89 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1688 = {_T_1681[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1690 = _T_1688 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1691 = _T_1686 | _T_1690; // @[Bitwise.scala 103:39]
|
|
wire _T_1694 = ~store_byteen_ext_r[7]; // @[el2_lsu_dccm_ctl.scala 286:131]
|
|
wire _T_1695 = _T_1581 & _T_1694; // @[el2_lsu_dccm_ctl.scala 286:129]
|
|
wire [7:0] _T_1699 = _T_1695 ? io_stbuf_data_any[31:24] : io_store_data_hi_r[31:24]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
|
wire [7:0] _T_1703 = {{4'd0}, _T_1699[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1705 = {_T_1699[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1707 = _T_1705 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1708 = _T_1703 | _T_1707; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_90 = {{2'd0}, _T_1708[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1713 = _GEN_90 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1715 = {_T_1708[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1717 = _T_1715 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1718 = _T_1713 | _T_1717; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_91 = {{1'd0}, _T_1718[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1723 = _GEN_91 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1725 = {_T_1718[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1727 = _T_1725 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1728 = _T_1723 | _T_1727; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _T_1732 = {_T_1617,_T_1654,_T_1691,_T_1728}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1736 = {{16'd0}, _T_1732[31:16]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1738 = {_T_1732[15:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1740 = _T_1738 & 32'hffff0000; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1741 = _T_1736 | _T_1740; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_92 = {{8'd0}, _T_1741[31:8]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1746 = _GEN_92 & 32'hff00ff; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1748 = {_T_1741[23:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1750 = _T_1748 & 32'hff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1751 = _T_1746 | _T_1750; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_93 = {{4'd0}, _T_1751[31:4]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1756 = _GEN_93 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1758 = {_T_1751[27:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1760 = _T_1758 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1761 = _T_1756 | _T_1760; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_94 = {{2'd0}, _T_1761[31:2]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1766 = _GEN_94 & 32'h33333333; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1768 = {_T_1761[29:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1770 = _T_1768 & 32'hcccccccc; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1771 = _T_1766 | _T_1770; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_95 = {{1'd0}, _T_1771[31:1]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1776 = _GEN_95 & 32'h55555555; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1778 = {_T_1771[30:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1780 = _T_1778 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_1784 = {io_store_data_hi_r,io_store_data_lo_r}; // @[Cat.scala 29:58]
|
|
wire [3:0] _GEN_96 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[el2_lsu_dccm_ctl.scala 287:94]
|
|
wire [5:0] _T_1786 = 4'h8 * _GEN_96; // @[el2_lsu_dccm_ctl.scala 287:94]
|
|
wire [63:0] _T_1787 = _T_1784 >> _T_1786; // @[el2_lsu_dccm_ctl.scala 287:88]
|
|
wire [7:0] _T_1790 = store_byteen_r[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1793 = store_byteen_r[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1796 = store_byteen_r[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1799 = store_byteen_r[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1803 = {_T_1790,_T_1793,_T_1796,_T_1799}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1807 = {{16'd0}, _T_1803[31:16]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1809 = {_T_1803[15:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1811 = _T_1809 & 32'hffff0000; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1812 = _T_1807 | _T_1811; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_97 = {{8'd0}, _T_1812[31:8]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1817 = _GEN_97 & 32'hff00ff; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1819 = {_T_1812[23:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1821 = _T_1819 & 32'hff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1822 = _T_1817 | _T_1821; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_98 = {{4'd0}, _T_1822[31:4]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1827 = _GEN_98 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1829 = {_T_1822[27:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1831 = _T_1829 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1832 = _T_1827 | _T_1831; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_99 = {{2'd0}, _T_1832[31:2]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1837 = _GEN_99 & 32'h33333333; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1839 = {_T_1832[29:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1841 = _T_1839 & 32'hcccccccc; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1842 = _T_1837 | _T_1841; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_100 = {{1'd0}, _T_1842[31:1]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1847 = _GEN_100 & 32'h55555555; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1849 = {_T_1842[30:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1851 = _T_1849 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1852 = _T_1847 | _T_1851; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_101 = {{32'd0}, _T_1852}; // @[el2_lsu_dccm_ctl.scala 287:115]
|
|
wire [63:0] _T_1853 = _T_1787 & _GEN_101; // @[el2_lsu_dccm_ctl.scala 287:115]
|
|
wire _T_1858 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[el2_lsu_dccm_ctl.scala 294:50]
|
|
wire _T_1859 = _T_1858 & io_addr_in_pic_r; // @[el2_lsu_dccm_ctl.scala 294:76]
|
|
wire _T_1860 = _T_1859 & io_lsu_commit_r; // @[el2_lsu_dccm_ctl.scala 294:95]
|
|
wire _T_1862 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_load; // @[el2_lsu_dccm_ctl.scala 295:50]
|
|
wire _T_1864 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_store; // @[el2_lsu_dccm_ctl.scala 296:50]
|
|
wire [31:0] _T_1868 = {17'h0,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58]
|
|
wire [14:0] _T_1874 = io_dma_pic_wen ? io_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[el2_lsu_dccm_ctl.scala 298:85]
|
|
wire [31:0] _T_1875 = {17'h0,_T_1874}; // @[Cat.scala 29:58]
|
|
reg _T_1882; // @[el2_lsu_dccm_ctl.scala 303:61]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
assign io_lsu_ld_data_corr_r = _T_2[31:0]; // @[el2_lsu_dccm_ctl.scala 171:28]
|
|
assign io_dccm_rdata_hi_m = io_dccm_rd_data_hi[31:0]; // @[el2_lsu_dccm_ctl.scala 290:27]
|
|
assign io_dccm_rdata_lo_m = io_dccm_rd_data_lo[31:0]; // @[el2_lsu_dccm_ctl.scala 289:27]
|
|
assign io_dccm_data_ecc_hi_m = io_dccm_rd_data_hi[38:32]; // @[el2_lsu_dccm_ctl.scala 292:27]
|
|
assign io_dccm_data_ecc_lo_m = io_dccm_rd_data_lo[38:32]; // @[el2_lsu_dccm_ctl.scala 291:27]
|
|
assign io_lsu_ld_data_m = _T_763[31:0]; // @[el2_lsu_dccm_ctl.scala 174:28]
|
|
assign io_store_data_hi_r = _T_1379; // @[el2_lsu_dccm_ctl.scala 284:29]
|
|
assign io_store_data_lo_r = _T_1173; // @[el2_lsu_dccm_ctl.scala 283:29]
|
|
assign io_store_datafn_hi_r = _T_1776 | _T_1780; // @[el2_lsu_dccm_ctl.scala 286:29]
|
|
assign io_store_datafn_lo_r = _T_1575 | _T_1579; // @[el2_lsu_dccm_ctl.scala 285:29]
|
|
assign io_store_data_r = _T_1853[31:0]; // @[el2_lsu_dccm_ctl.scala 287:29]
|
|
assign io_ld_single_ecc_error_r = _T_815 & _T_816; // @[el2_lsu_dccm_ctl.scala 187:34]
|
|
assign io_ld_single_ecc_error_r_ff = _T_838 & _T_839; // @[el2_lsu_dccm_ctl.scala 200:31]
|
|
assign io_picm_mask_data_m = picm_rd_data_m[31:0]; // @[el2_lsu_dccm_ctl.scala 299:27]
|
|
assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_853; // @[el2_lsu_dccm_ctl.scala 201:31]
|
|
assign io_lsu_dccm_rden_m = _T_1882; // @[el2_lsu_dccm_ctl.scala 303:24]
|
|
assign io_dccm_dma_rvalid = _T & io_lsu_pkt_m_bits_dma; // @[el2_lsu_dccm_ctl.scala 161:28]
|
|
assign io_dccm_dma_ecc_error = io_lsu_double_ecc_error_m; // @[el2_lsu_dccm_ctl.scala 162:28]
|
|
assign io_dccm_dma_rtag = io_dma_mem_tag_m; // @[el2_lsu_dccm_ctl.scala 164:28]
|
|
assign io_dccm_dma_rdata = _T_376 | _T_380; // @[el2_lsu_dccm_ctl.scala 163:28]
|
|
assign io_dccm_wren = _T_855 | io_ld_single_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 207:22]
|
|
assign io_dccm_rden = lsu_dccm_rden_d & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 208:22]
|
|
assign io_dccm_wr_addr_lo = io_ld_single_ecc_error_r_ff ? _T_862 : _T_866; // @[el2_lsu_dccm_ctl.scala 210:22]
|
|
assign io_dccm_wr_data_lo = io_ld_single_ecc_error_r_ff ? _T_888 : _T_896; // @[el2_lsu_dccm_ctl.scala 221:22]
|
|
assign io_dccm_rd_addr_lo = io_lsu_addr_d[15:0]; // @[el2_lsu_dccm_ctl.scala 218:22]
|
|
assign io_dccm_wr_addr_hi = io_ld_single_ecc_error_r_ff ? _T_872 : _T_876; // @[el2_lsu_dccm_ctl.scala 214:22]
|
|
assign io_dccm_wr_data_hi = io_ld_single_ecc_error_r_ff ? _T_906 : _T_914; // @[el2_lsu_dccm_ctl.scala 227:22]
|
|
assign io_dccm_rd_addr_hi = io_end_addr_d; // @[el2_lsu_dccm_ctl.scala 219:22]
|
|
assign io_picm_wren = _T_1860 | io_dma_pic_wen; // @[el2_lsu_dccm_ctl.scala 294:27]
|
|
assign io_picm_rden = _T_1862 & io_addr_in_pic_d; // @[el2_lsu_dccm_ctl.scala 295:27]
|
|
assign io_picm_mken = _T_1864 & io_addr_in_pic_d; // @[el2_lsu_dccm_ctl.scala 296:27]
|
|
assign io_picm_rdaddr = 32'hf00c0000 | _T_1868; // @[el2_lsu_dccm_ctl.scala 297:27]
|
|
assign io_picm_wraddr = 32'hf00c0000 | _T_1875; // @[el2_lsu_dccm_ctl.scala 298:27]
|
|
assign io_picm_wr_data = io_dma_pic_wen ? io_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[el2_lsu_dccm_ctl.scala 300:27]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {2{`RANDOM}};
|
|
_T_2 = _RAND_0[63:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
lsu_double_ecc_error_r_ff = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
ld_single_ecc_error_hi_r_ff = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
ld_single_ecc_error_lo_r_ff = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
ld_sec_addr_hi_r_ff = _RAND_4[15:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
ld_sec_addr_lo_r_ff = _RAND_5[15:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_1173 = _RAND_6[31:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_1379 = _RAND_7[31:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
_T_1882 = _RAND_8[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_2 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_double_ecc_error_r_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ld_single_ecc_error_hi_r_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ld_single_ecc_error_lo_r_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ld_sec_addr_hi_r_ff = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
ld_sec_addr_lo_r_ff = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1173 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1379 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1882 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_2 <= 64'h0;
|
|
end else begin
|
|
_T_2 <= lsu_rdata_corr_m >> _T_762;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_double_ecc_error_r_ff <= 1'h0;
|
|
end else begin
|
|
lsu_double_ecc_error_r_ff <= io_lsu_double_ecc_error_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ld_single_ecc_error_hi_r_ff <= 1'h0;
|
|
end else begin
|
|
ld_single_ecc_error_hi_r_ff <= _T_822 & _T_823;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ld_single_ecc_error_lo_r_ff <= 1'h0;
|
|
end else begin
|
|
ld_single_ecc_error_lo_r_ff <= _T_819 & _T_820;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ld_sec_addr_hi_r_ff <= 16'h0;
|
|
end else begin
|
|
ld_sec_addr_hi_r_ff <= io_end_addr_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ld_sec_addr_lo_r_ff <= 16'h0;
|
|
end else begin
|
|
ld_sec_addr_lo_r_ff <= io_lsu_addr_r[15:0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_store_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1173 <= 32'h0;
|
|
end else begin
|
|
_T_1173 <= _T_1167 | _T_1171;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_store_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1379 <= 32'h0;
|
|
end else begin
|
|
_T_1379 <= _T_1373 | _T_1377;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1882 <= 1'h0;
|
|
end else begin
|
|
_T_1882 <= _T_837 & io_addr_in_dccm_d;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_lsu_stbuf(
|
|
input clock,
|
|
input reset,
|
|
input io_lsu_c1_m_clk,
|
|
input io_lsu_c1_r_clk,
|
|
input io_lsu_stbuf_c1_clk,
|
|
input io_lsu_free_c2_clk,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_store,
|
|
input io_lsu_pkt_m_bits_dma,
|
|
input io_lsu_pkt_r_valid,
|
|
input io_lsu_pkt_r_bits_by,
|
|
input io_lsu_pkt_r_bits_half,
|
|
input io_lsu_pkt_r_bits_word,
|
|
input io_lsu_pkt_r_bits_dword,
|
|
input io_lsu_pkt_r_bits_store,
|
|
input io_lsu_pkt_r_bits_dma,
|
|
input io_store_stbuf_reqvld_r,
|
|
input io_lsu_commit_r,
|
|
input io_dec_lsu_valid_raw_d,
|
|
input [31:0] io_store_data_hi_r,
|
|
input [31:0] io_store_data_lo_r,
|
|
input [31:0] io_store_datafn_hi_r,
|
|
input [31:0] io_store_datafn_lo_r,
|
|
input io_lsu_stbuf_commit_any,
|
|
input [15:0] io_lsu_addr_d,
|
|
input [31:0] io_lsu_addr_m,
|
|
input [31:0] io_lsu_addr_r,
|
|
input [15:0] io_end_addr_d,
|
|
input [31:0] io_end_addr_m,
|
|
input [31:0] io_end_addr_r,
|
|
input io_addr_in_dccm_m,
|
|
input io_addr_in_dccm_r,
|
|
input io_scan_mode,
|
|
output io_stbuf_reqvld_any,
|
|
output io_stbuf_reqvld_flushed_any,
|
|
output [15:0] io_stbuf_addr_any,
|
|
output [31:0] io_stbuf_data_any,
|
|
output io_lsu_stbuf_full_any,
|
|
output io_lsu_stbuf_empty_any,
|
|
output io_ldst_stbuf_reqvld_r,
|
|
output [31:0] io_stbuf_fwddata_hi_m,
|
|
output [31:0] io_stbuf_fwddata_lo_m,
|
|
output [3:0] io_stbuf_fwdbyteen_hi_m,
|
|
output [3:0] io_stbuf_fwdbyteen_lo_m
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire [1:0] _T_5 = io_lsu_pkt_r_bits_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_6 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_7 = io_lsu_pkt_r_bits_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_10 = {{1'd0}, io_lsu_pkt_r_bits_by}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_8 = _GEN_10 | _T_5; // @[Mux.scala 27:72]
|
|
wire [3:0] _GEN_11 = {{2'd0}, _T_8}; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_9 = _GEN_11 | _T_6; // @[Mux.scala 27:72]
|
|
wire [7:0] _GEN_12 = {{4'd0}, _T_9}; // @[Mux.scala 27:72]
|
|
wire [7:0] ldst_byteen_r = _GEN_12 | _T_7; // @[Mux.scala 27:72]
|
|
wire ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[el2_lsu_stbuf.scala 117:39]
|
|
reg ldst_dual_r; // @[el2_lsu_stbuf.scala 171:52]
|
|
wire dual_stbuf_write_r = ldst_dual_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 118:40]
|
|
wire [10:0] _GEN_13 = {{3'd0}, ldst_byteen_r}; // @[el2_lsu_stbuf.scala 120:39]
|
|
wire [10:0] _T_14 = _GEN_13 << io_lsu_addr_r[1:0]; // @[el2_lsu_stbuf.scala 120:39]
|
|
wire [7:0] store_byteen_ext_r = _T_14[7:0]; // @[el2_lsu_stbuf.scala 120:22]
|
|
wire [3:0] _T_17 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_17; // @[el2_lsu_stbuf.scala 121:52]
|
|
wire [3:0] store_byteen_lo_r = store_byteen_ext_r[3:0] & _T_17; // @[el2_lsu_stbuf.scala 122:52]
|
|
reg [1:0] RdPtr; // @[Reg.scala 27:20]
|
|
wire [1:0] RdPtrPlus1 = RdPtr + 2'h1; // @[el2_lsu_stbuf.scala 124:26]
|
|
reg [1:0] WrPtr; // @[Reg.scala 27:20]
|
|
wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[el2_lsu_stbuf.scala 125:26]
|
|
wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[el2_lsu_stbuf.scala 126:26]
|
|
reg [15:0] stbuf_addr_0; // @[el2_lib.scala 514:16]
|
|
wire _T_27 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 130:120]
|
|
reg _T_588; // @[el2_lsu_stbuf.scala 163:88]
|
|
reg _T_580; // @[el2_lsu_stbuf.scala 163:88]
|
|
reg _T_572; // @[el2_lsu_stbuf.scala 163:88]
|
|
reg _T_564; // @[el2_lsu_stbuf.scala 163:88]
|
|
wire [3:0] stbuf_vld = {_T_588,_T_580,_T_572,_T_564}; // @[Cat.scala 29:58]
|
|
wire _T_29 = _T_27 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 130:179]
|
|
reg _T_623; // @[el2_lsu_stbuf.scala 164:92]
|
|
reg _T_615; // @[el2_lsu_stbuf.scala 164:92]
|
|
reg _T_607; // @[el2_lsu_stbuf.scala 164:92]
|
|
reg _T_599; // @[el2_lsu_stbuf.scala 164:92]
|
|
wire [3:0] stbuf_dma_kill = {_T_623,_T_615,_T_607,_T_599}; // @[Cat.scala 29:58]
|
|
wire _T_31 = ~stbuf_dma_kill[0]; // @[el2_lsu_stbuf.scala 130:197]
|
|
wire _T_32 = _T_29 & _T_31; // @[el2_lsu_stbuf.scala 130:195]
|
|
wire _T_212 = io_lsu_stbuf_commit_any | io_stbuf_reqvld_flushed_any; // @[el2_lsu_stbuf.scala 141:78]
|
|
wire _T_213 = 2'h3 == RdPtr; // @[el2_lsu_stbuf.scala 141:121]
|
|
wire _T_215 = _T_212 & _T_213; // @[el2_lsu_stbuf.scala 141:109]
|
|
wire _T_209 = 2'h2 == RdPtr; // @[el2_lsu_stbuf.scala 141:121]
|
|
wire _T_211 = _T_212 & _T_209; // @[el2_lsu_stbuf.scala 141:109]
|
|
wire _T_205 = 2'h1 == RdPtr; // @[el2_lsu_stbuf.scala 141:121]
|
|
wire _T_207 = _T_212 & _T_205; // @[el2_lsu_stbuf.scala 141:109]
|
|
wire _T_201 = 2'h0 == RdPtr; // @[el2_lsu_stbuf.scala 141:121]
|
|
wire _T_203 = _T_212 & _T_201; // @[el2_lsu_stbuf.scala 141:109]
|
|
wire [3:0] stbuf_reset = {_T_215,_T_211,_T_207,_T_203}; // @[Cat.scala 29:58]
|
|
wire _T_34 = ~stbuf_reset[0]; // @[el2_lsu_stbuf.scala 130:218]
|
|
wire _T_35 = _T_32 & _T_34; // @[el2_lsu_stbuf.scala 130:216]
|
|
reg [15:0] stbuf_addr_1; // @[el2_lib.scala 514:16]
|
|
wire _T_38 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 130:120]
|
|
wire _T_40 = _T_38 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 130:179]
|
|
wire _T_42 = ~stbuf_dma_kill[1]; // @[el2_lsu_stbuf.scala 130:197]
|
|
wire _T_43 = _T_40 & _T_42; // @[el2_lsu_stbuf.scala 130:195]
|
|
wire _T_45 = ~stbuf_reset[1]; // @[el2_lsu_stbuf.scala 130:218]
|
|
wire _T_46 = _T_43 & _T_45; // @[el2_lsu_stbuf.scala 130:216]
|
|
reg [15:0] stbuf_addr_2; // @[el2_lib.scala 514:16]
|
|
wire _T_49 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 130:120]
|
|
wire _T_51 = _T_49 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 130:179]
|
|
wire _T_53 = ~stbuf_dma_kill[2]; // @[el2_lsu_stbuf.scala 130:197]
|
|
wire _T_54 = _T_51 & _T_53; // @[el2_lsu_stbuf.scala 130:195]
|
|
wire _T_56 = ~stbuf_reset[2]; // @[el2_lsu_stbuf.scala 130:218]
|
|
wire _T_57 = _T_54 & _T_56; // @[el2_lsu_stbuf.scala 130:216]
|
|
reg [15:0] stbuf_addr_3; // @[el2_lib.scala 514:16]
|
|
wire _T_60 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 130:120]
|
|
wire _T_62 = _T_60 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 130:179]
|
|
wire _T_64 = ~stbuf_dma_kill[3]; // @[el2_lsu_stbuf.scala 130:197]
|
|
wire _T_65 = _T_62 & _T_64; // @[el2_lsu_stbuf.scala 130:195]
|
|
wire _T_67 = ~stbuf_reset[3]; // @[el2_lsu_stbuf.scala 130:218]
|
|
wire _T_68 = _T_65 & _T_67; // @[el2_lsu_stbuf.scala 130:216]
|
|
wire [3:0] store_matchvec_lo_r = {_T_68,_T_57,_T_46,_T_35}; // @[Cat.scala 29:58]
|
|
wire _T_73 = stbuf_addr_0[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120]
|
|
wire _T_75 = _T_73 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 131:179]
|
|
wire _T_78 = _T_75 & _T_31; // @[el2_lsu_stbuf.scala 131:194]
|
|
wire _T_79 = _T_78 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:215]
|
|
wire _T_82 = _T_79 & _T_34; // @[el2_lsu_stbuf.scala 131:236]
|
|
wire _T_85 = stbuf_addr_1[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120]
|
|
wire _T_87 = _T_85 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 131:179]
|
|
wire _T_90 = _T_87 & _T_42; // @[el2_lsu_stbuf.scala 131:194]
|
|
wire _T_91 = _T_90 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:215]
|
|
wire _T_94 = _T_91 & _T_45; // @[el2_lsu_stbuf.scala 131:236]
|
|
wire _T_97 = stbuf_addr_2[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120]
|
|
wire _T_99 = _T_97 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 131:179]
|
|
wire _T_102 = _T_99 & _T_53; // @[el2_lsu_stbuf.scala 131:194]
|
|
wire _T_103 = _T_102 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:215]
|
|
wire _T_106 = _T_103 & _T_56; // @[el2_lsu_stbuf.scala 131:236]
|
|
wire _T_109 = stbuf_addr_3[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120]
|
|
wire _T_111 = _T_109 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 131:179]
|
|
wire _T_114 = _T_111 & _T_64; // @[el2_lsu_stbuf.scala 131:194]
|
|
wire _T_115 = _T_114 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:215]
|
|
wire _T_118 = _T_115 & _T_67; // @[el2_lsu_stbuf.scala 131:236]
|
|
wire [3:0] store_matchvec_hi_r = {_T_118,_T_106,_T_94,_T_82}; // @[Cat.scala 29:58]
|
|
wire store_coalesce_lo_r = |store_matchvec_lo_r; // @[el2_lsu_stbuf.scala 133:49]
|
|
wire store_coalesce_hi_r = |store_matchvec_hi_r; // @[el2_lsu_stbuf.scala 134:49]
|
|
wire _T_121 = 2'h0 == WrPtr; // @[el2_lsu_stbuf.scala 137:16]
|
|
wire _T_122 = ~store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 137:29]
|
|
wire _T_123 = _T_121 & _T_122; // @[el2_lsu_stbuf.scala 137:27]
|
|
wire _T_125 = _T_121 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 138:29]
|
|
wire _T_126 = ~store_coalesce_hi_r; // @[el2_lsu_stbuf.scala 138:52]
|
|
wire _T_127 = _T_125 & _T_126; // @[el2_lsu_stbuf.scala 138:50]
|
|
wire _T_128 = _T_123 | _T_127; // @[el2_lsu_stbuf.scala 137:51]
|
|
wire _T_129 = 2'h0 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 139:18]
|
|
wire _T_130 = _T_129 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:34]
|
|
wire _T_131 = store_coalesce_lo_r | store_coalesce_hi_r; // @[el2_lsu_stbuf.scala 139:79]
|
|
wire _T_132 = ~_T_131; // @[el2_lsu_stbuf.scala 139:57]
|
|
wire _T_133 = _T_130 & _T_132; // @[el2_lsu_stbuf.scala 139:55]
|
|
wire _T_134 = _T_128 | _T_133; // @[el2_lsu_stbuf.scala 138:74]
|
|
wire _T_136 = _T_134 | store_matchvec_lo_r[0]; // @[el2_lsu_stbuf.scala 139:103]
|
|
wire _T_138 = _T_136 | store_matchvec_hi_r[0]; // @[el2_lsu_stbuf.scala 140:30]
|
|
wire _T_139 = io_ldst_stbuf_reqvld_r & _T_138; // @[el2_lsu_stbuf.scala 136:76]
|
|
wire _T_140 = 2'h1 == WrPtr; // @[el2_lsu_stbuf.scala 137:16]
|
|
wire _T_142 = _T_140 & _T_122; // @[el2_lsu_stbuf.scala 137:27]
|
|
wire _T_144 = _T_140 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 138:29]
|
|
wire _T_146 = _T_144 & _T_126; // @[el2_lsu_stbuf.scala 138:50]
|
|
wire _T_147 = _T_142 | _T_146; // @[el2_lsu_stbuf.scala 137:51]
|
|
wire _T_148 = 2'h1 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 139:18]
|
|
wire _T_149 = _T_148 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:34]
|
|
wire _T_152 = _T_149 & _T_132; // @[el2_lsu_stbuf.scala 139:55]
|
|
wire _T_153 = _T_147 | _T_152; // @[el2_lsu_stbuf.scala 138:74]
|
|
wire _T_155 = _T_153 | store_matchvec_lo_r[1]; // @[el2_lsu_stbuf.scala 139:103]
|
|
wire _T_157 = _T_155 | store_matchvec_hi_r[1]; // @[el2_lsu_stbuf.scala 140:30]
|
|
wire _T_158 = io_ldst_stbuf_reqvld_r & _T_157; // @[el2_lsu_stbuf.scala 136:76]
|
|
wire _T_159 = 2'h2 == WrPtr; // @[el2_lsu_stbuf.scala 137:16]
|
|
wire _T_161 = _T_159 & _T_122; // @[el2_lsu_stbuf.scala 137:27]
|
|
wire _T_163 = _T_159 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 138:29]
|
|
wire _T_165 = _T_163 & _T_126; // @[el2_lsu_stbuf.scala 138:50]
|
|
wire _T_166 = _T_161 | _T_165; // @[el2_lsu_stbuf.scala 137:51]
|
|
wire _T_167 = 2'h2 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 139:18]
|
|
wire _T_168 = _T_167 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:34]
|
|
wire _T_171 = _T_168 & _T_132; // @[el2_lsu_stbuf.scala 139:55]
|
|
wire _T_172 = _T_166 | _T_171; // @[el2_lsu_stbuf.scala 138:74]
|
|
wire _T_174 = _T_172 | store_matchvec_lo_r[2]; // @[el2_lsu_stbuf.scala 139:103]
|
|
wire _T_176 = _T_174 | store_matchvec_hi_r[2]; // @[el2_lsu_stbuf.scala 140:30]
|
|
wire _T_177 = io_ldst_stbuf_reqvld_r & _T_176; // @[el2_lsu_stbuf.scala 136:76]
|
|
wire _T_178 = 2'h3 == WrPtr; // @[el2_lsu_stbuf.scala 137:16]
|
|
wire _T_180 = _T_178 & _T_122; // @[el2_lsu_stbuf.scala 137:27]
|
|
wire _T_182 = _T_178 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 138:29]
|
|
wire _T_184 = _T_182 & _T_126; // @[el2_lsu_stbuf.scala 138:50]
|
|
wire _T_185 = _T_180 | _T_184; // @[el2_lsu_stbuf.scala 137:51]
|
|
wire _T_186 = 2'h3 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 139:18]
|
|
wire _T_187 = _T_186 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:34]
|
|
wire _T_190 = _T_187 & _T_132; // @[el2_lsu_stbuf.scala 139:55]
|
|
wire _T_191 = _T_185 | _T_190; // @[el2_lsu_stbuf.scala 138:74]
|
|
wire _T_193 = _T_191 | store_matchvec_lo_r[3]; // @[el2_lsu_stbuf.scala 139:103]
|
|
wire _T_195 = _T_193 | store_matchvec_hi_r[3]; // @[el2_lsu_stbuf.scala 140:30]
|
|
wire _T_196 = io_ldst_stbuf_reqvld_r & _T_195; // @[el2_lsu_stbuf.scala 136:76]
|
|
wire [3:0] stbuf_wr_en = {_T_196,_T_177,_T_158,_T_139}; // @[Cat.scala 29:58]
|
|
wire _T_219 = ~ldst_dual_r; // @[el2_lsu_stbuf.scala 142:53]
|
|
wire _T_220 = _T_219 | io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 142:66]
|
|
wire _T_223 = _T_220 & _T_121; // @[el2_lsu_stbuf.scala 142:93]
|
|
wire _T_225 = _T_223 & _T_122; // @[el2_lsu_stbuf.scala 142:123]
|
|
wire _T_227 = _T_225 | store_matchvec_lo_r[0]; // @[el2_lsu_stbuf.scala 142:147]
|
|
wire _T_232 = _T_220 & _T_140; // @[el2_lsu_stbuf.scala 142:93]
|
|
wire _T_234 = _T_232 & _T_122; // @[el2_lsu_stbuf.scala 142:123]
|
|
wire _T_236 = _T_234 | store_matchvec_lo_r[1]; // @[el2_lsu_stbuf.scala 142:147]
|
|
wire _T_241 = _T_220 & _T_159; // @[el2_lsu_stbuf.scala 142:93]
|
|
wire _T_243 = _T_241 & _T_122; // @[el2_lsu_stbuf.scala 142:123]
|
|
wire _T_245 = _T_243 | store_matchvec_lo_r[2]; // @[el2_lsu_stbuf.scala 142:147]
|
|
wire _T_250 = _T_220 & _T_178; // @[el2_lsu_stbuf.scala 142:93]
|
|
wire _T_252 = _T_250 & _T_122; // @[el2_lsu_stbuf.scala 142:123]
|
|
wire _T_254 = _T_252 | store_matchvec_lo_r[3]; // @[el2_lsu_stbuf.scala 142:147]
|
|
wire [3:0] sel_lo = {_T_254,_T_245,_T_236,_T_227}; // @[Cat.scala 29:58]
|
|
reg [3:0] stbuf_byteen_0; // @[el2_lsu_stbuf.scala 165:92]
|
|
wire [3:0] _T_274 = stbuf_byteen_0 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 145:86]
|
|
wire [3:0] _T_275 = stbuf_byteen_0 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 145:123]
|
|
wire [3:0] stbuf_byteenin_0 = sel_lo[0] ? _T_274 : _T_275; // @[el2_lsu_stbuf.scala 145:58]
|
|
reg [3:0] stbuf_byteen_1; // @[el2_lsu_stbuf.scala 165:92]
|
|
wire [3:0] _T_278 = stbuf_byteen_1 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 145:86]
|
|
wire [3:0] _T_279 = stbuf_byteen_1 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 145:123]
|
|
wire [3:0] stbuf_byteenin_1 = sel_lo[1] ? _T_278 : _T_279; // @[el2_lsu_stbuf.scala 145:58]
|
|
reg [3:0] stbuf_byteen_2; // @[el2_lsu_stbuf.scala 165:92]
|
|
wire [3:0] _T_282 = stbuf_byteen_2 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 145:86]
|
|
wire [3:0] _T_283 = stbuf_byteen_2 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 145:123]
|
|
wire [3:0] stbuf_byteenin_2 = sel_lo[2] ? _T_282 : _T_283; // @[el2_lsu_stbuf.scala 145:58]
|
|
reg [3:0] stbuf_byteen_3; // @[el2_lsu_stbuf.scala 165:92]
|
|
wire [3:0] _T_286 = stbuf_byteen_3 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 145:86]
|
|
wire [3:0] _T_287 = stbuf_byteen_3 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 145:123]
|
|
wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_286 : _T_287; // @[el2_lsu_stbuf.scala 145:58]
|
|
wire _T_291 = ~stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 147:67]
|
|
wire _T_293 = _T_291 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 147:87]
|
|
reg [31:0] stbuf_data_0; // @[el2_lib.scala 514:16]
|
|
wire [7:0] _T_296 = _T_293 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 147:66]
|
|
wire _T_300 = _T_291 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 148:29]
|
|
wire [7:0] _T_303 = _T_300 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 148:8]
|
|
wire [7:0] datain1_0 = sel_lo[0] ? _T_296 : _T_303; // @[el2_lsu_stbuf.scala 147:51]
|
|
wire _T_307 = ~stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 147:67]
|
|
wire _T_309 = _T_307 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 147:87]
|
|
reg [31:0] stbuf_data_1; // @[el2_lib.scala 514:16]
|
|
wire [7:0] _T_312 = _T_309 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 147:66]
|
|
wire _T_316 = _T_307 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 148:29]
|
|
wire [7:0] _T_319 = _T_316 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 148:8]
|
|
wire [7:0] datain1_1 = sel_lo[1] ? _T_312 : _T_319; // @[el2_lsu_stbuf.scala 147:51]
|
|
wire _T_323 = ~stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 147:67]
|
|
wire _T_325 = _T_323 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 147:87]
|
|
reg [31:0] stbuf_data_2; // @[el2_lib.scala 514:16]
|
|
wire [7:0] _T_328 = _T_325 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 147:66]
|
|
wire _T_332 = _T_323 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 148:29]
|
|
wire [7:0] _T_335 = _T_332 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 148:8]
|
|
wire [7:0] datain1_2 = sel_lo[2] ? _T_328 : _T_335; // @[el2_lsu_stbuf.scala 147:51]
|
|
wire _T_339 = ~stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 147:67]
|
|
wire _T_341 = _T_339 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 147:87]
|
|
reg [31:0] stbuf_data_3; // @[el2_lib.scala 514:16]
|
|
wire [7:0] _T_344 = _T_341 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 147:66]
|
|
wire _T_348 = _T_339 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 148:29]
|
|
wire [7:0] _T_351 = _T_348 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 148:8]
|
|
wire [7:0] datain1_3 = sel_lo[3] ? _T_344 : _T_351; // @[el2_lsu_stbuf.scala 147:51]
|
|
wire _T_355 = ~stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 150:68]
|
|
wire _T_357 = _T_355 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 150:88]
|
|
wire [7:0] _T_360 = _T_357 ? io_store_datafn_lo_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 150:67]
|
|
wire _T_364 = _T_355 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 151:29]
|
|
wire [7:0] _T_367 = _T_364 ? io_store_datafn_hi_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 151:8]
|
|
wire [7:0] datain2_0 = sel_lo[0] ? _T_360 : _T_367; // @[el2_lsu_stbuf.scala 150:52]
|
|
wire _T_371 = ~stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 150:68]
|
|
wire _T_373 = _T_371 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 150:88]
|
|
wire [7:0] _T_376 = _T_373 ? io_store_datafn_lo_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 150:67]
|
|
wire _T_380 = _T_371 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 151:29]
|
|
wire [7:0] _T_383 = _T_380 ? io_store_datafn_hi_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 151:8]
|
|
wire [7:0] datain2_1 = sel_lo[1] ? _T_376 : _T_383; // @[el2_lsu_stbuf.scala 150:52]
|
|
wire _T_387 = ~stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 150:68]
|
|
wire _T_389 = _T_387 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 150:88]
|
|
wire [7:0] _T_392 = _T_389 ? io_store_datafn_lo_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 150:67]
|
|
wire _T_396 = _T_387 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 151:29]
|
|
wire [7:0] _T_399 = _T_396 ? io_store_datafn_hi_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 151:8]
|
|
wire [7:0] datain2_2 = sel_lo[2] ? _T_392 : _T_399; // @[el2_lsu_stbuf.scala 150:52]
|
|
wire _T_403 = ~stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 150:68]
|
|
wire _T_405 = _T_403 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 150:88]
|
|
wire [7:0] _T_408 = _T_405 ? io_store_datafn_lo_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 150:67]
|
|
wire _T_412 = _T_403 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 151:29]
|
|
wire [7:0] _T_415 = _T_412 ? io_store_datafn_hi_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 151:8]
|
|
wire [7:0] datain2_3 = sel_lo[3] ? _T_408 : _T_415; // @[el2_lsu_stbuf.scala 150:52]
|
|
wire _T_419 = ~stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 153:68]
|
|
wire _T_421 = _T_419 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 153:88]
|
|
wire [7:0] _T_424 = _T_421 ? io_store_datafn_lo_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 153:67]
|
|
wire _T_428 = _T_419 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 154:29]
|
|
wire [7:0] _T_431 = _T_428 ? io_store_datafn_hi_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 154:8]
|
|
wire [7:0] datain3_0 = sel_lo[0] ? _T_424 : _T_431; // @[el2_lsu_stbuf.scala 153:52]
|
|
wire _T_435 = ~stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 153:68]
|
|
wire _T_437 = _T_435 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 153:88]
|
|
wire [7:0] _T_440 = _T_437 ? io_store_datafn_lo_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 153:67]
|
|
wire _T_444 = _T_435 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 154:29]
|
|
wire [7:0] _T_447 = _T_444 ? io_store_datafn_hi_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 154:8]
|
|
wire [7:0] datain3_1 = sel_lo[1] ? _T_440 : _T_447; // @[el2_lsu_stbuf.scala 153:52]
|
|
wire _T_451 = ~stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 153:68]
|
|
wire _T_453 = _T_451 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 153:88]
|
|
wire [7:0] _T_456 = _T_453 ? io_store_datafn_lo_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 153:67]
|
|
wire _T_460 = _T_451 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 154:29]
|
|
wire [7:0] _T_463 = _T_460 ? io_store_datafn_hi_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 154:8]
|
|
wire [7:0] datain3_2 = sel_lo[2] ? _T_456 : _T_463; // @[el2_lsu_stbuf.scala 153:52]
|
|
wire _T_467 = ~stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 153:68]
|
|
wire _T_469 = _T_467 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 153:88]
|
|
wire [7:0] _T_472 = _T_469 ? io_store_datafn_lo_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 153:67]
|
|
wire _T_476 = _T_467 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 154:29]
|
|
wire [7:0] _T_479 = _T_476 ? io_store_datafn_hi_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 154:8]
|
|
wire [7:0] datain3_3 = sel_lo[3] ? _T_472 : _T_479; // @[el2_lsu_stbuf.scala 153:52]
|
|
wire _T_483 = ~stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 156:68]
|
|
wire _T_485 = _T_483 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 156:88]
|
|
wire [7:0] _T_488 = _T_485 ? io_store_datafn_lo_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 156:67]
|
|
wire _T_492 = _T_483 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 157:29]
|
|
wire [7:0] _T_495 = _T_492 ? io_store_datafn_hi_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 157:8]
|
|
wire [7:0] datain4_0 = sel_lo[0] ? _T_488 : _T_495; // @[el2_lsu_stbuf.scala 156:52]
|
|
wire _T_499 = ~stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 156:68]
|
|
wire _T_501 = _T_499 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 156:88]
|
|
wire [7:0] _T_504 = _T_501 ? io_store_datafn_lo_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 156:67]
|
|
wire _T_508 = _T_499 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 157:29]
|
|
wire [7:0] _T_511 = _T_508 ? io_store_datafn_hi_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 157:8]
|
|
wire [7:0] datain4_1 = sel_lo[1] ? _T_504 : _T_511; // @[el2_lsu_stbuf.scala 156:52]
|
|
wire _T_515 = ~stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 156:68]
|
|
wire _T_517 = _T_515 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 156:88]
|
|
wire [7:0] _T_520 = _T_517 ? io_store_datafn_lo_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 156:67]
|
|
wire _T_524 = _T_515 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 157:29]
|
|
wire [7:0] _T_527 = _T_524 ? io_store_datafn_hi_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 157:8]
|
|
wire [7:0] datain4_2 = sel_lo[2] ? _T_520 : _T_527; // @[el2_lsu_stbuf.scala 156:52]
|
|
wire _T_531 = ~stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 156:68]
|
|
wire _T_533 = _T_531 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 156:88]
|
|
wire [7:0] _T_536 = _T_533 ? io_store_datafn_lo_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 156:67]
|
|
wire _T_540 = _T_531 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 157:29]
|
|
wire [7:0] _T_543 = _T_540 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 157:8]
|
|
wire [7:0] datain4_3 = sel_lo[3] ? _T_536 : _T_543; // @[el2_lsu_stbuf.scala 156:52]
|
|
wire [15:0] _T_545 = {datain2_0,datain1_0}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_546 = {datain4_0,datain3_0}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_548 = {datain2_1,datain1_1}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_549 = {datain4_1,datain3_1}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_551 = {datain2_2,datain1_2}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_552 = {datain4_2,datain3_2}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_554 = {datain2_3,datain1_3}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_555 = {datain4_3,datain3_3}; // @[Cat.scala 29:58]
|
|
wire _T_560 = stbuf_wr_en[0] | stbuf_vld[0]; // @[el2_lsu_stbuf.scala 163:92]
|
|
wire _T_568 = stbuf_wr_en[1] | stbuf_vld[1]; // @[el2_lsu_stbuf.scala 163:92]
|
|
wire _T_576 = stbuf_wr_en[2] | stbuf_vld[2]; // @[el2_lsu_stbuf.scala 163:92]
|
|
wire _T_584 = stbuf_wr_en[3] | stbuf_vld[3]; // @[el2_lsu_stbuf.scala 163:92]
|
|
wire [15:0] cmpaddr_hi_m = {{2'd0}, io_end_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 200:16]
|
|
wire _T_789 = stbuf_addr_3[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 206:115]
|
|
wire _T_791 = _T_789 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 206:139]
|
|
wire _T_794 = _T_791 & _T_64; // @[el2_lsu_stbuf.scala 206:154]
|
|
wire _T_795 = _T_794 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 206:175]
|
|
wire _T_780 = stbuf_addr_2[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 206:115]
|
|
wire _T_782 = _T_780 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 206:139]
|
|
wire _T_785 = _T_782 & _T_53; // @[el2_lsu_stbuf.scala 206:154]
|
|
wire _T_786 = _T_785 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 206:175]
|
|
wire _T_771 = stbuf_addr_1[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 206:115]
|
|
wire _T_773 = _T_771 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 206:139]
|
|
wire _T_776 = _T_773 & _T_42; // @[el2_lsu_stbuf.scala 206:154]
|
|
wire _T_777 = _T_776 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 206:175]
|
|
wire _T_762 = stbuf_addr_0[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 206:115]
|
|
wire _T_764 = _T_762 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 206:139]
|
|
wire _T_767 = _T_764 & _T_31; // @[el2_lsu_stbuf.scala 206:154]
|
|
wire _T_768 = _T_767 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 206:175]
|
|
wire [3:0] stbuf_match_hi = {_T_795,_T_786,_T_777,_T_768}; // @[Cat.scala 29:58]
|
|
wire [15:0] cmpaddr_lo_m = {{2'd0}, io_lsu_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 203:17]
|
|
wire _T_827 = stbuf_addr_3[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 207:115]
|
|
wire _T_829 = _T_827 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 207:139]
|
|
wire _T_832 = _T_829 & _T_64; // @[el2_lsu_stbuf.scala 207:154]
|
|
wire _T_833 = _T_832 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 207:175]
|
|
wire _T_818 = stbuf_addr_2[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 207:115]
|
|
wire _T_820 = _T_818 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 207:139]
|
|
wire _T_823 = _T_820 & _T_53; // @[el2_lsu_stbuf.scala 207:154]
|
|
wire _T_824 = _T_823 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 207:175]
|
|
wire _T_809 = stbuf_addr_1[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 207:115]
|
|
wire _T_811 = _T_809 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 207:139]
|
|
wire _T_814 = _T_811 & _T_42; // @[el2_lsu_stbuf.scala 207:154]
|
|
wire _T_815 = _T_814 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 207:175]
|
|
wire _T_800 = stbuf_addr_0[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 207:115]
|
|
wire _T_802 = _T_800 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 207:139]
|
|
wire _T_805 = _T_802 & _T_31; // @[el2_lsu_stbuf.scala 207:154]
|
|
wire _T_806 = _T_805 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 207:175]
|
|
wire [3:0] stbuf_match_lo = {_T_833,_T_824,_T_815,_T_806}; // @[Cat.scala 29:58]
|
|
wire _T_856 = stbuf_match_hi[3] | stbuf_match_lo[3]; // @[el2_lsu_stbuf.scala 208:78]
|
|
wire _T_857 = _T_856 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 208:99]
|
|
wire _T_858 = _T_857 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_stbuf.scala 208:120]
|
|
wire _T_859 = _T_858 & io_lsu_pkt_m_bits_store; // @[el2_lsu_stbuf.scala 208:144]
|
|
wire _T_850 = stbuf_match_hi[2] | stbuf_match_lo[2]; // @[el2_lsu_stbuf.scala 208:78]
|
|
wire _T_851 = _T_850 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 208:99]
|
|
wire _T_852 = _T_851 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_stbuf.scala 208:120]
|
|
wire _T_853 = _T_852 & io_lsu_pkt_m_bits_store; // @[el2_lsu_stbuf.scala 208:144]
|
|
wire _T_844 = stbuf_match_hi[1] | stbuf_match_lo[1]; // @[el2_lsu_stbuf.scala 208:78]
|
|
wire _T_845 = _T_844 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 208:99]
|
|
wire _T_846 = _T_845 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_stbuf.scala 208:120]
|
|
wire _T_847 = _T_846 & io_lsu_pkt_m_bits_store; // @[el2_lsu_stbuf.scala 208:144]
|
|
wire _T_838 = stbuf_match_hi[0] | stbuf_match_lo[0]; // @[el2_lsu_stbuf.scala 208:78]
|
|
wire _T_839 = _T_838 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 208:99]
|
|
wire _T_840 = _T_839 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_stbuf.scala 208:120]
|
|
wire _T_841 = _T_840 & io_lsu_pkt_m_bits_store; // @[el2_lsu_stbuf.scala 208:144]
|
|
wire [3:0] stbuf_dma_kill_en = {_T_859,_T_853,_T_847,_T_841}; // @[Cat.scala 29:58]
|
|
wire _T_595 = stbuf_dma_kill_en[0] | stbuf_dma_kill[0]; // @[el2_lsu_stbuf.scala 164:96]
|
|
wire _T_603 = stbuf_dma_kill_en[1] | stbuf_dma_kill[1]; // @[el2_lsu_stbuf.scala 164:96]
|
|
wire _T_611 = stbuf_dma_kill_en[2] | stbuf_dma_kill[2]; // @[el2_lsu_stbuf.scala 164:96]
|
|
wire _T_619 = stbuf_dma_kill_en[3] | stbuf_dma_kill[3]; // @[el2_lsu_stbuf.scala 164:96]
|
|
wire [3:0] _T_629 = stbuf_wr_en[0] ? stbuf_byteenin_0 : stbuf_byteen_0; // @[el2_lsu_stbuf.scala 165:96]
|
|
wire [3:0] _T_633 = _T_34 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_638 = stbuf_wr_en[1] ? stbuf_byteenin_1 : stbuf_byteen_1; // @[el2_lsu_stbuf.scala 165:96]
|
|
wire [3:0] _T_642 = _T_45 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_647 = stbuf_wr_en[2] ? stbuf_byteenin_2 : stbuf_byteen_2; // @[el2_lsu_stbuf.scala 165:96]
|
|
wire [3:0] _T_651 = _T_56 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_656 = stbuf_wr_en[3] ? stbuf_byteenin_3 : stbuf_byteen_3; // @[el2_lsu_stbuf.scala 165:96]
|
|
wire [3:0] _T_660 = _T_67 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
reg ldst_dual_m; // @[el2_lsu_stbuf.scala 170:52]
|
|
wire [3:0] _T_689 = stbuf_vld >> RdPtr; // @[el2_lsu_stbuf.scala 174:43]
|
|
wire [3:0] _T_691 = stbuf_dma_kill >> RdPtr; // @[el2_lsu_stbuf.scala 174:67]
|
|
wire _T_698 = ~_T_691[0]; // @[el2_lsu_stbuf.scala 175:46]
|
|
wire _T_699 = _T_689[0] & _T_698; // @[el2_lsu_stbuf.scala 175:44]
|
|
wire _T_700 = |stbuf_dma_kill_en; // @[el2_lsu_stbuf.scala 175:91]
|
|
wire _T_701 = ~_T_700; // @[el2_lsu_stbuf.scala 175:71]
|
|
wire [15:0] _GEN_1 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[el2_lsu_stbuf.scala 176:22]
|
|
wire [15:0] _GEN_2 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_1; // @[el2_lsu_stbuf.scala 176:22]
|
|
wire [31:0] _GEN_5 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[el2_lsu_stbuf.scala 177:22]
|
|
wire [31:0] _GEN_6 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_5; // @[el2_lsu_stbuf.scala 177:22]
|
|
wire _T_703 = ~dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 179:44]
|
|
wire _T_704 = io_ldst_stbuf_reqvld_r & _T_703; // @[el2_lsu_stbuf.scala 179:42]
|
|
wire _T_705 = store_coalesce_hi_r | store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 179:88]
|
|
wire _T_706 = ~_T_705; // @[el2_lsu_stbuf.scala 179:66]
|
|
wire _T_707 = _T_704 & _T_706; // @[el2_lsu_stbuf.scala 179:64]
|
|
wire _T_708 = io_ldst_stbuf_reqvld_r & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 180:30]
|
|
wire _T_709 = store_coalesce_hi_r & store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 180:76]
|
|
wire _T_710 = ~_T_709; // @[el2_lsu_stbuf.scala 180:54]
|
|
wire _T_711 = _T_708 & _T_710; // @[el2_lsu_stbuf.scala 180:52]
|
|
wire WrPtrEn = _T_707 | _T_711; // @[el2_lsu_stbuf.scala 179:113]
|
|
wire _T_716 = _T_708 & _T_706; // @[el2_lsu_stbuf.scala 181:67]
|
|
wire [3:0] _T_721 = {3'h0,stbuf_vld[0]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_723 = {3'h0,stbuf_vld[1]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_725 = {3'h0,stbuf_vld[2]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_727 = {3'h0,stbuf_vld[3]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_730 = _T_721 + _T_723; // @[el2_lsu_stbuf.scala 188:101]
|
|
wire [3:0] _T_732 = _T_730 + _T_725; // @[el2_lsu_stbuf.scala 188:101]
|
|
wire [3:0] stbuf_numvld_any = _T_732 + _T_727; // @[el2_lsu_stbuf.scala 188:101]
|
|
wire _T_734 = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_store; // @[el2_lsu_stbuf.scala 189:39]
|
|
wire _T_735 = _T_734 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 189:65]
|
|
wire _T_736 = ~io_lsu_pkt_m_bits_dma; // @[el2_lsu_stbuf.scala 189:87]
|
|
wire isdccmst_m = _T_735 & _T_736; // @[el2_lsu_stbuf.scala 189:85]
|
|
wire _T_737 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[el2_lsu_stbuf.scala 190:39]
|
|
wire _T_738 = _T_737 & io_addr_in_dccm_r; // @[el2_lsu_stbuf.scala 190:65]
|
|
wire _T_739 = ~io_lsu_pkt_r_bits_dma; // @[el2_lsu_stbuf.scala 190:87]
|
|
wire isdccmst_r = _T_738 & _T_739; // @[el2_lsu_stbuf.scala 190:85]
|
|
wire [1:0] _T_740 = {1'h0,isdccmst_m}; // @[Cat.scala 29:58]
|
|
wire _T_741 = isdccmst_m & ldst_dual_m; // @[el2_lsu_stbuf.scala 192:62]
|
|
wire [2:0] _GEN_14 = {{1'd0}, _T_740}; // @[el2_lsu_stbuf.scala 192:47]
|
|
wire [2:0] _T_742 = _GEN_14 << _T_741; // @[el2_lsu_stbuf.scala 192:47]
|
|
wire [1:0] _T_743 = {1'h0,isdccmst_r}; // @[Cat.scala 29:58]
|
|
wire _T_744 = isdccmst_r & ldst_dual_r; // @[el2_lsu_stbuf.scala 193:62]
|
|
wire [2:0] _GEN_15 = {{1'd0}, _T_743}; // @[el2_lsu_stbuf.scala 193:47]
|
|
wire [2:0] _T_745 = _GEN_15 << _T_744; // @[el2_lsu_stbuf.scala 193:47]
|
|
wire [1:0] stbuf_specvld_m = _T_742[1:0]; // @[el2_lsu_stbuf.scala 192:19]
|
|
wire [3:0] _T_746 = {2'h0,stbuf_specvld_m}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_748 = stbuf_numvld_any + _T_746; // @[el2_lsu_stbuf.scala 194:44]
|
|
wire [1:0] stbuf_specvld_r = _T_745[1:0]; // @[el2_lsu_stbuf.scala 193:19]
|
|
wire [3:0] _T_749 = {2'h0,stbuf_specvld_r}; // @[Cat.scala 29:58]
|
|
wire [3:0] stbuf_specvld_any = _T_748 + _T_749; // @[el2_lsu_stbuf.scala 194:78]
|
|
wire _T_751 = ~ldst_dual_d; // @[el2_lsu_stbuf.scala 196:34]
|
|
wire _T_752 = _T_751 & io_dec_lsu_valid_raw_d; // @[el2_lsu_stbuf.scala 196:47]
|
|
wire _T_754 = stbuf_specvld_any >= 4'h4; // @[el2_lsu_stbuf.scala 196:99]
|
|
wire _T_755 = stbuf_specvld_any >= 4'h3; // @[el2_lsu_stbuf.scala 196:140]
|
|
wire _T_865 = stbuf_match_hi[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_0_0 = _T_865 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_869 = stbuf_match_hi[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_0_1 = _T_869 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_873 = stbuf_match_hi[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_0_2 = _T_873 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_877 = stbuf_match_hi[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_0_3 = _T_877 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_881 = stbuf_match_hi[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_1_0 = _T_881 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_885 = stbuf_match_hi[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_1_1 = _T_885 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_889 = stbuf_match_hi[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_1_2 = _T_889 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_893 = stbuf_match_hi[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_1_3 = _T_893 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_897 = stbuf_match_hi[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_2_0 = _T_897 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_901 = stbuf_match_hi[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_2_1 = _T_901 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_905 = stbuf_match_hi[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_2_2 = _T_905 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_909 = stbuf_match_hi[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_2_3 = _T_909 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_913 = stbuf_match_hi[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_3_0 = _T_913 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_917 = stbuf_match_hi[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_3_1 = _T_917 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_921 = stbuf_match_hi[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_3_2 = _T_921 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_925 = stbuf_match_hi[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 211:116]
|
|
wire stbuf_fwdbyteenvec_hi_3_3 = _T_925 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 211:137]
|
|
wire _T_929 = stbuf_match_lo[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_0_0 = _T_929 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_933 = stbuf_match_lo[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_0_1 = _T_933 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_937 = stbuf_match_lo[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_0_2 = _T_937 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_941 = stbuf_match_lo[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_0_3 = _T_941 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_945 = stbuf_match_lo[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_1_0 = _T_945 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_949 = stbuf_match_lo[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_1_1 = _T_949 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_953 = stbuf_match_lo[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_1_2 = _T_953 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_957 = stbuf_match_lo[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_1_3 = _T_957 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_961 = stbuf_match_lo[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_2_0 = _T_961 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_965 = stbuf_match_lo[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_2_1 = _T_965 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_969 = stbuf_match_lo[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_2_2 = _T_969 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_973 = stbuf_match_lo[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_2_3 = _T_973 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_977 = stbuf_match_lo[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_3_0 = _T_977 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_981 = stbuf_match_lo[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_3_1 = _T_981 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_985 = stbuf_match_lo[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_3_2 = _T_985 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_989 = stbuf_match_lo[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 212:116]
|
|
wire stbuf_fwdbyteenvec_lo_3_3 = _T_989 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 212:137]
|
|
wire _T_991 = stbuf_fwdbyteenvec_hi_0_0 | stbuf_fwdbyteenvec_hi_1_0; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire _T_992 = _T_991 | stbuf_fwdbyteenvec_hi_2_0; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire stbuf_fwdbyteen_hi_pre_m_0 = _T_992 | stbuf_fwdbyteenvec_hi_3_0; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire _T_993 = stbuf_fwdbyteenvec_hi_0_1 | stbuf_fwdbyteenvec_hi_1_1; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire _T_994 = _T_993 | stbuf_fwdbyteenvec_hi_2_1; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire stbuf_fwdbyteen_hi_pre_m_1 = _T_994 | stbuf_fwdbyteenvec_hi_3_1; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire _T_995 = stbuf_fwdbyteenvec_hi_0_2 | stbuf_fwdbyteenvec_hi_1_2; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire _T_996 = _T_995 | stbuf_fwdbyteenvec_hi_2_2; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire stbuf_fwdbyteen_hi_pre_m_2 = _T_996 | stbuf_fwdbyteenvec_hi_3_2; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire _T_997 = stbuf_fwdbyteenvec_hi_0_3 | stbuf_fwdbyteenvec_hi_1_3; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire _T_998 = _T_997 | stbuf_fwdbyteenvec_hi_2_3; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire stbuf_fwdbyteen_hi_pre_m_3 = _T_998 | stbuf_fwdbyteenvec_hi_3_3; // @[el2_lsu_stbuf.scala 213:147]
|
|
wire _T_999 = stbuf_fwdbyteenvec_lo_0_0 | stbuf_fwdbyteenvec_lo_1_0; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire _T_1000 = _T_999 | stbuf_fwdbyteenvec_lo_2_0; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire stbuf_fwdbyteen_lo_pre_m_0 = _T_1000 | stbuf_fwdbyteenvec_lo_3_0; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire _T_1001 = stbuf_fwdbyteenvec_lo_0_1 | stbuf_fwdbyteenvec_lo_1_1; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire _T_1002 = _T_1001 | stbuf_fwdbyteenvec_lo_2_1; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire stbuf_fwdbyteen_lo_pre_m_1 = _T_1002 | stbuf_fwdbyteenvec_lo_3_1; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire _T_1003 = stbuf_fwdbyteenvec_lo_0_2 | stbuf_fwdbyteenvec_lo_1_2; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire _T_1004 = _T_1003 | stbuf_fwdbyteenvec_lo_2_2; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire stbuf_fwdbyteen_lo_pre_m_2 = _T_1004 | stbuf_fwdbyteenvec_lo_3_2; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire _T_1005 = stbuf_fwdbyteenvec_lo_0_3 | stbuf_fwdbyteenvec_lo_1_3; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire _T_1006 = _T_1005 | stbuf_fwdbyteenvec_lo_2_3; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire stbuf_fwdbyteen_lo_pre_m_3 = _T_1006 | stbuf_fwdbyteenvec_lo_3_3; // @[el2_lsu_stbuf.scala 214:147]
|
|
wire [31:0] _T_1009 = stbuf_match_hi[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1010 = _T_1009 & stbuf_data_0; // @[el2_lsu_stbuf.scala 216:97]
|
|
wire [31:0] _T_1013 = stbuf_match_hi[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1014 = _T_1013 & stbuf_data_1; // @[el2_lsu_stbuf.scala 216:97]
|
|
wire [31:0] _T_1017 = stbuf_match_hi[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1018 = _T_1017 & stbuf_data_2; // @[el2_lsu_stbuf.scala 216:97]
|
|
wire [31:0] _T_1021 = stbuf_match_hi[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1022 = _T_1021 & stbuf_data_3; // @[el2_lsu_stbuf.scala 216:97]
|
|
wire [31:0] _T_1024 = _T_1022 | _T_1018; // @[el2_lsu_stbuf.scala 216:130]
|
|
wire [31:0] _T_1025 = _T_1024 | _T_1014; // @[el2_lsu_stbuf.scala 216:130]
|
|
wire [31:0] stbuf_fwddata_hi_pre_m = _T_1025 | _T_1010; // @[el2_lsu_stbuf.scala 216:130]
|
|
wire [31:0] _T_1028 = stbuf_match_lo[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1029 = _T_1028 & stbuf_data_0; // @[el2_lsu_stbuf.scala 217:97]
|
|
wire [31:0] _T_1032 = stbuf_match_lo[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1033 = _T_1032 & stbuf_data_1; // @[el2_lsu_stbuf.scala 217:97]
|
|
wire [31:0] _T_1036 = stbuf_match_lo[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1037 = _T_1036 & stbuf_data_2; // @[el2_lsu_stbuf.scala 217:97]
|
|
wire [31:0] _T_1040 = stbuf_match_lo[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1041 = _T_1040 & stbuf_data_3; // @[el2_lsu_stbuf.scala 217:97]
|
|
wire [31:0] _T_1043 = _T_1041 | _T_1037; // @[el2_lsu_stbuf.scala 217:130]
|
|
wire [31:0] _T_1044 = _T_1043 | _T_1033; // @[el2_lsu_stbuf.scala 217:130]
|
|
wire [31:0] stbuf_fwddata_lo_pre_m = _T_1044 | _T_1029; // @[el2_lsu_stbuf.scala 217:130]
|
|
wire _T_1049 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 224:49]
|
|
wire _T_1050 = _T_1049 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 224:74]
|
|
wire _T_1051 = _T_1050 & io_lsu_pkt_r_bits_store; // @[el2_lsu_stbuf.scala 224:95]
|
|
wire ld_addr_rhit_lo_lo = _T_1051 & _T_739; // @[el2_lsu_stbuf.scala 224:121]
|
|
wire _T_1055 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 225:49]
|
|
wire _T_1056 = _T_1055 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 225:74]
|
|
wire _T_1057 = _T_1056 & io_lsu_pkt_r_bits_store; // @[el2_lsu_stbuf.scala 225:95]
|
|
wire ld_addr_rhit_lo_hi = _T_1057 & _T_739; // @[el2_lsu_stbuf.scala 225:121]
|
|
wire _T_1061 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 226:49]
|
|
wire _T_1062 = _T_1061 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 226:74]
|
|
wire _T_1063 = _T_1062 & io_lsu_pkt_r_bits_store; // @[el2_lsu_stbuf.scala 226:95]
|
|
wire _T_1065 = _T_1063 & _T_739; // @[el2_lsu_stbuf.scala 226:121]
|
|
wire ld_addr_rhit_hi_lo = _T_1065 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 226:146]
|
|
wire _T_1068 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 227:49]
|
|
wire _T_1069 = _T_1068 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 227:74]
|
|
wire _T_1070 = _T_1069 & io_lsu_pkt_r_bits_store; // @[el2_lsu_stbuf.scala 227:95]
|
|
wire _T_1072 = _T_1070 & _T_739; // @[el2_lsu_stbuf.scala 227:121]
|
|
wire ld_addr_rhit_hi_hi = _T_1072 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 227:146]
|
|
wire _T_1074 = ld_addr_rhit_lo_lo & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 229:79]
|
|
wire _T_1076 = ld_addr_rhit_lo_lo & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 229:79]
|
|
wire _T_1078 = ld_addr_rhit_lo_lo & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 229:79]
|
|
wire _T_1080 = ld_addr_rhit_lo_lo & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 229:79]
|
|
wire [3:0] ld_byte_rhit_lo_lo = {_T_1080,_T_1078,_T_1076,_T_1074}; // @[Cat.scala 29:58]
|
|
wire _T_1085 = ld_addr_rhit_lo_hi & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 230:79]
|
|
wire _T_1087 = ld_addr_rhit_lo_hi & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 230:79]
|
|
wire _T_1089 = ld_addr_rhit_lo_hi & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 230:79]
|
|
wire _T_1091 = ld_addr_rhit_lo_hi & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 230:79]
|
|
wire [3:0] ld_byte_rhit_lo_hi = {_T_1091,_T_1089,_T_1087,_T_1085}; // @[Cat.scala 29:58]
|
|
wire _T_1096 = ld_addr_rhit_hi_lo & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 231:79]
|
|
wire _T_1098 = ld_addr_rhit_hi_lo & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 231:79]
|
|
wire _T_1100 = ld_addr_rhit_hi_lo & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 231:79]
|
|
wire _T_1102 = ld_addr_rhit_hi_lo & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 231:79]
|
|
wire [3:0] ld_byte_rhit_hi_lo = {_T_1102,_T_1100,_T_1098,_T_1096}; // @[Cat.scala 29:58]
|
|
wire _T_1107 = ld_addr_rhit_hi_hi & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 232:79]
|
|
wire _T_1109 = ld_addr_rhit_hi_hi & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 232:79]
|
|
wire _T_1111 = ld_addr_rhit_hi_hi & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 232:79]
|
|
wire _T_1113 = ld_addr_rhit_hi_hi & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 232:79]
|
|
wire [3:0] ld_byte_rhit_hi_hi = {_T_1113,_T_1111,_T_1109,_T_1107}; // @[Cat.scala 29:58]
|
|
wire _T_1119 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[el2_lsu_stbuf.scala 234:79]
|
|
wire _T_1122 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[el2_lsu_stbuf.scala 234:79]
|
|
wire _T_1125 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[el2_lsu_stbuf.scala 234:79]
|
|
wire _T_1128 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[el2_lsu_stbuf.scala 234:79]
|
|
wire [3:0] ld_byte_rhit_lo = {_T_1128,_T_1125,_T_1122,_T_1119}; // @[Cat.scala 29:58]
|
|
wire _T_1134 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[el2_lsu_stbuf.scala 235:79]
|
|
wire _T_1137 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[el2_lsu_stbuf.scala 235:79]
|
|
wire _T_1140 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[el2_lsu_stbuf.scala 235:79]
|
|
wire _T_1143 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[el2_lsu_stbuf.scala 235:79]
|
|
wire [3:0] ld_byte_rhit_hi = {_T_1143,_T_1140,_T_1137,_T_1134}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1149 = ld_byte_rhit_lo_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1151 = _T_1149 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 237:53]
|
|
wire [7:0] _T_1154 = ld_byte_rhit_hi_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1156 = _T_1154 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 237:114]
|
|
wire [7:0] fwdpipe1_lo = _T_1151 | _T_1156; // @[el2_lsu_stbuf.scala 237:80]
|
|
wire [7:0] _T_1159 = ld_byte_rhit_lo_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1161 = _T_1159 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 238:53]
|
|
wire [7:0] _T_1164 = ld_byte_rhit_hi_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1166 = _T_1164 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 238:115]
|
|
wire [7:0] fwdpipe2_lo = _T_1161 | _T_1166; // @[el2_lsu_stbuf.scala 238:81]
|
|
wire [7:0] _T_1169 = ld_byte_rhit_lo_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1171 = _T_1169 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 239:53]
|
|
wire [7:0] _T_1174 = ld_byte_rhit_hi_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1176 = _T_1174 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 239:116]
|
|
wire [7:0] fwdpipe3_lo = _T_1171 | _T_1176; // @[el2_lsu_stbuf.scala 239:82]
|
|
wire [7:0] _T_1179 = ld_byte_rhit_lo_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1181 = _T_1179 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 240:53]
|
|
wire [7:0] _T_1184 = ld_byte_rhit_hi_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1186 = _T_1184 & io_store_data_hi_r[31:24]; // @[el2_lsu_stbuf.scala 240:116]
|
|
wire [7:0] fwdpipe4_lo = _T_1181 | _T_1186; // @[el2_lsu_stbuf.scala 240:82]
|
|
wire [31:0] ld_fwddata_rpipe_lo = {fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1192 = ld_byte_rhit_lo_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1194 = _T_1192 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 243:53]
|
|
wire [7:0] _T_1197 = ld_byte_rhit_hi_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1199 = _T_1197 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 243:114]
|
|
wire [7:0] fwdpipe1_hi = _T_1194 | _T_1199; // @[el2_lsu_stbuf.scala 243:80]
|
|
wire [7:0] _T_1202 = ld_byte_rhit_lo_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1204 = _T_1202 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 244:53]
|
|
wire [7:0] _T_1207 = ld_byte_rhit_hi_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1209 = _T_1207 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 244:115]
|
|
wire [7:0] fwdpipe2_hi = _T_1204 | _T_1209; // @[el2_lsu_stbuf.scala 244:81]
|
|
wire [7:0] _T_1212 = ld_byte_rhit_lo_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1214 = _T_1212 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 245:53]
|
|
wire [7:0] _T_1217 = ld_byte_rhit_hi_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1219 = _T_1217 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 245:116]
|
|
wire [7:0] fwdpipe3_hi = _T_1214 | _T_1219; // @[el2_lsu_stbuf.scala 245:82]
|
|
wire [7:0] _T_1222 = ld_byte_rhit_lo_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1224 = _T_1222 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 246:53]
|
|
wire [7:0] _T_1227 = ld_byte_rhit_hi_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1229 = _T_1227 & io_store_data_hi_r[31:24]; // @[el2_lsu_stbuf.scala 246:116]
|
|
wire [7:0] fwdpipe4_hi = _T_1224 | _T_1229; // @[el2_lsu_stbuf.scala 246:82]
|
|
wire [31:0] ld_fwddata_rpipe_hi = {fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi}; // @[Cat.scala 29:58]
|
|
wire _T_1264 = ld_byte_rhit_hi[0] | stbuf_fwdbyteen_hi_pre_m_0; // @[el2_lsu_stbuf.scala 252:83]
|
|
wire _T_1266 = ld_byte_rhit_hi[1] | stbuf_fwdbyteen_hi_pre_m_1; // @[el2_lsu_stbuf.scala 252:83]
|
|
wire _T_1268 = ld_byte_rhit_hi[2] | stbuf_fwdbyteen_hi_pre_m_2; // @[el2_lsu_stbuf.scala 252:83]
|
|
wire _T_1270 = ld_byte_rhit_hi[3] | stbuf_fwdbyteen_hi_pre_m_3; // @[el2_lsu_stbuf.scala 252:83]
|
|
wire [2:0] _T_1272 = {_T_1270,_T_1268,_T_1266}; // @[Cat.scala 29:58]
|
|
wire _T_1275 = ld_byte_rhit_lo[0] | stbuf_fwdbyteen_lo_pre_m_0; // @[el2_lsu_stbuf.scala 253:83]
|
|
wire _T_1277 = ld_byte_rhit_lo[1] | stbuf_fwdbyteen_lo_pre_m_1; // @[el2_lsu_stbuf.scala 253:83]
|
|
wire _T_1279 = ld_byte_rhit_lo[2] | stbuf_fwdbyteen_lo_pre_m_2; // @[el2_lsu_stbuf.scala 253:83]
|
|
wire _T_1281 = ld_byte_rhit_lo[3] | stbuf_fwdbyteen_lo_pre_m_3; // @[el2_lsu_stbuf.scala 253:83]
|
|
wire [2:0] _T_1283 = {_T_1281,_T_1279,_T_1277}; // @[Cat.scala 29:58]
|
|
wire [7:0] stbuf_fwdpipe1_lo = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : stbuf_fwddata_lo_pre_m[7:0]; // @[el2_lsu_stbuf.scala 256:30]
|
|
wire [7:0] stbuf_fwdpipe2_lo = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : stbuf_fwddata_lo_pre_m[15:8]; // @[el2_lsu_stbuf.scala 257:30]
|
|
wire [7:0] stbuf_fwdpipe3_lo = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : stbuf_fwddata_lo_pre_m[23:16]; // @[el2_lsu_stbuf.scala 258:30]
|
|
wire [7:0] stbuf_fwdpipe4_lo = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : stbuf_fwddata_lo_pre_m[31:24]; // @[el2_lsu_stbuf.scala 259:30]
|
|
wire [15:0] _T_1297 = {stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_1298 = {stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo}; // @[Cat.scala 29:58]
|
|
wire [7:0] stbuf_fwdpipe1_hi = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : stbuf_fwddata_hi_pre_m[7:0]; // @[el2_lsu_stbuf.scala 262:30]
|
|
wire [7:0] stbuf_fwdpipe2_hi = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : stbuf_fwddata_hi_pre_m[15:8]; // @[el2_lsu_stbuf.scala 263:30]
|
|
wire [7:0] stbuf_fwdpipe3_hi = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : stbuf_fwddata_hi_pre_m[23:16]; // @[el2_lsu_stbuf.scala 264:30]
|
|
wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[el2_lsu_stbuf.scala 265:30]
|
|
wire [15:0] _T_1312 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_1313 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en),
|
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en),
|
|
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
|
);
|
|
assign io_stbuf_reqvld_any = _T_699 & _T_701; // @[el2_lsu_stbuf.scala 51:47 el2_lsu_stbuf.scala 175:24]
|
|
assign io_stbuf_reqvld_flushed_any = _T_689[0] & _T_691[0]; // @[el2_lsu_stbuf.scala 52:35 el2_lsu_stbuf.scala 174:31]
|
|
assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_2; // @[el2_lsu_stbuf.scala 53:35 el2_lsu_stbuf.scala 176:22]
|
|
assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_6; // @[el2_lsu_stbuf.scala 54:35 el2_lsu_stbuf.scala 177:22]
|
|
assign io_lsu_stbuf_full_any = _T_752 ? _T_754 : _T_755; // @[el2_lsu_stbuf.scala 55:43 el2_lsu_stbuf.scala 196:26]
|
|
assign io_lsu_stbuf_empty_any = stbuf_numvld_any == 4'h0; // @[el2_lsu_stbuf.scala 56:43 el2_lsu_stbuf.scala 197:26]
|
|
assign io_ldst_stbuf_reqvld_r = io_lsu_commit_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 57:43 el2_lsu_stbuf.scala 128:26]
|
|
assign io_stbuf_fwddata_hi_m = {_T_1313,_T_1312}; // @[el2_lsu_stbuf.scala 58:43 el2_lsu_stbuf.scala 266:25]
|
|
assign io_stbuf_fwddata_lo_m = {_T_1298,_T_1297}; // @[el2_lsu_stbuf.scala 59:43 el2_lsu_stbuf.scala 260:25]
|
|
assign io_stbuf_fwdbyteen_hi_m = {_T_1272,_T_1264}; // @[el2_lsu_stbuf.scala 60:37 el2_lsu_stbuf.scala 252:27]
|
|
assign io_stbuf_fwdbyteen_lo_m = {_T_1283,_T_1275}; // @[el2_lsu_stbuf.scala 61:37 el2_lsu_stbuf.scala 253:27]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
ldst_dual_r = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
RdPtr = _RAND_1[1:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
WrPtr = _RAND_2[1:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
stbuf_addr_0 = _RAND_3[15:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_588 = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_580 = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_572 = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_564 = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
_T_623 = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
_T_615 = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
_T_607 = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
_T_599 = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
stbuf_addr_1 = _RAND_12[15:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
stbuf_addr_2 = _RAND_13[15:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
stbuf_addr_3 = _RAND_14[15:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
stbuf_byteen_0 = _RAND_15[3:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
stbuf_byteen_1 = _RAND_16[3:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
stbuf_byteen_2 = _RAND_17[3:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
stbuf_byteen_3 = _RAND_18[3:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
stbuf_data_0 = _RAND_19[31:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
stbuf_data_1 = _RAND_20[31:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
stbuf_data_2 = _RAND_21[31:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
stbuf_data_3 = _RAND_22[31:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
ldst_dual_m = _RAND_23[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
ldst_dual_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
RdPtr = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
WrPtr = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_addr_0 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_588 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_580 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_572 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_564 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_623 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_615 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_607 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_599 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_addr_1 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_addr_2 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_addr_3 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_byteen_0 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_byteen_1 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_byteen_2 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_byteen_3 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_data_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_data_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_data_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_data_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ldst_dual_m = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ldst_dual_r <= 1'h0;
|
|
end else begin
|
|
ldst_dual_r <= ldst_dual_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
RdPtr <= 2'h0;
|
|
end else if (_T_212) begin
|
|
RdPtr <= RdPtrPlus1;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
WrPtr <= 2'h0;
|
|
end else if (WrPtrEn) begin
|
|
if (_T_716) begin
|
|
WrPtr <= WrPtrPlus2;
|
|
end else begin
|
|
WrPtr <= WrPtrPlus1;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_addr_0 <= 16'h0;
|
|
end else if (sel_lo[0]) begin
|
|
stbuf_addr_0 <= io_lsu_addr_r[15:0];
|
|
end else begin
|
|
stbuf_addr_0 <= io_end_addr_r[15:0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_588 <= 1'h0;
|
|
end else begin
|
|
_T_588 <= _T_584 & _T_67;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_580 <= 1'h0;
|
|
end else begin
|
|
_T_580 <= _T_576 & _T_56;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_572 <= 1'h0;
|
|
end else begin
|
|
_T_572 <= _T_568 & _T_45;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_564 <= 1'h0;
|
|
end else begin
|
|
_T_564 <= _T_560 & _T_34;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_623 <= 1'h0;
|
|
end else begin
|
|
_T_623 <= _T_619 & _T_67;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_615 <= 1'h0;
|
|
end else begin
|
|
_T_615 <= _T_611 & _T_56;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_607 <= 1'h0;
|
|
end else begin
|
|
_T_607 <= _T_603 & _T_45;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_599 <= 1'h0;
|
|
end else begin
|
|
_T_599 <= _T_595 & _T_34;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_addr_1 <= 16'h0;
|
|
end else if (sel_lo[1]) begin
|
|
stbuf_addr_1 <= io_lsu_addr_r[15:0];
|
|
end else begin
|
|
stbuf_addr_1 <= io_end_addr_r[15:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_addr_2 <= 16'h0;
|
|
end else if (sel_lo[2]) begin
|
|
stbuf_addr_2 <= io_lsu_addr_r[15:0];
|
|
end else begin
|
|
stbuf_addr_2 <= io_end_addr_r[15:0];
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_addr_3 <= 16'h0;
|
|
end else if (sel_lo[3]) begin
|
|
stbuf_addr_3 <= io_lsu_addr_r[15:0];
|
|
end else begin
|
|
stbuf_addr_3 <= io_end_addr_r[15:0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_byteen_0 <= 4'h0;
|
|
end else begin
|
|
stbuf_byteen_0 <= _T_629 & _T_633;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_byteen_1 <= 4'h0;
|
|
end else begin
|
|
stbuf_byteen_1 <= _T_638 & _T_642;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_byteen_2 <= 4'h0;
|
|
end else begin
|
|
stbuf_byteen_2 <= _T_647 & _T_651;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_byteen_3 <= 4'h0;
|
|
end else begin
|
|
stbuf_byteen_3 <= _T_656 & _T_660;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_data_0 <= 32'h0;
|
|
end else begin
|
|
stbuf_data_0 <= {_T_546,_T_545};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_data_1 <= 32'h0;
|
|
end else begin
|
|
stbuf_data_1 <= {_T_549,_T_548};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_data_2 <= 32'h0;
|
|
end else begin
|
|
stbuf_data_2 <= {_T_552,_T_551};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_data_3 <= 32'h0;
|
|
end else begin
|
|
stbuf_data_3 <= {_T_555,_T_554};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ldst_dual_m <= 1'h0;
|
|
end else begin
|
|
ldst_dual_m <= io_lsu_addr_d[2] != io_end_addr_d[2];
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_lsu_ecc(
|
|
input clock,
|
|
input reset,
|
|
input io_lsu_c2_r_clk,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_load,
|
|
input io_lsu_pkt_m_bits_store,
|
|
input io_lsu_pkt_m_bits_dma,
|
|
input [31:0] io_stbuf_data_any,
|
|
input io_dec_tlu_core_ecc_disable,
|
|
input [15:0] io_lsu_addr_m,
|
|
input [15:0] io_end_addr_m,
|
|
input [31:0] io_dccm_rdata_hi_m,
|
|
input [31:0] io_dccm_rdata_lo_m,
|
|
input [6:0] io_dccm_data_ecc_hi_m,
|
|
input [6:0] io_dccm_data_ecc_lo_m,
|
|
input io_ld_single_ecc_error_r,
|
|
input io_ld_single_ecc_error_r_ff,
|
|
input io_lsu_dccm_rden_m,
|
|
input io_addr_in_dccm_m,
|
|
input io_dma_dccm_wen,
|
|
input [31:0] io_dma_dccm_wdata_lo,
|
|
input [31:0] io_dma_dccm_wdata_hi,
|
|
input io_scan_mode,
|
|
output [31:0] io_sec_data_hi_r,
|
|
output [31:0] io_sec_data_lo_r,
|
|
output [31:0] io_sec_data_hi_m,
|
|
output [31:0] io_sec_data_lo_m,
|
|
output [31:0] io_sec_data_hi_r_ff,
|
|
output [31:0] io_sec_data_lo_r_ff,
|
|
output [6:0] io_dma_dccm_wdata_ecc_hi,
|
|
output [6:0] io_dma_dccm_wdata_ecc_lo,
|
|
output [6:0] io_stbuf_ecc_any,
|
|
output [6:0] io_sec_data_ecc_hi_r_ff,
|
|
output [6:0] io_sec_data_ecc_lo_r_ff,
|
|
output io_single_ecc_error_hi_r,
|
|
output io_single_ecc_error_lo_r,
|
|
output io_lsu_single_ecc_error_r,
|
|
output io_lsu_double_ecc_error_r,
|
|
output io_lsu_single_ecc_error_m,
|
|
output io_lsu_double_ecc_error_m
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire _T_96 = ^io_dccm_rdata_hi_m; // @[el2_lib.scala 333:30]
|
|
wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[el2_lib.scala 333:44]
|
|
wire _T_98 = _T_96 ^ _T_97; // @[el2_lib.scala 333:35]
|
|
wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[el2_lib.scala 333:76]
|
|
wire _T_107 = ^_T_106; // @[el2_lib.scala 333:83]
|
|
wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[el2_lib.scala 333:71]
|
|
wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[el2_lib.scala 333:103]
|
|
wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[el2_lib.scala 333:103]
|
|
wire _T_124 = ^_T_123; // @[el2_lib.scala 333:110]
|
|
wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[el2_lib.scala 333:98]
|
|
wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[el2_lib.scala 333:130]
|
|
wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[el2_lib.scala 333:130]
|
|
wire _T_141 = ^_T_140; // @[el2_lib.scala 333:137]
|
|
wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[el2_lib.scala 333:125]
|
|
wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[el2_lib.scala 333:157]
|
|
wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[el2_lib.scala 333:157]
|
|
wire _T_161 = ^_T_160; // @[el2_lib.scala 333:164]
|
|
wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[el2_lib.scala 333:152]
|
|
wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 333:184]
|
|
wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[el2_lib.scala 333:184]
|
|
wire _T_181 = ^_T_180; // @[el2_lib.scala 333:191]
|
|
wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[el2_lib.scala 333:179]
|
|
wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 333:211]
|
|
wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[el2_lib.scala 333:211]
|
|
wire _T_201 = ^_T_200; // @[el2_lib.scala 333:218]
|
|
wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[el2_lib.scala 333:206]
|
|
wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58]
|
|
wire _T_209 = _T_208 != 7'h0; // @[el2_lib.scala 334:44]
|
|
wire _T_1131 = ~io_dec_tlu_core_ecc_disable; // @[el2_lsu_ecc.scala 107:73]
|
|
wire _T_1138 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[el2_lsu_ecc.scala 125:65]
|
|
wire _T_1139 = io_lsu_pkt_m_valid & _T_1138; // @[el2_lsu_ecc.scala 125:39]
|
|
wire _T_1140 = _T_1139 & io_addr_in_dccm_m; // @[el2_lsu_ecc.scala 125:92]
|
|
wire is_ldst_m = _T_1140 & io_lsu_dccm_rden_m; // @[el2_lsu_ecc.scala 125:112]
|
|
wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[el2_lsu_ecc.scala 124:39]
|
|
wire _T_1144 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[el2_lsu_ecc.scala 127:48]
|
|
wire _T_1145 = is_ldst_m & _T_1144; // @[el2_lsu_ecc.scala 127:33]
|
|
wire is_ldst_hi_m = _T_1145 & _T_1131; // @[el2_lsu_ecc.scala 127:73]
|
|
wire _T_210 = is_ldst_hi_m & _T_209; // @[el2_lib.scala 334:32]
|
|
wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[el2_lib.scala 334:53]
|
|
wire _T_215 = ~_T_208[6]; // @[el2_lib.scala 335:55]
|
|
wire double_ecc_error_hi_any = _T_210 & _T_215; // @[el2_lib.scala 335:53]
|
|
wire _T_218 = _T_208[5:0] == 6'h1; // @[el2_lib.scala 339:41]
|
|
wire _T_220 = _T_208[5:0] == 6'h2; // @[el2_lib.scala 339:41]
|
|
wire _T_222 = _T_208[5:0] == 6'h3; // @[el2_lib.scala 339:41]
|
|
wire _T_224 = _T_208[5:0] == 6'h4; // @[el2_lib.scala 339:41]
|
|
wire _T_226 = _T_208[5:0] == 6'h5; // @[el2_lib.scala 339:41]
|
|
wire _T_228 = _T_208[5:0] == 6'h6; // @[el2_lib.scala 339:41]
|
|
wire _T_230 = _T_208[5:0] == 6'h7; // @[el2_lib.scala 339:41]
|
|
wire _T_232 = _T_208[5:0] == 6'h8; // @[el2_lib.scala 339:41]
|
|
wire _T_234 = _T_208[5:0] == 6'h9; // @[el2_lib.scala 339:41]
|
|
wire _T_236 = _T_208[5:0] == 6'ha; // @[el2_lib.scala 339:41]
|
|
wire _T_238 = _T_208[5:0] == 6'hb; // @[el2_lib.scala 339:41]
|
|
wire _T_240 = _T_208[5:0] == 6'hc; // @[el2_lib.scala 339:41]
|
|
wire _T_242 = _T_208[5:0] == 6'hd; // @[el2_lib.scala 339:41]
|
|
wire _T_244 = _T_208[5:0] == 6'he; // @[el2_lib.scala 339:41]
|
|
wire _T_246 = _T_208[5:0] == 6'hf; // @[el2_lib.scala 339:41]
|
|
wire _T_248 = _T_208[5:0] == 6'h10; // @[el2_lib.scala 339:41]
|
|
wire _T_250 = _T_208[5:0] == 6'h11; // @[el2_lib.scala 339:41]
|
|
wire _T_252 = _T_208[5:0] == 6'h12; // @[el2_lib.scala 339:41]
|
|
wire _T_254 = _T_208[5:0] == 6'h13; // @[el2_lib.scala 339:41]
|
|
wire _T_256 = _T_208[5:0] == 6'h14; // @[el2_lib.scala 339:41]
|
|
wire _T_258 = _T_208[5:0] == 6'h15; // @[el2_lib.scala 339:41]
|
|
wire _T_260 = _T_208[5:0] == 6'h16; // @[el2_lib.scala 339:41]
|
|
wire _T_262 = _T_208[5:0] == 6'h17; // @[el2_lib.scala 339:41]
|
|
wire _T_264 = _T_208[5:0] == 6'h18; // @[el2_lib.scala 339:41]
|
|
wire _T_266 = _T_208[5:0] == 6'h19; // @[el2_lib.scala 339:41]
|
|
wire _T_268 = _T_208[5:0] == 6'h1a; // @[el2_lib.scala 339:41]
|
|
wire _T_270 = _T_208[5:0] == 6'h1b; // @[el2_lib.scala 339:41]
|
|
wire _T_272 = _T_208[5:0] == 6'h1c; // @[el2_lib.scala 339:41]
|
|
wire _T_274 = _T_208[5:0] == 6'h1d; // @[el2_lib.scala 339:41]
|
|
wire _T_276 = _T_208[5:0] == 6'h1e; // @[el2_lib.scala 339:41]
|
|
wire _T_278 = _T_208[5:0] == 6'h1f; // @[el2_lib.scala 339:41]
|
|
wire _T_280 = _T_208[5:0] == 6'h20; // @[el2_lib.scala 339:41]
|
|
wire _T_282 = _T_208[5:0] == 6'h21; // @[el2_lib.scala 339:41]
|
|
wire _T_284 = _T_208[5:0] == 6'h22; // @[el2_lib.scala 339:41]
|
|
wire _T_286 = _T_208[5:0] == 6'h23; // @[el2_lib.scala 339:41]
|
|
wire _T_288 = _T_208[5:0] == 6'h24; // @[el2_lib.scala 339:41]
|
|
wire _T_290 = _T_208[5:0] == 6'h25; // @[el2_lib.scala 339:41]
|
|
wire _T_292 = _T_208[5:0] == 6'h26; // @[el2_lib.scala 339:41]
|
|
wire _T_294 = _T_208[5:0] == 6'h27; // @[el2_lib.scala 339:41]
|
|
wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[el2_lib.scala 342:69]
|
|
wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[el2_lib.scala 342:69]
|
|
wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[el2_lib.scala 342:69]
|
|
wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[el2_lib.scala 342:69]
|
|
wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[el2_lib.scala 342:69]
|
|
wire [38:0] _T_355 = _T_354 ^ _T_315; // @[el2_lib.scala 342:76]
|
|
wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[el2_lib.scala 342:31]
|
|
wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58]
|
|
wire _T_474 = ^io_dccm_rdata_lo_m; // @[el2_lib.scala 333:30]
|
|
wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[el2_lib.scala 333:44]
|
|
wire _T_476 = _T_474 ^ _T_475; // @[el2_lib.scala 333:35]
|
|
wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[el2_lib.scala 333:76]
|
|
wire _T_485 = ^_T_484; // @[el2_lib.scala 333:83]
|
|
wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[el2_lib.scala 333:71]
|
|
wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[el2_lib.scala 333:103]
|
|
wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[el2_lib.scala 333:103]
|
|
wire _T_502 = ^_T_501; // @[el2_lib.scala 333:110]
|
|
wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[el2_lib.scala 333:98]
|
|
wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[el2_lib.scala 333:130]
|
|
wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[el2_lib.scala 333:130]
|
|
wire _T_519 = ^_T_518; // @[el2_lib.scala 333:137]
|
|
wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[el2_lib.scala 333:125]
|
|
wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[el2_lib.scala 333:157]
|
|
wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[el2_lib.scala 333:157]
|
|
wire _T_539 = ^_T_538; // @[el2_lib.scala 333:164]
|
|
wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[el2_lib.scala 333:152]
|
|
wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 333:184]
|
|
wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[el2_lib.scala 333:184]
|
|
wire _T_559 = ^_T_558; // @[el2_lib.scala 333:191]
|
|
wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[el2_lib.scala 333:179]
|
|
wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 333:211]
|
|
wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[el2_lib.scala 333:211]
|
|
wire _T_579 = ^_T_578; // @[el2_lib.scala 333:218]
|
|
wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[el2_lib.scala 333:206]
|
|
wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58]
|
|
wire _T_587 = _T_586 != 7'h0; // @[el2_lib.scala 334:44]
|
|
wire is_ldst_lo_m = is_ldst_m & _T_1131; // @[el2_lsu_ecc.scala 126:33]
|
|
wire _T_588 = is_ldst_lo_m & _T_587; // @[el2_lib.scala 334:32]
|
|
wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[el2_lib.scala 334:53]
|
|
wire _T_593 = ~_T_586[6]; // @[el2_lib.scala 335:55]
|
|
wire double_ecc_error_lo_any = _T_588 & _T_593; // @[el2_lib.scala 335:53]
|
|
wire _T_596 = _T_586[5:0] == 6'h1; // @[el2_lib.scala 339:41]
|
|
wire _T_598 = _T_586[5:0] == 6'h2; // @[el2_lib.scala 339:41]
|
|
wire _T_600 = _T_586[5:0] == 6'h3; // @[el2_lib.scala 339:41]
|
|
wire _T_602 = _T_586[5:0] == 6'h4; // @[el2_lib.scala 339:41]
|
|
wire _T_604 = _T_586[5:0] == 6'h5; // @[el2_lib.scala 339:41]
|
|
wire _T_606 = _T_586[5:0] == 6'h6; // @[el2_lib.scala 339:41]
|
|
wire _T_608 = _T_586[5:0] == 6'h7; // @[el2_lib.scala 339:41]
|
|
wire _T_610 = _T_586[5:0] == 6'h8; // @[el2_lib.scala 339:41]
|
|
wire _T_612 = _T_586[5:0] == 6'h9; // @[el2_lib.scala 339:41]
|
|
wire _T_614 = _T_586[5:0] == 6'ha; // @[el2_lib.scala 339:41]
|
|
wire _T_616 = _T_586[5:0] == 6'hb; // @[el2_lib.scala 339:41]
|
|
wire _T_618 = _T_586[5:0] == 6'hc; // @[el2_lib.scala 339:41]
|
|
wire _T_620 = _T_586[5:0] == 6'hd; // @[el2_lib.scala 339:41]
|
|
wire _T_622 = _T_586[5:0] == 6'he; // @[el2_lib.scala 339:41]
|
|
wire _T_624 = _T_586[5:0] == 6'hf; // @[el2_lib.scala 339:41]
|
|
wire _T_626 = _T_586[5:0] == 6'h10; // @[el2_lib.scala 339:41]
|
|
wire _T_628 = _T_586[5:0] == 6'h11; // @[el2_lib.scala 339:41]
|
|
wire _T_630 = _T_586[5:0] == 6'h12; // @[el2_lib.scala 339:41]
|
|
wire _T_632 = _T_586[5:0] == 6'h13; // @[el2_lib.scala 339:41]
|
|
wire _T_634 = _T_586[5:0] == 6'h14; // @[el2_lib.scala 339:41]
|
|
wire _T_636 = _T_586[5:0] == 6'h15; // @[el2_lib.scala 339:41]
|
|
wire _T_638 = _T_586[5:0] == 6'h16; // @[el2_lib.scala 339:41]
|
|
wire _T_640 = _T_586[5:0] == 6'h17; // @[el2_lib.scala 339:41]
|
|
wire _T_642 = _T_586[5:0] == 6'h18; // @[el2_lib.scala 339:41]
|
|
wire _T_644 = _T_586[5:0] == 6'h19; // @[el2_lib.scala 339:41]
|
|
wire _T_646 = _T_586[5:0] == 6'h1a; // @[el2_lib.scala 339:41]
|
|
wire _T_648 = _T_586[5:0] == 6'h1b; // @[el2_lib.scala 339:41]
|
|
wire _T_650 = _T_586[5:0] == 6'h1c; // @[el2_lib.scala 339:41]
|
|
wire _T_652 = _T_586[5:0] == 6'h1d; // @[el2_lib.scala 339:41]
|
|
wire _T_654 = _T_586[5:0] == 6'h1e; // @[el2_lib.scala 339:41]
|
|
wire _T_656 = _T_586[5:0] == 6'h1f; // @[el2_lib.scala 339:41]
|
|
wire _T_658 = _T_586[5:0] == 6'h20; // @[el2_lib.scala 339:41]
|
|
wire _T_660 = _T_586[5:0] == 6'h21; // @[el2_lib.scala 339:41]
|
|
wire _T_662 = _T_586[5:0] == 6'h22; // @[el2_lib.scala 339:41]
|
|
wire _T_664 = _T_586[5:0] == 6'h23; // @[el2_lib.scala 339:41]
|
|
wire _T_666 = _T_586[5:0] == 6'h24; // @[el2_lib.scala 339:41]
|
|
wire _T_668 = _T_586[5:0] == 6'h25; // @[el2_lib.scala 339:41]
|
|
wire _T_670 = _T_586[5:0] == 6'h26; // @[el2_lib.scala 339:41]
|
|
wire _T_672 = _T_586[5:0] == 6'h27; // @[el2_lib.scala 339:41]
|
|
wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[el2_lib.scala 342:69]
|
|
wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[el2_lib.scala 342:69]
|
|
wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[el2_lib.scala 342:69]
|
|
wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[el2_lib.scala 342:69]
|
|
wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[el2_lib.scala 342:69]
|
|
wire [38:0] _T_733 = _T_732 ^ _T_693; // @[el2_lib.scala 342:76]
|
|
wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[el2_lib.scala 342:31]
|
|
wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1158 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[el2_lsu_ecc.scala 149:87]
|
|
wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1158; // @[el2_lsu_ecc.scala 149:27]
|
|
wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[el2_lib.scala 259:74]
|
|
wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74]
|
|
wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[el2_lib.scala 259:74]
|
|
wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74]
|
|
wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74]
|
|
wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[el2_lib.scala 259:74]
|
|
wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74]
|
|
wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74]
|
|
wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74]
|
|
wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[el2_lib.scala 259:74]
|
|
wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74]
|
|
wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74]
|
|
wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[el2_lib.scala 259:74]
|
|
wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74]
|
|
wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[el2_lib.scala 259:74]
|
|
wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74]
|
|
wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74]
|
|
wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[el2_lib.scala 259:74]
|
|
wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74]
|
|
wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74]
|
|
wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74]
|
|
wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[el2_lib.scala 259:74]
|
|
wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74]
|
|
wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74]
|
|
wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[el2_lib.scala 259:74]
|
|
wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74]
|
|
wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[el2_lib.scala 259:74]
|
|
wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74]
|
|
wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74]
|
|
wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[el2_lib.scala 259:74]
|
|
wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74]
|
|
wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74]
|
|
wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74]
|
|
wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[el2_lib.scala 259:74]
|
|
wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74]
|
|
wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74]
|
|
wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[el2_lib.scala 259:74]
|
|
wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74]
|
|
wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[el2_lib.scala 259:74]
|
|
wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74]
|
|
wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74]
|
|
wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[el2_lib.scala 259:74]
|
|
wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74]
|
|
wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74]
|
|
wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74]
|
|
wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[el2_lib.scala 259:74]
|
|
wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74]
|
|
wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[el2_lib.scala 259:74]
|
|
wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74]
|
|
wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74]
|
|
wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[el2_lib.scala 259:74]
|
|
wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74]
|
|
wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74]
|
|
wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74]
|
|
wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[el2_lib.scala 259:74]
|
|
wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74]
|
|
wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[el2_lib.scala 259:74]
|
|
wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74]
|
|
wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74]
|
|
wire [5:0] _T_934 = {_T_929,_T_918,_T_889,_T_860,_T_825,_T_790}; // @[Cat.scala 29:58]
|
|
wire _T_935 = ^dccm_wdata_lo_any; // @[el2_lib.scala 267:13]
|
|
wire _T_936 = ^_T_934; // @[el2_lib.scala 267:23]
|
|
wire _T_937 = _T_935 ^ _T_936; // @[el2_lib.scala 267:18]
|
|
wire [31:0] _T_1162 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[el2_lsu_ecc.scala 150:87]
|
|
wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1162; // @[el2_lsu_ecc.scala 150:27]
|
|
wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[el2_lib.scala 259:74]
|
|
wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74]
|
|
wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[el2_lib.scala 259:74]
|
|
wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74]
|
|
wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74]
|
|
wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[el2_lib.scala 259:74]
|
|
wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74]
|
|
wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74]
|
|
wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74]
|
|
wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[el2_lib.scala 259:74]
|
|
wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74]
|
|
wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74]
|
|
wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[el2_lib.scala 259:74]
|
|
wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74]
|
|
wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[el2_lib.scala 259:74]
|
|
wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74]
|
|
wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74]
|
|
wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[el2_lib.scala 259:74]
|
|
wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74]
|
|
wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74]
|
|
wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74]
|
|
wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[el2_lib.scala 259:74]
|
|
wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74]
|
|
wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74]
|
|
wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[el2_lib.scala 259:74]
|
|
wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74]
|
|
wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[el2_lib.scala 259:74]
|
|
wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74]
|
|
wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74]
|
|
wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[el2_lib.scala 259:74]
|
|
wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74]
|
|
wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74]
|
|
wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74]
|
|
wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[el2_lib.scala 259:74]
|
|
wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74]
|
|
wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74]
|
|
wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[el2_lib.scala 259:74]
|
|
wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74]
|
|
wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[el2_lib.scala 259:74]
|
|
wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74]
|
|
wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74]
|
|
wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74]
|
|
wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[el2_lib.scala 259:74]
|
|
wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74]
|
|
wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74]
|
|
wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74]
|
|
wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[el2_lib.scala 259:74]
|
|
wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74]
|
|
wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[el2_lib.scala 259:74]
|
|
wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74]
|
|
wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74]
|
|
wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74]
|
|
wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[el2_lib.scala 259:74]
|
|
wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74]
|
|
wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74]
|
|
wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74]
|
|
wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74]
|
|
wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74]
|
|
wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74]
|
|
wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74]
|
|
wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[el2_lib.scala 259:74]
|
|
wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74]
|
|
wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[el2_lib.scala 259:74]
|
|
wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74]
|
|
wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74]
|
|
wire [5:0] _T_1116 = {_T_1111,_T_1100,_T_1071,_T_1042,_T_1007,_T_972}; // @[Cat.scala 29:58]
|
|
wire _T_1117 = ^dccm_wdata_hi_any; // @[el2_lib.scala 267:13]
|
|
wire _T_1118 = ^_T_1116; // @[el2_lib.scala 267:23]
|
|
wire _T_1119 = _T_1117 ^ _T_1118; // @[el2_lib.scala 267:18]
|
|
reg _T_1150; // @[el2_lsu_ecc.scala 141:72]
|
|
reg _T_1151; // @[el2_lsu_ecc.scala 142:72]
|
|
reg _T_1152; // @[el2_lsu_ecc.scala 143:72]
|
|
reg _T_1153; // @[el2_lsu_ecc.scala 144:72]
|
|
reg [31:0] _T_1154; // @[el2_lsu_ecc.scala 145:72]
|
|
reg [31:0] _T_1155; // @[el2_lsu_ecc.scala 146:72]
|
|
reg [31:0] _T_1164; // @[el2_lib.scala 514:16]
|
|
reg [31:0] _T_1165; // @[el2_lib.scala 514:16]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
assign io_sec_data_hi_r = _T_1154; // @[el2_lsu_ecc.scala 114:22 el2_lsu_ecc.scala 145:62]
|
|
assign io_sec_data_lo_r = _T_1155; // @[el2_lsu_ecc.scala 117:25 el2_lsu_ecc.scala 146:62]
|
|
assign io_sec_data_hi_m = {_T_364,_T_362}; // @[el2_lsu_ecc.scala 90:32 el2_lsu_ecc.scala 134:27]
|
|
assign io_sec_data_lo_m = {_T_742,_T_740}; // @[el2_lsu_ecc.scala 91:32 el2_lsu_ecc.scala 136:27]
|
|
assign io_sec_data_hi_r_ff = _T_1164; // @[el2_lsu_ecc.scala 157:23]
|
|
assign io_sec_data_lo_r_ff = _T_1165; // @[el2_lsu_ecc.scala 158:23]
|
|
assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[el2_lsu_ecc.scala 154:28]
|
|
assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 155:28]
|
|
assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 153:28]
|
|
assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[el2_lsu_ecc.scala 151:28]
|
|
assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 152:28]
|
|
assign io_single_ecc_error_hi_r = _T_1153; // @[el2_lsu_ecc.scala 115:31 el2_lsu_ecc.scala 144:62]
|
|
assign io_single_ecc_error_lo_r = _T_1152; // @[el2_lsu_ecc.scala 118:31 el2_lsu_ecc.scala 143:62]
|
|
assign io_lsu_single_ecc_error_r = _T_1150; // @[el2_lsu_ecc.scala 120:31 el2_lsu_ecc.scala 141:62]
|
|
assign io_lsu_double_ecc_error_r = _T_1151; // @[el2_lsu_ecc.scala 121:31 el2_lsu_ecc.scala 142:62]
|
|
assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[el2_lsu_ecc.scala 92:30 el2_lsu_ecc.scala 138:33]
|
|
assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[el2_lsu_ecc.scala 93:30 el2_lsu_ecc.scala 139:33]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
_T_1150 = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_1151 = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
_T_1152 = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
_T_1153 = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_1154 = _RAND_4[31:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_1155 = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_1164 = _RAND_6[31:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_1165 = _RAND_7[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_1150 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1151 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1152 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1153 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1154 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1155 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1164 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1165 = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1150 <= 1'h0;
|
|
end else begin
|
|
_T_1150 <= io_lsu_single_ecc_error_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1151 <= 1'h0;
|
|
end else begin
|
|
_T_1151 <= io_lsu_double_ecc_error_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1152 <= 1'h0;
|
|
end else begin
|
|
_T_1152 <= _T_588 & _T_586[6];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1153 <= 1'h0;
|
|
end else begin
|
|
_T_1153 <= _T_210 & _T_208[6];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1154 <= 32'h0;
|
|
end else begin
|
|
_T_1154 <= io_sec_data_hi_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1155 <= 32'h0;
|
|
end else begin
|
|
_T_1155 <= io_sec_data_lo_m;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1164 <= 32'h0;
|
|
end else begin
|
|
_T_1164 <= io_sec_data_hi_r;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1165 <= 32'h0;
|
|
end else begin
|
|
_T_1165 <= io_sec_data_lo_r;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_lsu_trigger(
|
|
input io_trigger_pkt_any_0_select,
|
|
input io_trigger_pkt_any_0_match_pkt,
|
|
input io_trigger_pkt_any_0_store,
|
|
input io_trigger_pkt_any_0_load,
|
|
input [31:0] io_trigger_pkt_any_0_tdata2,
|
|
input io_trigger_pkt_any_1_select,
|
|
input io_trigger_pkt_any_1_match_pkt,
|
|
input io_trigger_pkt_any_1_store,
|
|
input io_trigger_pkt_any_1_load,
|
|
input [31:0] io_trigger_pkt_any_1_tdata2,
|
|
input io_trigger_pkt_any_2_select,
|
|
input io_trigger_pkt_any_2_match_pkt,
|
|
input io_trigger_pkt_any_2_store,
|
|
input io_trigger_pkt_any_2_load,
|
|
input [31:0] io_trigger_pkt_any_2_tdata2,
|
|
input io_trigger_pkt_any_3_select,
|
|
input io_trigger_pkt_any_3_match_pkt,
|
|
input io_trigger_pkt_any_3_store,
|
|
input io_trigger_pkt_any_3_load,
|
|
input [31:0] io_trigger_pkt_any_3_tdata2,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_half,
|
|
input io_lsu_pkt_m_bits_word,
|
|
input io_lsu_pkt_m_bits_load,
|
|
input io_lsu_pkt_m_bits_store,
|
|
input io_lsu_pkt_m_bits_dma,
|
|
input [31:0] io_lsu_addr_m,
|
|
input [31:0] io_store_data_m,
|
|
output [3:0] io_lsu_trigger_match_m
|
|
);
|
|
wire [15:0] _T_1 = io_lsu_pkt_m_bits_word ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
|
wire [15:0] _T_3 = _T_1 & io_store_data_m[31:16]; // @[el2_lsu_trigger.scala 16:66]
|
|
wire _T_4 = io_lsu_pkt_m_bits_half | io_lsu_pkt_m_bits_word; // @[el2_lsu_trigger.scala 16:124]
|
|
wire [7:0] _T_6 = _T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_8 = _T_6 & io_store_data_m[15:8]; // @[el2_lsu_trigger.scala 16:151]
|
|
wire [31:0] store_data_trigger_m = {_T_3,_T_8,io_store_data_m[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_12 = ~io_trigger_pkt_any_0_select; // @[el2_lsu_trigger.scala 17:53]
|
|
wire _T_13 = io_trigger_pkt_any_0_select & io_trigger_pkt_any_0_store; // @[el2_lsu_trigger.scala 17:136]
|
|
wire [31:0] _T_15 = _T_12 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_16 = _T_13 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_match_data_0 = _T_15 | _T_16; // @[Mux.scala 27:72]
|
|
wire _T_19 = ~io_trigger_pkt_any_1_select; // @[el2_lsu_trigger.scala 17:53]
|
|
wire _T_20 = io_trigger_pkt_any_1_select & io_trigger_pkt_any_1_store; // @[el2_lsu_trigger.scala 17:136]
|
|
wire [31:0] _T_22 = _T_19 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_23 = _T_20 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_match_data_1 = _T_22 | _T_23; // @[Mux.scala 27:72]
|
|
wire _T_26 = ~io_trigger_pkt_any_2_select; // @[el2_lsu_trigger.scala 17:53]
|
|
wire _T_27 = io_trigger_pkt_any_2_select & io_trigger_pkt_any_2_store; // @[el2_lsu_trigger.scala 17:136]
|
|
wire [31:0] _T_29 = _T_26 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_30 = _T_27 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_match_data_2 = _T_29 | _T_30; // @[Mux.scala 27:72]
|
|
wire _T_33 = ~io_trigger_pkt_any_3_select; // @[el2_lsu_trigger.scala 17:53]
|
|
wire _T_34 = io_trigger_pkt_any_3_select & io_trigger_pkt_any_3_store; // @[el2_lsu_trigger.scala 17:136]
|
|
wire [31:0] _T_36 = _T_33 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_37 = _T_34 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_match_data_3 = _T_36 | _T_37; // @[Mux.scala 27:72]
|
|
wire _T_39 = ~io_lsu_pkt_m_bits_dma; // @[el2_lsu_trigger.scala 18:71]
|
|
wire _T_40 = io_lsu_pkt_m_valid & _T_39; // @[el2_lsu_trigger.scala 18:69]
|
|
wire _T_41 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_bits_store; // @[el2_lsu_trigger.scala 18:126]
|
|
wire _T_42 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_bits_load; // @[el2_lsu_trigger.scala 19:33]
|
|
wire _T_44 = _T_42 & _T_12; // @[el2_lsu_trigger.scala 19:58]
|
|
wire _T_45 = _T_41 | _T_44; // @[el2_lsu_trigger.scala 18:152]
|
|
wire _T_46 = _T_40 & _T_45; // @[el2_lsu_trigger.scala 18:94]
|
|
wire _T_49 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45]
|
|
wire _T_50 = ~_T_49; // @[el2_lib.scala 241:39]
|
|
wire _T_51 = io_trigger_pkt_any_0_match_pkt & _T_50; // @[el2_lib.scala 241:37]
|
|
wire _T_54 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[el2_lib.scala 242:52]
|
|
wire _T_55 = _T_51 | _T_54; // @[el2_lib.scala 242:41]
|
|
wire _T_57 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36]
|
|
wire _T_58 = _T_57 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_61 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[el2_lib.scala 244:78]
|
|
wire _T_62 = _T_58 | _T_61; // @[el2_lib.scala 244:23]
|
|
wire _T_64 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_65 = _T_64 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_68 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[el2_lib.scala 244:78]
|
|
wire _T_69 = _T_65 | _T_68; // @[el2_lib.scala 244:23]
|
|
wire _T_71 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_72 = _T_71 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_75 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[el2_lib.scala 244:78]
|
|
wire _T_76 = _T_72 | _T_75; // @[el2_lib.scala 244:23]
|
|
wire _T_78 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_79 = _T_78 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_82 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[el2_lib.scala 244:78]
|
|
wire _T_83 = _T_79 | _T_82; // @[el2_lib.scala 244:23]
|
|
wire _T_85 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_86 = _T_85 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_89 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[el2_lib.scala 244:78]
|
|
wire _T_90 = _T_86 | _T_89; // @[el2_lib.scala 244:23]
|
|
wire _T_92 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_93 = _T_92 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_96 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[el2_lib.scala 244:78]
|
|
wire _T_97 = _T_93 | _T_96; // @[el2_lib.scala 244:23]
|
|
wire _T_99 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_100 = _T_99 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_103 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[el2_lib.scala 244:78]
|
|
wire _T_104 = _T_100 | _T_103; // @[el2_lib.scala 244:23]
|
|
wire _T_106 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_107 = _T_106 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_110 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[el2_lib.scala 244:78]
|
|
wire _T_111 = _T_107 | _T_110; // @[el2_lib.scala 244:23]
|
|
wire _T_113 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_114 = _T_113 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_117 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[el2_lib.scala 244:78]
|
|
wire _T_118 = _T_114 | _T_117; // @[el2_lib.scala 244:23]
|
|
wire _T_120 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_121 = _T_120 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_124 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[el2_lib.scala 244:78]
|
|
wire _T_125 = _T_121 | _T_124; // @[el2_lib.scala 244:23]
|
|
wire _T_127 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_128 = _T_127 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_131 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[el2_lib.scala 244:78]
|
|
wire _T_132 = _T_128 | _T_131; // @[el2_lib.scala 244:23]
|
|
wire _T_134 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_135 = _T_134 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_138 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[el2_lib.scala 244:78]
|
|
wire _T_139 = _T_135 | _T_138; // @[el2_lib.scala 244:23]
|
|
wire _T_141 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_142 = _T_141 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_145 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[el2_lib.scala 244:78]
|
|
wire _T_146 = _T_142 | _T_145; // @[el2_lib.scala 244:23]
|
|
wire _T_148 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_149 = _T_148 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_152 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[el2_lib.scala 244:78]
|
|
wire _T_153 = _T_149 | _T_152; // @[el2_lib.scala 244:23]
|
|
wire _T_155 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_156 = _T_155 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_159 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[el2_lib.scala 244:78]
|
|
wire _T_160 = _T_156 | _T_159; // @[el2_lib.scala 244:23]
|
|
wire _T_162 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_163 = _T_162 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_166 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[el2_lib.scala 244:78]
|
|
wire _T_167 = _T_163 | _T_166; // @[el2_lib.scala 244:23]
|
|
wire _T_169 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_170 = _T_169 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_173 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[el2_lib.scala 244:78]
|
|
wire _T_174 = _T_170 | _T_173; // @[el2_lib.scala 244:23]
|
|
wire _T_176 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_177 = _T_176 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_180 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[el2_lib.scala 244:78]
|
|
wire _T_181 = _T_177 | _T_180; // @[el2_lib.scala 244:23]
|
|
wire _T_183 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_184 = _T_183 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_187 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[el2_lib.scala 244:78]
|
|
wire _T_188 = _T_184 | _T_187; // @[el2_lib.scala 244:23]
|
|
wire _T_190 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_191 = _T_190 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_194 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[el2_lib.scala 244:78]
|
|
wire _T_195 = _T_191 | _T_194; // @[el2_lib.scala 244:23]
|
|
wire _T_197 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_198 = _T_197 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_201 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[el2_lib.scala 244:78]
|
|
wire _T_202 = _T_198 | _T_201; // @[el2_lib.scala 244:23]
|
|
wire _T_204 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_205 = _T_204 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_208 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[el2_lib.scala 244:78]
|
|
wire _T_209 = _T_205 | _T_208; // @[el2_lib.scala 244:23]
|
|
wire _T_211 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_212 = _T_211 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_215 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[el2_lib.scala 244:78]
|
|
wire _T_216 = _T_212 | _T_215; // @[el2_lib.scala 244:23]
|
|
wire _T_218 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_219 = _T_218 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_222 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[el2_lib.scala 244:78]
|
|
wire _T_223 = _T_219 | _T_222; // @[el2_lib.scala 244:23]
|
|
wire _T_225 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_226 = _T_225 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_229 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[el2_lib.scala 244:78]
|
|
wire _T_230 = _T_226 | _T_229; // @[el2_lib.scala 244:23]
|
|
wire _T_232 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_233 = _T_232 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_236 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[el2_lib.scala 244:78]
|
|
wire _T_237 = _T_233 | _T_236; // @[el2_lib.scala 244:23]
|
|
wire _T_239 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_240 = _T_239 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_243 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[el2_lib.scala 244:78]
|
|
wire _T_244 = _T_240 | _T_243; // @[el2_lib.scala 244:23]
|
|
wire _T_246 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_247 = _T_246 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_250 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[el2_lib.scala 244:78]
|
|
wire _T_251 = _T_247 | _T_250; // @[el2_lib.scala 244:23]
|
|
wire _T_253 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_254 = _T_253 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_257 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[el2_lib.scala 244:78]
|
|
wire _T_258 = _T_254 | _T_257; // @[el2_lib.scala 244:23]
|
|
wire _T_260 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_261 = _T_260 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_264 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[el2_lib.scala 244:78]
|
|
wire _T_265 = _T_261 | _T_264; // @[el2_lib.scala 244:23]
|
|
wire _T_267 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_268 = _T_267 & _T_51; // @[el2_lib.scala 244:41]
|
|
wire _T_271 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[el2_lib.scala 244:78]
|
|
wire _T_272 = _T_268 | _T_271; // @[el2_lib.scala 244:23]
|
|
wire [7:0] _T_279 = {_T_104,_T_97,_T_90,_T_83,_T_76,_T_69,_T_62,_T_55}; // @[el2_lib.scala 245:14]
|
|
wire [15:0] _T_287 = {_T_160,_T_153,_T_146,_T_139,_T_132,_T_125,_T_118,_T_111,_T_279}; // @[el2_lib.scala 245:14]
|
|
wire [7:0] _T_294 = {_T_216,_T_209,_T_202,_T_195,_T_188,_T_181,_T_174,_T_167}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _T_303 = {_T_272,_T_265,_T_258,_T_251,_T_244,_T_237,_T_230,_T_223,_T_294,_T_287}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _GEN_0 = {{31'd0}, _T_46}; // @[el2_lsu_trigger.scala 19:92]
|
|
wire [31:0] _T_304 = _GEN_0 & _T_303; // @[el2_lsu_trigger.scala 19:92]
|
|
wire _T_307 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[el2_lsu_trigger.scala 18:126]
|
|
wire _T_308 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[el2_lsu_trigger.scala 19:33]
|
|
wire _T_310 = _T_308 & _T_19; // @[el2_lsu_trigger.scala 19:58]
|
|
wire _T_311 = _T_307 | _T_310; // @[el2_lsu_trigger.scala 18:152]
|
|
wire _T_312 = _T_40 & _T_311; // @[el2_lsu_trigger.scala 18:94]
|
|
wire _T_315 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45]
|
|
wire _T_316 = ~_T_315; // @[el2_lib.scala 241:39]
|
|
wire _T_317 = io_trigger_pkt_any_1_match_pkt & _T_316; // @[el2_lib.scala 241:37]
|
|
wire _T_320 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[el2_lib.scala 242:52]
|
|
wire _T_321 = _T_317 | _T_320; // @[el2_lib.scala 242:41]
|
|
wire _T_323 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36]
|
|
wire _T_324 = _T_323 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_327 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[el2_lib.scala 244:78]
|
|
wire _T_328 = _T_324 | _T_327; // @[el2_lib.scala 244:23]
|
|
wire _T_330 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_331 = _T_330 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_334 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[el2_lib.scala 244:78]
|
|
wire _T_335 = _T_331 | _T_334; // @[el2_lib.scala 244:23]
|
|
wire _T_337 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_338 = _T_337 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_341 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[el2_lib.scala 244:78]
|
|
wire _T_342 = _T_338 | _T_341; // @[el2_lib.scala 244:23]
|
|
wire _T_344 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_345 = _T_344 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_348 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[el2_lib.scala 244:78]
|
|
wire _T_349 = _T_345 | _T_348; // @[el2_lib.scala 244:23]
|
|
wire _T_351 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_352 = _T_351 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_355 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[el2_lib.scala 244:78]
|
|
wire _T_356 = _T_352 | _T_355; // @[el2_lib.scala 244:23]
|
|
wire _T_358 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_359 = _T_358 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_362 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[el2_lib.scala 244:78]
|
|
wire _T_363 = _T_359 | _T_362; // @[el2_lib.scala 244:23]
|
|
wire _T_365 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_366 = _T_365 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_369 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[el2_lib.scala 244:78]
|
|
wire _T_370 = _T_366 | _T_369; // @[el2_lib.scala 244:23]
|
|
wire _T_372 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_373 = _T_372 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_376 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[el2_lib.scala 244:78]
|
|
wire _T_377 = _T_373 | _T_376; // @[el2_lib.scala 244:23]
|
|
wire _T_379 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_380 = _T_379 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_383 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[el2_lib.scala 244:78]
|
|
wire _T_384 = _T_380 | _T_383; // @[el2_lib.scala 244:23]
|
|
wire _T_386 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_387 = _T_386 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_390 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[el2_lib.scala 244:78]
|
|
wire _T_391 = _T_387 | _T_390; // @[el2_lib.scala 244:23]
|
|
wire _T_393 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_394 = _T_393 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_397 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[el2_lib.scala 244:78]
|
|
wire _T_398 = _T_394 | _T_397; // @[el2_lib.scala 244:23]
|
|
wire _T_400 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_401 = _T_400 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_404 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[el2_lib.scala 244:78]
|
|
wire _T_405 = _T_401 | _T_404; // @[el2_lib.scala 244:23]
|
|
wire _T_407 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_408 = _T_407 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_411 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[el2_lib.scala 244:78]
|
|
wire _T_412 = _T_408 | _T_411; // @[el2_lib.scala 244:23]
|
|
wire _T_414 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_415 = _T_414 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_418 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[el2_lib.scala 244:78]
|
|
wire _T_419 = _T_415 | _T_418; // @[el2_lib.scala 244:23]
|
|
wire _T_421 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_422 = _T_421 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_425 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[el2_lib.scala 244:78]
|
|
wire _T_426 = _T_422 | _T_425; // @[el2_lib.scala 244:23]
|
|
wire _T_428 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_429 = _T_428 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_432 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[el2_lib.scala 244:78]
|
|
wire _T_433 = _T_429 | _T_432; // @[el2_lib.scala 244:23]
|
|
wire _T_435 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_436 = _T_435 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_439 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[el2_lib.scala 244:78]
|
|
wire _T_440 = _T_436 | _T_439; // @[el2_lib.scala 244:23]
|
|
wire _T_442 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_443 = _T_442 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_446 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[el2_lib.scala 244:78]
|
|
wire _T_447 = _T_443 | _T_446; // @[el2_lib.scala 244:23]
|
|
wire _T_449 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_450 = _T_449 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_453 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[el2_lib.scala 244:78]
|
|
wire _T_454 = _T_450 | _T_453; // @[el2_lib.scala 244:23]
|
|
wire _T_456 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_457 = _T_456 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_460 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[el2_lib.scala 244:78]
|
|
wire _T_461 = _T_457 | _T_460; // @[el2_lib.scala 244:23]
|
|
wire _T_463 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_464 = _T_463 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_467 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[el2_lib.scala 244:78]
|
|
wire _T_468 = _T_464 | _T_467; // @[el2_lib.scala 244:23]
|
|
wire _T_470 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_471 = _T_470 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_474 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[el2_lib.scala 244:78]
|
|
wire _T_475 = _T_471 | _T_474; // @[el2_lib.scala 244:23]
|
|
wire _T_477 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_478 = _T_477 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_481 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[el2_lib.scala 244:78]
|
|
wire _T_482 = _T_478 | _T_481; // @[el2_lib.scala 244:23]
|
|
wire _T_484 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_485 = _T_484 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_488 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[el2_lib.scala 244:78]
|
|
wire _T_489 = _T_485 | _T_488; // @[el2_lib.scala 244:23]
|
|
wire _T_491 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_492 = _T_491 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_495 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[el2_lib.scala 244:78]
|
|
wire _T_496 = _T_492 | _T_495; // @[el2_lib.scala 244:23]
|
|
wire _T_498 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_499 = _T_498 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_502 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[el2_lib.scala 244:78]
|
|
wire _T_503 = _T_499 | _T_502; // @[el2_lib.scala 244:23]
|
|
wire _T_505 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_506 = _T_505 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_509 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[el2_lib.scala 244:78]
|
|
wire _T_510 = _T_506 | _T_509; // @[el2_lib.scala 244:23]
|
|
wire _T_512 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_513 = _T_512 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_516 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[el2_lib.scala 244:78]
|
|
wire _T_517 = _T_513 | _T_516; // @[el2_lib.scala 244:23]
|
|
wire _T_519 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_520 = _T_519 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_523 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[el2_lib.scala 244:78]
|
|
wire _T_524 = _T_520 | _T_523; // @[el2_lib.scala 244:23]
|
|
wire _T_526 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_527 = _T_526 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_530 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[el2_lib.scala 244:78]
|
|
wire _T_531 = _T_527 | _T_530; // @[el2_lib.scala 244:23]
|
|
wire _T_533 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_534 = _T_533 & _T_317; // @[el2_lib.scala 244:41]
|
|
wire _T_537 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[el2_lib.scala 244:78]
|
|
wire _T_538 = _T_534 | _T_537; // @[el2_lib.scala 244:23]
|
|
wire [7:0] _T_545 = {_T_370,_T_363,_T_356,_T_349,_T_342,_T_335,_T_328,_T_321}; // @[el2_lib.scala 245:14]
|
|
wire [15:0] _T_553 = {_T_426,_T_419,_T_412,_T_405,_T_398,_T_391,_T_384,_T_377,_T_545}; // @[el2_lib.scala 245:14]
|
|
wire [7:0] _T_560 = {_T_482,_T_475,_T_468,_T_461,_T_454,_T_447,_T_440,_T_433}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _T_569 = {_T_538,_T_531,_T_524,_T_517,_T_510,_T_503,_T_496,_T_489,_T_560,_T_553}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _GEN_1 = {{31'd0}, _T_312}; // @[el2_lsu_trigger.scala 19:92]
|
|
wire [31:0] _T_570 = _GEN_1 & _T_569; // @[el2_lsu_trigger.scala 19:92]
|
|
wire _T_573 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[el2_lsu_trigger.scala 18:126]
|
|
wire _T_574 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[el2_lsu_trigger.scala 19:33]
|
|
wire _T_576 = _T_574 & _T_26; // @[el2_lsu_trigger.scala 19:58]
|
|
wire _T_577 = _T_573 | _T_576; // @[el2_lsu_trigger.scala 18:152]
|
|
wire _T_578 = _T_40 & _T_577; // @[el2_lsu_trigger.scala 18:94]
|
|
wire _T_581 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45]
|
|
wire _T_582 = ~_T_581; // @[el2_lib.scala 241:39]
|
|
wire _T_583 = io_trigger_pkt_any_2_match_pkt & _T_582; // @[el2_lib.scala 241:37]
|
|
wire _T_586 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[el2_lib.scala 242:52]
|
|
wire _T_587 = _T_583 | _T_586; // @[el2_lib.scala 242:41]
|
|
wire _T_589 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36]
|
|
wire _T_590 = _T_589 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_593 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[el2_lib.scala 244:78]
|
|
wire _T_594 = _T_590 | _T_593; // @[el2_lib.scala 244:23]
|
|
wire _T_596 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_597 = _T_596 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_600 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[el2_lib.scala 244:78]
|
|
wire _T_601 = _T_597 | _T_600; // @[el2_lib.scala 244:23]
|
|
wire _T_603 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_604 = _T_603 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_607 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[el2_lib.scala 244:78]
|
|
wire _T_608 = _T_604 | _T_607; // @[el2_lib.scala 244:23]
|
|
wire _T_610 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_611 = _T_610 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_614 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[el2_lib.scala 244:78]
|
|
wire _T_615 = _T_611 | _T_614; // @[el2_lib.scala 244:23]
|
|
wire _T_617 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_618 = _T_617 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_621 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[el2_lib.scala 244:78]
|
|
wire _T_622 = _T_618 | _T_621; // @[el2_lib.scala 244:23]
|
|
wire _T_624 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_625 = _T_624 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_628 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[el2_lib.scala 244:78]
|
|
wire _T_629 = _T_625 | _T_628; // @[el2_lib.scala 244:23]
|
|
wire _T_631 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_632 = _T_631 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_635 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[el2_lib.scala 244:78]
|
|
wire _T_636 = _T_632 | _T_635; // @[el2_lib.scala 244:23]
|
|
wire _T_638 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_639 = _T_638 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_642 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[el2_lib.scala 244:78]
|
|
wire _T_643 = _T_639 | _T_642; // @[el2_lib.scala 244:23]
|
|
wire _T_645 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_646 = _T_645 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_649 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[el2_lib.scala 244:78]
|
|
wire _T_650 = _T_646 | _T_649; // @[el2_lib.scala 244:23]
|
|
wire _T_652 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_653 = _T_652 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_656 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[el2_lib.scala 244:78]
|
|
wire _T_657 = _T_653 | _T_656; // @[el2_lib.scala 244:23]
|
|
wire _T_659 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_660 = _T_659 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_663 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[el2_lib.scala 244:78]
|
|
wire _T_664 = _T_660 | _T_663; // @[el2_lib.scala 244:23]
|
|
wire _T_666 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_667 = _T_666 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_670 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[el2_lib.scala 244:78]
|
|
wire _T_671 = _T_667 | _T_670; // @[el2_lib.scala 244:23]
|
|
wire _T_673 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_674 = _T_673 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_677 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[el2_lib.scala 244:78]
|
|
wire _T_678 = _T_674 | _T_677; // @[el2_lib.scala 244:23]
|
|
wire _T_680 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_681 = _T_680 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_684 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[el2_lib.scala 244:78]
|
|
wire _T_685 = _T_681 | _T_684; // @[el2_lib.scala 244:23]
|
|
wire _T_687 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_688 = _T_687 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_691 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[el2_lib.scala 244:78]
|
|
wire _T_692 = _T_688 | _T_691; // @[el2_lib.scala 244:23]
|
|
wire _T_694 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_695 = _T_694 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_698 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[el2_lib.scala 244:78]
|
|
wire _T_699 = _T_695 | _T_698; // @[el2_lib.scala 244:23]
|
|
wire _T_701 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_702 = _T_701 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_705 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[el2_lib.scala 244:78]
|
|
wire _T_706 = _T_702 | _T_705; // @[el2_lib.scala 244:23]
|
|
wire _T_708 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_709 = _T_708 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_712 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[el2_lib.scala 244:78]
|
|
wire _T_713 = _T_709 | _T_712; // @[el2_lib.scala 244:23]
|
|
wire _T_715 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_716 = _T_715 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_719 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[el2_lib.scala 244:78]
|
|
wire _T_720 = _T_716 | _T_719; // @[el2_lib.scala 244:23]
|
|
wire _T_722 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_723 = _T_722 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_726 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[el2_lib.scala 244:78]
|
|
wire _T_727 = _T_723 | _T_726; // @[el2_lib.scala 244:23]
|
|
wire _T_729 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_730 = _T_729 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_733 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[el2_lib.scala 244:78]
|
|
wire _T_734 = _T_730 | _T_733; // @[el2_lib.scala 244:23]
|
|
wire _T_736 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_737 = _T_736 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_740 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[el2_lib.scala 244:78]
|
|
wire _T_741 = _T_737 | _T_740; // @[el2_lib.scala 244:23]
|
|
wire _T_743 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_744 = _T_743 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_747 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[el2_lib.scala 244:78]
|
|
wire _T_748 = _T_744 | _T_747; // @[el2_lib.scala 244:23]
|
|
wire _T_750 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_751 = _T_750 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_754 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[el2_lib.scala 244:78]
|
|
wire _T_755 = _T_751 | _T_754; // @[el2_lib.scala 244:23]
|
|
wire _T_757 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_758 = _T_757 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_761 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[el2_lib.scala 244:78]
|
|
wire _T_762 = _T_758 | _T_761; // @[el2_lib.scala 244:23]
|
|
wire _T_764 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_765 = _T_764 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_768 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[el2_lib.scala 244:78]
|
|
wire _T_769 = _T_765 | _T_768; // @[el2_lib.scala 244:23]
|
|
wire _T_771 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_772 = _T_771 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_775 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[el2_lib.scala 244:78]
|
|
wire _T_776 = _T_772 | _T_775; // @[el2_lib.scala 244:23]
|
|
wire _T_778 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_779 = _T_778 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_782 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[el2_lib.scala 244:78]
|
|
wire _T_783 = _T_779 | _T_782; // @[el2_lib.scala 244:23]
|
|
wire _T_785 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_786 = _T_785 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_789 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[el2_lib.scala 244:78]
|
|
wire _T_790 = _T_786 | _T_789; // @[el2_lib.scala 244:23]
|
|
wire _T_792 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_793 = _T_792 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_796 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[el2_lib.scala 244:78]
|
|
wire _T_797 = _T_793 | _T_796; // @[el2_lib.scala 244:23]
|
|
wire _T_799 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_800 = _T_799 & _T_583; // @[el2_lib.scala 244:41]
|
|
wire _T_803 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[el2_lib.scala 244:78]
|
|
wire _T_804 = _T_800 | _T_803; // @[el2_lib.scala 244:23]
|
|
wire [7:0] _T_811 = {_T_636,_T_629,_T_622,_T_615,_T_608,_T_601,_T_594,_T_587}; // @[el2_lib.scala 245:14]
|
|
wire [15:0] _T_819 = {_T_692,_T_685,_T_678,_T_671,_T_664,_T_657,_T_650,_T_643,_T_811}; // @[el2_lib.scala 245:14]
|
|
wire [7:0] _T_826 = {_T_748,_T_741,_T_734,_T_727,_T_720,_T_713,_T_706,_T_699}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _T_835 = {_T_804,_T_797,_T_790,_T_783,_T_776,_T_769,_T_762,_T_755,_T_826,_T_819}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _GEN_2 = {{31'd0}, _T_578}; // @[el2_lsu_trigger.scala 19:92]
|
|
wire [31:0] _T_836 = _GEN_2 & _T_835; // @[el2_lsu_trigger.scala 19:92]
|
|
wire _T_839 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[el2_lsu_trigger.scala 18:126]
|
|
wire _T_840 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[el2_lsu_trigger.scala 19:33]
|
|
wire _T_842 = _T_840 & _T_33; // @[el2_lsu_trigger.scala 19:58]
|
|
wire _T_843 = _T_839 | _T_842; // @[el2_lsu_trigger.scala 18:152]
|
|
wire _T_844 = _T_40 & _T_843; // @[el2_lsu_trigger.scala 18:94]
|
|
wire _T_847 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45]
|
|
wire _T_848 = ~_T_847; // @[el2_lib.scala 241:39]
|
|
wire _T_849 = io_trigger_pkt_any_3_match_pkt & _T_848; // @[el2_lib.scala 241:37]
|
|
wire _T_852 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[el2_lib.scala 242:52]
|
|
wire _T_853 = _T_849 | _T_852; // @[el2_lib.scala 242:41]
|
|
wire _T_855 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36]
|
|
wire _T_856 = _T_855 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_859 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[el2_lib.scala 244:78]
|
|
wire _T_860 = _T_856 | _T_859; // @[el2_lib.scala 244:23]
|
|
wire _T_862 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_863 = _T_862 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_866 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[el2_lib.scala 244:78]
|
|
wire _T_867 = _T_863 | _T_866; // @[el2_lib.scala 244:23]
|
|
wire _T_869 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_870 = _T_869 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_873 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[el2_lib.scala 244:78]
|
|
wire _T_874 = _T_870 | _T_873; // @[el2_lib.scala 244:23]
|
|
wire _T_876 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_877 = _T_876 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_880 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[el2_lib.scala 244:78]
|
|
wire _T_881 = _T_877 | _T_880; // @[el2_lib.scala 244:23]
|
|
wire _T_883 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_884 = _T_883 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_887 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[el2_lib.scala 244:78]
|
|
wire _T_888 = _T_884 | _T_887; // @[el2_lib.scala 244:23]
|
|
wire _T_890 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_891 = _T_890 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_894 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[el2_lib.scala 244:78]
|
|
wire _T_895 = _T_891 | _T_894; // @[el2_lib.scala 244:23]
|
|
wire _T_897 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_898 = _T_897 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_901 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[el2_lib.scala 244:78]
|
|
wire _T_902 = _T_898 | _T_901; // @[el2_lib.scala 244:23]
|
|
wire _T_904 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_905 = _T_904 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_908 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[el2_lib.scala 244:78]
|
|
wire _T_909 = _T_905 | _T_908; // @[el2_lib.scala 244:23]
|
|
wire _T_911 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_912 = _T_911 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_915 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[el2_lib.scala 244:78]
|
|
wire _T_916 = _T_912 | _T_915; // @[el2_lib.scala 244:23]
|
|
wire _T_918 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_919 = _T_918 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_922 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[el2_lib.scala 244:78]
|
|
wire _T_923 = _T_919 | _T_922; // @[el2_lib.scala 244:23]
|
|
wire _T_925 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_926 = _T_925 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_929 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[el2_lib.scala 244:78]
|
|
wire _T_930 = _T_926 | _T_929; // @[el2_lib.scala 244:23]
|
|
wire _T_932 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_933 = _T_932 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_936 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[el2_lib.scala 244:78]
|
|
wire _T_937 = _T_933 | _T_936; // @[el2_lib.scala 244:23]
|
|
wire _T_939 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_940 = _T_939 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_943 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[el2_lib.scala 244:78]
|
|
wire _T_944 = _T_940 | _T_943; // @[el2_lib.scala 244:23]
|
|
wire _T_946 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_947 = _T_946 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_950 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[el2_lib.scala 244:78]
|
|
wire _T_951 = _T_947 | _T_950; // @[el2_lib.scala 244:23]
|
|
wire _T_953 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_954 = _T_953 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_957 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[el2_lib.scala 244:78]
|
|
wire _T_958 = _T_954 | _T_957; // @[el2_lib.scala 244:23]
|
|
wire _T_960 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_961 = _T_960 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_964 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[el2_lib.scala 244:78]
|
|
wire _T_965 = _T_961 | _T_964; // @[el2_lib.scala 244:23]
|
|
wire _T_967 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_968 = _T_967 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_971 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[el2_lib.scala 244:78]
|
|
wire _T_972 = _T_968 | _T_971; // @[el2_lib.scala 244:23]
|
|
wire _T_974 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_975 = _T_974 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_978 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[el2_lib.scala 244:78]
|
|
wire _T_979 = _T_975 | _T_978; // @[el2_lib.scala 244:23]
|
|
wire _T_981 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_982 = _T_981 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_985 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[el2_lib.scala 244:78]
|
|
wire _T_986 = _T_982 | _T_985; // @[el2_lib.scala 244:23]
|
|
wire _T_988 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_989 = _T_988 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_992 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[el2_lib.scala 244:78]
|
|
wire _T_993 = _T_989 | _T_992; // @[el2_lib.scala 244:23]
|
|
wire _T_995 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_996 = _T_995 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_999 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[el2_lib.scala 244:78]
|
|
wire _T_1000 = _T_996 | _T_999; // @[el2_lib.scala 244:23]
|
|
wire _T_1002 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1003 = _T_1002 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_1006 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[el2_lib.scala 244:78]
|
|
wire _T_1007 = _T_1003 | _T_1006; // @[el2_lib.scala 244:23]
|
|
wire _T_1009 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1010 = _T_1009 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_1013 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[el2_lib.scala 244:78]
|
|
wire _T_1014 = _T_1010 | _T_1013; // @[el2_lib.scala 244:23]
|
|
wire _T_1016 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1017 = _T_1016 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_1020 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[el2_lib.scala 244:78]
|
|
wire _T_1021 = _T_1017 | _T_1020; // @[el2_lib.scala 244:23]
|
|
wire _T_1023 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1024 = _T_1023 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_1027 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[el2_lib.scala 244:78]
|
|
wire _T_1028 = _T_1024 | _T_1027; // @[el2_lib.scala 244:23]
|
|
wire _T_1030 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1031 = _T_1030 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_1034 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[el2_lib.scala 244:78]
|
|
wire _T_1035 = _T_1031 | _T_1034; // @[el2_lib.scala 244:23]
|
|
wire _T_1037 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1038 = _T_1037 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_1041 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[el2_lib.scala 244:78]
|
|
wire _T_1042 = _T_1038 | _T_1041; // @[el2_lib.scala 244:23]
|
|
wire _T_1044 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1045 = _T_1044 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_1048 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[el2_lib.scala 244:78]
|
|
wire _T_1049 = _T_1045 | _T_1048; // @[el2_lib.scala 244:23]
|
|
wire _T_1051 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1052 = _T_1051 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_1055 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[el2_lib.scala 244:78]
|
|
wire _T_1056 = _T_1052 | _T_1055; // @[el2_lib.scala 244:23]
|
|
wire _T_1058 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1059 = _T_1058 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_1062 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[el2_lib.scala 244:78]
|
|
wire _T_1063 = _T_1059 | _T_1062; // @[el2_lib.scala 244:23]
|
|
wire _T_1065 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 244:36]
|
|
wire _T_1066 = _T_1065 & _T_849; // @[el2_lib.scala 244:41]
|
|
wire _T_1069 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[el2_lib.scala 244:78]
|
|
wire _T_1070 = _T_1066 | _T_1069; // @[el2_lib.scala 244:23]
|
|
wire [7:0] _T_1077 = {_T_902,_T_895,_T_888,_T_881,_T_874,_T_867,_T_860,_T_853}; // @[el2_lib.scala 245:14]
|
|
wire [15:0] _T_1085 = {_T_958,_T_951,_T_944,_T_937,_T_930,_T_923,_T_916,_T_909,_T_1077}; // @[el2_lib.scala 245:14]
|
|
wire [7:0] _T_1092 = {_T_1014,_T_1007,_T_1000,_T_993,_T_986,_T_979,_T_972,_T_965}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _T_1101 = {_T_1070,_T_1063,_T_1056,_T_1049,_T_1042,_T_1035,_T_1028,_T_1021,_T_1092,_T_1085}; // @[el2_lib.scala 245:14]
|
|
wire [31:0] _GEN_3 = {{31'd0}, _T_844}; // @[el2_lsu_trigger.scala 19:92]
|
|
wire [31:0] _T_1102 = _GEN_3 & _T_1101; // @[el2_lsu_trigger.scala 19:92]
|
|
wire [127:0] _T_1105 = {_T_1102,_T_836,_T_570,_T_304}; // @[Cat.scala 29:58]
|
|
assign io_lsu_trigger_match_m = _T_1105[3:0]; // @[el2_lsu_trigger.scala 18:26]
|
|
endmodule
|
|
module el2_lsu_clkdomain(
|
|
input clock,
|
|
input reset,
|
|
input io_free_clk,
|
|
input io_clk_override,
|
|
input io_dma_dccm_req,
|
|
input io_ldst_stbuf_reqvld_r,
|
|
input io_stbuf_reqvld_any,
|
|
input io_stbuf_reqvld_flushed_any,
|
|
input io_lsu_busreq_r,
|
|
input io_lsu_bus_buffer_pend_any,
|
|
input io_lsu_bus_buffer_empty_any,
|
|
input io_lsu_stbuf_empty_any,
|
|
input io_lsu_bus_clk_en,
|
|
input io_lsu_p_valid,
|
|
input io_lsu_pkt_d_valid,
|
|
input io_lsu_pkt_d_bits_store,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_store,
|
|
input io_lsu_pkt_r_valid,
|
|
output io_lsu_c1_m_clk,
|
|
output io_lsu_c1_r_clk,
|
|
output io_lsu_c2_m_clk,
|
|
output io_lsu_c2_r_clk,
|
|
output io_lsu_store_c1_m_clk,
|
|
output io_lsu_stbuf_c1_clk,
|
|
output io_lsu_bus_obuf_c1_clk,
|
|
output io_lsu_bus_ibuf_c1_clk,
|
|
output io_lsu_bus_buf_c1_clk,
|
|
output io_lsu_busm_clk,
|
|
output io_lsu_free_c2_clk,
|
|
input io_scan_mode
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_6_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_7_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_8_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_10_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_11_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[el2_lsu_clkdomain.scala 63:51]
|
|
reg lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 82:67]
|
|
wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 64:51]
|
|
wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 64:70]
|
|
reg lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 83:67]
|
|
wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 65:51]
|
|
wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 65:70]
|
|
wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 67:47]
|
|
reg lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 84:67]
|
|
wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 68:47]
|
|
wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_bits_store; // @[el2_lsu_clkdomain.scala 70:49]
|
|
wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_bits_store; // @[el2_lsu_clkdomain.scala 71:49]
|
|
wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[el2_lsu_clkdomain.scala 72:55]
|
|
wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[el2_lsu_clkdomain.scala 72:77]
|
|
wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 74:61]
|
|
wire _T_10 = _T_9 | io_clk_override; // @[el2_lsu_clkdomain.scala 74:79]
|
|
wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[el2_lsu_clkdomain.scala 75:32]
|
|
wire _T_12 = _T_11 | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 75:61]
|
|
wire _T_13 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[el2_lsu_clkdomain.scala 77:48]
|
|
wire _T_14 = _T_13 | io_lsu_pkt_m_valid; // @[el2_lsu_clkdomain.scala 77:69]
|
|
wire _T_15 = _T_14 | io_lsu_pkt_r_valid; // @[el2_lsu_clkdomain.scala 77:90]
|
|
wire _T_17 = _T_15 | _T_11; // @[el2_lsu_clkdomain.scala 77:112]
|
|
wire _T_18 = ~io_lsu_stbuf_empty_any; // @[el2_lsu_clkdomain.scala 77:145]
|
|
wire _T_19 = _T_17 | _T_18; // @[el2_lsu_clkdomain.scala 77:143]
|
|
wire lsu_free_c1_clken = _T_19 | io_clk_override; // @[el2_lsu_clkdomain.scala 77:169]
|
|
reg lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 81:60]
|
|
wire _T_20 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 78:50]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en),
|
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en),
|
|
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_8_io_l1clk),
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en),
|
|
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_9_io_l1clk),
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en),
|
|
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_10_io_l1clk),
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en),
|
|
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_11_io_l1clk),
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en),
|
|
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
|
);
|
|
assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[el2_lsu_clkdomain.scala 86:26]
|
|
assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[el2_lsu_clkdomain.scala 87:26]
|
|
assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[el2_lsu_clkdomain.scala 88:26]
|
|
assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[el2_lsu_clkdomain.scala 89:26]
|
|
assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[el2_lsu_clkdomain.scala 90:26]
|
|
assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[el2_lsu_clkdomain.scala 92:26]
|
|
assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[el2_lsu_clkdomain.scala 94:26]
|
|
assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[el2_lsu_clkdomain.scala 93:26]
|
|
assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[el2_lsu_clkdomain.scala 95:26]
|
|
assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[el2_lsu_clkdomain.scala 96:26]
|
|
assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[el2_lsu_clkdomain.scala 97:26]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_io_en = _T_1 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_1_io_en = _T_2 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_2_io_en = _T_3 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_3_io_en = _T_4 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_4_io_en = _T_5 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_5_io_en = _T_6 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_6_io_en = _T_8 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_8_io_en = _T_10 & io_lsu_bus_clk_en; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_9_io_en = _T_12 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_10_io_en = io_lsu_bus_clk_en; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_11_io_en = _T_20 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
lsu_c1_d_clken_q = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
lsu_c1_m_clken_q = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
lsu_c1_r_clken_q = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
lsu_free_c1_clken_q = _RAND_3[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
lsu_c1_d_clken_q = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_c1_m_clken_q = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_c1_r_clken_q = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_free_c1_clken_q = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_c1_d_clken_q <= 1'h0;
|
|
end else begin
|
|
lsu_c1_d_clken_q <= _T | io_clk_override;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_c1_m_clken_q <= 1'h0;
|
|
end else begin
|
|
lsu_c1_m_clken_q <= _T_1 | io_clk_override;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_c1_r_clken_q <= 1'h0;
|
|
end else begin
|
|
lsu_c1_r_clken_q <= _T_2 | io_clk_override;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_free_c1_clken_q <= 1'h0;
|
|
end else begin
|
|
lsu_free_c1_clken_q <= _T_19 | io_clk_override;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_lsu_bus_buffer(
|
|
input clock,
|
|
input reset,
|
|
input io_scan_mode,
|
|
input io_dec_tlu_external_ldfwd_disable,
|
|
input io_dec_tlu_wb_coalescing_disable,
|
|
input io_dec_tlu_sideeffect_posted_disable,
|
|
input io_dec_tlu_force_halt,
|
|
input io_lsu_c2_r_clk,
|
|
input io_lsu_bus_ibuf_c1_clk,
|
|
input io_lsu_bus_obuf_c1_clk,
|
|
input io_lsu_bus_buf_c1_clk,
|
|
input io_lsu_free_c2_clk,
|
|
input io_lsu_busm_clk,
|
|
input io_dec_lsu_valid_raw_d,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_load,
|
|
input io_lsu_pkt_r_bits_by,
|
|
input io_lsu_pkt_r_bits_half,
|
|
input io_lsu_pkt_r_bits_word,
|
|
input io_lsu_pkt_r_bits_load,
|
|
input io_lsu_pkt_r_bits_store,
|
|
input io_lsu_pkt_r_bits_unsign,
|
|
input [31:0] io_lsu_addr_m,
|
|
input [31:0] io_end_addr_m,
|
|
input [31:0] io_lsu_addr_r,
|
|
input [31:0] io_end_addr_r,
|
|
input [31:0] io_store_data_r,
|
|
input io_no_word_merge_r,
|
|
input io_no_dword_merge_r,
|
|
input io_lsu_busreq_m,
|
|
input io_ld_full_hit_m,
|
|
input io_flush_m_up,
|
|
input io_flush_r,
|
|
input io_lsu_commit_r,
|
|
input io_is_sideeffects_r,
|
|
input io_ldst_dual_d,
|
|
input io_ldst_dual_m,
|
|
input io_ldst_dual_r,
|
|
input [7:0] io_ldst_byteen_ext_m,
|
|
input io_lsu_axi_wready,
|
|
input io_lsu_axi_bvalid,
|
|
input [1:0] io_lsu_axi_bresp,
|
|
input [2:0] io_lsu_axi_bid,
|
|
input io_lsu_axi_arready,
|
|
input io_lsu_axi_rvalid,
|
|
input [2:0] io_lsu_axi_rid,
|
|
input [63:0] io_lsu_axi_rdata,
|
|
input io_lsu_bus_clk_en,
|
|
input io_lsu_bus_clk_en_q,
|
|
output io_lsu_busreq_r,
|
|
output io_lsu_bus_buffer_pend_any,
|
|
output io_lsu_bus_buffer_full_any,
|
|
output io_lsu_bus_buffer_empty_any,
|
|
output [3:0] io_ld_byte_hit_buf_lo,
|
|
output [3:0] io_ld_byte_hit_buf_hi,
|
|
output [31:0] io_ld_fwddata_buf_lo,
|
|
output [31:0] io_ld_fwddata_buf_hi,
|
|
output io_lsu_imprecise_error_load_any,
|
|
output io_lsu_imprecise_error_store_any,
|
|
output [31:0] io_lsu_imprecise_error_addr_any,
|
|
output io_lsu_nonblock_load_valid_m,
|
|
output [1:0] io_lsu_nonblock_load_tag_m,
|
|
output io_lsu_nonblock_load_inv_r,
|
|
output [1:0] io_lsu_nonblock_load_inv_tag_r,
|
|
output io_lsu_nonblock_load_data_valid,
|
|
output io_lsu_nonblock_load_data_error,
|
|
output [1:0] io_lsu_nonblock_load_data_tag,
|
|
output [31:0] io_lsu_nonblock_load_data,
|
|
output io_lsu_pmu_bus_trxn,
|
|
output io_lsu_pmu_bus_misaligned,
|
|
output io_lsu_pmu_bus_error,
|
|
output io_lsu_pmu_bus_busy,
|
|
output io_lsu_axi_awvalid,
|
|
input io_lsu_axi_awready,
|
|
output [2:0] io_lsu_axi_awid,
|
|
output [31:0] io_lsu_axi_awaddr,
|
|
output [3:0] io_lsu_axi_awregion,
|
|
output [2:0] io_lsu_axi_awsize,
|
|
output [3:0] io_lsu_axi_awcache,
|
|
output io_lsu_axi_wvalid,
|
|
output [63:0] io_lsu_axi_wdata,
|
|
output [7:0] io_lsu_axi_wstrb,
|
|
output io_lsu_axi_bready,
|
|
output io_lsu_axi_arvalid,
|
|
output [2:0] io_lsu_axi_arid,
|
|
output [31:0] io_lsu_axi_araddr,
|
|
output [3:0] io_lsu_axi_arregion,
|
|
output [2:0] io_lsu_axi_arsize,
|
|
output [3:0] io_lsu_axi_arcache,
|
|
output io_lsu_axi_rready
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
reg [31:0] _RAND_75;
|
|
reg [31:0] _RAND_76;
|
|
reg [31:0] _RAND_77;
|
|
reg [31:0] _RAND_78;
|
|
reg [31:0] _RAND_79;
|
|
reg [63:0] _RAND_80;
|
|
reg [31:0] _RAND_81;
|
|
reg [31:0] _RAND_82;
|
|
reg [31:0] _RAND_83;
|
|
reg [31:0] _RAND_84;
|
|
reg [31:0] _RAND_85;
|
|
reg [31:0] _RAND_86;
|
|
reg [31:0] _RAND_87;
|
|
reg [31:0] _RAND_88;
|
|
reg [31:0] _RAND_89;
|
|
reg [31:0] _RAND_90;
|
|
reg [31:0] _RAND_91;
|
|
reg [31:0] _RAND_92;
|
|
reg [31:0] _RAND_93;
|
|
reg [31:0] _RAND_94;
|
|
reg [31:0] _RAND_95;
|
|
reg [31:0] _RAND_96;
|
|
reg [31:0] _RAND_97;
|
|
reg [31:0] _RAND_98;
|
|
reg [31:0] _RAND_99;
|
|
reg [31:0] _RAND_100;
|
|
reg [31:0] _RAND_101;
|
|
reg [31:0] _RAND_102;
|
|
reg [31:0] _RAND_103;
|
|
reg [31:0] _RAND_104;
|
|
reg [31:0] _RAND_105;
|
|
reg [31:0] _RAND_106;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[el2_lsu_bus_buffer.scala 127:46]
|
|
wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[el2_lsu_bus_buffer.scala 128:46]
|
|
reg [31:0] buf_addr_0; // @[el2_lib.scala 514:16]
|
|
wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 130:74]
|
|
reg _T_4360; // @[Reg.scala 27:20]
|
|
reg _T_4357; // @[Reg.scala 27:20]
|
|
reg _T_4354; // @[Reg.scala 27:20]
|
|
reg _T_4351; // @[Reg.scala 27:20]
|
|
wire [3:0] buf_write = {_T_4360,_T_4357,_T_4354,_T_4351}; // @[Cat.scala 29:58]
|
|
wire _T_4 = _T_2 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 130:98]
|
|
reg [2:0] buf_state_0; // @[Reg.scala 27:20]
|
|
wire _T_5 = buf_state_0 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129]
|
|
wire _T_6 = _T_4 & _T_5; // @[el2_lsu_bus_buffer.scala 130:113]
|
|
wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141]
|
|
reg [31:0] buf_addr_1; // @[el2_lib.scala 514:16]
|
|
wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 130:74]
|
|
wire _T_11 = _T_9 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 130:98]
|
|
reg [2:0] buf_state_1; // @[Reg.scala 27:20]
|
|
wire _T_12 = buf_state_1 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129]
|
|
wire _T_13 = _T_11 & _T_12; // @[el2_lsu_bus_buffer.scala 130:113]
|
|
wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141]
|
|
reg [31:0] buf_addr_2; // @[el2_lib.scala 514:16]
|
|
wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 130:74]
|
|
wire _T_18 = _T_16 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 130:98]
|
|
reg [2:0] buf_state_2; // @[Reg.scala 27:20]
|
|
wire _T_19 = buf_state_2 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129]
|
|
wire _T_20 = _T_18 & _T_19; // @[el2_lsu_bus_buffer.scala 130:113]
|
|
wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141]
|
|
reg [31:0] buf_addr_3; // @[el2_lib.scala 514:16]
|
|
wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 130:74]
|
|
wire _T_25 = _T_23 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 130:98]
|
|
reg [2:0] buf_state_3; // @[Reg.scala 27:20]
|
|
wire _T_26 = buf_state_3 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129]
|
|
wire _T_27 = _T_25 & _T_26; // @[el2_lsu_bus_buffer.scala 130:113]
|
|
wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141]
|
|
wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 131:74]
|
|
wire _T_32 = _T_30 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 131:98]
|
|
wire _T_34 = _T_32 & _T_5; // @[el2_lsu_bus_buffer.scala 131:113]
|
|
wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141]
|
|
wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 131:74]
|
|
wire _T_39 = _T_37 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 131:98]
|
|
wire _T_41 = _T_39 & _T_12; // @[el2_lsu_bus_buffer.scala 131:113]
|
|
wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141]
|
|
wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 131:74]
|
|
wire _T_46 = _T_44 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 131:98]
|
|
wire _T_48 = _T_46 & _T_19; // @[el2_lsu_bus_buffer.scala 131:113]
|
|
wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141]
|
|
wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 131:74]
|
|
wire _T_53 = _T_51 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 131:98]
|
|
wire _T_55 = _T_53 & _T_26; // @[el2_lsu_bus_buffer.scala 131:113]
|
|
wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141]
|
|
reg [3:0] buf_byteen_3; // @[Reg.scala 27:20]
|
|
wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
reg [3:0] buf_byteen_2; // @[Reg.scala 27:20]
|
|
wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
reg [3:0] buf_byteen_1; // @[Reg.scala 27:20]
|
|
wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
reg [3:0] buf_byteen_0; // @[Reg.scala 27:20]
|
|
wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58]
|
|
reg [3:0] buf_ageQ_3; // @[el2_lsu_bus_buffer.scala 554:60]
|
|
wire _T_2621 = buf_state_3 == 3'h2; // @[el2_lsu_bus_buffer.scala 466:93]
|
|
wire _T_4107 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire _T_4130 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire _T_4134 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30]
|
|
reg [1:0] _T_1848; // @[Reg.scala 27:20]
|
|
wire [2:0] obuf_tag0 = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 406:13]
|
|
wire _T_4141 = obuf_tag0 == 3'h3; // @[el2_lsu_bus_buffer.scala 509:48]
|
|
reg obuf_merge; // @[Reg.scala 27:20]
|
|
reg [1:0] obuf_tag1; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_358 = {{1'd0}, obuf_tag1}; // @[el2_lsu_bus_buffer.scala 509:104]
|
|
wire _T_4142 = _GEN_358 == 3'h3; // @[el2_lsu_bus_buffer.scala 509:104]
|
|
wire _T_4143 = obuf_merge & _T_4142; // @[el2_lsu_bus_buffer.scala 509:91]
|
|
wire _T_4144 = _T_4141 | _T_4143; // @[el2_lsu_bus_buffer.scala 509:77]
|
|
reg obuf_valid; // @[el2_lsu_bus_buffer.scala 400:54]
|
|
wire _T_4145 = _T_4144 & obuf_valid; // @[el2_lsu_bus_buffer.scala 509:135]
|
|
reg obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 399:55]
|
|
wire _T_4146 = _T_4145 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 509:148]
|
|
wire _GEN_280 = _T_4134 & _T_4146; // @[Conditional.scala 39:67]
|
|
wire _GEN_293 = _T_4130 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67]
|
|
wire buf_cmd_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_293; // @[Conditional.scala 40:58]
|
|
wire _T_2622 = _T_2621 & buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 466:103]
|
|
wire _T_2623 = ~_T_2622; // @[el2_lsu_bus_buffer.scala 466:78]
|
|
wire _T_2624 = buf_ageQ_3[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2616 = buf_state_2 == 3'h2; // @[el2_lsu_bus_buffer.scala 466:93]
|
|
wire _T_3914 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _T_3937 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _T_3941 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _T_3948 = obuf_tag0 == 3'h2; // @[el2_lsu_bus_buffer.scala 509:48]
|
|
wire _T_3949 = _GEN_358 == 3'h2; // @[el2_lsu_bus_buffer.scala 509:104]
|
|
wire _T_3950 = obuf_merge & _T_3949; // @[el2_lsu_bus_buffer.scala 509:91]
|
|
wire _T_3951 = _T_3948 | _T_3950; // @[el2_lsu_bus_buffer.scala 509:77]
|
|
wire _T_3952 = _T_3951 & obuf_valid; // @[el2_lsu_bus_buffer.scala 509:135]
|
|
wire _T_3953 = _T_3952 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 509:148]
|
|
wire _GEN_204 = _T_3941 & _T_3953; // @[Conditional.scala 39:67]
|
|
wire _GEN_217 = _T_3937 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67]
|
|
wire buf_cmd_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_217; // @[Conditional.scala 40:58]
|
|
wire _T_2617 = _T_2616 & buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 466:103]
|
|
wire _T_2618 = ~_T_2617; // @[el2_lsu_bus_buffer.scala 466:78]
|
|
wire _T_2619 = buf_ageQ_3[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2611 = buf_state_1 == 3'h2; // @[el2_lsu_bus_buffer.scala 466:93]
|
|
wire _T_3721 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _T_3744 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _T_3748 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _T_3755 = obuf_tag0 == 3'h1; // @[el2_lsu_bus_buffer.scala 509:48]
|
|
wire _T_3756 = _GEN_358 == 3'h1; // @[el2_lsu_bus_buffer.scala 509:104]
|
|
wire _T_3757 = obuf_merge & _T_3756; // @[el2_lsu_bus_buffer.scala 509:91]
|
|
wire _T_3758 = _T_3755 | _T_3757; // @[el2_lsu_bus_buffer.scala 509:77]
|
|
wire _T_3759 = _T_3758 & obuf_valid; // @[el2_lsu_bus_buffer.scala 509:135]
|
|
wire _T_3760 = _T_3759 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 509:148]
|
|
wire _GEN_128 = _T_3748 & _T_3760; // @[Conditional.scala 39:67]
|
|
wire _GEN_141 = _T_3744 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67]
|
|
wire buf_cmd_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_141; // @[Conditional.scala 40:58]
|
|
wire _T_2612 = _T_2611 & buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 466:103]
|
|
wire _T_2613 = ~_T_2612; // @[el2_lsu_bus_buffer.scala 466:78]
|
|
wire _T_2614 = buf_ageQ_3[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2606 = buf_state_0 == 3'h2; // @[el2_lsu_bus_buffer.scala 466:93]
|
|
wire _T_3528 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire _T_3551 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire _T_3555 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire _T_3562 = obuf_tag0 == 3'h0; // @[el2_lsu_bus_buffer.scala 509:48]
|
|
wire _T_3563 = _GEN_358 == 3'h0; // @[el2_lsu_bus_buffer.scala 509:104]
|
|
wire _T_3564 = obuf_merge & _T_3563; // @[el2_lsu_bus_buffer.scala 509:91]
|
|
wire _T_3565 = _T_3562 | _T_3564; // @[el2_lsu_bus_buffer.scala 509:77]
|
|
wire _T_3566 = _T_3565 & obuf_valid; // @[el2_lsu_bus_buffer.scala 509:135]
|
|
wire _T_3567 = _T_3566 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 509:148]
|
|
wire _GEN_52 = _T_3555 & _T_3567; // @[Conditional.scala 39:67]
|
|
wire _GEN_65 = _T_3551 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67]
|
|
wire buf_cmd_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_65; // @[Conditional.scala 40:58]
|
|
wire _T_2607 = _T_2606 & buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 466:103]
|
|
wire _T_2608 = ~_T_2607; // @[el2_lsu_bus_buffer.scala 466:78]
|
|
wire _T_2609 = buf_ageQ_3[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire [3:0] buf_age_3 = {_T_2624,_T_2619,_T_2614,_T_2609}; // @[Cat.scala 29:58]
|
|
wire _T_2723 = ~buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2725 = _T_2723 & _T_19; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire _T_2717 = ~buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2719 = _T_2717 & _T_12; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire _T_2711 = ~buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2713 = _T_2711 & _T_5; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire [3:0] buf_age_younger_3 = {1'h0,_T_2725,_T_2719,_T_2713}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_256 = |_T_255; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_257 = ~_T_256; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
reg [31:0] ibuf_addr; // @[el2_lib.scala 514:16]
|
|
wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 206:51]
|
|
reg ibuf_write; // @[Reg.scala 27:20]
|
|
wire _T_513 = _T_512 & ibuf_write; // @[el2_lsu_bus_buffer.scala 206:73]
|
|
reg ibuf_valid; // @[el2_lsu_bus_buffer.scala 293:54]
|
|
wire _T_514 = _T_513 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 206:86]
|
|
wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 206:99]
|
|
wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
reg [3:0] ibuf_byteen; // @[Reg.scala 27:20]
|
|
wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 211:55]
|
|
wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[el2_lsu_bus_buffer.scala 211:69]
|
|
wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 200:150]
|
|
wire _T_261 = _T_258 & _T_260; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
reg [3:0] buf_ageQ_2; // @[el2_lsu_bus_buffer.scala 554:60]
|
|
wire _T_2601 = buf_ageQ_2[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2596 = buf_ageQ_2[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2591 = buf_ageQ_2[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2586 = buf_ageQ_2[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire [3:0] buf_age_2 = {_T_2601,_T_2596,_T_2591,_T_2586}; // @[Cat.scala 29:58]
|
|
wire _T_2702 = ~buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2704 = _T_2702 & _T_26; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire _T_2690 = ~buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2692 = _T_2690 & _T_12; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire _T_2684 = ~buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2686 = _T_2684 & _T_5; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire [3:0] buf_age_younger_2 = {_T_2704,1'h0,_T_2692,_T_2686}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_248 = |_T_247; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_249 = ~_T_248; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_253 = _T_250 & _T_260; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
reg [3:0] buf_ageQ_1; // @[el2_lsu_bus_buffer.scala 554:60]
|
|
wire _T_2578 = buf_ageQ_1[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2573 = buf_ageQ_1[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2568 = buf_ageQ_1[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2563 = buf_ageQ_1[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire [3:0] buf_age_1 = {_T_2578,_T_2573,_T_2568,_T_2563}; // @[Cat.scala 29:58]
|
|
wire _T_2675 = ~buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2677 = _T_2675 & _T_26; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire _T_2669 = ~buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2671 = _T_2669 & _T_19; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire _T_2657 = ~buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2659 = _T_2657 & _T_5; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire [3:0] buf_age_younger_1 = {_T_2677,_T_2671,1'h0,_T_2659}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_240 = |_T_239; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_241 = ~_T_240; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_245 = _T_242 & _T_260; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
reg [3:0] buf_ageQ_0; // @[el2_lsu_bus_buffer.scala 554:60]
|
|
wire _T_2555 = buf_ageQ_0[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2550 = buf_ageQ_0[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2545 = buf_ageQ_0[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire _T_2540 = buf_ageQ_0[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 466:76]
|
|
wire [3:0] buf_age_0 = {_T_2555,_T_2550,_T_2545,_T_2540}; // @[Cat.scala 29:58]
|
|
wire _T_2648 = ~buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2650 = _T_2648 & _T_26; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire _T_2642 = ~buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2644 = _T_2642 & _T_19; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire _T_2636 = ~buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 467:89]
|
|
wire _T_2638 = _T_2636 & _T_12; // @[el2_lsu_bus_buffer.scala 467:104]
|
|
wire [3:0] buf_age_younger_0 = {_T_2650,_T_2644,_T_2638,1'h0}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_232 = |_T_231; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_233 = ~_T_232; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_237 = _T_234 & _T_260; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58]
|
|
wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[el2_lsu_bus_buffer.scala 192:73]
|
|
wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 192:77]
|
|
wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_291 = |_T_290; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_292 = ~_T_291; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 200:150]
|
|
wire _T_296 = _T_293 & _T_295; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_283 = |_T_282; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_284 = ~_T_283; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_288 = _T_285 & _T_295; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_275 = |_T_274; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_276 = ~_T_275; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_280 = _T_277 & _T_295; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_267 = |_T_266; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_268 = ~_T_267; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_272 = _T_269 & _T_295; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58]
|
|
wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[el2_lsu_bus_buffer.scala 192:73]
|
|
wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 192:77]
|
|
wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_326 = |_T_325; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_327 = ~_T_326; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 200:150]
|
|
wire _T_331 = _T_328 & _T_330; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_318 = |_T_317; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_319 = ~_T_318; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_323 = _T_320 & _T_330; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_310 = |_T_309; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_311 = ~_T_310; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_315 = _T_312 & _T_330; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_302 = |_T_301; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_303 = ~_T_302; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_307 = _T_304 & _T_330; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58]
|
|
wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[el2_lsu_bus_buffer.scala 192:73]
|
|
wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 192:77]
|
|
wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 195:95]
|
|
wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 195:114]
|
|
wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_361 = |_T_360; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_362 = ~_T_361; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 200:150]
|
|
wire _T_366 = _T_363 & _T_365; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_353 = |_T_352; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_354 = ~_T_353; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_358 = _T_355 & _T_365; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_345 = |_T_344; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_346 = ~_T_345; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_350 = _T_347 & _T_365; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122]
|
|
wire _T_337 = |_T_336; // @[el2_lsu_bus_buffer.scala 200:144]
|
|
wire _T_338 = ~_T_337; // @[el2_lsu_bus_buffer.scala 200:99]
|
|
wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[el2_lsu_bus_buffer.scala 200:97]
|
|
wire _T_342 = _T_339 & _T_365; // @[el2_lsu_bus_buffer.scala 200:148]
|
|
wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58]
|
|
wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[el2_lsu_bus_buffer.scala 192:73]
|
|
wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 192:77]
|
|
wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58]
|
|
wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_396 = |_T_395; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_397 = ~_T_396; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 207:51]
|
|
wire _T_518 = _T_517 & ibuf_write; // @[el2_lsu_bus_buffer.scala 207:73]
|
|
wire _T_519 = _T_518 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 207:86]
|
|
wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 207:99]
|
|
wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 212:55]
|
|
wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[el2_lsu_bus_buffer.scala 212:69]
|
|
wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 201:150]
|
|
wire _T_401 = _T_398 & _T_400; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_388 = |_T_387; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_389 = ~_T_388; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_393 = _T_390 & _T_400; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_380 = |_T_379; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_381 = ~_T_380; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_385 = _T_382 & _T_400; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_372 = |_T_371; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_373 = ~_T_372; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_377 = _T_374 & _T_400; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58]
|
|
wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[el2_lsu_bus_buffer.scala 193:73]
|
|
wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 193:77]
|
|
wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_431 = |_T_430; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_432 = ~_T_431; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 201:150]
|
|
wire _T_436 = _T_433 & _T_435; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_423 = |_T_422; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_424 = ~_T_423; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_428 = _T_425 & _T_435; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_415 = |_T_414; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_416 = ~_T_415; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_420 = _T_417 & _T_435; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_407 = |_T_406; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_408 = ~_T_407; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_412 = _T_409 & _T_435; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58]
|
|
wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[el2_lsu_bus_buffer.scala 193:73]
|
|
wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 193:77]
|
|
wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_466 = |_T_465; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_467 = ~_T_466; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 201:150]
|
|
wire _T_471 = _T_468 & _T_470; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_458 = |_T_457; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_459 = ~_T_458; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_463 = _T_460 & _T_470; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_450 = |_T_449; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_451 = ~_T_450; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_455 = _T_452 & _T_470; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_442 = |_T_441; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_443 = ~_T_442; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_447 = _T_444 & _T_470; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58]
|
|
wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[el2_lsu_bus_buffer.scala 193:73]
|
|
wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 193:77]
|
|
wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 196:95]
|
|
wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 196:114]
|
|
wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_501 = |_T_500; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_502 = ~_T_501; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 201:150]
|
|
wire _T_506 = _T_503 & _T_505; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_493 = |_T_492; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_494 = ~_T_493; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_498 = _T_495 & _T_505; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_485 = |_T_484; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_486 = ~_T_485; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_490 = _T_487 & _T_505; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 201:122]
|
|
wire _T_477 = |_T_476; // @[el2_lsu_bus_buffer.scala 201:144]
|
|
wire _T_478 = ~_T_477; // @[el2_lsu_bus_buffer.scala 201:99]
|
|
wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[el2_lsu_bus_buffer.scala 201:97]
|
|
wire _T_482 = _T_479 & _T_505; // @[el2_lsu_bus_buffer.scala 201:148]
|
|
wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58]
|
|
wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[el2_lsu_bus_buffer.scala 193:73]
|
|
wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 193:77]
|
|
wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_536 = ld_byte_ibuf_hit_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_539 = ld_byte_ibuf_hit_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] ld_fwddata_buf_lo_initial = {_T_539,_T_536,_T_533,_T_530}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_544 = ld_byte_ibuf_hit_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_547 = ld_byte_ibuf_hit_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_550 = ld_byte_ibuf_hit_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
reg [31:0] buf_data_0; // @[el2_lib.scala 514:16]
|
|
wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 219:91]
|
|
wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
reg [31:0] buf_data_1; // @[el2_lib.scala 514:16]
|
|
wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 219:91]
|
|
wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
reg [31:0] buf_data_2; // @[el2_lib.scala 514:16]
|
|
wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 219:91]
|
|
wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
reg [31:0] buf_data_3; // @[el2_lib.scala 514:16]
|
|
wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 219:91]
|
|
wire [7:0] _T_576 = _T_560 | _T_565; // @[el2_lsu_bus_buffer.scala 219:123]
|
|
wire [7:0] _T_577 = _T_576 | _T_570; // @[el2_lsu_bus_buffer.scala 219:123]
|
|
wire [7:0] _T_578 = _T_577 | _T_575; // @[el2_lsu_bus_buffer.scala 219:123]
|
|
wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 220:65]
|
|
wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 220:65]
|
|
wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 220:65]
|
|
wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 220:65]
|
|
wire [7:0] _T_599 = _T_583 | _T_588; // @[el2_lsu_bus_buffer.scala 220:97]
|
|
wire [7:0] _T_600 = _T_599 | _T_593; // @[el2_lsu_bus_buffer.scala 220:97]
|
|
wire [7:0] _T_601 = _T_600 | _T_598; // @[el2_lsu_bus_buffer.scala 220:97]
|
|
wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 221:65]
|
|
wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 221:65]
|
|
wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 221:65]
|
|
wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 221:65]
|
|
wire [7:0] _T_622 = _T_606 | _T_611; // @[el2_lsu_bus_buffer.scala 221:97]
|
|
wire [7:0] _T_623 = _T_622 | _T_616; // @[el2_lsu_bus_buffer.scala 221:97]
|
|
wire [7:0] _T_624 = _T_623 | _T_621; // @[el2_lsu_bus_buffer.scala 221:97]
|
|
wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 222:65]
|
|
wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 222:65]
|
|
wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 222:65]
|
|
wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 222:65]
|
|
wire [7:0] _T_645 = _T_629 | _T_634; // @[el2_lsu_bus_buffer.scala 222:97]
|
|
wire [7:0] _T_646 = _T_645 | _T_639; // @[el2_lsu_bus_buffer.scala 222:97]
|
|
wire [7:0] _T_647 = _T_646 | _T_644; // @[el2_lsu_bus_buffer.scala 222:97]
|
|
wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58]
|
|
reg [31:0] ibuf_data; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 223:32]
|
|
wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 225:91]
|
|
wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 225:91]
|
|
wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 225:91]
|
|
wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 225:91]
|
|
wire [7:0] _T_673 = _T_657 | _T_662; // @[el2_lsu_bus_buffer.scala 225:123]
|
|
wire [7:0] _T_674 = _T_673 | _T_667; // @[el2_lsu_bus_buffer.scala 225:123]
|
|
wire [7:0] _T_675 = _T_674 | _T_672; // @[el2_lsu_bus_buffer.scala 225:123]
|
|
wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 226:65]
|
|
wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 226:65]
|
|
wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 226:65]
|
|
wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 226:65]
|
|
wire [7:0] _T_696 = _T_680 | _T_685; // @[el2_lsu_bus_buffer.scala 226:97]
|
|
wire [7:0] _T_697 = _T_696 | _T_690; // @[el2_lsu_bus_buffer.scala 226:97]
|
|
wire [7:0] _T_698 = _T_697 | _T_695; // @[el2_lsu_bus_buffer.scala 226:97]
|
|
wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 227:65]
|
|
wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 227:65]
|
|
wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 227:65]
|
|
wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 227:65]
|
|
wire [7:0] _T_719 = _T_703 | _T_708; // @[el2_lsu_bus_buffer.scala 227:97]
|
|
wire [7:0] _T_720 = _T_719 | _T_713; // @[el2_lsu_bus_buffer.scala 227:97]
|
|
wire [7:0] _T_721 = _T_720 | _T_718; // @[el2_lsu_bus_buffer.scala 227:97]
|
|
wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 228:65]
|
|
wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 228:65]
|
|
wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 228:65]
|
|
wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 228:65]
|
|
wire [7:0] _T_742 = _T_726 | _T_731; // @[el2_lsu_bus_buffer.scala 228:97]
|
|
wire [7:0] _T_743 = _T_742 | _T_736; // @[el2_lsu_bus_buffer.scala 228:97]
|
|
wire [7:0] _T_744 = _T_743 | _T_741; // @[el2_lsu_bus_buffer.scala 228:97]
|
|
wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 229:32]
|
|
wire [3:0] _T_750 = io_lsu_pkt_r_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_751 = io_lsu_pkt_r_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_752 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72]
|
|
wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72]
|
|
wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[el2_lsu_bus_buffer.scala 236:55]
|
|
wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[el2_lsu_bus_buffer.scala 237:24]
|
|
wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58]
|
|
wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[el2_lsu_bus_buffer.scala 238:24]
|
|
wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58]
|
|
wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[el2_lsu_bus_buffer.scala 239:24]
|
|
wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_772 = _T_766 ? _T_768 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_774 = _T_770 | _T_771; // @[Mux.scala 27:72]
|
|
wire [3:0] ldst_byteen_hi_r = _T_774 | _T_772; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_781 = {ldst_byteen_r[2:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_785 = {ldst_byteen_r[1:0],2'h0}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_789 = {ldst_byteen_r[0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_790 = _T_756 ? ldst_byteen_r : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_791 = _T_758 ? _T_781 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_792 = _T_762 ? _T_785 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_793 = _T_766 ? _T_789 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_794 = _T_790 | _T_791; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_795 = _T_794 | _T_792; // @[Mux.scala 27:72]
|
|
wire [3:0] ldst_byteen_lo_r = _T_795 | _T_793; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_802 = {24'h0,io_store_data_r[31:24]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_806 = {16'h0,io_store_data_r[31:16]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_810 = {8'h0,io_store_data_r[31:8]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_812 = _T_758 ? _T_802 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_813 = _T_762 ? _T_806 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_814 = _T_766 ? _T_810 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_816 = _T_812 | _T_813; // @[Mux.scala 27:72]
|
|
wire [31:0] store_data_hi_r = _T_816 | _T_814; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_823 = {io_store_data_r[23:0],8'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_827 = {io_store_data_r[15:0],16'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_831 = {io_store_data_r[7:0],24'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_832 = _T_756 ? io_store_data_r : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_833 = _T_758 ? _T_823 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_834 = _T_762 ? _T_827 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_835 = _T_766 ? _T_831 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72]
|
|
wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72]
|
|
wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[el2_lsu_bus_buffer.scala 256:40]
|
|
wire _T_844 = ~io_lsu_addr_r[0]; // @[el2_lsu_bus_buffer.scala 258:31]
|
|
wire _T_845 = io_lsu_pkt_r_bits_word & _T_756; // @[Mux.scala 27:72]
|
|
wire _T_846 = io_lsu_pkt_r_bits_half & _T_844; // @[Mux.scala 27:72]
|
|
wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72]
|
|
wire is_aligned_r = _T_848 | io_lsu_pkt_r_bits_by; // @[Mux.scala 27:72]
|
|
wire _T_850 = io_lsu_pkt_r_bits_load | io_no_word_merge_r; // @[el2_lsu_bus_buffer.scala 260:60]
|
|
wire _T_851 = io_lsu_busreq_r & _T_850; // @[el2_lsu_bus_buffer.scala 260:34]
|
|
wire _T_852 = ~ibuf_valid; // @[el2_lsu_bus_buffer.scala 260:84]
|
|
wire ibuf_byp = _T_851 & _T_852; // @[el2_lsu_bus_buffer.scala 260:82]
|
|
wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 261:36]
|
|
wire _T_854 = ~ibuf_byp; // @[el2_lsu_bus_buffer.scala 261:56]
|
|
wire ibuf_wr_en = _T_853 & _T_854; // @[el2_lsu_bus_buffer.scala 261:54]
|
|
wire _T_855 = ~ibuf_wr_en; // @[el2_lsu_bus_buffer.scala 263:36]
|
|
reg [2:0] ibuf_timer; // @[el2_lsu_bus_buffer.scala 306:55]
|
|
wire _T_864 = ibuf_timer == 3'h7; // @[el2_lsu_bus_buffer.scala 269:62]
|
|
wire _T_865 = ibuf_wr_en | _T_864; // @[el2_lsu_bus_buffer.scala 269:48]
|
|
wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 288:54]
|
|
wire _T_930 = _T_929 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 288:80]
|
|
wire _T_931 = _T_930 & ibuf_write; // @[el2_lsu_bus_buffer.scala 288:93]
|
|
wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 288:129]
|
|
wire _T_935 = _T_931 & _T_934; // @[el2_lsu_bus_buffer.scala 288:106]
|
|
wire _T_936 = ~io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 288:152]
|
|
wire _T_937 = _T_935 & _T_936; // @[el2_lsu_bus_buffer.scala 288:150]
|
|
wire _T_938 = ~io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 288:175]
|
|
wire ibuf_merge_en = _T_937 & _T_938; // @[el2_lsu_bus_buffer.scala 288:173]
|
|
wire ibuf_merge_in = ~io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 289:20]
|
|
wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 269:98]
|
|
wire _T_867 = ~_T_866; // @[el2_lsu_bus_buffer.scala 269:82]
|
|
wire _T_868 = _T_865 & _T_867; // @[el2_lsu_bus_buffer.scala 269:80]
|
|
wire _T_869 = _T_868 | ibuf_byp; // @[el2_lsu_bus_buffer.scala 270:5]
|
|
wire _T_857 = ~io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 264:44]
|
|
wire _T_858 = io_lsu_busreq_m & _T_857; // @[el2_lsu_bus_buffer.scala 264:42]
|
|
wire _T_859 = _T_858 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 264:61]
|
|
wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[el2_lsu_bus_buffer.scala 264:120]
|
|
wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[el2_lsu_bus_buffer.scala 264:100]
|
|
wire ibuf_force_drain = _T_859 & _T_863; // @[el2_lsu_bus_buffer.scala 264:74]
|
|
wire _T_870 = _T_869 | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 270:16]
|
|
reg ibuf_sideeffect; // @[Reg.scala 27:20]
|
|
wire _T_871 = _T_870 | ibuf_sideeffect; // @[el2_lsu_bus_buffer.scala 270:35]
|
|
wire _T_872 = ~ibuf_write; // @[el2_lsu_bus_buffer.scala 270:55]
|
|
wire _T_873 = _T_871 | _T_872; // @[el2_lsu_bus_buffer.scala 270:53]
|
|
wire _T_874 = _T_873 | io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 270:67]
|
|
wire ibuf_drain_vld = ibuf_valid & _T_874; // @[el2_lsu_bus_buffer.scala 269:32]
|
|
wire _T_856 = ibuf_drain_vld & _T_855; // @[el2_lsu_bus_buffer.scala 263:34]
|
|
wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 263:49]
|
|
reg [1:0] WrPtr1_r; // @[el2_lsu_bus_buffer.scala 670:49]
|
|
reg [1:0] WrPtr0_r; // @[el2_lsu_bus_buffer.scala 669:49]
|
|
reg [1:0] ibuf_tag; // @[Reg.scala 27:20]
|
|
wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 279:77]
|
|
wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 284:8]
|
|
wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[el2_lsu_bus_buffer.scala 285:8]
|
|
wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[el2_lsu_bus_buffer.scala 283:46]
|
|
wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 284:8]
|
|
wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[el2_lsu_bus_buffer.scala 285:8]
|
|
wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[el2_lsu_bus_buffer.scala 283:46]
|
|
wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 284:8]
|
|
wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[el2_lsu_bus_buffer.scala 285:8]
|
|
wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[el2_lsu_bus_buffer.scala 283:46]
|
|
wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 284:8]
|
|
wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[el2_lsu_bus_buffer.scala 285:8]
|
|
wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[el2_lsu_bus_buffer.scala 283:46]
|
|
wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58]
|
|
wire _T_923 = ibuf_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 286:59]
|
|
wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 286:93]
|
|
wire _T_941 = ~ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 290:65]
|
|
wire _T_942 = ibuf_merge_en & _T_941; // @[el2_lsu_bus_buffer.scala 290:63]
|
|
wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[el2_lsu_bus_buffer.scala 290:96]
|
|
wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[el2_lsu_bus_buffer.scala 290:48]
|
|
wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[el2_lsu_bus_buffer.scala 290:96]
|
|
wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[el2_lsu_bus_buffer.scala 290:48]
|
|
wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[el2_lsu_bus_buffer.scala 290:96]
|
|
wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[el2_lsu_bus_buffer.scala 290:48]
|
|
wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[el2_lsu_bus_buffer.scala 290:96]
|
|
wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 290:48]
|
|
wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 291:45]
|
|
wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 291:45]
|
|
wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 291:45]
|
|
wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 291:45]
|
|
wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58]
|
|
wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[el2_lsu_bus_buffer.scala 293:58]
|
|
wire _T_1006 = ~ibuf_rst; // @[el2_lsu_bus_buffer.scala 293:93]
|
|
reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20]
|
|
reg ibuf_dual; // @[Reg.scala 27:20]
|
|
reg ibuf_samedw; // @[Reg.scala 27:20]
|
|
reg ibuf_nomerge; // @[Reg.scala 27:20]
|
|
reg ibuf_unsign; // @[Reg.scala 27:20]
|
|
reg [1:0] ibuf_sz; // @[Reg.scala 27:20]
|
|
wire _T_4446 = buf_write[3] & _T_2621; // @[el2_lsu_bus_buffer.scala 576:64]
|
|
wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 576:91]
|
|
wire _T_4448 = _T_4446 & _T_4447; // @[el2_lsu_bus_buffer.scala 576:89]
|
|
wire _T_4441 = buf_write[2] & _T_2616; // @[el2_lsu_bus_buffer.scala 576:64]
|
|
wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 576:91]
|
|
wire _T_4443 = _T_4441 & _T_4442; // @[el2_lsu_bus_buffer.scala 576:89]
|
|
wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[el2_lsu_bus_buffer.scala 576:142]
|
|
wire _T_4436 = buf_write[1] & _T_2611; // @[el2_lsu_bus_buffer.scala 576:64]
|
|
wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 576:91]
|
|
wire _T_4438 = _T_4436 & _T_4437; // @[el2_lsu_bus_buffer.scala 576:89]
|
|
wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[el2_lsu_bus_buffer.scala 576:142]
|
|
wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[el2_lsu_bus_buffer.scala 576:142]
|
|
wire _T_4431 = buf_write[0] & _T_2606; // @[el2_lsu_bus_buffer.scala 576:64]
|
|
wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 576:91]
|
|
wire _T_4433 = _T_4431 & _T_4432; // @[el2_lsu_bus_buffer.scala 576:89]
|
|
wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[el2_lsu_bus_buffer.scala 576:142]
|
|
wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[el2_lsu_bus_buffer.scala 576:142]
|
|
wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 316:43]
|
|
wire _T_4463 = _T_2621 & _T_4447; // @[el2_lsu_bus_buffer.scala 577:73]
|
|
wire _T_4460 = _T_2616 & _T_4442; // @[el2_lsu_bus_buffer.scala 577:73]
|
|
wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[el2_lsu_bus_buffer.scala 577:126]
|
|
wire _T_4457 = _T_2611 & _T_4437; // @[el2_lsu_bus_buffer.scala 577:73]
|
|
wire [1:0] _GEN_364 = {{1'd0}, _T_4457}; // @[el2_lsu_bus_buffer.scala 577:126]
|
|
wire [2:0] _T_4465 = _T_4464 + _GEN_364; // @[el2_lsu_bus_buffer.scala 577:126]
|
|
wire _T_4454 = _T_2606 & _T_4432; // @[el2_lsu_bus_buffer.scala 577:73]
|
|
wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[el2_lsu_bus_buffer.scala 577:126]
|
|
wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[el2_lsu_bus_buffer.scala 577:126]
|
|
wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 316:72]
|
|
wire _T_1018 = _T_1016 & _T_1017; // @[el2_lsu_bus_buffer.scala 316:51]
|
|
reg [2:0] obuf_wr_timer; // @[el2_lsu_bus_buffer.scala 415:54]
|
|
wire _T_1019 = obuf_wr_timer != 3'h7; // @[el2_lsu_bus_buffer.scala 316:97]
|
|
wire _T_1020 = _T_1018 & _T_1019; // @[el2_lsu_bus_buffer.scala 316:80]
|
|
wire _T_1022 = _T_1020 & _T_938; // @[el2_lsu_bus_buffer.scala 316:114]
|
|
wire _T_1979 = |buf_age_3; // @[el2_lsu_bus_buffer.scala 432:58]
|
|
wire _T_1980 = ~_T_1979; // @[el2_lsu_bus_buffer.scala 432:45]
|
|
wire _T_1982 = _T_1980 & _T_2621; // @[el2_lsu_bus_buffer.scala 432:63]
|
|
wire _T_1984 = _T_1982 & _T_4447; // @[el2_lsu_bus_buffer.scala 432:88]
|
|
wire _T_1973 = |buf_age_2; // @[el2_lsu_bus_buffer.scala 432:58]
|
|
wire _T_1974 = ~_T_1973; // @[el2_lsu_bus_buffer.scala 432:45]
|
|
wire _T_1976 = _T_1974 & _T_2616; // @[el2_lsu_bus_buffer.scala 432:63]
|
|
wire _T_1978 = _T_1976 & _T_4442; // @[el2_lsu_bus_buffer.scala 432:88]
|
|
wire _T_1967 = |buf_age_1; // @[el2_lsu_bus_buffer.scala 432:58]
|
|
wire _T_1968 = ~_T_1967; // @[el2_lsu_bus_buffer.scala 432:45]
|
|
wire _T_1970 = _T_1968 & _T_2611; // @[el2_lsu_bus_buffer.scala 432:63]
|
|
wire _T_1972 = _T_1970 & _T_4437; // @[el2_lsu_bus_buffer.scala 432:88]
|
|
wire _T_1961 = |buf_age_0; // @[el2_lsu_bus_buffer.scala 432:58]
|
|
wire _T_1962 = ~_T_1961; // @[el2_lsu_bus_buffer.scala 432:45]
|
|
wire _T_1964 = _T_1962 & _T_2606; // @[el2_lsu_bus_buffer.scala 432:63]
|
|
wire _T_1966 = _T_1964 & _T_4432; // @[el2_lsu_bus_buffer.scala 432:88]
|
|
wire [3:0] CmdPtr0Dec = {_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_2054 = {4'h0,_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58]
|
|
wire _T_2057 = _T_2054[4] | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 440:42]
|
|
wire _T_2059 = _T_2057 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 440:48]
|
|
wire _T_2061 = _T_2059 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 440:54]
|
|
wire _T_2064 = _T_2054[2] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 440:67]
|
|
wire _T_2066 = _T_2064 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 440:73]
|
|
wire _T_2068 = _T_2066 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 440:79]
|
|
wire _T_2071 = _T_2054[1] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 440:92]
|
|
wire _T_2073 = _T_2071 | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 440:98]
|
|
wire _T_2075 = _T_2073 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 440:104]
|
|
wire [2:0] _T_2077 = {_T_2061,_T_2068,_T_2075}; // @[Cat.scala 29:58]
|
|
wire [1:0] CmdPtr0 = _T_2077[1:0]; // @[el2_lsu_bus_buffer.scala 445:11]
|
|
wire _T_1023 = CmdPtr0 == 2'h0; // @[el2_lsu_bus_buffer.scala 317:114]
|
|
wire _T_1024 = CmdPtr0 == 2'h1; // @[el2_lsu_bus_buffer.scala 317:114]
|
|
wire _T_1025 = CmdPtr0 == 2'h2; // @[el2_lsu_bus_buffer.scala 317:114]
|
|
wire _T_1026 = CmdPtr0 == 2'h3; // @[el2_lsu_bus_buffer.scala 317:114]
|
|
reg buf_nomerge_0; // @[Reg.scala 27:20]
|
|
wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72]
|
|
reg buf_nomerge_1; // @[Reg.scala 27:20]
|
|
wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72]
|
|
reg buf_nomerge_2; // @[Reg.scala 27:20]
|
|
wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72]
|
|
reg buf_nomerge_3; // @[Reg.scala 27:20]
|
|
wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72]
|
|
wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72]
|
|
wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72]
|
|
wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72]
|
|
wire _T_1035 = ~_T_1033; // @[el2_lsu_bus_buffer.scala 317:31]
|
|
wire _T_1036 = _T_1022 & _T_1035; // @[el2_lsu_bus_buffer.scala 317:29]
|
|
reg _T_4330; // @[Reg.scala 27:20]
|
|
reg _T_4327; // @[Reg.scala 27:20]
|
|
reg _T_4324; // @[Reg.scala 27:20]
|
|
reg _T_4321; // @[Reg.scala 27:20]
|
|
wire [3:0] buf_sideeffect = {_T_4330,_T_4327,_T_4324,_T_4321}; // @[Cat.scala 29:58]
|
|
wire _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72]
|
|
wire _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72]
|
|
wire _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72]
|
|
wire _T_1048 = _T_1026 & buf_sideeffect[3]; // @[Mux.scala 27:72]
|
|
wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72]
|
|
wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72]
|
|
wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72]
|
|
wire _T_1053 = ~_T_1051; // @[el2_lsu_bus_buffer.scala 318:5]
|
|
wire _T_1054 = _T_1036 & _T_1053; // @[el2_lsu_bus_buffer.scala 317:140]
|
|
wire _T_1065 = _T_858 & _T_852; // @[el2_lsu_bus_buffer.scala 320:58]
|
|
wire _T_1067 = _T_1065 & _T_1017; // @[el2_lsu_bus_buffer.scala 320:72]
|
|
wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1079 = _T_1025 ? buf_addr_2[31:2] : 30'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72]
|
|
wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[el2_lsu_bus_buffer.scala 320:123]
|
|
wire obuf_force_wr_en = _T_1067 & _T_1085; // @[el2_lsu_bus_buffer.scala 320:101]
|
|
wire _T_1055 = ~obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 318:119]
|
|
wire obuf_wr_wait = _T_1054 & _T_1055; // @[el2_lsu_bus_buffer.scala 318:117]
|
|
wire _T_1056 = |buf_numvld_cmd_any; // @[el2_lsu_bus_buffer.scala 319:75]
|
|
wire _T_1057 = obuf_wr_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 319:95]
|
|
wire _T_1058 = _T_1056 & _T_1057; // @[el2_lsu_bus_buffer.scala 319:79]
|
|
wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 319:123]
|
|
wire _T_4482 = buf_state_3 == 3'h1; // @[el2_lsu_bus_buffer.scala 578:63]
|
|
wire _T_4486 = _T_4482 | _T_4463; // @[el2_lsu_bus_buffer.scala 578:74]
|
|
wire _T_4477 = buf_state_2 == 3'h1; // @[el2_lsu_bus_buffer.scala 578:63]
|
|
wire _T_4481 = _T_4477 | _T_4460; // @[el2_lsu_bus_buffer.scala 578:74]
|
|
wire [1:0] _T_4487 = _T_4486 + _T_4481; // @[el2_lsu_bus_buffer.scala 578:154]
|
|
wire _T_4472 = buf_state_1 == 3'h1; // @[el2_lsu_bus_buffer.scala 578:63]
|
|
wire _T_4476 = _T_4472 | _T_4457; // @[el2_lsu_bus_buffer.scala 578:74]
|
|
wire [1:0] _GEN_366 = {{1'd0}, _T_4476}; // @[el2_lsu_bus_buffer.scala 578:154]
|
|
wire [2:0] _T_4488 = _T_4487 + _GEN_366; // @[el2_lsu_bus_buffer.scala 578:154]
|
|
wire _T_4467 = buf_state_0 == 3'h1; // @[el2_lsu_bus_buffer.scala 578:63]
|
|
wire _T_4471 = _T_4467 | _T_4454; // @[el2_lsu_bus_buffer.scala 578:74]
|
|
wire [2:0] _GEN_367 = {{2'd0}, _T_4471}; // @[el2_lsu_bus_buffer.scala 578:154]
|
|
wire [3:0] buf_numvld_pend_any = _T_4488 + _GEN_367; // @[el2_lsu_bus_buffer.scala 578:154]
|
|
wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[el2_lsu_bus_buffer.scala 322:53]
|
|
wire _T_1088 = ibuf_byp & _T_1087; // @[el2_lsu_bus_buffer.scala 322:31]
|
|
wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 322:64]
|
|
wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 322:89]
|
|
wire ibuf_buf_byp = _T_1088 & _T_1090; // @[el2_lsu_bus_buffer.scala 322:61]
|
|
wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 337:32]
|
|
wire _T_4778 = buf_state_0 == 3'h3; // @[el2_lsu_bus_buffer.scala 606:62]
|
|
wire _T_4780 = _T_4778 & buf_sideeffect[0]; // @[el2_lsu_bus_buffer.scala 606:73]
|
|
wire _T_4781 = _T_4780 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 606:93]
|
|
wire _T_4782 = buf_state_1 == 3'h3; // @[el2_lsu_bus_buffer.scala 606:62]
|
|
wire _T_4784 = _T_4782 & buf_sideeffect[1]; // @[el2_lsu_bus_buffer.scala 606:73]
|
|
wire _T_4785 = _T_4784 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 606:93]
|
|
wire _T_4794 = _T_4781 | _T_4785; // @[el2_lsu_bus_buffer.scala 606:141]
|
|
wire _T_4786 = buf_state_2 == 3'h3; // @[el2_lsu_bus_buffer.scala 606:62]
|
|
wire _T_4788 = _T_4786 & buf_sideeffect[2]; // @[el2_lsu_bus_buffer.scala 606:73]
|
|
wire _T_4789 = _T_4788 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 606:93]
|
|
wire _T_4795 = _T_4794 | _T_4789; // @[el2_lsu_bus_buffer.scala 606:141]
|
|
wire _T_4790 = buf_state_3 == 3'h3; // @[el2_lsu_bus_buffer.scala 606:62]
|
|
wire _T_4792 = _T_4790 & buf_sideeffect[3]; // @[el2_lsu_bus_buffer.scala 606:73]
|
|
wire _T_4793 = _T_4792 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 606:93]
|
|
wire bus_sideeffect_pend = _T_4795 | _T_4793; // @[el2_lsu_bus_buffer.scala 606:141]
|
|
wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 337:74]
|
|
wire _T_1093 = ~_T_1092; // @[el2_lsu_bus_buffer.scala 337:52]
|
|
wire _T_1094 = _T_1091 & _T_1093; // @[el2_lsu_bus_buffer.scala 337:50]
|
|
wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1101 = _T_1025 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72]
|
|
wire _T_1107 = _T_1105 == 3'h2; // @[el2_lsu_bus_buffer.scala 338:36]
|
|
wire found_cmdptr0 = |CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 437:31]
|
|
wire _T_1108 = _T_1107 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 338:47]
|
|
wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58]
|
|
wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72]
|
|
wire _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72]
|
|
wire _T_1124 = _T_1120 | _T_1121; // @[Mux.scala 27:72]
|
|
wire _T_1122 = _T_1025 & _T_1111[2]; // @[Mux.scala 27:72]
|
|
wire _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72]
|
|
wire _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72]
|
|
wire _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72]
|
|
wire _T_1128 = ~_T_1126; // @[el2_lsu_bus_buffer.scala 339:23]
|
|
wire _T_1129 = _T_1108 & _T_1128; // @[el2_lsu_bus_buffer.scala 339:21]
|
|
wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 339:141]
|
|
wire _T_1147 = ~_T_1146; // @[el2_lsu_bus_buffer.scala 339:105]
|
|
wire _T_1148 = _T_1129 & _T_1147; // @[el2_lsu_bus_buffer.scala 339:103]
|
|
reg buf_dual_3; // @[Reg.scala 27:20]
|
|
reg buf_dual_2; // @[Reg.scala 27:20]
|
|
reg buf_dual_1; // @[Reg.scala 27:20]
|
|
reg buf_dual_0; // @[Reg.scala 27:20]
|
|
wire [3:0] _T_1151 = {buf_dual_3,buf_dual_2,buf_dual_1,buf_dual_0}; // @[Cat.scala 29:58]
|
|
wire _T_1160 = _T_1023 & _T_1151[0]; // @[Mux.scala 27:72]
|
|
wire _T_1161 = _T_1024 & _T_1151[1]; // @[Mux.scala 27:72]
|
|
wire _T_1164 = _T_1160 | _T_1161; // @[Mux.scala 27:72]
|
|
wire _T_1162 = _T_1025 & _T_1151[2]; // @[Mux.scala 27:72]
|
|
wire _T_1165 = _T_1164 | _T_1162; // @[Mux.scala 27:72]
|
|
wire _T_1163 = _T_1026 & _T_1151[3]; // @[Mux.scala 27:72]
|
|
wire _T_1166 = _T_1165 | _T_1163; // @[Mux.scala 27:72]
|
|
reg buf_samedw_3; // @[Reg.scala 27:20]
|
|
reg buf_samedw_2; // @[Reg.scala 27:20]
|
|
reg buf_samedw_1; // @[Reg.scala 27:20]
|
|
reg buf_samedw_0; // @[Reg.scala 27:20]
|
|
wire [3:0] _T_1170 = {buf_samedw_3,buf_samedw_2,buf_samedw_1,buf_samedw_0}; // @[Cat.scala 29:58]
|
|
wire _T_1179 = _T_1023 & _T_1170[0]; // @[Mux.scala 27:72]
|
|
wire _T_1180 = _T_1024 & _T_1170[1]; // @[Mux.scala 27:72]
|
|
wire _T_1183 = _T_1179 | _T_1180; // @[Mux.scala 27:72]
|
|
wire _T_1181 = _T_1025 & _T_1170[2]; // @[Mux.scala 27:72]
|
|
wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72]
|
|
wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72]
|
|
wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72]
|
|
wire _T_1187 = _T_1166 & _T_1185; // @[el2_lsu_bus_buffer.scala 340:77]
|
|
wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72]
|
|
wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72]
|
|
wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72]
|
|
wire _T_1198 = _T_1025 & buf_write[2]; // @[Mux.scala 27:72]
|
|
wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72]
|
|
wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72]
|
|
wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72]
|
|
wire _T_1204 = ~_T_1202; // @[el2_lsu_bus_buffer.scala 340:150]
|
|
wire _T_1205 = _T_1187 & _T_1204; // @[el2_lsu_bus_buffer.scala 340:148]
|
|
wire _T_1206 = ~_T_1205; // @[el2_lsu_bus_buffer.scala 340:8]
|
|
wire [3:0] _T_2020 = ~CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 433:62]
|
|
wire [3:0] _T_2021 = buf_age_3 & _T_2020; // @[el2_lsu_bus_buffer.scala 433:59]
|
|
wire _T_2022 = |_T_2021; // @[el2_lsu_bus_buffer.scala 433:76]
|
|
wire _T_2023 = ~_T_2022; // @[el2_lsu_bus_buffer.scala 433:45]
|
|
wire _T_2025 = ~CmdPtr0Dec[3]; // @[el2_lsu_bus_buffer.scala 433:83]
|
|
wire _T_2026 = _T_2023 & _T_2025; // @[el2_lsu_bus_buffer.scala 433:81]
|
|
wire _T_2028 = _T_2026 & _T_2621; // @[el2_lsu_bus_buffer.scala 433:98]
|
|
wire _T_2030 = _T_2028 & _T_4447; // @[el2_lsu_bus_buffer.scala 433:123]
|
|
wire [3:0] _T_2010 = buf_age_2 & _T_2020; // @[el2_lsu_bus_buffer.scala 433:59]
|
|
wire _T_2011 = |_T_2010; // @[el2_lsu_bus_buffer.scala 433:76]
|
|
wire _T_2012 = ~_T_2011; // @[el2_lsu_bus_buffer.scala 433:45]
|
|
wire _T_2014 = ~CmdPtr0Dec[2]; // @[el2_lsu_bus_buffer.scala 433:83]
|
|
wire _T_2015 = _T_2012 & _T_2014; // @[el2_lsu_bus_buffer.scala 433:81]
|
|
wire _T_2017 = _T_2015 & _T_2616; // @[el2_lsu_bus_buffer.scala 433:98]
|
|
wire _T_2019 = _T_2017 & _T_4442; // @[el2_lsu_bus_buffer.scala 433:123]
|
|
wire [3:0] _T_1999 = buf_age_1 & _T_2020; // @[el2_lsu_bus_buffer.scala 433:59]
|
|
wire _T_2000 = |_T_1999; // @[el2_lsu_bus_buffer.scala 433:76]
|
|
wire _T_2001 = ~_T_2000; // @[el2_lsu_bus_buffer.scala 433:45]
|
|
wire _T_2003 = ~CmdPtr0Dec[1]; // @[el2_lsu_bus_buffer.scala 433:83]
|
|
wire _T_2004 = _T_2001 & _T_2003; // @[el2_lsu_bus_buffer.scala 433:81]
|
|
wire _T_2006 = _T_2004 & _T_2611; // @[el2_lsu_bus_buffer.scala 433:98]
|
|
wire _T_2008 = _T_2006 & _T_4437; // @[el2_lsu_bus_buffer.scala 433:123]
|
|
wire [3:0] _T_1988 = buf_age_0 & _T_2020; // @[el2_lsu_bus_buffer.scala 433:59]
|
|
wire _T_1989 = |_T_1988; // @[el2_lsu_bus_buffer.scala 433:76]
|
|
wire _T_1990 = ~_T_1989; // @[el2_lsu_bus_buffer.scala 433:45]
|
|
wire _T_1992 = ~CmdPtr0Dec[0]; // @[el2_lsu_bus_buffer.scala 433:83]
|
|
wire _T_1993 = _T_1990 & _T_1992; // @[el2_lsu_bus_buffer.scala 433:81]
|
|
wire _T_1995 = _T_1993 & _T_2606; // @[el2_lsu_bus_buffer.scala 433:98]
|
|
wire _T_1997 = _T_1995 & _T_4432; // @[el2_lsu_bus_buffer.scala 433:123]
|
|
wire [3:0] CmdPtr1Dec = {_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58]
|
|
wire found_cmdptr1 = |CmdPtr1Dec; // @[el2_lsu_bus_buffer.scala 438:31]
|
|
wire _T_1207 = _T_1206 | found_cmdptr1; // @[el2_lsu_bus_buffer.scala 340:181]
|
|
wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58]
|
|
wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72]
|
|
wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72]
|
|
wire _T_1223 = _T_1219 | _T_1220; // @[Mux.scala 27:72]
|
|
wire _T_1221 = _T_1025 & _T_1210[2]; // @[Mux.scala 27:72]
|
|
wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72]
|
|
wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72]
|
|
wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72]
|
|
wire _T_1227 = _T_1207 | _T_1225; // @[el2_lsu_bus_buffer.scala 340:197]
|
|
wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 340:269]
|
|
wire _T_1229 = _T_1148 & _T_1228; // @[el2_lsu_bus_buffer.scala 339:164]
|
|
wire _T_1230 = _T_1094 | _T_1229; // @[el2_lsu_bus_buffer.scala 337:98]
|
|
reg obuf_write; // @[Reg.scala 27:20]
|
|
reg obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 402:54]
|
|
reg obuf_data_done; // @[el2_lsu_bus_buffer.scala 403:55]
|
|
wire _T_4853 = obuf_cmd_done | obuf_data_done; // @[el2_lsu_bus_buffer.scala 610:54]
|
|
wire _T_4854 = obuf_cmd_done ? io_lsu_axi_wready : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 610:75]
|
|
wire _T_4856 = _T_4853 ? _T_4854 : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 610:39]
|
|
wire bus_cmd_ready = obuf_write ? _T_4856 : io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 610:23]
|
|
wire _T_1231 = ~obuf_valid; // @[el2_lsu_bus_buffer.scala 341:48]
|
|
wire _T_1232 = bus_cmd_ready | _T_1231; // @[el2_lsu_bus_buffer.scala 341:46]
|
|
reg obuf_nosend; // @[Reg.scala 27:20]
|
|
wire _T_1233 = _T_1232 | obuf_nosend; // @[el2_lsu_bus_buffer.scala 341:60]
|
|
wire _T_1234 = _T_1230 & _T_1233; // @[el2_lsu_bus_buffer.scala 341:29]
|
|
wire _T_1235 = ~obuf_wr_wait; // @[el2_lsu_bus_buffer.scala 341:77]
|
|
wire _T_1236 = _T_1234 & _T_1235; // @[el2_lsu_bus_buffer.scala 341:75]
|
|
reg [31:0] obuf_addr; // @[el2_lib.scala 514:16]
|
|
wire _T_4801 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[el2_lsu_bus_buffer.scala 608:56]
|
|
wire _T_4802 = obuf_valid & _T_4801; // @[el2_lsu_bus_buffer.scala 608:38]
|
|
wire _T_4804 = obuf_tag1 == 2'h0; // @[el2_lsu_bus_buffer.scala 608:126]
|
|
wire _T_4805 = obuf_merge & _T_4804; // @[el2_lsu_bus_buffer.scala 608:114]
|
|
wire _T_4806 = _T_3562 | _T_4805; // @[el2_lsu_bus_buffer.scala 608:100]
|
|
wire _T_4807 = ~_T_4806; // @[el2_lsu_bus_buffer.scala 608:80]
|
|
wire _T_4808 = _T_4802 & _T_4807; // @[el2_lsu_bus_buffer.scala 608:78]
|
|
wire _T_4845 = _T_4778 & _T_4808; // @[Mux.scala 27:72]
|
|
wire _T_4813 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[el2_lsu_bus_buffer.scala 608:56]
|
|
wire _T_4814 = obuf_valid & _T_4813; // @[el2_lsu_bus_buffer.scala 608:38]
|
|
wire _T_4816 = obuf_tag1 == 2'h1; // @[el2_lsu_bus_buffer.scala 608:126]
|
|
wire _T_4817 = obuf_merge & _T_4816; // @[el2_lsu_bus_buffer.scala 608:114]
|
|
wire _T_4818 = _T_3755 | _T_4817; // @[el2_lsu_bus_buffer.scala 608:100]
|
|
wire _T_4819 = ~_T_4818; // @[el2_lsu_bus_buffer.scala 608:80]
|
|
wire _T_4820 = _T_4814 & _T_4819; // @[el2_lsu_bus_buffer.scala 608:78]
|
|
wire _T_4846 = _T_4782 & _T_4820; // @[Mux.scala 27:72]
|
|
wire _T_4849 = _T_4845 | _T_4846; // @[Mux.scala 27:72]
|
|
wire _T_4825 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[el2_lsu_bus_buffer.scala 608:56]
|
|
wire _T_4826 = obuf_valid & _T_4825; // @[el2_lsu_bus_buffer.scala 608:38]
|
|
wire _T_4828 = obuf_tag1 == 2'h2; // @[el2_lsu_bus_buffer.scala 608:126]
|
|
wire _T_4829 = obuf_merge & _T_4828; // @[el2_lsu_bus_buffer.scala 608:114]
|
|
wire _T_4830 = _T_3948 | _T_4829; // @[el2_lsu_bus_buffer.scala 608:100]
|
|
wire _T_4831 = ~_T_4830; // @[el2_lsu_bus_buffer.scala 608:80]
|
|
wire _T_4832 = _T_4826 & _T_4831; // @[el2_lsu_bus_buffer.scala 608:78]
|
|
wire _T_4847 = _T_4786 & _T_4832; // @[Mux.scala 27:72]
|
|
wire _T_4850 = _T_4849 | _T_4847; // @[Mux.scala 27:72]
|
|
wire _T_4837 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[el2_lsu_bus_buffer.scala 608:56]
|
|
wire _T_4838 = obuf_valid & _T_4837; // @[el2_lsu_bus_buffer.scala 608:38]
|
|
wire _T_4840 = obuf_tag1 == 2'h3; // @[el2_lsu_bus_buffer.scala 608:126]
|
|
wire _T_4841 = obuf_merge & _T_4840; // @[el2_lsu_bus_buffer.scala 608:114]
|
|
wire _T_4842 = _T_4141 | _T_4841; // @[el2_lsu_bus_buffer.scala 608:100]
|
|
wire _T_4843 = ~_T_4842; // @[el2_lsu_bus_buffer.scala 608:80]
|
|
wire _T_4844 = _T_4838 & _T_4843; // @[el2_lsu_bus_buffer.scala 608:78]
|
|
wire _T_4848 = _T_4790 & _T_4844; // @[Mux.scala 27:72]
|
|
wire bus_addr_match_pending = _T_4850 | _T_4848; // @[Mux.scala 27:72]
|
|
wire _T_1239 = ~bus_addr_match_pending; // @[el2_lsu_bus_buffer.scala 341:118]
|
|
wire _T_1240 = _T_1236 & _T_1239; // @[el2_lsu_bus_buffer.scala 341:116]
|
|
wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 341:142]
|
|
wire _T_1242 = obuf_valid & obuf_nosend; // @[el2_lsu_bus_buffer.scala 343:47]
|
|
wire bus_wcmd_sent = io_lsu_axi_awvalid & io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 611:39]
|
|
wire _T_4860 = obuf_cmd_done | bus_wcmd_sent; // @[el2_lsu_bus_buffer.scala 613:35]
|
|
wire bus_wdata_sent = io_lsu_axi_wvalid & io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 612:39]
|
|
wire _T_4861 = obuf_data_done | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 613:70]
|
|
wire _T_4862 = _T_4860 & _T_4861; // @[el2_lsu_bus_buffer.scala 613:52]
|
|
wire _T_4863 = io_lsu_axi_arvalid & io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 613:111]
|
|
wire bus_cmd_sent = _T_4862 | _T_4863; // @[el2_lsu_bus_buffer.scala 613:89]
|
|
wire _T_1243 = bus_cmd_sent | _T_1242; // @[el2_lsu_bus_buffer.scala 343:33]
|
|
wire _T_1244 = ~obuf_wr_en; // @[el2_lsu_bus_buffer.scala 343:65]
|
|
wire _T_1245 = _T_1243 & _T_1244; // @[el2_lsu_bus_buffer.scala 343:63]
|
|
wire _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 343:77]
|
|
wire obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 343:98]
|
|
wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[el2_lsu_bus_buffer.scala 344:26]
|
|
wire [31:0] _T_1283 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1284 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1285 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1286 = _T_1026 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1287 = _T_1283 | _T_1284; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1288 = _T_1287 | _T_1285; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1289 = _T_1288 | _T_1286; // @[Mux.scala 27:72]
|
|
wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1289; // @[el2_lsu_bus_buffer.scala 346:25]
|
|
reg [1:0] buf_sz_0; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_1296 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72]
|
|
reg [1:0] buf_sz_1; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_1297 = _T_1024 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72]
|
|
reg [1:0] buf_sz_2; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_1298 = _T_1025 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72]
|
|
reg [1:0] buf_sz_3; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_1299 = _T_1026 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_1300 = _T_1296 | _T_1297; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_1301 = _T_1300 | _T_1298; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_1302 = _T_1301 | _T_1299; // @[Mux.scala 27:72]
|
|
wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1302; // @[el2_lsu_bus_buffer.scala 349:23]
|
|
wire [7:0] _T_2079 = {4'h0,_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58]
|
|
wire _T_2082 = _T_2079[4] | _T_2079[5]; // @[el2_lsu_bus_buffer.scala 440:42]
|
|
wire _T_2084 = _T_2082 | _T_2079[6]; // @[el2_lsu_bus_buffer.scala 440:48]
|
|
wire _T_2086 = _T_2084 | _T_2079[7]; // @[el2_lsu_bus_buffer.scala 440:54]
|
|
wire _T_2089 = _T_2079[2] | _T_2079[3]; // @[el2_lsu_bus_buffer.scala 440:67]
|
|
wire _T_2091 = _T_2089 | _T_2079[6]; // @[el2_lsu_bus_buffer.scala 440:73]
|
|
wire _T_2093 = _T_2091 | _T_2079[7]; // @[el2_lsu_bus_buffer.scala 440:79]
|
|
wire _T_2096 = _T_2079[1] | _T_2079[3]; // @[el2_lsu_bus_buffer.scala 440:92]
|
|
wire _T_2098 = _T_2096 | _T_2079[5]; // @[el2_lsu_bus_buffer.scala 440:98]
|
|
wire _T_2100 = _T_2098 | _T_2079[7]; // @[el2_lsu_bus_buffer.scala 440:104]
|
|
wire [2:0] _T_2102 = {_T_2086,_T_2093,_T_2100}; // @[Cat.scala 29:58]
|
|
wire [1:0] CmdPtr1 = _T_2102[1:0]; // @[el2_lsu_bus_buffer.scala 447:11]
|
|
wire _T_1304 = obuf_wr_en | obuf_rst; // @[el2_lsu_bus_buffer.scala 358:39]
|
|
wire _T_1305 = ~_T_1304; // @[el2_lsu_bus_buffer.scala 358:26]
|
|
wire _T_1311 = obuf_sz_in == 2'h0; // @[el2_lsu_bus_buffer.scala 362:72]
|
|
wire _T_1314 = ~obuf_addr_in[0]; // @[el2_lsu_bus_buffer.scala 362:98]
|
|
wire _T_1315 = obuf_sz_in[0] & _T_1314; // @[el2_lsu_bus_buffer.scala 362:96]
|
|
wire _T_1316 = _T_1311 | _T_1315; // @[el2_lsu_bus_buffer.scala 362:79]
|
|
wire _T_1319 = |obuf_addr_in[1:0]; // @[el2_lsu_bus_buffer.scala 362:153]
|
|
wire _T_1320 = ~_T_1319; // @[el2_lsu_bus_buffer.scala 362:134]
|
|
wire _T_1321 = obuf_sz_in[1] & _T_1320; // @[el2_lsu_bus_buffer.scala 362:132]
|
|
wire _T_1322 = _T_1316 | _T_1321; // @[el2_lsu_bus_buffer.scala 362:116]
|
|
wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1322; // @[el2_lsu_bus_buffer.scala 362:28]
|
|
wire _T_1339 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[el2_lsu_bus_buffer.scala 376:40]
|
|
wire _T_1340 = _T_1339 & obuf_aligned_in; // @[el2_lsu_bus_buffer.scala 376:60]
|
|
reg obuf_sideeffect; // @[Reg.scala 27:20]
|
|
wire _T_1341 = ~obuf_sideeffect; // @[el2_lsu_bus_buffer.scala 376:80]
|
|
wire _T_1342 = _T_1340 & _T_1341; // @[el2_lsu_bus_buffer.scala 376:78]
|
|
wire _T_1343 = ~obuf_write; // @[el2_lsu_bus_buffer.scala 376:99]
|
|
wire _T_1344 = _T_1342 & _T_1343; // @[el2_lsu_bus_buffer.scala 376:97]
|
|
wire _T_1345 = ~obuf_write_in; // @[el2_lsu_bus_buffer.scala 376:113]
|
|
wire _T_1346 = _T_1344 & _T_1345; // @[el2_lsu_bus_buffer.scala 376:111]
|
|
wire _T_1347 = ~io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_buffer.scala 376:130]
|
|
wire _T_1348 = _T_1346 & _T_1347; // @[el2_lsu_bus_buffer.scala 376:128]
|
|
wire _T_1349 = ~obuf_nosend; // @[el2_lsu_bus_buffer.scala 377:20]
|
|
wire _T_1350 = obuf_valid & _T_1349; // @[el2_lsu_bus_buffer.scala 377:18]
|
|
reg obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 404:56]
|
|
wire bus_rsp_read = io_lsu_axi_rvalid & io_lsu_axi_rready; // @[el2_lsu_bus_buffer.scala 614:37]
|
|
reg [2:0] obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 405:55]
|
|
wire _T_1351 = io_lsu_axi_rid == obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 377:90]
|
|
wire _T_1352 = bus_rsp_read & _T_1351; // @[el2_lsu_bus_buffer.scala 377:70]
|
|
wire _T_1353 = ~_T_1352; // @[el2_lsu_bus_buffer.scala 377:55]
|
|
wire _T_1354 = obuf_rdrsp_pend & _T_1353; // @[el2_lsu_bus_buffer.scala 377:53]
|
|
wire _T_1355 = _T_1350 | _T_1354; // @[el2_lsu_bus_buffer.scala 377:34]
|
|
wire obuf_nosend_in = _T_1348 & _T_1355; // @[el2_lsu_bus_buffer.scala 376:165]
|
|
wire _T_1323 = ~obuf_nosend_in; // @[el2_lsu_bus_buffer.scala 370:44]
|
|
wire _T_1324 = obuf_wr_en & _T_1323; // @[el2_lsu_bus_buffer.scala 370:42]
|
|
wire _T_1325 = ~_T_1324; // @[el2_lsu_bus_buffer.scala 370:29]
|
|
wire _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 370:61]
|
|
wire _T_1330 = _T_1326 & _T_1353; // @[el2_lsu_bus_buffer.scala 370:79]
|
|
wire _T_1332 = bus_cmd_sent & _T_1343; // @[el2_lsu_bus_buffer.scala 371:20]
|
|
wire _T_1333 = ~io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 371:37]
|
|
wire _T_1334 = _T_1332 & _T_1333; // @[el2_lsu_bus_buffer.scala 371:35]
|
|
wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[el2_lsu_bus_buffer.scala 378:46]
|
|
wire [3:0] _T_1379 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1380 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1381 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1382 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1383 = _T_1379 | _T_1380; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1384 = _T_1383 | _T_1381; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1385 = _T_1384 | _T_1382; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_1387 = {_T_1385,4'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1400 = {4'h0,_T_1385}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[el2_lsu_bus_buffer.scala 379:8]
|
|
wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[el2_lsu_bus_buffer.scala 378:28]
|
|
wire [7:0] _T_1403 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1404 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[el2_lsu_bus_buffer.scala 380:46]
|
|
wire _T_1406 = CmdPtr1 == 2'h0; // @[el2_lsu_bus_buffer.scala 112:123]
|
|
wire _T_1407 = CmdPtr1 == 2'h1; // @[el2_lsu_bus_buffer.scala 112:123]
|
|
wire _T_1408 = CmdPtr1 == 2'h2; // @[el2_lsu_bus_buffer.scala 112:123]
|
|
wire _T_1409 = CmdPtr1 == 2'h3; // @[el2_lsu_bus_buffer.scala 112:123]
|
|
wire [31:0] _T_1410 = _T_1406 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1411 = _T_1407 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1412 = _T_1408 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1413 = _T_1409 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1414 = _T_1410 | _T_1411; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1415 = _T_1414 | _T_1412; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1416 = _T_1415 | _T_1413; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1424 = _T_1406 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1425 = _T_1407 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1426 = _T_1408 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1427 = _T_1409 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1428 = _T_1424 | _T_1425; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1429 = _T_1428 | _T_1426; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1430 = _T_1429 | _T_1427; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_1432 = {_T_1430,4'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1445 = {4'h0,_T_1430}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1446 = _T_1416[2] ? _T_1432 : _T_1445; // @[el2_lsu_bus_buffer.scala 381:8]
|
|
wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[el2_lsu_bus_buffer.scala 380:28]
|
|
wire [63:0] _T_1448 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1449 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[el2_lsu_bus_buffer.scala 383:44]
|
|
wire [31:0] _T_1469 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1470 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1471 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1472 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1473 = _T_1469 | _T_1470; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1474 = _T_1473 | _T_1471; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1475 = _T_1474 | _T_1472; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_1477 = {_T_1475,32'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1490 = {32'h0,_T_1475}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[el2_lsu_bus_buffer.scala 384:8]
|
|
wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[el2_lsu_bus_buffer.scala 383:26]
|
|
wire [63:0] _T_1493 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1494 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[el2_lsu_bus_buffer.scala 385:44]
|
|
wire [31:0] _T_1514 = _T_1406 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1515 = _T_1407 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1516 = _T_1408 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1517 = _T_1409 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1518 = _T_1514 | _T_1515; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1519 = _T_1518 | _T_1516; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1520 = _T_1519 | _T_1517; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_1522 = {_T_1520,32'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1535 = {32'h0,_T_1520}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1536 = _T_1416[2] ? _T_1522 : _T_1535; // @[el2_lsu_bus_buffer.scala 386:8]
|
|
wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[el2_lsu_bus_buffer.scala 385:26]
|
|
wire _T_1621 = CmdPtr0 != CmdPtr1; // @[el2_lsu_bus_buffer.scala 392:30]
|
|
wire _T_1622 = _T_1621 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 392:43]
|
|
wire _T_1623 = _T_1622 & found_cmdptr1; // @[el2_lsu_bus_buffer.scala 392:59]
|
|
wire _T_1637 = _T_1623 & _T_1107; // @[el2_lsu_bus_buffer.scala 392:75]
|
|
wire [2:0] _T_1642 = _T_1406 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1643 = _T_1407 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1646 = _T_1642 | _T_1643; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1644 = _T_1408 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1647 = _T_1646 | _T_1644; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1645 = _T_1409 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1648 = _T_1647 | _T_1645; // @[Mux.scala 27:72]
|
|
wire _T_1650 = _T_1648 == 3'h2; // @[el2_lsu_bus_buffer.scala 392:150]
|
|
wire _T_1651 = _T_1637 & _T_1650; // @[el2_lsu_bus_buffer.scala 392:118]
|
|
wire _T_1672 = _T_1651 & _T_1128; // @[el2_lsu_bus_buffer.scala 392:161]
|
|
wire _T_1690 = _T_1672 & _T_1053; // @[el2_lsu_bus_buffer.scala 393:85]
|
|
wire _T_1792 = _T_1204 & _T_1166; // @[el2_lsu_bus_buffer.scala 396:38]
|
|
reg buf_dualhi_3; // @[Reg.scala 27:20]
|
|
reg buf_dualhi_2; // @[Reg.scala 27:20]
|
|
reg buf_dualhi_1; // @[Reg.scala 27:20]
|
|
reg buf_dualhi_0; // @[Reg.scala 27:20]
|
|
wire [3:0] _T_1795 = {buf_dualhi_3,buf_dualhi_2,buf_dualhi_1,buf_dualhi_0}; // @[Cat.scala 29:58]
|
|
wire _T_1804 = _T_1023 & _T_1795[0]; // @[Mux.scala 27:72]
|
|
wire _T_1805 = _T_1024 & _T_1795[1]; // @[Mux.scala 27:72]
|
|
wire _T_1808 = _T_1804 | _T_1805; // @[Mux.scala 27:72]
|
|
wire _T_1806 = _T_1025 & _T_1795[2]; // @[Mux.scala 27:72]
|
|
wire _T_1809 = _T_1808 | _T_1806; // @[Mux.scala 27:72]
|
|
wire _T_1807 = _T_1026 & _T_1795[3]; // @[Mux.scala 27:72]
|
|
wire _T_1810 = _T_1809 | _T_1807; // @[Mux.scala 27:72]
|
|
wire _T_1812 = ~_T_1810; // @[el2_lsu_bus_buffer.scala 396:109]
|
|
wire _T_1813 = _T_1792 & _T_1812; // @[el2_lsu_bus_buffer.scala 396:107]
|
|
wire _T_1833 = _T_1813 & _T_1185; // @[el2_lsu_bus_buffer.scala 396:179]
|
|
wire _T_1835 = _T_1690 & _T_1833; // @[el2_lsu_bus_buffer.scala 393:122]
|
|
wire _T_1836 = ibuf_buf_byp & ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 397:19]
|
|
wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 397:35]
|
|
wire obuf_merge_en = _T_1835 | _T_1837; // @[el2_lsu_bus_buffer.scala 396:253]
|
|
wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[el2_lsu_bus_buffer.scala 387:80]
|
|
wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[el2_lsu_bus_buffer.scala 387:63]
|
|
wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[el2_lsu_bus_buffer.scala 387:80]
|
|
wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[el2_lsu_bus_buffer.scala 387:63]
|
|
wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[el2_lsu_bus_buffer.scala 387:80]
|
|
wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[el2_lsu_bus_buffer.scala 387:63]
|
|
wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[el2_lsu_bus_buffer.scala 387:80]
|
|
wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[el2_lsu_bus_buffer.scala 387:63]
|
|
wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[el2_lsu_bus_buffer.scala 387:80]
|
|
wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[el2_lsu_bus_buffer.scala 387:63]
|
|
wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[el2_lsu_bus_buffer.scala 387:80]
|
|
wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[el2_lsu_bus_buffer.scala 387:63]
|
|
wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[el2_lsu_bus_buffer.scala 387:80]
|
|
wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[el2_lsu_bus_buffer.scala 387:63]
|
|
wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[el2_lsu_bus_buffer.scala 387:80]
|
|
wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[el2_lsu_bus_buffer.scala 387:63]
|
|
wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[el2_lsu_bus_buffer.scala 388:44]
|
|
wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[el2_lsu_bus_buffer.scala 388:44]
|
|
wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[el2_lsu_bus_buffer.scala 388:44]
|
|
wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[el2_lsu_bus_buffer.scala 388:44]
|
|
wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[el2_lsu_bus_buffer.scala 388:44]
|
|
wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[el2_lsu_bus_buffer.scala 388:44]
|
|
wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[el2_lsu_bus_buffer.scala 388:44]
|
|
wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[el2_lsu_bus_buffer.scala 388:44]
|
|
wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58]
|
|
wire _T_1839 = obuf_wr_en | obuf_valid; // @[el2_lsu_bus_buffer.scala 400:58]
|
|
wire _T_1840 = ~obuf_rst; // @[el2_lsu_bus_buffer.scala 400:93]
|
|
reg [1:0] obuf_sz; // @[Reg.scala 27:20]
|
|
reg [7:0] obuf_byteen; // @[Reg.scala 27:20]
|
|
reg [63:0] obuf_data; // @[el2_lib.scala 514:16]
|
|
wire _T_1853 = buf_state_0 == 3'h0; // @[el2_lsu_bus_buffer.scala 418:65]
|
|
wire _T_1854 = ibuf_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 419:30]
|
|
wire _T_1855 = ibuf_valid & _T_1854; // @[el2_lsu_bus_buffer.scala 419:19]
|
|
wire _T_1856 = WrPtr0_r == 2'h0; // @[el2_lsu_bus_buffer.scala 420:18]
|
|
wire _T_1857 = WrPtr1_r == 2'h0; // @[el2_lsu_bus_buffer.scala 420:57]
|
|
wire _T_1858 = io_ldst_dual_r & _T_1857; // @[el2_lsu_bus_buffer.scala 420:45]
|
|
wire _T_1859 = _T_1856 | _T_1858; // @[el2_lsu_bus_buffer.scala 420:27]
|
|
wire _T_1860 = io_lsu_busreq_r & _T_1859; // @[el2_lsu_bus_buffer.scala 419:58]
|
|
wire _T_1861 = _T_1855 | _T_1860; // @[el2_lsu_bus_buffer.scala 419:39]
|
|
wire _T_1862 = ~_T_1861; // @[el2_lsu_bus_buffer.scala 419:5]
|
|
wire _T_1863 = _T_1853 & _T_1862; // @[el2_lsu_bus_buffer.scala 418:76]
|
|
wire _T_1864 = buf_state_1 == 3'h0; // @[el2_lsu_bus_buffer.scala 418:65]
|
|
wire _T_1865 = ibuf_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 419:30]
|
|
wire _T_1866 = ibuf_valid & _T_1865; // @[el2_lsu_bus_buffer.scala 419:19]
|
|
wire _T_1867 = WrPtr0_r == 2'h1; // @[el2_lsu_bus_buffer.scala 420:18]
|
|
wire _T_1868 = WrPtr1_r == 2'h1; // @[el2_lsu_bus_buffer.scala 420:57]
|
|
wire _T_1869 = io_ldst_dual_r & _T_1868; // @[el2_lsu_bus_buffer.scala 420:45]
|
|
wire _T_1870 = _T_1867 | _T_1869; // @[el2_lsu_bus_buffer.scala 420:27]
|
|
wire _T_1871 = io_lsu_busreq_r & _T_1870; // @[el2_lsu_bus_buffer.scala 419:58]
|
|
wire _T_1872 = _T_1866 | _T_1871; // @[el2_lsu_bus_buffer.scala 419:39]
|
|
wire _T_1873 = ~_T_1872; // @[el2_lsu_bus_buffer.scala 419:5]
|
|
wire _T_1874 = _T_1864 & _T_1873; // @[el2_lsu_bus_buffer.scala 418:76]
|
|
wire _T_1875 = buf_state_2 == 3'h0; // @[el2_lsu_bus_buffer.scala 418:65]
|
|
wire _T_1876 = ibuf_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 419:30]
|
|
wire _T_1877 = ibuf_valid & _T_1876; // @[el2_lsu_bus_buffer.scala 419:19]
|
|
wire _T_1878 = WrPtr0_r == 2'h2; // @[el2_lsu_bus_buffer.scala 420:18]
|
|
wire _T_1879 = WrPtr1_r == 2'h2; // @[el2_lsu_bus_buffer.scala 420:57]
|
|
wire _T_1880 = io_ldst_dual_r & _T_1879; // @[el2_lsu_bus_buffer.scala 420:45]
|
|
wire _T_1881 = _T_1878 | _T_1880; // @[el2_lsu_bus_buffer.scala 420:27]
|
|
wire _T_1882 = io_lsu_busreq_r & _T_1881; // @[el2_lsu_bus_buffer.scala 419:58]
|
|
wire _T_1883 = _T_1877 | _T_1882; // @[el2_lsu_bus_buffer.scala 419:39]
|
|
wire _T_1884 = ~_T_1883; // @[el2_lsu_bus_buffer.scala 419:5]
|
|
wire _T_1885 = _T_1875 & _T_1884; // @[el2_lsu_bus_buffer.scala 418:76]
|
|
wire _T_1886 = buf_state_3 == 3'h0; // @[el2_lsu_bus_buffer.scala 418:65]
|
|
wire _T_1887 = ibuf_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 419:30]
|
|
wire _T_1889 = WrPtr0_r == 2'h3; // @[el2_lsu_bus_buffer.scala 420:18]
|
|
wire _T_1890 = WrPtr1_r == 2'h3; // @[el2_lsu_bus_buffer.scala 420:57]
|
|
wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1899 = _T_1874 ? 2'h1 : _T_1898; // @[Mux.scala 98:16]
|
|
wire [1:0] WrPtr0_m = _T_1863 ? 2'h0 : _T_1899; // @[Mux.scala 98:16]
|
|
wire _T_1904 = WrPtr0_m == 2'h0; // @[el2_lsu_bus_buffer.scala 425:33]
|
|
wire _T_1905 = io_lsu_busreq_m & _T_1904; // @[el2_lsu_bus_buffer.scala 425:22]
|
|
wire _T_1906 = _T_1855 | _T_1905; // @[el2_lsu_bus_buffer.scala 424:112]
|
|
wire _T_1912 = _T_1906 | _T_1860; // @[el2_lsu_bus_buffer.scala 425:42]
|
|
wire _T_1913 = ~_T_1912; // @[el2_lsu_bus_buffer.scala 424:78]
|
|
wire _T_1914 = _T_1853 & _T_1913; // @[el2_lsu_bus_buffer.scala 424:76]
|
|
wire _T_1918 = WrPtr0_m == 2'h1; // @[el2_lsu_bus_buffer.scala 425:33]
|
|
wire _T_1919 = io_lsu_busreq_m & _T_1918; // @[el2_lsu_bus_buffer.scala 425:22]
|
|
wire _T_1920 = _T_1866 | _T_1919; // @[el2_lsu_bus_buffer.scala 424:112]
|
|
wire _T_1926 = _T_1920 | _T_1871; // @[el2_lsu_bus_buffer.scala 425:42]
|
|
wire _T_1927 = ~_T_1926; // @[el2_lsu_bus_buffer.scala 424:78]
|
|
wire _T_1928 = _T_1864 & _T_1927; // @[el2_lsu_bus_buffer.scala 424:76]
|
|
wire _T_1932 = WrPtr0_m == 2'h2; // @[el2_lsu_bus_buffer.scala 425:33]
|
|
wire _T_1933 = io_lsu_busreq_m & _T_1932; // @[el2_lsu_bus_buffer.scala 425:22]
|
|
wire _T_1934 = _T_1877 | _T_1933; // @[el2_lsu_bus_buffer.scala 424:112]
|
|
wire _T_1940 = _T_1934 | _T_1882; // @[el2_lsu_bus_buffer.scala 425:42]
|
|
wire _T_1941 = ~_T_1940; // @[el2_lsu_bus_buffer.scala 424:78]
|
|
wire _T_1942 = _T_1875 & _T_1941; // @[el2_lsu_bus_buffer.scala 424:76]
|
|
reg [3:0] buf_rspageQ_0; // @[el2_lsu_bus_buffer.scala 555:63]
|
|
wire _T_2746 = buf_state_3 == 3'h5; // @[el2_lsu_bus_buffer.scala 468:102]
|
|
wire _T_2747 = buf_rspageQ_0[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2743 = buf_state_2 == 3'h5; // @[el2_lsu_bus_buffer.scala 468:102]
|
|
wire _T_2744 = buf_rspageQ_0[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2740 = buf_state_1 == 3'h5; // @[el2_lsu_bus_buffer.scala 468:102]
|
|
wire _T_2741 = buf_rspageQ_0[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2737 = buf_state_0 == 3'h5; // @[el2_lsu_bus_buffer.scala 468:102]
|
|
wire _T_2738 = buf_rspageQ_0[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire [3:0] buf_rsp_pickage_0 = {_T_2747,_T_2744,_T_2741,_T_2738}; // @[Cat.scala 29:58]
|
|
wire _T_2033 = |buf_rsp_pickage_0; // @[el2_lsu_bus_buffer.scala 436:65]
|
|
wire _T_2034 = ~_T_2033; // @[el2_lsu_bus_buffer.scala 436:44]
|
|
wire _T_2036 = _T_2034 & _T_2737; // @[el2_lsu_bus_buffer.scala 436:70]
|
|
reg [3:0] buf_rspageQ_1; // @[el2_lsu_bus_buffer.scala 555:63]
|
|
wire _T_2762 = buf_rspageQ_1[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2759 = buf_rspageQ_1[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2756 = buf_rspageQ_1[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2753 = buf_rspageQ_1[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire [3:0] buf_rsp_pickage_1 = {_T_2762,_T_2759,_T_2756,_T_2753}; // @[Cat.scala 29:58]
|
|
wire _T_2037 = |buf_rsp_pickage_1; // @[el2_lsu_bus_buffer.scala 436:65]
|
|
wire _T_2038 = ~_T_2037; // @[el2_lsu_bus_buffer.scala 436:44]
|
|
wire _T_2040 = _T_2038 & _T_2740; // @[el2_lsu_bus_buffer.scala 436:70]
|
|
reg [3:0] buf_rspageQ_2; // @[el2_lsu_bus_buffer.scala 555:63]
|
|
wire _T_2777 = buf_rspageQ_2[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2774 = buf_rspageQ_2[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2771 = buf_rspageQ_2[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2768 = buf_rspageQ_2[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire [3:0] buf_rsp_pickage_2 = {_T_2777,_T_2774,_T_2771,_T_2768}; // @[Cat.scala 29:58]
|
|
wire _T_2041 = |buf_rsp_pickage_2; // @[el2_lsu_bus_buffer.scala 436:65]
|
|
wire _T_2042 = ~_T_2041; // @[el2_lsu_bus_buffer.scala 436:44]
|
|
wire _T_2044 = _T_2042 & _T_2743; // @[el2_lsu_bus_buffer.scala 436:70]
|
|
reg [3:0] buf_rspageQ_3; // @[el2_lsu_bus_buffer.scala 555:63]
|
|
wire _T_2792 = buf_rspageQ_3[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2789 = buf_rspageQ_3[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2786 = buf_rspageQ_3[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire _T_2783 = buf_rspageQ_3[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 468:87]
|
|
wire [3:0] buf_rsp_pickage_3 = {_T_2792,_T_2789,_T_2786,_T_2783}; // @[Cat.scala 29:58]
|
|
wire _T_2045 = |buf_rsp_pickage_3; // @[el2_lsu_bus_buffer.scala 436:65]
|
|
wire _T_2046 = ~_T_2045; // @[el2_lsu_bus_buffer.scala 436:44]
|
|
wire _T_2048 = _T_2046 & _T_2746; // @[el2_lsu_bus_buffer.scala 436:70]
|
|
wire [7:0] _T_2104 = {4'h0,_T_2048,_T_2044,_T_2040,_T_2036}; // @[Cat.scala 29:58]
|
|
wire _T_2107 = _T_2104[4] | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 440:42]
|
|
wire _T_2109 = _T_2107 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 440:48]
|
|
wire _T_2111 = _T_2109 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 440:54]
|
|
wire _T_2114 = _T_2104[2] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 440:67]
|
|
wire _T_2116 = _T_2114 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 440:73]
|
|
wire _T_2118 = _T_2116 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 440:79]
|
|
wire _T_2121 = _T_2104[1] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 440:92]
|
|
wire _T_2123 = _T_2121 | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 440:98]
|
|
wire _T_2125 = _T_2123 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 440:104]
|
|
wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58]
|
|
wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 498:77]
|
|
wire _T_3533 = ~ibuf_merge_en; // @[el2_lsu_bus_buffer.scala 498:97]
|
|
wire _T_3534 = _T_3532 & _T_3533; // @[el2_lsu_bus_buffer.scala 498:95]
|
|
wire _T_3535 = 2'h0 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 498:117]
|
|
wire _T_3536 = _T_3534 & _T_3535; // @[el2_lsu_bus_buffer.scala 498:112]
|
|
wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 498:144]
|
|
wire _T_3538 = 2'h0 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 498:166]
|
|
wire _T_3539 = _T_3537 & _T_3538; // @[el2_lsu_bus_buffer.scala 498:161]
|
|
wire _T_3540 = _T_3536 | _T_3539; // @[el2_lsu_bus_buffer.scala 498:132]
|
|
wire _T_3541 = _T_853 & _T_3540; // @[el2_lsu_bus_buffer.scala 498:63]
|
|
wire _T_3542 = 2'h0 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 498:206]
|
|
wire _T_3543 = ibuf_drain_vld & _T_3542; // @[el2_lsu_bus_buffer.scala 498:201]
|
|
wire _T_3544 = _T_3541 | _T_3543; // @[el2_lsu_bus_buffer.scala 498:183]
|
|
wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 505:46]
|
|
wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire bus_rsp_write = io_lsu_axi_bvalid & io_lsu_axi_bready; // @[el2_lsu_bus_buffer.scala 615:38]
|
|
wire _T_3634 = io_lsu_axi_bid == 3'h0; // @[el2_lsu_bus_buffer.scala 523:73]
|
|
wire _T_3635 = bus_rsp_write & _T_3634; // @[el2_lsu_bus_buffer.scala 523:52]
|
|
wire _T_3636 = io_lsu_axi_rid == 3'h0; // @[el2_lsu_bus_buffer.scala 524:46]
|
|
reg _T_4307; // @[Reg.scala 27:20]
|
|
reg _T_4305; // @[Reg.scala 27:20]
|
|
reg _T_4303; // @[Reg.scala 27:20]
|
|
reg _T_4301; // @[Reg.scala 27:20]
|
|
wire [3:0] buf_ldfwd = {_T_4307,_T_4305,_T_4303,_T_4301}; // @[Cat.scala 29:58]
|
|
reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_0}; // @[el2_lsu_bus_buffer.scala 525:47]
|
|
wire _T_3638 = io_lsu_axi_rid == _GEN_368; // @[el2_lsu_bus_buffer.scala 525:47]
|
|
wire _T_3639 = buf_ldfwd[0] & _T_3638; // @[el2_lsu_bus_buffer.scala 525:27]
|
|
wire _T_3640 = _T_3636 | _T_3639; // @[el2_lsu_bus_buffer.scala 524:77]
|
|
wire _T_3641 = buf_dual_0 & buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 526:26]
|
|
wire _T_3643 = ~buf_write[0]; // @[el2_lsu_bus_buffer.scala 526:44]
|
|
wire _T_3644 = _T_3641 & _T_3643; // @[el2_lsu_bus_buffer.scala 526:42]
|
|
wire _T_3645 = _T_3644 & buf_samedw_0; // @[el2_lsu_bus_buffer.scala 526:58]
|
|
reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_0}; // @[el2_lsu_bus_buffer.scala 526:94]
|
|
wire _T_3646 = io_lsu_axi_rid == _GEN_369; // @[el2_lsu_bus_buffer.scala 526:94]
|
|
wire _T_3647 = _T_3645 & _T_3646; // @[el2_lsu_bus_buffer.scala 526:74]
|
|
wire _T_3648 = _T_3640 | _T_3647; // @[el2_lsu_bus_buffer.scala 525:71]
|
|
wire _T_3649 = bus_rsp_read & _T_3648; // @[el2_lsu_bus_buffer.scala 524:25]
|
|
wire _T_3650 = _T_3635 | _T_3649; // @[el2_lsu_bus_buffer.scala 523:105]
|
|
wire _GEN_42 = _T_3589 & _T_3650; // @[Conditional.scala 39:67]
|
|
wire _GEN_61 = _T_3555 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67]
|
|
wire _GEN_73 = _T_3551 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67]
|
|
wire buf_resp_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_73; // @[Conditional.scala 40:58]
|
|
wire _T_3676 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[el2_lsu_bus_buffer.scala 538:21]
|
|
reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20]
|
|
reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20]
|
|
reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20]
|
|
wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [2:0] _GEN_371 = {{1'd0}, _GEN_25}; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire _T_3688 = io_lsu_axi_rid == _GEN_371; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire _T_3689 = _T_3686[0] & _T_3688; // @[el2_lsu_bus_buffer.scala 538:38]
|
|
wire _T_3690 = _T_3646 | _T_3689; // @[el2_lsu_bus_buffer.scala 537:95]
|
|
wire _T_3691 = bus_rsp_read & _T_3690; // @[el2_lsu_bus_buffer.scala 537:45]
|
|
wire _GEN_36 = _T_3676 & _T_3691; // @[Conditional.scala 39:67]
|
|
wire _GEN_43 = _T_3589 ? buf_resp_state_bus_en_0 : _GEN_36; // @[Conditional.scala 39:67]
|
|
wire _GEN_53 = _T_3555 ? buf_cmd_state_bus_en_0 : _GEN_43; // @[Conditional.scala 39:67]
|
|
wire _GEN_66 = _T_3551 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
|
|
wire buf_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58]
|
|
wire _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 511:49]
|
|
wire _T_3569 = _T_3568 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 511:70]
|
|
wire _T_3694 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire [1:0] RspPtr = _T_2127[1:0]; // @[el2_lsu_bus_buffer.scala 448:10]
|
|
wire _T_3697 = RspPtr == 2'h0; // @[el2_lsu_bus_buffer.scala 543:37]
|
|
wire _T_3698 = buf_dualtag_0 == RspPtr; // @[el2_lsu_bus_buffer.scala 543:98]
|
|
wire _T_3699 = buf_dual_0 & _T_3698; // @[el2_lsu_bus_buffer.scala 543:80]
|
|
wire _T_3700 = _T_3697 | _T_3699; // @[el2_lsu_bus_buffer.scala 543:65]
|
|
wire _T_3701 = _T_3700 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 543:112]
|
|
wire _T_3702 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire _GEN_31 = _T_3694 ? _T_3701 : _T_3702; // @[Conditional.scala 39:67]
|
|
wire _GEN_37 = _T_3676 ? _T_3569 : _GEN_31; // @[Conditional.scala 39:67]
|
|
wire _GEN_44 = _T_3589 ? _T_3569 : _GEN_37; // @[Conditional.scala 39:67]
|
|
wire _GEN_54 = _T_3555 ? _T_3569 : _GEN_44; // @[Conditional.scala 39:67]
|
|
wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67]
|
|
wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58]
|
|
wire _T_2129 = _T_1853 & buf_state_en_0; // @[el2_lsu_bus_buffer.scala 460:94]
|
|
wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 462:23]
|
|
wire _T_2137 = _T_2135 & _T_3532; // @[el2_lsu_bus_buffer.scala 462:41]
|
|
wire _T_2139 = _T_2137 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:71]
|
|
wire _T_2141 = _T_2139 & _T_1854; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2142 = _T_4471 | _T_2141; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2143 = ibuf_byp & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 463:17]
|
|
wire _T_2144 = _T_2143 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 463:35]
|
|
wire _T_2146 = _T_2144 & _T_1857; // @[el2_lsu_bus_buffer.scala 463:52]
|
|
wire _T_2148 = _T_2146 & _T_1856; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2149 = _T_2142 | _T_2148; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2150 = _T_2129 & _T_2149; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2152 = _T_2150 | buf_age_0[0]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2166 = _T_2139 & _T_1865; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2167 = _T_4476 | _T_2166; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2173 = _T_2146 & _T_1867; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2174 = _T_2167 | _T_2173; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2175 = _T_2129 & _T_2174; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2177 = _T_2175 | buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2191 = _T_2139 & _T_1876; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2192 = _T_4481 | _T_2191; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2198 = _T_2146 & _T_1878; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2199 = _T_2192 | _T_2198; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2200 = _T_2129 & _T_2199; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2202 = _T_2200 | buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2216 = _T_2139 & _T_1887; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2217 = _T_4486 | _T_2216; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2223 = _T_2146 & _T_1889; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2224 = _T_2217 | _T_2223; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2225 = _T_2129 & _T_2224; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2227 = _T_2225 | buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58]
|
|
wire _T_3728 = 2'h1 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 498:117]
|
|
wire _T_3729 = _T_3534 & _T_3728; // @[el2_lsu_bus_buffer.scala 498:112]
|
|
wire _T_3731 = 2'h1 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 498:166]
|
|
wire _T_3732 = _T_3537 & _T_3731; // @[el2_lsu_bus_buffer.scala 498:161]
|
|
wire _T_3733 = _T_3729 | _T_3732; // @[el2_lsu_bus_buffer.scala 498:132]
|
|
wire _T_3734 = _T_853 & _T_3733; // @[el2_lsu_bus_buffer.scala 498:63]
|
|
wire _T_3735 = 2'h1 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 498:206]
|
|
wire _T_3736 = ibuf_drain_vld & _T_3735; // @[el2_lsu_bus_buffer.scala 498:201]
|
|
wire _T_3737 = _T_3734 | _T_3736; // @[el2_lsu_bus_buffer.scala 498:183]
|
|
wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _T_3827 = io_lsu_axi_bid == 3'h1; // @[el2_lsu_bus_buffer.scala 523:73]
|
|
wire _T_3828 = bus_rsp_write & _T_3827; // @[el2_lsu_bus_buffer.scala 523:52]
|
|
wire _T_3829 = io_lsu_axi_rid == 3'h1; // @[el2_lsu_bus_buffer.scala 524:46]
|
|
wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_1}; // @[el2_lsu_bus_buffer.scala 525:47]
|
|
wire _T_3831 = io_lsu_axi_rid == _GEN_372; // @[el2_lsu_bus_buffer.scala 525:47]
|
|
wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[el2_lsu_bus_buffer.scala 525:27]
|
|
wire _T_3833 = _T_3829 | _T_3832; // @[el2_lsu_bus_buffer.scala 524:77]
|
|
wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 526:26]
|
|
wire _T_3836 = ~buf_write[1]; // @[el2_lsu_bus_buffer.scala 526:44]
|
|
wire _T_3837 = _T_3834 & _T_3836; // @[el2_lsu_bus_buffer.scala 526:42]
|
|
wire _T_3838 = _T_3837 & buf_samedw_1; // @[el2_lsu_bus_buffer.scala 526:58]
|
|
reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_1}; // @[el2_lsu_bus_buffer.scala 526:94]
|
|
wire _T_3839 = io_lsu_axi_rid == _GEN_373; // @[el2_lsu_bus_buffer.scala 526:94]
|
|
wire _T_3840 = _T_3838 & _T_3839; // @[el2_lsu_bus_buffer.scala 526:74]
|
|
wire _T_3841 = _T_3833 | _T_3840; // @[el2_lsu_bus_buffer.scala 525:71]
|
|
wire _T_3842 = bus_rsp_read & _T_3841; // @[el2_lsu_bus_buffer.scala 524:25]
|
|
wire _T_3843 = _T_3828 | _T_3842; // @[el2_lsu_bus_buffer.scala 523:105]
|
|
wire _GEN_118 = _T_3782 & _T_3843; // @[Conditional.scala 39:67]
|
|
wire _GEN_137 = _T_3748 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67]
|
|
wire _GEN_149 = _T_3744 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67]
|
|
wire buf_resp_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58]
|
|
wire _T_3869 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[el2_lsu_bus_buffer.scala 538:21]
|
|
wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [2:0] _GEN_375 = {{1'd0}, _GEN_101}; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire _T_3881 = io_lsu_axi_rid == _GEN_375; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire _T_3882 = _T_3879[0] & _T_3881; // @[el2_lsu_bus_buffer.scala 538:38]
|
|
wire _T_3883 = _T_3839 | _T_3882; // @[el2_lsu_bus_buffer.scala 537:95]
|
|
wire _T_3884 = bus_rsp_read & _T_3883; // @[el2_lsu_bus_buffer.scala 537:45]
|
|
wire _GEN_112 = _T_3869 & _T_3884; // @[Conditional.scala 39:67]
|
|
wire _GEN_119 = _T_3782 ? buf_resp_state_bus_en_1 : _GEN_112; // @[Conditional.scala 39:67]
|
|
wire _GEN_129 = _T_3748 ? buf_cmd_state_bus_en_1 : _GEN_119; // @[Conditional.scala 39:67]
|
|
wire _GEN_142 = _T_3744 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67]
|
|
wire buf_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58]
|
|
wire _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 511:49]
|
|
wire _T_3762 = _T_3761 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 511:70]
|
|
wire _T_3887 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _T_3890 = RspPtr == 2'h1; // @[el2_lsu_bus_buffer.scala 543:37]
|
|
wire _T_3891 = buf_dualtag_1 == RspPtr; // @[el2_lsu_bus_buffer.scala 543:98]
|
|
wire _T_3892 = buf_dual_1 & _T_3891; // @[el2_lsu_bus_buffer.scala 543:80]
|
|
wire _T_3893 = _T_3890 | _T_3892; // @[el2_lsu_bus_buffer.scala 543:65]
|
|
wire _T_3894 = _T_3893 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 543:112]
|
|
wire _T_3895 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _GEN_107 = _T_3887 ? _T_3894 : _T_3895; // @[Conditional.scala 39:67]
|
|
wire _GEN_113 = _T_3869 ? _T_3762 : _GEN_107; // @[Conditional.scala 39:67]
|
|
wire _GEN_120 = _T_3782 ? _T_3762 : _GEN_113; // @[Conditional.scala 39:67]
|
|
wire _GEN_130 = _T_3748 ? _T_3762 : _GEN_120; // @[Conditional.scala 39:67]
|
|
wire _GEN_140 = _T_3744 ? _T_3554 : _GEN_130; // @[Conditional.scala 39:67]
|
|
wire buf_state_en_1 = _T_3721 ? _T_3737 : _GEN_140; // @[Conditional.scala 40:58]
|
|
wire _T_2231 = _T_1864 & buf_state_en_1; // @[el2_lsu_bus_buffer.scala 460:94]
|
|
wire _T_2241 = _T_2137 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:71]
|
|
wire _T_2243 = _T_2241 & _T_1854; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2244 = _T_4471 | _T_2243; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2248 = _T_2144 & _T_1868; // @[el2_lsu_bus_buffer.scala 463:52]
|
|
wire _T_2250 = _T_2248 & _T_1856; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2251 = _T_2244 | _T_2250; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2252 = _T_2231 & _T_2251; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2254 = _T_2252 | buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2268 = _T_2241 & _T_1865; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2269 = _T_4476 | _T_2268; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2275 = _T_2248 & _T_1867; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2276 = _T_2269 | _T_2275; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2277 = _T_2231 & _T_2276; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2279 = _T_2277 | buf_age_1[1]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2293 = _T_2241 & _T_1876; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2294 = _T_4481 | _T_2293; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2300 = _T_2248 & _T_1878; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2301 = _T_2294 | _T_2300; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2302 = _T_2231 & _T_2301; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2304 = _T_2302 | buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2318 = _T_2241 & _T_1887; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2319 = _T_4486 | _T_2318; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2325 = _T_2248 & _T_1889; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2326 = _T_2319 | _T_2325; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2327 = _T_2231 & _T_2326; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2329 = _T_2327 | buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58]
|
|
wire _T_3921 = 2'h2 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 498:117]
|
|
wire _T_3922 = _T_3534 & _T_3921; // @[el2_lsu_bus_buffer.scala 498:112]
|
|
wire _T_3924 = 2'h2 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 498:166]
|
|
wire _T_3925 = _T_3537 & _T_3924; // @[el2_lsu_bus_buffer.scala 498:161]
|
|
wire _T_3926 = _T_3922 | _T_3925; // @[el2_lsu_bus_buffer.scala 498:132]
|
|
wire _T_3927 = _T_853 & _T_3926; // @[el2_lsu_bus_buffer.scala 498:63]
|
|
wire _T_3928 = 2'h2 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 498:206]
|
|
wire _T_3929 = ibuf_drain_vld & _T_3928; // @[el2_lsu_bus_buffer.scala 498:201]
|
|
wire _T_3930 = _T_3927 | _T_3929; // @[el2_lsu_bus_buffer.scala 498:183]
|
|
wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _T_4020 = io_lsu_axi_bid == 3'h2; // @[el2_lsu_bus_buffer.scala 523:73]
|
|
wire _T_4021 = bus_rsp_write & _T_4020; // @[el2_lsu_bus_buffer.scala 523:52]
|
|
wire _T_4022 = io_lsu_axi_rid == 3'h2; // @[el2_lsu_bus_buffer.scala 524:46]
|
|
wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_2}; // @[el2_lsu_bus_buffer.scala 525:47]
|
|
wire _T_4024 = io_lsu_axi_rid == _GEN_376; // @[el2_lsu_bus_buffer.scala 525:47]
|
|
wire _T_4025 = buf_ldfwd[2] & _T_4024; // @[el2_lsu_bus_buffer.scala 525:27]
|
|
wire _T_4026 = _T_4022 | _T_4025; // @[el2_lsu_bus_buffer.scala 524:77]
|
|
wire _T_4027 = buf_dual_2 & buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 526:26]
|
|
wire _T_4029 = ~buf_write[2]; // @[el2_lsu_bus_buffer.scala 526:44]
|
|
wire _T_4030 = _T_4027 & _T_4029; // @[el2_lsu_bus_buffer.scala 526:42]
|
|
wire _T_4031 = _T_4030 & buf_samedw_2; // @[el2_lsu_bus_buffer.scala 526:58]
|
|
reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_2}; // @[el2_lsu_bus_buffer.scala 526:94]
|
|
wire _T_4032 = io_lsu_axi_rid == _GEN_377; // @[el2_lsu_bus_buffer.scala 526:94]
|
|
wire _T_4033 = _T_4031 & _T_4032; // @[el2_lsu_bus_buffer.scala 526:74]
|
|
wire _T_4034 = _T_4026 | _T_4033; // @[el2_lsu_bus_buffer.scala 525:71]
|
|
wire _T_4035 = bus_rsp_read & _T_4034; // @[el2_lsu_bus_buffer.scala 524:25]
|
|
wire _T_4036 = _T_4021 | _T_4035; // @[el2_lsu_bus_buffer.scala 523:105]
|
|
wire _GEN_194 = _T_3975 & _T_4036; // @[Conditional.scala 39:67]
|
|
wire _GEN_213 = _T_3941 ? 1'h0 : _GEN_194; // @[Conditional.scala 39:67]
|
|
wire _GEN_225 = _T_3937 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67]
|
|
wire buf_resp_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_225; // @[Conditional.scala 40:58]
|
|
wire _T_4062 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[el2_lsu_bus_buffer.scala 538:21]
|
|
wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [2:0] _GEN_379 = {{1'd0}, _GEN_177}; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire _T_4074 = io_lsu_axi_rid == _GEN_379; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire _T_4075 = _T_4072[0] & _T_4074; // @[el2_lsu_bus_buffer.scala 538:38]
|
|
wire _T_4076 = _T_4032 | _T_4075; // @[el2_lsu_bus_buffer.scala 537:95]
|
|
wire _T_4077 = bus_rsp_read & _T_4076; // @[el2_lsu_bus_buffer.scala 537:45]
|
|
wire _GEN_188 = _T_4062 & _T_4077; // @[Conditional.scala 39:67]
|
|
wire _GEN_195 = _T_3975 ? buf_resp_state_bus_en_2 : _GEN_188; // @[Conditional.scala 39:67]
|
|
wire _GEN_205 = _T_3941 ? buf_cmd_state_bus_en_2 : _GEN_195; // @[Conditional.scala 39:67]
|
|
wire _GEN_218 = _T_3937 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67]
|
|
wire buf_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_218; // @[Conditional.scala 40:58]
|
|
wire _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 511:49]
|
|
wire _T_3955 = _T_3954 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 511:70]
|
|
wire _T_4080 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _T_4083 = RspPtr == 2'h2; // @[el2_lsu_bus_buffer.scala 543:37]
|
|
wire _T_4084 = buf_dualtag_2 == RspPtr; // @[el2_lsu_bus_buffer.scala 543:98]
|
|
wire _T_4085 = buf_dual_2 & _T_4084; // @[el2_lsu_bus_buffer.scala 543:80]
|
|
wire _T_4086 = _T_4083 | _T_4085; // @[el2_lsu_bus_buffer.scala 543:65]
|
|
wire _T_4087 = _T_4086 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 543:112]
|
|
wire _T_4088 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _GEN_183 = _T_4080 ? _T_4087 : _T_4088; // @[Conditional.scala 39:67]
|
|
wire _GEN_189 = _T_4062 ? _T_3955 : _GEN_183; // @[Conditional.scala 39:67]
|
|
wire _GEN_196 = _T_3975 ? _T_3955 : _GEN_189; // @[Conditional.scala 39:67]
|
|
wire _GEN_206 = _T_3941 ? _T_3955 : _GEN_196; // @[Conditional.scala 39:67]
|
|
wire _GEN_216 = _T_3937 ? _T_3554 : _GEN_206; // @[Conditional.scala 39:67]
|
|
wire buf_state_en_2 = _T_3914 ? _T_3930 : _GEN_216; // @[Conditional.scala 40:58]
|
|
wire _T_2333 = _T_1875 & buf_state_en_2; // @[el2_lsu_bus_buffer.scala 460:94]
|
|
wire _T_2343 = _T_2137 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:71]
|
|
wire _T_2345 = _T_2343 & _T_1854; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2346 = _T_4471 | _T_2345; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2350 = _T_2144 & _T_1879; // @[el2_lsu_bus_buffer.scala 463:52]
|
|
wire _T_2352 = _T_2350 & _T_1856; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2353 = _T_2346 | _T_2352; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2354 = _T_2333 & _T_2353; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2356 = _T_2354 | buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2370 = _T_2343 & _T_1865; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2371 = _T_4476 | _T_2370; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2377 = _T_2350 & _T_1867; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2378 = _T_2371 | _T_2377; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2379 = _T_2333 & _T_2378; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2381 = _T_2379 | buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2395 = _T_2343 & _T_1876; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2396 = _T_4481 | _T_2395; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2402 = _T_2350 & _T_1878; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2403 = _T_2396 | _T_2402; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2404 = _T_2333 & _T_2403; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2406 = _T_2404 | buf_age_2[2]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2420 = _T_2343 & _T_1887; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2421 = _T_4486 | _T_2420; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2427 = _T_2350 & _T_1889; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2428 = _T_2421 | _T_2427; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2429 = _T_2333 & _T_2428; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2431 = _T_2429 | buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58]
|
|
wire _T_4114 = 2'h3 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 498:117]
|
|
wire _T_4115 = _T_3534 & _T_4114; // @[el2_lsu_bus_buffer.scala 498:112]
|
|
wire _T_4117 = 2'h3 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 498:166]
|
|
wire _T_4118 = _T_3537 & _T_4117; // @[el2_lsu_bus_buffer.scala 498:161]
|
|
wire _T_4119 = _T_4115 | _T_4118; // @[el2_lsu_bus_buffer.scala 498:132]
|
|
wire _T_4120 = _T_853 & _T_4119; // @[el2_lsu_bus_buffer.scala 498:63]
|
|
wire _T_4121 = 2'h3 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 498:206]
|
|
wire _T_4122 = ibuf_drain_vld & _T_4121; // @[el2_lsu_bus_buffer.scala 498:201]
|
|
wire _T_4123 = _T_4120 | _T_4122; // @[el2_lsu_bus_buffer.scala 498:183]
|
|
wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire _T_4213 = io_lsu_axi_bid == 3'h3; // @[el2_lsu_bus_buffer.scala 523:73]
|
|
wire _T_4214 = bus_rsp_write & _T_4213; // @[el2_lsu_bus_buffer.scala 523:52]
|
|
wire _T_4215 = io_lsu_axi_rid == 3'h3; // @[el2_lsu_bus_buffer.scala 524:46]
|
|
wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_3}; // @[el2_lsu_bus_buffer.scala 525:47]
|
|
wire _T_4217 = io_lsu_axi_rid == _GEN_380; // @[el2_lsu_bus_buffer.scala 525:47]
|
|
wire _T_4218 = buf_ldfwd[3] & _T_4217; // @[el2_lsu_bus_buffer.scala 525:27]
|
|
wire _T_4219 = _T_4215 | _T_4218; // @[el2_lsu_bus_buffer.scala 524:77]
|
|
wire _T_4220 = buf_dual_3 & buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 526:26]
|
|
wire _T_4222 = ~buf_write[3]; // @[el2_lsu_bus_buffer.scala 526:44]
|
|
wire _T_4223 = _T_4220 & _T_4222; // @[el2_lsu_bus_buffer.scala 526:42]
|
|
wire _T_4224 = _T_4223 & buf_samedw_3; // @[el2_lsu_bus_buffer.scala 526:58]
|
|
reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_3}; // @[el2_lsu_bus_buffer.scala 526:94]
|
|
wire _T_4225 = io_lsu_axi_rid == _GEN_381; // @[el2_lsu_bus_buffer.scala 526:94]
|
|
wire _T_4226 = _T_4224 & _T_4225; // @[el2_lsu_bus_buffer.scala 526:74]
|
|
wire _T_4227 = _T_4219 | _T_4226; // @[el2_lsu_bus_buffer.scala 525:71]
|
|
wire _T_4228 = bus_rsp_read & _T_4227; // @[el2_lsu_bus_buffer.scala 524:25]
|
|
wire _T_4229 = _T_4214 | _T_4228; // @[el2_lsu_bus_buffer.scala 523:105]
|
|
wire _GEN_270 = _T_4168 & _T_4229; // @[Conditional.scala 39:67]
|
|
wire _GEN_289 = _T_4134 ? 1'h0 : _GEN_270; // @[Conditional.scala 39:67]
|
|
wire _GEN_301 = _T_4130 ? 1'h0 : _GEN_289; // @[Conditional.scala 39:67]
|
|
wire buf_resp_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_301; // @[Conditional.scala 40:58]
|
|
wire _T_4255 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[el2_lsu_bus_buffer.scala 538:21]
|
|
wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire [2:0] _GEN_383 = {{1'd0}, _GEN_253}; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire _T_4267 = io_lsu_axi_rid == _GEN_383; // @[el2_lsu_bus_buffer.scala 538:58]
|
|
wire _T_4268 = _T_4265[0] & _T_4267; // @[el2_lsu_bus_buffer.scala 538:38]
|
|
wire _T_4269 = _T_4225 | _T_4268; // @[el2_lsu_bus_buffer.scala 537:95]
|
|
wire _T_4270 = bus_rsp_read & _T_4269; // @[el2_lsu_bus_buffer.scala 537:45]
|
|
wire _GEN_264 = _T_4255 & _T_4270; // @[Conditional.scala 39:67]
|
|
wire _GEN_271 = _T_4168 ? buf_resp_state_bus_en_3 : _GEN_264; // @[Conditional.scala 39:67]
|
|
wire _GEN_281 = _T_4134 ? buf_cmd_state_bus_en_3 : _GEN_271; // @[Conditional.scala 39:67]
|
|
wire _GEN_294 = _T_4130 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67]
|
|
wire buf_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_294; // @[Conditional.scala 40:58]
|
|
wire _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 511:49]
|
|
wire _T_4148 = _T_4147 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 511:70]
|
|
wire _T_4273 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire _T_4276 = RspPtr == 2'h3; // @[el2_lsu_bus_buffer.scala 543:37]
|
|
wire _T_4277 = buf_dualtag_3 == RspPtr; // @[el2_lsu_bus_buffer.scala 543:98]
|
|
wire _T_4278 = buf_dual_3 & _T_4277; // @[el2_lsu_bus_buffer.scala 543:80]
|
|
wire _T_4279 = _T_4276 | _T_4278; // @[el2_lsu_bus_buffer.scala 543:65]
|
|
wire _T_4280 = _T_4279 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 543:112]
|
|
wire _T_4281 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire _GEN_259 = _T_4273 ? _T_4280 : _T_4281; // @[Conditional.scala 39:67]
|
|
wire _GEN_265 = _T_4255 ? _T_4148 : _GEN_259; // @[Conditional.scala 39:67]
|
|
wire _GEN_272 = _T_4168 ? _T_4148 : _GEN_265; // @[Conditional.scala 39:67]
|
|
wire _GEN_282 = _T_4134 ? _T_4148 : _GEN_272; // @[Conditional.scala 39:67]
|
|
wire _GEN_292 = _T_4130 ? _T_3554 : _GEN_282; // @[Conditional.scala 39:67]
|
|
wire buf_state_en_3 = _T_4107 ? _T_4123 : _GEN_292; // @[Conditional.scala 40:58]
|
|
wire _T_2435 = _T_1886 & buf_state_en_3; // @[el2_lsu_bus_buffer.scala 460:94]
|
|
wire _T_2445 = _T_2137 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:71]
|
|
wire _T_2447 = _T_2445 & _T_1854; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2448 = _T_4471 | _T_2447; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2452 = _T_2144 & _T_1890; // @[el2_lsu_bus_buffer.scala 463:52]
|
|
wire _T_2454 = _T_2452 & _T_1856; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2455 = _T_2448 | _T_2454; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2456 = _T_2435 & _T_2455; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2458 = _T_2456 | buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2472 = _T_2445 & _T_1865; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2473 = _T_4476 | _T_2472; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2479 = _T_2452 & _T_1867; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2480 = _T_2473 | _T_2479; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2481 = _T_2435 & _T_2480; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2483 = _T_2481 | buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2497 = _T_2445 & _T_1876; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2498 = _T_4481 | _T_2497; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2504 = _T_2452 & _T_1878; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2505 = _T_2498 | _T_2504; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2506 = _T_2435 & _T_2505; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2508 = _T_2506 | buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire _T_2522 = _T_2445 & _T_1887; // @[el2_lsu_bus_buffer.scala 462:92]
|
|
wire _T_2523 = _T_4486 | _T_2522; // @[el2_lsu_bus_buffer.scala 461:86]
|
|
wire _T_2529 = _T_2452 & _T_1889; // @[el2_lsu_bus_buffer.scala 463:73]
|
|
wire _T_2530 = _T_2523 | _T_2529; // @[el2_lsu_bus_buffer.scala 462:114]
|
|
wire _T_2531 = _T_2435 & _T_2530; // @[el2_lsu_bus_buffer.scala 460:113]
|
|
wire _T_2533 = _T_2531 | buf_age_3[3]; // @[el2_lsu_bus_buffer.scala 463:97]
|
|
wire [2:0] _T_2535 = {_T_2533,_T_2508,_T_2483}; // @[Cat.scala 29:58]
|
|
wire _T_2799 = buf_state_0 == 3'h6; // @[el2_lsu_bus_buffer.scala 471:47]
|
|
wire _T_2800 = _T_1853 | _T_2799; // @[el2_lsu_bus_buffer.scala 471:32]
|
|
wire _T_2801 = ~_T_2800; // @[el2_lsu_bus_buffer.scala 471:6]
|
|
wire _T_2809 = _T_2801 | _T_2141; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_2816 = _T_2809 | _T_2148; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_2817 = _T_2129 & _T_2816; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_2821 = buf_state_1 == 3'h6; // @[el2_lsu_bus_buffer.scala 471:47]
|
|
wire _T_2822 = _T_1864 | _T_2821; // @[el2_lsu_bus_buffer.scala 471:32]
|
|
wire _T_2823 = ~_T_2822; // @[el2_lsu_bus_buffer.scala 471:6]
|
|
wire _T_2831 = _T_2823 | _T_2166; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_2838 = _T_2831 | _T_2173; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_2839 = _T_2129 & _T_2838; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_2843 = buf_state_2 == 3'h6; // @[el2_lsu_bus_buffer.scala 471:47]
|
|
wire _T_2844 = _T_1875 | _T_2843; // @[el2_lsu_bus_buffer.scala 471:32]
|
|
wire _T_2845 = ~_T_2844; // @[el2_lsu_bus_buffer.scala 471:6]
|
|
wire _T_2853 = _T_2845 | _T_2191; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_2860 = _T_2853 | _T_2198; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_2861 = _T_2129 & _T_2860; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_2865 = buf_state_3 == 3'h6; // @[el2_lsu_bus_buffer.scala 471:47]
|
|
wire _T_2866 = _T_1886 | _T_2865; // @[el2_lsu_bus_buffer.scala 471:32]
|
|
wire _T_2867 = ~_T_2866; // @[el2_lsu_bus_buffer.scala 471:6]
|
|
wire _T_2875 = _T_2867 | _T_2216; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_2882 = _T_2875 | _T_2223; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_2883 = _T_2129 & _T_2882; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire [3:0] buf_rspage_set_0 = {_T_2883,_T_2861,_T_2839,_T_2817}; // @[Cat.scala 29:58]
|
|
wire _T_2900 = _T_2801 | _T_2243; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_2907 = _T_2900 | _T_2250; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_2908 = _T_2231 & _T_2907; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_2922 = _T_2823 | _T_2268; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_2929 = _T_2922 | _T_2275; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_2930 = _T_2231 & _T_2929; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_2944 = _T_2845 | _T_2293; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_2951 = _T_2944 | _T_2300; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_2952 = _T_2231 & _T_2951; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_2966 = _T_2867 | _T_2318; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_2973 = _T_2966 | _T_2325; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_2974 = _T_2231 & _T_2973; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire [3:0] buf_rspage_set_1 = {_T_2974,_T_2952,_T_2930,_T_2908}; // @[Cat.scala 29:58]
|
|
wire _T_2991 = _T_2801 | _T_2345; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_2998 = _T_2991 | _T_2352; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_2999 = _T_2333 & _T_2998; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_3013 = _T_2823 | _T_2370; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_3020 = _T_3013 | _T_2377; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_3021 = _T_2333 & _T_3020; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_3035 = _T_2845 | _T_2395; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_3042 = _T_3035 | _T_2402; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_3043 = _T_2333 & _T_3042; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_3057 = _T_2867 | _T_2420; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_3064 = _T_3057 | _T_2427; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_3065 = _T_2333 & _T_3064; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire [3:0] buf_rspage_set_2 = {_T_3065,_T_3043,_T_3021,_T_2999}; // @[Cat.scala 29:58]
|
|
wire _T_3082 = _T_2801 | _T_2447; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_3089 = _T_3082 | _T_2454; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_3090 = _T_2435 & _T_3089; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_3104 = _T_2823 | _T_2472; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_3111 = _T_3104 | _T_2479; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_3112 = _T_2435 & _T_3111; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_3126 = _T_2845 | _T_2497; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_3133 = _T_3126 | _T_2504; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_3134 = _T_2435 & _T_3133; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire _T_3148 = _T_2867 | _T_2522; // @[el2_lsu_bus_buffer.scala 471:59]
|
|
wire _T_3155 = _T_3148 | _T_2529; // @[el2_lsu_bus_buffer.scala 472:110]
|
|
wire _T_3156 = _T_2435 & _T_3155; // @[el2_lsu_bus_buffer.scala 470:112]
|
|
wire [3:0] buf_rspage_set_3 = {_T_3156,_T_3134,_T_3112,_T_3090}; // @[Cat.scala 29:58]
|
|
wire _T_3241 = _T_2865 | _T_1886; // @[el2_lsu_bus_buffer.scala 475:110]
|
|
wire _T_3242 = ~_T_3241; // @[el2_lsu_bus_buffer.scala 475:84]
|
|
wire _T_3243 = buf_rspageQ_0[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3235 = _T_2843 | _T_1875; // @[el2_lsu_bus_buffer.scala 475:110]
|
|
wire _T_3236 = ~_T_3235; // @[el2_lsu_bus_buffer.scala 475:84]
|
|
wire _T_3237 = buf_rspageQ_0[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3229 = _T_2821 | _T_1864; // @[el2_lsu_bus_buffer.scala 475:110]
|
|
wire _T_3230 = ~_T_3229; // @[el2_lsu_bus_buffer.scala 475:84]
|
|
wire _T_3231 = buf_rspageQ_0[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3223 = _T_2799 | _T_1853; // @[el2_lsu_bus_buffer.scala 475:110]
|
|
wire _T_3224 = ~_T_3223; // @[el2_lsu_bus_buffer.scala 475:84]
|
|
wire _T_3225 = buf_rspageQ_0[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire [3:0] buf_rspage_0 = {_T_3243,_T_3237,_T_3231,_T_3225}; // @[Cat.scala 29:58]
|
|
wire _T_3162 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3165 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3168 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3171 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire [2:0] _T_3173 = {_T_3171,_T_3168,_T_3165}; // @[Cat.scala 29:58]
|
|
wire _T_3270 = buf_rspageQ_1[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3264 = buf_rspageQ_1[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3258 = buf_rspageQ_1[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3252 = buf_rspageQ_1[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire [3:0] buf_rspage_1 = {_T_3270,_T_3264,_T_3258,_T_3252}; // @[Cat.scala 29:58]
|
|
wire _T_3177 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3180 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3183 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3186 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire [2:0] _T_3188 = {_T_3186,_T_3183,_T_3180}; // @[Cat.scala 29:58]
|
|
wire _T_3297 = buf_rspageQ_2[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3291 = buf_rspageQ_2[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3285 = buf_rspageQ_2[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3279 = buf_rspageQ_2[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire [3:0] buf_rspage_2 = {_T_3297,_T_3291,_T_3285,_T_3279}; // @[Cat.scala 29:58]
|
|
wire _T_3192 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3195 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3198 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3201 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire [2:0] _T_3203 = {_T_3201,_T_3198,_T_3195}; // @[Cat.scala 29:58]
|
|
wire _T_3324 = buf_rspageQ_3[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3318 = buf_rspageQ_3[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3312 = buf_rspageQ_3[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire _T_3306 = buf_rspageQ_3[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 475:82]
|
|
wire [3:0] buf_rspage_3 = {_T_3324,_T_3318,_T_3312,_T_3306}; // @[Cat.scala 29:58]
|
|
wire _T_3207 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3210 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[el2_lsu_bus_buffer.scala 474:88]
|
|
wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58]
|
|
wire _T_3329 = ibuf_drain_vld & _T_1854; // @[el2_lsu_bus_buffer.scala 480:63]
|
|
wire _T_3331 = ibuf_drain_vld & _T_1865; // @[el2_lsu_bus_buffer.scala 480:63]
|
|
wire _T_3333 = ibuf_drain_vld & _T_1876; // @[el2_lsu_bus_buffer.scala 480:63]
|
|
wire _T_3335 = ibuf_drain_vld & _T_1887; // @[el2_lsu_bus_buffer.scala 480:63]
|
|
wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58]
|
|
wire _T_3343 = _T_3537 & _T_1857; // @[el2_lsu_bus_buffer.scala 482:35]
|
|
wire _T_3352 = _T_3537 & _T_1868; // @[el2_lsu_bus_buffer.scala 482:35]
|
|
wire _T_3361 = _T_3537 & _T_1879; // @[el2_lsu_bus_buffer.scala 482:35]
|
|
wire _T_3370 = _T_3537 & _T_1890; // @[el2_lsu_bus_buffer.scala 482:35]
|
|
wire _T_3400 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 484:45]
|
|
wire _T_3402 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 484:45]
|
|
wire _T_3404 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 484:45]
|
|
wire _T_3406 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 484:45]
|
|
wire [3:0] buf_dual_in = {_T_3406,_T_3404,_T_3402,_T_3400}; // @[Cat.scala 29:58]
|
|
wire _T_3411 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 485:47]
|
|
wire _T_3413 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 485:47]
|
|
wire _T_3415 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 485:47]
|
|
wire _T_3417 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 485:47]
|
|
wire [3:0] buf_samedw_in = {_T_3417,_T_3415,_T_3413,_T_3411}; // @[Cat.scala 29:58]
|
|
wire _T_3422 = ibuf_nomerge | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 486:84]
|
|
wire _T_3423 = ibuf_drainvec_vld[0] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 486:48]
|
|
wire _T_3426 = ibuf_drainvec_vld[1] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 486:48]
|
|
wire _T_3429 = ibuf_drainvec_vld[2] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 486:48]
|
|
wire _T_3432 = ibuf_drainvec_vld[3] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 486:48]
|
|
wire [3:0] buf_nomerge_in = {_T_3432,_T_3429,_T_3426,_T_3423}; // @[Cat.scala 29:58]
|
|
wire _T_3440 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3343; // @[el2_lsu_bus_buffer.scala 487:47]
|
|
wire _T_3445 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3352; // @[el2_lsu_bus_buffer.scala 487:47]
|
|
wire _T_3450 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3361; // @[el2_lsu_bus_buffer.scala 487:47]
|
|
wire _T_3455 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3370; // @[el2_lsu_bus_buffer.scala 487:47]
|
|
wire [3:0] buf_dualhi_in = {_T_3455,_T_3450,_T_3445,_T_3440}; // @[Cat.scala 29:58]
|
|
wire _T_3484 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 489:51]
|
|
wire _T_3486 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 489:51]
|
|
wire _T_3488 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 489:51]
|
|
wire _T_3490 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 489:51]
|
|
wire [3:0] buf_sideeffect_in = {_T_3490,_T_3488,_T_3486,_T_3484}; // @[Cat.scala 29:58]
|
|
wire _T_3495 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_buffer.scala 490:47]
|
|
wire _T_3497 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_buffer.scala 490:47]
|
|
wire _T_3499 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_buffer.scala 490:47]
|
|
wire _T_3501 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_buffer.scala 490:47]
|
|
wire [3:0] buf_unsign_in = {_T_3501,_T_3499,_T_3497,_T_3495}; // @[Cat.scala 29:58]
|
|
wire _T_3518 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 492:46]
|
|
wire _T_3520 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 492:46]
|
|
wire _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 492:46]
|
|
wire _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 492:46]
|
|
wire [3:0] buf_write_in = {_T_3524,_T_3522,_T_3520,_T_3518}; // @[Cat.scala 29:58]
|
|
wire _T_3557 = obuf_nosend & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 508:89]
|
|
wire _T_3559 = _T_3557 & _T_1351; // @[el2_lsu_bus_buffer.scala 508:104]
|
|
wire _T_3572 = buf_state_en_0 & _T_3643; // @[el2_lsu_bus_buffer.scala 513:44]
|
|
wire _T_3573 = _T_3572 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 513:60]
|
|
wire _T_3575 = _T_3573 & _T_1333; // @[el2_lsu_bus_buffer.scala 513:74]
|
|
wire _T_3578 = _T_3568 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 515:67]
|
|
wire _T_3579 = _T_3578 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 515:81]
|
|
wire _T_4869 = io_lsu_axi_bresp != 2'h0; // @[el2_lsu_bus_buffer.scala 619:58]
|
|
wire bus_rsp_read_error = bus_rsp_read & _T_4869; // @[el2_lsu_bus_buffer.scala 619:38]
|
|
wire _T_3582 = _T_3578 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 516:82]
|
|
wire _T_3657 = bus_rsp_read_error & _T_3636; // @[el2_lsu_bus_buffer.scala 530:91]
|
|
wire _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[el2_lsu_bus_buffer.scala 531:31]
|
|
wire _T_3661 = _T_3659 & _T_3638; // @[el2_lsu_bus_buffer.scala 531:46]
|
|
wire _T_3662 = _T_3657 | _T_3661; // @[el2_lsu_bus_buffer.scala 530:143]
|
|
wire bus_rsp_write_error = bus_rsp_write & _T_4869; // @[el2_lsu_bus_buffer.scala 618:40]
|
|
wire _T_3665 = bus_rsp_write_error & _T_3634; // @[el2_lsu_bus_buffer.scala 532:53]
|
|
wire _T_3666 = _T_3662 | _T_3665; // @[el2_lsu_bus_buffer.scala 531:88]
|
|
wire _T_3667 = _T_3568 & _T_3666; // @[el2_lsu_bus_buffer.scala 530:68]
|
|
wire _GEN_46 = _T_3589 & _T_3667; // @[Conditional.scala 39:67]
|
|
wire _GEN_59 = _T_3555 ? _T_3582 : _GEN_46; // @[Conditional.scala 39:67]
|
|
wire _GEN_71 = _T_3551 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
|
|
wire buf_error_en_0 = _T_3528 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58]
|
|
wire _T_3592 = ~bus_rsp_write_error; // @[el2_lsu_bus_buffer.scala 520:73]
|
|
wire _T_3593 = buf_write[0] & _T_3592; // @[el2_lsu_bus_buffer.scala 520:71]
|
|
wire _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[el2_lsu_bus_buffer.scala 520:55]
|
|
wire _T_3596 = ~buf_samedw_0; // @[el2_lsu_bus_buffer.scala 521:30]
|
|
wire _T_3597 = buf_dual_0 & _T_3596; // @[el2_lsu_bus_buffer.scala 521:28]
|
|
wire _T_3600 = _T_3597 & _T_3643; // @[el2_lsu_bus_buffer.scala 521:45]
|
|
wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire _T_3601 = _GEN_21 != 3'h4; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire _T_3602 = _T_3600 & _T_3601; // @[el2_lsu_bus_buffer.scala 521:61]
|
|
wire _T_4494 = _T_2746 | _T_2743; // @[el2_lsu_bus_buffer.scala 579:93]
|
|
wire _T_4495 = _T_4494 | _T_2740; // @[el2_lsu_bus_buffer.scala 579:93]
|
|
wire any_done_wait_state = _T_4495 | _T_2737; // @[el2_lsu_bus_buffer.scala 579:93]
|
|
wire _T_3604 = buf_ldfwd[0] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:31]
|
|
wire _T_3610 = buf_dualtag_0 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_3612 = buf_dualtag_0 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_3614 = buf_dualtag_0 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_3616 = buf_dualtag_0 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_3618 = _T_3610 & buf_ldfwd[0]; // @[Mux.scala 27:72]
|
|
wire _T_3619 = _T_3612 & buf_ldfwd[1]; // @[Mux.scala 27:72]
|
|
wire _T_3620 = _T_3614 & buf_ldfwd[2]; // @[Mux.scala 27:72]
|
|
wire _T_3621 = _T_3616 & buf_ldfwd[3]; // @[Mux.scala 27:72]
|
|
wire _T_3622 = _T_3618 | _T_3619; // @[Mux.scala 27:72]
|
|
wire _T_3623 = _T_3622 | _T_3620; // @[Mux.scala 27:72]
|
|
wire _T_3624 = _T_3623 | _T_3621; // @[Mux.scala 27:72]
|
|
wire _T_3626 = _T_3600 & _T_3624; // @[el2_lsu_bus_buffer.scala 522:101]
|
|
wire _T_3627 = _GEN_21 == 3'h4; // @[el2_lsu_bus_buffer.scala 522:167]
|
|
wire _T_3628 = _T_3626 & _T_3627; // @[el2_lsu_bus_buffer.scala 522:138]
|
|
wire _T_3629 = _T_3628 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:187]
|
|
wire _T_3630 = _T_3604 | _T_3629; // @[el2_lsu_bus_buffer.scala 522:53]
|
|
wire _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 529:47]
|
|
wire _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 529:62]
|
|
wire _T_3668 = ~buf_error_en_0; // @[el2_lsu_bus_buffer.scala 533:50]
|
|
wire _T_3669 = buf_state_en_0 & _T_3668; // @[el2_lsu_bus_buffer.scala 533:48]
|
|
wire _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[el2_lsu_bus_buffer.scala 536:90]
|
|
wire _T_3682 = _T_3681 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 536:118]
|
|
wire _GEN_29 = _T_3702 & buf_state_en_0; // @[Conditional.scala 39:67]
|
|
wire _GEN_32 = _T_3694 ? 1'h0 : _T_3702; // @[Conditional.scala 39:67]
|
|
wire _GEN_34 = _T_3694 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
|
|
wire _GEN_38 = _T_3676 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
|
|
wire _GEN_40 = _T_3676 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67]
|
|
wire _GEN_45 = _T_3589 & _T_3654; // @[Conditional.scala 39:67]
|
|
wire _GEN_48 = _T_3589 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
|
|
wire _GEN_50 = _T_3589 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67]
|
|
wire _GEN_56 = _T_3555 ? _T_3575 : _GEN_50; // @[Conditional.scala 39:67]
|
|
wire _GEN_58 = _T_3555 ? _T_3579 : _GEN_45; // @[Conditional.scala 39:67]
|
|
wire _GEN_62 = _T_3555 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67]
|
|
wire _GEN_68 = _T_3551 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67]
|
|
wire _GEN_70 = _T_3551 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67]
|
|
wire _GEN_74 = _T_3551 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
|
|
wire buf_wr_en_0 = _T_3528 & buf_state_en_0; // @[Conditional.scala 40:58]
|
|
wire buf_ldfwd_en_0 = _T_3528 ? 1'h0 : _GEN_68; // @[Conditional.scala 40:58]
|
|
wire buf_rst_0 = _T_3528 ? 1'h0 : _GEN_74; // @[Conditional.scala 40:58]
|
|
wire _T_3765 = buf_state_en_1 & _T_3836; // @[el2_lsu_bus_buffer.scala 513:44]
|
|
wire _T_3766 = _T_3765 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 513:60]
|
|
wire _T_3768 = _T_3766 & _T_1333; // @[el2_lsu_bus_buffer.scala 513:74]
|
|
wire _T_3771 = _T_3761 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 515:67]
|
|
wire _T_3772 = _T_3771 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 515:81]
|
|
wire _T_3775 = _T_3771 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 516:82]
|
|
wire _T_3850 = bus_rsp_read_error & _T_3829; // @[el2_lsu_bus_buffer.scala 530:91]
|
|
wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[el2_lsu_bus_buffer.scala 531:31]
|
|
wire _T_3854 = _T_3852 & _T_3831; // @[el2_lsu_bus_buffer.scala 531:46]
|
|
wire _T_3855 = _T_3850 | _T_3854; // @[el2_lsu_bus_buffer.scala 530:143]
|
|
wire _T_3858 = bus_rsp_write_error & _T_3827; // @[el2_lsu_bus_buffer.scala 532:53]
|
|
wire _T_3859 = _T_3855 | _T_3858; // @[el2_lsu_bus_buffer.scala 531:88]
|
|
wire _T_3860 = _T_3761 & _T_3859; // @[el2_lsu_bus_buffer.scala 530:68]
|
|
wire _GEN_122 = _T_3782 & _T_3860; // @[Conditional.scala 39:67]
|
|
wire _GEN_135 = _T_3748 ? _T_3775 : _GEN_122; // @[Conditional.scala 39:67]
|
|
wire _GEN_147 = _T_3744 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67]
|
|
wire buf_error_en_1 = _T_3721 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58]
|
|
wire _T_3786 = buf_write[1] & _T_3592; // @[el2_lsu_bus_buffer.scala 520:71]
|
|
wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[el2_lsu_bus_buffer.scala 520:55]
|
|
wire _T_3789 = ~buf_samedw_1; // @[el2_lsu_bus_buffer.scala 521:30]
|
|
wire _T_3790 = buf_dual_1 & _T_3789; // @[el2_lsu_bus_buffer.scala 521:28]
|
|
wire _T_3793 = _T_3790 & _T_3836; // @[el2_lsu_bus_buffer.scala 521:45]
|
|
wire [2:0] _GEN_95 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire [2:0] _GEN_96 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_95; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire [2:0] _GEN_97 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_96; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire _T_3794 = _GEN_97 != 3'h4; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire _T_3795 = _T_3793 & _T_3794; // @[el2_lsu_bus_buffer.scala 521:61]
|
|
wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:31]
|
|
wire _T_3803 = buf_dualtag_1 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_3805 = buf_dualtag_1 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_3807 = buf_dualtag_1 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_3809 = buf_dualtag_1 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72]
|
|
wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72]
|
|
wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72]
|
|
wire _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72]
|
|
wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72]
|
|
wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72]
|
|
wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72]
|
|
wire _T_3819 = _T_3793 & _T_3817; // @[el2_lsu_bus_buffer.scala 522:101]
|
|
wire _T_3820 = _GEN_97 == 3'h4; // @[el2_lsu_bus_buffer.scala 522:167]
|
|
wire _T_3821 = _T_3819 & _T_3820; // @[el2_lsu_bus_buffer.scala 522:138]
|
|
wire _T_3822 = _T_3821 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:187]
|
|
wire _T_3823 = _T_3797 | _T_3822; // @[el2_lsu_bus_buffer.scala 522:53]
|
|
wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 529:47]
|
|
wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 529:62]
|
|
wire _T_3861 = ~buf_error_en_1; // @[el2_lsu_bus_buffer.scala 533:50]
|
|
wire _T_3862 = buf_state_en_1 & _T_3861; // @[el2_lsu_bus_buffer.scala 533:48]
|
|
wire _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[el2_lsu_bus_buffer.scala 536:90]
|
|
wire _T_3875 = _T_3874 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 536:118]
|
|
wire _GEN_105 = _T_3895 & buf_state_en_1; // @[Conditional.scala 39:67]
|
|
wire _GEN_108 = _T_3887 ? 1'h0 : _T_3895; // @[Conditional.scala 39:67]
|
|
wire _GEN_110 = _T_3887 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67]
|
|
wire _GEN_114 = _T_3869 ? 1'h0 : _GEN_108; // @[Conditional.scala 39:67]
|
|
wire _GEN_116 = _T_3869 ? 1'h0 : _GEN_110; // @[Conditional.scala 39:67]
|
|
wire _GEN_121 = _T_3782 & _T_3847; // @[Conditional.scala 39:67]
|
|
wire _GEN_124 = _T_3782 ? 1'h0 : _GEN_114; // @[Conditional.scala 39:67]
|
|
wire _GEN_126 = _T_3782 ? 1'h0 : _GEN_116; // @[Conditional.scala 39:67]
|
|
wire _GEN_132 = _T_3748 ? _T_3768 : _GEN_126; // @[Conditional.scala 39:67]
|
|
wire _GEN_134 = _T_3748 ? _T_3772 : _GEN_121; // @[Conditional.scala 39:67]
|
|
wire _GEN_138 = _T_3748 ? 1'h0 : _GEN_124; // @[Conditional.scala 39:67]
|
|
wire _GEN_144 = _T_3744 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67]
|
|
wire _GEN_146 = _T_3744 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67]
|
|
wire _GEN_150 = _T_3744 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67]
|
|
wire buf_wr_en_1 = _T_3721 & buf_state_en_1; // @[Conditional.scala 40:58]
|
|
wire buf_ldfwd_en_1 = _T_3721 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58]
|
|
wire buf_rst_1 = _T_3721 ? 1'h0 : _GEN_150; // @[Conditional.scala 40:58]
|
|
wire _T_3958 = buf_state_en_2 & _T_4029; // @[el2_lsu_bus_buffer.scala 513:44]
|
|
wire _T_3959 = _T_3958 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 513:60]
|
|
wire _T_3961 = _T_3959 & _T_1333; // @[el2_lsu_bus_buffer.scala 513:74]
|
|
wire _T_3964 = _T_3954 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 515:67]
|
|
wire _T_3965 = _T_3964 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 515:81]
|
|
wire _T_3968 = _T_3964 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 516:82]
|
|
wire _T_4043 = bus_rsp_read_error & _T_4022; // @[el2_lsu_bus_buffer.scala 530:91]
|
|
wire _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[el2_lsu_bus_buffer.scala 531:31]
|
|
wire _T_4047 = _T_4045 & _T_4024; // @[el2_lsu_bus_buffer.scala 531:46]
|
|
wire _T_4048 = _T_4043 | _T_4047; // @[el2_lsu_bus_buffer.scala 530:143]
|
|
wire _T_4051 = bus_rsp_write_error & _T_4020; // @[el2_lsu_bus_buffer.scala 532:53]
|
|
wire _T_4052 = _T_4048 | _T_4051; // @[el2_lsu_bus_buffer.scala 531:88]
|
|
wire _T_4053 = _T_3954 & _T_4052; // @[el2_lsu_bus_buffer.scala 530:68]
|
|
wire _GEN_198 = _T_3975 & _T_4053; // @[Conditional.scala 39:67]
|
|
wire _GEN_211 = _T_3941 ? _T_3968 : _GEN_198; // @[Conditional.scala 39:67]
|
|
wire _GEN_223 = _T_3937 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67]
|
|
wire buf_error_en_2 = _T_3914 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58]
|
|
wire _T_3979 = buf_write[2] & _T_3592; // @[el2_lsu_bus_buffer.scala 520:71]
|
|
wire _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[el2_lsu_bus_buffer.scala 520:55]
|
|
wire _T_3982 = ~buf_samedw_2; // @[el2_lsu_bus_buffer.scala 521:30]
|
|
wire _T_3983 = buf_dual_2 & _T_3982; // @[el2_lsu_bus_buffer.scala 521:28]
|
|
wire _T_3986 = _T_3983 & _T_4029; // @[el2_lsu_bus_buffer.scala 521:45]
|
|
wire [2:0] _GEN_171 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire [2:0] _GEN_172 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_171; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire [2:0] _GEN_173 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_172; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire _T_3987 = _GEN_173 != 3'h4; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire _T_3988 = _T_3986 & _T_3987; // @[el2_lsu_bus_buffer.scala 521:61]
|
|
wire _T_3990 = buf_ldfwd[2] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:31]
|
|
wire _T_3996 = buf_dualtag_2 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_3998 = buf_dualtag_2 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_4000 = buf_dualtag_2 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_4002 = buf_dualtag_2 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_4004 = _T_3996 & buf_ldfwd[0]; // @[Mux.scala 27:72]
|
|
wire _T_4005 = _T_3998 & buf_ldfwd[1]; // @[Mux.scala 27:72]
|
|
wire _T_4006 = _T_4000 & buf_ldfwd[2]; // @[Mux.scala 27:72]
|
|
wire _T_4007 = _T_4002 & buf_ldfwd[3]; // @[Mux.scala 27:72]
|
|
wire _T_4008 = _T_4004 | _T_4005; // @[Mux.scala 27:72]
|
|
wire _T_4009 = _T_4008 | _T_4006; // @[Mux.scala 27:72]
|
|
wire _T_4010 = _T_4009 | _T_4007; // @[Mux.scala 27:72]
|
|
wire _T_4012 = _T_3986 & _T_4010; // @[el2_lsu_bus_buffer.scala 522:101]
|
|
wire _T_4013 = _GEN_173 == 3'h4; // @[el2_lsu_bus_buffer.scala 522:167]
|
|
wire _T_4014 = _T_4012 & _T_4013; // @[el2_lsu_bus_buffer.scala 522:138]
|
|
wire _T_4015 = _T_4014 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:187]
|
|
wire _T_4016 = _T_3990 | _T_4015; // @[el2_lsu_bus_buffer.scala 522:53]
|
|
wire _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 529:47]
|
|
wire _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 529:62]
|
|
wire _T_4054 = ~buf_error_en_2; // @[el2_lsu_bus_buffer.scala 533:50]
|
|
wire _T_4055 = buf_state_en_2 & _T_4054; // @[el2_lsu_bus_buffer.scala 533:48]
|
|
wire _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[el2_lsu_bus_buffer.scala 536:90]
|
|
wire _T_4068 = _T_4067 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 536:118]
|
|
wire _GEN_181 = _T_4088 & buf_state_en_2; // @[Conditional.scala 39:67]
|
|
wire _GEN_184 = _T_4080 ? 1'h0 : _T_4088; // @[Conditional.scala 39:67]
|
|
wire _GEN_186 = _T_4080 ? 1'h0 : _GEN_181; // @[Conditional.scala 39:67]
|
|
wire _GEN_190 = _T_4062 ? 1'h0 : _GEN_184; // @[Conditional.scala 39:67]
|
|
wire _GEN_192 = _T_4062 ? 1'h0 : _GEN_186; // @[Conditional.scala 39:67]
|
|
wire _GEN_197 = _T_3975 & _T_4040; // @[Conditional.scala 39:67]
|
|
wire _GEN_200 = _T_3975 ? 1'h0 : _GEN_190; // @[Conditional.scala 39:67]
|
|
wire _GEN_202 = _T_3975 ? 1'h0 : _GEN_192; // @[Conditional.scala 39:67]
|
|
wire _GEN_208 = _T_3941 ? _T_3961 : _GEN_202; // @[Conditional.scala 39:67]
|
|
wire _GEN_210 = _T_3941 ? _T_3965 : _GEN_197; // @[Conditional.scala 39:67]
|
|
wire _GEN_214 = _T_3941 ? 1'h0 : _GEN_200; // @[Conditional.scala 39:67]
|
|
wire _GEN_220 = _T_3937 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67]
|
|
wire _GEN_222 = _T_3937 ? 1'h0 : _GEN_210; // @[Conditional.scala 39:67]
|
|
wire _GEN_226 = _T_3937 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67]
|
|
wire buf_wr_en_2 = _T_3914 & buf_state_en_2; // @[Conditional.scala 40:58]
|
|
wire buf_ldfwd_en_2 = _T_3914 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58]
|
|
wire buf_rst_2 = _T_3914 ? 1'h0 : _GEN_226; // @[Conditional.scala 40:58]
|
|
wire _T_4151 = buf_state_en_3 & _T_4222; // @[el2_lsu_bus_buffer.scala 513:44]
|
|
wire _T_4152 = _T_4151 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 513:60]
|
|
wire _T_4154 = _T_4152 & _T_1333; // @[el2_lsu_bus_buffer.scala 513:74]
|
|
wire _T_4157 = _T_4147 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 515:67]
|
|
wire _T_4158 = _T_4157 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 515:81]
|
|
wire _T_4161 = _T_4157 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 516:82]
|
|
wire _T_4236 = bus_rsp_read_error & _T_4215; // @[el2_lsu_bus_buffer.scala 530:91]
|
|
wire _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[el2_lsu_bus_buffer.scala 531:31]
|
|
wire _T_4240 = _T_4238 & _T_4217; // @[el2_lsu_bus_buffer.scala 531:46]
|
|
wire _T_4241 = _T_4236 | _T_4240; // @[el2_lsu_bus_buffer.scala 530:143]
|
|
wire _T_4244 = bus_rsp_write_error & _T_4213; // @[el2_lsu_bus_buffer.scala 532:53]
|
|
wire _T_4245 = _T_4241 | _T_4244; // @[el2_lsu_bus_buffer.scala 531:88]
|
|
wire _T_4246 = _T_4147 & _T_4245; // @[el2_lsu_bus_buffer.scala 530:68]
|
|
wire _GEN_274 = _T_4168 & _T_4246; // @[Conditional.scala 39:67]
|
|
wire _GEN_287 = _T_4134 ? _T_4161 : _GEN_274; // @[Conditional.scala 39:67]
|
|
wire _GEN_299 = _T_4130 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67]
|
|
wire buf_error_en_3 = _T_4107 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58]
|
|
wire _T_4172 = buf_write[3] & _T_3592; // @[el2_lsu_bus_buffer.scala 520:71]
|
|
wire _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[el2_lsu_bus_buffer.scala 520:55]
|
|
wire _T_4175 = ~buf_samedw_3; // @[el2_lsu_bus_buffer.scala 521:30]
|
|
wire _T_4176 = buf_dual_3 & _T_4175; // @[el2_lsu_bus_buffer.scala 521:28]
|
|
wire _T_4179 = _T_4176 & _T_4222; // @[el2_lsu_bus_buffer.scala 521:45]
|
|
wire [2:0] _GEN_247 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire [2:0] _GEN_248 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_247; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire [2:0] _GEN_249 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_248; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire _T_4180 = _GEN_249 != 3'h4; // @[el2_lsu_bus_buffer.scala 521:90]
|
|
wire _T_4181 = _T_4179 & _T_4180; // @[el2_lsu_bus_buffer.scala 521:61]
|
|
wire _T_4183 = buf_ldfwd[3] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:31]
|
|
wire _T_4189 = buf_dualtag_3 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_4191 = buf_dualtag_3 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_4193 = buf_dualtag_3 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_4195 = buf_dualtag_3 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118]
|
|
wire _T_4197 = _T_4189 & buf_ldfwd[0]; // @[Mux.scala 27:72]
|
|
wire _T_4198 = _T_4191 & buf_ldfwd[1]; // @[Mux.scala 27:72]
|
|
wire _T_4199 = _T_4193 & buf_ldfwd[2]; // @[Mux.scala 27:72]
|
|
wire _T_4200 = _T_4195 & buf_ldfwd[3]; // @[Mux.scala 27:72]
|
|
wire _T_4201 = _T_4197 | _T_4198; // @[Mux.scala 27:72]
|
|
wire _T_4202 = _T_4201 | _T_4199; // @[Mux.scala 27:72]
|
|
wire _T_4203 = _T_4202 | _T_4200; // @[Mux.scala 27:72]
|
|
wire _T_4205 = _T_4179 & _T_4203; // @[el2_lsu_bus_buffer.scala 522:101]
|
|
wire _T_4206 = _GEN_249 == 3'h4; // @[el2_lsu_bus_buffer.scala 522:167]
|
|
wire _T_4207 = _T_4205 & _T_4206; // @[el2_lsu_bus_buffer.scala 522:138]
|
|
wire _T_4208 = _T_4207 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:187]
|
|
wire _T_4209 = _T_4183 | _T_4208; // @[el2_lsu_bus_buffer.scala 522:53]
|
|
wire _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 529:47]
|
|
wire _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 529:62]
|
|
wire _T_4247 = ~buf_error_en_3; // @[el2_lsu_bus_buffer.scala 533:50]
|
|
wire _T_4248 = buf_state_en_3 & _T_4247; // @[el2_lsu_bus_buffer.scala 533:48]
|
|
wire _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[el2_lsu_bus_buffer.scala 536:90]
|
|
wire _T_4261 = _T_4260 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 536:118]
|
|
wire _GEN_257 = _T_4281 & buf_state_en_3; // @[Conditional.scala 39:67]
|
|
wire _GEN_260 = _T_4273 ? 1'h0 : _T_4281; // @[Conditional.scala 39:67]
|
|
wire _GEN_262 = _T_4273 ? 1'h0 : _GEN_257; // @[Conditional.scala 39:67]
|
|
wire _GEN_266 = _T_4255 ? 1'h0 : _GEN_260; // @[Conditional.scala 39:67]
|
|
wire _GEN_268 = _T_4255 ? 1'h0 : _GEN_262; // @[Conditional.scala 39:67]
|
|
wire _GEN_273 = _T_4168 & _T_4233; // @[Conditional.scala 39:67]
|
|
wire _GEN_276 = _T_4168 ? 1'h0 : _GEN_266; // @[Conditional.scala 39:67]
|
|
wire _GEN_278 = _T_4168 ? 1'h0 : _GEN_268; // @[Conditional.scala 39:67]
|
|
wire _GEN_284 = _T_4134 ? _T_4154 : _GEN_278; // @[Conditional.scala 39:67]
|
|
wire _GEN_286 = _T_4134 ? _T_4158 : _GEN_273; // @[Conditional.scala 39:67]
|
|
wire _GEN_290 = _T_4134 ? 1'h0 : _GEN_276; // @[Conditional.scala 39:67]
|
|
wire _GEN_296 = _T_4130 ? 1'h0 : _GEN_284; // @[Conditional.scala 39:67]
|
|
wire _GEN_298 = _T_4130 ? 1'h0 : _GEN_286; // @[Conditional.scala 39:67]
|
|
wire _GEN_302 = _T_4130 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67]
|
|
wire buf_wr_en_3 = _T_4107 & buf_state_en_3; // @[Conditional.scala 40:58]
|
|
wire buf_ldfwd_en_3 = _T_4107 ? 1'h0 : _GEN_296; // @[Conditional.scala 40:58]
|
|
wire buf_rst_3 = _T_4107 ? 1'h0 : _GEN_302; // @[Conditional.scala 40:58]
|
|
reg _T_4336; // @[Reg.scala 27:20]
|
|
reg _T_4339; // @[Reg.scala 27:20]
|
|
reg _T_4342; // @[Reg.scala 27:20]
|
|
reg _T_4345; // @[Reg.scala 27:20]
|
|
wire [3:0] buf_unsign = {_T_4345,_T_4342,_T_4339,_T_4336}; // @[Cat.scala 29:58]
|
|
reg _T_4411; // @[el2_lsu_bus_buffer.scala 572:80]
|
|
reg _T_4406; // @[el2_lsu_bus_buffer.scala 572:80]
|
|
reg _T_4401; // @[el2_lsu_bus_buffer.scala 572:80]
|
|
reg _T_4396; // @[el2_lsu_bus_buffer.scala 572:80]
|
|
wire [3:0] buf_error = {_T_4411,_T_4406,_T_4401,_T_4396}; // @[Cat.scala 29:58]
|
|
wire _T_4393 = buf_error_en_0 | buf_error[0]; // @[el2_lsu_bus_buffer.scala 572:84]
|
|
wire _T_4394 = ~buf_rst_0; // @[el2_lsu_bus_buffer.scala 572:126]
|
|
wire _T_4398 = buf_error_en_1 | buf_error[1]; // @[el2_lsu_bus_buffer.scala 572:84]
|
|
wire _T_4399 = ~buf_rst_1; // @[el2_lsu_bus_buffer.scala 572:126]
|
|
wire _T_4403 = buf_error_en_2 | buf_error[2]; // @[el2_lsu_bus_buffer.scala 572:84]
|
|
wire _T_4404 = ~buf_rst_2; // @[el2_lsu_bus_buffer.scala 572:126]
|
|
wire _T_4408 = buf_error_en_3 | buf_error[3]; // @[el2_lsu_bus_buffer.scala 572:84]
|
|
wire _T_4409 = ~buf_rst_3; // @[el2_lsu_bus_buffer.scala 572:126]
|
|
wire [1:0] _T_4415 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[el2_lsu_bus_buffer.scala 575:28]
|
|
wire [1:0] _T_4417 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[el2_lsu_bus_buffer.scala 575:94]
|
|
wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[el2_lsu_bus_buffer.scala 575:88]
|
|
wire [2:0] _GEN_388 = {{2'd0}, ibuf_valid}; // @[el2_lsu_bus_buffer.scala 575:154]
|
|
wire [3:0] _T_4420 = _T_4419 + _GEN_388; // @[el2_lsu_bus_buffer.scala 575:154]
|
|
wire [1:0] _T_4425 = _T_5 + _T_12; // @[el2_lsu_bus_buffer.scala 575:217]
|
|
wire [1:0] _GEN_389 = {{1'd0}, _T_19}; // @[el2_lsu_bus_buffer.scala 575:217]
|
|
wire [2:0] _T_4426 = _T_4425 + _GEN_389; // @[el2_lsu_bus_buffer.scala 575:217]
|
|
wire [2:0] _GEN_390 = {{2'd0}, _T_26}; // @[el2_lsu_bus_buffer.scala 575:217]
|
|
wire [3:0] _T_4427 = _T_4426 + _GEN_390; // @[el2_lsu_bus_buffer.scala 575:217]
|
|
wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[el2_lsu_bus_buffer.scala 575:169]
|
|
wire _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_buffer.scala 581:52]
|
|
wire _T_4499 = buf_numvld_any >= 4'h3; // @[el2_lsu_bus_buffer.scala 581:92]
|
|
wire _T_4500 = buf_numvld_any == 4'h4; // @[el2_lsu_bus_buffer.scala 581:121]
|
|
wire _T_4502 = |buf_state_0; // @[el2_lsu_bus_buffer.scala 582:52]
|
|
wire _T_4503 = |buf_state_1; // @[el2_lsu_bus_buffer.scala 582:52]
|
|
wire _T_4504 = |buf_state_2; // @[el2_lsu_bus_buffer.scala 582:52]
|
|
wire _T_4505 = |buf_state_3; // @[el2_lsu_bus_buffer.scala 582:52]
|
|
wire _T_4506 = _T_4502 | _T_4503; // @[el2_lsu_bus_buffer.scala 582:65]
|
|
wire _T_4507 = _T_4506 | _T_4504; // @[el2_lsu_bus_buffer.scala 582:65]
|
|
wire _T_4508 = _T_4507 | _T_4505; // @[el2_lsu_bus_buffer.scala 582:65]
|
|
wire _T_4509 = ~_T_4508; // @[el2_lsu_bus_buffer.scala 582:34]
|
|
wire _T_4511 = _T_4509 & _T_852; // @[el2_lsu_bus_buffer.scala 582:70]
|
|
wire _T_4514 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[el2_lsu_bus_buffer.scala 584:51]
|
|
wire _T_4515 = _T_4514 & io_lsu_pkt_m_bits_load; // @[el2_lsu_bus_buffer.scala 584:72]
|
|
wire _T_4516 = ~io_flush_m_up; // @[el2_lsu_bus_buffer.scala 584:99]
|
|
wire _T_4517 = _T_4515 & _T_4516; // @[el2_lsu_bus_buffer.scala 584:97]
|
|
wire _T_4518 = ~io_ld_full_hit_m; // @[el2_lsu_bus_buffer.scala 584:116]
|
|
wire _T_4520 = ~io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 587:61]
|
|
reg lsu_nonblock_load_valid_r; // @[el2_lsu_bus_buffer.scala 672:66]
|
|
wire _T_4538 = _T_2799 & _T_3643; // @[Mux.scala 27:72]
|
|
wire _T_4539 = _T_2821 & _T_3836; // @[Mux.scala 27:72]
|
|
wire _T_4540 = _T_2843 & _T_4029; // @[Mux.scala 27:72]
|
|
wire _T_4541 = _T_2865 & _T_4222; // @[Mux.scala 27:72]
|
|
wire _T_4542 = _T_4538 | _T_4539; // @[Mux.scala 27:72]
|
|
wire _T_4543 = _T_4542 | _T_4540; // @[Mux.scala 27:72]
|
|
wire lsu_nonblock_load_data_ready = _T_4543 | _T_4541; // @[Mux.scala 27:72]
|
|
wire _T_4549 = buf_error[0] & _T_3643; // @[el2_lsu_bus_buffer.scala 590:108]
|
|
wire _T_4554 = buf_error[1] & _T_3836; // @[el2_lsu_bus_buffer.scala 590:108]
|
|
wire _T_4559 = buf_error[2] & _T_4029; // @[el2_lsu_bus_buffer.scala 590:108]
|
|
wire _T_4564 = buf_error[3] & _T_4222; // @[el2_lsu_bus_buffer.scala 590:108]
|
|
wire _T_4565 = _T_2799 & _T_4549; // @[Mux.scala 27:72]
|
|
wire _T_4566 = _T_2821 & _T_4554; // @[Mux.scala 27:72]
|
|
wire _T_4567 = _T_2843 & _T_4559; // @[Mux.scala 27:72]
|
|
wire _T_4568 = _T_2865 & _T_4564; // @[Mux.scala 27:72]
|
|
wire _T_4569 = _T_4565 | _T_4566; // @[Mux.scala 27:72]
|
|
wire _T_4570 = _T_4569 | _T_4567; // @[Mux.scala 27:72]
|
|
wire _T_4577 = ~buf_dual_0; // @[el2_lsu_bus_buffer.scala 591:109]
|
|
wire _T_4578 = ~buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 591:124]
|
|
wire _T_4579 = _T_4577 | _T_4578; // @[el2_lsu_bus_buffer.scala 591:122]
|
|
wire _T_4580 = _T_4538 & _T_4579; // @[el2_lsu_bus_buffer.scala 591:106]
|
|
wire _T_4585 = ~buf_dual_1; // @[el2_lsu_bus_buffer.scala 591:109]
|
|
wire _T_4586 = ~buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 591:124]
|
|
wire _T_4587 = _T_4585 | _T_4586; // @[el2_lsu_bus_buffer.scala 591:122]
|
|
wire _T_4588 = _T_4539 & _T_4587; // @[el2_lsu_bus_buffer.scala 591:106]
|
|
wire _T_4593 = ~buf_dual_2; // @[el2_lsu_bus_buffer.scala 591:109]
|
|
wire _T_4594 = ~buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 591:124]
|
|
wire _T_4595 = _T_4593 | _T_4594; // @[el2_lsu_bus_buffer.scala 591:122]
|
|
wire _T_4596 = _T_4540 & _T_4595; // @[el2_lsu_bus_buffer.scala 591:106]
|
|
wire _T_4601 = ~buf_dual_3; // @[el2_lsu_bus_buffer.scala 591:109]
|
|
wire _T_4602 = ~buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 591:124]
|
|
wire _T_4603 = _T_4601 | _T_4602; // @[el2_lsu_bus_buffer.scala 591:122]
|
|
wire _T_4604 = _T_4541 & _T_4603; // @[el2_lsu_bus_buffer.scala 591:106]
|
|
wire [1:0] _T_4607 = _T_4596 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4608 = _T_4604 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_391 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4610 = _GEN_391 | _T_4607; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4645 = _T_4580 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4646 = _T_4588 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4647 = _T_4596 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4648 = _T_4604 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4649 = _T_4645 | _T_4646; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4650 = _T_4649 | _T_4647; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_nonblock_load_data_lo = _T_4650 | _T_4648; // @[Mux.scala 27:72]
|
|
wire _T_4657 = _T_4538 & _T_3641; // @[el2_lsu_bus_buffer.scala 593:105]
|
|
wire _T_4663 = _T_4539 & _T_3834; // @[el2_lsu_bus_buffer.scala 593:105]
|
|
wire _T_4669 = _T_4540 & _T_4027; // @[el2_lsu_bus_buffer.scala 593:105]
|
|
wire _T_4675 = _T_4541 & _T_4220; // @[el2_lsu_bus_buffer.scala 593:105]
|
|
wire [31:0] _T_4676 = _T_4657 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4677 = _T_4663 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4678 = _T_4669 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4679 = _T_4675 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4680 = _T_4676 | _T_4677; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4681 = _T_4680 | _T_4678; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_nonblock_load_data_hi = _T_4681 | _T_4679; // @[Mux.scala 27:72]
|
|
wire _T_4683 = io_lsu_nonblock_load_data_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 112:123]
|
|
wire _T_4684 = io_lsu_nonblock_load_data_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 112:123]
|
|
wire _T_4685 = io_lsu_nonblock_load_data_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 112:123]
|
|
wire _T_4686 = io_lsu_nonblock_load_data_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 112:123]
|
|
wire [31:0] _T_4687 = _T_4683 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4688 = _T_4684 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4689 = _T_4685 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4690 = _T_4686 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4691 = _T_4687 | _T_4688; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4692 = _T_4691 | _T_4689; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4693 = _T_4692 | _T_4690; // @[Mux.scala 27:72]
|
|
wire [1:0] lsu_nonblock_addr_offset = _T_4693[1:0]; // @[el2_lsu_bus_buffer.scala 594:83]
|
|
wire [1:0] _T_4699 = _T_4683 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4700 = _T_4684 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4701 = _T_4685 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4702 = _T_4686 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4703 = _T_4699 | _T_4700; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4704 = _T_4703 | _T_4701; // @[Mux.scala 27:72]
|
|
wire [1:0] lsu_nonblock_sz = _T_4704 | _T_4702; // @[Mux.scala 27:72]
|
|
wire _T_4714 = _T_4683 & buf_unsign[0]; // @[Mux.scala 27:72]
|
|
wire _T_4715 = _T_4684 & buf_unsign[1]; // @[Mux.scala 27:72]
|
|
wire _T_4716 = _T_4685 & buf_unsign[2]; // @[Mux.scala 27:72]
|
|
wire _T_4717 = _T_4686 & buf_unsign[3]; // @[Mux.scala 27:72]
|
|
wire _T_4718 = _T_4714 | _T_4715; // @[Mux.scala 27:72]
|
|
wire _T_4719 = _T_4718 | _T_4716; // @[Mux.scala 27:72]
|
|
wire lsu_nonblock_unsign = _T_4719 | _T_4717; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_4739 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58]
|
|
wire [3:0] _GEN_392 = {{2'd0}, lsu_nonblock_addr_offset}; // @[el2_lsu_bus_buffer.scala 598:121]
|
|
wire [5:0] _T_4740 = _GEN_392 * 4'h8; // @[el2_lsu_bus_buffer.scala 598:121]
|
|
wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[el2_lsu_bus_buffer.scala 598:92]
|
|
wire _T_4741 = ~io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_buffer.scala 600:69]
|
|
wire _T_4743 = lsu_nonblock_sz == 2'h0; // @[el2_lsu_bus_buffer.scala 601:81]
|
|
wire _T_4744 = lsu_nonblock_unsign & _T_4743; // @[el2_lsu_bus_buffer.scala 601:63]
|
|
wire [31:0] _T_4746 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_4747 = lsu_nonblock_sz == 2'h1; // @[el2_lsu_bus_buffer.scala 602:45]
|
|
wire _T_4748 = lsu_nonblock_unsign & _T_4747; // @[el2_lsu_bus_buffer.scala 602:26]
|
|
wire [31:0] _T_4750 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58]
|
|
wire _T_4751 = ~lsu_nonblock_unsign; // @[el2_lsu_bus_buffer.scala 603:6]
|
|
wire _T_4753 = _T_4751 & _T_4743; // @[el2_lsu_bus_buffer.scala 603:27]
|
|
wire [23:0] _T_4756 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_4758 = {_T_4756,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_4761 = _T_4751 & _T_4747; // @[el2_lsu_bus_buffer.scala 604:27]
|
|
wire [15:0] _T_4764 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_4766 = {_T_4764,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58]
|
|
wire _T_4767 = lsu_nonblock_sz == 2'h2; // @[el2_lsu_bus_buffer.scala 605:21]
|
|
wire [31:0] _T_4768 = _T_4744 ? _T_4746 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4769 = _T_4748 ? _T_4750 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4770 = _T_4753 ? _T_4758 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4771 = _T_4761 ? _T_4766 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_4772 = _T_4767 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4773 = _T_4768 | _T_4769; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4774 = _T_4773 | _T_4770; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4775 = _T_4774 | _T_4771; // @[Mux.scala 27:72]
|
|
wire [63:0] _GEN_393 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_4776 = _GEN_393 | _T_4772; // @[Mux.scala 27:72]
|
|
wire _T_4871 = obuf_valid & obuf_write; // @[el2_lsu_bus_buffer.scala 623:36]
|
|
wire _T_4872 = ~obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 623:51]
|
|
wire _T_4873 = _T_4871 & _T_4872; // @[el2_lsu_bus_buffer.scala 623:49]
|
|
wire [31:0] _T_4877 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58]
|
|
wire [2:0] _T_4879 = {1'h0,obuf_sz}; // @[Cat.scala 29:58]
|
|
wire _T_4884 = ~obuf_data_done; // @[el2_lsu_bus_buffer.scala 635:50]
|
|
wire _T_4885 = _T_4871 & _T_4884; // @[el2_lsu_bus_buffer.scala 635:48]
|
|
wire [7:0] _T_4889 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_4892 = obuf_valid & _T_1343; // @[el2_lsu_bus_buffer.scala 640:36]
|
|
wire _T_4894 = _T_4892 & _T_1349; // @[el2_lsu_bus_buffer.scala 640:50]
|
|
wire _T_4906 = io_lsu_bus_clk_en_q & buf_error[0]; // @[el2_lsu_bus_buffer.scala 653:114]
|
|
wire _T_4908 = _T_4906 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 653:129]
|
|
wire _T_4911 = io_lsu_bus_clk_en_q & buf_error[1]; // @[el2_lsu_bus_buffer.scala 653:114]
|
|
wire _T_4913 = _T_4911 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 653:129]
|
|
wire _T_4916 = io_lsu_bus_clk_en_q & buf_error[2]; // @[el2_lsu_bus_buffer.scala 653:114]
|
|
wire _T_4918 = _T_4916 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 653:129]
|
|
wire _T_4921 = io_lsu_bus_clk_en_q & buf_error[3]; // @[el2_lsu_bus_buffer.scala 653:114]
|
|
wire _T_4923 = _T_4921 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 653:129]
|
|
wire _T_4924 = _T_2799 & _T_4908; // @[Mux.scala 27:72]
|
|
wire _T_4925 = _T_2821 & _T_4913; // @[Mux.scala 27:72]
|
|
wire _T_4926 = _T_2843 & _T_4918; // @[Mux.scala 27:72]
|
|
wire _T_4927 = _T_2865 & _T_4923; // @[Mux.scala 27:72]
|
|
wire _T_4928 = _T_4924 | _T_4925; // @[Mux.scala 27:72]
|
|
wire _T_4929 = _T_4928 | _T_4926; // @[Mux.scala 27:72]
|
|
wire _T_4939 = _T_2821 & buf_error[1]; // @[el2_lsu_bus_buffer.scala 654:93]
|
|
wire _T_4941 = _T_4939 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 654:108]
|
|
wire _T_4944 = _T_2843 & buf_error[2]; // @[el2_lsu_bus_buffer.scala 654:93]
|
|
wire _T_4946 = _T_4944 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 654:108]
|
|
wire _T_4949 = _T_2865 & buf_error[3]; // @[el2_lsu_bus_buffer.scala 654:93]
|
|
wire _T_4951 = _T_4949 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 654:108]
|
|
wire [1:0] _T_4954 = _T_4946 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4955 = _T_4951 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_394 = {{1'd0}, _T_4941}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4957 = _GEN_394 | _T_4954; // @[Mux.scala 27:72]
|
|
wire [1:0] lsu_imprecise_error_store_tag = _T_4957 | _T_4955; // @[Mux.scala 27:72]
|
|
wire _T_4959 = ~io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 656:72]
|
|
wire [31:0] _GEN_351 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 657:41]
|
|
wire [31:0] _GEN_352 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_351; // @[el2_lsu_bus_buffer.scala 657:41]
|
|
wire [31:0] _GEN_353 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_352; // @[el2_lsu_bus_buffer.scala 657:41]
|
|
wire [31:0] _GEN_355 = 2'h1 == io_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 657:41]
|
|
wire [31:0] _GEN_356 = 2'h2 == io_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_355; // @[el2_lsu_bus_buffer.scala 657:41]
|
|
wire [31:0] _GEN_357 = 2'h3 == io_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_356; // @[el2_lsu_bus_buffer.scala 657:41]
|
|
wire _T_4964 = bus_wcmd_sent | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 663:68]
|
|
wire _T_4967 = io_lsu_busreq_r & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 664:48]
|
|
wire _T_4970 = ~io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 667:48]
|
|
wire _T_4971 = io_lsu_axi_awvalid & _T_4970; // @[el2_lsu_bus_buffer.scala 667:46]
|
|
wire _T_4972 = ~io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 667:92]
|
|
wire _T_4973 = io_lsu_axi_wvalid & _T_4972; // @[el2_lsu_bus_buffer.scala 667:90]
|
|
wire _T_4974 = _T_4971 | _T_4973; // @[el2_lsu_bus_buffer.scala 667:69]
|
|
wire _T_4975 = ~io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 667:136]
|
|
wire _T_4976 = io_lsu_axi_arvalid & _T_4975; // @[el2_lsu_bus_buffer.scala 667:134]
|
|
wire _T_4980 = ~io_flush_r; // @[el2_lsu_bus_buffer.scala 671:75]
|
|
wire _T_4981 = io_lsu_busreq_m & _T_4980; // @[el2_lsu_bus_buffer.scala 671:73]
|
|
reg _T_4984; // @[el2_lsu_bus_buffer.scala 671:56]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en),
|
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en),
|
|
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_8_io_l1clk),
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en),
|
|
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_9_io_l1clk),
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en),
|
|
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_10_io_l1clk),
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en),
|
|
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_11_io_l1clk),
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en),
|
|
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
|
);
|
|
assign io_lsu_busreq_r = _T_4984; // @[el2_lsu_bus_buffer.scala 671:19]
|
|
assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[el2_lsu_bus_buffer.scala 580:30]
|
|
assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[el2_lsu_bus_buffer.scala 581:30]
|
|
assign io_lsu_bus_buffer_empty_any = _T_4511 & _T_1231; // @[el2_lsu_bus_buffer.scala 582:31]
|
|
assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[el2_lsu_bus_buffer.scala 192:25]
|
|
assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[el2_lsu_bus_buffer.scala 193:25]
|
|
assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[el2_lsu_bus_buffer.scala 219:24]
|
|
assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[el2_lsu_bus_buffer.scala 225:24]
|
|
assign io_lsu_imprecise_error_load_any = io_lsu_nonblock_load_data_error & _T_4959; // @[el2_lsu_bus_buffer.scala 656:35]
|
|
assign io_lsu_imprecise_error_store_any = _T_4929 | _T_4927; // @[el2_lsu_bus_buffer.scala 653:36]
|
|
assign io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_store_any ? _GEN_353 : _GEN_357; // @[el2_lsu_bus_buffer.scala 657:35]
|
|
assign io_lsu_nonblock_load_valid_m = _T_4517 & _T_4518; // @[el2_lsu_bus_buffer.scala 584:32]
|
|
assign io_lsu_nonblock_load_tag_m = _T_1863 ? 2'h0 : _T_1899; // @[el2_lsu_bus_buffer.scala 585:30]
|
|
assign io_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4520; // @[el2_lsu_bus_buffer.scala 587:30]
|
|
assign io_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[el2_lsu_bus_buffer.scala 588:34]
|
|
assign io_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4741; // @[el2_lsu_bus_buffer.scala 600:35]
|
|
assign io_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[el2_lsu_bus_buffer.scala 590:35]
|
|
assign io_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[el2_lsu_bus_buffer.scala 591:33]
|
|
assign io_lsu_nonblock_load_data = _T_4776[31:0]; // @[el2_lsu_bus_buffer.scala 601:29]
|
|
assign io_lsu_pmu_bus_trxn = _T_4964 | _T_4863; // @[el2_lsu_bus_buffer.scala 663:23]
|
|
assign io_lsu_pmu_bus_misaligned = _T_4967 & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 664:29]
|
|
assign io_lsu_pmu_bus_error = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 665:24]
|
|
assign io_lsu_pmu_bus_busy = _T_4974 | _T_4976; // @[el2_lsu_bus_buffer.scala 667:23]
|
|
assign io_lsu_axi_awvalid = _T_4873 & _T_1239; // @[el2_lsu_bus_buffer.scala 623:22]
|
|
assign io_lsu_axi_awid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 624:19]
|
|
assign io_lsu_axi_awaddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 625:21]
|
|
assign io_lsu_axi_awregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 629:23]
|
|
assign io_lsu_axi_awsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 626:21]
|
|
assign io_lsu_axi_awcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 628:22]
|
|
assign io_lsu_axi_wvalid = _T_4885 & _T_1239; // @[el2_lsu_bus_buffer.scala 635:21]
|
|
assign io_lsu_axi_wdata = obuf_data; // @[el2_lsu_bus_buffer.scala 637:20]
|
|
assign io_lsu_axi_wstrb = obuf_byteen & _T_4889; // @[el2_lsu_bus_buffer.scala 636:20]
|
|
assign io_lsu_axi_bready = 1'h1; // @[el2_lsu_bus_buffer.scala 651:21]
|
|
assign io_lsu_axi_arvalid = _T_4894 & _T_1239; // @[el2_lsu_bus_buffer.scala 640:22]
|
|
assign io_lsu_axi_arid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 641:19]
|
|
assign io_lsu_axi_araddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 642:21]
|
|
assign io_lsu_axi_arregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 646:23]
|
|
assign io_lsu_axi_arsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 643:21]
|
|
assign io_lsu_axi_arcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 645:22]
|
|
assign io_lsu_axi_rready = 1'h1; // @[el2_lsu_bus_buffer.scala 652:21]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = _T_853 & _T_854; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_2_io_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_4_io_en = _T_3528 & buf_state_en_0; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_5_io_en = _T_3721 & buf_state_en_1; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_6_io_en = _T_3914 & buf_state_en_2; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_7_io_en = _T_4107 & buf_state_en_3; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_8_io_en = _T_3528 ? buf_state_en_0 : _GEN_70; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_9_io_en = _T_3721 ? buf_state_en_1 : _GEN_146; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_10_io_en = _T_3914 ? buf_state_en_2 : _GEN_222; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_11_io_en = _T_4107 ? buf_state_en_3 : _GEN_298; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
buf_addr_0 = _RAND_0[31:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_4360 = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
_T_4357 = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
_T_4354 = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_4351 = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
buf_state_0 = _RAND_5[2:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
buf_addr_1 = _RAND_6[31:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
buf_state_1 = _RAND_7[2:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
buf_addr_2 = _RAND_8[31:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
buf_state_2 = _RAND_9[2:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
buf_addr_3 = _RAND_10[31:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
buf_state_3 = _RAND_11[2:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
buf_byteen_3 = _RAND_12[3:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
buf_byteen_2 = _RAND_13[3:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
buf_byteen_1 = _RAND_14[3:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
buf_byteen_0 = _RAND_15[3:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
buf_ageQ_3 = _RAND_16[3:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
_T_1848 = _RAND_17[1:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
obuf_merge = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
obuf_tag1 = _RAND_19[1:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
obuf_valid = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
obuf_wr_enQ = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
ibuf_addr = _RAND_22[31:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
ibuf_write = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
ibuf_valid = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
ibuf_byteen = _RAND_25[3:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
buf_ageQ_2 = _RAND_26[3:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
buf_ageQ_1 = _RAND_27[3:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
buf_ageQ_0 = _RAND_28[3:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
buf_data_0 = _RAND_29[31:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
buf_data_1 = _RAND_30[31:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
buf_data_2 = _RAND_31[31:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
buf_data_3 = _RAND_32[31:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
ibuf_data = _RAND_33[31:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
ibuf_timer = _RAND_34[2:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
ibuf_sideeffect = _RAND_35[0:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
WrPtr1_r = _RAND_36[1:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
WrPtr0_r = _RAND_37[1:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
ibuf_tag = _RAND_38[1:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
ibuf_dualtag = _RAND_39[1:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
ibuf_dual = _RAND_40[0:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
ibuf_samedw = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
ibuf_nomerge = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
ibuf_unsign = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
ibuf_sz = _RAND_44[1:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
obuf_wr_timer = _RAND_45[2:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
buf_nomerge_0 = _RAND_46[0:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
buf_nomerge_1 = _RAND_47[0:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
buf_nomerge_2 = _RAND_48[0:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
buf_nomerge_3 = _RAND_49[0:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
_T_4330 = _RAND_50[0:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
_T_4327 = _RAND_51[0:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
_T_4324 = _RAND_52[0:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
_T_4321 = _RAND_53[0:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
buf_dual_3 = _RAND_54[0:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
buf_dual_2 = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
buf_dual_1 = _RAND_56[0:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
buf_dual_0 = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
buf_samedw_3 = _RAND_58[0:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
buf_samedw_2 = _RAND_59[0:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
buf_samedw_1 = _RAND_60[0:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
buf_samedw_0 = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
obuf_write = _RAND_62[0:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
obuf_cmd_done = _RAND_63[0:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
obuf_data_done = _RAND_64[0:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
obuf_nosend = _RAND_65[0:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
obuf_addr = _RAND_66[31:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
buf_sz_0 = _RAND_67[1:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
buf_sz_1 = _RAND_68[1:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
buf_sz_2 = _RAND_69[1:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
buf_sz_3 = _RAND_70[1:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
obuf_sideeffect = _RAND_71[0:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
obuf_rdrsp_pend = _RAND_72[0:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
obuf_rdrsp_tag = _RAND_73[2:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
buf_dualhi_3 = _RAND_74[0:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
buf_dualhi_2 = _RAND_75[0:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
buf_dualhi_1 = _RAND_76[0:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
buf_dualhi_0 = _RAND_77[0:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
obuf_sz = _RAND_78[1:0];
|
|
_RAND_79 = {1{`RANDOM}};
|
|
obuf_byteen = _RAND_79[7:0];
|
|
_RAND_80 = {2{`RANDOM}};
|
|
obuf_data = _RAND_80[63:0];
|
|
_RAND_81 = {1{`RANDOM}};
|
|
buf_rspageQ_0 = _RAND_81[3:0];
|
|
_RAND_82 = {1{`RANDOM}};
|
|
buf_rspageQ_1 = _RAND_82[3:0];
|
|
_RAND_83 = {1{`RANDOM}};
|
|
buf_rspageQ_2 = _RAND_83[3:0];
|
|
_RAND_84 = {1{`RANDOM}};
|
|
buf_rspageQ_3 = _RAND_84[3:0];
|
|
_RAND_85 = {1{`RANDOM}};
|
|
_T_4307 = _RAND_85[0:0];
|
|
_RAND_86 = {1{`RANDOM}};
|
|
_T_4305 = _RAND_86[0:0];
|
|
_RAND_87 = {1{`RANDOM}};
|
|
_T_4303 = _RAND_87[0:0];
|
|
_RAND_88 = {1{`RANDOM}};
|
|
_T_4301 = _RAND_88[0:0];
|
|
_RAND_89 = {1{`RANDOM}};
|
|
buf_ldfwdtag_0 = _RAND_89[1:0];
|
|
_RAND_90 = {1{`RANDOM}};
|
|
buf_dualtag_0 = _RAND_90[1:0];
|
|
_RAND_91 = {1{`RANDOM}};
|
|
buf_ldfwdtag_3 = _RAND_91[1:0];
|
|
_RAND_92 = {1{`RANDOM}};
|
|
buf_ldfwdtag_2 = _RAND_92[1:0];
|
|
_RAND_93 = {1{`RANDOM}};
|
|
buf_ldfwdtag_1 = _RAND_93[1:0];
|
|
_RAND_94 = {1{`RANDOM}};
|
|
buf_dualtag_1 = _RAND_94[1:0];
|
|
_RAND_95 = {1{`RANDOM}};
|
|
buf_dualtag_2 = _RAND_95[1:0];
|
|
_RAND_96 = {1{`RANDOM}};
|
|
buf_dualtag_3 = _RAND_96[1:0];
|
|
_RAND_97 = {1{`RANDOM}};
|
|
_T_4336 = _RAND_97[0:0];
|
|
_RAND_98 = {1{`RANDOM}};
|
|
_T_4339 = _RAND_98[0:0];
|
|
_RAND_99 = {1{`RANDOM}};
|
|
_T_4342 = _RAND_99[0:0];
|
|
_RAND_100 = {1{`RANDOM}};
|
|
_T_4345 = _RAND_100[0:0];
|
|
_RAND_101 = {1{`RANDOM}};
|
|
_T_4411 = _RAND_101[0:0];
|
|
_RAND_102 = {1{`RANDOM}};
|
|
_T_4406 = _RAND_102[0:0];
|
|
_RAND_103 = {1{`RANDOM}};
|
|
_T_4401 = _RAND_103[0:0];
|
|
_RAND_104 = {1{`RANDOM}};
|
|
_T_4396 = _RAND_104[0:0];
|
|
_RAND_105 = {1{`RANDOM}};
|
|
lsu_nonblock_load_valid_r = _RAND_105[0:0];
|
|
_RAND_106 = {1{`RANDOM}};
|
|
_T_4984 = _RAND_106[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
buf_addr_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4360 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4357 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4354 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4351 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_state_0 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_addr_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_state_1 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_addr_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_state_2 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_addr_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_state_3 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_byteen_3 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_byteen_2 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_byteen_1 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_byteen_0 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ageQ_3 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1848 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_merge = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_tag1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_wr_enQ = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_addr = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_write = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_byteen = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ageQ_2 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ageQ_1 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ageQ_0 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_data_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_data_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_data_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_data_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_data = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_timer = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_sideeffect = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
WrPtr1_r = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
WrPtr0_r = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_tag = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_dualtag = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_dual = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_samedw = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_nomerge = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_unsign = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_sz = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_wr_timer = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_nomerge_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_nomerge_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_nomerge_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_nomerge_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4330 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4327 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4324 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4321 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dual_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dual_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dual_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dual_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_samedw_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_samedw_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_samedw_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_samedw_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_write = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_cmd_done = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_data_done = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_nosend = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_addr = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_sz_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_sz_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_sz_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_sz_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_sideeffect = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_rdrsp_pend = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_rdrsp_tag = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualhi_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualhi_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualhi_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualhi_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_sz = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_byteen = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_data = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_rspageQ_0 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_rspageQ_1 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_rspageQ_2 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_rspageQ_3 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4307 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4305 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4303 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4301 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ldfwdtag_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualtag_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ldfwdtag_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ldfwdtag_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ldfwdtag_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualtag_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualtag_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualtag_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4336 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4339 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4342 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4345 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4411 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4406 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4401 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4396 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_nonblock_load_valid_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4984 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_addr_0 <= 32'h0;
|
|
end else if (ibuf_drainvec_vld[0]) begin
|
|
buf_addr_0 <= ibuf_addr;
|
|
end else if (_T_3343) begin
|
|
buf_addr_0 <= io_end_addr_r;
|
|
end else begin
|
|
buf_addr_0 <= io_lsu_addr_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4360 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
_T_4360 <= buf_write_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4357 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
_T_4357 <= buf_write_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4354 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
_T_4354 <= buf_write_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4351 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
_T_4351 <= buf_write_in[0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else if (buf_state_en_0) begin
|
|
if (_T_3528) begin
|
|
if (io_lsu_bus_clk_en) begin
|
|
buf_state_0 <= 3'h2;
|
|
end else begin
|
|
buf_state_0 <= 3'h1;
|
|
end
|
|
end else if (_T_3551) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else begin
|
|
buf_state_0 <= 3'h2;
|
|
end
|
|
end else if (_T_3555) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else if (_T_3559) begin
|
|
buf_state_0 <= 3'h5;
|
|
end else begin
|
|
buf_state_0 <= 3'h3;
|
|
end
|
|
end else if (_T_3589) begin
|
|
if (_T_3594) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else if (_T_3602) begin
|
|
buf_state_0 <= 3'h4;
|
|
end else if (_T_3630) begin
|
|
buf_state_0 <= 3'h5;
|
|
end else begin
|
|
buf_state_0 <= 3'h6;
|
|
end
|
|
end else if (_T_3676) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else if (_T_3682) begin
|
|
buf_state_0 <= 3'h5;
|
|
end else begin
|
|
buf_state_0 <= 3'h6;
|
|
end
|
|
end else if (_T_3694) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else begin
|
|
buf_state_0 <= 3'h6;
|
|
end
|
|
end else begin
|
|
buf_state_0 <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_addr_1 <= 32'h0;
|
|
end else if (ibuf_drainvec_vld[1]) begin
|
|
buf_addr_1 <= ibuf_addr;
|
|
end else if (_T_3352) begin
|
|
buf_addr_1 <= io_end_addr_r;
|
|
end else begin
|
|
buf_addr_1 <= io_lsu_addr_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else if (buf_state_en_1) begin
|
|
if (_T_3721) begin
|
|
if (io_lsu_bus_clk_en) begin
|
|
buf_state_1 <= 3'h2;
|
|
end else begin
|
|
buf_state_1 <= 3'h1;
|
|
end
|
|
end else if (_T_3744) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else begin
|
|
buf_state_1 <= 3'h2;
|
|
end
|
|
end else if (_T_3748) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else if (_T_3559) begin
|
|
buf_state_1 <= 3'h5;
|
|
end else begin
|
|
buf_state_1 <= 3'h3;
|
|
end
|
|
end else if (_T_3782) begin
|
|
if (_T_3787) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else if (_T_3795) begin
|
|
buf_state_1 <= 3'h4;
|
|
end else if (_T_3823) begin
|
|
buf_state_1 <= 3'h5;
|
|
end else begin
|
|
buf_state_1 <= 3'h6;
|
|
end
|
|
end else if (_T_3869) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else if (_T_3875) begin
|
|
buf_state_1 <= 3'h5;
|
|
end else begin
|
|
buf_state_1 <= 3'h6;
|
|
end
|
|
end else if (_T_3887) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else begin
|
|
buf_state_1 <= 3'h6;
|
|
end
|
|
end else begin
|
|
buf_state_1 <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_addr_2 <= 32'h0;
|
|
end else if (ibuf_drainvec_vld[2]) begin
|
|
buf_addr_2 <= ibuf_addr;
|
|
end else if (_T_3361) begin
|
|
buf_addr_2 <= io_end_addr_r;
|
|
end else begin
|
|
buf_addr_2 <= io_lsu_addr_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else if (buf_state_en_2) begin
|
|
if (_T_3914) begin
|
|
if (io_lsu_bus_clk_en) begin
|
|
buf_state_2 <= 3'h2;
|
|
end else begin
|
|
buf_state_2 <= 3'h1;
|
|
end
|
|
end else if (_T_3937) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else begin
|
|
buf_state_2 <= 3'h2;
|
|
end
|
|
end else if (_T_3941) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else if (_T_3559) begin
|
|
buf_state_2 <= 3'h5;
|
|
end else begin
|
|
buf_state_2 <= 3'h3;
|
|
end
|
|
end else if (_T_3975) begin
|
|
if (_T_3980) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else if (_T_3988) begin
|
|
buf_state_2 <= 3'h4;
|
|
end else if (_T_4016) begin
|
|
buf_state_2 <= 3'h5;
|
|
end else begin
|
|
buf_state_2 <= 3'h6;
|
|
end
|
|
end else if (_T_4062) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else if (_T_4068) begin
|
|
buf_state_2 <= 3'h5;
|
|
end else begin
|
|
buf_state_2 <= 3'h6;
|
|
end
|
|
end else if (_T_4080) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else begin
|
|
buf_state_2 <= 3'h6;
|
|
end
|
|
end else begin
|
|
buf_state_2 <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_addr_3 <= 32'h0;
|
|
end else if (ibuf_drainvec_vld[3]) begin
|
|
buf_addr_3 <= ibuf_addr;
|
|
end else if (_T_3370) begin
|
|
buf_addr_3 <= io_end_addr_r;
|
|
end else begin
|
|
buf_addr_3 <= io_lsu_addr_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else if (buf_state_en_3) begin
|
|
if (_T_4107) begin
|
|
if (io_lsu_bus_clk_en) begin
|
|
buf_state_3 <= 3'h2;
|
|
end else begin
|
|
buf_state_3 <= 3'h1;
|
|
end
|
|
end else if (_T_4130) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else begin
|
|
buf_state_3 <= 3'h2;
|
|
end
|
|
end else if (_T_4134) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else if (_T_3559) begin
|
|
buf_state_3 <= 3'h5;
|
|
end else begin
|
|
buf_state_3 <= 3'h3;
|
|
end
|
|
end else if (_T_4168) begin
|
|
if (_T_4173) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else if (_T_4181) begin
|
|
buf_state_3 <= 3'h4;
|
|
end else if (_T_4209) begin
|
|
buf_state_3 <= 3'h5;
|
|
end else begin
|
|
buf_state_3 <= 3'h6;
|
|
end
|
|
end else if (_T_4255) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else if (_T_4261) begin
|
|
buf_state_3 <= 3'h5;
|
|
end else begin
|
|
buf_state_3 <= 3'h6;
|
|
end
|
|
end else if (_T_4273) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else begin
|
|
buf_state_3 <= 3'h6;
|
|
end
|
|
end else begin
|
|
buf_state_3 <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_byteen_3 <= 4'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
if (ibuf_drainvec_vld[3]) begin
|
|
buf_byteen_3 <= ibuf_byteen_out;
|
|
end else if (_T_3370) begin
|
|
buf_byteen_3 <= ldst_byteen_hi_r;
|
|
end else begin
|
|
buf_byteen_3 <= ldst_byteen_lo_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_byteen_2 <= 4'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
if (ibuf_drainvec_vld[2]) begin
|
|
buf_byteen_2 <= ibuf_byteen_out;
|
|
end else if (_T_3361) begin
|
|
buf_byteen_2 <= ldst_byteen_hi_r;
|
|
end else begin
|
|
buf_byteen_2 <= ldst_byteen_lo_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_byteen_1 <= 4'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
if (ibuf_drainvec_vld[1]) begin
|
|
buf_byteen_1 <= ibuf_byteen_out;
|
|
end else if (_T_3352) begin
|
|
buf_byteen_1 <= ldst_byteen_hi_r;
|
|
end else begin
|
|
buf_byteen_1 <= ldst_byteen_lo_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_byteen_0 <= 4'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
if (ibuf_drainvec_vld[0]) begin
|
|
buf_byteen_0 <= ibuf_byteen_out;
|
|
end else if (_T_3343) begin
|
|
buf_byteen_0 <= ldst_byteen_hi_r;
|
|
end else begin
|
|
buf_byteen_0 <= ldst_byteen_lo_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ageQ_3 <= 4'h0;
|
|
end else begin
|
|
buf_ageQ_3 <= {_T_2535,_T_2458};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1848 <= 2'h0;
|
|
end else if (obuf_wr_en) begin
|
|
if (ibuf_buf_byp) begin
|
|
_T_1848 <= WrPtr0_r;
|
|
end else begin
|
|
_T_1848 <= CmdPtr0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_merge <= 1'h0;
|
|
end else if (obuf_wr_en) begin
|
|
obuf_merge <= obuf_merge_en;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_tag1 <= 2'h0;
|
|
end else if (obuf_wr_en) begin
|
|
if (ibuf_buf_byp) begin
|
|
obuf_tag1 <= WrPtr1_r;
|
|
end else begin
|
|
obuf_tag1 <= CmdPtr1;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_valid <= 1'h0;
|
|
end else begin
|
|
obuf_valid <= _T_1839 & _T_1840;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_busm_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_wr_enQ <= 1'h0;
|
|
end else begin
|
|
obuf_wr_enQ <= _T_1240 & io_lsu_bus_clk_en;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_addr <= 32'h0;
|
|
end else if (io_ldst_dual_r) begin
|
|
ibuf_addr <= io_end_addr_r;
|
|
end else begin
|
|
ibuf_addr <= io_lsu_addr_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_write <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_write <= io_lsu_pkt_r_bits_store;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_valid <= 1'h0;
|
|
end else begin
|
|
ibuf_valid <= _T_1005 & _T_1006;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_byteen <= 4'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
if (_T_866) begin
|
|
ibuf_byteen <= _T_881;
|
|
end else if (io_ldst_dual_r) begin
|
|
ibuf_byteen <= ldst_byteen_hi_r;
|
|
end else begin
|
|
ibuf_byteen <= ldst_byteen_lo_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ageQ_2 <= 4'h0;
|
|
end else begin
|
|
buf_ageQ_2 <= {_T_2433,_T_2356};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ageQ_1 <= 4'h0;
|
|
end else begin
|
|
buf_ageQ_1 <= {_T_2331,_T_2254};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ageQ_0 <= 4'h0;
|
|
end else begin
|
|
buf_ageQ_0 <= {_T_2229,_T_2152};
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_data_0 <= 32'h0;
|
|
end else if (_T_3528) begin
|
|
if (_T_3543) begin
|
|
buf_data_0 <= ibuf_data_out;
|
|
end else begin
|
|
buf_data_0 <= store_data_lo_r;
|
|
end
|
|
end else if (_T_3551) begin
|
|
buf_data_0 <= 32'h0;
|
|
end else if (_T_3555) begin
|
|
if (buf_error_en_0) begin
|
|
buf_data_0 <= io_lsu_axi_rdata[31:0];
|
|
end else if (buf_addr_0[2]) begin
|
|
buf_data_0 <= io_lsu_axi_rdata[63:32];
|
|
end else begin
|
|
buf_data_0 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else if (_T_3589) begin
|
|
if (_T_3669) begin
|
|
if (buf_addr_0[2]) begin
|
|
buf_data_0 <= io_lsu_axi_rdata[63:32];
|
|
end else begin
|
|
buf_data_0 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_0 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_0 <= 32'h0;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_data_1 <= 32'h0;
|
|
end else if (_T_3721) begin
|
|
if (_T_3736) begin
|
|
buf_data_1 <= ibuf_data_out;
|
|
end else begin
|
|
buf_data_1 <= store_data_lo_r;
|
|
end
|
|
end else if (_T_3744) begin
|
|
buf_data_1 <= 32'h0;
|
|
end else if (_T_3748) begin
|
|
if (buf_error_en_1) begin
|
|
buf_data_1 <= io_lsu_axi_rdata[31:0];
|
|
end else if (buf_addr_1[2]) begin
|
|
buf_data_1 <= io_lsu_axi_rdata[63:32];
|
|
end else begin
|
|
buf_data_1 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else if (_T_3782) begin
|
|
if (_T_3862) begin
|
|
if (buf_addr_1[2]) begin
|
|
buf_data_1 <= io_lsu_axi_rdata[63:32];
|
|
end else begin
|
|
buf_data_1 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_1 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_1 <= 32'h0;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_data_2 <= 32'h0;
|
|
end else if (_T_3914) begin
|
|
if (_T_3929) begin
|
|
buf_data_2 <= ibuf_data_out;
|
|
end else begin
|
|
buf_data_2 <= store_data_lo_r;
|
|
end
|
|
end else if (_T_3937) begin
|
|
buf_data_2 <= 32'h0;
|
|
end else if (_T_3941) begin
|
|
if (buf_error_en_2) begin
|
|
buf_data_2 <= io_lsu_axi_rdata[31:0];
|
|
end else if (buf_addr_2[2]) begin
|
|
buf_data_2 <= io_lsu_axi_rdata[63:32];
|
|
end else begin
|
|
buf_data_2 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else if (_T_3975) begin
|
|
if (_T_4055) begin
|
|
if (buf_addr_2[2]) begin
|
|
buf_data_2 <= io_lsu_axi_rdata[63:32];
|
|
end else begin
|
|
buf_data_2 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_2 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_2 <= 32'h0;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_data_3 <= 32'h0;
|
|
end else if (_T_4107) begin
|
|
if (_T_4122) begin
|
|
buf_data_3 <= ibuf_data_out;
|
|
end else begin
|
|
buf_data_3 <= store_data_lo_r;
|
|
end
|
|
end else if (_T_4130) begin
|
|
buf_data_3 <= 32'h0;
|
|
end else if (_T_4134) begin
|
|
if (buf_error_en_3) begin
|
|
buf_data_3 <= io_lsu_axi_rdata[31:0];
|
|
end else if (buf_addr_3[2]) begin
|
|
buf_data_3 <= io_lsu_axi_rdata[63:32];
|
|
end else begin
|
|
buf_data_3 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else if (_T_4168) begin
|
|
if (_T_4248) begin
|
|
if (buf_addr_3[2]) begin
|
|
buf_data_3 <= io_lsu_axi_rdata[63:32];
|
|
end else begin
|
|
buf_data_3 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_3 <= io_lsu_axi_rdata[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_3 <= 32'h0;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_data <= 32'h0;
|
|
end else begin
|
|
ibuf_data <= {_T_922,_T_893};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_timer <= 3'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_timer <= 3'h0;
|
|
end else if (_T_923) begin
|
|
ibuf_timer <= _T_926;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_sideeffect <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_sideeffect <= io_is_sideeffects_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
WrPtr1_r <= 2'h0;
|
|
end else if (_T_1914) begin
|
|
WrPtr1_r <= 2'h0;
|
|
end else if (_T_1928) begin
|
|
WrPtr1_r <= 2'h1;
|
|
end else if (_T_1942) begin
|
|
WrPtr1_r <= 2'h2;
|
|
end else begin
|
|
WrPtr1_r <= 2'h3;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
WrPtr0_r <= 2'h0;
|
|
end else if (_T_1863) begin
|
|
WrPtr0_r <= 2'h0;
|
|
end else if (_T_1874) begin
|
|
WrPtr0_r <= 2'h1;
|
|
end else if (_T_1885) begin
|
|
WrPtr0_r <= 2'h2;
|
|
end else begin
|
|
WrPtr0_r <= 2'h3;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_tag <= 2'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
if (!(_T_866)) begin
|
|
if (io_ldst_dual_r) begin
|
|
ibuf_tag <= WrPtr1_r;
|
|
end else begin
|
|
ibuf_tag <= WrPtr0_r;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_dualtag <= 2'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_dualtag <= WrPtr0_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_dual <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_dual <= io_ldst_dual_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_samedw <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_samedw <= ldst_samedw_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_nomerge <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_nomerge <= io_no_dword_merge_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_unsign <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_unsign <= io_lsu_pkt_r_bits_unsign;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_sz <= 2'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_sz <= ibuf_sz_in;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_busm_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_wr_timer <= 3'h0;
|
|
end else if (obuf_wr_en) begin
|
|
obuf_wr_timer <= 3'h0;
|
|
end else if (_T_1058) begin
|
|
obuf_wr_timer <= _T_1060;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_nomerge_0 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
buf_nomerge_0 <= buf_nomerge_in[0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_nomerge_1 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
buf_nomerge_1 <= buf_nomerge_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_nomerge_2 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
buf_nomerge_2 <= buf_nomerge_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_nomerge_3 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
buf_nomerge_3 <= buf_nomerge_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4330 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
_T_4330 <= buf_sideeffect_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4327 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
_T_4327 <= buf_sideeffect_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4324 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
_T_4324 <= buf_sideeffect_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4321 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
_T_4321 <= buf_sideeffect_in[0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dual_3 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
buf_dual_3 <= buf_dual_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dual_2 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
buf_dual_2 <= buf_dual_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dual_1 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
buf_dual_1 <= buf_dual_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dual_0 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
buf_dual_0 <= buf_dual_in[0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_samedw_3 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
buf_samedw_3 <= buf_samedw_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_samedw_2 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
buf_samedw_2 <= buf_samedw_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_samedw_1 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
buf_samedw_1 <= buf_samedw_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_samedw_0 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
buf_samedw_0 <= buf_samedw_in[0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_write <= 1'h0;
|
|
end else if (obuf_wr_en) begin
|
|
if (ibuf_buf_byp) begin
|
|
obuf_write <= io_lsu_pkt_r_bits_store;
|
|
end else begin
|
|
obuf_write <= _T_1202;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_busm_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_cmd_done <= 1'h0;
|
|
end else begin
|
|
obuf_cmd_done <= _T_1305 & _T_4860;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_busm_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_data_done <= 1'h0;
|
|
end else begin
|
|
obuf_data_done <= _T_1305 & _T_4861;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_nosend <= 1'h0;
|
|
end else if (obuf_wr_en) begin
|
|
obuf_nosend <= obuf_nosend_in;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_addr <= 32'h0;
|
|
end else if (ibuf_buf_byp) begin
|
|
obuf_addr <= io_lsu_addr_r;
|
|
end else begin
|
|
obuf_addr <= _T_1289;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_sz_0 <= 2'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
if (ibuf_drainvec_vld[0]) begin
|
|
buf_sz_0 <= ibuf_sz;
|
|
end else begin
|
|
buf_sz_0 <= ibuf_sz_in;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_sz_1 <= 2'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
if (ibuf_drainvec_vld[1]) begin
|
|
buf_sz_1 <= ibuf_sz;
|
|
end else begin
|
|
buf_sz_1 <= ibuf_sz_in;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_sz_2 <= 2'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
if (ibuf_drainvec_vld[2]) begin
|
|
buf_sz_2 <= ibuf_sz;
|
|
end else begin
|
|
buf_sz_2 <= ibuf_sz_in;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_sz_3 <= 2'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
if (ibuf_drainvec_vld[3]) begin
|
|
buf_sz_3 <= ibuf_sz;
|
|
end else begin
|
|
buf_sz_3 <= ibuf_sz_in;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_sideeffect <= 1'h0;
|
|
end else if (obuf_wr_en) begin
|
|
if (ibuf_buf_byp) begin
|
|
obuf_sideeffect <= io_is_sideeffects_r;
|
|
end else begin
|
|
obuf_sideeffect <= _T_1051;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_busm_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_rdrsp_pend <= 1'h0;
|
|
end else begin
|
|
obuf_rdrsp_pend <= _T_1330 | _T_1334;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_busm_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_rdrsp_tag <= 3'h0;
|
|
end else if (_T_1332) begin
|
|
obuf_rdrsp_tag <= obuf_tag0;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualhi_3 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
buf_dualhi_3 <= buf_dualhi_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualhi_2 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
buf_dualhi_2 <= buf_dualhi_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualhi_1 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
buf_dualhi_1 <= buf_dualhi_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualhi_0 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
buf_dualhi_0 <= buf_dualhi_in[0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_sz <= 2'h0;
|
|
end else if (obuf_wr_en) begin
|
|
if (ibuf_buf_byp) begin
|
|
obuf_sz <= ibuf_sz_in;
|
|
end else begin
|
|
obuf_sz <= _T_1302;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_byteen <= 8'h0;
|
|
end else if (obuf_wr_en) begin
|
|
obuf_byteen <= obuf_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_data <= 64'h0;
|
|
end else begin
|
|
obuf_data <= {_T_1620,_T_1579};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_rspageQ_0 <= 4'h0;
|
|
end else begin
|
|
buf_rspageQ_0 <= {_T_3173,_T_3162};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_rspageQ_1 <= 4'h0;
|
|
end else begin
|
|
buf_rspageQ_1 <= {_T_3188,_T_3177};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_rspageQ_2 <= 4'h0;
|
|
end else begin
|
|
buf_rspageQ_2 <= {_T_3203,_T_3192};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_rspageQ_3 <= 4'h0;
|
|
end else begin
|
|
buf_rspageQ_3 <= {_T_3218,_T_3207};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4307 <= 1'h0;
|
|
end else if (buf_ldfwd_en_3) begin
|
|
if (_T_4107) begin
|
|
_T_4307 <= 1'h0;
|
|
end else if (_T_4130) begin
|
|
_T_4307 <= 1'h0;
|
|
end else begin
|
|
_T_4307 <= _T_4134;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4305 <= 1'h0;
|
|
end else if (buf_ldfwd_en_2) begin
|
|
if (_T_3914) begin
|
|
_T_4305 <= 1'h0;
|
|
end else if (_T_3937) begin
|
|
_T_4305 <= 1'h0;
|
|
end else begin
|
|
_T_4305 <= _T_3941;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4303 <= 1'h0;
|
|
end else if (buf_ldfwd_en_1) begin
|
|
if (_T_3721) begin
|
|
_T_4303 <= 1'h0;
|
|
end else if (_T_3744) begin
|
|
_T_4303 <= 1'h0;
|
|
end else begin
|
|
_T_4303 <= _T_3748;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4301 <= 1'h0;
|
|
end else if (buf_ldfwd_en_0) begin
|
|
if (_T_3528) begin
|
|
_T_4301 <= 1'h0;
|
|
end else if (_T_3551) begin
|
|
_T_4301 <= 1'h0;
|
|
end else begin
|
|
_T_4301 <= _T_3555;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ldfwdtag_0 <= 2'h0;
|
|
end else if (buf_ldfwd_en_0) begin
|
|
if (_T_3528) begin
|
|
buf_ldfwdtag_0 <= 2'h0;
|
|
end else if (_T_3551) begin
|
|
buf_ldfwdtag_0 <= 2'h0;
|
|
end else if (_T_3555) begin
|
|
buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0];
|
|
end else begin
|
|
buf_ldfwdtag_0 <= 2'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualtag_0 <= 2'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
if (ibuf_drainvec_vld[0]) begin
|
|
buf_dualtag_0 <= ibuf_dualtag;
|
|
end else if (_T_3343) begin
|
|
buf_dualtag_0 <= WrPtr0_r;
|
|
end else begin
|
|
buf_dualtag_0 <= WrPtr1_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ldfwdtag_3 <= 2'h0;
|
|
end else if (buf_ldfwd_en_3) begin
|
|
if (_T_4107) begin
|
|
buf_ldfwdtag_3 <= 2'h0;
|
|
end else if (_T_4130) begin
|
|
buf_ldfwdtag_3 <= 2'h0;
|
|
end else if (_T_4134) begin
|
|
buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0];
|
|
end else begin
|
|
buf_ldfwdtag_3 <= 2'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ldfwdtag_2 <= 2'h0;
|
|
end else if (buf_ldfwd_en_2) begin
|
|
if (_T_3914) begin
|
|
buf_ldfwdtag_2 <= 2'h0;
|
|
end else if (_T_3937) begin
|
|
buf_ldfwdtag_2 <= 2'h0;
|
|
end else if (_T_3941) begin
|
|
buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0];
|
|
end else begin
|
|
buf_ldfwdtag_2 <= 2'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ldfwdtag_1 <= 2'h0;
|
|
end else if (buf_ldfwd_en_1) begin
|
|
if (_T_3721) begin
|
|
buf_ldfwdtag_1 <= 2'h0;
|
|
end else if (_T_3744) begin
|
|
buf_ldfwdtag_1 <= 2'h0;
|
|
end else if (_T_3748) begin
|
|
buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0];
|
|
end else begin
|
|
buf_ldfwdtag_1 <= 2'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualtag_1 <= 2'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
if (ibuf_drainvec_vld[1]) begin
|
|
buf_dualtag_1 <= ibuf_dualtag;
|
|
end else if (_T_3352) begin
|
|
buf_dualtag_1 <= WrPtr0_r;
|
|
end else begin
|
|
buf_dualtag_1 <= WrPtr1_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualtag_2 <= 2'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
if (ibuf_drainvec_vld[2]) begin
|
|
buf_dualtag_2 <= ibuf_dualtag;
|
|
end else if (_T_3361) begin
|
|
buf_dualtag_2 <= WrPtr0_r;
|
|
end else begin
|
|
buf_dualtag_2 <= WrPtr1_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualtag_3 <= 2'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
if (ibuf_drainvec_vld[3]) begin
|
|
buf_dualtag_3 <= ibuf_dualtag;
|
|
end else if (_T_3370) begin
|
|
buf_dualtag_3 <= WrPtr0_r;
|
|
end else begin
|
|
buf_dualtag_3 <= WrPtr1_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4336 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
_T_4336 <= buf_unsign_in[0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4339 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
_T_4339 <= buf_unsign_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4342 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
_T_4342 <= buf_unsign_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4345 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
_T_4345 <= buf_unsign_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4411 <= 1'h0;
|
|
end else begin
|
|
_T_4411 <= _T_4408 & _T_4409;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4406 <= 1'h0;
|
|
end else begin
|
|
_T_4406 <= _T_4403 & _T_4404;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4401 <= 1'h0;
|
|
end else begin
|
|
_T_4401 <= _T_4398 & _T_4399;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4396 <= 1'h0;
|
|
end else begin
|
|
_T_4396 <= _T_4393 & _T_4394;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_nonblock_load_valid_r <= 1'h0;
|
|
end else begin
|
|
lsu_nonblock_load_valid_r <= io_lsu_nonblock_load_valid_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4984 <= 1'h0;
|
|
end else begin
|
|
_T_4984 <= _T_4981 & _T_4518;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_lsu_bus_intf(
|
|
input clock,
|
|
input reset,
|
|
input io_scan_mode,
|
|
input io_dec_tlu_external_ldfwd_disable,
|
|
input io_dec_tlu_wb_coalescing_disable,
|
|
input io_dec_tlu_sideeffect_posted_disable,
|
|
input io_lsu_c1_m_clk,
|
|
input io_lsu_c1_r_clk,
|
|
input io_lsu_c2_r_clk,
|
|
input io_lsu_bus_ibuf_c1_clk,
|
|
input io_lsu_bus_obuf_c1_clk,
|
|
input io_lsu_bus_buf_c1_clk,
|
|
input io_lsu_free_c2_clk,
|
|
input io_free_clk,
|
|
input io_lsu_busm_clk,
|
|
input io_dec_lsu_valid_raw_d,
|
|
input io_lsu_busreq_m,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_by,
|
|
input io_lsu_pkt_m_bits_half,
|
|
input io_lsu_pkt_m_bits_word,
|
|
input io_lsu_pkt_m_bits_load,
|
|
input io_lsu_pkt_r_valid,
|
|
input io_lsu_pkt_r_bits_by,
|
|
input io_lsu_pkt_r_bits_half,
|
|
input io_lsu_pkt_r_bits_word,
|
|
input io_lsu_pkt_r_bits_load,
|
|
input io_lsu_pkt_r_bits_store,
|
|
input io_lsu_pkt_r_bits_unsign,
|
|
input [31:0] io_lsu_addr_d,
|
|
input [31:0] io_lsu_addr_m,
|
|
input [31:0] io_lsu_addr_r,
|
|
input [31:0] io_end_addr_d,
|
|
input [31:0] io_end_addr_m,
|
|
input [31:0] io_end_addr_r,
|
|
input [31:0] io_store_data_r,
|
|
input io_dec_tlu_force_halt,
|
|
input io_lsu_commit_r,
|
|
input io_is_sideeffects_m,
|
|
input io_flush_m_up,
|
|
input io_flush_r,
|
|
output io_lsu_busreq_r,
|
|
output io_lsu_bus_buffer_pend_any,
|
|
output io_lsu_bus_buffer_full_any,
|
|
output io_lsu_bus_buffer_empty_any,
|
|
output [31:0] io_bus_read_data_m,
|
|
output io_lsu_imprecise_error_load_any,
|
|
output io_lsu_imprecise_error_store_any,
|
|
output [31:0] io_lsu_imprecise_error_addr_any,
|
|
output io_lsu_nonblock_load_valid_m,
|
|
output [1:0] io_lsu_nonblock_load_tag_m,
|
|
output io_lsu_nonblock_load_inv_r,
|
|
output [1:0] io_lsu_nonblock_load_inv_tag_r,
|
|
output io_lsu_nonblock_load_data_valid,
|
|
output io_lsu_nonblock_load_data_error,
|
|
output [1:0] io_lsu_nonblock_load_data_tag,
|
|
output [31:0] io_lsu_nonblock_load_data,
|
|
output io_lsu_pmu_bus_trxn,
|
|
output io_lsu_pmu_bus_misaligned,
|
|
output io_lsu_pmu_bus_error,
|
|
output io_lsu_pmu_bus_busy,
|
|
output io_lsu_axi_awvalid,
|
|
input io_lsu_axi_awready,
|
|
output [2:0] io_lsu_axi_awid,
|
|
output [31:0] io_lsu_axi_awaddr,
|
|
output [3:0] io_lsu_axi_awregion,
|
|
output [2:0] io_lsu_axi_awsize,
|
|
output [3:0] io_lsu_axi_awcache,
|
|
output io_lsu_axi_wvalid,
|
|
input io_lsu_axi_wready,
|
|
output [63:0] io_lsu_axi_wdata,
|
|
output [7:0] io_lsu_axi_wstrb,
|
|
input io_lsu_axi_bvalid,
|
|
input [1:0] io_lsu_axi_bresp,
|
|
input [2:0] io_lsu_axi_bid,
|
|
output io_lsu_axi_arvalid,
|
|
input io_lsu_axi_arready,
|
|
output [2:0] io_lsu_axi_arid,
|
|
output [31:0] io_lsu_axi_araddr,
|
|
output [3:0] io_lsu_axi_arregion,
|
|
output [2:0] io_lsu_axi_arsize,
|
|
output [3:0] io_lsu_axi_arcache,
|
|
input io_lsu_axi_rvalid,
|
|
input [2:0] io_lsu_axi_rid,
|
|
input [63:0] io_lsu_axi_rdata,
|
|
input io_lsu_bus_clk_en
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire bus_buffer_clock; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_reset; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_scan_mode; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_dec_tlu_force_halt; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_c2_r_clk; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_bus_obuf_c1_clk; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_free_c2_clk; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_busm_clk; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pkt_m_valid; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pkt_m_bits_load; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_by; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_half; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_word; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_load; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [31:0] bus_buffer_io_lsu_addr_m; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [31:0] bus_buffer_io_end_addr_m; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [31:0] bus_buffer_io_lsu_addr_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [31:0] bus_buffer_io_end_addr_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [31:0] bus_buffer_io_store_data_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_no_word_merge_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_no_dword_merge_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_ld_full_hit_m; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_flush_m_up; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_flush_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_commit_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_is_sideeffects_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_ldst_dual_d; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_ldst_dual_m; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_ldst_dual_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_axi_wready; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_axi_bvalid; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [1:0] bus_buffer_io_lsu_axi_bresp; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_bid; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_axi_arready; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_axi_rvalid; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_rid; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [63:0] bus_buffer_io_lsu_axi_rdata; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_bus_clk_en; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_busreq_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_bus_buffer_full_any; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_imprecise_error_load_any; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [31:0] bus_buffer_io_lsu_imprecise_error_addr_any; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_nonblock_load_valid_m; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [1:0] bus_buffer_io_lsu_nonblock_load_tag_m; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_nonblock_load_inv_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [1:0] bus_buffer_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_nonblock_load_data_valid; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [1:0] bus_buffer_io_lsu_nonblock_load_data_tag; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [31:0] bus_buffer_io_lsu_nonblock_load_data; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pmu_bus_trxn; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pmu_bus_misaligned; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pmu_bus_error; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_pmu_bus_busy; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_axi_awvalid; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_axi_awready; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_awid; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [31:0] bus_buffer_io_lsu_axi_awaddr; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [3:0] bus_buffer_io_lsu_axi_awregion; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_awsize; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [3:0] bus_buffer_io_lsu_axi_awcache; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_axi_wvalid; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [63:0] bus_buffer_io_lsu_axi_wdata; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [7:0] bus_buffer_io_lsu_axi_wstrb; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_axi_bready; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_axi_arvalid; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_arid; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [31:0] bus_buffer_io_lsu_axi_araddr; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [3:0] bus_buffer_io_lsu_axi_arregion; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_arsize; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [3:0] bus_buffer_io_lsu_axi_arcache; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire bus_buffer_io_lsu_axi_rready; // @[el2_lsu_bus_intf.scala 167:39]
|
|
wire [3:0] _T_3 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_4 = io_lsu_pkt_m_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_5 = io_lsu_pkt_m_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72]
|
|
wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72]
|
|
wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[el2_lsu_bus_intf.scala 278:51]
|
|
wire _T_17 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[el2_lsu_bus_intf.scala 279:71]
|
|
wire _T_18 = ~_T_17; // @[el2_lsu_bus_intf.scala 279:53]
|
|
wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_18; // @[el2_lsu_bus_intf.scala 279:51]
|
|
reg ldst_dual_r; // @[el2_lsu_bus_intf.scala 324:33]
|
|
wire _T_20 = ~ldst_dual_r; // @[el2_lsu_bus_intf.scala 280:48]
|
|
wire _T_21 = io_lsu_busreq_r & _T_20; // @[el2_lsu_bus_intf.scala 280:46]
|
|
wire _T_22 = _T_21 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 280:61]
|
|
wire _T_23 = ~addr_match_word_lo_r_m; // @[el2_lsu_bus_intf.scala 280:107]
|
|
wire _T_24 = io_lsu_pkt_m_bits_load | _T_23; // @[el2_lsu_bus_intf.scala 280:105]
|
|
wire _T_29 = ~addr_match_dw_lo_r_m; // @[el2_lsu_bus_intf.scala 281:107]
|
|
wire _T_30 = io_lsu_pkt_m_bits_load | _T_29; // @[el2_lsu_bus_intf.scala 281:105]
|
|
wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[el2_lsu_bus_intf.scala 283:49]
|
|
wire [6:0] _T_34 = _GEN_0 << io_lsu_addr_m[1:0]; // @[el2_lsu_bus_intf.scala 283:49]
|
|
reg [3:0] ldst_byteen_r; // @[el2_lsu_bus_intf.scala 326:33]
|
|
wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[el2_lsu_bus_intf.scala 284:49]
|
|
wire [6:0] _T_37 = _GEN_1 << io_lsu_addr_r[1:0]; // @[el2_lsu_bus_intf.scala 284:49]
|
|
wire [4:0] _T_40 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[el2_lsu_bus_intf.scala 285:52]
|
|
wire [62:0] _T_41 = _GEN_2 << _T_40; // @[el2_lsu_bus_intf.scala 285:52]
|
|
wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[el2_lsu_bus_intf.scala 283:27]
|
|
wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[el2_lsu_bus_intf.scala 286:47]
|
|
wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[el2_lsu_bus_intf.scala 287:47]
|
|
wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_37}; // @[el2_lsu_bus_intf.scala 284:27]
|
|
wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[el2_lsu_bus_intf.scala 288:47]
|
|
wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[el2_lsu_bus_intf.scala 289:47]
|
|
wire [63:0] store_data_ext_r = {{1'd0}, _T_41}; // @[el2_lsu_bus_intf.scala 285:27]
|
|
wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[el2_lsu_bus_intf.scala 291:46]
|
|
wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[el2_lsu_bus_intf.scala 292:46]
|
|
wire _T_50 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 293:51]
|
|
wire _T_51 = _T_50 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 293:76]
|
|
wire _T_52 = _T_51 & io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 293:97]
|
|
wire ld_addr_rhit_lo_lo = _T_52 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 293:123]
|
|
wire _T_56 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 294:51]
|
|
wire _T_57 = _T_56 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 294:76]
|
|
wire _T_58 = _T_57 & io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 294:97]
|
|
wire ld_addr_rhit_lo_hi = _T_58 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 294:123]
|
|
wire _T_62 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 295:51]
|
|
wire _T_63 = _T_62 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 295:76]
|
|
wire _T_64 = _T_63 & io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 295:97]
|
|
wire ld_addr_rhit_hi_lo = _T_64 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 295:123]
|
|
wire _T_68 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 296:51]
|
|
wire _T_69 = _T_68 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 296:76]
|
|
wire _T_70 = _T_69 & io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 296:97]
|
|
wire ld_addr_rhit_hi_hi = _T_70 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 296:123]
|
|
wire _T_73 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[el2_lsu_bus_intf.scala 298:70]
|
|
wire _T_75 = _T_73 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 298:92]
|
|
wire _T_77 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[el2_lsu_bus_intf.scala 298:70]
|
|
wire _T_79 = _T_77 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 298:92]
|
|
wire _T_81 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[el2_lsu_bus_intf.scala 298:70]
|
|
wire _T_83 = _T_81 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 298:92]
|
|
wire _T_85 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[el2_lsu_bus_intf.scala 298:70]
|
|
wire _T_87 = _T_85 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 298:92]
|
|
wire [3:0] ld_byte_rhit_lo_lo = {_T_87,_T_83,_T_79,_T_75}; // @[Cat.scala 29:58]
|
|
wire _T_92 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[el2_lsu_bus_intf.scala 299:70]
|
|
wire _T_94 = _T_92 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 299:92]
|
|
wire _T_96 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[el2_lsu_bus_intf.scala 299:70]
|
|
wire _T_98 = _T_96 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 299:92]
|
|
wire _T_100 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[el2_lsu_bus_intf.scala 299:70]
|
|
wire _T_102 = _T_100 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 299:92]
|
|
wire _T_104 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[el2_lsu_bus_intf.scala 299:70]
|
|
wire _T_106 = _T_104 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 299:92]
|
|
wire [3:0] ld_byte_rhit_lo_hi = {_T_106,_T_102,_T_98,_T_94}; // @[Cat.scala 29:58]
|
|
wire _T_111 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[el2_lsu_bus_intf.scala 300:70]
|
|
wire _T_113 = _T_111 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 300:92]
|
|
wire _T_115 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[el2_lsu_bus_intf.scala 300:70]
|
|
wire _T_117 = _T_115 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 300:92]
|
|
wire _T_119 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[el2_lsu_bus_intf.scala 300:70]
|
|
wire _T_121 = _T_119 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 300:92]
|
|
wire _T_123 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[el2_lsu_bus_intf.scala 300:70]
|
|
wire _T_125 = _T_123 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 300:92]
|
|
wire [3:0] ld_byte_rhit_hi_lo = {_T_125,_T_121,_T_117,_T_113}; // @[Cat.scala 29:58]
|
|
wire _T_130 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[el2_lsu_bus_intf.scala 301:70]
|
|
wire _T_132 = _T_130 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 301:92]
|
|
wire _T_134 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[el2_lsu_bus_intf.scala 301:70]
|
|
wire _T_136 = _T_134 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 301:92]
|
|
wire _T_138 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[el2_lsu_bus_intf.scala 301:70]
|
|
wire _T_140 = _T_138 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 301:92]
|
|
wire _T_142 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[el2_lsu_bus_intf.scala 301:70]
|
|
wire _T_144 = _T_142 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 301:92]
|
|
wire [3:0] ld_byte_rhit_hi_hi = {_T_144,_T_140,_T_136,_T_132}; // @[Cat.scala 29:58]
|
|
wire _T_150 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[el2_lsu_bus_intf.scala 303:73]
|
|
wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[el2_lsu_bus_intf.scala 215:38]
|
|
wire _T_152 = _T_150 | ld_byte_hit_buf_lo[0]; // @[el2_lsu_bus_intf.scala 303:97]
|
|
wire _T_155 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[el2_lsu_bus_intf.scala 303:73]
|
|
wire _T_157 = _T_155 | ld_byte_hit_buf_lo[1]; // @[el2_lsu_bus_intf.scala 303:97]
|
|
wire _T_160 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[el2_lsu_bus_intf.scala 303:73]
|
|
wire _T_162 = _T_160 | ld_byte_hit_buf_lo[2]; // @[el2_lsu_bus_intf.scala 303:97]
|
|
wire _T_165 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[el2_lsu_bus_intf.scala 303:73]
|
|
wire _T_167 = _T_165 | ld_byte_hit_buf_lo[3]; // @[el2_lsu_bus_intf.scala 303:97]
|
|
wire [3:0] ld_byte_hit_lo = {_T_167,_T_162,_T_157,_T_152}; // @[Cat.scala 29:58]
|
|
wire _T_173 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[el2_lsu_bus_intf.scala 304:73]
|
|
wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[el2_lsu_bus_intf.scala 216:38]
|
|
wire _T_175 = _T_173 | ld_byte_hit_buf_hi[0]; // @[el2_lsu_bus_intf.scala 304:97]
|
|
wire _T_178 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[el2_lsu_bus_intf.scala 304:73]
|
|
wire _T_180 = _T_178 | ld_byte_hit_buf_hi[1]; // @[el2_lsu_bus_intf.scala 304:97]
|
|
wire _T_183 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[el2_lsu_bus_intf.scala 304:73]
|
|
wire _T_185 = _T_183 | ld_byte_hit_buf_hi[2]; // @[el2_lsu_bus_intf.scala 304:97]
|
|
wire _T_188 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[el2_lsu_bus_intf.scala 304:73]
|
|
wire _T_190 = _T_188 | ld_byte_hit_buf_hi[3]; // @[el2_lsu_bus_intf.scala 304:97]
|
|
wire [3:0] ld_byte_hit_hi = {_T_190,_T_185,_T_180,_T_175}; // @[Cat.scala 29:58]
|
|
wire [3:0] ld_byte_rhit_lo = {_T_165,_T_160,_T_155,_T_150}; // @[Cat.scala 29:58]
|
|
wire [3:0] ld_byte_rhit_hi = {_T_188,_T_183,_T_178,_T_173}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_228 = ld_byte_rhit_lo_lo[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_229 = ld_byte_rhit_hi_lo[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_230 = _T_228 | _T_229; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_236 = ld_byte_rhit_lo_lo[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_237 = ld_byte_rhit_hi_lo[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_238 = _T_236 | _T_237; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_244 = ld_byte_rhit_lo_lo[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_245 = ld_byte_rhit_hi_lo[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_246 = _T_244 | _T_245; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_252 = ld_byte_rhit_lo_lo[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_253 = ld_byte_rhit_hi_lo[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_254 = _T_252 | _T_253; // @[Mux.scala 27:72]
|
|
wire [31:0] ld_fwddata_rpipe_lo = {_T_254,_T_246,_T_238,_T_230}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_263 = ld_byte_rhit_lo_hi[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_264 = ld_byte_rhit_hi_hi[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_265 = _T_263 | _T_264; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_271 = ld_byte_rhit_lo_hi[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_272 = ld_byte_rhit_hi_hi[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_273 = _T_271 | _T_272; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_279 = ld_byte_rhit_lo_hi[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_280 = ld_byte_rhit_hi_hi[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_281 = _T_279 | _T_280; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_287 = ld_byte_rhit_lo_hi[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_288 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_289 = _T_287 | _T_288; // @[Mux.scala 27:72]
|
|
wire [31:0] ld_fwddata_rpipe_hi = {_T_289,_T_281,_T_273,_T_265}; // @[Cat.scala 29:58]
|
|
wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[el2_lsu_bus_intf.scala 217:38]
|
|
wire [7:0] _T_297 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[el2_lsu_bus_intf.scala 309:54]
|
|
wire [7:0] _T_301 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[el2_lsu_bus_intf.scala 309:54]
|
|
wire [7:0] _T_305 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[el2_lsu_bus_intf.scala 309:54]
|
|
wire [7:0] _T_309 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[el2_lsu_bus_intf.scala 309:54]
|
|
wire [31:0] _T_312 = {_T_309,_T_305,_T_301,_T_297}; // @[Cat.scala 29:58]
|
|
wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[el2_lsu_bus_intf.scala 218:38]
|
|
wire [7:0] _T_316 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[el2_lsu_bus_intf.scala 310:54]
|
|
wire [7:0] _T_320 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[el2_lsu_bus_intf.scala 310:54]
|
|
wire [7:0] _T_324 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[el2_lsu_bus_intf.scala 310:54]
|
|
wire [7:0] _T_328 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[el2_lsu_bus_intf.scala 310:54]
|
|
wire [31:0] _T_331 = {_T_328,_T_324,_T_320,_T_316}; // @[Cat.scala 29:58]
|
|
wire _T_334 = ~ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 311:72]
|
|
wire _T_335 = ld_byte_hit_lo[0] | _T_334; // @[el2_lsu_bus_intf.scala 311:70]
|
|
wire _T_338 = ~ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 311:72]
|
|
wire _T_339 = ld_byte_hit_lo[1] | _T_338; // @[el2_lsu_bus_intf.scala 311:70]
|
|
wire _T_342 = ~ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 311:72]
|
|
wire _T_343 = ld_byte_hit_lo[2] | _T_342; // @[el2_lsu_bus_intf.scala 311:70]
|
|
wire _T_346 = ~ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 311:72]
|
|
wire _T_347 = ld_byte_hit_lo[3] | _T_346; // @[el2_lsu_bus_intf.scala 311:70]
|
|
wire _T_348 = _T_335 & _T_339; // @[el2_lsu_bus_intf.scala 311:111]
|
|
wire _T_349 = _T_348 & _T_343; // @[el2_lsu_bus_intf.scala 311:111]
|
|
wire ld_full_hit_lo_m = _T_349 & _T_347; // @[el2_lsu_bus_intf.scala 311:111]
|
|
wire _T_353 = ~ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 312:72]
|
|
wire _T_354 = ld_byte_hit_hi[0] | _T_353; // @[el2_lsu_bus_intf.scala 312:70]
|
|
wire _T_357 = ~ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 312:72]
|
|
wire _T_358 = ld_byte_hit_hi[1] | _T_357; // @[el2_lsu_bus_intf.scala 312:70]
|
|
wire _T_361 = ~ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 312:72]
|
|
wire _T_362 = ld_byte_hit_hi[2] | _T_361; // @[el2_lsu_bus_intf.scala 312:70]
|
|
wire _T_365 = ~ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 312:72]
|
|
wire _T_366 = ld_byte_hit_hi[3] | _T_365; // @[el2_lsu_bus_intf.scala 312:70]
|
|
wire _T_367 = _T_354 & _T_358; // @[el2_lsu_bus_intf.scala 312:111]
|
|
wire _T_368 = _T_367 & _T_362; // @[el2_lsu_bus_intf.scala 312:111]
|
|
wire ld_full_hit_hi_m = _T_368 & _T_366; // @[el2_lsu_bus_intf.scala 312:111]
|
|
wire _T_370 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[el2_lsu_bus_intf.scala 313:47]
|
|
wire _T_371 = _T_370 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 313:66]
|
|
wire _T_372 = _T_371 & io_lsu_pkt_m_bits_load; // @[el2_lsu_bus_intf.scala 313:84]
|
|
wire _T_373 = ~io_is_sideeffects_m; // @[el2_lsu_bus_intf.scala 313:111]
|
|
wire [63:0] ld_fwddata_hi = {{32'd0}, _T_331}; // @[el2_lsu_bus_intf.scala 310:27]
|
|
wire [63:0] ld_fwddata_lo = {{32'd0}, _T_312}; // @[el2_lsu_bus_intf.scala 309:27]
|
|
wire [63:0] _T_377 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[el2_lsu_bus_intf.scala 314:83]
|
|
wire [5:0] _T_379 = 4'h8 * _GEN_3; // @[el2_lsu_bus_intf.scala 314:83]
|
|
wire [63:0] ld_fwddata_m = _T_377 >> _T_379; // @[el2_lsu_bus_intf.scala 314:76]
|
|
reg lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 318:32]
|
|
reg ldst_dual_m; // @[el2_lsu_bus_intf.scala 321:27]
|
|
reg is_sideeffects_r; // @[el2_lsu_bus_intf.scala 325:33]
|
|
el2_lsu_bus_buffer bus_buffer ( // @[el2_lsu_bus_intf.scala 167:39]
|
|
.clock(bus_buffer_clock),
|
|
.reset(bus_buffer_reset),
|
|
.io_scan_mode(bus_buffer_io_scan_mode),
|
|
.io_dec_tlu_external_ldfwd_disable(bus_buffer_io_dec_tlu_external_ldfwd_disable),
|
|
.io_dec_tlu_wb_coalescing_disable(bus_buffer_io_dec_tlu_wb_coalescing_disable),
|
|
.io_dec_tlu_sideeffect_posted_disable(bus_buffer_io_dec_tlu_sideeffect_posted_disable),
|
|
.io_dec_tlu_force_halt(bus_buffer_io_dec_tlu_force_halt),
|
|
.io_lsu_c2_r_clk(bus_buffer_io_lsu_c2_r_clk),
|
|
.io_lsu_bus_ibuf_c1_clk(bus_buffer_io_lsu_bus_ibuf_c1_clk),
|
|
.io_lsu_bus_obuf_c1_clk(bus_buffer_io_lsu_bus_obuf_c1_clk),
|
|
.io_lsu_bus_buf_c1_clk(bus_buffer_io_lsu_bus_buf_c1_clk),
|
|
.io_lsu_free_c2_clk(bus_buffer_io_lsu_free_c2_clk),
|
|
.io_lsu_busm_clk(bus_buffer_io_lsu_busm_clk),
|
|
.io_dec_lsu_valid_raw_d(bus_buffer_io_dec_lsu_valid_raw_d),
|
|
.io_lsu_pkt_m_valid(bus_buffer_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_load(bus_buffer_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_r_bits_by(bus_buffer_io_lsu_pkt_r_bits_by),
|
|
.io_lsu_pkt_r_bits_half(bus_buffer_io_lsu_pkt_r_bits_half),
|
|
.io_lsu_pkt_r_bits_word(bus_buffer_io_lsu_pkt_r_bits_word),
|
|
.io_lsu_pkt_r_bits_load(bus_buffer_io_lsu_pkt_r_bits_load),
|
|
.io_lsu_pkt_r_bits_store(bus_buffer_io_lsu_pkt_r_bits_store),
|
|
.io_lsu_pkt_r_bits_unsign(bus_buffer_io_lsu_pkt_r_bits_unsign),
|
|
.io_lsu_addr_m(bus_buffer_io_lsu_addr_m),
|
|
.io_end_addr_m(bus_buffer_io_end_addr_m),
|
|
.io_lsu_addr_r(bus_buffer_io_lsu_addr_r),
|
|
.io_end_addr_r(bus_buffer_io_end_addr_r),
|
|
.io_store_data_r(bus_buffer_io_store_data_r),
|
|
.io_no_word_merge_r(bus_buffer_io_no_word_merge_r),
|
|
.io_no_dword_merge_r(bus_buffer_io_no_dword_merge_r),
|
|
.io_lsu_busreq_m(bus_buffer_io_lsu_busreq_m),
|
|
.io_ld_full_hit_m(bus_buffer_io_ld_full_hit_m),
|
|
.io_flush_m_up(bus_buffer_io_flush_m_up),
|
|
.io_flush_r(bus_buffer_io_flush_r),
|
|
.io_lsu_commit_r(bus_buffer_io_lsu_commit_r),
|
|
.io_is_sideeffects_r(bus_buffer_io_is_sideeffects_r),
|
|
.io_ldst_dual_d(bus_buffer_io_ldst_dual_d),
|
|
.io_ldst_dual_m(bus_buffer_io_ldst_dual_m),
|
|
.io_ldst_dual_r(bus_buffer_io_ldst_dual_r),
|
|
.io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m),
|
|
.io_lsu_axi_wready(bus_buffer_io_lsu_axi_wready),
|
|
.io_lsu_axi_bvalid(bus_buffer_io_lsu_axi_bvalid),
|
|
.io_lsu_axi_bresp(bus_buffer_io_lsu_axi_bresp),
|
|
.io_lsu_axi_bid(bus_buffer_io_lsu_axi_bid),
|
|
.io_lsu_axi_arready(bus_buffer_io_lsu_axi_arready),
|
|
.io_lsu_axi_rvalid(bus_buffer_io_lsu_axi_rvalid),
|
|
.io_lsu_axi_rid(bus_buffer_io_lsu_axi_rid),
|
|
.io_lsu_axi_rdata(bus_buffer_io_lsu_axi_rdata),
|
|
.io_lsu_bus_clk_en(bus_buffer_io_lsu_bus_clk_en),
|
|
.io_lsu_bus_clk_en_q(bus_buffer_io_lsu_bus_clk_en_q),
|
|
.io_lsu_busreq_r(bus_buffer_io_lsu_busreq_r),
|
|
.io_lsu_bus_buffer_pend_any(bus_buffer_io_lsu_bus_buffer_pend_any),
|
|
.io_lsu_bus_buffer_full_any(bus_buffer_io_lsu_bus_buffer_full_any),
|
|
.io_lsu_bus_buffer_empty_any(bus_buffer_io_lsu_bus_buffer_empty_any),
|
|
.io_ld_byte_hit_buf_lo(bus_buffer_io_ld_byte_hit_buf_lo),
|
|
.io_ld_byte_hit_buf_hi(bus_buffer_io_ld_byte_hit_buf_hi),
|
|
.io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo),
|
|
.io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi),
|
|
.io_lsu_imprecise_error_load_any(bus_buffer_io_lsu_imprecise_error_load_any),
|
|
.io_lsu_imprecise_error_store_any(bus_buffer_io_lsu_imprecise_error_store_any),
|
|
.io_lsu_imprecise_error_addr_any(bus_buffer_io_lsu_imprecise_error_addr_any),
|
|
.io_lsu_nonblock_load_valid_m(bus_buffer_io_lsu_nonblock_load_valid_m),
|
|
.io_lsu_nonblock_load_tag_m(bus_buffer_io_lsu_nonblock_load_tag_m),
|
|
.io_lsu_nonblock_load_inv_r(bus_buffer_io_lsu_nonblock_load_inv_r),
|
|
.io_lsu_nonblock_load_inv_tag_r(bus_buffer_io_lsu_nonblock_load_inv_tag_r),
|
|
.io_lsu_nonblock_load_data_valid(bus_buffer_io_lsu_nonblock_load_data_valid),
|
|
.io_lsu_nonblock_load_data_error(bus_buffer_io_lsu_nonblock_load_data_error),
|
|
.io_lsu_nonblock_load_data_tag(bus_buffer_io_lsu_nonblock_load_data_tag),
|
|
.io_lsu_nonblock_load_data(bus_buffer_io_lsu_nonblock_load_data),
|
|
.io_lsu_pmu_bus_trxn(bus_buffer_io_lsu_pmu_bus_trxn),
|
|
.io_lsu_pmu_bus_misaligned(bus_buffer_io_lsu_pmu_bus_misaligned),
|
|
.io_lsu_pmu_bus_error(bus_buffer_io_lsu_pmu_bus_error),
|
|
.io_lsu_pmu_bus_busy(bus_buffer_io_lsu_pmu_bus_busy),
|
|
.io_lsu_axi_awvalid(bus_buffer_io_lsu_axi_awvalid),
|
|
.io_lsu_axi_awready(bus_buffer_io_lsu_axi_awready),
|
|
.io_lsu_axi_awid(bus_buffer_io_lsu_axi_awid),
|
|
.io_lsu_axi_awaddr(bus_buffer_io_lsu_axi_awaddr),
|
|
.io_lsu_axi_awregion(bus_buffer_io_lsu_axi_awregion),
|
|
.io_lsu_axi_awsize(bus_buffer_io_lsu_axi_awsize),
|
|
.io_lsu_axi_awcache(bus_buffer_io_lsu_axi_awcache),
|
|
.io_lsu_axi_wvalid(bus_buffer_io_lsu_axi_wvalid),
|
|
.io_lsu_axi_wdata(bus_buffer_io_lsu_axi_wdata),
|
|
.io_lsu_axi_wstrb(bus_buffer_io_lsu_axi_wstrb),
|
|
.io_lsu_axi_bready(bus_buffer_io_lsu_axi_bready),
|
|
.io_lsu_axi_arvalid(bus_buffer_io_lsu_axi_arvalid),
|
|
.io_lsu_axi_arid(bus_buffer_io_lsu_axi_arid),
|
|
.io_lsu_axi_araddr(bus_buffer_io_lsu_axi_araddr),
|
|
.io_lsu_axi_arregion(bus_buffer_io_lsu_axi_arregion),
|
|
.io_lsu_axi_arsize(bus_buffer_io_lsu_axi_arsize),
|
|
.io_lsu_axi_arcache(bus_buffer_io_lsu_axi_arcache),
|
|
.io_lsu_axi_rready(bus_buffer_io_lsu_axi_rready)
|
|
);
|
|
assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[el2_lsu_bus_intf.scala 210:38]
|
|
assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[el2_lsu_bus_intf.scala 211:38]
|
|
assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[el2_lsu_bus_intf.scala 212:38]
|
|
assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[el2_lsu_bus_intf.scala 213:38]
|
|
assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[el2_lsu_bus_intf.scala 315:27]
|
|
assign io_lsu_imprecise_error_load_any = bus_buffer_io_lsu_imprecise_error_load_any; // @[el2_lsu_bus_intf.scala 219:38]
|
|
assign io_lsu_imprecise_error_store_any = bus_buffer_io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_intf.scala 220:38]
|
|
assign io_lsu_imprecise_error_addr_any = bus_buffer_io_lsu_imprecise_error_addr_any; // @[el2_lsu_bus_intf.scala 221:38]
|
|
assign io_lsu_nonblock_load_valid_m = bus_buffer_io_lsu_nonblock_load_valid_m; // @[el2_lsu_bus_intf.scala 222:38]
|
|
assign io_lsu_nonblock_load_tag_m = bus_buffer_io_lsu_nonblock_load_tag_m; // @[el2_lsu_bus_intf.scala 223:38]
|
|
assign io_lsu_nonblock_load_inv_r = bus_buffer_io_lsu_nonblock_load_inv_r; // @[el2_lsu_bus_intf.scala 224:38]
|
|
assign io_lsu_nonblock_load_inv_tag_r = bus_buffer_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu_bus_intf.scala 225:38]
|
|
assign io_lsu_nonblock_load_data_valid = bus_buffer_io_lsu_nonblock_load_data_valid; // @[el2_lsu_bus_intf.scala 226:38]
|
|
assign io_lsu_nonblock_load_data_error = bus_buffer_io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_intf.scala 227:38]
|
|
assign io_lsu_nonblock_load_data_tag = bus_buffer_io_lsu_nonblock_load_data_tag; // @[el2_lsu_bus_intf.scala 228:38]
|
|
assign io_lsu_nonblock_load_data = bus_buffer_io_lsu_nonblock_load_data; // @[el2_lsu_bus_intf.scala 229:38]
|
|
assign io_lsu_pmu_bus_trxn = bus_buffer_io_lsu_pmu_bus_trxn; // @[el2_lsu_bus_intf.scala 230:38]
|
|
assign io_lsu_pmu_bus_misaligned = bus_buffer_io_lsu_pmu_bus_misaligned; // @[el2_lsu_bus_intf.scala 231:38]
|
|
assign io_lsu_pmu_bus_error = bus_buffer_io_lsu_pmu_bus_error; // @[el2_lsu_bus_intf.scala 232:38]
|
|
assign io_lsu_pmu_bus_busy = bus_buffer_io_lsu_pmu_bus_busy; // @[el2_lsu_bus_intf.scala 233:38]
|
|
assign io_lsu_axi_awvalid = bus_buffer_io_lsu_axi_awvalid; // @[el2_lsu_bus_intf.scala 234:38]
|
|
assign io_lsu_axi_awid = bus_buffer_io_lsu_axi_awid; // @[el2_lsu_bus_intf.scala 235:38]
|
|
assign io_lsu_axi_awaddr = bus_buffer_io_lsu_axi_awaddr; // @[el2_lsu_bus_intf.scala 236:38]
|
|
assign io_lsu_axi_awregion = bus_buffer_io_lsu_axi_awregion; // @[el2_lsu_bus_intf.scala 237:38]
|
|
assign io_lsu_axi_awsize = bus_buffer_io_lsu_axi_awsize; // @[el2_lsu_bus_intf.scala 239:38]
|
|
assign io_lsu_axi_awcache = bus_buffer_io_lsu_axi_awcache; // @[el2_lsu_bus_intf.scala 242:38]
|
|
assign io_lsu_axi_wvalid = bus_buffer_io_lsu_axi_wvalid; // @[el2_lsu_bus_intf.scala 245:38]
|
|
assign io_lsu_axi_wdata = bus_buffer_io_lsu_axi_wdata; // @[el2_lsu_bus_intf.scala 246:38]
|
|
assign io_lsu_axi_wstrb = bus_buffer_io_lsu_axi_wstrb; // @[el2_lsu_bus_intf.scala 247:38]
|
|
assign io_lsu_axi_arvalid = bus_buffer_io_lsu_axi_arvalid; // @[el2_lsu_bus_intf.scala 250:38]
|
|
assign io_lsu_axi_arid = bus_buffer_io_lsu_axi_arid; // @[el2_lsu_bus_intf.scala 251:38]
|
|
assign io_lsu_axi_araddr = bus_buffer_io_lsu_axi_araddr; // @[el2_lsu_bus_intf.scala 252:38]
|
|
assign io_lsu_axi_arregion = bus_buffer_io_lsu_axi_arregion; // @[el2_lsu_bus_intf.scala 253:38]
|
|
assign io_lsu_axi_arsize = bus_buffer_io_lsu_axi_arsize; // @[el2_lsu_bus_intf.scala 255:38]
|
|
assign io_lsu_axi_arcache = bus_buffer_io_lsu_axi_arcache; // @[el2_lsu_bus_intf.scala 258:38]
|
|
assign bus_buffer_clock = clock;
|
|
assign bus_buffer_reset = reset;
|
|
assign bus_buffer_io_scan_mode = io_scan_mode; // @[el2_lsu_bus_intf.scala 169:29]
|
|
assign bus_buffer_io_dec_tlu_external_ldfwd_disable = io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_intf.scala 171:51]
|
|
assign bus_buffer_io_dec_tlu_wb_coalescing_disable = io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_intf.scala 172:51]
|
|
assign bus_buffer_io_dec_tlu_sideeffect_posted_disable = io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_intf.scala 173:51]
|
|
assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[el2_lsu_bus_intf.scala 174:51]
|
|
assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[el2_lsu_bus_intf.scala 175:51]
|
|
assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[el2_lsu_bus_intf.scala 176:51]
|
|
assign bus_buffer_io_lsu_bus_obuf_c1_clk = io_lsu_bus_obuf_c1_clk; // @[el2_lsu_bus_intf.scala 177:51]
|
|
assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[el2_lsu_bus_intf.scala 178:51]
|
|
assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[el2_lsu_bus_intf.scala 179:51]
|
|
assign bus_buffer_io_lsu_busm_clk = io_lsu_busm_clk; // @[el2_lsu_bus_intf.scala 180:51]
|
|
assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_intf.scala 181:51]
|
|
assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[el2_lsu_bus_intf.scala 184:27]
|
|
assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[el2_lsu_bus_intf.scala 184:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[el2_lsu_bus_intf.scala 185:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[el2_lsu_bus_intf.scala 185:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[el2_lsu_bus_intf.scala 185:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[el2_lsu_bus_intf.scala 185:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 185:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_intf.scala 185:27]
|
|
assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[el2_lsu_bus_intf.scala 188:51]
|
|
assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[el2_lsu_bus_intf.scala 189:51]
|
|
assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[el2_lsu_bus_intf.scala 190:51]
|
|
assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[el2_lsu_bus_intf.scala 191:51]
|
|
assign bus_buffer_io_store_data_r = io_store_data_r; // @[el2_lsu_bus_intf.scala 192:51]
|
|
assign bus_buffer_io_no_word_merge_r = _T_22 & _T_24; // @[el2_lsu_bus_intf.scala 263:51]
|
|
assign bus_buffer_io_no_dword_merge_r = _T_22 & _T_30; // @[el2_lsu_bus_intf.scala 264:51]
|
|
assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 194:51]
|
|
assign bus_buffer_io_ld_full_hit_m = _T_372 & _T_373; // @[el2_lsu_bus_intf.scala 270:51]
|
|
assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[el2_lsu_bus_intf.scala 195:51]
|
|
assign bus_buffer_io_flush_r = io_flush_r; // @[el2_lsu_bus_intf.scala 196:51]
|
|
assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[el2_lsu_bus_intf.scala 197:51]
|
|
assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[el2_lsu_bus_intf.scala 265:51]
|
|
assign bus_buffer_io_ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[el2_lsu_bus_intf.scala 266:51]
|
|
assign bus_buffer_io_ldst_dual_m = ldst_dual_m; // @[el2_lsu_bus_intf.scala 267:51]
|
|
assign bus_buffer_io_ldst_dual_r = ldst_dual_r; // @[el2_lsu_bus_intf.scala 268:51]
|
|
assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[el2_lsu_bus_intf.scala 269:51]
|
|
assign bus_buffer_io_lsu_axi_wready = io_lsu_axi_wready; // @[el2_lsu_bus_intf.scala 199:51]
|
|
assign bus_buffer_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[el2_lsu_bus_intf.scala 200:51]
|
|
assign bus_buffer_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[el2_lsu_bus_intf.scala 201:51]
|
|
assign bus_buffer_io_lsu_axi_bid = io_lsu_axi_bid; // @[el2_lsu_bus_intf.scala 202:51]
|
|
assign bus_buffer_io_lsu_axi_arready = io_lsu_axi_arready; // @[el2_lsu_bus_intf.scala 203:51]
|
|
assign bus_buffer_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[el2_lsu_bus_intf.scala 204:51]
|
|
assign bus_buffer_io_lsu_axi_rid = io_lsu_axi_rid; // @[el2_lsu_bus_intf.scala 205:51]
|
|
assign bus_buffer_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[el2_lsu_bus_intf.scala 206:51]
|
|
assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_lsu_bus_intf.scala 208:51]
|
|
assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 271:51]
|
|
assign bus_buffer_io_lsu_axi_awready = io_lsu_axi_awready; // @[el2_lsu_bus_intf.scala 198:51]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
ldst_dual_r = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
ldst_byteen_r = _RAND_1[3:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
lsu_bus_clk_en_q = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
ldst_dual_m = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
is_sideeffects_r = _RAND_4[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
ldst_dual_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ldst_byteen_r = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_bus_clk_en_q = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ldst_dual_m = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
is_sideeffects_r = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ldst_dual_r <= 1'h0;
|
|
end else begin
|
|
ldst_dual_r <= ldst_dual_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ldst_byteen_r <= 4'h0;
|
|
end else begin
|
|
ldst_byteen_r <= _T_6 | _T_5;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_bus_clk_en_q <= 1'h0;
|
|
end else begin
|
|
lsu_bus_clk_en_q <= io_lsu_bus_clk_en;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ldst_dual_m <= 1'h0;
|
|
end else begin
|
|
ldst_dual_m <= io_lsu_addr_d[2] != io_end_addr_d[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
is_sideeffects_r <= 1'h0;
|
|
end else begin
|
|
is_sideeffects_r <= io_is_sideeffects_m;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_lsu(
|
|
input clock,
|
|
input reset,
|
|
input io_clk_override,
|
|
input io_dec_tlu_flush_lower_r,
|
|
input io_dec_tlu_i0_kill_writeb_r,
|
|
input io_dec_tlu_force_halt,
|
|
input io_dec_tlu_external_ldfwd_disable,
|
|
input io_dec_tlu_wb_coalescing_disable,
|
|
input io_dec_tlu_sideeffect_posted_disable,
|
|
input io_dec_tlu_core_ecc_disable,
|
|
input [31:0] io_exu_lsu_rs1_d,
|
|
input [31:0] io_exu_lsu_rs2_d,
|
|
input [11:0] io_dec_lsu_offset_d,
|
|
input io_lsu_p_valid,
|
|
input io_lsu_p_bits_fast_int,
|
|
input io_lsu_p_bits_by,
|
|
input io_lsu_p_bits_half,
|
|
input io_lsu_p_bits_word,
|
|
input io_lsu_p_bits_load,
|
|
input io_lsu_p_bits_store,
|
|
input io_lsu_p_bits_unsign,
|
|
input io_lsu_p_bits_store_data_bypass_d,
|
|
input io_lsu_p_bits_load_ldst_bypass_d,
|
|
input io_trigger_pkt_any_0_select,
|
|
input io_trigger_pkt_any_0_match_pkt,
|
|
input io_trigger_pkt_any_0_store,
|
|
input io_trigger_pkt_any_0_load,
|
|
input [31:0] io_trigger_pkt_any_0_tdata2,
|
|
input io_trigger_pkt_any_1_select,
|
|
input io_trigger_pkt_any_1_match_pkt,
|
|
input io_trigger_pkt_any_1_store,
|
|
input io_trigger_pkt_any_1_load,
|
|
input [31:0] io_trigger_pkt_any_1_tdata2,
|
|
input io_trigger_pkt_any_2_select,
|
|
input io_trigger_pkt_any_2_match_pkt,
|
|
input io_trigger_pkt_any_2_store,
|
|
input io_trigger_pkt_any_2_load,
|
|
input [31:0] io_trigger_pkt_any_2_tdata2,
|
|
input io_trigger_pkt_any_3_select,
|
|
input io_trigger_pkt_any_3_match_pkt,
|
|
input io_trigger_pkt_any_3_store,
|
|
input io_trigger_pkt_any_3_load,
|
|
input [31:0] io_trigger_pkt_any_3_tdata2,
|
|
input io_dec_lsu_valid_raw_d,
|
|
input [31:0] io_dec_tlu_mrac_ff,
|
|
output [31:0] io_lsu_result_m,
|
|
output [31:0] io_lsu_result_corr_r,
|
|
output io_lsu_load_stall_any,
|
|
output io_lsu_store_stall_any,
|
|
output io_lsu_fastint_stall_any,
|
|
output io_lsu_idle_any,
|
|
output [30:0] io_lsu_fir_addr,
|
|
output [1:0] io_lsu_fir_error,
|
|
output io_lsu_single_ecc_error_incr,
|
|
output io_lsu_error_pkt_r_valid,
|
|
output io_lsu_error_pkt_r_bits_single_ecc_error,
|
|
output io_lsu_error_pkt_r_bits_inst_type,
|
|
output io_lsu_error_pkt_r_bits_exc_type,
|
|
output [3:0] io_lsu_error_pkt_r_bits_mscause,
|
|
output [31:0] io_lsu_error_pkt_r_bits_addr,
|
|
output io_lsu_imprecise_error_load_any,
|
|
output io_lsu_imprecise_error_store_any,
|
|
output [31:0] io_lsu_imprecise_error_addr_any,
|
|
output io_lsu_nonblock_load_valid_m,
|
|
output [1:0] io_lsu_nonblock_load_tag_m,
|
|
output io_lsu_nonblock_load_inv_r,
|
|
output [1:0] io_lsu_nonblock_load_inv_tag_r,
|
|
output io_lsu_nonblock_load_data_valid,
|
|
output io_lsu_nonblock_load_data_error,
|
|
output [1:0] io_lsu_nonblock_load_data_tag,
|
|
output [31:0] io_lsu_nonblock_load_data,
|
|
output io_lsu_pmu_load_external_m,
|
|
output io_lsu_pmu_store_external_m,
|
|
output io_lsu_pmu_bus_trxn,
|
|
output io_lsu_pmu_bus_misaligned,
|
|
output io_lsu_pmu_bus_error,
|
|
output io_lsu_pmu_bus_busy,
|
|
output [3:0] io_lsu_trigger_match_m,
|
|
output io_dccm_wren,
|
|
output io_dccm_rden,
|
|
output [15:0] io_dccm_wr_addr_lo,
|
|
output [15:0] io_dccm_wr_addr_hi,
|
|
output [15:0] io_dccm_rd_addr_lo,
|
|
output [15:0] io_dccm_rd_addr_hi,
|
|
output [38:0] io_dccm_wr_data_lo,
|
|
output [38:0] io_dccm_wr_data_hi,
|
|
input [38:0] io_dccm_rd_data_lo,
|
|
input [38:0] io_dccm_rd_data_hi,
|
|
output io_picm_wren,
|
|
output io_picm_rden,
|
|
output io_picm_mken,
|
|
output [31:0] io_picm_rdaddr,
|
|
output [31:0] io_picm_wraddr,
|
|
output [31:0] io_picm_wr_data,
|
|
input [31:0] io_picm_rd_data,
|
|
output io_lsu_axi_awvalid,
|
|
input io_lsu_axi_awready,
|
|
output [2:0] io_lsu_axi_awid,
|
|
output [31:0] io_lsu_axi_awaddr,
|
|
output [3:0] io_lsu_axi_awregion,
|
|
output [2:0] io_lsu_axi_awsize,
|
|
output [3:0] io_lsu_axi_awcache,
|
|
output io_lsu_axi_wvalid,
|
|
input io_lsu_axi_wready,
|
|
output [63:0] io_lsu_axi_wdata,
|
|
output [7:0] io_lsu_axi_wstrb,
|
|
input io_lsu_axi_bvalid,
|
|
input [1:0] io_lsu_axi_bresp,
|
|
input [2:0] io_lsu_axi_bid,
|
|
output io_lsu_axi_arvalid,
|
|
input io_lsu_axi_arready,
|
|
output [2:0] io_lsu_axi_arid,
|
|
output [31:0] io_lsu_axi_araddr,
|
|
output [3:0] io_lsu_axi_arregion,
|
|
output [2:0] io_lsu_axi_arsize,
|
|
output [3:0] io_lsu_axi_arcache,
|
|
input io_lsu_axi_rvalid,
|
|
input [63:0] io_lsu_axi_rdata,
|
|
input [2:0] io_lsu_axi_rid,
|
|
input io_lsu_bus_clk_en,
|
|
input io_dma_dccm_req,
|
|
input io_dma_mem_write,
|
|
output io_dccm_dma_rvalid,
|
|
output io_dccm_dma_ecc_error,
|
|
input [2:0] io_dma_mem_tag,
|
|
input [31:0] io_dma_mem_addr,
|
|
input [2:0] io_dma_mem_sz,
|
|
input [63:0] io_dma_mem_wdata,
|
|
output [2:0] io_dccm_dma_rtag,
|
|
output [63:0] io_dccm_dma_rdata,
|
|
output io_dccm_ready,
|
|
input io_scan_mode,
|
|
input io_free_clk
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire lsu_lsc_ctl_reset; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_c1_m_clk; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_c1_r_clk; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_c2_m_clk; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_c2_r_clk; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_store_c1_m_clk; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_corr_r; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_single_ecc_error_r; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_m; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_flush_m_up; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_flush_r; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_exu_lsu_rs1_d; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_exu_lsu_rs2_d; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_valid; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_fast_int; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_by; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_half; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_word; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_load; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_store; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_unsign; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 154:30]
|
|
wire [11:0] lsu_lsc_ctl_io_dec_lsu_offset_d; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_picm_mask_data_m; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_bus_read_data_m; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_result_m; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_result_corr_r; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_addr_d; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_addr_m; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_addr_r; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_end_addr_d; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_end_addr_m; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_end_addr_r; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_store_data_m; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_dec_tlu_mrac_ff; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_exc_m; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_is_sideeffects_m; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_commit_r; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[el2_lsu.scala 154:30]
|
|
wire [3:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[el2_lsu.scala 154:30]
|
|
wire [30:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[el2_lsu.scala 154:30]
|
|
wire [1:0] lsu_lsc_ctl_io_lsu_fir_error; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_addr_in_pic_r; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_addr_external_m; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_dma_dccm_req; // @[el2_lsu.scala 154:30]
|
|
wire [31:0] lsu_lsc_ctl_io_dma_mem_addr; // @[el2_lsu.scala 154:30]
|
|
wire [2:0] lsu_lsc_ctl_io_dma_mem_sz; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_dma_mem_write; // @[el2_lsu.scala 154:30]
|
|
wire [63:0] lsu_lsc_ctl_io_dma_mem_wdata; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_by; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_half; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_dword; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[el2_lsu.scala 154:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[el2_lsu.scala 154:30]
|
|
wire dccm_ctl_clock; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_reset; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_c2_m_clk; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_c2_r_clk; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_free_c2_clk; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_store_c1_r_clk; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_d_bits_word; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_d_bits_dword; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_d_bits_load; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_d_bits_store; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_d_bits_dma; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_m_bits_by; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_m_bits_half; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_m_bits_word; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_m_bits_load; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_m_bits_dma; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_r_bits_by; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_r_bits_half; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_r_bits_word; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_r_bits_load; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_r_bits_store; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_pkt_r_bits_dma; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_addr_in_pic_r; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_raw_fwd_lo_r; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_raw_fwd_hi_r; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_commit_r; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_lsu_addr_d; // @[el2_lsu.scala 157:30]
|
|
wire [15:0] dccm_ctl_io_lsu_addr_m; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_lsu_addr_r; // @[el2_lsu.scala 157:30]
|
|
wire [15:0] dccm_ctl_io_end_addr_d; // @[el2_lsu.scala 157:30]
|
|
wire [15:0] dccm_ctl_io_end_addr_m; // @[el2_lsu.scala 157:30]
|
|
wire [15:0] dccm_ctl_io_end_addr_r; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_stbuf_reqvld_any; // @[el2_lsu.scala 157:30]
|
|
wire [15:0] dccm_ctl_io_stbuf_addr_any; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_stbuf_data_any; // @[el2_lsu.scala 157:30]
|
|
wire [6:0] dccm_ctl_io_stbuf_ecc_any; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_stbuf_fwddata_hi_m; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_stbuf_fwddata_lo_m; // @[el2_lsu.scala 157:30]
|
|
wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_lo_m; // @[el2_lsu.scala 157:30]
|
|
wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_hi_m; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_lsu_ld_data_corr_r; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_single_ecc_error_hi_r; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_single_ecc_error_lo_r; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_sec_data_hi_r_ff; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_sec_data_lo_r_ff; // @[el2_lsu.scala 157:30]
|
|
wire [6:0] dccm_ctl_io_sec_data_ecc_hi_r_ff; // @[el2_lsu.scala 157:30]
|
|
wire [6:0] dccm_ctl_io_sec_data_ecc_lo_r_ff; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_dccm_rdata_hi_m; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_dccm_rdata_lo_m; // @[el2_lsu.scala 157:30]
|
|
wire [6:0] dccm_ctl_io_dccm_data_ecc_hi_m; // @[el2_lsu.scala 157:30]
|
|
wire [6:0] dccm_ctl_io_dccm_data_ecc_lo_m; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_lsu_ld_data_m; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_sec_data_hi_m; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_sec_data_lo_m; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_store_data_m; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_dma_dccm_wen; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_dma_pic_wen; // @[el2_lsu.scala 157:30]
|
|
wire [2:0] dccm_ctl_io_dma_mem_tag_m; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_dma_mem_addr; // @[el2_lsu.scala 157:30]
|
|
wire [63:0] dccm_ctl_io_dma_mem_wdata; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_dma_dccm_wdata_lo; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_dma_dccm_wdata_hi; // @[el2_lsu.scala 157:30]
|
|
wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_hi; // @[el2_lsu.scala 157:30]
|
|
wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_lo; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_store_data_hi_r; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_store_data_lo_r; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_store_datafn_hi_r; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_store_datafn_lo_r; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_store_data_r; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_ld_single_ecc_error_r; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_picm_mask_data_m; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_stbuf_commit_any; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_lsu_dccm_rden_m; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_dccm_dma_rvalid; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_dccm_dma_ecc_error; // @[el2_lsu.scala 157:30]
|
|
wire [2:0] dccm_ctl_io_dccm_dma_rtag; // @[el2_lsu.scala 157:30]
|
|
wire [63:0] dccm_ctl_io_dccm_dma_rdata; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_dccm_wren; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_dccm_rden; // @[el2_lsu.scala 157:30]
|
|
wire [15:0] dccm_ctl_io_dccm_wr_addr_lo; // @[el2_lsu.scala 157:30]
|
|
wire [38:0] dccm_ctl_io_dccm_wr_data_lo; // @[el2_lsu.scala 157:30]
|
|
wire [15:0] dccm_ctl_io_dccm_rd_addr_lo; // @[el2_lsu.scala 157:30]
|
|
wire [38:0] dccm_ctl_io_dccm_rd_data_lo; // @[el2_lsu.scala 157:30]
|
|
wire [15:0] dccm_ctl_io_dccm_wr_addr_hi; // @[el2_lsu.scala 157:30]
|
|
wire [38:0] dccm_ctl_io_dccm_wr_data_hi; // @[el2_lsu.scala 157:30]
|
|
wire [15:0] dccm_ctl_io_dccm_rd_addr_hi; // @[el2_lsu.scala 157:30]
|
|
wire [38:0] dccm_ctl_io_dccm_rd_data_hi; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_picm_wren; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_picm_rden; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_picm_mken; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_picm_rdaddr; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_picm_wraddr; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_picm_wr_data; // @[el2_lsu.scala 157:30]
|
|
wire [31:0] dccm_ctl_io_picm_rd_data; // @[el2_lsu.scala 157:30]
|
|
wire dccm_ctl_io_scan_mode; // @[el2_lsu.scala 157:30]
|
|
wire stbuf_clock; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_reset; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_c1_m_clk; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_c1_r_clk; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_stbuf_c1_clk; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_free_c2_clk; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_pkt_m_valid; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_pkt_m_bits_dma; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_pkt_r_valid; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_by; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_half; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_word; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_dword; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_store; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_dma; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_store_stbuf_reqvld_r; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_commit_r; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 158:30]
|
|
wire [31:0] stbuf_io_store_data_hi_r; // @[el2_lsu.scala 158:30]
|
|
wire [31:0] stbuf_io_store_data_lo_r; // @[el2_lsu.scala 158:30]
|
|
wire [31:0] stbuf_io_store_datafn_hi_r; // @[el2_lsu.scala 158:30]
|
|
wire [31:0] stbuf_io_store_datafn_lo_r; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_stbuf_commit_any; // @[el2_lsu.scala 158:30]
|
|
wire [15:0] stbuf_io_lsu_addr_d; // @[el2_lsu.scala 158:30]
|
|
wire [31:0] stbuf_io_lsu_addr_m; // @[el2_lsu.scala 158:30]
|
|
wire [31:0] stbuf_io_lsu_addr_r; // @[el2_lsu.scala 158:30]
|
|
wire [15:0] stbuf_io_end_addr_d; // @[el2_lsu.scala 158:30]
|
|
wire [31:0] stbuf_io_end_addr_m; // @[el2_lsu.scala 158:30]
|
|
wire [31:0] stbuf_io_end_addr_r; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_addr_in_dccm_m; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_addr_in_dccm_r; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_scan_mode; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_stbuf_reqvld_any; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_stbuf_reqvld_flushed_any; // @[el2_lsu.scala 158:30]
|
|
wire [15:0] stbuf_io_stbuf_addr_any; // @[el2_lsu.scala 158:30]
|
|
wire [31:0] stbuf_io_stbuf_data_any; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_stbuf_full_any; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_lsu_stbuf_empty_any; // @[el2_lsu.scala 158:30]
|
|
wire stbuf_io_ldst_stbuf_reqvld_r; // @[el2_lsu.scala 158:30]
|
|
wire [31:0] stbuf_io_stbuf_fwddata_hi_m; // @[el2_lsu.scala 158:30]
|
|
wire [31:0] stbuf_io_stbuf_fwddata_lo_m; // @[el2_lsu.scala 158:30]
|
|
wire [3:0] stbuf_io_stbuf_fwdbyteen_hi_m; // @[el2_lsu.scala 158:30]
|
|
wire [3:0] stbuf_io_stbuf_fwdbyteen_lo_m; // @[el2_lsu.scala 158:30]
|
|
wire ecc_clock; // @[el2_lsu.scala 159:30]
|
|
wire ecc_reset; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_lsu_c2_r_clk; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_lsu_pkt_m_valid; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_lsu_pkt_m_bits_load; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_lsu_pkt_m_bits_dma; // @[el2_lsu.scala 159:30]
|
|
wire [31:0] ecc_io_stbuf_data_any; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_dec_tlu_core_ecc_disable; // @[el2_lsu.scala 159:30]
|
|
wire [15:0] ecc_io_lsu_addr_m; // @[el2_lsu.scala 159:30]
|
|
wire [15:0] ecc_io_end_addr_m; // @[el2_lsu.scala 159:30]
|
|
wire [31:0] ecc_io_dccm_rdata_hi_m; // @[el2_lsu.scala 159:30]
|
|
wire [31:0] ecc_io_dccm_rdata_lo_m; // @[el2_lsu.scala 159:30]
|
|
wire [6:0] ecc_io_dccm_data_ecc_hi_m; // @[el2_lsu.scala 159:30]
|
|
wire [6:0] ecc_io_dccm_data_ecc_lo_m; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_ld_single_ecc_error_r; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_lsu_dccm_rden_m; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_addr_in_dccm_m; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_dma_dccm_wen; // @[el2_lsu.scala 159:30]
|
|
wire [31:0] ecc_io_dma_dccm_wdata_lo; // @[el2_lsu.scala 159:30]
|
|
wire [31:0] ecc_io_dma_dccm_wdata_hi; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_scan_mode; // @[el2_lsu.scala 159:30]
|
|
wire [31:0] ecc_io_sec_data_hi_r; // @[el2_lsu.scala 159:30]
|
|
wire [31:0] ecc_io_sec_data_lo_r; // @[el2_lsu.scala 159:30]
|
|
wire [31:0] ecc_io_sec_data_hi_m; // @[el2_lsu.scala 159:30]
|
|
wire [31:0] ecc_io_sec_data_lo_m; // @[el2_lsu.scala 159:30]
|
|
wire [31:0] ecc_io_sec_data_hi_r_ff; // @[el2_lsu.scala 159:30]
|
|
wire [31:0] ecc_io_sec_data_lo_r_ff; // @[el2_lsu.scala 159:30]
|
|
wire [6:0] ecc_io_dma_dccm_wdata_ecc_hi; // @[el2_lsu.scala 159:30]
|
|
wire [6:0] ecc_io_dma_dccm_wdata_ecc_lo; // @[el2_lsu.scala 159:30]
|
|
wire [6:0] ecc_io_stbuf_ecc_any; // @[el2_lsu.scala 159:30]
|
|
wire [6:0] ecc_io_sec_data_ecc_hi_r_ff; // @[el2_lsu.scala 159:30]
|
|
wire [6:0] ecc_io_sec_data_ecc_lo_r_ff; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_single_ecc_error_hi_r; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_single_ecc_error_lo_r; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_lsu_single_ecc_error_r; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 159:30]
|
|
wire ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 159:30]
|
|
wire trigger_io_trigger_pkt_any_0_select; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_0_match_pkt; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_0_store; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_0_load; // @[el2_lsu.scala 160:30]
|
|
wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_1_select; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_1_match_pkt; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_1_store; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_1_load; // @[el2_lsu.scala 160:30]
|
|
wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_2_select; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_2_match_pkt; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_2_store; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_2_load; // @[el2_lsu.scala 160:30]
|
|
wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_3_select; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_3_match_pkt; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_3_store; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_trigger_pkt_any_3_load; // @[el2_lsu.scala 160:30]
|
|
wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_lsu_pkt_m_valid; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_lsu_pkt_m_bits_half; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_lsu_pkt_m_bits_word; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_lsu_pkt_m_bits_load; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 160:30]
|
|
wire trigger_io_lsu_pkt_m_bits_dma; // @[el2_lsu.scala 160:30]
|
|
wire [31:0] trigger_io_lsu_addr_m; // @[el2_lsu.scala 160:30]
|
|
wire [31:0] trigger_io_store_data_m; // @[el2_lsu.scala 160:30]
|
|
wire [3:0] trigger_io_lsu_trigger_match_m; // @[el2_lsu.scala 160:30]
|
|
wire clkdomain_clock; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_reset; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_free_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_clk_override; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_dma_dccm_req; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_ldst_stbuf_reqvld_r; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_stbuf_reqvld_any; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_stbuf_reqvld_flushed_any; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_busreq_r; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_bus_buffer_pend_any; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_bus_buffer_empty_any; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_stbuf_empty_any; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_bus_clk_en; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_p_valid; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_pkt_d_valid; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_pkt_d_bits_store; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_pkt_m_valid; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_pkt_r_valid; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_store_c1_m_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_stbuf_c1_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_bus_obuf_c1_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_bus_buf_c1_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_busm_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_lsu_free_c2_clk; // @[el2_lsu.scala 161:30]
|
|
wire clkdomain_io_scan_mode; // @[el2_lsu.scala 161:30]
|
|
wire bus_intf_clock; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_reset; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_scan_mode; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_dec_tlu_external_ldfwd_disable; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_dec_tlu_wb_coalescing_disable; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_c1_m_clk; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_c1_r_clk; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_c2_r_clk; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_bus_obuf_c1_clk; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_bus_buf_c1_clk; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_free_c2_clk; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_free_clk; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_busm_clk; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_busreq_m; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_m_valid; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_m_bits_by; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_m_bits_half; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_m_bits_word; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_m_bits_load; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_r_valid; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_by; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_half; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_word; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_load; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_store; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_unsign; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_lsu_addr_d; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_lsu_addr_m; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_lsu_addr_r; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_end_addr_d; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_end_addr_m; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_end_addr_r; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_store_data_r; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_dec_tlu_force_halt; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_commit_r; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_is_sideeffects_m; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_flush_m_up; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_flush_r; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_busreq_r; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_bus_buffer_pend_any; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_bus_buffer_full_any; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_bus_buffer_empty_any; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_bus_read_data_m; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_imprecise_error_load_any; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_imprecise_error_store_any; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_lsu_imprecise_error_addr_any; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_nonblock_load_valid_m; // @[el2_lsu.scala 162:30]
|
|
wire [1:0] bus_intf_io_lsu_nonblock_load_tag_m; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_nonblock_load_inv_r; // @[el2_lsu.scala 162:30]
|
|
wire [1:0] bus_intf_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_nonblock_load_data_valid; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_nonblock_load_data_error; // @[el2_lsu.scala 162:30]
|
|
wire [1:0] bus_intf_io_lsu_nonblock_load_data_tag; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_lsu_nonblock_load_data; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pmu_bus_trxn; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pmu_bus_misaligned; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pmu_bus_error; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_pmu_bus_busy; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_axi_awvalid; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_axi_awready; // @[el2_lsu.scala 162:30]
|
|
wire [2:0] bus_intf_io_lsu_axi_awid; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_lsu_axi_awaddr; // @[el2_lsu.scala 162:30]
|
|
wire [3:0] bus_intf_io_lsu_axi_awregion; // @[el2_lsu.scala 162:30]
|
|
wire [2:0] bus_intf_io_lsu_axi_awsize; // @[el2_lsu.scala 162:30]
|
|
wire [3:0] bus_intf_io_lsu_axi_awcache; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_axi_wvalid; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_axi_wready; // @[el2_lsu.scala 162:30]
|
|
wire [63:0] bus_intf_io_lsu_axi_wdata; // @[el2_lsu.scala 162:30]
|
|
wire [7:0] bus_intf_io_lsu_axi_wstrb; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_axi_bvalid; // @[el2_lsu.scala 162:30]
|
|
wire [1:0] bus_intf_io_lsu_axi_bresp; // @[el2_lsu.scala 162:30]
|
|
wire [2:0] bus_intf_io_lsu_axi_bid; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_axi_arvalid; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_axi_arready; // @[el2_lsu.scala 162:30]
|
|
wire [2:0] bus_intf_io_lsu_axi_arid; // @[el2_lsu.scala 162:30]
|
|
wire [31:0] bus_intf_io_lsu_axi_araddr; // @[el2_lsu.scala 162:30]
|
|
wire [3:0] bus_intf_io_lsu_axi_arregion; // @[el2_lsu.scala 162:30]
|
|
wire [2:0] bus_intf_io_lsu_axi_arsize; // @[el2_lsu.scala 162:30]
|
|
wire [3:0] bus_intf_io_lsu_axi_arcache; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_axi_rvalid; // @[el2_lsu.scala 162:30]
|
|
wire [2:0] bus_intf_io_lsu_axi_rid; // @[el2_lsu.scala 162:30]
|
|
wire [63:0] bus_intf_io_lsu_axi_rdata; // @[el2_lsu.scala 162:30]
|
|
wire bus_intf_io_lsu_bus_clk_en; // @[el2_lsu.scala 162:30]
|
|
wire _T = stbuf_io_lsu_stbuf_full_any | bus_intf_io_lsu_bus_buffer_full_any; // @[el2_lsu.scala 168:57]
|
|
wire _T_3 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[el2_lsu.scala 175:58]
|
|
wire _T_4 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_3; // @[el2_lsu.scala 175:56]
|
|
wire _T_5 = lsu_lsc_ctl_io_addr_in_dccm_m | lsu_lsc_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 175:126]
|
|
wire _T_6 = _T_4 & _T_5; // @[el2_lsu.scala 175:93]
|
|
wire ldst_nodma_mtor = _T_6 & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 175:158]
|
|
wire _T_7 = io_dec_lsu_valid_raw_d | ldst_nodma_mtor; // @[el2_lsu.scala 176:45]
|
|
wire _T_8 = _T_7 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 176:63]
|
|
wire _T_10 = io_dma_dccm_req & io_dma_mem_write; // @[el2_lsu.scala 177:38]
|
|
wire [5:0] _T_13 = {io_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] dma_dccm_wdata = io_dma_mem_wdata >> _T_13; // @[el2_lsu.scala 179:38]
|
|
wire _T_19 = ~lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[el2_lsu.scala 190:130]
|
|
wire _T_20 = lsu_lsc_ctl_io_lsu_pkt_r_valid & _T_19; // @[el2_lsu.scala 190:128]
|
|
wire _T_21 = _T_4 | _T_20; // @[el2_lsu.scala 190:94]
|
|
wire _T_22 = ~_T_21; // @[el2_lsu.scala 190:22]
|
|
wire _T_25 = lsu_lsc_ctl_io_lsu_pkt_r_valid & lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[el2_lsu.scala 192:61]
|
|
wire _T_26 = _T_25 & lsu_lsc_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 192:99]
|
|
wire _T_27 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_lsu.scala 192:133]
|
|
wire _T_28 = _T_26 & _T_27; // @[el2_lsu.scala 192:131]
|
|
wire _T_30 = lsu_lsc_ctl_io_lsu_pkt_m_bits_load | lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 194:90]
|
|
wire _T_34 = _T_30 & lsu_lsc_ctl_io_addr_external_m; // @[el2_lsu.scala 196:131]
|
|
wire _T_35 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_34; // @[el2_lsu.scala 196:53]
|
|
wire _T_36 = ~io_dec_tlu_flush_lower_r; // @[el2_lsu.scala 196:167]
|
|
wire _T_37 = _T_35 & _T_36; // @[el2_lsu.scala 196:165]
|
|
wire _T_38 = ~lsu_lsc_ctl_io_lsu_exc_m; // @[el2_lsu.scala 196:181]
|
|
wire _T_39 = _T_37 & _T_38; // @[el2_lsu.scala 196:179]
|
|
wire _T_40 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[el2_lsu.scala 196:209]
|
|
wire _T_48 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[el2_lsu.scala 199:65]
|
|
wire _T_50 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 200:65]
|
|
reg [2:0] dma_mem_tag_m; // @[el2_lsu.scala 492:67]
|
|
reg lsu_raw_fwd_hi_r; // @[el2_lsu.scala 493:67]
|
|
reg lsu_raw_fwd_lo_r; // @[el2_lsu.scala 494:67]
|
|
el2_lsu_lsc_ctl lsu_lsc_ctl ( // @[el2_lsu.scala 154:30]
|
|
.reset(lsu_lsc_ctl_reset),
|
|
.io_lsu_c1_m_clk(lsu_lsc_ctl_io_lsu_c1_m_clk),
|
|
.io_lsu_c1_r_clk(lsu_lsc_ctl_io_lsu_c1_r_clk),
|
|
.io_lsu_c2_m_clk(lsu_lsc_ctl_io_lsu_c2_m_clk),
|
|
.io_lsu_c2_r_clk(lsu_lsc_ctl_io_lsu_c2_r_clk),
|
|
.io_lsu_store_c1_m_clk(lsu_lsc_ctl_io_lsu_store_c1_m_clk),
|
|
.io_lsu_ld_data_corr_r(lsu_lsc_ctl_io_lsu_ld_data_corr_r),
|
|
.io_lsu_single_ecc_error_r(lsu_lsc_ctl_io_lsu_single_ecc_error_r),
|
|
.io_lsu_double_ecc_error_r(lsu_lsc_ctl_io_lsu_double_ecc_error_r),
|
|
.io_lsu_ld_data_m(lsu_lsc_ctl_io_lsu_ld_data_m),
|
|
.io_lsu_single_ecc_error_m(lsu_lsc_ctl_io_lsu_single_ecc_error_m),
|
|
.io_lsu_double_ecc_error_m(lsu_lsc_ctl_io_lsu_double_ecc_error_m),
|
|
.io_flush_m_up(lsu_lsc_ctl_io_flush_m_up),
|
|
.io_flush_r(lsu_lsc_ctl_io_flush_r),
|
|
.io_exu_lsu_rs1_d(lsu_lsc_ctl_io_exu_lsu_rs1_d),
|
|
.io_exu_lsu_rs2_d(lsu_lsc_ctl_io_exu_lsu_rs2_d),
|
|
.io_lsu_p_valid(lsu_lsc_ctl_io_lsu_p_valid),
|
|
.io_lsu_p_bits_fast_int(lsu_lsc_ctl_io_lsu_p_bits_fast_int),
|
|
.io_lsu_p_bits_by(lsu_lsc_ctl_io_lsu_p_bits_by),
|
|
.io_lsu_p_bits_half(lsu_lsc_ctl_io_lsu_p_bits_half),
|
|
.io_lsu_p_bits_word(lsu_lsc_ctl_io_lsu_p_bits_word),
|
|
.io_lsu_p_bits_load(lsu_lsc_ctl_io_lsu_p_bits_load),
|
|
.io_lsu_p_bits_store(lsu_lsc_ctl_io_lsu_p_bits_store),
|
|
.io_lsu_p_bits_unsign(lsu_lsc_ctl_io_lsu_p_bits_unsign),
|
|
.io_lsu_p_bits_store_data_bypass_d(lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d),
|
|
.io_lsu_p_bits_load_ldst_bypass_d(lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d),
|
|
.io_dec_lsu_valid_raw_d(lsu_lsc_ctl_io_dec_lsu_valid_raw_d),
|
|
.io_dec_lsu_offset_d(lsu_lsc_ctl_io_dec_lsu_offset_d),
|
|
.io_picm_mask_data_m(lsu_lsc_ctl_io_picm_mask_data_m),
|
|
.io_bus_read_data_m(lsu_lsc_ctl_io_bus_read_data_m),
|
|
.io_lsu_result_m(lsu_lsc_ctl_io_lsu_result_m),
|
|
.io_lsu_result_corr_r(lsu_lsc_ctl_io_lsu_result_corr_r),
|
|
.io_lsu_addr_d(lsu_lsc_ctl_io_lsu_addr_d),
|
|
.io_lsu_addr_m(lsu_lsc_ctl_io_lsu_addr_m),
|
|
.io_lsu_addr_r(lsu_lsc_ctl_io_lsu_addr_r),
|
|
.io_end_addr_d(lsu_lsc_ctl_io_end_addr_d),
|
|
.io_end_addr_m(lsu_lsc_ctl_io_end_addr_m),
|
|
.io_end_addr_r(lsu_lsc_ctl_io_end_addr_r),
|
|
.io_store_data_m(lsu_lsc_ctl_io_store_data_m),
|
|
.io_dec_tlu_mrac_ff(lsu_lsc_ctl_io_dec_tlu_mrac_ff),
|
|
.io_lsu_exc_m(lsu_lsc_ctl_io_lsu_exc_m),
|
|
.io_is_sideeffects_m(lsu_lsc_ctl_io_is_sideeffects_m),
|
|
.io_lsu_commit_r(lsu_lsc_ctl_io_lsu_commit_r),
|
|
.io_lsu_single_ecc_error_incr(lsu_lsc_ctl_io_lsu_single_ecc_error_incr),
|
|
.io_lsu_error_pkt_r_valid(lsu_lsc_ctl_io_lsu_error_pkt_r_valid),
|
|
.io_lsu_error_pkt_r_bits_single_ecc_error(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error),
|
|
.io_lsu_error_pkt_r_bits_inst_type(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type),
|
|
.io_lsu_error_pkt_r_bits_exc_type(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type),
|
|
.io_lsu_error_pkt_r_bits_mscause(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause),
|
|
.io_lsu_error_pkt_r_bits_addr(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr),
|
|
.io_lsu_fir_addr(lsu_lsc_ctl_io_lsu_fir_addr),
|
|
.io_lsu_fir_error(lsu_lsc_ctl_io_lsu_fir_error),
|
|
.io_addr_in_dccm_d(lsu_lsc_ctl_io_addr_in_dccm_d),
|
|
.io_addr_in_dccm_m(lsu_lsc_ctl_io_addr_in_dccm_m),
|
|
.io_addr_in_dccm_r(lsu_lsc_ctl_io_addr_in_dccm_r),
|
|
.io_addr_in_pic_d(lsu_lsc_ctl_io_addr_in_pic_d),
|
|
.io_addr_in_pic_m(lsu_lsc_ctl_io_addr_in_pic_m),
|
|
.io_addr_in_pic_r(lsu_lsc_ctl_io_addr_in_pic_r),
|
|
.io_addr_external_m(lsu_lsc_ctl_io_addr_external_m),
|
|
.io_dma_dccm_req(lsu_lsc_ctl_io_dma_dccm_req),
|
|
.io_dma_mem_addr(lsu_lsc_ctl_io_dma_mem_addr),
|
|
.io_dma_mem_sz(lsu_lsc_ctl_io_dma_mem_sz),
|
|
.io_dma_mem_write(lsu_lsc_ctl_io_dma_mem_write),
|
|
.io_dma_mem_wdata(lsu_lsc_ctl_io_dma_mem_wdata),
|
|
.io_lsu_pkt_d_valid(lsu_lsc_ctl_io_lsu_pkt_d_valid),
|
|
.io_lsu_pkt_d_bits_fast_int(lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int),
|
|
.io_lsu_pkt_d_bits_by(lsu_lsc_ctl_io_lsu_pkt_d_bits_by),
|
|
.io_lsu_pkt_d_bits_half(lsu_lsc_ctl_io_lsu_pkt_d_bits_half),
|
|
.io_lsu_pkt_d_bits_word(lsu_lsc_ctl_io_lsu_pkt_d_bits_word),
|
|
.io_lsu_pkt_d_bits_dword(lsu_lsc_ctl_io_lsu_pkt_d_bits_dword),
|
|
.io_lsu_pkt_d_bits_load(lsu_lsc_ctl_io_lsu_pkt_d_bits_load),
|
|
.io_lsu_pkt_d_bits_store(lsu_lsc_ctl_io_lsu_pkt_d_bits_store),
|
|
.io_lsu_pkt_d_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign),
|
|
.io_lsu_pkt_d_bits_dma(lsu_lsc_ctl_io_lsu_pkt_d_bits_dma),
|
|
.io_lsu_pkt_d_bits_store_data_bypass_d(lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d),
|
|
.io_lsu_pkt_d_bits_load_ldst_bypass_d(lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d),
|
|
.io_lsu_pkt_d_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m),
|
|
.io_lsu_pkt_m_valid(lsu_lsc_ctl_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_fast_int(lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int),
|
|
.io_lsu_pkt_m_bits_by(lsu_lsc_ctl_io_lsu_pkt_m_bits_by),
|
|
.io_lsu_pkt_m_bits_half(lsu_lsc_ctl_io_lsu_pkt_m_bits_half),
|
|
.io_lsu_pkt_m_bits_word(lsu_lsc_ctl_io_lsu_pkt_m_bits_word),
|
|
.io_lsu_pkt_m_bits_dword(lsu_lsc_ctl_io_lsu_pkt_m_bits_dword),
|
|
.io_lsu_pkt_m_bits_load(lsu_lsc_ctl_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_m_bits_store(lsu_lsc_ctl_io_lsu_pkt_m_bits_store),
|
|
.io_lsu_pkt_m_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign),
|
|
.io_lsu_pkt_m_bits_dma(lsu_lsc_ctl_io_lsu_pkt_m_bits_dma),
|
|
.io_lsu_pkt_m_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m),
|
|
.io_lsu_pkt_r_valid(lsu_lsc_ctl_io_lsu_pkt_r_valid),
|
|
.io_lsu_pkt_r_bits_by(lsu_lsc_ctl_io_lsu_pkt_r_bits_by),
|
|
.io_lsu_pkt_r_bits_half(lsu_lsc_ctl_io_lsu_pkt_r_bits_half),
|
|
.io_lsu_pkt_r_bits_word(lsu_lsc_ctl_io_lsu_pkt_r_bits_word),
|
|
.io_lsu_pkt_r_bits_dword(lsu_lsc_ctl_io_lsu_pkt_r_bits_dword),
|
|
.io_lsu_pkt_r_bits_load(lsu_lsc_ctl_io_lsu_pkt_r_bits_load),
|
|
.io_lsu_pkt_r_bits_store(lsu_lsc_ctl_io_lsu_pkt_r_bits_store),
|
|
.io_lsu_pkt_r_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign),
|
|
.io_lsu_pkt_r_bits_dma(lsu_lsc_ctl_io_lsu_pkt_r_bits_dma)
|
|
);
|
|
el2_lsu_dccm_ctl dccm_ctl ( // @[el2_lsu.scala 157:30]
|
|
.clock(dccm_ctl_clock),
|
|
.reset(dccm_ctl_reset),
|
|
.io_lsu_c2_m_clk(dccm_ctl_io_lsu_c2_m_clk),
|
|
.io_lsu_c2_r_clk(dccm_ctl_io_lsu_c2_r_clk),
|
|
.io_lsu_free_c2_clk(dccm_ctl_io_lsu_free_c2_clk),
|
|
.io_lsu_store_c1_r_clk(dccm_ctl_io_lsu_store_c1_r_clk),
|
|
.io_lsu_pkt_d_valid(dccm_ctl_io_lsu_pkt_d_valid),
|
|
.io_lsu_pkt_d_bits_word(dccm_ctl_io_lsu_pkt_d_bits_word),
|
|
.io_lsu_pkt_d_bits_dword(dccm_ctl_io_lsu_pkt_d_bits_dword),
|
|
.io_lsu_pkt_d_bits_load(dccm_ctl_io_lsu_pkt_d_bits_load),
|
|
.io_lsu_pkt_d_bits_store(dccm_ctl_io_lsu_pkt_d_bits_store),
|
|
.io_lsu_pkt_d_bits_dma(dccm_ctl_io_lsu_pkt_d_bits_dma),
|
|
.io_lsu_pkt_m_valid(dccm_ctl_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_by(dccm_ctl_io_lsu_pkt_m_bits_by),
|
|
.io_lsu_pkt_m_bits_half(dccm_ctl_io_lsu_pkt_m_bits_half),
|
|
.io_lsu_pkt_m_bits_word(dccm_ctl_io_lsu_pkt_m_bits_word),
|
|
.io_lsu_pkt_m_bits_load(dccm_ctl_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_m_bits_store(dccm_ctl_io_lsu_pkt_m_bits_store),
|
|
.io_lsu_pkt_m_bits_dma(dccm_ctl_io_lsu_pkt_m_bits_dma),
|
|
.io_lsu_pkt_r_valid(dccm_ctl_io_lsu_pkt_r_valid),
|
|
.io_lsu_pkt_r_bits_by(dccm_ctl_io_lsu_pkt_r_bits_by),
|
|
.io_lsu_pkt_r_bits_half(dccm_ctl_io_lsu_pkt_r_bits_half),
|
|
.io_lsu_pkt_r_bits_word(dccm_ctl_io_lsu_pkt_r_bits_word),
|
|
.io_lsu_pkt_r_bits_load(dccm_ctl_io_lsu_pkt_r_bits_load),
|
|
.io_lsu_pkt_r_bits_store(dccm_ctl_io_lsu_pkt_r_bits_store),
|
|
.io_lsu_pkt_r_bits_dma(dccm_ctl_io_lsu_pkt_r_bits_dma),
|
|
.io_addr_in_dccm_d(dccm_ctl_io_addr_in_dccm_d),
|
|
.io_addr_in_dccm_m(dccm_ctl_io_addr_in_dccm_m),
|
|
.io_addr_in_dccm_r(dccm_ctl_io_addr_in_dccm_r),
|
|
.io_addr_in_pic_d(dccm_ctl_io_addr_in_pic_d),
|
|
.io_addr_in_pic_m(dccm_ctl_io_addr_in_pic_m),
|
|
.io_addr_in_pic_r(dccm_ctl_io_addr_in_pic_r),
|
|
.io_lsu_raw_fwd_lo_r(dccm_ctl_io_lsu_raw_fwd_lo_r),
|
|
.io_lsu_raw_fwd_hi_r(dccm_ctl_io_lsu_raw_fwd_hi_r),
|
|
.io_lsu_commit_r(dccm_ctl_io_lsu_commit_r),
|
|
.io_lsu_addr_d(dccm_ctl_io_lsu_addr_d),
|
|
.io_lsu_addr_m(dccm_ctl_io_lsu_addr_m),
|
|
.io_lsu_addr_r(dccm_ctl_io_lsu_addr_r),
|
|
.io_end_addr_d(dccm_ctl_io_end_addr_d),
|
|
.io_end_addr_m(dccm_ctl_io_end_addr_m),
|
|
.io_end_addr_r(dccm_ctl_io_end_addr_r),
|
|
.io_stbuf_reqvld_any(dccm_ctl_io_stbuf_reqvld_any),
|
|
.io_stbuf_addr_any(dccm_ctl_io_stbuf_addr_any),
|
|
.io_stbuf_data_any(dccm_ctl_io_stbuf_data_any),
|
|
.io_stbuf_ecc_any(dccm_ctl_io_stbuf_ecc_any),
|
|
.io_stbuf_fwddata_hi_m(dccm_ctl_io_stbuf_fwddata_hi_m),
|
|
.io_stbuf_fwddata_lo_m(dccm_ctl_io_stbuf_fwddata_lo_m),
|
|
.io_stbuf_fwdbyteen_lo_m(dccm_ctl_io_stbuf_fwdbyteen_lo_m),
|
|
.io_stbuf_fwdbyteen_hi_m(dccm_ctl_io_stbuf_fwdbyteen_hi_m),
|
|
.io_lsu_ld_data_corr_r(dccm_ctl_io_lsu_ld_data_corr_r),
|
|
.io_lsu_double_ecc_error_r(dccm_ctl_io_lsu_double_ecc_error_r),
|
|
.io_single_ecc_error_hi_r(dccm_ctl_io_single_ecc_error_hi_r),
|
|
.io_single_ecc_error_lo_r(dccm_ctl_io_single_ecc_error_lo_r),
|
|
.io_sec_data_hi_r_ff(dccm_ctl_io_sec_data_hi_r_ff),
|
|
.io_sec_data_lo_r_ff(dccm_ctl_io_sec_data_lo_r_ff),
|
|
.io_sec_data_ecc_hi_r_ff(dccm_ctl_io_sec_data_ecc_hi_r_ff),
|
|
.io_sec_data_ecc_lo_r_ff(dccm_ctl_io_sec_data_ecc_lo_r_ff),
|
|
.io_dccm_rdata_hi_m(dccm_ctl_io_dccm_rdata_hi_m),
|
|
.io_dccm_rdata_lo_m(dccm_ctl_io_dccm_rdata_lo_m),
|
|
.io_dccm_data_ecc_hi_m(dccm_ctl_io_dccm_data_ecc_hi_m),
|
|
.io_dccm_data_ecc_lo_m(dccm_ctl_io_dccm_data_ecc_lo_m),
|
|
.io_lsu_ld_data_m(dccm_ctl_io_lsu_ld_data_m),
|
|
.io_lsu_double_ecc_error_m(dccm_ctl_io_lsu_double_ecc_error_m),
|
|
.io_sec_data_hi_m(dccm_ctl_io_sec_data_hi_m),
|
|
.io_sec_data_lo_m(dccm_ctl_io_sec_data_lo_m),
|
|
.io_store_data_m(dccm_ctl_io_store_data_m),
|
|
.io_dma_dccm_wen(dccm_ctl_io_dma_dccm_wen),
|
|
.io_dma_pic_wen(dccm_ctl_io_dma_pic_wen),
|
|
.io_dma_mem_tag_m(dccm_ctl_io_dma_mem_tag_m),
|
|
.io_dma_mem_addr(dccm_ctl_io_dma_mem_addr),
|
|
.io_dma_mem_wdata(dccm_ctl_io_dma_mem_wdata),
|
|
.io_dma_dccm_wdata_lo(dccm_ctl_io_dma_dccm_wdata_lo),
|
|
.io_dma_dccm_wdata_hi(dccm_ctl_io_dma_dccm_wdata_hi),
|
|
.io_dma_dccm_wdata_ecc_hi(dccm_ctl_io_dma_dccm_wdata_ecc_hi),
|
|
.io_dma_dccm_wdata_ecc_lo(dccm_ctl_io_dma_dccm_wdata_ecc_lo),
|
|
.io_store_data_hi_r(dccm_ctl_io_store_data_hi_r),
|
|
.io_store_data_lo_r(dccm_ctl_io_store_data_lo_r),
|
|
.io_store_datafn_hi_r(dccm_ctl_io_store_datafn_hi_r),
|
|
.io_store_datafn_lo_r(dccm_ctl_io_store_datafn_lo_r),
|
|
.io_store_data_r(dccm_ctl_io_store_data_r),
|
|
.io_ld_single_ecc_error_r(dccm_ctl_io_ld_single_ecc_error_r),
|
|
.io_ld_single_ecc_error_r_ff(dccm_ctl_io_ld_single_ecc_error_r_ff),
|
|
.io_picm_mask_data_m(dccm_ctl_io_picm_mask_data_m),
|
|
.io_lsu_stbuf_commit_any(dccm_ctl_io_lsu_stbuf_commit_any),
|
|
.io_lsu_dccm_rden_m(dccm_ctl_io_lsu_dccm_rden_m),
|
|
.io_dccm_dma_rvalid(dccm_ctl_io_dccm_dma_rvalid),
|
|
.io_dccm_dma_ecc_error(dccm_ctl_io_dccm_dma_ecc_error),
|
|
.io_dccm_dma_rtag(dccm_ctl_io_dccm_dma_rtag),
|
|
.io_dccm_dma_rdata(dccm_ctl_io_dccm_dma_rdata),
|
|
.io_dccm_wren(dccm_ctl_io_dccm_wren),
|
|
.io_dccm_rden(dccm_ctl_io_dccm_rden),
|
|
.io_dccm_wr_addr_lo(dccm_ctl_io_dccm_wr_addr_lo),
|
|
.io_dccm_wr_data_lo(dccm_ctl_io_dccm_wr_data_lo),
|
|
.io_dccm_rd_addr_lo(dccm_ctl_io_dccm_rd_addr_lo),
|
|
.io_dccm_rd_data_lo(dccm_ctl_io_dccm_rd_data_lo),
|
|
.io_dccm_wr_addr_hi(dccm_ctl_io_dccm_wr_addr_hi),
|
|
.io_dccm_wr_data_hi(dccm_ctl_io_dccm_wr_data_hi),
|
|
.io_dccm_rd_addr_hi(dccm_ctl_io_dccm_rd_addr_hi),
|
|
.io_dccm_rd_data_hi(dccm_ctl_io_dccm_rd_data_hi),
|
|
.io_picm_wren(dccm_ctl_io_picm_wren),
|
|
.io_picm_rden(dccm_ctl_io_picm_rden),
|
|
.io_picm_mken(dccm_ctl_io_picm_mken),
|
|
.io_picm_rdaddr(dccm_ctl_io_picm_rdaddr),
|
|
.io_picm_wraddr(dccm_ctl_io_picm_wraddr),
|
|
.io_picm_wr_data(dccm_ctl_io_picm_wr_data),
|
|
.io_picm_rd_data(dccm_ctl_io_picm_rd_data),
|
|
.io_scan_mode(dccm_ctl_io_scan_mode)
|
|
);
|
|
el2_lsu_stbuf stbuf ( // @[el2_lsu.scala 158:30]
|
|
.clock(stbuf_clock),
|
|
.reset(stbuf_reset),
|
|
.io_lsu_c1_m_clk(stbuf_io_lsu_c1_m_clk),
|
|
.io_lsu_c1_r_clk(stbuf_io_lsu_c1_r_clk),
|
|
.io_lsu_stbuf_c1_clk(stbuf_io_lsu_stbuf_c1_clk),
|
|
.io_lsu_free_c2_clk(stbuf_io_lsu_free_c2_clk),
|
|
.io_lsu_pkt_m_valid(stbuf_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_store(stbuf_io_lsu_pkt_m_bits_store),
|
|
.io_lsu_pkt_m_bits_dma(stbuf_io_lsu_pkt_m_bits_dma),
|
|
.io_lsu_pkt_r_valid(stbuf_io_lsu_pkt_r_valid),
|
|
.io_lsu_pkt_r_bits_by(stbuf_io_lsu_pkt_r_bits_by),
|
|
.io_lsu_pkt_r_bits_half(stbuf_io_lsu_pkt_r_bits_half),
|
|
.io_lsu_pkt_r_bits_word(stbuf_io_lsu_pkt_r_bits_word),
|
|
.io_lsu_pkt_r_bits_dword(stbuf_io_lsu_pkt_r_bits_dword),
|
|
.io_lsu_pkt_r_bits_store(stbuf_io_lsu_pkt_r_bits_store),
|
|
.io_lsu_pkt_r_bits_dma(stbuf_io_lsu_pkt_r_bits_dma),
|
|
.io_store_stbuf_reqvld_r(stbuf_io_store_stbuf_reqvld_r),
|
|
.io_lsu_commit_r(stbuf_io_lsu_commit_r),
|
|
.io_dec_lsu_valid_raw_d(stbuf_io_dec_lsu_valid_raw_d),
|
|
.io_store_data_hi_r(stbuf_io_store_data_hi_r),
|
|
.io_store_data_lo_r(stbuf_io_store_data_lo_r),
|
|
.io_store_datafn_hi_r(stbuf_io_store_datafn_hi_r),
|
|
.io_store_datafn_lo_r(stbuf_io_store_datafn_lo_r),
|
|
.io_lsu_stbuf_commit_any(stbuf_io_lsu_stbuf_commit_any),
|
|
.io_lsu_addr_d(stbuf_io_lsu_addr_d),
|
|
.io_lsu_addr_m(stbuf_io_lsu_addr_m),
|
|
.io_lsu_addr_r(stbuf_io_lsu_addr_r),
|
|
.io_end_addr_d(stbuf_io_end_addr_d),
|
|
.io_end_addr_m(stbuf_io_end_addr_m),
|
|
.io_end_addr_r(stbuf_io_end_addr_r),
|
|
.io_addr_in_dccm_m(stbuf_io_addr_in_dccm_m),
|
|
.io_addr_in_dccm_r(stbuf_io_addr_in_dccm_r),
|
|
.io_scan_mode(stbuf_io_scan_mode),
|
|
.io_stbuf_reqvld_any(stbuf_io_stbuf_reqvld_any),
|
|
.io_stbuf_reqvld_flushed_any(stbuf_io_stbuf_reqvld_flushed_any),
|
|
.io_stbuf_addr_any(stbuf_io_stbuf_addr_any),
|
|
.io_stbuf_data_any(stbuf_io_stbuf_data_any),
|
|
.io_lsu_stbuf_full_any(stbuf_io_lsu_stbuf_full_any),
|
|
.io_lsu_stbuf_empty_any(stbuf_io_lsu_stbuf_empty_any),
|
|
.io_ldst_stbuf_reqvld_r(stbuf_io_ldst_stbuf_reqvld_r),
|
|
.io_stbuf_fwddata_hi_m(stbuf_io_stbuf_fwddata_hi_m),
|
|
.io_stbuf_fwddata_lo_m(stbuf_io_stbuf_fwddata_lo_m),
|
|
.io_stbuf_fwdbyteen_hi_m(stbuf_io_stbuf_fwdbyteen_hi_m),
|
|
.io_stbuf_fwdbyteen_lo_m(stbuf_io_stbuf_fwdbyteen_lo_m)
|
|
);
|
|
el2_lsu_ecc ecc ( // @[el2_lsu.scala 159:30]
|
|
.clock(ecc_clock),
|
|
.reset(ecc_reset),
|
|
.io_lsu_c2_r_clk(ecc_io_lsu_c2_r_clk),
|
|
.io_lsu_pkt_m_valid(ecc_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_load(ecc_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_m_bits_store(ecc_io_lsu_pkt_m_bits_store),
|
|
.io_lsu_pkt_m_bits_dma(ecc_io_lsu_pkt_m_bits_dma),
|
|
.io_stbuf_data_any(ecc_io_stbuf_data_any),
|
|
.io_dec_tlu_core_ecc_disable(ecc_io_dec_tlu_core_ecc_disable),
|
|
.io_lsu_addr_m(ecc_io_lsu_addr_m),
|
|
.io_end_addr_m(ecc_io_end_addr_m),
|
|
.io_dccm_rdata_hi_m(ecc_io_dccm_rdata_hi_m),
|
|
.io_dccm_rdata_lo_m(ecc_io_dccm_rdata_lo_m),
|
|
.io_dccm_data_ecc_hi_m(ecc_io_dccm_data_ecc_hi_m),
|
|
.io_dccm_data_ecc_lo_m(ecc_io_dccm_data_ecc_lo_m),
|
|
.io_ld_single_ecc_error_r(ecc_io_ld_single_ecc_error_r),
|
|
.io_ld_single_ecc_error_r_ff(ecc_io_ld_single_ecc_error_r_ff),
|
|
.io_lsu_dccm_rden_m(ecc_io_lsu_dccm_rden_m),
|
|
.io_addr_in_dccm_m(ecc_io_addr_in_dccm_m),
|
|
.io_dma_dccm_wen(ecc_io_dma_dccm_wen),
|
|
.io_dma_dccm_wdata_lo(ecc_io_dma_dccm_wdata_lo),
|
|
.io_dma_dccm_wdata_hi(ecc_io_dma_dccm_wdata_hi),
|
|
.io_scan_mode(ecc_io_scan_mode),
|
|
.io_sec_data_hi_r(ecc_io_sec_data_hi_r),
|
|
.io_sec_data_lo_r(ecc_io_sec_data_lo_r),
|
|
.io_sec_data_hi_m(ecc_io_sec_data_hi_m),
|
|
.io_sec_data_lo_m(ecc_io_sec_data_lo_m),
|
|
.io_sec_data_hi_r_ff(ecc_io_sec_data_hi_r_ff),
|
|
.io_sec_data_lo_r_ff(ecc_io_sec_data_lo_r_ff),
|
|
.io_dma_dccm_wdata_ecc_hi(ecc_io_dma_dccm_wdata_ecc_hi),
|
|
.io_dma_dccm_wdata_ecc_lo(ecc_io_dma_dccm_wdata_ecc_lo),
|
|
.io_stbuf_ecc_any(ecc_io_stbuf_ecc_any),
|
|
.io_sec_data_ecc_hi_r_ff(ecc_io_sec_data_ecc_hi_r_ff),
|
|
.io_sec_data_ecc_lo_r_ff(ecc_io_sec_data_ecc_lo_r_ff),
|
|
.io_single_ecc_error_hi_r(ecc_io_single_ecc_error_hi_r),
|
|
.io_single_ecc_error_lo_r(ecc_io_single_ecc_error_lo_r),
|
|
.io_lsu_single_ecc_error_r(ecc_io_lsu_single_ecc_error_r),
|
|
.io_lsu_double_ecc_error_r(ecc_io_lsu_double_ecc_error_r),
|
|
.io_lsu_single_ecc_error_m(ecc_io_lsu_single_ecc_error_m),
|
|
.io_lsu_double_ecc_error_m(ecc_io_lsu_double_ecc_error_m)
|
|
);
|
|
el2_lsu_trigger trigger ( // @[el2_lsu.scala 160:30]
|
|
.io_trigger_pkt_any_0_select(trigger_io_trigger_pkt_any_0_select),
|
|
.io_trigger_pkt_any_0_match_pkt(trigger_io_trigger_pkt_any_0_match_pkt),
|
|
.io_trigger_pkt_any_0_store(trigger_io_trigger_pkt_any_0_store),
|
|
.io_trigger_pkt_any_0_load(trigger_io_trigger_pkt_any_0_load),
|
|
.io_trigger_pkt_any_0_tdata2(trigger_io_trigger_pkt_any_0_tdata2),
|
|
.io_trigger_pkt_any_1_select(trigger_io_trigger_pkt_any_1_select),
|
|
.io_trigger_pkt_any_1_match_pkt(trigger_io_trigger_pkt_any_1_match_pkt),
|
|
.io_trigger_pkt_any_1_store(trigger_io_trigger_pkt_any_1_store),
|
|
.io_trigger_pkt_any_1_load(trigger_io_trigger_pkt_any_1_load),
|
|
.io_trigger_pkt_any_1_tdata2(trigger_io_trigger_pkt_any_1_tdata2),
|
|
.io_trigger_pkt_any_2_select(trigger_io_trigger_pkt_any_2_select),
|
|
.io_trigger_pkt_any_2_match_pkt(trigger_io_trigger_pkt_any_2_match_pkt),
|
|
.io_trigger_pkt_any_2_store(trigger_io_trigger_pkt_any_2_store),
|
|
.io_trigger_pkt_any_2_load(trigger_io_trigger_pkt_any_2_load),
|
|
.io_trigger_pkt_any_2_tdata2(trigger_io_trigger_pkt_any_2_tdata2),
|
|
.io_trigger_pkt_any_3_select(trigger_io_trigger_pkt_any_3_select),
|
|
.io_trigger_pkt_any_3_match_pkt(trigger_io_trigger_pkt_any_3_match_pkt),
|
|
.io_trigger_pkt_any_3_store(trigger_io_trigger_pkt_any_3_store),
|
|
.io_trigger_pkt_any_3_load(trigger_io_trigger_pkt_any_3_load),
|
|
.io_trigger_pkt_any_3_tdata2(trigger_io_trigger_pkt_any_3_tdata2),
|
|
.io_lsu_pkt_m_valid(trigger_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_half(trigger_io_lsu_pkt_m_bits_half),
|
|
.io_lsu_pkt_m_bits_word(trigger_io_lsu_pkt_m_bits_word),
|
|
.io_lsu_pkt_m_bits_load(trigger_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_m_bits_store(trigger_io_lsu_pkt_m_bits_store),
|
|
.io_lsu_pkt_m_bits_dma(trigger_io_lsu_pkt_m_bits_dma),
|
|
.io_lsu_addr_m(trigger_io_lsu_addr_m),
|
|
.io_store_data_m(trigger_io_store_data_m),
|
|
.io_lsu_trigger_match_m(trigger_io_lsu_trigger_match_m)
|
|
);
|
|
el2_lsu_clkdomain clkdomain ( // @[el2_lsu.scala 161:30]
|
|
.clock(clkdomain_clock),
|
|
.reset(clkdomain_reset),
|
|
.io_free_clk(clkdomain_io_free_clk),
|
|
.io_clk_override(clkdomain_io_clk_override),
|
|
.io_dma_dccm_req(clkdomain_io_dma_dccm_req),
|
|
.io_ldst_stbuf_reqvld_r(clkdomain_io_ldst_stbuf_reqvld_r),
|
|
.io_stbuf_reqvld_any(clkdomain_io_stbuf_reqvld_any),
|
|
.io_stbuf_reqvld_flushed_any(clkdomain_io_stbuf_reqvld_flushed_any),
|
|
.io_lsu_busreq_r(clkdomain_io_lsu_busreq_r),
|
|
.io_lsu_bus_buffer_pend_any(clkdomain_io_lsu_bus_buffer_pend_any),
|
|
.io_lsu_bus_buffer_empty_any(clkdomain_io_lsu_bus_buffer_empty_any),
|
|
.io_lsu_stbuf_empty_any(clkdomain_io_lsu_stbuf_empty_any),
|
|
.io_lsu_bus_clk_en(clkdomain_io_lsu_bus_clk_en),
|
|
.io_lsu_p_valid(clkdomain_io_lsu_p_valid),
|
|
.io_lsu_pkt_d_valid(clkdomain_io_lsu_pkt_d_valid),
|
|
.io_lsu_pkt_d_bits_store(clkdomain_io_lsu_pkt_d_bits_store),
|
|
.io_lsu_pkt_m_valid(clkdomain_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_store(clkdomain_io_lsu_pkt_m_bits_store),
|
|
.io_lsu_pkt_r_valid(clkdomain_io_lsu_pkt_r_valid),
|
|
.io_lsu_c1_m_clk(clkdomain_io_lsu_c1_m_clk),
|
|
.io_lsu_c1_r_clk(clkdomain_io_lsu_c1_r_clk),
|
|
.io_lsu_c2_m_clk(clkdomain_io_lsu_c2_m_clk),
|
|
.io_lsu_c2_r_clk(clkdomain_io_lsu_c2_r_clk),
|
|
.io_lsu_store_c1_m_clk(clkdomain_io_lsu_store_c1_m_clk),
|
|
.io_lsu_stbuf_c1_clk(clkdomain_io_lsu_stbuf_c1_clk),
|
|
.io_lsu_bus_obuf_c1_clk(clkdomain_io_lsu_bus_obuf_c1_clk),
|
|
.io_lsu_bus_ibuf_c1_clk(clkdomain_io_lsu_bus_ibuf_c1_clk),
|
|
.io_lsu_bus_buf_c1_clk(clkdomain_io_lsu_bus_buf_c1_clk),
|
|
.io_lsu_busm_clk(clkdomain_io_lsu_busm_clk),
|
|
.io_lsu_free_c2_clk(clkdomain_io_lsu_free_c2_clk),
|
|
.io_scan_mode(clkdomain_io_scan_mode)
|
|
);
|
|
el2_lsu_bus_intf bus_intf ( // @[el2_lsu.scala 162:30]
|
|
.clock(bus_intf_clock),
|
|
.reset(bus_intf_reset),
|
|
.io_scan_mode(bus_intf_io_scan_mode),
|
|
.io_dec_tlu_external_ldfwd_disable(bus_intf_io_dec_tlu_external_ldfwd_disable),
|
|
.io_dec_tlu_wb_coalescing_disable(bus_intf_io_dec_tlu_wb_coalescing_disable),
|
|
.io_dec_tlu_sideeffect_posted_disable(bus_intf_io_dec_tlu_sideeffect_posted_disable),
|
|
.io_lsu_c1_m_clk(bus_intf_io_lsu_c1_m_clk),
|
|
.io_lsu_c1_r_clk(bus_intf_io_lsu_c1_r_clk),
|
|
.io_lsu_c2_r_clk(bus_intf_io_lsu_c2_r_clk),
|
|
.io_lsu_bus_ibuf_c1_clk(bus_intf_io_lsu_bus_ibuf_c1_clk),
|
|
.io_lsu_bus_obuf_c1_clk(bus_intf_io_lsu_bus_obuf_c1_clk),
|
|
.io_lsu_bus_buf_c1_clk(bus_intf_io_lsu_bus_buf_c1_clk),
|
|
.io_lsu_free_c2_clk(bus_intf_io_lsu_free_c2_clk),
|
|
.io_free_clk(bus_intf_io_free_clk),
|
|
.io_lsu_busm_clk(bus_intf_io_lsu_busm_clk),
|
|
.io_dec_lsu_valid_raw_d(bus_intf_io_dec_lsu_valid_raw_d),
|
|
.io_lsu_busreq_m(bus_intf_io_lsu_busreq_m),
|
|
.io_lsu_pkt_m_valid(bus_intf_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_by(bus_intf_io_lsu_pkt_m_bits_by),
|
|
.io_lsu_pkt_m_bits_half(bus_intf_io_lsu_pkt_m_bits_half),
|
|
.io_lsu_pkt_m_bits_word(bus_intf_io_lsu_pkt_m_bits_word),
|
|
.io_lsu_pkt_m_bits_load(bus_intf_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_r_valid(bus_intf_io_lsu_pkt_r_valid),
|
|
.io_lsu_pkt_r_bits_by(bus_intf_io_lsu_pkt_r_bits_by),
|
|
.io_lsu_pkt_r_bits_half(bus_intf_io_lsu_pkt_r_bits_half),
|
|
.io_lsu_pkt_r_bits_word(bus_intf_io_lsu_pkt_r_bits_word),
|
|
.io_lsu_pkt_r_bits_load(bus_intf_io_lsu_pkt_r_bits_load),
|
|
.io_lsu_pkt_r_bits_store(bus_intf_io_lsu_pkt_r_bits_store),
|
|
.io_lsu_pkt_r_bits_unsign(bus_intf_io_lsu_pkt_r_bits_unsign),
|
|
.io_lsu_addr_d(bus_intf_io_lsu_addr_d),
|
|
.io_lsu_addr_m(bus_intf_io_lsu_addr_m),
|
|
.io_lsu_addr_r(bus_intf_io_lsu_addr_r),
|
|
.io_end_addr_d(bus_intf_io_end_addr_d),
|
|
.io_end_addr_m(bus_intf_io_end_addr_m),
|
|
.io_end_addr_r(bus_intf_io_end_addr_r),
|
|
.io_store_data_r(bus_intf_io_store_data_r),
|
|
.io_dec_tlu_force_halt(bus_intf_io_dec_tlu_force_halt),
|
|
.io_lsu_commit_r(bus_intf_io_lsu_commit_r),
|
|
.io_is_sideeffects_m(bus_intf_io_is_sideeffects_m),
|
|
.io_flush_m_up(bus_intf_io_flush_m_up),
|
|
.io_flush_r(bus_intf_io_flush_r),
|
|
.io_lsu_busreq_r(bus_intf_io_lsu_busreq_r),
|
|
.io_lsu_bus_buffer_pend_any(bus_intf_io_lsu_bus_buffer_pend_any),
|
|
.io_lsu_bus_buffer_full_any(bus_intf_io_lsu_bus_buffer_full_any),
|
|
.io_lsu_bus_buffer_empty_any(bus_intf_io_lsu_bus_buffer_empty_any),
|
|
.io_bus_read_data_m(bus_intf_io_bus_read_data_m),
|
|
.io_lsu_imprecise_error_load_any(bus_intf_io_lsu_imprecise_error_load_any),
|
|
.io_lsu_imprecise_error_store_any(bus_intf_io_lsu_imprecise_error_store_any),
|
|
.io_lsu_imprecise_error_addr_any(bus_intf_io_lsu_imprecise_error_addr_any),
|
|
.io_lsu_nonblock_load_valid_m(bus_intf_io_lsu_nonblock_load_valid_m),
|
|
.io_lsu_nonblock_load_tag_m(bus_intf_io_lsu_nonblock_load_tag_m),
|
|
.io_lsu_nonblock_load_inv_r(bus_intf_io_lsu_nonblock_load_inv_r),
|
|
.io_lsu_nonblock_load_inv_tag_r(bus_intf_io_lsu_nonblock_load_inv_tag_r),
|
|
.io_lsu_nonblock_load_data_valid(bus_intf_io_lsu_nonblock_load_data_valid),
|
|
.io_lsu_nonblock_load_data_error(bus_intf_io_lsu_nonblock_load_data_error),
|
|
.io_lsu_nonblock_load_data_tag(bus_intf_io_lsu_nonblock_load_data_tag),
|
|
.io_lsu_nonblock_load_data(bus_intf_io_lsu_nonblock_load_data),
|
|
.io_lsu_pmu_bus_trxn(bus_intf_io_lsu_pmu_bus_trxn),
|
|
.io_lsu_pmu_bus_misaligned(bus_intf_io_lsu_pmu_bus_misaligned),
|
|
.io_lsu_pmu_bus_error(bus_intf_io_lsu_pmu_bus_error),
|
|
.io_lsu_pmu_bus_busy(bus_intf_io_lsu_pmu_bus_busy),
|
|
.io_lsu_axi_awvalid(bus_intf_io_lsu_axi_awvalid),
|
|
.io_lsu_axi_awready(bus_intf_io_lsu_axi_awready),
|
|
.io_lsu_axi_awid(bus_intf_io_lsu_axi_awid),
|
|
.io_lsu_axi_awaddr(bus_intf_io_lsu_axi_awaddr),
|
|
.io_lsu_axi_awregion(bus_intf_io_lsu_axi_awregion),
|
|
.io_lsu_axi_awsize(bus_intf_io_lsu_axi_awsize),
|
|
.io_lsu_axi_awcache(bus_intf_io_lsu_axi_awcache),
|
|
.io_lsu_axi_wvalid(bus_intf_io_lsu_axi_wvalid),
|
|
.io_lsu_axi_wready(bus_intf_io_lsu_axi_wready),
|
|
.io_lsu_axi_wdata(bus_intf_io_lsu_axi_wdata),
|
|
.io_lsu_axi_wstrb(bus_intf_io_lsu_axi_wstrb),
|
|
.io_lsu_axi_bvalid(bus_intf_io_lsu_axi_bvalid),
|
|
.io_lsu_axi_bresp(bus_intf_io_lsu_axi_bresp),
|
|
.io_lsu_axi_bid(bus_intf_io_lsu_axi_bid),
|
|
.io_lsu_axi_arvalid(bus_intf_io_lsu_axi_arvalid),
|
|
.io_lsu_axi_arready(bus_intf_io_lsu_axi_arready),
|
|
.io_lsu_axi_arid(bus_intf_io_lsu_axi_arid),
|
|
.io_lsu_axi_araddr(bus_intf_io_lsu_axi_araddr),
|
|
.io_lsu_axi_arregion(bus_intf_io_lsu_axi_arregion),
|
|
.io_lsu_axi_arsize(bus_intf_io_lsu_axi_arsize),
|
|
.io_lsu_axi_arcache(bus_intf_io_lsu_axi_arcache),
|
|
.io_lsu_axi_rvalid(bus_intf_io_lsu_axi_rvalid),
|
|
.io_lsu_axi_rid(bus_intf_io_lsu_axi_rid),
|
|
.io_lsu_axi_rdata(bus_intf_io_lsu_axi_rdata),
|
|
.io_lsu_bus_clk_en(bus_intf_io_lsu_bus_clk_en)
|
|
);
|
|
assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[el2_lsu.scala 155:19]
|
|
assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[el2_lsu.scala 156:24]
|
|
assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 169:25]
|
|
assign io_lsu_store_stall_any = _T | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 168:26]
|
|
assign io_lsu_fastint_stall_any = dccm_ctl_io_ld_single_ecc_error_r; // @[el2_lsu.scala 170:28]
|
|
assign io_lsu_idle_any = _T_22 & bus_intf_io_lsu_bus_buffer_empty_any; // @[el2_lsu.scala 190:19]
|
|
assign io_lsu_fir_addr = lsu_lsc_ctl_io_lsu_fir_addr; // @[el2_lsu.scala 236:49]
|
|
assign io_lsu_fir_error = lsu_lsc_ctl_io_lsu_fir_error; // @[el2_lsu.scala 237:49]
|
|
assign io_lsu_single_ecc_error_incr = lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[el2_lsu.scala 234:49]
|
|
assign io_lsu_error_pkt_r_valid = lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[el2_lsu.scala 235:49]
|
|
assign io_lsu_error_pkt_r_bits_single_ecc_error = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_lsu.scala 235:49]
|
|
assign io_lsu_error_pkt_r_bits_inst_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[el2_lsu.scala 235:49]
|
|
assign io_lsu_error_pkt_r_bits_exc_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[el2_lsu.scala 235:49]
|
|
assign io_lsu_error_pkt_r_bits_mscause = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[el2_lsu.scala 235:49]
|
|
assign io_lsu_error_pkt_r_bits_addr = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[el2_lsu.scala 235:49]
|
|
assign io_lsu_imprecise_error_load_any = bus_intf_io_lsu_imprecise_error_load_any; // @[el2_lsu.scala 436:49]
|
|
assign io_lsu_imprecise_error_store_any = bus_intf_io_lsu_imprecise_error_store_any; // @[el2_lsu.scala 437:49]
|
|
assign io_lsu_imprecise_error_addr_any = bus_intf_io_lsu_imprecise_error_addr_any; // @[el2_lsu.scala 438:49]
|
|
assign io_lsu_nonblock_load_valid_m = bus_intf_io_lsu_nonblock_load_valid_m; // @[el2_lsu.scala 439:49]
|
|
assign io_lsu_nonblock_load_tag_m = bus_intf_io_lsu_nonblock_load_tag_m; // @[el2_lsu.scala 440:49]
|
|
assign io_lsu_nonblock_load_inv_r = bus_intf_io_lsu_nonblock_load_inv_r; // @[el2_lsu.scala 441:49]
|
|
assign io_lsu_nonblock_load_inv_tag_r = bus_intf_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu.scala 442:49]
|
|
assign io_lsu_nonblock_load_data_valid = bus_intf_io_lsu_nonblock_load_data_valid; // @[el2_lsu.scala 443:49]
|
|
assign io_lsu_nonblock_load_data_error = bus_intf_io_lsu_nonblock_load_data_error; // @[el2_lsu.scala 444:49]
|
|
assign io_lsu_nonblock_load_data_tag = bus_intf_io_lsu_nonblock_load_data_tag; // @[el2_lsu.scala 445:49]
|
|
assign io_lsu_nonblock_load_data = bus_intf_io_lsu_nonblock_load_data; // @[el2_lsu.scala 446:49]
|
|
assign io_lsu_pmu_load_external_m = _T_48 & lsu_lsc_ctl_io_addr_external_m; // @[el2_lsu.scala 199:31]
|
|
assign io_lsu_pmu_store_external_m = _T_50 & lsu_lsc_ctl_io_addr_external_m; // @[el2_lsu.scala 200:31]
|
|
assign io_lsu_pmu_bus_trxn = bus_intf_io_lsu_pmu_bus_trxn; // @[el2_lsu.scala 447:49]
|
|
assign io_lsu_pmu_bus_misaligned = bus_intf_io_lsu_pmu_bus_misaligned; // @[el2_lsu.scala 448:49]
|
|
assign io_lsu_pmu_bus_error = bus_intf_io_lsu_pmu_bus_error; // @[el2_lsu.scala 449:49]
|
|
assign io_lsu_pmu_bus_busy = bus_intf_io_lsu_pmu_bus_busy; // @[el2_lsu.scala 450:49]
|
|
assign io_lsu_trigger_match_m = trigger_io_lsu_trigger_match_m; // @[el2_lsu.scala 381:50]
|
|
assign io_dccm_wren = dccm_ctl_io_dccm_wren; // @[el2_lsu.scala 303:49]
|
|
assign io_dccm_rden = dccm_ctl_io_dccm_rden; // @[el2_lsu.scala 304:49]
|
|
assign io_dccm_wr_addr_lo = dccm_ctl_io_dccm_wr_addr_lo; // @[el2_lsu.scala 305:49]
|
|
assign io_dccm_wr_addr_hi = dccm_ctl_io_dccm_wr_addr_hi; // @[el2_lsu.scala 308:49]
|
|
assign io_dccm_rd_addr_lo = dccm_ctl_io_dccm_rd_addr_lo; // @[el2_lsu.scala 307:49]
|
|
assign io_dccm_rd_addr_hi = dccm_ctl_io_dccm_rd_addr_hi; // @[el2_lsu.scala 310:49]
|
|
assign io_dccm_wr_data_lo = dccm_ctl_io_dccm_wr_data_lo; // @[el2_lsu.scala 306:49]
|
|
assign io_dccm_wr_data_hi = dccm_ctl_io_dccm_wr_data_hi; // @[el2_lsu.scala 309:49]
|
|
assign io_picm_wren = dccm_ctl_io_picm_wren; // @[el2_lsu.scala 311:49]
|
|
assign io_picm_rden = dccm_ctl_io_picm_rden; // @[el2_lsu.scala 312:49]
|
|
assign io_picm_mken = dccm_ctl_io_picm_mken; // @[el2_lsu.scala 313:49]
|
|
assign io_picm_rdaddr = dccm_ctl_io_picm_rdaddr; // @[el2_lsu.scala 314:49]
|
|
assign io_picm_wraddr = dccm_ctl_io_picm_wraddr; // @[el2_lsu.scala 315:49]
|
|
assign io_picm_wr_data = dccm_ctl_io_picm_wr_data; // @[el2_lsu.scala 316:49]
|
|
assign io_lsu_axi_awvalid = bus_intf_io_lsu_axi_awvalid; // @[el2_lsu.scala 451:49]
|
|
assign io_lsu_axi_awid = bus_intf_io_lsu_axi_awid; // @[el2_lsu.scala 453:49]
|
|
assign io_lsu_axi_awaddr = bus_intf_io_lsu_axi_awaddr; // @[el2_lsu.scala 454:49]
|
|
assign io_lsu_axi_awregion = bus_intf_io_lsu_axi_awregion; // @[el2_lsu.scala 455:49]
|
|
assign io_lsu_axi_awsize = bus_intf_io_lsu_axi_awsize; // @[el2_lsu.scala 457:49]
|
|
assign io_lsu_axi_awcache = bus_intf_io_lsu_axi_awcache; // @[el2_lsu.scala 460:49]
|
|
assign io_lsu_axi_wvalid = bus_intf_io_lsu_axi_wvalid; // @[el2_lsu.scala 463:49]
|
|
assign io_lsu_axi_wdata = bus_intf_io_lsu_axi_wdata; // @[el2_lsu.scala 465:49]
|
|
assign io_lsu_axi_wstrb = bus_intf_io_lsu_axi_wstrb; // @[el2_lsu.scala 466:49]
|
|
assign io_lsu_axi_arvalid = bus_intf_io_lsu_axi_arvalid; // @[el2_lsu.scala 472:49]
|
|
assign io_lsu_axi_arid = bus_intf_io_lsu_axi_arid; // @[el2_lsu.scala 474:49]
|
|
assign io_lsu_axi_araddr = bus_intf_io_lsu_axi_araddr; // @[el2_lsu.scala 475:49]
|
|
assign io_lsu_axi_arregion = bus_intf_io_lsu_axi_arregion; // @[el2_lsu.scala 476:49]
|
|
assign io_lsu_axi_arsize = bus_intf_io_lsu_axi_arsize; // @[el2_lsu.scala 478:49]
|
|
assign io_lsu_axi_arcache = bus_intf_io_lsu_axi_arcache; // @[el2_lsu.scala 481:49]
|
|
assign io_dccm_dma_rvalid = dccm_ctl_io_dccm_dma_rvalid; // @[el2_lsu.scala 299:49]
|
|
assign io_dccm_dma_ecc_error = dccm_ctl_io_dccm_dma_ecc_error; // @[el2_lsu.scala 300:49]
|
|
assign io_dccm_dma_rtag = dccm_ctl_io_dccm_dma_rtag; // @[el2_lsu.scala 301:49]
|
|
assign io_dccm_dma_rdata = dccm_ctl_io_dccm_dma_rdata; // @[el2_lsu.scala 302:49]
|
|
assign io_dccm_ready = ~_T_8; // @[el2_lsu.scala 176:17]
|
|
assign lsu_lsc_ctl_reset = reset;
|
|
assign lsu_lsc_ctl_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 204:46]
|
|
assign lsu_lsc_ctl_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 205:46]
|
|
assign lsu_lsc_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 206:46]
|
|
assign lsu_lsc_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 207:46]
|
|
assign lsu_lsc_ctl_io_lsu_store_c1_m_clk = clkdomain_io_lsu_store_c1_m_clk; // @[el2_lsu.scala 208:46]
|
|
assign lsu_lsc_ctl_io_lsu_ld_data_corr_r = dccm_ctl_io_lsu_ld_data_corr_r; // @[el2_lsu.scala 210:46]
|
|
assign lsu_lsc_ctl_io_lsu_single_ecc_error_r = ecc_io_lsu_single_ecc_error_r; // @[el2_lsu.scala 211:46]
|
|
assign lsu_lsc_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 212:46]
|
|
assign lsu_lsc_ctl_io_lsu_ld_data_m = dccm_ctl_io_lsu_ld_data_m; // @[el2_lsu.scala 213:46]
|
|
assign lsu_lsc_ctl_io_lsu_single_ecc_error_m = ecc_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 214:46]
|
|
assign lsu_lsc_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 215:46]
|
|
assign lsu_lsc_ctl_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[el2_lsu.scala 216:46]
|
|
assign lsu_lsc_ctl_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[el2_lsu.scala 217:46]
|
|
assign lsu_lsc_ctl_io_exu_lsu_rs1_d = io_exu_lsu_rs1_d; // @[el2_lsu.scala 218:46]
|
|
assign lsu_lsc_ctl_io_exu_lsu_rs2_d = io_exu_lsu_rs2_d; // @[el2_lsu.scala 219:46]
|
|
assign lsu_lsc_ctl_io_lsu_p_valid = io_lsu_p_valid; // @[el2_lsu.scala 220:46]
|
|
assign lsu_lsc_ctl_io_lsu_p_bits_fast_int = io_lsu_p_bits_fast_int; // @[el2_lsu.scala 220:46]
|
|
assign lsu_lsc_ctl_io_lsu_p_bits_by = io_lsu_p_bits_by; // @[el2_lsu.scala 220:46]
|
|
assign lsu_lsc_ctl_io_lsu_p_bits_half = io_lsu_p_bits_half; // @[el2_lsu.scala 220:46]
|
|
assign lsu_lsc_ctl_io_lsu_p_bits_word = io_lsu_p_bits_word; // @[el2_lsu.scala 220:46]
|
|
assign lsu_lsc_ctl_io_lsu_p_bits_load = io_lsu_p_bits_load; // @[el2_lsu.scala 220:46]
|
|
assign lsu_lsc_ctl_io_lsu_p_bits_store = io_lsu_p_bits_store; // @[el2_lsu.scala 220:46]
|
|
assign lsu_lsc_ctl_io_lsu_p_bits_unsign = io_lsu_p_bits_unsign; // @[el2_lsu.scala 220:46]
|
|
assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d = io_lsu_p_bits_store_data_bypass_d; // @[el2_lsu.scala 220:46]
|
|
assign lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d = io_lsu_p_bits_load_ldst_bypass_d; // @[el2_lsu.scala 220:46]
|
|
assign lsu_lsc_ctl_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 221:46]
|
|
assign lsu_lsc_ctl_io_dec_lsu_offset_d = io_dec_lsu_offset_d; // @[el2_lsu.scala 222:46]
|
|
assign lsu_lsc_ctl_io_picm_mask_data_m = dccm_ctl_io_picm_mask_data_m; // @[el2_lsu.scala 223:46]
|
|
assign lsu_lsc_ctl_io_bus_read_data_m = bus_intf_io_bus_read_data_m; // @[el2_lsu.scala 224:46]
|
|
assign lsu_lsc_ctl_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[el2_lsu.scala 230:46]
|
|
assign lsu_lsc_ctl_io_dma_dccm_req = io_dma_dccm_req; // @[el2_lsu.scala 225:46]
|
|
assign lsu_lsc_ctl_io_dma_mem_addr = io_dma_mem_addr; // @[el2_lsu.scala 226:46]
|
|
assign lsu_lsc_ctl_io_dma_mem_sz = io_dma_mem_sz; // @[el2_lsu.scala 227:46]
|
|
assign lsu_lsc_ctl_io_dma_mem_write = io_dma_mem_write; // @[el2_lsu.scala 228:46]
|
|
assign lsu_lsc_ctl_io_dma_mem_wdata = io_dma_mem_wdata; // @[el2_lsu.scala 229:46]
|
|
assign dccm_ctl_clock = clock;
|
|
assign dccm_ctl_reset = reset;
|
|
assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 240:46]
|
|
assign dccm_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 241:46]
|
|
assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 242:46]
|
|
assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 244:46]
|
|
assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 246:46]
|
|
assign dccm_ctl_io_lsu_pkt_d_bits_word = lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[el2_lsu.scala 246:46]
|
|
assign dccm_ctl_io_lsu_pkt_d_bits_dword = lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[el2_lsu.scala 246:46]
|
|
assign dccm_ctl_io_lsu_pkt_d_bits_load = lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[el2_lsu.scala 246:46]
|
|
assign dccm_ctl_io_lsu_pkt_d_bits_store = lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[el2_lsu.scala 246:46]
|
|
assign dccm_ctl_io_lsu_pkt_d_bits_dma = lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[el2_lsu.scala 246:46]
|
|
assign dccm_ctl_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 247:46]
|
|
assign dccm_ctl_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[el2_lsu.scala 247:46]
|
|
assign dccm_ctl_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[el2_lsu.scala 247:46]
|
|
assign dccm_ctl_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[el2_lsu.scala 247:46]
|
|
assign dccm_ctl_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[el2_lsu.scala 247:46]
|
|
assign dccm_ctl_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 247:46]
|
|
assign dccm_ctl_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[el2_lsu.scala 247:46]
|
|
assign dccm_ctl_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 248:46]
|
|
assign dccm_ctl_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[el2_lsu.scala 248:46]
|
|
assign dccm_ctl_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[el2_lsu.scala 248:46]
|
|
assign dccm_ctl_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[el2_lsu.scala 248:46]
|
|
assign dccm_ctl_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[el2_lsu.scala 248:46]
|
|
assign dccm_ctl_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[el2_lsu.scala 248:46]
|
|
assign dccm_ctl_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[el2_lsu.scala 248:46]
|
|
assign dccm_ctl_io_addr_in_dccm_d = lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 249:46]
|
|
assign dccm_ctl_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 250:46]
|
|
assign dccm_ctl_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 251:46]
|
|
assign dccm_ctl_io_addr_in_pic_d = lsu_lsc_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 252:46]
|
|
assign dccm_ctl_io_addr_in_pic_m = lsu_lsc_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 253:46]
|
|
assign dccm_ctl_io_addr_in_pic_r = lsu_lsc_ctl_io_addr_in_pic_r; // @[el2_lsu.scala 254:46]
|
|
assign dccm_ctl_io_lsu_raw_fwd_lo_r = lsu_raw_fwd_lo_r; // @[el2_lsu.scala 255:46]
|
|
assign dccm_ctl_io_lsu_raw_fwd_hi_r = lsu_raw_fwd_hi_r; // @[el2_lsu.scala 256:46]
|
|
assign dccm_ctl_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[el2_lsu.scala 257:46]
|
|
assign dccm_ctl_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[el2_lsu.scala 258:46]
|
|
assign dccm_ctl_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[el2_lsu.scala 259:46]
|
|
assign dccm_ctl_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[el2_lsu.scala 260:46]
|
|
assign dccm_ctl_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d[15:0]; // @[el2_lsu.scala 261:46]
|
|
assign dccm_ctl_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[el2_lsu.scala 262:46]
|
|
assign dccm_ctl_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r[15:0]; // @[el2_lsu.scala 263:46]
|
|
assign dccm_ctl_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[el2_lsu.scala 264:46]
|
|
assign dccm_ctl_io_stbuf_addr_any = stbuf_io_stbuf_addr_any; // @[el2_lsu.scala 265:46]
|
|
assign dccm_ctl_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[el2_lsu.scala 266:46]
|
|
assign dccm_ctl_io_stbuf_ecc_any = ecc_io_stbuf_ecc_any; // @[el2_lsu.scala 267:46]
|
|
assign dccm_ctl_io_stbuf_fwddata_hi_m = stbuf_io_stbuf_fwddata_hi_m; // @[el2_lsu.scala 268:46]
|
|
assign dccm_ctl_io_stbuf_fwddata_lo_m = stbuf_io_stbuf_fwddata_lo_m; // @[el2_lsu.scala 269:46]
|
|
assign dccm_ctl_io_stbuf_fwdbyteen_lo_m = stbuf_io_stbuf_fwdbyteen_lo_m; // @[el2_lsu.scala 270:46]
|
|
assign dccm_ctl_io_stbuf_fwdbyteen_hi_m = stbuf_io_stbuf_fwdbyteen_hi_m; // @[el2_lsu.scala 271:46]
|
|
assign dccm_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 272:46]
|
|
assign dccm_ctl_io_single_ecc_error_hi_r = ecc_io_single_ecc_error_hi_r; // @[el2_lsu.scala 273:46]
|
|
assign dccm_ctl_io_single_ecc_error_lo_r = ecc_io_single_ecc_error_lo_r; // @[el2_lsu.scala 274:46]
|
|
assign dccm_ctl_io_sec_data_hi_r_ff = ecc_io_sec_data_hi_r_ff; // @[el2_lsu.scala 277:46]
|
|
assign dccm_ctl_io_sec_data_lo_r_ff = ecc_io_sec_data_lo_r_ff; // @[el2_lsu.scala 278:46]
|
|
assign dccm_ctl_io_sec_data_ecc_hi_r_ff = ecc_io_sec_data_ecc_hi_r_ff; // @[el2_lsu.scala 279:46]
|
|
assign dccm_ctl_io_sec_data_ecc_lo_r_ff = ecc_io_sec_data_ecc_lo_r_ff; // @[el2_lsu.scala 280:46]
|
|
assign dccm_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 281:46]
|
|
assign dccm_ctl_io_sec_data_hi_m = ecc_io_sec_data_hi_m; // @[el2_lsu.scala 282:46]
|
|
assign dccm_ctl_io_sec_data_lo_m = ecc_io_sec_data_lo_m; // @[el2_lsu.scala 283:46]
|
|
assign dccm_ctl_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[el2_lsu.scala 284:46]
|
|
assign dccm_ctl_io_dma_dccm_wen = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 285:46]
|
|
assign dccm_ctl_io_dma_pic_wen = _T_10 & lsu_lsc_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 286:46]
|
|
assign dccm_ctl_io_dma_mem_tag_m = dma_mem_tag_m; // @[el2_lsu.scala 287:46]
|
|
assign dccm_ctl_io_dma_mem_addr = io_dma_mem_addr; // @[el2_lsu.scala 288:46]
|
|
assign dccm_ctl_io_dma_mem_wdata = io_dma_mem_wdata; // @[el2_lsu.scala 289:46]
|
|
assign dccm_ctl_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[el2_lsu.scala 290:46]
|
|
assign dccm_ctl_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[el2_lsu.scala 291:46]
|
|
assign dccm_ctl_io_dma_dccm_wdata_ecc_hi = ecc_io_dma_dccm_wdata_ecc_hi; // @[el2_lsu.scala 292:46]
|
|
assign dccm_ctl_io_dma_dccm_wdata_ecc_lo = ecc_io_dma_dccm_wdata_ecc_lo; // @[el2_lsu.scala 293:46]
|
|
assign dccm_ctl_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[el2_lsu.scala 294:46]
|
|
assign dccm_ctl_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[el2_lsu.scala 295:46]
|
|
assign dccm_ctl_io_picm_rd_data = io_picm_rd_data; // @[el2_lsu.scala 296:46]
|
|
assign dccm_ctl_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 297:46]
|
|
assign stbuf_clock = clock;
|
|
assign stbuf_reset = reset;
|
|
assign stbuf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 319:49]
|
|
assign stbuf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 320:48]
|
|
assign stbuf_io_lsu_stbuf_c1_clk = clkdomain_io_lsu_stbuf_c1_clk; // @[el2_lsu.scala 321:54]
|
|
assign stbuf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[el2_lsu.scala 322:54]
|
|
assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 323:48]
|
|
assign stbuf_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 323:48]
|
|
assign stbuf_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[el2_lsu.scala 323:48]
|
|
assign stbuf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 324:48]
|
|
assign stbuf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[el2_lsu.scala 324:48]
|
|
assign stbuf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[el2_lsu.scala 324:48]
|
|
assign stbuf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[el2_lsu.scala 324:48]
|
|
assign stbuf_io_lsu_pkt_r_bits_dword = lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[el2_lsu.scala 324:48]
|
|
assign stbuf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[el2_lsu.scala 324:48]
|
|
assign stbuf_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[el2_lsu.scala 324:48]
|
|
assign stbuf_io_store_stbuf_reqvld_r = _T_28 & _T_19; // @[el2_lsu.scala 325:48]
|
|
assign stbuf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[el2_lsu.scala 326:49]
|
|
assign stbuf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 327:49]
|
|
assign stbuf_io_store_data_hi_r = dccm_ctl_io_store_data_hi_r; // @[el2_lsu.scala 328:62]
|
|
assign stbuf_io_store_data_lo_r = dccm_ctl_io_store_data_lo_r; // @[el2_lsu.scala 329:62]
|
|
assign stbuf_io_store_datafn_hi_r = dccm_ctl_io_store_datafn_hi_r; // @[el2_lsu.scala 330:49]
|
|
assign stbuf_io_store_datafn_lo_r = dccm_ctl_io_store_datafn_lo_r; // @[el2_lsu.scala 331:56]
|
|
assign stbuf_io_lsu_stbuf_commit_any = dccm_ctl_io_lsu_stbuf_commit_any; // @[el2_lsu.scala 332:52]
|
|
assign stbuf_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d[15:0]; // @[el2_lsu.scala 333:64]
|
|
assign stbuf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[el2_lsu.scala 334:64]
|
|
assign stbuf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[el2_lsu.scala 335:64]
|
|
assign stbuf_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d[15:0]; // @[el2_lsu.scala 336:64]
|
|
assign stbuf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[el2_lsu.scala 337:64]
|
|
assign stbuf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[el2_lsu.scala 338:64]
|
|
assign stbuf_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 339:49]
|
|
assign stbuf_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 340:56]
|
|
assign stbuf_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 342:49]
|
|
assign ecc_clock = clock;
|
|
assign ecc_reset = reset;
|
|
assign ecc_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 346:52]
|
|
assign ecc_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 347:52]
|
|
assign ecc_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[el2_lsu.scala 347:52]
|
|
assign ecc_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 347:52]
|
|
assign ecc_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[el2_lsu.scala 347:52]
|
|
assign ecc_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[el2_lsu.scala 349:54]
|
|
assign ecc_io_dec_tlu_core_ecc_disable = io_dec_tlu_core_ecc_disable; // @[el2_lsu.scala 350:50]
|
|
assign ecc_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[el2_lsu.scala 355:58]
|
|
assign ecc_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[el2_lsu.scala 356:58]
|
|
assign ecc_io_dccm_rdata_hi_m = dccm_ctl_io_dccm_rdata_hi_m; // @[el2_lsu.scala 359:54]
|
|
assign ecc_io_dccm_rdata_lo_m = dccm_ctl_io_dccm_rdata_lo_m; // @[el2_lsu.scala 360:54]
|
|
assign ecc_io_dccm_data_ecc_hi_m = dccm_ctl_io_dccm_data_ecc_hi_m; // @[el2_lsu.scala 363:50]
|
|
assign ecc_io_dccm_data_ecc_lo_m = dccm_ctl_io_dccm_data_ecc_lo_m; // @[el2_lsu.scala 364:50]
|
|
assign ecc_io_ld_single_ecc_error_r = dccm_ctl_io_ld_single_ecc_error_r; // @[el2_lsu.scala 365:50]
|
|
assign ecc_io_ld_single_ecc_error_r_ff = dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 366:50]
|
|
assign ecc_io_lsu_dccm_rden_m = dccm_ctl_io_lsu_dccm_rden_m; // @[el2_lsu.scala 367:50]
|
|
assign ecc_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 368:50]
|
|
assign ecc_io_dma_dccm_wen = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 369:50]
|
|
assign ecc_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[el2_lsu.scala 370:50]
|
|
assign ecc_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[el2_lsu.scala 371:50]
|
|
assign ecc_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 372:50]
|
|
assign trigger_io_trigger_pkt_any_0_select = io_trigger_pkt_any_0_select; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_0_match_pkt = io_trigger_pkt_any_0_match_pkt; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_0_store = io_trigger_pkt_any_0_store; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_0_load = io_trigger_pkt_any_0_load; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_0_tdata2 = io_trigger_pkt_any_0_tdata2; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_1_select = io_trigger_pkt_any_1_select; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_1_match_pkt = io_trigger_pkt_any_1_match_pkt; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_1_store = io_trigger_pkt_any_1_store; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_1_load = io_trigger_pkt_any_1_load; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_1_tdata2 = io_trigger_pkt_any_1_tdata2; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_2_select = io_trigger_pkt_any_2_select; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_2_match_pkt = io_trigger_pkt_any_2_match_pkt; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_2_store = io_trigger_pkt_any_2_store; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_2_load = io_trigger_pkt_any_2_load; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_2_tdata2 = io_trigger_pkt_any_2_tdata2; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_3_select = io_trigger_pkt_any_3_select; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_3_match_pkt = io_trigger_pkt_any_3_match_pkt; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_3_store = io_trigger_pkt_any_3_store; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_3_load = io_trigger_pkt_any_3_load; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_trigger_pkt_any_3_tdata2 = io_trigger_pkt_any_3_tdata2; // @[el2_lsu.scala 376:50]
|
|
assign trigger_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 377:50]
|
|
assign trigger_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[el2_lsu.scala 377:50]
|
|
assign trigger_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[el2_lsu.scala 377:50]
|
|
assign trigger_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[el2_lsu.scala 377:50]
|
|
assign trigger_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 377:50]
|
|
assign trigger_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[el2_lsu.scala 377:50]
|
|
assign trigger_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[el2_lsu.scala 378:50]
|
|
assign trigger_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[el2_lsu.scala 379:50]
|
|
assign clkdomain_clock = clock;
|
|
assign clkdomain_reset = reset;
|
|
assign clkdomain_io_free_clk = io_free_clk; // @[el2_lsu.scala 385:50]
|
|
assign clkdomain_io_clk_override = io_clk_override; // @[el2_lsu.scala 386:50]
|
|
assign clkdomain_io_dma_dccm_req = io_dma_dccm_req; // @[el2_lsu.scala 388:50]
|
|
assign clkdomain_io_ldst_stbuf_reqvld_r = stbuf_io_ldst_stbuf_reqvld_r; // @[el2_lsu.scala 389:50]
|
|
assign clkdomain_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[el2_lsu.scala 390:50]
|
|
assign clkdomain_io_stbuf_reqvld_flushed_any = stbuf_io_stbuf_reqvld_flushed_any; // @[el2_lsu.scala 391:50]
|
|
assign clkdomain_io_lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[el2_lsu.scala 392:50]
|
|
assign clkdomain_io_lsu_bus_buffer_pend_any = bus_intf_io_lsu_bus_buffer_pend_any; // @[el2_lsu.scala 393:50]
|
|
assign clkdomain_io_lsu_bus_buffer_empty_any = bus_intf_io_lsu_bus_buffer_empty_any; // @[el2_lsu.scala 394:50]
|
|
assign clkdomain_io_lsu_stbuf_empty_any = stbuf_io_lsu_stbuf_empty_any; // @[el2_lsu.scala 395:50]
|
|
assign clkdomain_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_lsu.scala 396:50]
|
|
assign clkdomain_io_lsu_p_valid = io_lsu_p_valid; // @[el2_lsu.scala 397:50]
|
|
assign clkdomain_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 398:50]
|
|
assign clkdomain_io_lsu_pkt_d_bits_store = lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[el2_lsu.scala 398:50]
|
|
assign clkdomain_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 399:50]
|
|
assign clkdomain_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[el2_lsu.scala 399:50]
|
|
assign clkdomain_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 400:50]
|
|
assign clkdomain_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 401:50]
|
|
assign bus_intf_clock = clock;
|
|
assign bus_intf_reset = reset;
|
|
assign bus_intf_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 405:49]
|
|
assign bus_intf_io_dec_tlu_external_ldfwd_disable = io_dec_tlu_external_ldfwd_disable; // @[el2_lsu.scala 406:49]
|
|
assign bus_intf_io_dec_tlu_wb_coalescing_disable = io_dec_tlu_wb_coalescing_disable; // @[el2_lsu.scala 407:49]
|
|
assign bus_intf_io_dec_tlu_sideeffect_posted_disable = io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu.scala 408:49]
|
|
assign bus_intf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 409:49]
|
|
assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 410:49]
|
|
assign bus_intf_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 411:49]
|
|
assign bus_intf_io_lsu_bus_ibuf_c1_clk = clkdomain_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu.scala 412:49]
|
|
assign bus_intf_io_lsu_bus_obuf_c1_clk = clkdomain_io_lsu_bus_obuf_c1_clk; // @[el2_lsu.scala 413:49]
|
|
assign bus_intf_io_lsu_bus_buf_c1_clk = clkdomain_io_lsu_bus_buf_c1_clk; // @[el2_lsu.scala 414:49]
|
|
assign bus_intf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[el2_lsu.scala 415:49]
|
|
assign bus_intf_io_free_clk = io_free_clk; // @[el2_lsu.scala 416:49]
|
|
assign bus_intf_io_lsu_busm_clk = clkdomain_io_lsu_busm_clk; // @[el2_lsu.scala 417:49]
|
|
assign bus_intf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 418:49]
|
|
assign bus_intf_io_lsu_busreq_m = _T_39 & _T_40; // @[el2_lsu.scala 419:49]
|
|
assign bus_intf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 427:49]
|
|
assign bus_intf_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[el2_lsu.scala 427:49]
|
|
assign bus_intf_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[el2_lsu.scala 427:49]
|
|
assign bus_intf_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[el2_lsu.scala 427:49]
|
|
assign bus_intf_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[el2_lsu.scala 427:49]
|
|
assign bus_intf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 428:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[el2_lsu.scala 428:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[el2_lsu.scala 428:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[el2_lsu.scala 428:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[el2_lsu.scala 428:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[el2_lsu.scala 428:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_unsign = lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[el2_lsu.scala 428:49]
|
|
assign bus_intf_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[el2_lsu.scala 420:49]
|
|
assign bus_intf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[el2_lsu.scala 421:49]
|
|
assign bus_intf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[el2_lsu.scala 422:49]
|
|
assign bus_intf_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d; // @[el2_lsu.scala 423:49]
|
|
assign bus_intf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[el2_lsu.scala 424:49]
|
|
assign bus_intf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[el2_lsu.scala 425:49]
|
|
assign bus_intf_io_store_data_r = dccm_ctl_io_store_data_r; // @[el2_lsu.scala 426:49]
|
|
assign bus_intf_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[el2_lsu.scala 429:49]
|
|
assign bus_intf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[el2_lsu.scala 430:49]
|
|
assign bus_intf_io_is_sideeffects_m = lsu_lsc_ctl_io_is_sideeffects_m; // @[el2_lsu.scala 431:49]
|
|
assign bus_intf_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[el2_lsu.scala 432:49]
|
|
assign bus_intf_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[el2_lsu.scala 433:49]
|
|
assign bus_intf_io_lsu_axi_awready = io_lsu_axi_awready; // @[el2_lsu.scala 452:49]
|
|
assign bus_intf_io_lsu_axi_wready = io_lsu_axi_wready; // @[el2_lsu.scala 464:49]
|
|
assign bus_intf_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[el2_lsu.scala 468:49]
|
|
assign bus_intf_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[el2_lsu.scala 470:49]
|
|
assign bus_intf_io_lsu_axi_bid = io_lsu_axi_bid; // @[el2_lsu.scala 471:49]
|
|
assign bus_intf_io_lsu_axi_arready = io_lsu_axi_arready; // @[el2_lsu.scala 473:49]
|
|
assign bus_intf_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[el2_lsu.scala 484:49]
|
|
assign bus_intf_io_lsu_axi_rid = io_lsu_axi_rid; // @[el2_lsu.scala 486:49]
|
|
assign bus_intf_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[el2_lsu.scala 487:49]
|
|
assign bus_intf_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_lsu.scala 490:49]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
dma_mem_tag_m = _RAND_0[2:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
lsu_raw_fwd_hi_r = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
lsu_raw_fwd_lo_r = _RAND_2[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
dma_mem_tag_m = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_raw_fwd_hi_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_raw_fwd_lo_r = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clkdomain_io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_mem_tag_m <= 3'h0;
|
|
end else begin
|
|
dma_mem_tag_m <= io_dma_mem_tag;
|
|
end
|
|
end
|
|
always @(posedge clkdomain_io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_raw_fwd_hi_r <= 1'h0;
|
|
end else begin
|
|
lsu_raw_fwd_hi_r <= |stbuf_io_stbuf_fwdbyteen_hi_m;
|
|
end
|
|
end
|
|
always @(posedge clkdomain_io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_raw_fwd_lo_r <= 1'h0;
|
|
end else begin
|
|
lsu_raw_fwd_lo_r <= |stbuf_io_stbuf_fwdbyteen_lo_m;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_pic_ctrl(
|
|
input clock,
|
|
input reset,
|
|
input io_scan_mode,
|
|
input io_free_clk,
|
|
input io_active_clk,
|
|
input io_clk_override,
|
|
input [31:0] io_extintsrc_req,
|
|
input [31:0] io_picm_rdaddr,
|
|
input [31:0] io_picm_wraddr,
|
|
input [31:0] io_picm_wr_data,
|
|
input io_picm_wren,
|
|
input io_picm_rden,
|
|
input io_picm_mken,
|
|
input [3:0] io_meicurpl,
|
|
input [3:0] io_meipt,
|
|
output io_mexintpend,
|
|
output [7:0] io_claimid,
|
|
output [3:0] io_pl,
|
|
output [31:0] io_picm_rd_data,
|
|
output io_mhwakeup
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
reg [31:0] _RAND_75;
|
|
reg [31:0] _RAND_76;
|
|
reg [31:0] _RAND_77;
|
|
reg [31:0] _RAND_78;
|
|
reg [31:0] _RAND_79;
|
|
reg [31:0] _RAND_80;
|
|
reg [31:0] _RAND_81;
|
|
reg [31:0] _RAND_82;
|
|
reg [31:0] _RAND_83;
|
|
reg [31:0] _RAND_84;
|
|
reg [31:0] _RAND_85;
|
|
reg [31:0] _RAND_86;
|
|
reg [31:0] _RAND_87;
|
|
reg [31:0] _RAND_88;
|
|
reg [31:0] _RAND_89;
|
|
reg [31:0] _RAND_90;
|
|
reg [31:0] _RAND_91;
|
|
reg [31:0] _RAND_92;
|
|
reg [31:0] _RAND_93;
|
|
reg [31:0] _RAND_94;
|
|
reg [31:0] _RAND_95;
|
|
reg [31:0] _RAND_96;
|
|
reg [31:0] _RAND_97;
|
|
reg [31:0] _RAND_98;
|
|
reg [31:0] _RAND_99;
|
|
reg [31:0] _RAND_100;
|
|
reg [31:0] _RAND_101;
|
|
reg [31:0] _RAND_102;
|
|
reg [31:0] _RAND_103;
|
|
reg [31:0] _RAND_104;
|
|
reg [31:0] _RAND_105;
|
|
reg [31:0] _RAND_106;
|
|
reg [31:0] _RAND_107;
|
|
reg [31:0] _RAND_108;
|
|
reg [31:0] _RAND_109;
|
|
reg [31:0] _RAND_110;
|
|
reg [31:0] _RAND_111;
|
|
reg [31:0] _RAND_112;
|
|
reg [31:0] _RAND_113;
|
|
reg [31:0] _RAND_114;
|
|
reg [31:0] _RAND_115;
|
|
reg [31:0] _RAND_116;
|
|
reg [31:0] _RAND_117;
|
|
reg [31:0] _RAND_118;
|
|
reg [31:0] _RAND_119;
|
|
reg [31:0] _RAND_120;
|
|
reg [31:0] _RAND_121;
|
|
reg [31:0] _RAND_122;
|
|
reg [31:0] _RAND_123;
|
|
reg [31:0] _RAND_124;
|
|
reg [31:0] _RAND_125;
|
|
reg [31:0] _RAND_126;
|
|
reg [31:0] _RAND_127;
|
|
reg [31:0] _RAND_128;
|
|
reg [31:0] _RAND_129;
|
|
reg [31:0] _RAND_130;
|
|
reg [31:0] _RAND_131;
|
|
reg [31:0] _RAND_132;
|
|
reg [31:0] _RAND_133;
|
|
reg [31:0] _RAND_134;
|
|
reg [31:0] _RAND_135;
|
|
reg [31:0] _RAND_136;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire pic_raddr_c1_clk = rvclkhdr_io_l1clk; // @[el2_pic_ctl.scala 101:42 el2_pic_ctl.scala 138:21]
|
|
reg [31:0] picm_raddr_ff; // @[el2_pic_ctl.scala 107:56]
|
|
wire pic_data_c1_clk = rvclkhdr_1_io_l1clk; // @[el2_pic_ctl.scala 102:42 el2_pic_ctl.scala 139:21]
|
|
reg [31:0] picm_waddr_ff; // @[el2_pic_ctl.scala 108:57]
|
|
reg picm_wren_ff; // @[el2_pic_ctl.scala 109:55]
|
|
reg picm_rden_ff; // @[el2_pic_ctl.scala 110:55]
|
|
reg picm_mken_ff; // @[el2_pic_ctl.scala 111:55]
|
|
reg [31:0] picm_wr_data_ff; // @[el2_pic_ctl.scala 112:58]
|
|
wire [31:0] _T_6 = picm_raddr_ff ^ 32'hf00c2000; // @[el2_pic_ctl.scala 114:59]
|
|
wire [31:0] temp_raddr_intenable_base_match = ~_T_6; // @[el2_pic_ctl.scala 114:43]
|
|
wire raddr_intenable_base_match = &temp_raddr_intenable_base_match[31:7]; // @[el2_pic_ctl.scala 115:89]
|
|
wire raddr_intpriority_base_match = picm_raddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctl.scala 117:71]
|
|
wire raddr_config_gw_base_match = picm_raddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctl.scala 118:71]
|
|
wire raddr_config_pic_match = picm_raddr_ff == 32'hf00c3000; // @[el2_pic_ctl.scala 119:71]
|
|
wire addr_intpend_base_match = picm_raddr_ff[31:6] == 26'h3c03040; // @[el2_pic_ctl.scala 120:71]
|
|
wire waddr_config_pic_match = picm_waddr_ff == 32'hf00c3000; // @[el2_pic_ctl.scala 122:71]
|
|
wire addr_clear_gw_base_match = picm_waddr_ff[31:7] == 25'h1e018a0; // @[el2_pic_ctl.scala 123:71]
|
|
wire waddr_intpriority_base_match = picm_waddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctl.scala 124:71]
|
|
wire waddr_intenable_base_match = picm_waddr_ff[31:7] == 25'h1e01840; // @[el2_pic_ctl.scala 125:71]
|
|
wire waddr_config_gw_base_match = picm_waddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctl.scala 126:71]
|
|
wire _T_17 = picm_rden_ff & picm_wren_ff; // @[el2_pic_ctl.scala 127:53]
|
|
wire _T_18 = picm_raddr_ff == picm_waddr_ff; // @[el2_pic_ctl.scala 127:86]
|
|
wire picm_bypass_ff = _T_17 & _T_18; // @[el2_pic_ctl.scala 127:68]
|
|
wire _T_19 = io_picm_mken | io_picm_rden; // @[el2_pic_ctl.scala 131:42]
|
|
wire _T_20 = waddr_intpriority_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 133:59]
|
|
wire _T_21 = raddr_intpriority_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 133:108]
|
|
wire _T_22 = _T_20 | _T_21; // @[el2_pic_ctl.scala 133:76]
|
|
wire _T_23 = waddr_intenable_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 134:57]
|
|
wire _T_24 = raddr_intenable_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 134:104]
|
|
wire _T_25 = _T_23 | _T_24; // @[el2_pic_ctl.scala 134:74]
|
|
wire _T_26 = waddr_config_gw_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 135:59]
|
|
wire _T_27 = raddr_config_gw_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 135:108]
|
|
wire _T_28 = _T_26 | _T_27; // @[el2_pic_ctl.scala 135:76]
|
|
reg [30:0] _T_33; // @[el2_lib.scala 177:81]
|
|
reg [30:0] _T_34; // @[el2_lib.scala 177:58]
|
|
wire [31:0] extintsrc_req_sync = {_T_34,io_extintsrc_req[0]}; // @[Cat.scala 29:58]
|
|
wire _T_37 = picm_waddr_ff[6:2] == 5'h1; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_38 = waddr_intpriority_base_match & _T_37; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_1 = _T_38 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_40 = picm_waddr_ff[6:2] == 5'h2; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_41 = waddr_intpriority_base_match & _T_40; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_2 = _T_41 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_43 = picm_waddr_ff[6:2] == 5'h3; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_44 = waddr_intpriority_base_match & _T_43; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_3 = _T_44 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_46 = picm_waddr_ff[6:2] == 5'h4; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_47 = waddr_intpriority_base_match & _T_46; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_4 = _T_47 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_49 = picm_waddr_ff[6:2] == 5'h5; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_50 = waddr_intpriority_base_match & _T_49; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_5 = _T_50 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_52 = picm_waddr_ff[6:2] == 5'h6; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_53 = waddr_intpriority_base_match & _T_52; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_6 = _T_53 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_55 = picm_waddr_ff[6:2] == 5'h7; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_56 = waddr_intpriority_base_match & _T_55; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_7 = _T_56 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_58 = picm_waddr_ff[6:2] == 5'h8; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_59 = waddr_intpriority_base_match & _T_58; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_8 = _T_59 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_61 = picm_waddr_ff[6:2] == 5'h9; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_62 = waddr_intpriority_base_match & _T_61; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_9 = _T_62 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_64 = picm_waddr_ff[6:2] == 5'ha; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_65 = waddr_intpriority_base_match & _T_64; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_10 = _T_65 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_67 = picm_waddr_ff[6:2] == 5'hb; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_68 = waddr_intpriority_base_match & _T_67; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_11 = _T_68 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_70 = picm_waddr_ff[6:2] == 5'hc; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_71 = waddr_intpriority_base_match & _T_70; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_12 = _T_71 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_73 = picm_waddr_ff[6:2] == 5'hd; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_74 = waddr_intpriority_base_match & _T_73; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_13 = _T_74 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_76 = picm_waddr_ff[6:2] == 5'he; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_77 = waddr_intpriority_base_match & _T_76; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_14 = _T_77 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_79 = picm_waddr_ff[6:2] == 5'hf; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_80 = waddr_intpriority_base_match & _T_79; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_15 = _T_80 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_82 = picm_waddr_ff[6:2] == 5'h10; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_83 = waddr_intpriority_base_match & _T_82; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_16 = _T_83 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_85 = picm_waddr_ff[6:2] == 5'h11; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_86 = waddr_intpriority_base_match & _T_85; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_17 = _T_86 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_88 = picm_waddr_ff[6:2] == 5'h12; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_89 = waddr_intpriority_base_match & _T_88; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_18 = _T_89 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_91 = picm_waddr_ff[6:2] == 5'h13; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_92 = waddr_intpriority_base_match & _T_91; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_19 = _T_92 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_94 = picm_waddr_ff[6:2] == 5'h14; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_95 = waddr_intpriority_base_match & _T_94; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_20 = _T_95 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_97 = picm_waddr_ff[6:2] == 5'h15; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_98 = waddr_intpriority_base_match & _T_97; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_21 = _T_98 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_100 = picm_waddr_ff[6:2] == 5'h16; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_101 = waddr_intpriority_base_match & _T_100; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_22 = _T_101 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_103 = picm_waddr_ff[6:2] == 5'h17; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_104 = waddr_intpriority_base_match & _T_103; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_23 = _T_104 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_106 = picm_waddr_ff[6:2] == 5'h18; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_107 = waddr_intpriority_base_match & _T_106; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_24 = _T_107 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_109 = picm_waddr_ff[6:2] == 5'h19; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_110 = waddr_intpriority_base_match & _T_109; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_25 = _T_110 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_112 = picm_waddr_ff[6:2] == 5'h1a; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_113 = waddr_intpriority_base_match & _T_112; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_26 = _T_113 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_115 = picm_waddr_ff[6:2] == 5'h1b; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_116 = waddr_intpriority_base_match & _T_115; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_27 = _T_116 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_118 = picm_waddr_ff[6:2] == 5'h1c; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_119 = waddr_intpriority_base_match & _T_118; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_28 = _T_119 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_121 = picm_waddr_ff[6:2] == 5'h1d; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_122 = waddr_intpriority_base_match & _T_121; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_29 = _T_122 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_124 = picm_waddr_ff[6:2] == 5'h1e; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_125 = waddr_intpriority_base_match & _T_124; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_30 = _T_125 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_127 = picm_waddr_ff[6:2] == 5'h1f; // @[el2_pic_ctl.scala 147:139]
|
|
wire _T_128 = waddr_intpriority_base_match & _T_127; // @[el2_pic_ctl.scala 147:106]
|
|
wire intpriority_reg_we_31 = _T_128 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153]
|
|
wire _T_130 = picm_raddr_ff[6:2] == 5'h1; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_131 = raddr_intpriority_base_match & _T_130; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_1 = _T_131 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_133 = picm_raddr_ff[6:2] == 5'h2; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_134 = raddr_intpriority_base_match & _T_133; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_2 = _T_134 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_136 = picm_raddr_ff[6:2] == 5'h3; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_137 = raddr_intpriority_base_match & _T_136; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_3 = _T_137 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_139 = picm_raddr_ff[6:2] == 5'h4; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_140 = raddr_intpriority_base_match & _T_139; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_4 = _T_140 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_142 = picm_raddr_ff[6:2] == 5'h5; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_143 = raddr_intpriority_base_match & _T_142; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_5 = _T_143 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_145 = picm_raddr_ff[6:2] == 5'h6; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_146 = raddr_intpriority_base_match & _T_145; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_6 = _T_146 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_148 = picm_raddr_ff[6:2] == 5'h7; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_149 = raddr_intpriority_base_match & _T_148; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_7 = _T_149 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_151 = picm_raddr_ff[6:2] == 5'h8; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_152 = raddr_intpriority_base_match & _T_151; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_8 = _T_152 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_154 = picm_raddr_ff[6:2] == 5'h9; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_155 = raddr_intpriority_base_match & _T_154; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_9 = _T_155 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_157 = picm_raddr_ff[6:2] == 5'ha; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_158 = raddr_intpriority_base_match & _T_157; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_10 = _T_158 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_160 = picm_raddr_ff[6:2] == 5'hb; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_161 = raddr_intpriority_base_match & _T_160; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_11 = _T_161 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_163 = picm_raddr_ff[6:2] == 5'hc; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_164 = raddr_intpriority_base_match & _T_163; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_12 = _T_164 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_166 = picm_raddr_ff[6:2] == 5'hd; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_167 = raddr_intpriority_base_match & _T_166; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_13 = _T_167 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_169 = picm_raddr_ff[6:2] == 5'he; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_170 = raddr_intpriority_base_match & _T_169; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_14 = _T_170 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_172 = picm_raddr_ff[6:2] == 5'hf; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_173 = raddr_intpriority_base_match & _T_172; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_15 = _T_173 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_175 = picm_raddr_ff[6:2] == 5'h10; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_176 = raddr_intpriority_base_match & _T_175; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_16 = _T_176 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_178 = picm_raddr_ff[6:2] == 5'h11; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_179 = raddr_intpriority_base_match & _T_178; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_17 = _T_179 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_181 = picm_raddr_ff[6:2] == 5'h12; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_182 = raddr_intpriority_base_match & _T_181; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_18 = _T_182 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_184 = picm_raddr_ff[6:2] == 5'h13; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_185 = raddr_intpriority_base_match & _T_184; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_19 = _T_185 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_187 = picm_raddr_ff[6:2] == 5'h14; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_188 = raddr_intpriority_base_match & _T_187; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_20 = _T_188 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_190 = picm_raddr_ff[6:2] == 5'h15; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_191 = raddr_intpriority_base_match & _T_190; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_21 = _T_191 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_193 = picm_raddr_ff[6:2] == 5'h16; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_194 = raddr_intpriority_base_match & _T_193; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_22 = _T_194 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_196 = picm_raddr_ff[6:2] == 5'h17; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_197 = raddr_intpriority_base_match & _T_196; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_23 = _T_197 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_199 = picm_raddr_ff[6:2] == 5'h18; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_200 = raddr_intpriority_base_match & _T_199; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_24 = _T_200 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_202 = picm_raddr_ff[6:2] == 5'h19; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_203 = raddr_intpriority_base_match & _T_202; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_25 = _T_203 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_205 = picm_raddr_ff[6:2] == 5'h1a; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_206 = raddr_intpriority_base_match & _T_205; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_26 = _T_206 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_208 = picm_raddr_ff[6:2] == 5'h1b; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_209 = raddr_intpriority_base_match & _T_208; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_27 = _T_209 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_211 = picm_raddr_ff[6:2] == 5'h1c; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_212 = raddr_intpriority_base_match & _T_211; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_28 = _T_212 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_214 = picm_raddr_ff[6:2] == 5'h1d; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_215 = raddr_intpriority_base_match & _T_214; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_29 = _T_215 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_217 = picm_raddr_ff[6:2] == 5'h1e; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_218 = raddr_intpriority_base_match & _T_217; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_30 = _T_218 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_220 = picm_raddr_ff[6:2] == 5'h1f; // @[el2_pic_ctl.scala 148:139]
|
|
wire _T_221 = raddr_intpriority_base_match & _T_220; // @[el2_pic_ctl.scala 148:106]
|
|
wire intpriority_reg_re_31 = _T_221 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153]
|
|
wire _T_224 = waddr_intenable_base_match & _T_37; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_1 = _T_224 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_227 = waddr_intenable_base_match & _T_40; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_2 = _T_227 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_230 = waddr_intenable_base_match & _T_43; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_3 = _T_230 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_233 = waddr_intenable_base_match & _T_46; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_4 = _T_233 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_236 = waddr_intenable_base_match & _T_49; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_5 = _T_236 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_239 = waddr_intenable_base_match & _T_52; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_6 = _T_239 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_242 = waddr_intenable_base_match & _T_55; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_7 = _T_242 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_245 = waddr_intenable_base_match & _T_58; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_8 = _T_245 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_248 = waddr_intenable_base_match & _T_61; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_9 = _T_248 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_251 = waddr_intenable_base_match & _T_64; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_10 = _T_251 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_254 = waddr_intenable_base_match & _T_67; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_11 = _T_254 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_257 = waddr_intenable_base_match & _T_70; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_12 = _T_257 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_260 = waddr_intenable_base_match & _T_73; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_13 = _T_260 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_263 = waddr_intenable_base_match & _T_76; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_14 = _T_263 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_266 = waddr_intenable_base_match & _T_79; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_15 = _T_266 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_269 = waddr_intenable_base_match & _T_82; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_16 = _T_269 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_272 = waddr_intenable_base_match & _T_85; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_17 = _T_272 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_275 = waddr_intenable_base_match & _T_88; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_18 = _T_275 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_278 = waddr_intenable_base_match & _T_91; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_19 = _T_278 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_281 = waddr_intenable_base_match & _T_94; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_20 = _T_281 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_284 = waddr_intenable_base_match & _T_97; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_21 = _T_284 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_287 = waddr_intenable_base_match & _T_100; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_22 = _T_287 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_290 = waddr_intenable_base_match & _T_103; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_23 = _T_290 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_293 = waddr_intenable_base_match & _T_106; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_24 = _T_293 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_296 = waddr_intenable_base_match & _T_109; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_25 = _T_296 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_299 = waddr_intenable_base_match & _T_112; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_26 = _T_299 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_302 = waddr_intenable_base_match & _T_115; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_27 = _T_302 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_305 = waddr_intenable_base_match & _T_118; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_28 = _T_305 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_308 = waddr_intenable_base_match & _T_121; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_29 = _T_308 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_311 = waddr_intenable_base_match & _T_124; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_30 = _T_311 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_314 = waddr_intenable_base_match & _T_127; // @[el2_pic_ctl.scala 149:106]
|
|
wire intenable_reg_we_31 = _T_314 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153]
|
|
wire _T_407 = raddr_intenable_base_match & _T_220; // @[el2_pic_ctl.scala 150:106]
|
|
wire intenable_reg_re_31 = _T_407 & picm_rden_ff; // @[el2_pic_ctl.scala 150:153]
|
|
wire _T_410 = waddr_config_gw_base_match & _T_37; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_1 = _T_410 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_413 = waddr_config_gw_base_match & _T_40; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_2 = _T_413 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_416 = waddr_config_gw_base_match & _T_43; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_3 = _T_416 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_419 = waddr_config_gw_base_match & _T_46; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_4 = _T_419 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_422 = waddr_config_gw_base_match & _T_49; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_5 = _T_422 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_425 = waddr_config_gw_base_match & _T_52; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_6 = _T_425 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_428 = waddr_config_gw_base_match & _T_55; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_7 = _T_428 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_431 = waddr_config_gw_base_match & _T_58; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_8 = _T_431 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_434 = waddr_config_gw_base_match & _T_61; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_9 = _T_434 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_437 = waddr_config_gw_base_match & _T_64; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_10 = _T_437 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_440 = waddr_config_gw_base_match & _T_67; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_11 = _T_440 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_443 = waddr_config_gw_base_match & _T_70; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_12 = _T_443 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_446 = waddr_config_gw_base_match & _T_73; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_13 = _T_446 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_449 = waddr_config_gw_base_match & _T_76; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_14 = _T_449 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_452 = waddr_config_gw_base_match & _T_79; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_15 = _T_452 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_455 = waddr_config_gw_base_match & _T_82; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_16 = _T_455 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_458 = waddr_config_gw_base_match & _T_85; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_17 = _T_458 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_461 = waddr_config_gw_base_match & _T_88; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_18 = _T_461 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_464 = waddr_config_gw_base_match & _T_91; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_19 = _T_464 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_467 = waddr_config_gw_base_match & _T_94; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_20 = _T_467 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_470 = waddr_config_gw_base_match & _T_97; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_21 = _T_470 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_473 = waddr_config_gw_base_match & _T_100; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_22 = _T_473 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_476 = waddr_config_gw_base_match & _T_103; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_23 = _T_476 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_479 = waddr_config_gw_base_match & _T_106; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_24 = _T_479 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_482 = waddr_config_gw_base_match & _T_109; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_25 = _T_482 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_485 = waddr_config_gw_base_match & _T_112; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_26 = _T_485 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_488 = waddr_config_gw_base_match & _T_115; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_27 = _T_488 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_491 = waddr_config_gw_base_match & _T_118; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_28 = _T_491 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_494 = waddr_config_gw_base_match & _T_121; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_29 = _T_494 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_497 = waddr_config_gw_base_match & _T_124; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_30 = _T_497 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_500 = waddr_config_gw_base_match & _T_127; // @[el2_pic_ctl.scala 151:106]
|
|
wire gw_config_reg_we_31 = _T_500 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153]
|
|
wire _T_503 = raddr_config_gw_base_match & _T_130; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_1 = _T_503 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_506 = raddr_config_gw_base_match & _T_133; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_2 = _T_506 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_509 = raddr_config_gw_base_match & _T_136; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_3 = _T_509 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_512 = raddr_config_gw_base_match & _T_139; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_4 = _T_512 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_515 = raddr_config_gw_base_match & _T_142; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_5 = _T_515 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_518 = raddr_config_gw_base_match & _T_145; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_6 = _T_518 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_521 = raddr_config_gw_base_match & _T_148; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_7 = _T_521 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_524 = raddr_config_gw_base_match & _T_151; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_8 = _T_524 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_527 = raddr_config_gw_base_match & _T_154; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_9 = _T_527 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_530 = raddr_config_gw_base_match & _T_157; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_10 = _T_530 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_533 = raddr_config_gw_base_match & _T_160; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_11 = _T_533 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_536 = raddr_config_gw_base_match & _T_163; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_12 = _T_536 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_539 = raddr_config_gw_base_match & _T_166; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_13 = _T_539 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_542 = raddr_config_gw_base_match & _T_169; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_14 = _T_542 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_545 = raddr_config_gw_base_match & _T_172; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_15 = _T_545 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_548 = raddr_config_gw_base_match & _T_175; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_16 = _T_548 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_551 = raddr_config_gw_base_match & _T_178; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_17 = _T_551 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_554 = raddr_config_gw_base_match & _T_181; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_18 = _T_554 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_557 = raddr_config_gw_base_match & _T_184; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_19 = _T_557 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_560 = raddr_config_gw_base_match & _T_187; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_20 = _T_560 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_563 = raddr_config_gw_base_match & _T_190; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_21 = _T_563 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_566 = raddr_config_gw_base_match & _T_193; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_22 = _T_566 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_569 = raddr_config_gw_base_match & _T_196; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_23 = _T_569 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_572 = raddr_config_gw_base_match & _T_199; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_24 = _T_572 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_575 = raddr_config_gw_base_match & _T_202; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_25 = _T_575 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_578 = raddr_config_gw_base_match & _T_205; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_26 = _T_578 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_581 = raddr_config_gw_base_match & _T_208; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_27 = _T_581 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_584 = raddr_config_gw_base_match & _T_211; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_28 = _T_584 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_587 = raddr_config_gw_base_match & _T_214; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_29 = _T_587 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_590 = raddr_config_gw_base_match & _T_217; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_30 = _T_590 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_593 = raddr_config_gw_base_match & _T_220; // @[el2_pic_ctl.scala 152:106]
|
|
wire gw_config_reg_re_31 = _T_593 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153]
|
|
wire _T_596 = addr_clear_gw_base_match & _T_37; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_1 = _T_596 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_599 = addr_clear_gw_base_match & _T_40; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_2 = _T_599 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_602 = addr_clear_gw_base_match & _T_43; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_3 = _T_602 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_605 = addr_clear_gw_base_match & _T_46; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_4 = _T_605 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_608 = addr_clear_gw_base_match & _T_49; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_5 = _T_608 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_611 = addr_clear_gw_base_match & _T_52; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_6 = _T_611 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_614 = addr_clear_gw_base_match & _T_55; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_7 = _T_614 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_617 = addr_clear_gw_base_match & _T_58; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_8 = _T_617 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_620 = addr_clear_gw_base_match & _T_61; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_9 = _T_620 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_623 = addr_clear_gw_base_match & _T_64; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_10 = _T_623 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_626 = addr_clear_gw_base_match & _T_67; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_11 = _T_626 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_629 = addr_clear_gw_base_match & _T_70; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_12 = _T_629 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_632 = addr_clear_gw_base_match & _T_73; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_13 = _T_632 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_635 = addr_clear_gw_base_match & _T_76; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_14 = _T_635 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_638 = addr_clear_gw_base_match & _T_79; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_15 = _T_638 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_641 = addr_clear_gw_base_match & _T_82; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_16 = _T_641 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_644 = addr_clear_gw_base_match & _T_85; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_17 = _T_644 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_647 = addr_clear_gw_base_match & _T_88; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_18 = _T_647 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_650 = addr_clear_gw_base_match & _T_91; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_19 = _T_650 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_653 = addr_clear_gw_base_match & _T_94; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_20 = _T_653 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_656 = addr_clear_gw_base_match & _T_97; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_21 = _T_656 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_659 = addr_clear_gw_base_match & _T_100; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_22 = _T_659 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_662 = addr_clear_gw_base_match & _T_103; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_23 = _T_662 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_665 = addr_clear_gw_base_match & _T_106; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_24 = _T_665 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_668 = addr_clear_gw_base_match & _T_109; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_25 = _T_668 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_671 = addr_clear_gw_base_match & _T_112; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_26 = _T_671 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_674 = addr_clear_gw_base_match & _T_115; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_27 = _T_674 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_677 = addr_clear_gw_base_match & _T_118; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_28 = _T_677 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_680 = addr_clear_gw_base_match & _T_121; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_29 = _T_680 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_683 = addr_clear_gw_base_match & _T_124; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_30 = _T_683 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire _T_686 = addr_clear_gw_base_match & _T_127; // @[el2_pic_ctl.scala 153:106]
|
|
wire gw_clear_reg_we_31 = _T_686 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153]
|
|
wire pic_pri_c1_clk = rvclkhdr_2_io_l1clk; // @[el2_pic_ctl.scala 103:42 el2_pic_ctl.scala 140:21]
|
|
reg [3:0] intpriority_reg_1; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_2; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_3; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_4; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_5; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_6; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_7; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_8; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_9; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_10; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_11; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_12; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_13; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_14; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_15; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_16; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_17; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_18; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_19; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_20; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_21; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_22; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_23; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_24; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_25; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_26; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_27; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_28; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_29; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_30; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_31; // @[Reg.scala 27:20]
|
|
wire pic_int_c1_clk = rvclkhdr_3_io_l1clk; // @[el2_pic_ctl.scala 104:42 el2_pic_ctl.scala 141:21]
|
|
reg intenable_reg_1; // @[Reg.scala 27:20]
|
|
reg intenable_reg_2; // @[Reg.scala 27:20]
|
|
reg intenable_reg_3; // @[Reg.scala 27:20]
|
|
reg intenable_reg_4; // @[Reg.scala 27:20]
|
|
reg intenable_reg_5; // @[Reg.scala 27:20]
|
|
reg intenable_reg_6; // @[Reg.scala 27:20]
|
|
reg intenable_reg_7; // @[Reg.scala 27:20]
|
|
reg intenable_reg_8; // @[Reg.scala 27:20]
|
|
reg intenable_reg_9; // @[Reg.scala 27:20]
|
|
reg intenable_reg_10; // @[Reg.scala 27:20]
|
|
reg intenable_reg_11; // @[Reg.scala 27:20]
|
|
reg intenable_reg_12; // @[Reg.scala 27:20]
|
|
reg intenable_reg_13; // @[Reg.scala 27:20]
|
|
reg intenable_reg_14; // @[Reg.scala 27:20]
|
|
reg intenable_reg_15; // @[Reg.scala 27:20]
|
|
reg intenable_reg_16; // @[Reg.scala 27:20]
|
|
reg intenable_reg_17; // @[Reg.scala 27:20]
|
|
reg intenable_reg_18; // @[Reg.scala 27:20]
|
|
reg intenable_reg_19; // @[Reg.scala 27:20]
|
|
reg intenable_reg_20; // @[Reg.scala 27:20]
|
|
reg intenable_reg_21; // @[Reg.scala 27:20]
|
|
reg intenable_reg_22; // @[Reg.scala 27:20]
|
|
reg intenable_reg_23; // @[Reg.scala 27:20]
|
|
reg intenable_reg_24; // @[Reg.scala 27:20]
|
|
reg intenable_reg_25; // @[Reg.scala 27:20]
|
|
reg intenable_reg_26; // @[Reg.scala 27:20]
|
|
reg intenable_reg_27; // @[Reg.scala 27:20]
|
|
reg intenable_reg_28; // @[Reg.scala 27:20]
|
|
reg intenable_reg_29; // @[Reg.scala 27:20]
|
|
reg intenable_reg_30; // @[Reg.scala 27:20]
|
|
reg intenable_reg_31; // @[Reg.scala 27:20]
|
|
wire gw_config_c1_clk = rvclkhdr_4_io_l1clk; // @[el2_pic_ctl.scala 105:42 el2_pic_ctl.scala 142:21]
|
|
reg [1:0] gw_config_reg_1; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_2; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_3; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_4; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_5; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_6; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_7; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_8; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_9; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_10; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_11; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_12; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_13; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_14; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_15; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_16; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_17; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_18; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_19; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_20; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_21; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_22; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_23; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_24; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_25; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_26; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_27; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_28; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_29; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_30; // @[Reg.scala 27:20]
|
|
reg [1:0] gw_config_reg_31; // @[Reg.scala 27:20]
|
|
wire _T_970 = extintsrc_req_sync[1] ^ gw_config_reg_1[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_971 = ~gw_clear_reg_we_1; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_972 = gw_int_pending & _T_971; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_976 = _T_970 | gw_int_pending; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_1 = gw_config_reg_1[1] ? _T_976 : _T_970; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_982 = extintsrc_req_sync[2] ^ gw_config_reg_2[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_983 = ~gw_clear_reg_we_2; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_1; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_984 = gw_int_pending_1 & _T_983; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_988 = _T_982 | gw_int_pending_1; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_2 = gw_config_reg_2[1] ? _T_988 : _T_982; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_994 = extintsrc_req_sync[3] ^ gw_config_reg_3[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_995 = ~gw_clear_reg_we_3; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_2; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_996 = gw_int_pending_2 & _T_995; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1000 = _T_994 | gw_int_pending_2; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_3 = gw_config_reg_3[1] ? _T_1000 : _T_994; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1006 = extintsrc_req_sync[4] ^ gw_config_reg_4[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1007 = ~gw_clear_reg_we_4; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_3; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1008 = gw_int_pending_3 & _T_1007; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1012 = _T_1006 | gw_int_pending_3; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_4 = gw_config_reg_4[1] ? _T_1012 : _T_1006; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1018 = extintsrc_req_sync[5] ^ gw_config_reg_5[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1019 = ~gw_clear_reg_we_5; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_4; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1020 = gw_int_pending_4 & _T_1019; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1024 = _T_1018 | gw_int_pending_4; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_5 = gw_config_reg_5[1] ? _T_1024 : _T_1018; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1030 = extintsrc_req_sync[6] ^ gw_config_reg_6[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1031 = ~gw_clear_reg_we_6; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_5; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1032 = gw_int_pending_5 & _T_1031; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1036 = _T_1030 | gw_int_pending_5; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_6 = gw_config_reg_6[1] ? _T_1036 : _T_1030; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1042 = extintsrc_req_sync[7] ^ gw_config_reg_7[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1043 = ~gw_clear_reg_we_7; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_6; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1044 = gw_int_pending_6 & _T_1043; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1048 = _T_1042 | gw_int_pending_6; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_7 = gw_config_reg_7[1] ? _T_1048 : _T_1042; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1054 = extintsrc_req_sync[8] ^ gw_config_reg_8[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1055 = ~gw_clear_reg_we_8; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_7; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1056 = gw_int_pending_7 & _T_1055; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1060 = _T_1054 | gw_int_pending_7; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_8 = gw_config_reg_8[1] ? _T_1060 : _T_1054; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1066 = extintsrc_req_sync[9] ^ gw_config_reg_9[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1067 = ~gw_clear_reg_we_9; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_8; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1068 = gw_int_pending_8 & _T_1067; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1072 = _T_1066 | gw_int_pending_8; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_9 = gw_config_reg_9[1] ? _T_1072 : _T_1066; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1078 = extintsrc_req_sync[10] ^ gw_config_reg_10[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1079 = ~gw_clear_reg_we_10; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_9; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1080 = gw_int_pending_9 & _T_1079; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1084 = _T_1078 | gw_int_pending_9; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_10 = gw_config_reg_10[1] ? _T_1084 : _T_1078; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1090 = extintsrc_req_sync[11] ^ gw_config_reg_11[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1091 = ~gw_clear_reg_we_11; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_10; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1092 = gw_int_pending_10 & _T_1091; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1096 = _T_1090 | gw_int_pending_10; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_11 = gw_config_reg_11[1] ? _T_1096 : _T_1090; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1102 = extintsrc_req_sync[12] ^ gw_config_reg_12[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1103 = ~gw_clear_reg_we_12; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_11; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1104 = gw_int_pending_11 & _T_1103; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1108 = _T_1102 | gw_int_pending_11; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_12 = gw_config_reg_12[1] ? _T_1108 : _T_1102; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1114 = extintsrc_req_sync[13] ^ gw_config_reg_13[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1115 = ~gw_clear_reg_we_13; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_12; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1116 = gw_int_pending_12 & _T_1115; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1120 = _T_1114 | gw_int_pending_12; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_13 = gw_config_reg_13[1] ? _T_1120 : _T_1114; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1126 = extintsrc_req_sync[14] ^ gw_config_reg_14[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1127 = ~gw_clear_reg_we_14; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_13; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1128 = gw_int_pending_13 & _T_1127; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1132 = _T_1126 | gw_int_pending_13; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_14 = gw_config_reg_14[1] ? _T_1132 : _T_1126; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1138 = extintsrc_req_sync[15] ^ gw_config_reg_15[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1139 = ~gw_clear_reg_we_15; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_14; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1140 = gw_int_pending_14 & _T_1139; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1144 = _T_1138 | gw_int_pending_14; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_15 = gw_config_reg_15[1] ? _T_1144 : _T_1138; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1150 = extintsrc_req_sync[16] ^ gw_config_reg_16[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1151 = ~gw_clear_reg_we_16; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_15; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1152 = gw_int_pending_15 & _T_1151; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1156 = _T_1150 | gw_int_pending_15; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_16 = gw_config_reg_16[1] ? _T_1156 : _T_1150; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1162 = extintsrc_req_sync[17] ^ gw_config_reg_17[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1163 = ~gw_clear_reg_we_17; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_16; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1164 = gw_int_pending_16 & _T_1163; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1168 = _T_1162 | gw_int_pending_16; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_17 = gw_config_reg_17[1] ? _T_1168 : _T_1162; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1174 = extintsrc_req_sync[18] ^ gw_config_reg_18[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1175 = ~gw_clear_reg_we_18; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_17; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1176 = gw_int_pending_17 & _T_1175; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1180 = _T_1174 | gw_int_pending_17; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_18 = gw_config_reg_18[1] ? _T_1180 : _T_1174; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1186 = extintsrc_req_sync[19] ^ gw_config_reg_19[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1187 = ~gw_clear_reg_we_19; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_18; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1188 = gw_int_pending_18 & _T_1187; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1192 = _T_1186 | gw_int_pending_18; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_19 = gw_config_reg_19[1] ? _T_1192 : _T_1186; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1198 = extintsrc_req_sync[20] ^ gw_config_reg_20[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1199 = ~gw_clear_reg_we_20; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_19; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1200 = gw_int_pending_19 & _T_1199; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1204 = _T_1198 | gw_int_pending_19; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_20 = gw_config_reg_20[1] ? _T_1204 : _T_1198; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1210 = extintsrc_req_sync[21] ^ gw_config_reg_21[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1211 = ~gw_clear_reg_we_21; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_20; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1212 = gw_int_pending_20 & _T_1211; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1216 = _T_1210 | gw_int_pending_20; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_21 = gw_config_reg_21[1] ? _T_1216 : _T_1210; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1222 = extintsrc_req_sync[22] ^ gw_config_reg_22[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1223 = ~gw_clear_reg_we_22; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_21; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1224 = gw_int_pending_21 & _T_1223; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1228 = _T_1222 | gw_int_pending_21; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_22 = gw_config_reg_22[1] ? _T_1228 : _T_1222; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1234 = extintsrc_req_sync[23] ^ gw_config_reg_23[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1235 = ~gw_clear_reg_we_23; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_22; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1236 = gw_int_pending_22 & _T_1235; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1240 = _T_1234 | gw_int_pending_22; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_23 = gw_config_reg_23[1] ? _T_1240 : _T_1234; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1246 = extintsrc_req_sync[24] ^ gw_config_reg_24[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1247 = ~gw_clear_reg_we_24; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_23; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1248 = gw_int_pending_23 & _T_1247; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1252 = _T_1246 | gw_int_pending_23; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_24 = gw_config_reg_24[1] ? _T_1252 : _T_1246; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1258 = extintsrc_req_sync[25] ^ gw_config_reg_25[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1259 = ~gw_clear_reg_we_25; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_24; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1260 = gw_int_pending_24 & _T_1259; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1264 = _T_1258 | gw_int_pending_24; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_25 = gw_config_reg_25[1] ? _T_1264 : _T_1258; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1270 = extintsrc_req_sync[26] ^ gw_config_reg_26[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1271 = ~gw_clear_reg_we_26; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_25; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1272 = gw_int_pending_25 & _T_1271; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1276 = _T_1270 | gw_int_pending_25; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_26 = gw_config_reg_26[1] ? _T_1276 : _T_1270; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1282 = extintsrc_req_sync[27] ^ gw_config_reg_27[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1283 = ~gw_clear_reg_we_27; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_26; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1284 = gw_int_pending_26 & _T_1283; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1288 = _T_1282 | gw_int_pending_26; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_27 = gw_config_reg_27[1] ? _T_1288 : _T_1282; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1294 = extintsrc_req_sync[28] ^ gw_config_reg_28[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1295 = ~gw_clear_reg_we_28; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_27; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1296 = gw_int_pending_27 & _T_1295; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1300 = _T_1294 | gw_int_pending_27; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_28 = gw_config_reg_28[1] ? _T_1300 : _T_1294; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1306 = extintsrc_req_sync[29] ^ gw_config_reg_29[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1307 = ~gw_clear_reg_we_29; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_28; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1308 = gw_int_pending_28 & _T_1307; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1312 = _T_1306 | gw_int_pending_28; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_29 = gw_config_reg_29[1] ? _T_1312 : _T_1306; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1318 = extintsrc_req_sync[30] ^ gw_config_reg_30[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1319 = ~gw_clear_reg_we_30; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_29; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1320 = gw_int_pending_29 & _T_1319; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1324 = _T_1318 | gw_int_pending_29; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_30 = gw_config_reg_30[1] ? _T_1324 : _T_1318; // @[el2_pic_ctl.scala 39:8]
|
|
wire _T_1330 = extintsrc_req_sync[31] ^ gw_config_reg_31[0]; // @[el2_pic_ctl.scala 37:50]
|
|
wire _T_1331 = ~gw_clear_reg_we_31; // @[el2_pic_ctl.scala 37:92]
|
|
reg gw_int_pending_30; // @[el2_pic_ctl.scala 38:30]
|
|
wire _T_1332 = gw_int_pending_30 & _T_1331; // @[el2_pic_ctl.scala 37:90]
|
|
wire _T_1336 = _T_1330 | gw_int_pending_30; // @[el2_pic_ctl.scala 39:78]
|
|
wire extintsrc_req_gw_31 = gw_config_reg_31[1] ? _T_1336 : _T_1330; // @[el2_pic_ctl.scala 39:8]
|
|
reg config_reg; // @[Reg.scala 27:20]
|
|
wire [3:0] intpriority_reg_0 = 4'h0; // @[el2_pic_ctl.scala 154:32 el2_pic_ctl.scala 155:208]
|
|
wire [3:0] _T_1342 = ~intpriority_reg_1; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_1 = config_reg ? _T_1342 : intpriority_reg_1; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1345 = ~intpriority_reg_2; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_2 = config_reg ? _T_1345 : intpriority_reg_2; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1348 = ~intpriority_reg_3; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_3 = config_reg ? _T_1348 : intpriority_reg_3; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1351 = ~intpriority_reg_4; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_4 = config_reg ? _T_1351 : intpriority_reg_4; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1354 = ~intpriority_reg_5; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_5 = config_reg ? _T_1354 : intpriority_reg_5; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1357 = ~intpriority_reg_6; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_6 = config_reg ? _T_1357 : intpriority_reg_6; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1360 = ~intpriority_reg_7; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_7 = config_reg ? _T_1360 : intpriority_reg_7; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1363 = ~intpriority_reg_8; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_8 = config_reg ? _T_1363 : intpriority_reg_8; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1366 = ~intpriority_reg_9; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_9 = config_reg ? _T_1366 : intpriority_reg_9; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1369 = ~intpriority_reg_10; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_10 = config_reg ? _T_1369 : intpriority_reg_10; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1372 = ~intpriority_reg_11; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_11 = config_reg ? _T_1372 : intpriority_reg_11; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1375 = ~intpriority_reg_12; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_12 = config_reg ? _T_1375 : intpriority_reg_12; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1378 = ~intpriority_reg_13; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_13 = config_reg ? _T_1378 : intpriority_reg_13; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1381 = ~intpriority_reg_14; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_14 = config_reg ? _T_1381 : intpriority_reg_14; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1384 = ~intpriority_reg_15; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_15 = config_reg ? _T_1384 : intpriority_reg_15; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1387 = ~intpriority_reg_16; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_16 = config_reg ? _T_1387 : intpriority_reg_16; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1390 = ~intpriority_reg_17; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_17 = config_reg ? _T_1390 : intpriority_reg_17; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1393 = ~intpriority_reg_18; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_18 = config_reg ? _T_1393 : intpriority_reg_18; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1396 = ~intpriority_reg_19; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_19 = config_reg ? _T_1396 : intpriority_reg_19; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1399 = ~intpriority_reg_20; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_20 = config_reg ? _T_1399 : intpriority_reg_20; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1402 = ~intpriority_reg_21; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_21 = config_reg ? _T_1402 : intpriority_reg_21; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1405 = ~intpriority_reg_22; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_22 = config_reg ? _T_1405 : intpriority_reg_22; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1408 = ~intpriority_reg_23; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_23 = config_reg ? _T_1408 : intpriority_reg_23; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1411 = ~intpriority_reg_24; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_24 = config_reg ? _T_1411 : intpriority_reg_24; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1414 = ~intpriority_reg_25; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_25 = config_reg ? _T_1414 : intpriority_reg_25; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1417 = ~intpriority_reg_26; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_26 = config_reg ? _T_1417 : intpriority_reg_26; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1420 = ~intpriority_reg_27; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_27 = config_reg ? _T_1420 : intpriority_reg_27; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1423 = ~intpriority_reg_28; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_28 = config_reg ? _T_1423 : intpriority_reg_28; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1426 = ~intpriority_reg_29; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_29 = config_reg ? _T_1426 : intpriority_reg_29; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1429 = ~intpriority_reg_30; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_30 = config_reg ? _T_1429 : intpriority_reg_30; // @[el2_pic_ctl.scala 166:70]
|
|
wire [3:0] _T_1432 = ~intpriority_reg_31; // @[el2_pic_ctl.scala 166:89]
|
|
wire [3:0] intpriority_reg_inv_31 = config_reg ? _T_1432 : intpriority_reg_31; // @[el2_pic_ctl.scala 166:70]
|
|
wire _T_1438 = extintsrc_req_gw_1 & intenable_reg_1; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1440 = _T_1438 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_1 = _T_1440 & intpriority_reg_inv_1; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1442 = extintsrc_req_gw_2 & intenable_reg_2; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1444 = _T_1442 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_2 = _T_1444 & intpriority_reg_inv_2; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1446 = extintsrc_req_gw_3 & intenable_reg_3; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1448 = _T_1446 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_3 = _T_1448 & intpriority_reg_inv_3; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1450 = extintsrc_req_gw_4 & intenable_reg_4; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1452 = _T_1450 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_4 = _T_1452 & intpriority_reg_inv_4; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1454 = extintsrc_req_gw_5 & intenable_reg_5; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1456 = _T_1454 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_5 = _T_1456 & intpriority_reg_inv_5; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1458 = extintsrc_req_gw_6 & intenable_reg_6; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1460 = _T_1458 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_6 = _T_1460 & intpriority_reg_inv_6; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1462 = extintsrc_req_gw_7 & intenable_reg_7; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1464 = _T_1462 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_7 = _T_1464 & intpriority_reg_inv_7; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1466 = extintsrc_req_gw_8 & intenable_reg_8; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1468 = _T_1466 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_8 = _T_1468 & intpriority_reg_inv_8; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1470 = extintsrc_req_gw_9 & intenable_reg_9; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1472 = _T_1470 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_9 = _T_1472 & intpriority_reg_inv_9; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1474 = extintsrc_req_gw_10 & intenable_reg_10; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1476 = _T_1474 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_10 = _T_1476 & intpriority_reg_inv_10; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1478 = extintsrc_req_gw_11 & intenable_reg_11; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1480 = _T_1478 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_11 = _T_1480 & intpriority_reg_inv_11; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1482 = extintsrc_req_gw_12 & intenable_reg_12; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1484 = _T_1482 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_12 = _T_1484 & intpriority_reg_inv_12; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1486 = extintsrc_req_gw_13 & intenable_reg_13; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1488 = _T_1486 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_13 = _T_1488 & intpriority_reg_inv_13; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1490 = extintsrc_req_gw_14 & intenable_reg_14; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1492 = _T_1490 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_14 = _T_1492 & intpriority_reg_inv_14; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1494 = extintsrc_req_gw_15 & intenable_reg_15; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1496 = _T_1494 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_15 = _T_1496 & intpriority_reg_inv_15; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1498 = extintsrc_req_gw_16 & intenable_reg_16; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1500 = _T_1498 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_16 = _T_1500 & intpriority_reg_inv_16; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1502 = extintsrc_req_gw_17 & intenable_reg_17; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1504 = _T_1502 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_17 = _T_1504 & intpriority_reg_inv_17; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1506 = extintsrc_req_gw_18 & intenable_reg_18; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1508 = _T_1506 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_18 = _T_1508 & intpriority_reg_inv_18; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1510 = extintsrc_req_gw_19 & intenable_reg_19; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1512 = _T_1510 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_19 = _T_1512 & intpriority_reg_inv_19; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1514 = extintsrc_req_gw_20 & intenable_reg_20; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1516 = _T_1514 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_20 = _T_1516 & intpriority_reg_inv_20; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1518 = extintsrc_req_gw_21 & intenable_reg_21; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1520 = _T_1518 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_21 = _T_1520 & intpriority_reg_inv_21; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1522 = extintsrc_req_gw_22 & intenable_reg_22; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1524 = _T_1522 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_22 = _T_1524 & intpriority_reg_inv_22; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1526 = extintsrc_req_gw_23 & intenable_reg_23; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1528 = _T_1526 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_23 = _T_1528 & intpriority_reg_inv_23; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1530 = extintsrc_req_gw_24 & intenable_reg_24; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1532 = _T_1530 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_24 = _T_1532 & intpriority_reg_inv_24; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1534 = extintsrc_req_gw_25 & intenable_reg_25; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1536 = _T_1534 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_25 = _T_1536 & intpriority_reg_inv_25; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1538 = extintsrc_req_gw_26 & intenable_reg_26; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1540 = _T_1538 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_26 = _T_1540 & intpriority_reg_inv_26; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1542 = extintsrc_req_gw_27 & intenable_reg_27; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1544 = _T_1542 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_27 = _T_1544 & intpriority_reg_inv_27; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1546 = extintsrc_req_gw_28 & intenable_reg_28; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1548 = _T_1546 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_28 = _T_1548 & intpriority_reg_inv_28; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1550 = extintsrc_req_gw_29 & intenable_reg_29; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1552 = _T_1550 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_29 = _T_1552 & intpriority_reg_inv_29; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1554 = extintsrc_req_gw_30 & intenable_reg_30; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1556 = _T_1554 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_30 = _T_1556 & intpriority_reg_inv_30; // @[el2_pic_ctl.scala 167:129]
|
|
wire _T_1558 = extintsrc_req_gw_31 & intenable_reg_31; // @[el2_pic_ctl.scala 167:109]
|
|
wire [3:0] _T_1560 = _T_1558 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_31 = _T_1560 & intpriority_reg_inv_31; // @[el2_pic_ctl.scala 167:129]
|
|
wire [7:0] _T_1564 = 8'hff; // @[Bitwise.scala 72:12]
|
|
wire [3:0] level_intpend_w_prior_en_0_0 = 4'h0; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1441 = intpend_w_prior_en_1; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_1 = intpend_w_prior_en_1; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1566 = intpriority_reg_0 < _T_1441; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_1 = 8'h1; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_1 = 8'h1; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_0 = 8'h0; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_0 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id = _T_1566 ? intpend_id_1 : intpend_id_0; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority = _T_1566 ? _T_1441 : intpriority_reg_0; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1445 = intpend_w_prior_en_2; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_2 = intpend_w_prior_en_2; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1449 = intpend_w_prior_en_3; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_3 = intpend_w_prior_en_3; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1568 = _T_1445 < _T_1449; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_3 = 8'h3; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_3 = 8'h3; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_2 = 8'h2; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_2 = 8'h2; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_1 = _T_1568 ? intpend_id_3 : intpend_id_2; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_1 = _T_1568 ? _T_1449 : _T_1445; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1453 = intpend_w_prior_en_4; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_4 = intpend_w_prior_en_4; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1457 = intpend_w_prior_en_5; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_5 = intpend_w_prior_en_5; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1570 = _T_1453 < _T_1457; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_5 = 8'h5; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_5 = 8'h5; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_4 = 8'h4; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_4 = 8'h4; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_2 = _T_1570 ? intpend_id_5 : intpend_id_4; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_2 = _T_1570 ? _T_1457 : _T_1453; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1461 = intpend_w_prior_en_6; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_6 = intpend_w_prior_en_6; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1465 = intpend_w_prior_en_7; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_7 = intpend_w_prior_en_7; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1572 = _T_1461 < _T_1465; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_7 = 8'h7; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_7 = 8'h7; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_6 = 8'h6; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_6 = 8'h6; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_3 = _T_1572 ? intpend_id_7 : intpend_id_6; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_3 = _T_1572 ? _T_1465 : _T_1461; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1469 = intpend_w_prior_en_8; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_8 = intpend_w_prior_en_8; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1473 = intpend_w_prior_en_9; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_9 = intpend_w_prior_en_9; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1574 = _T_1469 < _T_1473; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_9 = 8'h9; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_9 = 8'h9; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_8 = 8'h8; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_8 = 8'h8; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_4 = _T_1574 ? intpend_id_9 : intpend_id_8; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_4 = _T_1574 ? _T_1473 : _T_1469; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1477 = intpend_w_prior_en_10; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_10 = intpend_w_prior_en_10; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1481 = intpend_w_prior_en_11; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_11 = intpend_w_prior_en_11; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1576 = _T_1477 < _T_1481; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_11 = 8'hb; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_11 = 8'hb; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_10 = 8'ha; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_10 = 8'ha; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_5 = _T_1576 ? intpend_id_11 : intpend_id_10; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_5 = _T_1576 ? _T_1481 : _T_1477; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1485 = intpend_w_prior_en_12; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_12 = intpend_w_prior_en_12; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1489 = intpend_w_prior_en_13; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_13 = intpend_w_prior_en_13; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1578 = _T_1485 < _T_1489; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_13 = 8'hd; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_13 = 8'hd; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_12 = 8'hc; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_12 = 8'hc; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_6 = _T_1578 ? intpend_id_13 : intpend_id_12; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_6 = _T_1578 ? _T_1489 : _T_1485; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1493 = intpend_w_prior_en_14; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_14 = intpend_w_prior_en_14; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1497 = intpend_w_prior_en_15; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_15 = intpend_w_prior_en_15; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1580 = _T_1493 < _T_1497; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_15 = 8'hf; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_15 = 8'hf; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_14 = 8'he; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_14 = 8'he; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_7 = _T_1580 ? intpend_id_15 : intpend_id_14; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_7 = _T_1580 ? _T_1497 : _T_1493; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1501 = intpend_w_prior_en_16; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_16 = intpend_w_prior_en_16; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1505 = intpend_w_prior_en_17; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_17 = intpend_w_prior_en_17; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1582 = _T_1501 < _T_1505; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_17 = 8'h11; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_17 = 8'h11; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_16 = 8'h10; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_16 = 8'h10; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_8 = _T_1582 ? intpend_id_17 : intpend_id_16; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_8 = _T_1582 ? _T_1505 : _T_1501; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1509 = intpend_w_prior_en_18; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_18 = intpend_w_prior_en_18; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1513 = intpend_w_prior_en_19; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_19 = intpend_w_prior_en_19; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1584 = _T_1509 < _T_1513; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_19 = 8'h13; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_19 = 8'h13; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_18 = 8'h12; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_18 = 8'h12; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_9 = _T_1584 ? intpend_id_19 : intpend_id_18; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_9 = _T_1584 ? _T_1513 : _T_1509; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1517 = intpend_w_prior_en_20; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_20 = intpend_w_prior_en_20; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1521 = intpend_w_prior_en_21; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_21 = intpend_w_prior_en_21; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1586 = _T_1517 < _T_1521; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_21 = 8'h15; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_21 = 8'h15; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_20 = 8'h14; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_20 = 8'h14; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_10 = _T_1586 ? intpend_id_21 : intpend_id_20; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_10 = _T_1586 ? _T_1521 : _T_1517; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1525 = intpend_w_prior_en_22; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_22 = intpend_w_prior_en_22; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1529 = intpend_w_prior_en_23; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_23 = intpend_w_prior_en_23; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1588 = _T_1525 < _T_1529; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_23 = 8'h17; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_23 = 8'h17; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_22 = 8'h16; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_22 = 8'h16; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_11 = _T_1588 ? intpend_id_23 : intpend_id_22; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_11 = _T_1588 ? _T_1529 : _T_1525; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1533 = intpend_w_prior_en_24; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_24 = intpend_w_prior_en_24; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1537 = intpend_w_prior_en_25; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_25 = intpend_w_prior_en_25; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1590 = _T_1533 < _T_1537; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_25 = 8'h19; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_25 = 8'h19; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_24 = 8'h18; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_24 = 8'h18; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_12 = _T_1590 ? intpend_id_25 : intpend_id_24; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_12 = _T_1590 ? _T_1537 : _T_1533; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1541 = intpend_w_prior_en_26; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_26 = intpend_w_prior_en_26; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1545 = intpend_w_prior_en_27; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_27 = intpend_w_prior_en_27; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1592 = _T_1541 < _T_1545; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_27 = 8'h1b; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_27 = 8'h1b; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_26 = 8'h1a; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_26 = 8'h1a; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_13 = _T_1592 ? intpend_id_27 : intpend_id_26; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_13 = _T_1592 ? _T_1545 : _T_1541; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1549 = intpend_w_prior_en_28; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_28 = intpend_w_prior_en_28; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1553 = intpend_w_prior_en_29; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_29 = intpend_w_prior_en_29; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1594 = _T_1549 < _T_1553; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_29 = 8'h1d; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_29 = 8'h1d; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_28 = 8'h1c; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_28 = 8'h1c; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_14 = _T_1594 ? intpend_id_29 : intpend_id_28; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_14 = _T_1594 ? _T_1553 : _T_1549; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] _T_1557 = intpend_w_prior_en_30; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_30 = intpend_w_prior_en_30; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] _T_1561 = intpend_w_prior_en_31; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_31 = intpend_w_prior_en_31; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1596 = _T_1557 < _T_1561; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] intpend_id_31 = 8'h1f; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_31 = 8'h1f; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] intpend_id_30 = 8'h1e; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55]
|
|
wire [7:0] level_intpend_id_0_30 = 8'h1e; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_15 = _T_1596 ? intpend_id_31 : intpend_id_30; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_15 = _T_1596 ? _T_1561 : _T_1557; // @[el2_pic_ctl.scala 33:49]
|
|
wire [3:0] level_intpend_w_prior_en_0_32 = 4'h0; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire [3:0] level_intpend_w_prior_en_0_33 = 4'h0; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33]
|
|
wire _T_1598 = intpriority_reg_0 < intpriority_reg_0; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_0_33 = 8'hff; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] level_intpend_id_0_32 = 8'hff; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33]
|
|
wire [7:0] out_id_16 = _T_1598 ? _T_1564 : _T_1564; // @[el2_pic_ctl.scala 33:9]
|
|
wire _T_1600 = out_priority < out_priority_1; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_1_1 = out_id_1; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_1_0 = out_id; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_17 = _T_1600 ? level_intpend_id_1_1 : level_intpend_id_1_0; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_17 = _T_1600 ? out_priority_1 : out_priority; // @[el2_pic_ctl.scala 33:49]
|
|
wire _T_1602 = out_priority_2 < out_priority_3; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_1_3 = out_id_3; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_1_2 = out_id_2; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_18 = _T_1602 ? level_intpend_id_1_3 : level_intpend_id_1_2; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_18 = _T_1602 ? out_priority_3 : out_priority_2; // @[el2_pic_ctl.scala 33:49]
|
|
wire _T_1604 = out_priority_4 < out_priority_5; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_1_5 = out_id_5; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_1_4 = out_id_4; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_19 = _T_1604 ? level_intpend_id_1_5 : level_intpend_id_1_4; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_19 = _T_1604 ? out_priority_5 : out_priority_4; // @[el2_pic_ctl.scala 33:49]
|
|
wire _T_1606 = out_priority_6 < out_priority_7; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_1_7 = out_id_7; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_1_6 = out_id_6; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_20 = _T_1606 ? level_intpend_id_1_7 : level_intpend_id_1_6; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_20 = _T_1606 ? out_priority_7 : out_priority_6; // @[el2_pic_ctl.scala 33:49]
|
|
wire _T_1608 = out_priority_8 < out_priority_9; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_1_9 = out_id_9; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_1_8 = out_id_8; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_21 = _T_1608 ? level_intpend_id_1_9 : level_intpend_id_1_8; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_21 = _T_1608 ? out_priority_9 : out_priority_8; // @[el2_pic_ctl.scala 33:49]
|
|
wire _T_1610 = out_priority_10 < out_priority_11; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_1_11 = out_id_11; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_1_10 = out_id_10; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_22 = _T_1610 ? level_intpend_id_1_11 : level_intpend_id_1_10; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_22 = _T_1610 ? out_priority_11 : out_priority_10; // @[el2_pic_ctl.scala 33:49]
|
|
wire _T_1612 = out_priority_12 < out_priority_13; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_1_13 = out_id_13; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_1_12 = out_id_12; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_23 = _T_1612 ? level_intpend_id_1_13 : level_intpend_id_1_12; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_23 = _T_1612 ? out_priority_13 : out_priority_12; // @[el2_pic_ctl.scala 33:49]
|
|
wire _T_1614 = out_priority_14 < out_priority_15; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_1_15 = out_id_15; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_1_14 = out_id_14; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_24 = _T_1614 ? level_intpend_id_1_15 : level_intpend_id_1_14; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_24 = _T_1614 ? out_priority_15 : out_priority_14; // @[el2_pic_ctl.scala 33:49]
|
|
wire [7:0] level_intpend_id_1_17 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 235:46]
|
|
wire [7:0] level_intpend_id_1_16 = out_id_16; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_25 = level_intpend_id_1_16; // @[el2_pic_ctl.scala 33:9]
|
|
wire _T_1618 = out_priority_17 < out_priority_18; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_2_1 = out_id_18; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_2_0 = out_id_17; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_26 = _T_1618 ? level_intpend_id_2_1 : level_intpend_id_2_0; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_26 = _T_1618 ? out_priority_18 : out_priority_17; // @[el2_pic_ctl.scala 33:49]
|
|
wire _T_1620 = out_priority_19 < out_priority_20; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_2_3 = out_id_20; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_2_2 = out_id_19; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_27 = _T_1620 ? level_intpend_id_2_3 : level_intpend_id_2_2; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_27 = _T_1620 ? out_priority_20 : out_priority_19; // @[el2_pic_ctl.scala 33:49]
|
|
wire _T_1622 = out_priority_21 < out_priority_22; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_2_5 = out_id_22; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_2_4 = out_id_21; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_28 = _T_1622 ? level_intpend_id_2_5 : level_intpend_id_2_4; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_28 = _T_1622 ? out_priority_22 : out_priority_21; // @[el2_pic_ctl.scala 33:49]
|
|
wire _T_1624 = out_priority_23 < out_priority_24; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_2_7 = out_id_24; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_2_6 = out_id_23; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_29 = _T_1624 ? level_intpend_id_2_7 : level_intpend_id_2_6; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_29 = _T_1624 ? out_priority_24 : out_priority_23; // @[el2_pic_ctl.scala 33:49]
|
|
wire [7:0] level_intpend_id_2_9 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 235:46]
|
|
wire [7:0] level_intpend_id_2_8 = level_intpend_id_1_16; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_30 = out_id_25; // @[el2_pic_ctl.scala 33:9]
|
|
wire _T_1628 = out_priority_26 < out_priority_27; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_3_1 = out_id_27; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_3_0 = out_id_26; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_31 = _T_1628 ? level_intpend_id_3_1 : level_intpend_id_3_0; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_31 = _T_1628 ? out_priority_27 : out_priority_26; // @[el2_pic_ctl.scala 33:49]
|
|
wire _T_1630 = out_priority_28 < out_priority_29; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_3_3 = out_id_29; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_3_2 = out_id_28; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_32 = _T_1630 ? level_intpend_id_3_3 : level_intpend_id_3_2; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_32 = _T_1630 ? out_priority_29 : out_priority_28; // @[el2_pic_ctl.scala 33:49]
|
|
wire [7:0] level_intpend_id_3_5 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 235:46]
|
|
wire [7:0] level_intpend_id_3_4 = out_id_25; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_33 = out_id_30; // @[el2_pic_ctl.scala 33:9]
|
|
wire _T_1634 = out_priority_31 < out_priority_32; // @[el2_pic_ctl.scala 33:20]
|
|
wire [7:0] level_intpend_id_4_1 = out_id_32; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_4_0 = out_id_31; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] out_id_34 = _T_1634 ? level_intpend_id_4_1 : level_intpend_id_4_0; // @[el2_pic_ctl.scala 33:9]
|
|
wire [3:0] out_priority_34 = _T_1634 ? out_priority_32 : out_priority_31; // @[el2_pic_ctl.scala 33:49]
|
|
wire [7:0] level_intpend_id_4_3 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 235:46]
|
|
wire [7:0] level_intpend_id_4_2 = out_id_30; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire config_reg_we = waddr_config_pic_match & picm_wren_ff; // @[el2_pic_ctl.scala 255:47]
|
|
wire config_reg_re = raddr_config_pic_match & picm_rden_ff; // @[el2_pic_ctl.scala 256:47]
|
|
wire [3:0] level_intpend_w_prior_en_5_0 = out_priority_34; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 239:43]
|
|
wire [3:0] selected_int_priority = out_priority_34; // @[el2_pic_ctl.scala 243:29]
|
|
wire [3:0] _T_1641 = ~level_intpend_w_prior_en_5_0; // @[el2_pic_ctl.scala 267:38]
|
|
wire [3:0] pl_in_q = config_reg ? _T_1641 : level_intpend_w_prior_en_5_0; // @[el2_pic_ctl.scala 267:20]
|
|
reg [7:0] _T_1642; // @[el2_pic_ctl.scala 268:47]
|
|
reg [3:0] _T_1643; // @[el2_pic_ctl.scala 269:42]
|
|
wire [3:0] _T_1645 = ~io_meipt; // @[el2_pic_ctl.scala 270:40]
|
|
wire [3:0] meipt_inv = config_reg ? _T_1645 : io_meipt; // @[el2_pic_ctl.scala 270:22]
|
|
wire [3:0] _T_1647 = ~io_meicurpl; // @[el2_pic_ctl.scala 271:43]
|
|
wire [3:0] meicurpl_inv = config_reg ? _T_1647 : io_meicurpl; // @[el2_pic_ctl.scala 271:25]
|
|
wire _T_1648 = level_intpend_w_prior_en_5_0 > meipt_inv; // @[el2_pic_ctl.scala 272:47]
|
|
wire _T_1649 = level_intpend_w_prior_en_5_0 > meicurpl_inv; // @[el2_pic_ctl.scala 272:86]
|
|
reg _T_1650; // @[el2_pic_ctl.scala 273:50]
|
|
wire [3:0] maxint = config_reg ? 4'h0 : 4'hf; // @[el2_pic_ctl.scala 274:19]
|
|
reg _T_1652; // @[el2_pic_ctl.scala 276:48]
|
|
wire intpend_reg_read = addr_intpend_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 282:60]
|
|
wire [9:0] _T_1662 = {extintsrc_req_gw_31,extintsrc_req_gw_30,extintsrc_req_gw_29,extintsrc_req_gw_28,extintsrc_req_gw_27,extintsrc_req_gw_26,extintsrc_req_gw_25,extintsrc_req_gw_24,extintsrc_req_gw_23,extintsrc_req_gw_22}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_1671 = {_T_1662,extintsrc_req_gw_21,extintsrc_req_gw_20,extintsrc_req_gw_19,extintsrc_req_gw_18,extintsrc_req_gw_17,extintsrc_req_gw_16,extintsrc_req_gw_15,extintsrc_req_gw_14,extintsrc_req_gw_13}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_1680 = {_T_1671,extintsrc_req_gw_12,extintsrc_req_gw_11,extintsrc_req_gw_10,extintsrc_req_gw_9,extintsrc_req_gw_8,extintsrc_req_gw_7,extintsrc_req_gw_6,extintsrc_req_gw_5,extintsrc_req_gw_4}; // @[Cat.scala 29:58]
|
|
wire [63:0] intpend_reg_extended = {32'h0,_T_1680,extintsrc_req_gw_3,extintsrc_req_gw_2,extintsrc_req_gw_1,1'h0}; // @[Cat.scala 29:58]
|
|
wire [3:0] _GEN_220 = {{3'd0}, intpend_reg_read}; // @[el2_pic_ctl.scala 290:83]
|
|
wire [3:0] _T_1687 = _GEN_220 & picm_raddr_ff[5:2]; // @[el2_pic_ctl.scala 290:83]
|
|
wire _T_1688 = _T_1687 == 4'h0; // @[el2_pic_ctl.scala 290:105]
|
|
wire [31:0] _T_1690 = _T_1688 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] intpend_rd_part_out_0 = _T_1690 & intpend_reg_extended[31:0]; // @[el2_pic_ctl.scala 290:119]
|
|
wire _T_1695 = _T_1687 == 4'h1; // @[el2_pic_ctl.scala 290:105]
|
|
wire [31:0] _T_1697 = _T_1695 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] intpend_rd_part_out_1 = _T_1697 & intpend_reg_extended[63:32]; // @[el2_pic_ctl.scala 290:119]
|
|
wire [31:0] intpend_rd_out = intpend_rd_part_out_0 | intpend_rd_part_out_1; // @[el2_pic_ctl.scala 291:89]
|
|
wire intenable_rd_out = intenable_reg_re_31 & intenable_reg_31; // @[el2_pic_ctl.scala 292:76]
|
|
wire [3:0] _T_1763 = intpriority_reg_re_31 ? intpriority_reg_31 : 4'h0; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1764 = intpriority_reg_re_30 ? intpriority_reg_30 : _T_1763; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1765 = intpriority_reg_re_29 ? intpriority_reg_29 : _T_1764; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1766 = intpriority_reg_re_28 ? intpriority_reg_28 : _T_1765; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1767 = intpriority_reg_re_27 ? intpriority_reg_27 : _T_1766; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1768 = intpriority_reg_re_26 ? intpriority_reg_26 : _T_1767; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1769 = intpriority_reg_re_25 ? intpriority_reg_25 : _T_1768; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1770 = intpriority_reg_re_24 ? intpriority_reg_24 : _T_1769; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1771 = intpriority_reg_re_23 ? intpriority_reg_23 : _T_1770; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1772 = intpriority_reg_re_22 ? intpriority_reg_22 : _T_1771; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1773 = intpriority_reg_re_21 ? intpriority_reg_21 : _T_1772; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1774 = intpriority_reg_re_20 ? intpriority_reg_20 : _T_1773; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1775 = intpriority_reg_re_19 ? intpriority_reg_19 : _T_1774; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1776 = intpriority_reg_re_18 ? intpriority_reg_18 : _T_1775; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1777 = intpriority_reg_re_17 ? intpriority_reg_17 : _T_1776; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1778 = intpriority_reg_re_16 ? intpriority_reg_16 : _T_1777; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1779 = intpriority_reg_re_15 ? intpriority_reg_15 : _T_1778; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1780 = intpriority_reg_re_14 ? intpriority_reg_14 : _T_1779; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1781 = intpriority_reg_re_13 ? intpriority_reg_13 : _T_1780; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1782 = intpriority_reg_re_12 ? intpriority_reg_12 : _T_1781; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1783 = intpriority_reg_re_11 ? intpriority_reg_11 : _T_1782; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1784 = intpriority_reg_re_10 ? intpriority_reg_10 : _T_1783; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1785 = intpriority_reg_re_9 ? intpriority_reg_9 : _T_1784; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1786 = intpriority_reg_re_8 ? intpriority_reg_8 : _T_1785; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1787 = intpriority_reg_re_7 ? intpriority_reg_7 : _T_1786; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1788 = intpriority_reg_re_6 ? intpriority_reg_6 : _T_1787; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1789 = intpriority_reg_re_5 ? intpriority_reg_5 : _T_1788; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1790 = intpriority_reg_re_4 ? intpriority_reg_4 : _T_1789; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1791 = intpriority_reg_re_3 ? intpriority_reg_3 : _T_1790; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_1792 = intpriority_reg_re_2 ? intpriority_reg_2 : _T_1791; // @[Mux.scala 98:16]
|
|
wire [3:0] intpriority_rd_out = intpriority_reg_re_1 ? intpriority_reg_1 : _T_1792; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1825 = gw_config_reg_re_31 ? gw_config_reg_31 : 2'h0; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1826 = gw_config_reg_re_30 ? gw_config_reg_30 : _T_1825; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1827 = gw_config_reg_re_29 ? gw_config_reg_29 : _T_1826; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1828 = gw_config_reg_re_28 ? gw_config_reg_28 : _T_1827; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1829 = gw_config_reg_re_27 ? gw_config_reg_27 : _T_1828; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1830 = gw_config_reg_re_26 ? gw_config_reg_26 : _T_1829; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1831 = gw_config_reg_re_25 ? gw_config_reg_25 : _T_1830; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1832 = gw_config_reg_re_24 ? gw_config_reg_24 : _T_1831; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1833 = gw_config_reg_re_23 ? gw_config_reg_23 : _T_1832; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1834 = gw_config_reg_re_22 ? gw_config_reg_22 : _T_1833; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1835 = gw_config_reg_re_21 ? gw_config_reg_21 : _T_1834; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1836 = gw_config_reg_re_20 ? gw_config_reg_20 : _T_1835; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1837 = gw_config_reg_re_19 ? gw_config_reg_19 : _T_1836; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1838 = gw_config_reg_re_18 ? gw_config_reg_18 : _T_1837; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1839 = gw_config_reg_re_17 ? gw_config_reg_17 : _T_1838; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1840 = gw_config_reg_re_16 ? gw_config_reg_16 : _T_1839; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1841 = gw_config_reg_re_15 ? gw_config_reg_15 : _T_1840; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1842 = gw_config_reg_re_14 ? gw_config_reg_14 : _T_1841; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1843 = gw_config_reg_re_13 ? gw_config_reg_13 : _T_1842; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1844 = gw_config_reg_re_12 ? gw_config_reg_12 : _T_1843; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1845 = gw_config_reg_re_11 ? gw_config_reg_11 : _T_1844; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1846 = gw_config_reg_re_10 ? gw_config_reg_10 : _T_1845; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1847 = gw_config_reg_re_9 ? gw_config_reg_9 : _T_1846; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1848 = gw_config_reg_re_8 ? gw_config_reg_8 : _T_1847; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1849 = gw_config_reg_re_7 ? gw_config_reg_7 : _T_1848; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1850 = gw_config_reg_re_6 ? gw_config_reg_6 : _T_1849; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1851 = gw_config_reg_re_5 ? gw_config_reg_5 : _T_1850; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1852 = gw_config_reg_re_4 ? gw_config_reg_4 : _T_1851; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1853 = gw_config_reg_re_3 ? gw_config_reg_3 : _T_1852; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1854 = gw_config_reg_re_2 ? gw_config_reg_2 : _T_1853; // @[Mux.scala 98:16]
|
|
wire [1:0] gw_config_rd_out = gw_config_reg_re_1 ? gw_config_reg_1 : _T_1854; // @[Mux.scala 98:16]
|
|
wire [31:0] _T_1859 = {28'h0,intpriority_rd_out}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1862 = {31'h0,intenable_rd_out}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1865 = {30'h0,gw_config_rd_out}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1868 = {31'h0,config_reg}; // @[Cat.scala 29:58]
|
|
wire [14:0] address = picm_raddr_ff[14:0]; // @[el2_pic_ctl.scala 312:30]
|
|
wire _T_1908 = 15'h3000 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1909 = 15'h4004 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1910 = 15'h4008 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1911 = 15'h400c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1912 = 15'h4010 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1913 = 15'h4014 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1914 = 15'h4018 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1915 = 15'h401c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1916 = 15'h4020 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1917 = 15'h4024 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1918 = 15'h4028 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1919 = 15'h402c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1920 = 15'h4030 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1921 = 15'h4034 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1922 = 15'h4038 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1923 = 15'h403c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1924 = 15'h4040 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1925 = 15'h4044 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1926 = 15'h4048 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1927 = 15'h404c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1928 = 15'h4050 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1929 = 15'h4054 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1930 = 15'h4058 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1931 = 15'h405c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1932 = 15'h4060 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1933 = 15'h4064 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1934 = 15'h4068 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1935 = 15'h406c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1936 = 15'h4070 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1937 = 15'h4074 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1938 = 15'h4078 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1939 = 15'h407c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1940 = 15'h2004 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1941 = 15'h2008 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1942 = 15'h200c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1943 = 15'h2010 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1944 = 15'h2014 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1945 = 15'h2018 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1946 = 15'h201c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1947 = 15'h2020 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1948 = 15'h2024 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1949 = 15'h2028 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1950 = 15'h202c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1951 = 15'h2030 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1952 = 15'h2034 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1953 = 15'h2038 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1954 = 15'h203c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1955 = 15'h2040 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1956 = 15'h2044 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1957 = 15'h2048 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1958 = 15'h204c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1959 = 15'h2050 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1960 = 15'h2054 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1961 = 15'h2058 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1962 = 15'h205c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1963 = 15'h2060 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1964 = 15'h2064 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1965 = 15'h2068 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1966 = 15'h206c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1967 = 15'h2070 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1968 = 15'h2074 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1969 = 15'h2078 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1970 = 15'h207c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1971 = 15'h4 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1972 = 15'h8 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1973 = 15'hc == address; // @[Conditional.scala 37:30]
|
|
wire _T_1974 = 15'h10 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1975 = 15'h14 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1976 = 15'h18 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1977 = 15'h1c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1978 = 15'h20 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1979 = 15'h24 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1980 = 15'h28 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1981 = 15'h2c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1982 = 15'h30 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1983 = 15'h34 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1984 = 15'h38 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1985 = 15'h3c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1986 = 15'h40 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1987 = 15'h44 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1988 = 15'h48 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1989 = 15'h4c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1990 = 15'h50 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1991 = 15'h54 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1992 = 15'h58 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1993 = 15'h5c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1994 = 15'h60 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1995 = 15'h64 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1996 = 15'h68 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1997 = 15'h6c == address; // @[Conditional.scala 37:30]
|
|
wire _T_1998 = 15'h70 == address; // @[Conditional.scala 37:30]
|
|
wire _T_1999 = 15'h74 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2000 = 15'h78 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2001 = 15'h7c == address; // @[Conditional.scala 37:30]
|
|
wire [3:0] _GEN_126 = _T_2001 ? 4'h2 : 4'h1; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_127 = _T_2000 ? 4'h2 : _GEN_126; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_128 = _T_1999 ? 4'h2 : _GEN_127; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_129 = _T_1998 ? 4'h2 : _GEN_128; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_130 = _T_1997 ? 4'h2 : _GEN_129; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_131 = _T_1996 ? 4'h2 : _GEN_130; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_132 = _T_1995 ? 4'h2 : _GEN_131; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_133 = _T_1994 ? 4'h2 : _GEN_132; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_134 = _T_1993 ? 4'h2 : _GEN_133; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_135 = _T_1992 ? 4'h2 : _GEN_134; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_136 = _T_1991 ? 4'h2 : _GEN_135; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_137 = _T_1990 ? 4'h2 : _GEN_136; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_138 = _T_1989 ? 4'h2 : _GEN_137; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_139 = _T_1988 ? 4'h2 : _GEN_138; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_140 = _T_1987 ? 4'h2 : _GEN_139; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_141 = _T_1986 ? 4'h2 : _GEN_140; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_142 = _T_1985 ? 4'h2 : _GEN_141; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_143 = _T_1984 ? 4'h2 : _GEN_142; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_144 = _T_1983 ? 4'h2 : _GEN_143; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_145 = _T_1982 ? 4'h2 : _GEN_144; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_146 = _T_1981 ? 4'h2 : _GEN_145; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_147 = _T_1980 ? 4'h2 : _GEN_146; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_148 = _T_1979 ? 4'h2 : _GEN_147; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_149 = _T_1978 ? 4'h2 : _GEN_148; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_150 = _T_1977 ? 4'h2 : _GEN_149; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_151 = _T_1976 ? 4'h2 : _GEN_150; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_152 = _T_1975 ? 4'h2 : _GEN_151; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_153 = _T_1974 ? 4'h2 : _GEN_152; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_154 = _T_1973 ? 4'h2 : _GEN_153; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_155 = _T_1972 ? 4'h2 : _GEN_154; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_156 = _T_1971 ? 4'h2 : _GEN_155; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_157 = _T_1970 ? 4'h4 : _GEN_156; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_158 = _T_1969 ? 4'h4 : _GEN_157; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_159 = _T_1968 ? 4'h4 : _GEN_158; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_160 = _T_1967 ? 4'h4 : _GEN_159; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_161 = _T_1966 ? 4'h4 : _GEN_160; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_162 = _T_1965 ? 4'h4 : _GEN_161; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_163 = _T_1964 ? 4'h4 : _GEN_162; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_164 = _T_1963 ? 4'h4 : _GEN_163; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_165 = _T_1962 ? 4'h4 : _GEN_164; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_166 = _T_1961 ? 4'h4 : _GEN_165; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_167 = _T_1960 ? 4'h4 : _GEN_166; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_168 = _T_1959 ? 4'h4 : _GEN_167; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_169 = _T_1958 ? 4'h4 : _GEN_168; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_170 = _T_1957 ? 4'h4 : _GEN_169; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_171 = _T_1956 ? 4'h4 : _GEN_170; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_172 = _T_1955 ? 4'h4 : _GEN_171; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_173 = _T_1954 ? 4'h4 : _GEN_172; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_174 = _T_1953 ? 4'h4 : _GEN_173; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_175 = _T_1952 ? 4'h4 : _GEN_174; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_176 = _T_1951 ? 4'h4 : _GEN_175; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_177 = _T_1950 ? 4'h4 : _GEN_176; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_178 = _T_1949 ? 4'h4 : _GEN_177; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_179 = _T_1948 ? 4'h4 : _GEN_178; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_180 = _T_1947 ? 4'h4 : _GEN_179; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_181 = _T_1946 ? 4'h4 : _GEN_180; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_182 = _T_1945 ? 4'h4 : _GEN_181; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_183 = _T_1944 ? 4'h4 : _GEN_182; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_184 = _T_1943 ? 4'h4 : _GEN_183; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_185 = _T_1942 ? 4'h4 : _GEN_184; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_186 = _T_1941 ? 4'h4 : _GEN_185; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_187 = _T_1940 ? 4'h4 : _GEN_186; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_188 = _T_1939 ? 4'h8 : _GEN_187; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_189 = _T_1938 ? 4'h8 : _GEN_188; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_190 = _T_1937 ? 4'h8 : _GEN_189; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_191 = _T_1936 ? 4'h8 : _GEN_190; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_192 = _T_1935 ? 4'h8 : _GEN_191; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_193 = _T_1934 ? 4'h8 : _GEN_192; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_194 = _T_1933 ? 4'h8 : _GEN_193; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_195 = _T_1932 ? 4'h8 : _GEN_194; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_196 = _T_1931 ? 4'h8 : _GEN_195; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_197 = _T_1930 ? 4'h8 : _GEN_196; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_198 = _T_1929 ? 4'h8 : _GEN_197; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_199 = _T_1928 ? 4'h8 : _GEN_198; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_200 = _T_1927 ? 4'h8 : _GEN_199; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_201 = _T_1926 ? 4'h8 : _GEN_200; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_202 = _T_1925 ? 4'h8 : _GEN_201; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_203 = _T_1924 ? 4'h8 : _GEN_202; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_204 = _T_1923 ? 4'h8 : _GEN_203; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_205 = _T_1922 ? 4'h8 : _GEN_204; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_206 = _T_1921 ? 4'h8 : _GEN_205; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_207 = _T_1920 ? 4'h8 : _GEN_206; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_208 = _T_1919 ? 4'h8 : _GEN_207; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_209 = _T_1918 ? 4'h8 : _GEN_208; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_210 = _T_1917 ? 4'h8 : _GEN_209; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_211 = _T_1916 ? 4'h8 : _GEN_210; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_212 = _T_1915 ? 4'h8 : _GEN_211; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_213 = _T_1914 ? 4'h8 : _GEN_212; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_214 = _T_1913 ? 4'h8 : _GEN_213; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_215 = _T_1912 ? 4'h8 : _GEN_214; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_216 = _T_1911 ? 4'h8 : _GEN_215; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_217 = _T_1910 ? 4'h8 : _GEN_216; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_218 = _T_1909 ? 4'h8 : _GEN_217; // @[Conditional.scala 39:67]
|
|
wire [3:0] mask = _T_1908 ? 4'h4 : _GEN_218; // @[Conditional.scala 40:58]
|
|
wire _T_1870 = picm_mken_ff & mask[3]; // @[el2_pic_ctl.scala 305:19]
|
|
wire _T_1875 = picm_mken_ff & mask[2]; // @[el2_pic_ctl.scala 306:19]
|
|
wire _T_1880 = picm_mken_ff & mask[1]; // @[el2_pic_ctl.scala 307:19]
|
|
wire [31:0] _T_1888 = intpend_reg_read ? intpend_rd_out : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1889 = _T_21 ? _T_1859 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1890 = _T_24 ? _T_1862 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1891 = _T_27 ? _T_1865 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1892 = config_reg_re ? _T_1868 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1893 = _T_1870 ? 32'h3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1894 = _T_1875 ? 32'h1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1895 = _T_1880 ? 32'hf : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1897 = _T_1888 | _T_1889; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1898 = _T_1897 | _T_1890; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1899 = _T_1898 | _T_1891; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1900 = _T_1899 | _T_1892; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1901 = _T_1900 | _T_1893; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1902 = _T_1901 | _T_1894; // @[Mux.scala 27:72]
|
|
wire [31:0] picm_rd_data_in = _T_1902 | _T_1895; // @[Mux.scala 27:72]
|
|
wire [7:0] level_intpend_id_5_0 = out_id_34; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_1_18 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_19 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_20 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_21 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_22 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_23 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_24 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_25 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_26 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_27 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_28 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_29 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_30 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_31 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_32 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_1_33 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_10 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_11 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_12 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_13 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_14 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_15 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_16 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_17 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_18 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_19 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_20 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_21 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_22 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_23 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_24 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_25 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_26 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_27 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_28 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_29 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_30 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_31 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_32 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_2_33 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_6 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_7 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_8 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_9 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_10 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_11 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_12 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_13 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_14 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_15 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_16 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_17 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_18 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_19 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_20 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_21 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_22 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_23 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_24 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_25 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_26 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_27 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_28 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_29 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_30 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_31 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_32 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_3_33 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_4 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_5 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_6 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_7 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_8 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_9 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_10 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_11 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_12 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_13 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_14 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_15 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_16 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_17 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_18 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_19 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_20 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_21 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_22 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_23 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_24 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_25 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_26 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_27 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_28 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_29 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_30 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_31 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_32 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_4_33 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_1 = out_id_33; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43]
|
|
wire [7:0] level_intpend_id_5_2 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 235:46]
|
|
wire [7:0] level_intpend_id_5_3 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_4 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_5 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_6 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_7 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_8 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_9 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_10 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_11 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_12 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_13 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_14 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_15 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_16 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_17 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_18 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_19 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_20 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_21 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_22 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_23 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_24 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_25 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_26 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_27 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_28 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_29 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_30 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_31 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_32 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
wire [7:0] level_intpend_id_5_33 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
assign io_mexintpend = _T_1650; // @[el2_pic_ctl.scala 273:17]
|
|
assign io_claimid = _T_1642; // @[el2_pic_ctl.scala 268:37]
|
|
assign io_pl = _T_1643; // @[el2_pic_ctl.scala 269:32]
|
|
assign io_picm_rd_data = picm_bypass_ff ? picm_wr_data_ff : picm_rd_data_in; // @[el2_pic_ctl.scala 311:19]
|
|
assign io_mhwakeup = _T_1652; // @[el2_pic_ctl.scala 276:15]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_io_en = _T_19 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_1_io_en = io_picm_wren | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_2_io_en = _T_22 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_3_io_en = _T_25 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_4_io_en = _T_28 | io_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
picm_raddr_ff = _RAND_0[31:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
picm_waddr_ff = _RAND_1[31:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
picm_wren_ff = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
picm_rden_ff = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
picm_mken_ff = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
picm_wr_data_ff = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_33 = _RAND_6[30:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_34 = _RAND_7[30:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
intpriority_reg_1 = _RAND_8[3:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
intpriority_reg_2 = _RAND_9[3:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
intpriority_reg_3 = _RAND_10[3:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
intpriority_reg_4 = _RAND_11[3:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
intpriority_reg_5 = _RAND_12[3:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
intpriority_reg_6 = _RAND_13[3:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
intpriority_reg_7 = _RAND_14[3:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
intpriority_reg_8 = _RAND_15[3:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
intpriority_reg_9 = _RAND_16[3:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
intpriority_reg_10 = _RAND_17[3:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
intpriority_reg_11 = _RAND_18[3:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
intpriority_reg_12 = _RAND_19[3:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
intpriority_reg_13 = _RAND_20[3:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
intpriority_reg_14 = _RAND_21[3:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
intpriority_reg_15 = _RAND_22[3:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
intpriority_reg_16 = _RAND_23[3:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
intpriority_reg_17 = _RAND_24[3:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
intpriority_reg_18 = _RAND_25[3:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
intpriority_reg_19 = _RAND_26[3:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
intpriority_reg_20 = _RAND_27[3:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
intpriority_reg_21 = _RAND_28[3:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
intpriority_reg_22 = _RAND_29[3:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
intpriority_reg_23 = _RAND_30[3:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
intpriority_reg_24 = _RAND_31[3:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
intpriority_reg_25 = _RAND_32[3:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
intpriority_reg_26 = _RAND_33[3:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
intpriority_reg_27 = _RAND_34[3:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
intpriority_reg_28 = _RAND_35[3:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
intpriority_reg_29 = _RAND_36[3:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
intpriority_reg_30 = _RAND_37[3:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
intpriority_reg_31 = _RAND_38[3:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
intenable_reg_1 = _RAND_39[0:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
intenable_reg_2 = _RAND_40[0:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
intenable_reg_3 = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
intenable_reg_4 = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
intenable_reg_5 = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
intenable_reg_6 = _RAND_44[0:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
intenable_reg_7 = _RAND_45[0:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
intenable_reg_8 = _RAND_46[0:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
intenable_reg_9 = _RAND_47[0:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
intenable_reg_10 = _RAND_48[0:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
intenable_reg_11 = _RAND_49[0:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
intenable_reg_12 = _RAND_50[0:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
intenable_reg_13 = _RAND_51[0:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
intenable_reg_14 = _RAND_52[0:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
intenable_reg_15 = _RAND_53[0:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
intenable_reg_16 = _RAND_54[0:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
intenable_reg_17 = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
intenable_reg_18 = _RAND_56[0:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
intenable_reg_19 = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
intenable_reg_20 = _RAND_58[0:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
intenable_reg_21 = _RAND_59[0:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
intenable_reg_22 = _RAND_60[0:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
intenable_reg_23 = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
intenable_reg_24 = _RAND_62[0:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
intenable_reg_25 = _RAND_63[0:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
intenable_reg_26 = _RAND_64[0:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
intenable_reg_27 = _RAND_65[0:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
intenable_reg_28 = _RAND_66[0:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
intenable_reg_29 = _RAND_67[0:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
intenable_reg_30 = _RAND_68[0:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
intenable_reg_31 = _RAND_69[0:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
gw_config_reg_1 = _RAND_70[1:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
gw_config_reg_2 = _RAND_71[1:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
gw_config_reg_3 = _RAND_72[1:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
gw_config_reg_4 = _RAND_73[1:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
gw_config_reg_5 = _RAND_74[1:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
gw_config_reg_6 = _RAND_75[1:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
gw_config_reg_7 = _RAND_76[1:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
gw_config_reg_8 = _RAND_77[1:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
gw_config_reg_9 = _RAND_78[1:0];
|
|
_RAND_79 = {1{`RANDOM}};
|
|
gw_config_reg_10 = _RAND_79[1:0];
|
|
_RAND_80 = {1{`RANDOM}};
|
|
gw_config_reg_11 = _RAND_80[1:0];
|
|
_RAND_81 = {1{`RANDOM}};
|
|
gw_config_reg_12 = _RAND_81[1:0];
|
|
_RAND_82 = {1{`RANDOM}};
|
|
gw_config_reg_13 = _RAND_82[1:0];
|
|
_RAND_83 = {1{`RANDOM}};
|
|
gw_config_reg_14 = _RAND_83[1:0];
|
|
_RAND_84 = {1{`RANDOM}};
|
|
gw_config_reg_15 = _RAND_84[1:0];
|
|
_RAND_85 = {1{`RANDOM}};
|
|
gw_config_reg_16 = _RAND_85[1:0];
|
|
_RAND_86 = {1{`RANDOM}};
|
|
gw_config_reg_17 = _RAND_86[1:0];
|
|
_RAND_87 = {1{`RANDOM}};
|
|
gw_config_reg_18 = _RAND_87[1:0];
|
|
_RAND_88 = {1{`RANDOM}};
|
|
gw_config_reg_19 = _RAND_88[1:0];
|
|
_RAND_89 = {1{`RANDOM}};
|
|
gw_config_reg_20 = _RAND_89[1:0];
|
|
_RAND_90 = {1{`RANDOM}};
|
|
gw_config_reg_21 = _RAND_90[1:0];
|
|
_RAND_91 = {1{`RANDOM}};
|
|
gw_config_reg_22 = _RAND_91[1:0];
|
|
_RAND_92 = {1{`RANDOM}};
|
|
gw_config_reg_23 = _RAND_92[1:0];
|
|
_RAND_93 = {1{`RANDOM}};
|
|
gw_config_reg_24 = _RAND_93[1:0];
|
|
_RAND_94 = {1{`RANDOM}};
|
|
gw_config_reg_25 = _RAND_94[1:0];
|
|
_RAND_95 = {1{`RANDOM}};
|
|
gw_config_reg_26 = _RAND_95[1:0];
|
|
_RAND_96 = {1{`RANDOM}};
|
|
gw_config_reg_27 = _RAND_96[1:0];
|
|
_RAND_97 = {1{`RANDOM}};
|
|
gw_config_reg_28 = _RAND_97[1:0];
|
|
_RAND_98 = {1{`RANDOM}};
|
|
gw_config_reg_29 = _RAND_98[1:0];
|
|
_RAND_99 = {1{`RANDOM}};
|
|
gw_config_reg_30 = _RAND_99[1:0];
|
|
_RAND_100 = {1{`RANDOM}};
|
|
gw_config_reg_31 = _RAND_100[1:0];
|
|
_RAND_101 = {1{`RANDOM}};
|
|
gw_int_pending = _RAND_101[0:0];
|
|
_RAND_102 = {1{`RANDOM}};
|
|
gw_int_pending_1 = _RAND_102[0:0];
|
|
_RAND_103 = {1{`RANDOM}};
|
|
gw_int_pending_2 = _RAND_103[0:0];
|
|
_RAND_104 = {1{`RANDOM}};
|
|
gw_int_pending_3 = _RAND_104[0:0];
|
|
_RAND_105 = {1{`RANDOM}};
|
|
gw_int_pending_4 = _RAND_105[0:0];
|
|
_RAND_106 = {1{`RANDOM}};
|
|
gw_int_pending_5 = _RAND_106[0:0];
|
|
_RAND_107 = {1{`RANDOM}};
|
|
gw_int_pending_6 = _RAND_107[0:0];
|
|
_RAND_108 = {1{`RANDOM}};
|
|
gw_int_pending_7 = _RAND_108[0:0];
|
|
_RAND_109 = {1{`RANDOM}};
|
|
gw_int_pending_8 = _RAND_109[0:0];
|
|
_RAND_110 = {1{`RANDOM}};
|
|
gw_int_pending_9 = _RAND_110[0:0];
|
|
_RAND_111 = {1{`RANDOM}};
|
|
gw_int_pending_10 = _RAND_111[0:0];
|
|
_RAND_112 = {1{`RANDOM}};
|
|
gw_int_pending_11 = _RAND_112[0:0];
|
|
_RAND_113 = {1{`RANDOM}};
|
|
gw_int_pending_12 = _RAND_113[0:0];
|
|
_RAND_114 = {1{`RANDOM}};
|
|
gw_int_pending_13 = _RAND_114[0:0];
|
|
_RAND_115 = {1{`RANDOM}};
|
|
gw_int_pending_14 = _RAND_115[0:0];
|
|
_RAND_116 = {1{`RANDOM}};
|
|
gw_int_pending_15 = _RAND_116[0:0];
|
|
_RAND_117 = {1{`RANDOM}};
|
|
gw_int_pending_16 = _RAND_117[0:0];
|
|
_RAND_118 = {1{`RANDOM}};
|
|
gw_int_pending_17 = _RAND_118[0:0];
|
|
_RAND_119 = {1{`RANDOM}};
|
|
gw_int_pending_18 = _RAND_119[0:0];
|
|
_RAND_120 = {1{`RANDOM}};
|
|
gw_int_pending_19 = _RAND_120[0:0];
|
|
_RAND_121 = {1{`RANDOM}};
|
|
gw_int_pending_20 = _RAND_121[0:0];
|
|
_RAND_122 = {1{`RANDOM}};
|
|
gw_int_pending_21 = _RAND_122[0:0];
|
|
_RAND_123 = {1{`RANDOM}};
|
|
gw_int_pending_22 = _RAND_123[0:0];
|
|
_RAND_124 = {1{`RANDOM}};
|
|
gw_int_pending_23 = _RAND_124[0:0];
|
|
_RAND_125 = {1{`RANDOM}};
|
|
gw_int_pending_24 = _RAND_125[0:0];
|
|
_RAND_126 = {1{`RANDOM}};
|
|
gw_int_pending_25 = _RAND_126[0:0];
|
|
_RAND_127 = {1{`RANDOM}};
|
|
gw_int_pending_26 = _RAND_127[0:0];
|
|
_RAND_128 = {1{`RANDOM}};
|
|
gw_int_pending_27 = _RAND_128[0:0];
|
|
_RAND_129 = {1{`RANDOM}};
|
|
gw_int_pending_28 = _RAND_129[0:0];
|
|
_RAND_130 = {1{`RANDOM}};
|
|
gw_int_pending_29 = _RAND_130[0:0];
|
|
_RAND_131 = {1{`RANDOM}};
|
|
gw_int_pending_30 = _RAND_131[0:0];
|
|
_RAND_132 = {1{`RANDOM}};
|
|
config_reg = _RAND_132[0:0];
|
|
_RAND_133 = {1{`RANDOM}};
|
|
_T_1642 = _RAND_133[7:0];
|
|
_RAND_134 = {1{`RANDOM}};
|
|
_T_1643 = _RAND_134[3:0];
|
|
_RAND_135 = {1{`RANDOM}};
|
|
_T_1650 = _RAND_135[0:0];
|
|
_RAND_136 = {1{`RANDOM}};
|
|
_T_1652 = _RAND_136[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
picm_raddr_ff = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
picm_waddr_ff = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
picm_wren_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
picm_rden_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
picm_mken_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
picm_wr_data_ff = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_33 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_34 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_1 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_2 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_3 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_4 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_5 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_6 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_7 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_8 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_9 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_10 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_11 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_12 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_13 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_14 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_15 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_16 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_17 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_18 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_19 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_20 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_21 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_22 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_23 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_24 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_25 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_26 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_27 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_28 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_29 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_30 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_31 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_5 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_6 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_7 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_8 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_9 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_10 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_11 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_13 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_14 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_15 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_16 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_17 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_18 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_19 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_20 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_21 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_22 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_23 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_24 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_25 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_26 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_27 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_28 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_29 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_30 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_31 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_4 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_5 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_6 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_7 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_8 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_9 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_10 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_11 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_12 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_13 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_14 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_15 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_16 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_17 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_18 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_19 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_20 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_21 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_22 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_23 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_24 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_25 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_26 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_27 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_28 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_29 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_30 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_31 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_5 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_6 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_7 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_8 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_9 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_10 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_11 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_13 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_14 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_15 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_16 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_17 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_18 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_19 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_20 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_21 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_22 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_23 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_24 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_25 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_26 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_27 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_28 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_29 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_int_pending_30 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
config_reg = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1642 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1643 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1650 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1652 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge pic_raddr_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
picm_raddr_ff <= 32'h0;
|
|
end else begin
|
|
picm_raddr_ff <= io_picm_rdaddr;
|
|
end
|
|
end
|
|
always @(posedge pic_data_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
picm_waddr_ff <= 32'h0;
|
|
end else begin
|
|
picm_waddr_ff <= io_picm_wraddr;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
picm_wren_ff <= 1'h0;
|
|
end else begin
|
|
picm_wren_ff <= io_picm_wren;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
picm_rden_ff <= 1'h0;
|
|
end else begin
|
|
picm_rden_ff <= io_picm_rden;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
picm_mken_ff <= 1'h0;
|
|
end else begin
|
|
picm_mken_ff <= io_picm_mken;
|
|
end
|
|
end
|
|
always @(posedge pic_data_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
picm_wr_data_ff <= 32'h0;
|
|
end else begin
|
|
picm_wr_data_ff <= io_picm_wr_data;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_33 <= 31'h0;
|
|
end else begin
|
|
_T_33 <= io_extintsrc_req[31:1];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_34 <= 31'h0;
|
|
end else begin
|
|
_T_34 <= _T_33;
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_1 <= 4'h0;
|
|
end else if (intpriority_reg_we_1) begin
|
|
intpriority_reg_1 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_2 <= 4'h0;
|
|
end else if (intpriority_reg_we_2) begin
|
|
intpriority_reg_2 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_3 <= 4'h0;
|
|
end else if (intpriority_reg_we_3) begin
|
|
intpriority_reg_3 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_4 <= 4'h0;
|
|
end else if (intpriority_reg_we_4) begin
|
|
intpriority_reg_4 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_5 <= 4'h0;
|
|
end else if (intpriority_reg_we_5) begin
|
|
intpriority_reg_5 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_6 <= 4'h0;
|
|
end else if (intpriority_reg_we_6) begin
|
|
intpriority_reg_6 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_7 <= 4'h0;
|
|
end else if (intpriority_reg_we_7) begin
|
|
intpriority_reg_7 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_8 <= 4'h0;
|
|
end else if (intpriority_reg_we_8) begin
|
|
intpriority_reg_8 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_9 <= 4'h0;
|
|
end else if (intpriority_reg_we_9) begin
|
|
intpriority_reg_9 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_10 <= 4'h0;
|
|
end else if (intpriority_reg_we_10) begin
|
|
intpriority_reg_10 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_11 <= 4'h0;
|
|
end else if (intpriority_reg_we_11) begin
|
|
intpriority_reg_11 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_12 <= 4'h0;
|
|
end else if (intpriority_reg_we_12) begin
|
|
intpriority_reg_12 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_13 <= 4'h0;
|
|
end else if (intpriority_reg_we_13) begin
|
|
intpriority_reg_13 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_14 <= 4'h0;
|
|
end else if (intpriority_reg_we_14) begin
|
|
intpriority_reg_14 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_15 <= 4'h0;
|
|
end else if (intpriority_reg_we_15) begin
|
|
intpriority_reg_15 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_16 <= 4'h0;
|
|
end else if (intpriority_reg_we_16) begin
|
|
intpriority_reg_16 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_17 <= 4'h0;
|
|
end else if (intpriority_reg_we_17) begin
|
|
intpriority_reg_17 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_18 <= 4'h0;
|
|
end else if (intpriority_reg_we_18) begin
|
|
intpriority_reg_18 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_19 <= 4'h0;
|
|
end else if (intpriority_reg_we_19) begin
|
|
intpriority_reg_19 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_20 <= 4'h0;
|
|
end else if (intpriority_reg_we_20) begin
|
|
intpriority_reg_20 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_21 <= 4'h0;
|
|
end else if (intpriority_reg_we_21) begin
|
|
intpriority_reg_21 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_22 <= 4'h0;
|
|
end else if (intpriority_reg_we_22) begin
|
|
intpriority_reg_22 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_23 <= 4'h0;
|
|
end else if (intpriority_reg_we_23) begin
|
|
intpriority_reg_23 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_24 <= 4'h0;
|
|
end else if (intpriority_reg_we_24) begin
|
|
intpriority_reg_24 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_25 <= 4'h0;
|
|
end else if (intpriority_reg_we_25) begin
|
|
intpriority_reg_25 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_26 <= 4'h0;
|
|
end else if (intpriority_reg_we_26) begin
|
|
intpriority_reg_26 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_27 <= 4'h0;
|
|
end else if (intpriority_reg_we_27) begin
|
|
intpriority_reg_27 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_28 <= 4'h0;
|
|
end else if (intpriority_reg_we_28) begin
|
|
intpriority_reg_28 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_29 <= 4'h0;
|
|
end else if (intpriority_reg_we_29) begin
|
|
intpriority_reg_29 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_30 <= 4'h0;
|
|
end else if (intpriority_reg_we_30) begin
|
|
intpriority_reg_30 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_pri_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_31 <= 4'h0;
|
|
end else if (intpriority_reg_we_31) begin
|
|
intpriority_reg_31 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_1 <= 1'h0;
|
|
end else if (intenable_reg_we_1) begin
|
|
intenable_reg_1 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_2 <= 1'h0;
|
|
end else if (intenable_reg_we_2) begin
|
|
intenable_reg_2 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_3 <= 1'h0;
|
|
end else if (intenable_reg_we_3) begin
|
|
intenable_reg_3 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_4 <= 1'h0;
|
|
end else if (intenable_reg_we_4) begin
|
|
intenable_reg_4 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_5 <= 1'h0;
|
|
end else if (intenable_reg_we_5) begin
|
|
intenable_reg_5 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_6 <= 1'h0;
|
|
end else if (intenable_reg_we_6) begin
|
|
intenable_reg_6 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_7 <= 1'h0;
|
|
end else if (intenable_reg_we_7) begin
|
|
intenable_reg_7 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_8 <= 1'h0;
|
|
end else if (intenable_reg_we_8) begin
|
|
intenable_reg_8 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_9 <= 1'h0;
|
|
end else if (intenable_reg_we_9) begin
|
|
intenable_reg_9 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_10 <= 1'h0;
|
|
end else if (intenable_reg_we_10) begin
|
|
intenable_reg_10 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_11 <= 1'h0;
|
|
end else if (intenable_reg_we_11) begin
|
|
intenable_reg_11 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_12 <= 1'h0;
|
|
end else if (intenable_reg_we_12) begin
|
|
intenable_reg_12 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_13 <= 1'h0;
|
|
end else if (intenable_reg_we_13) begin
|
|
intenable_reg_13 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_14 <= 1'h0;
|
|
end else if (intenable_reg_we_14) begin
|
|
intenable_reg_14 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_15 <= 1'h0;
|
|
end else if (intenable_reg_we_15) begin
|
|
intenable_reg_15 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_16 <= 1'h0;
|
|
end else if (intenable_reg_we_16) begin
|
|
intenable_reg_16 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_17 <= 1'h0;
|
|
end else if (intenable_reg_we_17) begin
|
|
intenable_reg_17 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_18 <= 1'h0;
|
|
end else if (intenable_reg_we_18) begin
|
|
intenable_reg_18 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_19 <= 1'h0;
|
|
end else if (intenable_reg_we_19) begin
|
|
intenable_reg_19 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_20 <= 1'h0;
|
|
end else if (intenable_reg_we_20) begin
|
|
intenable_reg_20 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_21 <= 1'h0;
|
|
end else if (intenable_reg_we_21) begin
|
|
intenable_reg_21 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_22 <= 1'h0;
|
|
end else if (intenable_reg_we_22) begin
|
|
intenable_reg_22 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_23 <= 1'h0;
|
|
end else if (intenable_reg_we_23) begin
|
|
intenable_reg_23 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_24 <= 1'h0;
|
|
end else if (intenable_reg_we_24) begin
|
|
intenable_reg_24 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_25 <= 1'h0;
|
|
end else if (intenable_reg_we_25) begin
|
|
intenable_reg_25 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_26 <= 1'h0;
|
|
end else if (intenable_reg_we_26) begin
|
|
intenable_reg_26 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_27 <= 1'h0;
|
|
end else if (intenable_reg_we_27) begin
|
|
intenable_reg_27 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_28 <= 1'h0;
|
|
end else if (intenable_reg_we_28) begin
|
|
intenable_reg_28 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_29 <= 1'h0;
|
|
end else if (intenable_reg_we_29) begin
|
|
intenable_reg_29 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_30 <= 1'h0;
|
|
end else if (intenable_reg_we_30) begin
|
|
intenable_reg_30 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge pic_int_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_31 <= 1'h0;
|
|
end else if (intenable_reg_we_31) begin
|
|
intenable_reg_31 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_1 <= 2'h0;
|
|
end else if (gw_config_reg_we_1) begin
|
|
gw_config_reg_1 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_2 <= 2'h0;
|
|
end else if (gw_config_reg_we_2) begin
|
|
gw_config_reg_2 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_3 <= 2'h0;
|
|
end else if (gw_config_reg_we_3) begin
|
|
gw_config_reg_3 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_4 <= 2'h0;
|
|
end else if (gw_config_reg_we_4) begin
|
|
gw_config_reg_4 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_5 <= 2'h0;
|
|
end else if (gw_config_reg_we_5) begin
|
|
gw_config_reg_5 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_6 <= 2'h0;
|
|
end else if (gw_config_reg_we_6) begin
|
|
gw_config_reg_6 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_7 <= 2'h0;
|
|
end else if (gw_config_reg_we_7) begin
|
|
gw_config_reg_7 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_8 <= 2'h0;
|
|
end else if (gw_config_reg_we_8) begin
|
|
gw_config_reg_8 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_9 <= 2'h0;
|
|
end else if (gw_config_reg_we_9) begin
|
|
gw_config_reg_9 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_10 <= 2'h0;
|
|
end else if (gw_config_reg_we_10) begin
|
|
gw_config_reg_10 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_11 <= 2'h0;
|
|
end else if (gw_config_reg_we_11) begin
|
|
gw_config_reg_11 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_12 <= 2'h0;
|
|
end else if (gw_config_reg_we_12) begin
|
|
gw_config_reg_12 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_13 <= 2'h0;
|
|
end else if (gw_config_reg_we_13) begin
|
|
gw_config_reg_13 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_14 <= 2'h0;
|
|
end else if (gw_config_reg_we_14) begin
|
|
gw_config_reg_14 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_15 <= 2'h0;
|
|
end else if (gw_config_reg_we_15) begin
|
|
gw_config_reg_15 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_16 <= 2'h0;
|
|
end else if (gw_config_reg_we_16) begin
|
|
gw_config_reg_16 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_17 <= 2'h0;
|
|
end else if (gw_config_reg_we_17) begin
|
|
gw_config_reg_17 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_18 <= 2'h0;
|
|
end else if (gw_config_reg_we_18) begin
|
|
gw_config_reg_18 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_19 <= 2'h0;
|
|
end else if (gw_config_reg_we_19) begin
|
|
gw_config_reg_19 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_20 <= 2'h0;
|
|
end else if (gw_config_reg_we_20) begin
|
|
gw_config_reg_20 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_21 <= 2'h0;
|
|
end else if (gw_config_reg_we_21) begin
|
|
gw_config_reg_21 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_22 <= 2'h0;
|
|
end else if (gw_config_reg_we_22) begin
|
|
gw_config_reg_22 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_23 <= 2'h0;
|
|
end else if (gw_config_reg_we_23) begin
|
|
gw_config_reg_23 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_24 <= 2'h0;
|
|
end else if (gw_config_reg_we_24) begin
|
|
gw_config_reg_24 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_25 <= 2'h0;
|
|
end else if (gw_config_reg_we_25) begin
|
|
gw_config_reg_25 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_26 <= 2'h0;
|
|
end else if (gw_config_reg_we_26) begin
|
|
gw_config_reg_26 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_27 <= 2'h0;
|
|
end else if (gw_config_reg_we_27) begin
|
|
gw_config_reg_27 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_28 <= 2'h0;
|
|
end else if (gw_config_reg_we_28) begin
|
|
gw_config_reg_28 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_29 <= 2'h0;
|
|
end else if (gw_config_reg_we_29) begin
|
|
gw_config_reg_29 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_30 <= 2'h0;
|
|
end else if (gw_config_reg_we_30) begin
|
|
gw_config_reg_30 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge gw_config_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_31 <= 2'h0;
|
|
end else if (gw_config_reg_we_31) begin
|
|
gw_config_reg_31 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending <= 1'h0;
|
|
end else begin
|
|
gw_int_pending <= _T_970 | _T_972;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_1 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_1 <= _T_982 | _T_984;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_2 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_2 <= _T_994 | _T_996;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_3 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_3 <= _T_1006 | _T_1008;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_4 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_4 <= _T_1018 | _T_1020;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_5 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_5 <= _T_1030 | _T_1032;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_6 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_6 <= _T_1042 | _T_1044;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_7 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_7 <= _T_1054 | _T_1056;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_8 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_8 <= _T_1066 | _T_1068;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_9 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_9 <= _T_1078 | _T_1080;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_10 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_10 <= _T_1090 | _T_1092;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_11 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_11 <= _T_1102 | _T_1104;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_12 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_12 <= _T_1114 | _T_1116;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_13 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_13 <= _T_1126 | _T_1128;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_14 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_14 <= _T_1138 | _T_1140;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_15 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_15 <= _T_1150 | _T_1152;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_16 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_16 <= _T_1162 | _T_1164;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_17 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_17 <= _T_1174 | _T_1176;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_18 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_18 <= _T_1186 | _T_1188;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_19 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_19 <= _T_1198 | _T_1200;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_20 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_20 <= _T_1210 | _T_1212;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_21 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_21 <= _T_1222 | _T_1224;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_22 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_22 <= _T_1234 | _T_1236;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_23 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_23 <= _T_1246 | _T_1248;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_24 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_24 <= _T_1258 | _T_1260;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_25 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_25 <= _T_1270 | _T_1272;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_26 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_26 <= _T_1282 | _T_1284;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_27 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_27 <= _T_1294 | _T_1296;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_28 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_28 <= _T_1306 | _T_1308;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_29 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_29 <= _T_1318 | _T_1320;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_int_pending_30 <= 1'h0;
|
|
end else begin
|
|
gw_int_pending_30 <= _T_1330 | _T_1332;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
config_reg <= 1'h0;
|
|
end else if (config_reg_we) begin
|
|
config_reg <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1642 <= 8'h0;
|
|
end else begin
|
|
_T_1642 <= level_intpend_id_5_0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1643 <= 4'h0;
|
|
end else if (config_reg) begin
|
|
_T_1643 <= _T_1641;
|
|
end else begin
|
|
_T_1643 <= level_intpend_w_prior_en_5_0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1650 <= 1'h0;
|
|
end else begin
|
|
_T_1650 <= _T_1648 & _T_1649;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1652 <= 1'h0;
|
|
end else begin
|
|
_T_1652 <= pl_in_q == maxint;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_dma_ctrl(
|
|
input clock,
|
|
input reset,
|
|
input io_free_clk,
|
|
input io_dma_bus_clk_en,
|
|
input io_clk_override,
|
|
input io_scan_mode,
|
|
input [31:0] io_dbg_cmd_addr,
|
|
input [31:0] io_dbg_cmd_wrdata,
|
|
input io_dbg_cmd_valid,
|
|
input io_dbg_cmd_write,
|
|
input [1:0] io_dbg_cmd_type,
|
|
input [1:0] io_dbg_cmd_size,
|
|
input io_dbg_dma_bubble,
|
|
output io_dma_dbg_ready,
|
|
output io_dma_dbg_cmd_done,
|
|
output io_dma_dbg_cmd_fail,
|
|
output [31:0] io_dma_dbg_rddata,
|
|
output io_dma_dccm_req,
|
|
output io_dma_iccm_req,
|
|
output [2:0] io_dma_mem_tag,
|
|
output [31:0] io_dma_mem_addr,
|
|
output [2:0] io_dma_mem_sz,
|
|
output io_dma_mem_write,
|
|
output [63:0] io_dma_mem_wdata,
|
|
input io_dccm_dma_rvalid,
|
|
input io_dccm_dma_ecc_error,
|
|
input [2:0] io_dccm_dma_rtag,
|
|
input [63:0] io_dccm_dma_rdata,
|
|
input io_iccm_dma_rvalid,
|
|
input io_iccm_dma_ecc_error,
|
|
input [2:0] io_iccm_dma_rtag,
|
|
input [63:0] io_iccm_dma_rdata,
|
|
output io_dma_dccm_stall_any,
|
|
output io_dma_iccm_stall_any,
|
|
input io_dccm_ready,
|
|
input io_iccm_ready,
|
|
input [2:0] io_dec_tlu_dma_qos_prty,
|
|
output io_dma_pmu_dccm_read,
|
|
output io_dma_pmu_dccm_write,
|
|
output io_dma_pmu_any_read,
|
|
output io_dma_pmu_any_write,
|
|
input io_dma_axi_awvalid,
|
|
output io_dma_axi_awready,
|
|
input io_dma_axi_awid,
|
|
input [31:0] io_dma_axi_awaddr,
|
|
input [2:0] io_dma_axi_awsize,
|
|
input io_dma_axi_wvalid,
|
|
output io_dma_axi_wready,
|
|
input [63:0] io_dma_axi_wdata,
|
|
input [7:0] io_dma_axi_wstrb,
|
|
output io_dma_axi_bvalid,
|
|
input io_dma_axi_bready,
|
|
output [1:0] io_dma_axi_bresp,
|
|
output io_dma_axi_bid,
|
|
input io_dma_axi_arvalid,
|
|
output io_dma_axi_arready,
|
|
input io_dma_axi_arid,
|
|
input [31:0] io_dma_axi_araddr,
|
|
input [2:0] io_dma_axi_arsize,
|
|
output io_dma_axi_rvalid,
|
|
input io_dma_axi_rready,
|
|
output io_dma_axi_rid,
|
|
output [63:0] io_dma_axi_rdata,
|
|
output [1:0] io_dma_axi_rresp
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [63:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [63:0] _RAND_65;
|
|
reg [63:0] _RAND_66;
|
|
reg [63:0] _RAND_67;
|
|
reg [63:0] _RAND_68;
|
|
reg [63:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
reg [31:0] _RAND_75;
|
|
reg [31:0] _RAND_76;
|
|
reg [31:0] _RAND_77;
|
|
reg [31:0] _RAND_78;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire dma_buffer_c1cgc_io_l1clk; // @[el2_dma_ctrl.scala 439:32]
|
|
wire dma_buffer_c1cgc_io_clk; // @[el2_dma_ctrl.scala 439:32]
|
|
wire dma_buffer_c1cgc_io_en; // @[el2_dma_ctrl.scala 439:32]
|
|
wire dma_buffer_c1cgc_io_scan_mode; // @[el2_dma_ctrl.scala 439:32]
|
|
wire dma_free_cgc_io_l1clk; // @[el2_dma_ctrl.scala 445:28]
|
|
wire dma_free_cgc_io_clk; // @[el2_dma_ctrl.scala 445:28]
|
|
wire dma_free_cgc_io_en; // @[el2_dma_ctrl.scala 445:28]
|
|
wire dma_free_cgc_io_scan_mode; // @[el2_dma_ctrl.scala 445:28]
|
|
wire dma_bus_cgc_io_l1clk; // @[el2_dma_ctrl.scala 451:27]
|
|
wire dma_bus_cgc_io_clk; // @[el2_dma_ctrl.scala 451:27]
|
|
wire dma_bus_cgc_io_en; // @[el2_dma_ctrl.scala 451:27]
|
|
wire dma_bus_cgc_io_scan_mode; // @[el2_dma_ctrl.scala 451:27]
|
|
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23]
|
|
wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23]
|
|
wire dma_free_clk = dma_free_cgc_io_l1clk; // @[el2_dma_ctrl.scala 224:26 el2_dma_ctrl.scala 449:29]
|
|
reg [2:0] RdPtr; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_4; // @[el2_lib.scala 514:16]
|
|
reg [31:0] fifo_addr_3; // @[el2_lib.scala 514:16]
|
|
reg [31:0] fifo_addr_2; // @[el2_lib.scala 514:16]
|
|
reg [31:0] fifo_addr_1; // @[el2_lib.scala 514:16]
|
|
reg [31:0] fifo_addr_0; // @[el2_lib.scala 514:16]
|
|
wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[el2_dma_ctrl.scala 405:20]
|
|
wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[el2_dma_ctrl.scala 405:20]
|
|
wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[el2_dma_ctrl.scala 405:20]
|
|
wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[el2_dma_ctrl.scala 405:20]
|
|
wire dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[el2_lib.scala 501:39]
|
|
wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[el2_lib.scala 501:39]
|
|
wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[el2_lib.scala 501:39]
|
|
wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[el2_dma_ctrl.scala 226:25 el2_dma_ctrl.scala 455:28]
|
|
reg wrbuf_vld; // @[el2_dma_ctrl.scala 465:59]
|
|
reg wrbuf_data_vld; // @[el2_dma_ctrl.scala 467:59]
|
|
wire _T_1240 = wrbuf_vld & wrbuf_data_vld; // @[el2_dma_ctrl.scala 523:43]
|
|
reg rdbuf_vld; // @[el2_dma_ctrl.scala 491:47]
|
|
wire _T_1241 = _T_1240 & rdbuf_vld; // @[el2_dma_ctrl.scala 523:60]
|
|
reg axi_mstr_priority; // @[Reg.scala 27:20]
|
|
wire axi_mstr_sel = _T_1241 ? axi_mstr_priority : _T_1240; // @[el2_dma_ctrl.scala 523:31]
|
|
reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16]
|
|
reg [31:0] rdbuf_addr; // @[el2_lib.scala 514:16]
|
|
wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[el2_dma_ctrl.scala 513:43]
|
|
wire [2:0] _GEN_90 = {{2'd0}, io_dbg_cmd_addr[2]}; // @[el2_dma_ctrl.scala 251:76]
|
|
wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[el2_dma_ctrl.scala 251:76]
|
|
wire [18:0] _T_18 = 19'hf << _T_17; // @[el2_dma_ctrl.scala 251:68]
|
|
reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
|
|
wire [18:0] _T_20 = io_dbg_cmd_valid ? _T_18 : {{11'd0}, wrbuf_byteen}; // @[el2_dma_ctrl.scala 251:34]
|
|
wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58]
|
|
reg [2:0] wrbuf_sz; // @[Reg.scala 27:20]
|
|
reg [2:0] rdbuf_sz; // @[Reg.scala 27:20]
|
|
wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[el2_dma_ctrl.scala 514:45]
|
|
wire [2:0] fifo_sz_in = io_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[el2_dma_ctrl.scala 253:33]
|
|
wire fifo_write_in = io_dbg_cmd_valid ? io_dbg_cmd_write : axi_mstr_sel; // @[el2_dma_ctrl.scala 255:33]
|
|
wire bus_cmd_valid = _T_1240 | rdbuf_vld; // @[el2_dma_ctrl.scala 509:69]
|
|
reg fifo_full; // @[el2_dma_ctrl.scala 423:12]
|
|
reg dbg_dma_bubble_bus; // @[el2_dma_ctrl.scala 427:12]
|
|
wire _T_989 = fifo_full | dbg_dma_bubble_bus; // @[el2_dma_ctrl.scala 355:39]
|
|
wire dma_fifo_ready = ~_T_989; // @[el2_dma_ctrl.scala 355:27]
|
|
wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[el2_dma_ctrl.scala 510:54]
|
|
wire _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 262:80]
|
|
wire _T_31 = io_dbg_cmd_valid & io_dbg_cmd_type[1]; // @[el2_dma_ctrl.scala 262:121]
|
|
wire _T_32 = _T_28 | _T_31; // @[el2_dma_ctrl.scala 262:101]
|
|
reg [2:0] WrPtr; // @[Reg.scala 27:20]
|
|
wire _T_33 = 3'h0 == WrPtr; // @[el2_dma_ctrl.scala 262:158]
|
|
wire _T_34 = _T_32 & _T_33; // @[el2_dma_ctrl.scala 262:151]
|
|
wire _T_41 = 3'h1 == WrPtr; // @[el2_dma_ctrl.scala 262:158]
|
|
wire _T_42 = _T_32 & _T_41; // @[el2_dma_ctrl.scala 262:151]
|
|
wire _T_49 = 3'h2 == WrPtr; // @[el2_dma_ctrl.scala 262:158]
|
|
wire _T_50 = _T_32 & _T_49; // @[el2_dma_ctrl.scala 262:151]
|
|
wire _T_57 = 3'h3 == WrPtr; // @[el2_dma_ctrl.scala 262:158]
|
|
wire _T_58 = _T_32 & _T_57; // @[el2_dma_ctrl.scala 262:151]
|
|
wire _T_65 = 3'h4 == WrPtr; // @[el2_dma_ctrl.scala 262:158]
|
|
wire _T_66 = _T_32 & _T_65; // @[el2_dma_ctrl.scala 262:151]
|
|
wire [4:0] fifo_cmd_en = {_T_66,_T_58,_T_50,_T_42,_T_34}; // @[Cat.scala 29:58]
|
|
wire _T_71 = axi_mstr_prty_en & fifo_write_in; // @[el2_dma_ctrl.scala 264:73]
|
|
wire _T_72 = _T_71 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 264:89]
|
|
wire _T_75 = _T_31 & io_dbg_cmd_write; // @[el2_dma_ctrl.scala 264:151]
|
|
wire _T_76 = _T_72 | _T_75; // @[el2_dma_ctrl.scala 264:110]
|
|
wire _T_78 = _T_76 & _T_33; // @[el2_dma_ctrl.scala 264:172]
|
|
reg _T_598; // @[el2_dma_ctrl.scala 282:82]
|
|
reg _T_591; // @[el2_dma_ctrl.scala 282:82]
|
|
reg _T_584; // @[el2_dma_ctrl.scala 282:82]
|
|
reg _T_577; // @[el2_dma_ctrl.scala 282:82]
|
|
reg _T_570; // @[el2_dma_ctrl.scala 282:82]
|
|
wire [4:0] fifo_valid = {_T_598,_T_591,_T_584,_T_577,_T_570}; // @[Cat.scala 29:58]
|
|
wire [4:0] _T_990 = fifo_valid >> RdPtr; // @[el2_dma_ctrl.scala 359:38]
|
|
reg _T_760; // @[el2_dma_ctrl.scala 290:89]
|
|
reg _T_753; // @[el2_dma_ctrl.scala 290:89]
|
|
reg _T_746; // @[el2_dma_ctrl.scala 290:89]
|
|
reg _T_739; // @[el2_dma_ctrl.scala 290:89]
|
|
reg _T_732; // @[el2_dma_ctrl.scala 290:89]
|
|
wire [4:0] fifo_done = {_T_760,_T_753,_T_746,_T_739,_T_732}; // @[Cat.scala 29:58]
|
|
wire [4:0] _T_992 = fifo_done >> RdPtr; // @[el2_dma_ctrl.scala 359:58]
|
|
wire _T_994 = ~_T_992[0]; // @[el2_dma_ctrl.scala 359:48]
|
|
wire _T_995 = _T_990[0] & _T_994; // @[el2_dma_ctrl.scala 359:46]
|
|
wire dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[el2_dma_ctrl.scala 228:31 el2_dma_ctrl.scala 443:33]
|
|
reg _T_886; // @[Reg.scala 27:20]
|
|
reg _T_884; // @[Reg.scala 27:20]
|
|
reg _T_882; // @[Reg.scala 27:20]
|
|
reg _T_880; // @[Reg.scala 27:20]
|
|
reg _T_878; // @[Reg.scala 27:20]
|
|
wire [4:0] fifo_dbg = {_T_886,_T_884,_T_882,_T_880,_T_878}; // @[Cat.scala 29:58]
|
|
wire [4:0] _T_996 = fifo_dbg >> RdPtr; // @[el2_dma_ctrl.scala 359:77]
|
|
wire _T_998 = ~_T_996[0]; // @[el2_dma_ctrl.scala 359:68]
|
|
wire _T_999 = _T_995 & _T_998; // @[el2_dma_ctrl.scala 359:66]
|
|
wire _T_1000 = dma_mem_addr_in_dccm | dma_mem_addr_in_iccm; // @[el2_dma_ctrl.scala 359:111]
|
|
wire _T_1001 = ~_T_1000; // @[el2_dma_ctrl.scala 359:88]
|
|
wire dma_address_error = _T_999 & _T_1001; // @[el2_dma_ctrl.scala 359:85]
|
|
wire _T_1009 = ~dma_address_error; // @[el2_dma_ctrl.scala 360:68]
|
|
wire _T_1010 = _T_995 & _T_1009; // @[el2_dma_ctrl.scala 360:66]
|
|
reg [2:0] fifo_sz_4; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_3; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_2; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_1; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_0; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_65 = 3'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[el2_dma_ctrl.scala 406:20]
|
|
wire [2:0] _GEN_66 = 3'h2 == RdPtr ? fifo_sz_2 : _GEN_65; // @[el2_dma_ctrl.scala 406:20]
|
|
wire [2:0] _GEN_67 = 3'h3 == RdPtr ? fifo_sz_3 : _GEN_66; // @[el2_dma_ctrl.scala 406:20]
|
|
wire [2:0] dma_mem_sz_int = 3'h4 == RdPtr ? fifo_sz_4 : _GEN_67; // @[el2_dma_ctrl.scala 406:20]
|
|
wire _T_1012 = dma_mem_sz_int == 3'h1; // @[el2_dma_ctrl.scala 361:28]
|
|
wire _T_1014 = _T_1012 & dma_mem_addr_int[0]; // @[el2_dma_ctrl.scala 361:37]
|
|
wire _T_1016 = dma_mem_sz_int == 3'h2; // @[el2_dma_ctrl.scala 362:29]
|
|
wire _T_1018 = |dma_mem_addr_int[1:0]; // @[el2_dma_ctrl.scala 362:64]
|
|
wire _T_1019 = _T_1016 & _T_1018; // @[el2_dma_ctrl.scala 362:38]
|
|
wire _T_1020 = _T_1014 | _T_1019; // @[el2_dma_ctrl.scala 361:60]
|
|
wire _T_1022 = dma_mem_sz_int == 3'h3; // @[el2_dma_ctrl.scala 363:29]
|
|
wire _T_1024 = |dma_mem_addr_int[2:0]; // @[el2_dma_ctrl.scala 363:64]
|
|
wire _T_1025 = _T_1022 & _T_1024; // @[el2_dma_ctrl.scala 363:38]
|
|
wire _T_1026 = _T_1020 | _T_1025; // @[el2_dma_ctrl.scala 362:70]
|
|
wire _T_1028 = dma_mem_sz_int[1:0] == 2'h2; // @[el2_dma_ctrl.scala 364:55]
|
|
wire _T_1030 = dma_mem_sz_int[1:0] == 2'h3; // @[el2_dma_ctrl.scala 364:88]
|
|
wire _T_1031 = _T_1028 | _T_1030; // @[el2_dma_ctrl.scala 364:64]
|
|
wire _T_1032 = ~_T_1031; // @[el2_dma_ctrl.scala 364:31]
|
|
wire _T_1033 = dma_mem_addr_in_iccm & _T_1032; // @[el2_dma_ctrl.scala 364:29]
|
|
wire _T_1034 = _T_1026 | _T_1033; // @[el2_dma_ctrl.scala 363:70]
|
|
wire _T_1035 = dma_mem_addr_in_dccm & io_dma_mem_write; // @[el2_dma_ctrl.scala 365:29]
|
|
wire _T_1042 = _T_1035 & _T_1032; // @[el2_dma_ctrl.scala 365:48]
|
|
wire _T_1043 = _T_1034 | _T_1042; // @[el2_dma_ctrl.scala 364:108]
|
|
wire _T_1046 = io_dma_mem_write & _T_1016; // @[el2_dma_ctrl.scala 366:25]
|
|
wire _T_1048 = dma_mem_addr_int[2:0] == 3'h0; // @[el2_dma_ctrl.scala 366:94]
|
|
reg [7:0] fifo_byteen_4; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_3; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_2; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_1; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_0; // @[Reg.scala 27:20]
|
|
wire [7:0] _GEN_70 = 3'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[el2_dma_ctrl.scala 409:20]
|
|
wire [7:0] _GEN_71 = 3'h2 == RdPtr ? fifo_byteen_2 : _GEN_70; // @[el2_dma_ctrl.scala 409:20]
|
|
wire [7:0] _GEN_72 = 3'h3 == RdPtr ? fifo_byteen_3 : _GEN_71; // @[el2_dma_ctrl.scala 409:20]
|
|
wire [7:0] dma_mem_byteen = 3'h4 == RdPtr ? fifo_byteen_4 : _GEN_72; // @[el2_dma_ctrl.scala 409:20]
|
|
wire [3:0] _T_1059 = _T_1048 ? dma_mem_byteen[3:0] : 4'h0; // @[Mux.scala 27:72]
|
|
wire _T_1051 = dma_mem_addr_int[2:0] == 3'h1; // @[el2_dma_ctrl.scala 367:32]
|
|
wire [3:0] _T_1060 = _T_1051 ? dma_mem_byteen[4:1] : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1063 = _T_1059 | _T_1060; // @[Mux.scala 27:72]
|
|
wire _T_1054 = dma_mem_addr_int[2:0] == 3'h2; // @[el2_dma_ctrl.scala 368:32]
|
|
wire [3:0] _T_1061 = _T_1054 ? dma_mem_byteen[5:2] : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1064 = _T_1063 | _T_1061; // @[Mux.scala 27:72]
|
|
wire _T_1057 = dma_mem_addr_int[2:0] == 3'h3; // @[el2_dma_ctrl.scala 369:32]
|
|
wire [3:0] _T_1062 = _T_1057 ? dma_mem_byteen[6:3] : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1065 = _T_1064 | _T_1062; // @[Mux.scala 27:72]
|
|
wire _T_1067 = _T_1065 != 4'hf; // @[el2_dma_ctrl.scala 369:68]
|
|
wire _T_1068 = _T_1046 & _T_1067; // @[el2_dma_ctrl.scala 366:58]
|
|
wire _T_1069 = _T_1043 | _T_1068; // @[el2_dma_ctrl.scala 365:125]
|
|
wire _T_1072 = io_dma_mem_write & _T_1022; // @[el2_dma_ctrl.scala 370:25]
|
|
wire _T_1074 = dma_mem_byteen == 8'hf; // @[el2_dma_ctrl.scala 370:83]
|
|
wire _T_1076 = dma_mem_byteen == 8'hf0; // @[el2_dma_ctrl.scala 370:119]
|
|
wire _T_1077 = _T_1074 | _T_1076; // @[el2_dma_ctrl.scala 370:96]
|
|
wire _T_1079 = dma_mem_byteen == 8'hff; // @[el2_dma_ctrl.scala 370:155]
|
|
wire _T_1080 = _T_1077 | _T_1079; // @[el2_dma_ctrl.scala 370:132]
|
|
wire _T_1081 = ~_T_1080; // @[el2_dma_ctrl.scala 370:60]
|
|
wire _T_1082 = _T_1072 & _T_1081; // @[el2_dma_ctrl.scala 370:58]
|
|
wire _T_1083 = _T_1069 | _T_1082; // @[el2_dma_ctrl.scala 369:79]
|
|
wire dma_alignment_error = _T_1010 & _T_1083; // @[el2_dma_ctrl.scala 360:87]
|
|
wire _T_79 = dma_address_error | dma_alignment_error; // @[el2_dma_ctrl.scala 264:213]
|
|
wire _T_80 = 3'h0 == RdPtr; // @[el2_dma_ctrl.scala 264:243]
|
|
wire _T_81 = _T_79 & _T_80; // @[el2_dma_ctrl.scala 264:236]
|
|
wire _T_82 = _T_78 | _T_81; // @[el2_dma_ctrl.scala 264:191]
|
|
wire _T_83 = 3'h0 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 264:284]
|
|
wire _T_84 = io_dccm_dma_rvalid & _T_83; // @[el2_dma_ctrl.scala 264:277]
|
|
wire _T_85 = _T_82 | _T_84; // @[el2_dma_ctrl.scala 264:255]
|
|
wire _T_86 = 3'h0 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 264:336]
|
|
wire _T_87 = io_iccm_dma_rvalid & _T_86; // @[el2_dma_ctrl.scala 264:329]
|
|
wire _T_88 = _T_85 | _T_87; // @[el2_dma_ctrl.scala 264:307]
|
|
wire _T_96 = _T_76 & _T_41; // @[el2_dma_ctrl.scala 264:172]
|
|
wire _T_98 = 3'h1 == RdPtr; // @[el2_dma_ctrl.scala 264:243]
|
|
wire _T_99 = _T_79 & _T_98; // @[el2_dma_ctrl.scala 264:236]
|
|
wire _T_100 = _T_96 | _T_99; // @[el2_dma_ctrl.scala 264:191]
|
|
wire _T_101 = 3'h1 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 264:284]
|
|
wire _T_102 = io_dccm_dma_rvalid & _T_101; // @[el2_dma_ctrl.scala 264:277]
|
|
wire _T_103 = _T_100 | _T_102; // @[el2_dma_ctrl.scala 264:255]
|
|
wire _T_104 = 3'h1 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 264:336]
|
|
wire _T_105 = io_iccm_dma_rvalid & _T_104; // @[el2_dma_ctrl.scala 264:329]
|
|
wire _T_106 = _T_103 | _T_105; // @[el2_dma_ctrl.scala 264:307]
|
|
wire _T_114 = _T_76 & _T_49; // @[el2_dma_ctrl.scala 264:172]
|
|
wire _T_116 = 3'h2 == RdPtr; // @[el2_dma_ctrl.scala 264:243]
|
|
wire _T_117 = _T_79 & _T_116; // @[el2_dma_ctrl.scala 264:236]
|
|
wire _T_118 = _T_114 | _T_117; // @[el2_dma_ctrl.scala 264:191]
|
|
wire _T_119 = 3'h2 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 264:284]
|
|
wire _T_120 = io_dccm_dma_rvalid & _T_119; // @[el2_dma_ctrl.scala 264:277]
|
|
wire _T_121 = _T_118 | _T_120; // @[el2_dma_ctrl.scala 264:255]
|
|
wire _T_122 = 3'h2 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 264:336]
|
|
wire _T_123 = io_iccm_dma_rvalid & _T_122; // @[el2_dma_ctrl.scala 264:329]
|
|
wire _T_124 = _T_121 | _T_123; // @[el2_dma_ctrl.scala 264:307]
|
|
wire _T_132 = _T_76 & _T_57; // @[el2_dma_ctrl.scala 264:172]
|
|
wire _T_134 = 3'h3 == RdPtr; // @[el2_dma_ctrl.scala 264:243]
|
|
wire _T_135 = _T_79 & _T_134; // @[el2_dma_ctrl.scala 264:236]
|
|
wire _T_136 = _T_132 | _T_135; // @[el2_dma_ctrl.scala 264:191]
|
|
wire _T_137 = 3'h3 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 264:284]
|
|
wire _T_138 = io_dccm_dma_rvalid & _T_137; // @[el2_dma_ctrl.scala 264:277]
|
|
wire _T_139 = _T_136 | _T_138; // @[el2_dma_ctrl.scala 264:255]
|
|
wire _T_140 = 3'h3 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 264:336]
|
|
wire _T_141 = io_iccm_dma_rvalid & _T_140; // @[el2_dma_ctrl.scala 264:329]
|
|
wire _T_142 = _T_139 | _T_141; // @[el2_dma_ctrl.scala 264:307]
|
|
wire _T_150 = _T_76 & _T_65; // @[el2_dma_ctrl.scala 264:172]
|
|
wire _T_152 = 3'h4 == RdPtr; // @[el2_dma_ctrl.scala 264:243]
|
|
wire _T_153 = _T_79 & _T_152; // @[el2_dma_ctrl.scala 264:236]
|
|
wire _T_154 = _T_150 | _T_153; // @[el2_dma_ctrl.scala 264:191]
|
|
wire _T_155 = 3'h4 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 264:284]
|
|
wire _T_156 = io_dccm_dma_rvalid & _T_155; // @[el2_dma_ctrl.scala 264:277]
|
|
wire _T_157 = _T_154 | _T_156; // @[el2_dma_ctrl.scala 264:255]
|
|
wire _T_158 = 3'h4 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 264:336]
|
|
wire _T_159 = io_iccm_dma_rvalid & _T_158; // @[el2_dma_ctrl.scala 264:329]
|
|
wire _T_160 = _T_157 | _T_159; // @[el2_dma_ctrl.scala 264:307]
|
|
wire [4:0] fifo_data_en = {_T_160,_T_142,_T_124,_T_106,_T_88}; // @[Cat.scala 29:58]
|
|
wire _T_165 = io_dma_dccm_req | io_dma_iccm_req; // @[el2_dma_ctrl.scala 266:75]
|
|
wire _T_166 = ~io_dma_mem_write; // @[el2_dma_ctrl.scala 266:96]
|
|
wire _T_167 = _T_165 & _T_166; // @[el2_dma_ctrl.scala 266:94]
|
|
wire _T_169 = _T_167 & _T_80; // @[el2_dma_ctrl.scala 266:114]
|
|
wire _T_174 = _T_167 & _T_98; // @[el2_dma_ctrl.scala 266:114]
|
|
wire _T_179 = _T_167 & _T_116; // @[el2_dma_ctrl.scala 266:114]
|
|
wire _T_184 = _T_167 & _T_134; // @[el2_dma_ctrl.scala 266:114]
|
|
wire _T_189 = _T_167 & _T_152; // @[el2_dma_ctrl.scala 266:114]
|
|
wire [4:0] fifo_pend_en = {_T_189,_T_184,_T_179,_T_174,_T_169}; // @[Cat.scala 29:58]
|
|
wire _T_1107 = _T_995 & _T_996[0]; // @[el2_dma_ctrl.scala 379:66]
|
|
wire _T_1109 = _T_1000 | dma_mem_addr_in_pic; // @[el2_dma_ctrl.scala 379:134]
|
|
wire _T_1110 = ~_T_1109; // @[el2_dma_ctrl.scala 379:88]
|
|
wire _T_1113 = dma_mem_sz_int[1:0] != 2'h2; // @[el2_dma_ctrl.scala 379:191]
|
|
wire _T_1114 = _T_1110 | _T_1113; // @[el2_dma_ctrl.scala 379:167]
|
|
wire dma_dbg_cmd_error = _T_1107 & _T_1114; // @[el2_dma_ctrl.scala 379:84]
|
|
wire _T_197 = _T_79 | dma_dbg_cmd_error; // @[el2_dma_ctrl.scala 268:114]
|
|
wire _T_199 = _T_197 & _T_80; // @[el2_dma_ctrl.scala 268:135]
|
|
wire _T_200 = io_dccm_dma_rvalid & io_dccm_dma_ecc_error; // @[el2_dma_ctrl.scala 268:177]
|
|
wire _T_202 = _T_200 & _T_83; // @[el2_dma_ctrl.scala 268:202]
|
|
wire _T_203 = _T_199 | _T_202; // @[el2_dma_ctrl.scala 268:154]
|
|
wire _T_204 = io_iccm_dma_rvalid & io_iccm_dma_ecc_error; // @[el2_dma_ctrl.scala 268:255]
|
|
wire _T_206 = _T_204 & _T_86; // @[el2_dma_ctrl.scala 268:280]
|
|
wire _T_207 = _T_203 | _T_206; // @[el2_dma_ctrl.scala 268:232]
|
|
wire _T_213 = _T_197 & _T_98; // @[el2_dma_ctrl.scala 268:135]
|
|
wire _T_216 = _T_200 & _T_101; // @[el2_dma_ctrl.scala 268:202]
|
|
wire _T_217 = _T_213 | _T_216; // @[el2_dma_ctrl.scala 268:154]
|
|
wire _T_220 = _T_204 & _T_104; // @[el2_dma_ctrl.scala 268:280]
|
|
wire _T_221 = _T_217 | _T_220; // @[el2_dma_ctrl.scala 268:232]
|
|
wire _T_227 = _T_197 & _T_116; // @[el2_dma_ctrl.scala 268:135]
|
|
wire _T_230 = _T_200 & _T_119; // @[el2_dma_ctrl.scala 268:202]
|
|
wire _T_231 = _T_227 | _T_230; // @[el2_dma_ctrl.scala 268:154]
|
|
wire _T_234 = _T_204 & _T_122; // @[el2_dma_ctrl.scala 268:280]
|
|
wire _T_235 = _T_231 | _T_234; // @[el2_dma_ctrl.scala 268:232]
|
|
wire _T_241 = _T_197 & _T_134; // @[el2_dma_ctrl.scala 268:135]
|
|
wire _T_244 = _T_200 & _T_137; // @[el2_dma_ctrl.scala 268:202]
|
|
wire _T_245 = _T_241 | _T_244; // @[el2_dma_ctrl.scala 268:154]
|
|
wire _T_248 = _T_204 & _T_140; // @[el2_dma_ctrl.scala 268:280]
|
|
wire _T_249 = _T_245 | _T_248; // @[el2_dma_ctrl.scala 268:232]
|
|
wire _T_255 = _T_197 & _T_152; // @[el2_dma_ctrl.scala 268:135]
|
|
wire _T_258 = _T_200 & _T_155; // @[el2_dma_ctrl.scala 268:202]
|
|
wire _T_259 = _T_255 | _T_258; // @[el2_dma_ctrl.scala 268:154]
|
|
wire _T_262 = _T_204 & _T_158; // @[el2_dma_ctrl.scala 268:280]
|
|
wire _T_263 = _T_259 | _T_262; // @[el2_dma_ctrl.scala 268:232]
|
|
wire [4:0] fifo_error_en = {_T_263,_T_249,_T_235,_T_221,_T_207}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_436 = {1'h0,io_dccm_dma_ecc_error}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_439 = {1'h0,io_iccm_dma_ecc_error}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_442 = {_T_197,dma_alignment_error}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_443 = _T_87 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 278:146]
|
|
wire [1:0] fifo_error_in_0 = _T_84 ? _T_436 : _T_443; // @[el2_dma_ctrl.scala 278:60]
|
|
wire _T_269 = |fifo_error_in_0; // @[el2_dma_ctrl.scala 270:83]
|
|
reg [1:0] fifo_error_0; // @[el2_dma_ctrl.scala 284:85]
|
|
wire _T_272 = |fifo_error_0; // @[el2_dma_ctrl.scala 270:125]
|
|
wire [1:0] _T_454 = _T_105 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 278:146]
|
|
wire [1:0] fifo_error_in_1 = _T_102 ? _T_436 : _T_454; // @[el2_dma_ctrl.scala 278:60]
|
|
wire _T_276 = |fifo_error_in_1; // @[el2_dma_ctrl.scala 270:83]
|
|
reg [1:0] fifo_error_1; // @[el2_dma_ctrl.scala 284:85]
|
|
wire _T_279 = |fifo_error_1; // @[el2_dma_ctrl.scala 270:125]
|
|
wire [1:0] _T_465 = _T_123 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 278:146]
|
|
wire [1:0] fifo_error_in_2 = _T_120 ? _T_436 : _T_465; // @[el2_dma_ctrl.scala 278:60]
|
|
wire _T_283 = |fifo_error_in_2; // @[el2_dma_ctrl.scala 270:83]
|
|
reg [1:0] fifo_error_2; // @[el2_dma_ctrl.scala 284:85]
|
|
wire _T_286 = |fifo_error_2; // @[el2_dma_ctrl.scala 270:125]
|
|
wire [1:0] _T_476 = _T_141 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 278:146]
|
|
wire [1:0] fifo_error_in_3 = _T_138 ? _T_436 : _T_476; // @[el2_dma_ctrl.scala 278:60]
|
|
wire _T_290 = |fifo_error_in_3; // @[el2_dma_ctrl.scala 270:83]
|
|
reg [1:0] fifo_error_3; // @[el2_dma_ctrl.scala 284:85]
|
|
wire _T_293 = |fifo_error_3; // @[el2_dma_ctrl.scala 270:125]
|
|
wire [1:0] _T_487 = _T_159 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 278:146]
|
|
wire [1:0] fifo_error_in_4 = _T_156 ? _T_436 : _T_487; // @[el2_dma_ctrl.scala 278:60]
|
|
wire _T_297 = |fifo_error_in_4; // @[el2_dma_ctrl.scala 270:83]
|
|
reg [1:0] fifo_error_4; // @[el2_dma_ctrl.scala 284:85]
|
|
wire _T_300 = |fifo_error_4; // @[el2_dma_ctrl.scala 270:125]
|
|
wire _T_309 = _T_272 | fifo_error_en[0]; // @[el2_dma_ctrl.scala 272:78]
|
|
wire _T_311 = _T_165 & io_dma_mem_write; // @[el2_dma_ctrl.scala 272:136]
|
|
wire _T_312 = _T_309 | _T_311; // @[el2_dma_ctrl.scala 272:97]
|
|
wire _T_314 = _T_312 & _T_80; // @[el2_dma_ctrl.scala 272:157]
|
|
wire _T_317 = _T_314 | _T_84; // @[el2_dma_ctrl.scala 272:176]
|
|
wire _T_320 = _T_317 | _T_87; // @[el2_dma_ctrl.scala 272:228]
|
|
wire _T_323 = _T_279 | fifo_error_en[1]; // @[el2_dma_ctrl.scala 272:78]
|
|
wire _T_326 = _T_323 | _T_311; // @[el2_dma_ctrl.scala 272:97]
|
|
wire _T_328 = _T_326 & _T_98; // @[el2_dma_ctrl.scala 272:157]
|
|
wire _T_331 = _T_328 | _T_102; // @[el2_dma_ctrl.scala 272:176]
|
|
wire _T_334 = _T_331 | _T_105; // @[el2_dma_ctrl.scala 272:228]
|
|
wire _T_337 = _T_286 | fifo_error_en[2]; // @[el2_dma_ctrl.scala 272:78]
|
|
wire _T_340 = _T_337 | _T_311; // @[el2_dma_ctrl.scala 272:97]
|
|
wire _T_342 = _T_340 & _T_116; // @[el2_dma_ctrl.scala 272:157]
|
|
wire _T_345 = _T_342 | _T_120; // @[el2_dma_ctrl.scala 272:176]
|
|
wire _T_348 = _T_345 | _T_123; // @[el2_dma_ctrl.scala 272:228]
|
|
wire _T_351 = _T_293 | fifo_error_en[3]; // @[el2_dma_ctrl.scala 272:78]
|
|
wire _T_354 = _T_351 | _T_311; // @[el2_dma_ctrl.scala 272:97]
|
|
wire _T_356 = _T_354 & _T_134; // @[el2_dma_ctrl.scala 272:157]
|
|
wire _T_359 = _T_356 | _T_138; // @[el2_dma_ctrl.scala 272:176]
|
|
wire _T_362 = _T_359 | _T_141; // @[el2_dma_ctrl.scala 272:228]
|
|
wire _T_365 = _T_300 | fifo_error_en[4]; // @[el2_dma_ctrl.scala 272:78]
|
|
wire _T_368 = _T_365 | _T_311; // @[el2_dma_ctrl.scala 272:97]
|
|
wire _T_370 = _T_368 & _T_152; // @[el2_dma_ctrl.scala 272:157]
|
|
wire _T_373 = _T_370 | _T_156; // @[el2_dma_ctrl.scala 272:176]
|
|
wire _T_376 = _T_373 | _T_159; // @[el2_dma_ctrl.scala 272:228]
|
|
wire [4:0] fifo_done_en = {_T_376,_T_362,_T_348,_T_334,_T_320}; // @[Cat.scala 29:58]
|
|
wire _T_383 = fifo_done_en[0] | fifo_done[0]; // @[el2_dma_ctrl.scala 274:75]
|
|
wire _T_384 = _T_383 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 274:91]
|
|
wire _T_387 = fifo_done_en[1] | fifo_done[1]; // @[el2_dma_ctrl.scala 274:75]
|
|
wire _T_388 = _T_387 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 274:91]
|
|
wire _T_391 = fifo_done_en[2] | fifo_done[2]; // @[el2_dma_ctrl.scala 274:75]
|
|
wire _T_392 = _T_391 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 274:91]
|
|
wire _T_395 = fifo_done_en[3] | fifo_done[3]; // @[el2_dma_ctrl.scala 274:75]
|
|
wire _T_396 = _T_395 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 274:91]
|
|
wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[el2_dma_ctrl.scala 274:75]
|
|
wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 274:91]
|
|
wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58]
|
|
wire _T_1265 = io_dma_axi_bvalid & io_dma_axi_bready; // @[el2_dma_ctrl.scala 552:60]
|
|
wire _T_1266 = io_dma_axi_rvalid & io_dma_axi_rready; // @[el2_dma_ctrl.scala 552:102]
|
|
wire bus_rsp_sent = _T_1265 | _T_1266; // @[el2_dma_ctrl.scala 552:81]
|
|
wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 276:99]
|
|
wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[el2_dma_ctrl.scala 276:120]
|
|
reg [2:0] RspPtr; // @[Reg.scala 27:20]
|
|
wire _T_408 = 3'h0 == RspPtr; // @[el2_dma_ctrl.scala 276:150]
|
|
wire _T_409 = _T_407 & _T_408; // @[el2_dma_ctrl.scala 276:143]
|
|
wire _T_413 = 3'h1 == RspPtr; // @[el2_dma_ctrl.scala 276:150]
|
|
wire _T_414 = _T_407 & _T_413; // @[el2_dma_ctrl.scala 276:143]
|
|
wire _T_418 = 3'h2 == RspPtr; // @[el2_dma_ctrl.scala 276:150]
|
|
wire _T_419 = _T_407 & _T_418; // @[el2_dma_ctrl.scala 276:143]
|
|
wire _T_423 = 3'h3 == RspPtr; // @[el2_dma_ctrl.scala 276:150]
|
|
wire _T_424 = _T_407 & _T_423; // @[el2_dma_ctrl.scala 276:143]
|
|
wire _T_428 = 3'h4 == RspPtr; // @[el2_dma_ctrl.scala 276:150]
|
|
wire _T_429 = _T_407 & _T_428; // @[el2_dma_ctrl.scala 276:143]
|
|
wire [4:0] fifo_reset = {_T_429,_T_424,_T_419,_T_414,_T_409}; // @[Cat.scala 29:58]
|
|
wire _T_491 = fifo_error_en[0] & _T_269; // @[el2_dma_ctrl.scala 280:77]
|
|
wire [63:0] _T_493 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_498 = {io_dbg_cmd_wrdata,io_dbg_cmd_wrdata}; // @[Cat.scala 29:58]
|
|
reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16]
|
|
wire [63:0] _T_500 = io_dbg_cmd_valid ? _T_498 : wrbuf_data; // @[el2_dma_ctrl.scala 280:284]
|
|
wire _T_506 = fifo_error_en[1] & _T_276; // @[el2_dma_ctrl.scala 280:77]
|
|
wire [63:0] _T_508 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58]
|
|
wire _T_521 = fifo_error_en[2] & _T_283; // @[el2_dma_ctrl.scala 280:77]
|
|
wire [63:0] _T_523 = {32'h0,fifo_addr_2}; // @[Cat.scala 29:58]
|
|
wire _T_536 = fifo_error_en[3] & _T_290; // @[el2_dma_ctrl.scala 280:77]
|
|
wire [63:0] _T_538 = {32'h0,fifo_addr_3}; // @[Cat.scala 29:58]
|
|
wire _T_551 = fifo_error_en[4] & _T_297; // @[el2_dma_ctrl.scala 280:77]
|
|
wire [63:0] _T_553 = {32'h0,fifo_addr_4}; // @[Cat.scala 29:58]
|
|
wire _T_566 = fifo_cmd_en[0] | fifo_valid[0]; // @[el2_dma_ctrl.scala 282:86]
|
|
wire _T_568 = ~fifo_reset[0]; // @[el2_dma_ctrl.scala 282:125]
|
|
wire _T_573 = fifo_cmd_en[1] | fifo_valid[1]; // @[el2_dma_ctrl.scala 282:86]
|
|
wire _T_575 = ~fifo_reset[1]; // @[el2_dma_ctrl.scala 282:125]
|
|
wire _T_580 = fifo_cmd_en[2] | fifo_valid[2]; // @[el2_dma_ctrl.scala 282:86]
|
|
wire _T_582 = ~fifo_reset[2]; // @[el2_dma_ctrl.scala 282:125]
|
|
wire _T_587 = fifo_cmd_en[3] | fifo_valid[3]; // @[el2_dma_ctrl.scala 282:86]
|
|
wire _T_589 = ~fifo_reset[3]; // @[el2_dma_ctrl.scala 282:125]
|
|
wire _T_594 = fifo_cmd_en[4] | fifo_valid[4]; // @[el2_dma_ctrl.scala 282:86]
|
|
wire _T_596 = ~fifo_reset[4]; // @[el2_dma_ctrl.scala 282:125]
|
|
wire [1:0] _T_605 = fifo_error_en[0] ? fifo_error_in_0 : fifo_error_0; // @[el2_dma_ctrl.scala 284:89]
|
|
wire [1:0] _T_609 = _T_568 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_614 = fifo_error_en[1] ? fifo_error_in_1 : fifo_error_1; // @[el2_dma_ctrl.scala 284:89]
|
|
wire [1:0] _T_618 = _T_575 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_623 = fifo_error_en[2] ? fifo_error_in_2 : fifo_error_2; // @[el2_dma_ctrl.scala 284:89]
|
|
wire [1:0] _T_627 = _T_582 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_632 = fifo_error_en[3] ? fifo_error_in_3 : fifo_error_3; // @[el2_dma_ctrl.scala 284:89]
|
|
wire [1:0] _T_636 = _T_589 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_641 = fifo_error_en[4] ? fifo_error_in_4 : fifo_error_4; // @[el2_dma_ctrl.scala 284:89]
|
|
wire [1:0] _T_645 = _T_596 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
reg _T_721; // @[el2_dma_ctrl.scala 288:89]
|
|
reg _T_714; // @[el2_dma_ctrl.scala 288:89]
|
|
reg _T_707; // @[el2_dma_ctrl.scala 288:89]
|
|
reg _T_700; // @[el2_dma_ctrl.scala 288:89]
|
|
reg _T_693; // @[el2_dma_ctrl.scala 288:89]
|
|
wire [4:0] fifo_rpend = {_T_721,_T_714,_T_707,_T_700,_T_693}; // @[Cat.scala 29:58]
|
|
wire _T_689 = fifo_pend_en[0] | fifo_rpend[0]; // @[el2_dma_ctrl.scala 288:93]
|
|
wire _T_696 = fifo_pend_en[1] | fifo_rpend[1]; // @[el2_dma_ctrl.scala 288:93]
|
|
wire _T_703 = fifo_pend_en[2] | fifo_rpend[2]; // @[el2_dma_ctrl.scala 288:93]
|
|
wire _T_710 = fifo_pend_en[3] | fifo_rpend[3]; // @[el2_dma_ctrl.scala 288:93]
|
|
wire _T_717 = fifo_pend_en[4] | fifo_rpend[4]; // @[el2_dma_ctrl.scala 288:93]
|
|
reg _T_799; // @[el2_dma_ctrl.scala 292:89]
|
|
reg _T_792; // @[el2_dma_ctrl.scala 292:89]
|
|
reg _T_785; // @[el2_dma_ctrl.scala 292:89]
|
|
reg _T_778; // @[el2_dma_ctrl.scala 292:89]
|
|
reg _T_771; // @[el2_dma_ctrl.scala 292:89]
|
|
wire [4:0] fifo_done_bus = {_T_799,_T_792,_T_785,_T_778,_T_771}; // @[Cat.scala 29:58]
|
|
wire _T_767 = fifo_done_bus_en[0] | fifo_done_bus[0]; // @[el2_dma_ctrl.scala 292:93]
|
|
wire _T_774 = fifo_done_bus_en[1] | fifo_done_bus[1]; // @[el2_dma_ctrl.scala 292:93]
|
|
wire _T_781 = fifo_done_bus_en[2] | fifo_done_bus[2]; // @[el2_dma_ctrl.scala 292:93]
|
|
wire _T_788 = fifo_done_bus_en[3] | fifo_done_bus[3]; // @[el2_dma_ctrl.scala 292:93]
|
|
wire _T_795 = fifo_done_bus_en[4] | fifo_done_bus[4]; // @[el2_dma_ctrl.scala 292:93]
|
|
wire [7:0] fifo_byteen_in = _T_20[7:0]; // @[el2_dma_ctrl.scala 251:28]
|
|
reg _T_850; // @[Reg.scala 27:20]
|
|
reg _T_852; // @[Reg.scala 27:20]
|
|
reg _T_854; // @[Reg.scala 27:20]
|
|
reg _T_856; // @[Reg.scala 27:20]
|
|
reg _T_858; // @[Reg.scala 27:20]
|
|
wire [4:0] fifo_write = {_T_858,_T_856,_T_854,_T_852,_T_850}; // @[Cat.scala 29:58]
|
|
reg [63:0] fifo_data_0; // @[el2_lib.scala 514:16]
|
|
reg [63:0] fifo_data_1; // @[el2_lib.scala 514:16]
|
|
reg [63:0] fifo_data_2; // @[el2_lib.scala 514:16]
|
|
reg [63:0] fifo_data_3; // @[el2_lib.scala 514:16]
|
|
reg [63:0] fifo_data_4; // @[el2_lib.scala 514:16]
|
|
reg fifo_tag_0; // @[Reg.scala 27:20]
|
|
reg wrbuf_tag; // @[Reg.scala 27:20]
|
|
reg rdbuf_tag; // @[Reg.scala 27:20]
|
|
wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[el2_dma_ctrl.scala 517:43]
|
|
reg fifo_tag_1; // @[Reg.scala 27:20]
|
|
reg fifo_tag_2; // @[Reg.scala 27:20]
|
|
reg fifo_tag_3; // @[Reg.scala 27:20]
|
|
reg fifo_tag_4; // @[Reg.scala 27:20]
|
|
wire _T_931 = WrPtr == 3'h4; // @[el2_dma_ctrl.scala 316:30]
|
|
wire [2:0] _T_934 = WrPtr + 3'h1; // @[el2_dma_ctrl.scala 316:76]
|
|
wire _T_936 = RdPtr == 3'h4; // @[el2_dma_ctrl.scala 318:30]
|
|
wire [2:0] _T_939 = RdPtr + 3'h1; // @[el2_dma_ctrl.scala 318:76]
|
|
wire _T_941 = RspPtr == 3'h4; // @[el2_dma_ctrl.scala 320:31]
|
|
wire [2:0] _T_944 = RspPtr + 3'h1; // @[el2_dma_ctrl.scala 320:78]
|
|
wire WrPtrEn = |fifo_cmd_en; // @[el2_dma_ctrl.scala 322:30]
|
|
wire RdPtrEn = _T_165 | _T_197; // @[el2_dma_ctrl.scala 324:53]
|
|
wire RspPtrEn = io_dma_dbg_cmd_done | _T_406; // @[el2_dma_ctrl.scala 326:39]
|
|
wire [3:0] _T_966 = {3'h0,fifo_valid[0]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_969 = {3'h0,fifo_valid[1]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_972 = {3'h0,fifo_valid[2]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_975 = {3'h0,fifo_valid[3]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_978 = {3'h0,fifo_valid[4]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_980 = _T_966 + _T_969; // @[el2_dma_ctrl.scala 349:102]
|
|
wire [3:0] _T_982 = _T_980 + _T_972; // @[el2_dma_ctrl.scala 349:102]
|
|
wire [3:0] _T_984 = _T_982 + _T_975; // @[el2_dma_ctrl.scala 349:102]
|
|
wire [3:0] num_fifo_vld_tmp2 = _T_984 + _T_978; // @[el2_dma_ctrl.scala 349:102]
|
|
wire _T_1123 = |fifo_valid; // @[el2_dma_ctrl.scala 388:30]
|
|
wire fifo_empty = ~_T_1123; // @[el2_dma_ctrl.scala 388:17]
|
|
wire [4:0] _T_1086 = fifo_valid >> RspPtr; // @[el2_dma_ctrl.scala 375:39]
|
|
wire [4:0] _T_1088 = fifo_dbg >> RspPtr; // @[el2_dma_ctrl.scala 375:58]
|
|
wire _T_1090 = _T_1086[0] & _T_1088[0]; // @[el2_dma_ctrl.scala 375:48]
|
|
wire [4:0] _T_1091 = fifo_done >> RspPtr; // @[el2_dma_ctrl.scala 375:78]
|
|
wire [31:0] _GEN_44 = 3'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[el2_dma_ctrl.scala 376:49]
|
|
wire [31:0] _GEN_45 = 3'h2 == RspPtr ? fifo_addr_2 : _GEN_44; // @[el2_dma_ctrl.scala 376:49]
|
|
wire [31:0] _GEN_46 = 3'h3 == RspPtr ? fifo_addr_3 : _GEN_45; // @[el2_dma_ctrl.scala 376:49]
|
|
wire [31:0] _GEN_47 = 3'h4 == RspPtr ? fifo_addr_4 : _GEN_46; // @[el2_dma_ctrl.scala 376:49]
|
|
wire [63:0] _GEN_49 = 3'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[el2_dma_ctrl.scala 376:71]
|
|
wire [63:0] _GEN_50 = 3'h2 == RspPtr ? fifo_data_2 : _GEN_49; // @[el2_dma_ctrl.scala 376:71]
|
|
wire [63:0] _GEN_51 = 3'h3 == RspPtr ? fifo_data_3 : _GEN_50; // @[el2_dma_ctrl.scala 376:71]
|
|
wire [63:0] _GEN_52 = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[el2_dma_ctrl.scala 376:71]
|
|
wire [1:0] _GEN_54 = 3'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[el2_dma_ctrl.scala 377:47]
|
|
wire [1:0] _GEN_55 = 3'h2 == RspPtr ? fifo_error_2 : _GEN_54; // @[el2_dma_ctrl.scala 377:47]
|
|
wire [1:0] _GEN_56 = 3'h3 == RspPtr ? fifo_error_3 : _GEN_55; // @[el2_dma_ctrl.scala 377:47]
|
|
wire [1:0] _GEN_57 = 3'h4 == RspPtr ? fifo_error_4 : _GEN_56; // @[el2_dma_ctrl.scala 377:47]
|
|
wire _T_1116 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[el2_dma_ctrl.scala 383:64]
|
|
wire [4:0] _T_1145 = fifo_rpend >> RdPtr; // @[el2_dma_ctrl.scala 401:54]
|
|
wire _T_1147 = ~_T_1145[0]; // @[el2_dma_ctrl.scala 401:43]
|
|
wire _T_1148 = _T_990[0] & _T_1147; // @[el2_dma_ctrl.scala 401:41]
|
|
wire _T_1152 = _T_1148 & _T_994; // @[el2_dma_ctrl.scala 401:62]
|
|
wire _T_1155 = ~_T_197; // @[el2_dma_ctrl.scala 401:84]
|
|
wire dma_mem_req = _T_1152 & _T_1155; // @[el2_dma_ctrl.scala 401:82]
|
|
wire _T_1117 = dma_mem_req & _T_1116; // @[el2_dma_ctrl.scala 383:40]
|
|
reg [2:0] dma_nack_count; // @[Reg.scala 27:20]
|
|
wire _T_1118 = dma_nack_count >= io_dec_tlu_dma_qos_prty; // @[el2_dma_ctrl.scala 383:105]
|
|
wire _T_1120 = dma_mem_req & dma_mem_addr_in_iccm; // @[el2_dma_ctrl.scala 384:40]
|
|
wire _T_1127 = ~_T_165; // @[el2_dma_ctrl.scala 393:77]
|
|
wire [2:0] _T_1129 = _T_1127 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_1131 = _T_1129 & dma_nack_count; // @[el2_dma_ctrl.scala 393:115]
|
|
wire _T_1135 = dma_mem_req & _T_1127; // @[el2_dma_ctrl.scala 393:163]
|
|
wire [2:0] _T_1138 = dma_nack_count + 3'h1; // @[el2_dma_ctrl.scala 393:224]
|
|
wire _T_1164 = io_dma_mem_write & _T_1076; // @[el2_dma_ctrl.scala 407:44]
|
|
wire [31:0] _T_1168 = {dma_mem_addr_int[31:3],1'h1,dma_mem_addr_int[1:0]}; // @[Cat.scala 29:58]
|
|
wire _T_1176 = io_dma_mem_write & _T_1077; // @[el2_dma_ctrl.scala 408:44]
|
|
wire [4:0] _T_1179 = fifo_write >> RdPtr; // @[el2_dma_ctrl.scala 410:33]
|
|
wire [63:0] _GEN_75 = 3'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[el2_dma_ctrl.scala 411:20]
|
|
wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[el2_dma_ctrl.scala 411:20]
|
|
wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[el2_dma_ctrl.scala 411:20]
|
|
reg dma_dbg_cmd_done_q; // @[el2_dma_ctrl.scala 431:12]
|
|
wire _T_1192 = bus_cmd_valid & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 436:44]
|
|
wire _T_1193 = _T_1192 | io_dbg_cmd_valid; // @[el2_dma_ctrl.scala 436:65]
|
|
wire bus_rsp_valid = io_dma_axi_bvalid | io_dma_axi_rvalid; // @[el2_dma_ctrl.scala 551:59]
|
|
wire _T_1194 = bus_cmd_valid | bus_rsp_valid; // @[el2_dma_ctrl.scala 437:44]
|
|
wire _T_1195 = _T_1194 | io_dbg_cmd_valid; // @[el2_dma_ctrl.scala 437:60]
|
|
wire _T_1196 = _T_1195 | io_dma_dbg_cmd_done; // @[el2_dma_ctrl.scala 437:79]
|
|
wire _T_1197 = _T_1196 | dma_dbg_cmd_done_q; // @[el2_dma_ctrl.scala 437:101]
|
|
wire _T_1199 = _T_1197 | _T_1123; // @[el2_dma_ctrl.scala 437:122]
|
|
wire wrbuf_en = io_dma_axi_awvalid & io_dma_axi_awready; // @[el2_dma_ctrl.scala 459:46]
|
|
wire wrbuf_data_en = io_dma_axi_wvalid & io_dma_axi_wready; // @[el2_dma_ctrl.scala 460:45]
|
|
wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[el2_dma_ctrl.scala 461:40]
|
|
wire _T_1201 = ~wrbuf_en; // @[el2_dma_ctrl.scala 462:51]
|
|
wire wrbuf_rst = wrbuf_cmd_sent & _T_1201; // @[el2_dma_ctrl.scala 462:49]
|
|
wire _T_1203 = ~wrbuf_data_en; // @[el2_dma_ctrl.scala 463:51]
|
|
wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1203; // @[el2_dma_ctrl.scala 463:49]
|
|
wire _T_1204 = wrbuf_en | wrbuf_vld; // @[el2_dma_ctrl.scala 465:63]
|
|
wire _T_1205 = ~wrbuf_rst; // @[el2_dma_ctrl.scala 465:92]
|
|
wire _T_1208 = wrbuf_data_en | wrbuf_data_vld; // @[el2_dma_ctrl.scala 467:63]
|
|
wire _T_1209 = ~wrbuf_data_rst; // @[el2_dma_ctrl.scala 467:102]
|
|
wire rdbuf_en = io_dma_axi_arvalid & io_dma_axi_arready; // @[el2_dma_ctrl.scala 487:58]
|
|
wire _T_1214 = ~axi_mstr_sel; // @[el2_dma_ctrl.scala 488:44]
|
|
wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1214; // @[el2_dma_ctrl.scala 488:42]
|
|
wire _T_1216 = ~rdbuf_en; // @[el2_dma_ctrl.scala 489:63]
|
|
wire rdbuf_rst = rdbuf_cmd_sent & _T_1216; // @[el2_dma_ctrl.scala 489:61]
|
|
wire _T_1217 = rdbuf_en | rdbuf_vld; // @[el2_dma_ctrl.scala 491:51]
|
|
wire _T_1218 = ~rdbuf_rst; // @[el2_dma_ctrl.scala 491:80]
|
|
wire _T_1222 = ~wrbuf_cmd_sent; // @[el2_dma_ctrl.scala 503:44]
|
|
wire _T_1223 = wrbuf_vld & _T_1222; // @[el2_dma_ctrl.scala 503:42]
|
|
wire _T_1226 = wrbuf_data_vld & _T_1222; // @[el2_dma_ctrl.scala 504:47]
|
|
wire _T_1228 = ~rdbuf_cmd_sent; // @[el2_dma_ctrl.scala 505:44]
|
|
wire _T_1229 = rdbuf_vld & _T_1228; // @[el2_dma_ctrl.scala 505:42]
|
|
wire axi_mstr_prty_in = ~axi_mstr_priority; // @[el2_dma_ctrl.scala 524:27]
|
|
wire _T_1251 = ~_T_1088[0]; // @[el2_dma_ctrl.scala 531:50]
|
|
wire _T_1252 = _T_1086[0] & _T_1251; // @[el2_dma_ctrl.scala 531:48]
|
|
wire [4:0] _T_1253 = fifo_done_bus >> RspPtr; // @[el2_dma_ctrl.scala 531:83]
|
|
wire axi_rsp_valid = _T_1252 & _T_1253[0]; // @[el2_dma_ctrl.scala 531:68]
|
|
wire [4:0] _T_1255 = fifo_write >> RspPtr; // @[el2_dma_ctrl.scala 533:39]
|
|
wire axi_rsp_write = _T_1255[0]; // @[el2_dma_ctrl.scala 533:39]
|
|
wire [1:0] _T_1258 = _GEN_57[1] ? 2'h3 : 2'h0; // @[el2_dma_ctrl.scala 534:64]
|
|
wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[el2_dma_ctrl.scala 542:33]
|
|
wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[el2_dma_ctrl.scala 542:33]
|
|
wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[el2_dma_ctrl.scala 542:33]
|
|
wire _T_1261 = ~axi_rsp_write; // @[el2_dma_ctrl.scala 544:46]
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en),
|
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en),
|
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en),
|
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en),
|
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en),
|
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en),
|
|
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_8_io_l1clk),
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en),
|
|
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_9_io_l1clk),
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en),
|
|
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
|
);
|
|
rvclkhdr dma_buffer_c1cgc ( // @[el2_dma_ctrl.scala 439:32]
|
|
.io_l1clk(dma_buffer_c1cgc_io_l1clk),
|
|
.io_clk(dma_buffer_c1cgc_io_clk),
|
|
.io_en(dma_buffer_c1cgc_io_en),
|
|
.io_scan_mode(dma_buffer_c1cgc_io_scan_mode)
|
|
);
|
|
rvclkhdr dma_free_cgc ( // @[el2_dma_ctrl.scala 445:28]
|
|
.io_l1clk(dma_free_cgc_io_l1clk),
|
|
.io_clk(dma_free_cgc_io_clk),
|
|
.io_en(dma_free_cgc_io_en),
|
|
.io_scan_mode(dma_free_cgc_io_scan_mode)
|
|
);
|
|
rvclkhdr dma_bus_cgc ( // @[el2_dma_ctrl.scala 451:27]
|
|
.io_l1clk(dma_bus_cgc_io_l1clk),
|
|
.io_clk(dma_bus_cgc_io_clk),
|
|
.io_en(dma_bus_cgc_io_en),
|
|
.io_scan_mode(dma_bus_cgc_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_10_io_l1clk),
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en),
|
|
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_11_io_l1clk),
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en),
|
|
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23]
|
|
.io_l1clk(rvclkhdr_12_io_l1clk),
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en),
|
|
.io_scan_mode(rvclkhdr_12_io_scan_mode)
|
|
);
|
|
assign io_dma_dbg_ready = fifo_empty & dbg_dma_bubble_bus; // @[el2_dma_ctrl.scala 374:25]
|
|
assign io_dma_dbg_cmd_done = _T_1090 & _T_1091[0]; // @[el2_dma_ctrl.scala 375:25]
|
|
assign io_dma_dbg_cmd_fail = |_GEN_57; // @[el2_dma_ctrl.scala 377:25]
|
|
assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[el2_dma_ctrl.scala 376:25]
|
|
assign io_dma_dccm_req = _T_1117 & io_dccm_ready; // @[el2_dma_ctrl.scala 402:20]
|
|
assign io_dma_iccm_req = _T_1120 & io_iccm_ready; // @[el2_dma_ctrl.scala 403:20]
|
|
assign io_dma_mem_tag = RdPtr; // @[el2_dma_ctrl.scala 404:20]
|
|
assign io_dma_mem_addr = _T_1164 ? _T_1168 : dma_mem_addr_int; // @[el2_dma_ctrl.scala 407:20]
|
|
assign io_dma_mem_sz = _T_1176 ? 3'h2 : dma_mem_sz_int; // @[el2_dma_ctrl.scala 408:20]
|
|
assign io_dma_mem_write = _T_1179[0]; // @[el2_dma_ctrl.scala 410:20]
|
|
assign io_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[el2_dma_ctrl.scala 411:20]
|
|
assign io_dma_dccm_stall_any = _T_1117 & _T_1118; // @[el2_dma_ctrl.scala 383:25]
|
|
assign io_dma_iccm_stall_any = _T_1120 & _T_1118; // @[el2_dma_ctrl.scala 384:25]
|
|
assign io_dma_pmu_dccm_read = io_dma_dccm_req & _T_166; // @[el2_dma_ctrl.scala 415:26]
|
|
assign io_dma_pmu_dccm_write = io_dma_dccm_req & io_dma_mem_write; // @[el2_dma_ctrl.scala 416:26]
|
|
assign io_dma_pmu_any_read = _T_165 & _T_166; // @[el2_dma_ctrl.scala 417:26]
|
|
assign io_dma_pmu_any_write = _T_165 & io_dma_mem_write; // @[el2_dma_ctrl.scala 418:26]
|
|
assign io_dma_axi_awready = ~_T_1223; // @[el2_dma_ctrl.scala 503:27]
|
|
assign io_dma_axi_wready = ~_T_1226; // @[el2_dma_ctrl.scala 504:27]
|
|
assign io_dma_axi_bvalid = axi_rsp_valid & axi_rsp_write; // @[el2_dma_ctrl.scala 540:27]
|
|
assign io_dma_axi_bresp = _GEN_57[0] ? 2'h2 : _T_1258; // @[el2_dma_ctrl.scala 541:33]
|
|
assign io_dma_axi_bid = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[el2_dma_ctrl.scala 542:33]
|
|
assign io_dma_axi_arready = ~_T_1229; // @[el2_dma_ctrl.scala 505:27]
|
|
assign io_dma_axi_rvalid = axi_rsp_valid & _T_1261; // @[el2_dma_ctrl.scala 544:27]
|
|
assign io_dma_axi_rid = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[el2_dma_ctrl.scala 548:37]
|
|
assign io_dma_axi_rdata = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[el2_dma_ctrl.scala 546:35]
|
|
assign io_dma_axi_rresp = _GEN_57[0] ? 2'h2 : _T_1258; // @[el2_dma_ctrl.scala 545:33]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_1_io_en = fifo_cmd_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_2_io_en = fifo_cmd_en[2]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_3_io_en = fifo_cmd_en[3]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_4_io_en = fifo_cmd_en[4]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_5_io_en = fifo_data_en[0]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_6_io_en = fifo_data_en[1]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_7_io_en = fifo_data_en[2]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_8_io_en = fifo_data_en[3]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign dma_buffer_c1cgc_io_clk = clock; // @[el2_dma_ctrl.scala 442:33]
|
|
assign dma_buffer_c1cgc_io_en = _T_1193 | io_clk_override; // @[el2_dma_ctrl.scala 440:33]
|
|
assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[el2_dma_ctrl.scala 441:33]
|
|
assign dma_free_cgc_io_clk = clock; // @[el2_dma_ctrl.scala 448:29]
|
|
assign dma_free_cgc_io_en = _T_1199 | io_clk_override; // @[el2_dma_ctrl.scala 446:29]
|
|
assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[el2_dma_ctrl.scala 447:29]
|
|
assign dma_bus_cgc_io_clk = clock; // @[el2_dma_ctrl.scala 454:28]
|
|
assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 452:28]
|
|
assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[el2_dma_ctrl.scala 453:28]
|
|
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_11_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18]
|
|
assign rvclkhdr_12_io_en = rdbuf_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17]
|
|
assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
RdPtr = _RAND_0[2:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
fifo_addr_4 = _RAND_1[31:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
fifo_addr_3 = _RAND_2[31:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
fifo_addr_2 = _RAND_3[31:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
fifo_addr_1 = _RAND_4[31:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
fifo_addr_0 = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
wrbuf_vld = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
wrbuf_data_vld = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
rdbuf_vld = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
axi_mstr_priority = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
wrbuf_addr = _RAND_10[31:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
rdbuf_addr = _RAND_11[31:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
wrbuf_byteen = _RAND_12[7:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
wrbuf_sz = _RAND_13[2:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
rdbuf_sz = _RAND_14[2:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
fifo_full = _RAND_15[0:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
dbg_dma_bubble_bus = _RAND_16[0:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
WrPtr = _RAND_17[2:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
_T_598 = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
_T_591 = _RAND_19[0:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
_T_584 = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
_T_577 = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
_T_570 = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
_T_760 = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
_T_753 = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
_T_746 = _RAND_25[0:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
_T_739 = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
_T_732 = _RAND_27[0:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
_T_886 = _RAND_28[0:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
_T_884 = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
_T_882 = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
_T_880 = _RAND_31[0:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
_T_878 = _RAND_32[0:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
fifo_sz_4 = _RAND_33[2:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
fifo_sz_3 = _RAND_34[2:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
fifo_sz_2 = _RAND_35[2:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
fifo_sz_1 = _RAND_36[2:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
fifo_sz_0 = _RAND_37[2:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
fifo_byteen_4 = _RAND_38[7:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
fifo_byteen_3 = _RAND_39[7:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
fifo_byteen_2 = _RAND_40[7:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
fifo_byteen_1 = _RAND_41[7:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
fifo_byteen_0 = _RAND_42[7:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
fifo_error_0 = _RAND_43[1:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
fifo_error_1 = _RAND_44[1:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
fifo_error_2 = _RAND_45[1:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
fifo_error_3 = _RAND_46[1:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
fifo_error_4 = _RAND_47[1:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
RspPtr = _RAND_48[2:0];
|
|
_RAND_49 = {2{`RANDOM}};
|
|
wrbuf_data = _RAND_49[63:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
_T_721 = _RAND_50[0:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
_T_714 = _RAND_51[0:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
_T_707 = _RAND_52[0:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
_T_700 = _RAND_53[0:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
_T_693 = _RAND_54[0:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
_T_799 = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
_T_792 = _RAND_56[0:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
_T_785 = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
_T_778 = _RAND_58[0:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
_T_771 = _RAND_59[0:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
_T_850 = _RAND_60[0:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
_T_852 = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
_T_854 = _RAND_62[0:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
_T_856 = _RAND_63[0:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
_T_858 = _RAND_64[0:0];
|
|
_RAND_65 = {2{`RANDOM}};
|
|
fifo_data_0 = _RAND_65[63:0];
|
|
_RAND_66 = {2{`RANDOM}};
|
|
fifo_data_1 = _RAND_66[63:0];
|
|
_RAND_67 = {2{`RANDOM}};
|
|
fifo_data_2 = _RAND_67[63:0];
|
|
_RAND_68 = {2{`RANDOM}};
|
|
fifo_data_3 = _RAND_68[63:0];
|
|
_RAND_69 = {2{`RANDOM}};
|
|
fifo_data_4 = _RAND_69[63:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
fifo_tag_0 = _RAND_70[0:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
wrbuf_tag = _RAND_71[0:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
rdbuf_tag = _RAND_72[0:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
fifo_tag_1 = _RAND_73[0:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
fifo_tag_2 = _RAND_74[0:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
fifo_tag_3 = _RAND_75[0:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
fifo_tag_4 = _RAND_76[0:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
dma_nack_count = _RAND_77[2:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
dma_dbg_cmd_done_q = _RAND_78[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
RdPtr = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_4 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_vld = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_data_vld = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
rdbuf_vld = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
axi_mstr_priority = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_addr = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rdbuf_addr = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_byteen = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_sz = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
rdbuf_sz = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_full = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dbg_dma_bubble_bus = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
WrPtr = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_598 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_591 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_584 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_577 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_570 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_760 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_753 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_746 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_739 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_732 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_886 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_884 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_882 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_880 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_878 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_4 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_3 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_2 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_1 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_0 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_4 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_3 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_2 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_1 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_0 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_4 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
RspPtr = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_data = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_721 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_714 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_707 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_700 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_693 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_799 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_792 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_785 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_778 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_771 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_850 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_852 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_854 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_856 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_858 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_0 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_1 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_2 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_3 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_4 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_tag = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
rdbuf_tag = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_nack_count = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_dbg_cmd_done_q = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
RdPtr <= 3'h0;
|
|
end else if (RdPtrEn) begin
|
|
if (_T_936) begin
|
|
RdPtr <= 3'h0;
|
|
end else begin
|
|
RdPtr <= _T_939;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_4 <= 32'h0;
|
|
end else if (io_dbg_cmd_valid) begin
|
|
fifo_addr_4 <= io_dbg_cmd_addr;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_addr_4 <= wrbuf_addr;
|
|
end else begin
|
|
fifo_addr_4 <= rdbuf_addr;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_3 <= 32'h0;
|
|
end else if (io_dbg_cmd_valid) begin
|
|
fifo_addr_3 <= io_dbg_cmd_addr;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_addr_3 <= wrbuf_addr;
|
|
end else begin
|
|
fifo_addr_3 <= rdbuf_addr;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_2 <= 32'h0;
|
|
end else if (io_dbg_cmd_valid) begin
|
|
fifo_addr_2 <= io_dbg_cmd_addr;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_addr_2 <= wrbuf_addr;
|
|
end else begin
|
|
fifo_addr_2 <= rdbuf_addr;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_1 <= 32'h0;
|
|
end else if (io_dbg_cmd_valid) begin
|
|
fifo_addr_1 <= io_dbg_cmd_addr;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_addr_1 <= wrbuf_addr;
|
|
end else begin
|
|
fifo_addr_1 <= rdbuf_addr;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_0 <= 32'h0;
|
|
end else if (io_dbg_cmd_valid) begin
|
|
fifo_addr_0 <= io_dbg_cmd_addr;
|
|
end else begin
|
|
fifo_addr_0 <= bus_cmd_addr;
|
|
end
|
|
end
|
|
always @(posedge dma_bus_clk or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_vld <= 1'h0;
|
|
end else begin
|
|
wrbuf_vld <= _T_1204 & _T_1205;
|
|
end
|
|
end
|
|
always @(posedge dma_bus_clk or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_data_vld <= 1'h0;
|
|
end else begin
|
|
wrbuf_data_vld <= _T_1208 & _T_1209;
|
|
end
|
|
end
|
|
always @(posedge dma_bus_clk or posedge reset) begin
|
|
if (reset) begin
|
|
rdbuf_vld <= 1'h0;
|
|
end else begin
|
|
rdbuf_vld <= _T_1217 & _T_1218;
|
|
end
|
|
end
|
|
always @(posedge dma_bus_clk or posedge reset) begin
|
|
if (reset) begin
|
|
axi_mstr_priority <= 1'h0;
|
|
end else if (axi_mstr_prty_en) begin
|
|
axi_mstr_priority <= axi_mstr_prty_in;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_addr <= 32'h0;
|
|
end else begin
|
|
wrbuf_addr <= io_dma_axi_awaddr;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
rdbuf_addr <= 32'h0;
|
|
end else begin
|
|
rdbuf_addr <= io_dma_axi_araddr;
|
|
end
|
|
end
|
|
always @(posedge dma_bus_clk or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_byteen <= 8'h0;
|
|
end else if (wrbuf_data_en) begin
|
|
wrbuf_byteen <= io_dma_axi_wstrb;
|
|
end
|
|
end
|
|
always @(posedge dma_bus_clk or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_sz <= 3'h0;
|
|
end else if (wrbuf_en) begin
|
|
wrbuf_sz <= io_dma_axi_awsize;
|
|
end
|
|
end
|
|
always @(posedge dma_bus_clk or posedge reset) begin
|
|
if (reset) begin
|
|
rdbuf_sz <= 3'h0;
|
|
end else if (rdbuf_en) begin
|
|
rdbuf_sz <= io_dma_axi_arsize;
|
|
end
|
|
end
|
|
always @(posedge dma_bus_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_full <= 1'h0;
|
|
end else begin
|
|
fifo_full <= num_fifo_vld_tmp2 >= 4'h5;
|
|
end
|
|
end
|
|
always @(posedge dma_bus_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dbg_dma_bubble_bus <= 1'h0;
|
|
end else begin
|
|
dbg_dma_bubble_bus <= io_dbg_dma_bubble;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
WrPtr <= 3'h0;
|
|
end else if (WrPtrEn) begin
|
|
if (_T_931) begin
|
|
WrPtr <= 3'h0;
|
|
end else begin
|
|
WrPtr <= _T_934;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_598 <= 1'h0;
|
|
end else begin
|
|
_T_598 <= _T_594 & _T_596;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_591 <= 1'h0;
|
|
end else begin
|
|
_T_591 <= _T_587 & _T_589;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_584 <= 1'h0;
|
|
end else begin
|
|
_T_584 <= _T_580 & _T_582;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_577 <= 1'h0;
|
|
end else begin
|
|
_T_577 <= _T_573 & _T_575;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_570 <= 1'h0;
|
|
end else begin
|
|
_T_570 <= _T_566 & _T_568;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_760 <= 1'h0;
|
|
end else begin
|
|
_T_760 <= _T_399 & _T_596;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_753 <= 1'h0;
|
|
end else begin
|
|
_T_753 <= _T_395 & _T_589;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_746 <= 1'h0;
|
|
end else begin
|
|
_T_746 <= _T_391 & _T_582;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_739 <= 1'h0;
|
|
end else begin
|
|
_T_739 <= _T_387 & _T_575;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_732 <= 1'h0;
|
|
end else begin
|
|
_T_732 <= _T_383 & _T_568;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_886 <= 1'h0;
|
|
end else if (fifo_cmd_en[4]) begin
|
|
_T_886 <= io_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_884 <= 1'h0;
|
|
end else if (fifo_cmd_en[3]) begin
|
|
_T_884 <= io_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_882 <= 1'h0;
|
|
end else if (fifo_cmd_en[2]) begin
|
|
_T_882 <= io_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_880 <= 1'h0;
|
|
end else if (fifo_cmd_en[1]) begin
|
|
_T_880 <= io_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_878 <= 1'h0;
|
|
end else if (fifo_cmd_en[0]) begin
|
|
_T_878 <= io_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_4 <= 3'h0;
|
|
end else if (fifo_cmd_en[4]) begin
|
|
if (io_dbg_cmd_valid) begin
|
|
fifo_sz_4 <= _T_23;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_sz_4 <= wrbuf_sz;
|
|
end else begin
|
|
fifo_sz_4 <= rdbuf_sz;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_3 <= 3'h0;
|
|
end else if (fifo_cmd_en[3]) begin
|
|
if (io_dbg_cmd_valid) begin
|
|
fifo_sz_3 <= _T_23;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_sz_3 <= wrbuf_sz;
|
|
end else begin
|
|
fifo_sz_3 <= rdbuf_sz;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_2 <= 3'h0;
|
|
end else if (fifo_cmd_en[2]) begin
|
|
if (io_dbg_cmd_valid) begin
|
|
fifo_sz_2 <= _T_23;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_sz_2 <= wrbuf_sz;
|
|
end else begin
|
|
fifo_sz_2 <= rdbuf_sz;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_1 <= 3'h0;
|
|
end else if (fifo_cmd_en[1]) begin
|
|
if (io_dbg_cmd_valid) begin
|
|
fifo_sz_1 <= _T_23;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_sz_1 <= wrbuf_sz;
|
|
end else begin
|
|
fifo_sz_1 <= rdbuf_sz;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_0 <= 3'h0;
|
|
end else if (fifo_cmd_en[0]) begin
|
|
fifo_sz_0 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_4 <= 8'h0;
|
|
end else if (fifo_cmd_en[4]) begin
|
|
fifo_byteen_4 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_3 <= 8'h0;
|
|
end else if (fifo_cmd_en[3]) begin
|
|
fifo_byteen_3 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_2 <= 8'h0;
|
|
end else if (fifo_cmd_en[2]) begin
|
|
fifo_byteen_2 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_1 <= 8'h0;
|
|
end else if (fifo_cmd_en[1]) begin
|
|
fifo_byteen_1 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_0 <= 8'h0;
|
|
end else if (fifo_cmd_en[0]) begin
|
|
fifo_byteen_0 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_0 <= 2'h0;
|
|
end else begin
|
|
fifo_error_0 <= _T_605 & _T_609;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_1 <= 2'h0;
|
|
end else begin
|
|
fifo_error_1 <= _T_614 & _T_618;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_2 <= 2'h0;
|
|
end else begin
|
|
fifo_error_2 <= _T_623 & _T_627;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_3 <= 2'h0;
|
|
end else begin
|
|
fifo_error_3 <= _T_632 & _T_636;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_4 <= 2'h0;
|
|
end else begin
|
|
fifo_error_4 <= _T_641 & _T_645;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
RspPtr <= 3'h0;
|
|
end else if (RspPtrEn) begin
|
|
if (_T_941) begin
|
|
RspPtr <= 3'h0;
|
|
end else begin
|
|
RspPtr <= _T_944;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_data <= 64'h0;
|
|
end else begin
|
|
wrbuf_data <= io_dma_axi_wdata;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_721 <= 1'h0;
|
|
end else begin
|
|
_T_721 <= _T_717 & _T_596;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_714 <= 1'h0;
|
|
end else begin
|
|
_T_714 <= _T_710 & _T_589;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_707 <= 1'h0;
|
|
end else begin
|
|
_T_707 <= _T_703 & _T_582;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_700 <= 1'h0;
|
|
end else begin
|
|
_T_700 <= _T_696 & _T_575;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_693 <= 1'h0;
|
|
end else begin
|
|
_T_693 <= _T_689 & _T_568;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_799 <= 1'h0;
|
|
end else begin
|
|
_T_799 <= _T_795 & _T_596;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_792 <= 1'h0;
|
|
end else begin
|
|
_T_792 <= _T_788 & _T_589;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_785 <= 1'h0;
|
|
end else begin
|
|
_T_785 <= _T_781 & _T_582;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_778 <= 1'h0;
|
|
end else begin
|
|
_T_778 <= _T_774 & _T_575;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_771 <= 1'h0;
|
|
end else begin
|
|
_T_771 <= _T_767 & _T_568;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_850 <= 1'h0;
|
|
end else if (fifo_cmd_en[0]) begin
|
|
if (io_dbg_cmd_valid) begin
|
|
_T_850 <= io_dbg_cmd_write;
|
|
end else if (_T_1241) begin
|
|
_T_850 <= axi_mstr_priority;
|
|
end else begin
|
|
_T_850 <= _T_1240;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_852 <= 1'h0;
|
|
end else if (fifo_cmd_en[1]) begin
|
|
if (io_dbg_cmd_valid) begin
|
|
_T_852 <= io_dbg_cmd_write;
|
|
end else if (_T_1241) begin
|
|
_T_852 <= axi_mstr_priority;
|
|
end else begin
|
|
_T_852 <= _T_1240;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_854 <= 1'h0;
|
|
end else if (fifo_cmd_en[2]) begin
|
|
if (io_dbg_cmd_valid) begin
|
|
_T_854 <= io_dbg_cmd_write;
|
|
end else if (_T_1241) begin
|
|
_T_854 <= axi_mstr_priority;
|
|
end else begin
|
|
_T_854 <= _T_1240;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_856 <= 1'h0;
|
|
end else if (fifo_cmd_en[3]) begin
|
|
if (io_dbg_cmd_valid) begin
|
|
_T_856 <= io_dbg_cmd_write;
|
|
end else if (_T_1241) begin
|
|
_T_856 <= axi_mstr_priority;
|
|
end else begin
|
|
_T_856 <= _T_1240;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_858 <= 1'h0;
|
|
end else if (fifo_cmd_en[4]) begin
|
|
_T_858 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_0 <= 64'h0;
|
|
end else if (_T_491) begin
|
|
fifo_data_0 <= _T_493;
|
|
end else if (_T_84) begin
|
|
fifo_data_0 <= io_dccm_dma_rdata;
|
|
end else if (_T_87) begin
|
|
fifo_data_0 <= io_iccm_dma_rdata;
|
|
end else if (io_dbg_cmd_valid) begin
|
|
fifo_data_0 <= _T_498;
|
|
end else begin
|
|
fifo_data_0 <= wrbuf_data;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_1 <= 64'h0;
|
|
end else if (_T_506) begin
|
|
fifo_data_1 <= _T_508;
|
|
end else if (_T_102) begin
|
|
fifo_data_1 <= io_dccm_dma_rdata;
|
|
end else if (_T_105) begin
|
|
fifo_data_1 <= io_iccm_dma_rdata;
|
|
end else if (io_dbg_cmd_valid) begin
|
|
fifo_data_1 <= _T_498;
|
|
end else begin
|
|
fifo_data_1 <= wrbuf_data;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_2 <= 64'h0;
|
|
end else if (_T_521) begin
|
|
fifo_data_2 <= _T_523;
|
|
end else if (_T_120) begin
|
|
fifo_data_2 <= io_dccm_dma_rdata;
|
|
end else if (_T_123) begin
|
|
fifo_data_2 <= io_iccm_dma_rdata;
|
|
end else if (io_dbg_cmd_valid) begin
|
|
fifo_data_2 <= _T_498;
|
|
end else begin
|
|
fifo_data_2 <= wrbuf_data;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_3 <= 64'h0;
|
|
end else if (_T_536) begin
|
|
fifo_data_3 <= _T_538;
|
|
end else if (_T_138) begin
|
|
fifo_data_3 <= io_dccm_dma_rdata;
|
|
end else if (_T_141) begin
|
|
fifo_data_3 <= io_iccm_dma_rdata;
|
|
end else if (io_dbg_cmd_valid) begin
|
|
fifo_data_3 <= _T_498;
|
|
end else begin
|
|
fifo_data_3 <= wrbuf_data;
|
|
end
|
|
end
|
|
always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_4 <= 64'h0;
|
|
end else if (_T_551) begin
|
|
fifo_data_4 <= _T_553;
|
|
end else if (_T_156) begin
|
|
fifo_data_4 <= io_dccm_dma_rdata;
|
|
end else if (_T_159) begin
|
|
fifo_data_4 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_4 <= _T_500;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_0 <= 1'h0;
|
|
end else if (fifo_cmd_en[0]) begin
|
|
if (axi_mstr_sel) begin
|
|
fifo_tag_0 <= wrbuf_tag;
|
|
end else begin
|
|
fifo_tag_0 <= rdbuf_tag;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_bus_clk or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_tag <= 1'h0;
|
|
end else if (wrbuf_en) begin
|
|
wrbuf_tag <= io_dma_axi_awid;
|
|
end
|
|
end
|
|
always @(posedge dma_bus_clk or posedge reset) begin
|
|
if (reset) begin
|
|
rdbuf_tag <= 1'h0;
|
|
end else if (rdbuf_en) begin
|
|
rdbuf_tag <= io_dma_axi_arid;
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_1 <= 1'h0;
|
|
end else if (fifo_cmd_en[1]) begin
|
|
if (axi_mstr_sel) begin
|
|
fifo_tag_1 <= wrbuf_tag;
|
|
end else begin
|
|
fifo_tag_1 <= rdbuf_tag;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_2 <= 1'h0;
|
|
end else if (fifo_cmd_en[2]) begin
|
|
if (axi_mstr_sel) begin
|
|
fifo_tag_2 <= wrbuf_tag;
|
|
end else begin
|
|
fifo_tag_2 <= rdbuf_tag;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_3 <= 1'h0;
|
|
end else if (fifo_cmd_en[3]) begin
|
|
if (axi_mstr_sel) begin
|
|
fifo_tag_3 <= wrbuf_tag;
|
|
end else begin
|
|
fifo_tag_3 <= rdbuf_tag;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge dma_buffer_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_4 <= 1'h0;
|
|
end else if (fifo_cmd_en[4]) begin
|
|
fifo_tag_4 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge dma_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_nack_count <= 3'h0;
|
|
end else if (dma_mem_req) begin
|
|
if (_T_1118) begin
|
|
dma_nack_count <= _T_1131;
|
|
end else if (_T_1135) begin
|
|
dma_nack_count <= _T_1138;
|
|
end else begin
|
|
dma_nack_count <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_dbg_cmd_done_q <= 1'h0;
|
|
end else begin
|
|
dma_dbg_cmd_done_q <= io_dma_dbg_cmd_done;
|
|
end
|
|
end
|
|
endmodule
|
|
module el2_swerv(
|
|
input clock,
|
|
input reset,
|
|
input io_dbg_rst_l,
|
|
input [30:0] io_rst_vec,
|
|
input io_nmi_int,
|
|
input [30:0] io_nmi_vec,
|
|
output io_core_rst_l,
|
|
output [31:0] io_trace_rv_i_insn_ip,
|
|
output [31:0] io_trace_rv_i_address_ip,
|
|
output [1:0] io_trace_rv_i_valid_ip,
|
|
output [1:0] io_trace_rv_i_exception_ip,
|
|
output [4:0] io_trace_rv_i_ecause_ip,
|
|
output [1:0] io_trace_rv_i_interrupt_ip,
|
|
output [31:0] io_trace_rv_i_tval_ip,
|
|
output io_dccm_clk_override,
|
|
output io_icm_clk_override,
|
|
output io_dec_tlu_core_ecc_disable,
|
|
input io_i_cpu_halt_req,
|
|
input io_i_cpu_run_req,
|
|
output io_o_cpu_halt_ack,
|
|
output io_o_cpu_halt_status,
|
|
output io_o_cpu_run_ack,
|
|
output io_o_debug_mode_status,
|
|
input [27:0] io_core_id,
|
|
input io_mpc_debug_halt_req,
|
|
input io_mpc_debug_run_req,
|
|
input io_mpc_reset_run_req,
|
|
output io_mpc_debug_halt_ack,
|
|
output io_mpc_debug_run_ack,
|
|
output io_debug_brkpt_status,
|
|
output io_dec_tlu_perfcnt0,
|
|
output io_dec_tlu_perfcnt1,
|
|
output io_dec_tlu_perfcnt2,
|
|
output io_dec_tlu_perfcnt3,
|
|
output io_dccm_wren,
|
|
output io_dccm_rden,
|
|
output [15:0] io_dccm_wr_addr_lo,
|
|
output [15:0] io_dccm_wr_addr_hi,
|
|
output [15:0] io_dccm_rd_addr_lo,
|
|
output [15:0] io_dccm_rd_addr_hi,
|
|
output [38:0] io_dccm_wr_data_lo,
|
|
output [38:0] io_dccm_wr_data_hi,
|
|
input [38:0] io_dccm_rd_data_lo,
|
|
input [38:0] io_dccm_rd_data_hi,
|
|
output [14:0] io_iccm_rw_addr,
|
|
output io_iccm_wren,
|
|
output io_iccm_rden,
|
|
output [2:0] io_iccm_wr_size,
|
|
output [77:0] io_iccm_wr_data,
|
|
output io_iccm_buf_correct_ecc,
|
|
output io_iccm_correction_state,
|
|
input [63:0] io_iccm_rd_data,
|
|
input [77:0] io_iccm_rd_data_ecc,
|
|
output [30:0] io_ic_rw_addr,
|
|
output [1:0] io_ic_tag_valid,
|
|
output [1:0] io_ic_wr_en,
|
|
output io_ic_rd_en,
|
|
output [70:0] io_ic_wr_data_0,
|
|
output [70:0] io_ic_wr_data_1,
|
|
input [63:0] io_ic_rd_data,
|
|
input [70:0] io_ic_debug_rd_data,
|
|
input [25:0] io_ictag_debug_rd_data,
|
|
output [70:0] io_ic_debug_wr_data,
|
|
input [1:0] io_ic_eccerr,
|
|
input [1:0] io_ic_parerr,
|
|
output [63:0] io_ic_premux_data,
|
|
output io_ic_sel_premux_data,
|
|
output [9:0] io_ic_debug_addr,
|
|
output io_ic_debug_rd_en,
|
|
output io_ic_debug_wr_en,
|
|
output io_ic_debug_tag_array,
|
|
output [1:0] io_ic_debug_way,
|
|
input [1:0] io_ic_rd_hit,
|
|
input io_ic_tag_perr,
|
|
output io_lsu_axi_awvalid,
|
|
input io_lsu_axi_awready,
|
|
output [2:0] io_lsu_axi_awid,
|
|
output [31:0] io_lsu_axi_awaddr,
|
|
output [3:0] io_lsu_axi_awregion,
|
|
output [7:0] io_lsu_axi_awlen,
|
|
output [2:0] io_lsu_axi_awsize,
|
|
output [1:0] io_lsu_axi_awburst,
|
|
output io_lsu_axi_awlock,
|
|
output [3:0] io_lsu_axi_awcache,
|
|
output [2:0] io_lsu_axi_awprot,
|
|
output [3:0] io_lsu_axi_awqos,
|
|
output io_lsu_axi_wvalid,
|
|
input io_lsu_axi_wready,
|
|
output [63:0] io_lsu_axi_wdata,
|
|
output [7:0] io_lsu_axi_wstrb,
|
|
output io_lsu_axi_wlast,
|
|
input io_lsu_axi_bvalid,
|
|
output io_lsu_axi_bready,
|
|
input [1:0] io_lsu_axi_bresp,
|
|
input [2:0] io_lsu_axi_bid,
|
|
output io_lsu_axi_arvalid,
|
|
input io_lsu_axi_arready,
|
|
output [2:0] io_lsu_axi_arid,
|
|
output [31:0] io_lsu_axi_araddr,
|
|
output [3:0] io_lsu_axi_arregion,
|
|
output [7:0] io_lsu_axi_arlen,
|
|
output [2:0] io_lsu_axi_arsize,
|
|
output [1:0] io_lsu_axi_arburst,
|
|
output io_lsu_axi_arlock,
|
|
output [3:0] io_lsu_axi_arcache,
|
|
output [2:0] io_lsu_axi_arprot,
|
|
output [3:0] io_lsu_axi_arqos,
|
|
input io_lsu_axi_rvalid,
|
|
output io_lsu_axi_rready,
|
|
input [2:0] io_lsu_axi_rid,
|
|
input [63:0] io_lsu_axi_rdata,
|
|
input [1:0] io_lsu_axi_rresp,
|
|
input io_lsu_axi_rlast,
|
|
output io_ifu_axi_awvalid,
|
|
input io_ifu_axi_awready,
|
|
output [2:0] io_ifu_axi_awid,
|
|
output [31:0] io_ifu_axi_awaddr,
|
|
output [3:0] io_ifu_axi_awregion,
|
|
output [7:0] io_ifu_axi_awlen,
|
|
output [2:0] io_ifu_axi_awsize,
|
|
output [1:0] io_ifu_axi_awburst,
|
|
output io_ifu_axi_awlock,
|
|
output [3:0] io_ifu_axi_awcache,
|
|
output [2:0] io_ifu_axi_awprot,
|
|
output [3:0] io_ifu_axi_awqos,
|
|
output io_ifu_axi_wvalid,
|
|
input io_ifu_axi_wready,
|
|
output [63:0] io_ifu_axi_wdata,
|
|
output [7:0] io_ifu_axi_wstrb,
|
|
output io_ifu_axi_wlast,
|
|
input io_ifu_axi_bvalid,
|
|
output io_ifu_axi_bready,
|
|
input [1:0] io_ifu_axi_bresp,
|
|
input [2:0] io_ifu_axi_bid,
|
|
output io_ifu_axi_arvalid,
|
|
input io_ifu_axi_arready,
|
|
output [2:0] io_ifu_axi_arid,
|
|
output [31:0] io_ifu_axi_araddr,
|
|
output [3:0] io_ifu_axi_arregion,
|
|
output [7:0] io_ifu_axi_arlen,
|
|
output [2:0] io_ifu_axi_arsize,
|
|
output [1:0] io_ifu_axi_arburst,
|
|
output io_ifu_axi_arlock,
|
|
output [3:0] io_ifu_axi_arcache,
|
|
output [2:0] io_ifu_axi_arprot,
|
|
output [3:0] io_ifu_axi_arqos,
|
|
input io_ifu_axi_rvalid,
|
|
output io_ifu_axi_rready,
|
|
input [2:0] io_ifu_axi_rid,
|
|
input [63:0] io_ifu_axi_rdata,
|
|
input [1:0] io_ifu_axi_rresp,
|
|
input io_ifu_axi_rlast,
|
|
output io_sb_axi_awvalid,
|
|
input io_sb_axi_awready,
|
|
output io_sb_axi_awid,
|
|
output [31:0] io_sb_axi_awaddr,
|
|
output [3:0] io_sb_axi_awregion,
|
|
output [7:0] io_sb_axi_awlen,
|
|
output [2:0] io_sb_axi_awsize,
|
|
output [1:0] io_sb_axi_awburst,
|
|
output io_sb_axi_awlock,
|
|
output [3:0] io_sb_axi_awcache,
|
|
output [2:0] io_sb_axi_awprot,
|
|
output [3:0] io_sb_axi_awqos,
|
|
output io_sb_axi_wvalid,
|
|
input io_sb_axi_wready,
|
|
output [63:0] io_sb_axi_wdata,
|
|
output [7:0] io_sb_axi_wstrb,
|
|
output io_sb_axi_wlast,
|
|
input io_sb_axi_bvalid,
|
|
output io_sb_axi_bready,
|
|
input [1:0] io_sb_axi_bresp,
|
|
input io_sb_axi_bid,
|
|
output io_sb_axi_arvalid,
|
|
input io_sb_axi_arready,
|
|
output io_sb_axi_arid,
|
|
output [31:0] io_sb_axi_araddr,
|
|
output [3:0] io_sb_axi_arregion,
|
|
output [7:0] io_sb_axi_arlen,
|
|
output [2:0] io_sb_axi_arsize,
|
|
output [1:0] io_sb_axi_arburst,
|
|
output io_sb_axi_arlock,
|
|
output [3:0] io_sb_axi_arcache,
|
|
output [2:0] io_sb_axi_arprot,
|
|
output [3:0] io_sb_axi_arqos,
|
|
input io_sb_axi_rvalid,
|
|
output io_sb_axi_rready,
|
|
input io_sb_axi_rid,
|
|
input [63:0] io_sb_axi_rdata,
|
|
input [1:0] io_sb_axi_rresp,
|
|
input io_sb_axi_rlast,
|
|
input io_dma_axi_awvalid,
|
|
output io_dma_axi_awready,
|
|
input io_dma_axi_awid,
|
|
input [31:0] io_dma_axi_awaddr,
|
|
input [2:0] io_dma_axi_awsize,
|
|
input [2:0] io_dma_axi_awprot,
|
|
input [7:0] io_dma_axi_awlen,
|
|
input [1:0] io_dma_axi_awburst,
|
|
input io_dma_axi_wvalid,
|
|
output io_dma_axi_wready,
|
|
input [63:0] io_dma_axi_wdata,
|
|
input [7:0] io_dma_axi_wstrb,
|
|
input io_dma_axi_wlast,
|
|
output io_dma_axi_bvalid,
|
|
input io_dma_axi_bready,
|
|
output [1:0] io_dma_axi_bresp,
|
|
output io_dma_axi_bid,
|
|
input io_dma_axi_arvalid,
|
|
output io_dma_axi_arready,
|
|
input io_dma_axi_arid,
|
|
input [31:0] io_dma_axi_araddr,
|
|
input [2:0] io_dma_axi_arsize,
|
|
input [2:0] io_dma_axi_arprot,
|
|
input [7:0] io_dma_axi_arlen,
|
|
input [1:0] io_dma_axi_arburst,
|
|
output io_dma_axi_rvalid,
|
|
input io_dma_axi_rready,
|
|
output io_dma_axi_rid,
|
|
output [63:0] io_dma_axi_rdata,
|
|
output [1:0] io_dma_axi_rresp,
|
|
output io_dma_axi_rlast,
|
|
output [31:0] io_haddr,
|
|
output [2:0] io_hburst,
|
|
output io_hmastlock,
|
|
output [3:0] io_hprot,
|
|
output [2:0] io_hsize,
|
|
output [1:0] io_htrans,
|
|
output io_hwrite,
|
|
input [63:0] io_hrdata,
|
|
input io_hready,
|
|
input io_hresp,
|
|
output [31:0] io_lsu_haddr,
|
|
output [2:0] io_lsu_hburst,
|
|
output io_lsu_hmastlock,
|
|
output [3:0] io_lsu_hprot,
|
|
output [2:0] io_lsu_hsize,
|
|
output [1:0] io_lsu_htrans,
|
|
output io_lsu_hwrite,
|
|
output [63:0] io_lsu_hwdata,
|
|
input [63:0] io_lsu_hrdata,
|
|
input io_lsu_hready,
|
|
input io_lsu_hresp,
|
|
output [31:0] io_sb_haddr,
|
|
output [2:0] io_sb_hburst,
|
|
output io_sb_hmastlock,
|
|
output [3:0] io_sb_hprot,
|
|
output [2:0] io_sb_hsize,
|
|
output [1:0] io_sb_htrans,
|
|
output io_sb_hwrite,
|
|
output [63:0] io_sb_hwdata,
|
|
input [63:0] io_sb_hrdata,
|
|
input io_sb_hready,
|
|
input io_sb_hresp,
|
|
input io_dma_hsel,
|
|
input [31:0] io_dma_haddr,
|
|
input [2:0] io_dma_hburst,
|
|
input io_dma_hmastlock,
|
|
input [3:0] io_dma_hprot,
|
|
input [2:0] io_dma_hsize,
|
|
input [1:0] io_dma_htrans,
|
|
input io_dma_hwrite,
|
|
input [63:0] io_dma_hwdata,
|
|
input io_dma_hreadyin,
|
|
output [63:0] io_dma_hrdata,
|
|
output io_dma_hreadyout,
|
|
output io_dma_hresp,
|
|
input io_lsu_bus_clk_en,
|
|
input io_ifu_bus_clk_en,
|
|
input io_dbg_bus_clk_en,
|
|
input io_dma_bus_clk_en,
|
|
input io_dmi_reg_en,
|
|
input [6:0] io_dmi_reg_addr,
|
|
input io_dmi_reg_wr_en,
|
|
input [31:0] io_dmi_reg_wdata,
|
|
output [31:0] io_dmi_reg_rdata,
|
|
input io_dmi_hard_reset,
|
|
input [30:0] io_extintsrc_req,
|
|
input io_timer_int,
|
|
input io_soft_int,
|
|
input io_scan_mode
|
|
);
|
|
wire ifu_clock; // @[el2_swerv.scala 321:19]
|
|
wire ifu_reset; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_free_clk; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_active_clk; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_i0_decode_d; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_exu_flush_final; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_i0_commit_cmt; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_flush_err_wb; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_flush_noredir_wb; // @[el2_swerv.scala 321:19]
|
|
wire [30:0] ifu_io_exu_flush_path_final; // @[el2_swerv.scala 321:19]
|
|
wire [31:0] ifu_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_fence_i_wb; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_flush_leak_one_wb; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_bpred_disable; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_force_halt; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_axi_arvalid; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_axi_arready; // @[el2_swerv.scala 321:19]
|
|
wire [2:0] ifu_io_ifu_axi_arid; // @[el2_swerv.scala 321:19]
|
|
wire [31:0] ifu_io_ifu_axi_araddr; // @[el2_swerv.scala 321:19]
|
|
wire [3:0] ifu_io_ifu_axi_arregion; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_axi_rvalid; // @[el2_swerv.scala 321:19]
|
|
wire [2:0] ifu_io_ifu_axi_rid; // @[el2_swerv.scala 321:19]
|
|
wire [63:0] ifu_io_ifu_axi_rdata; // @[el2_swerv.scala 321:19]
|
|
wire [1:0] ifu_io_ifu_axi_rresp; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_bus_clk_en; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dma_iccm_req; // @[el2_swerv.scala 321:19]
|
|
wire [31:0] ifu_io_dma_mem_addr; // @[el2_swerv.scala 321:19]
|
|
wire [2:0] ifu_io_dma_mem_sz; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dma_mem_write; // @[el2_swerv.scala 321:19]
|
|
wire [63:0] ifu_io_dma_mem_wdata; // @[el2_swerv.scala 321:19]
|
|
wire [2:0] ifu_io_dma_mem_tag; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dma_iccm_stall_any; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_iccm_dma_ecc_error; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_iccm_dma_rvalid; // @[el2_swerv.scala 321:19]
|
|
wire [63:0] ifu_io_iccm_dma_rdata; // @[el2_swerv.scala 321:19]
|
|
wire [2:0] ifu_io_iccm_dma_rtag; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_iccm_ready; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_pmu_instr_aligned; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_pmu_fetch_stall; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_ic_error_start; // @[el2_swerv.scala 321:19]
|
|
wire [30:0] ifu_io_ic_rw_addr; // @[el2_swerv.scala 321:19]
|
|
wire [1:0] ifu_io_ic_wr_en; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ic_rd_en; // @[el2_swerv.scala 321:19]
|
|
wire [70:0] ifu_io_ic_wr_data_0; // @[el2_swerv.scala 321:19]
|
|
wire [70:0] ifu_io_ic_wr_data_1; // @[el2_swerv.scala 321:19]
|
|
wire [63:0] ifu_io_ic_rd_data; // @[el2_swerv.scala 321:19]
|
|
wire [70:0] ifu_io_ic_debug_rd_data; // @[el2_swerv.scala 321:19]
|
|
wire [25:0] ifu_io_ictag_debug_rd_data; // @[el2_swerv.scala 321:19]
|
|
wire [70:0] ifu_io_ic_debug_wr_data; // @[el2_swerv.scala 321:19]
|
|
wire [70:0] ifu_io_ifu_ic_debug_rd_data; // @[el2_swerv.scala 321:19]
|
|
wire [1:0] ifu_io_ic_eccerr; // @[el2_swerv.scala 321:19]
|
|
wire [63:0] ifu_io_ic_premux_data; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ic_sel_premux_data; // @[el2_swerv.scala 321:19]
|
|
wire [9:0] ifu_io_ic_debug_addr; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ic_debug_rd_en; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ic_debug_wr_en; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ic_debug_tag_array; // @[el2_swerv.scala 321:19]
|
|
wire [1:0] ifu_io_ic_debug_way; // @[el2_swerv.scala 321:19]
|
|
wire [1:0] ifu_io_ic_tag_valid; // @[el2_swerv.scala 321:19]
|
|
wire [1:0] ifu_io_ic_rd_hit; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ic_tag_perr; // @[el2_swerv.scala 321:19]
|
|
wire [14:0] ifu_io_iccm_rw_addr; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_iccm_wren; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_iccm_rden; // @[el2_swerv.scala 321:19]
|
|
wire [77:0] ifu_io_iccm_wr_data; // @[el2_swerv.scala 321:19]
|
|
wire [2:0] ifu_io_iccm_wr_size; // @[el2_swerv.scala 321:19]
|
|
wire [63:0] ifu_io_iccm_rd_data; // @[el2_swerv.scala 321:19]
|
|
wire [77:0] ifu_io_iccm_rd_data_ecc; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_iccm_rd_ecc_single_err; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_pmu_ic_miss; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_pmu_ic_hit; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_pmu_bus_error; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_pmu_bus_busy; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_pmu_bus_trxn; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_i0_icaf; // @[el2_swerv.scala 321:19]
|
|
wire [1:0] ifu_io_ifu_i0_icaf_type; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_i0_valid; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_i0_icaf_f1; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_i0_dbecc; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_iccm_dma_sb_error; // @[el2_swerv.scala 321:19]
|
|
wire [31:0] ifu_io_ifu_i0_instr; // @[el2_swerv.scala 321:19]
|
|
wire [30:0] ifu_io_ifu_i0_pc; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_i0_pc4; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_miss_state_idle; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_i0_brp_valid; // @[el2_swerv.scala 321:19]
|
|
wire [11:0] ifu_io_i0_brp_toffset; // @[el2_swerv.scala 321:19]
|
|
wire [1:0] ifu_io_i0_brp_hist; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_i0_brp_br_error; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_i0_brp_br_start_error; // @[el2_swerv.scala 321:19]
|
|
wire [30:0] ifu_io_i0_brp_prett; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_i0_brp_way; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_i0_brp_ret; // @[el2_swerv.scala 321:19]
|
|
wire [7:0] ifu_io_ifu_i0_bp_index; // @[el2_swerv.scala 321:19]
|
|
wire [7:0] ifu_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 321:19]
|
|
wire [4:0] ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_exu_mp_pkt_bits_boffset; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 321:19]
|
|
wire [1:0] ifu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 321:19]
|
|
wire [11:0] ifu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_exu_mp_pkt_bits_pcall; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_exu_mp_pkt_bits_pret; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_exu_mp_pkt_bits_pja; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_exu_mp_pkt_bits_way; // @[el2_swerv.scala 321:19]
|
|
wire [7:0] ifu_io_exu_mp_eghr; // @[el2_swerv.scala 321:19]
|
|
wire [7:0] ifu_io_exu_mp_fghr; // @[el2_swerv.scala 321:19]
|
|
wire [7:0] ifu_io_exu_mp_index; // @[el2_swerv.scala 321:19]
|
|
wire [4:0] ifu_io_exu_mp_btag; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 321:19]
|
|
wire [1:0] ifu_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 321:19]
|
|
wire [7:0] ifu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 321:19]
|
|
wire [7:0] ifu_io_exu_i0_br_index_r; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_flush_lower_wb; // @[el2_swerv.scala 321:19]
|
|
wire [15:0] ifu_io_ifu_i0_cinst; // @[el2_swerv.scala 321:19]
|
|
wire [70:0] ifu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_swerv.scala 321:19]
|
|
wire [16:0] ifu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_ifu_ic_debug_rd_data_valid; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_iccm_buf_correct_ecc; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_iccm_correction_state; // @[el2_swerv.scala 321:19]
|
|
wire ifu_io_scan_mode; // @[el2_swerv.scala 321:19]
|
|
wire dec_clock; // @[el2_swerv.scala 322:19]
|
|
wire dec_reset; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_free_clk; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_active_clk; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_fastint_stall_any; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_extint_stall; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_decode_d; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_pause_state_cg; // @[el2_swerv.scala 322:19]
|
|
wire [30:0] dec_io_rst_vec; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_nmi_int; // @[el2_swerv.scala 322:19]
|
|
wire [30:0] dec_io_nmi_vec; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i_cpu_halt_req; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i_cpu_run_req; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_o_cpu_halt_status; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_o_cpu_halt_ack; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_o_cpu_run_ack; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_o_debug_mode_status; // @[el2_swerv.scala 322:19]
|
|
wire [27:0] dec_io_core_id; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_mpc_debug_halt_req; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_mpc_debug_run_req; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_mpc_reset_run_req; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_mpc_debug_halt_ack; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_mpc_debug_run_ack; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_debug_brkpt_status; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_exu_pmu_i0_br_misp; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_exu_pmu_i0_br_ataken; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_exu_pmu_i0_pc4; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_nonblock_load_valid_m; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_lsu_nonblock_load_tag_m; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_nonblock_load_inv_r; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_lsu_nonblock_load_inv_tag_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_nonblock_load_data_valid; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_nonblock_load_data_error; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_lsu_nonblock_load_data_tag; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_lsu_nonblock_load_data; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_pmu_bus_trxn; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_pmu_bus_misaligned; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_pmu_bus_error; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_pmu_bus_busy; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_pmu_load_external_m; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_pmu_store_external_m; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dma_pmu_dccm_read; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dma_pmu_dccm_write; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dma_pmu_any_read; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dma_pmu_any_write; // @[el2_swerv.scala 322:19]
|
|
wire [30:0] dec_io_lsu_fir_addr; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_lsu_fir_error; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_pmu_instr_aligned; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_pmu_fetch_stall; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_pmu_ic_miss; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_pmu_ic_hit; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_pmu_bus_error; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_pmu_bus_busy; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_pmu_bus_trxn; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_ic_error_start; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_iccm_rd_ecc_single_err; // @[el2_swerv.scala 322:19]
|
|
wire [3:0] dec_io_lsu_trigger_match_m; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dbg_cmd_valid; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dbg_cmd_write; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_dbg_cmd_type; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_dbg_cmd_addr; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_dbg_cmd_wrdata; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_i0_icaf; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_ifu_i0_icaf_type; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_i0_icaf_f1; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_i0_dbecc; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_idle_any; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_brp_valid; // @[el2_swerv.scala 322:19]
|
|
wire [11:0] dec_io_i0_brp_toffset; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_i0_brp_hist; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_brp_br_error; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_brp_br_start_error; // @[el2_swerv.scala 322:19]
|
|
wire [30:0] dec_io_i0_brp_prett; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_brp_way; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_brp_ret; // @[el2_swerv.scala 322:19]
|
|
wire [7:0] dec_io_ifu_i0_bp_index; // @[el2_swerv.scala 322:19]
|
|
wire [7:0] dec_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 322:19]
|
|
wire [4:0] dec_io_ifu_i0_bp_btag; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_error_pkt_r_valid; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[el2_swerv.scala 322:19]
|
|
wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_single_ecc_error_incr; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_imprecise_error_load_any; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_imprecise_error_store_any; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_lsu_imprecise_error_addr_any; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_exu_div_result; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_exu_div_wren; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_exu_csr_rs1_x; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_lsu_result_m; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_lsu_result_corr_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_load_stall_any; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_store_stall_any; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dma_dccm_stall_any; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dma_iccm_stall_any; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_iccm_dma_sb_error; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_exu_flush_final; // @[el2_swerv.scala 322:19]
|
|
wire [30:0] dec_io_exu_npc_r; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_exu_i0_result_x; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_i0_valid; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_ifu_i0_instr; // @[el2_swerv.scala 322:19]
|
|
wire [30:0] dec_io_ifu_i0_pc; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_i0_pc4; // @[el2_swerv.scala 322:19]
|
|
wire [30:0] dec_io_exu_i0_pc_x; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_mexintpend; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_timer_int; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_soft_int; // @[el2_swerv.scala 322:19]
|
|
wire [7:0] dec_io_pic_claimid; // @[el2_swerv.scala 322:19]
|
|
wire [3:0] dec_io_pic_pl; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_mhwakeup; // @[el2_swerv.scala 322:19]
|
|
wire [3:0] dec_io_dec_tlu_meicurpl; // @[el2_swerv.scala 322:19]
|
|
wire [3:0] dec_io_dec_tlu_meipt; // @[el2_swerv.scala 322:19]
|
|
wire [70:0] dec_io_ifu_ic_debug_rd_data; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_ic_debug_rd_data_valid; // @[el2_swerv.scala 322:19]
|
|
wire [70:0] dec_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_swerv.scala 322:19]
|
|
wire [16:0] dec_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dbg_halt_req; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dbg_resume_req; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_ifu_miss_state_idle; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_dbg_halted; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_debug_mode; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_resume_ack; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_flush_noredir_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_mpc_halted_only; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_flush_leak_one_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_flush_err_r; // @[el2_swerv.scala 322:19]
|
|
wire [29:0] dec_io_dec_tlu_meihap; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_debug_wdata_rs1_d; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_dec_dbg_rddata; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_dbg_cmd_done; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_dbg_cmd_fail; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_0_match_pkt; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_1_match_pkt; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_2_match_pkt; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_3_match_pkt; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_force_halt; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_exu_i0_br_hist_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_exu_i0_br_error_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_exu_i0_br_start_error_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_exu_i0_br_valid_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_exu_i0_br_mp_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_exu_i0_br_middle_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_exu_i0_br_way_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_rs1_en_d; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_rs2_en_d; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_gpr_i0_rs1_d; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_gpr_i0_rs2_d; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_dec_i0_immed_d; // @[el2_swerv.scala 322:19]
|
|
wire [11:0] dec_io_dec_i0_br_immed_d; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_land; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_lor; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_lxor; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_sll; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_srl; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_sra; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_beq; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_bne; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_blt; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_bge; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_add; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_sub; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_slt; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_unsign; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_jal; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_predict_t; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_predict_nt; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_csr_write; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_i0_ap_csr_imm; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_select_pc_d; // @[el2_swerv.scala 322:19]
|
|
wire [30:0] dec_io_dec_i0_pc_d; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_dec_i0_rs1_bypass_data_d; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_dec_i0_rs2_bypass_data_d; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_p_valid; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_p_bits_fast_int; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_p_bits_by; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_p_bits_half; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_p_bits_word; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_p_bits_load; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_p_bits_store; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_p_bits_unsign; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_p_bits_store_data_bypass_d; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_mul_p_valid; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_mul_p_bits_rs1_sign; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_mul_p_bits_rs2_sign; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_mul_p_bits_low; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_div_p_valid; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_div_p_bits_unsign; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_div_p_bits_rem; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_div_cancel; // @[el2_swerv.scala 322:19]
|
|
wire [11:0] dec_io_dec_lsu_offset_d; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_csr_ren_d; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 322:19]
|
|
wire [30:0] dec_io_dec_tlu_flush_path_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_i0_kill_writeb_r; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_fence_i_r; // @[el2_swerv.scala 322:19]
|
|
wire [30:0] dec_io_pred_correct_npc_x; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_perfcnt0; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_perfcnt1; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_perfcnt2; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_perfcnt3; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_predict_p_d_valid; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_predict_p_d_bits_pc4; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_dec_i0_predict_p_d_bits_hist; // @[el2_swerv.scala 322:19]
|
|
wire [11:0] dec_io_dec_i0_predict_p_d_bits_toffset; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_predict_p_d_bits_br_error; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_swerv.scala 322:19]
|
|
wire [30:0] dec_io_dec_i0_predict_p_d_bits_prett; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_predict_p_d_bits_pcall; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_predict_p_d_bits_pret; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_predict_p_d_bits_pja; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_i0_predict_p_d_bits_way; // @[el2_swerv.scala 322:19]
|
|
wire [7:0] dec_io_i0_predict_fghr_d; // @[el2_swerv.scala 322:19]
|
|
wire [7:0] dec_io_i0_predict_index_d; // @[el2_swerv.scala 322:19]
|
|
wire [4:0] dec_io_i0_predict_btag_d; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_lsu_valid_raw_d; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_dec_data_en; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_dec_ctl_en; // @[el2_swerv.scala 322:19]
|
|
wire [15:0] dec_io_ifu_i0_cinst; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[el2_swerv.scala 322:19]
|
|
wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[el2_swerv.scala 322:19]
|
|
wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[el2_swerv.scala 322:19]
|
|
wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_external_ldfwd_disable; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_sideeffect_posted_disable; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_bpred_disable; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_wb_coalescing_disable; // @[el2_swerv.scala 322:19]
|
|
wire [2:0] dec_io_dec_tlu_dma_qos_prty; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_misc_clk_override; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_lsu_clk_override; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_pic_clk_override; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_dccm_clk_override; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_icm_clk_override; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_dec_tlu_i0_commit_cmt; // @[el2_swerv.scala 322:19]
|
|
wire dec_io_scan_mode; // @[el2_swerv.scala 322:19]
|
|
wire dbg_clock; // @[el2_swerv.scala 323:19]
|
|
wire dbg_reset; // @[el2_swerv.scala 323:19]
|
|
wire [31:0] dbg_io_dbg_cmd_addr; // @[el2_swerv.scala 323:19]
|
|
wire [31:0] dbg_io_dbg_cmd_wrdata; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dbg_cmd_valid; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dbg_cmd_write; // @[el2_swerv.scala 323:19]
|
|
wire [1:0] dbg_io_dbg_cmd_type; // @[el2_swerv.scala 323:19]
|
|
wire [1:0] dbg_io_dbg_cmd_size; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dbg_core_rst_l; // @[el2_swerv.scala 323:19]
|
|
wire [31:0] dbg_io_core_dbg_rddata; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_core_dbg_cmd_done; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_core_dbg_cmd_fail; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dbg_dma_bubble; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dma_dbg_ready; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dbg_halt_req; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dbg_resume_req; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dec_tlu_debug_mode; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dec_tlu_dbg_halted; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dec_tlu_mpc_halted_only; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dec_tlu_resume_ack; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dmi_reg_en; // @[el2_swerv.scala 323:19]
|
|
wire [6:0] dbg_io_dmi_reg_addr; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dmi_reg_wr_en; // @[el2_swerv.scala 323:19]
|
|
wire [31:0] dbg_io_dmi_reg_wdata; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_sb_axi_awvalid; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_sb_axi_awready; // @[el2_swerv.scala 323:19]
|
|
wire [31:0] dbg_io_sb_axi_awaddr; // @[el2_swerv.scala 323:19]
|
|
wire [3:0] dbg_io_sb_axi_awregion; // @[el2_swerv.scala 323:19]
|
|
wire [2:0] dbg_io_sb_axi_awsize; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_sb_axi_wvalid; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_sb_axi_wready; // @[el2_swerv.scala 323:19]
|
|
wire [63:0] dbg_io_sb_axi_wdata; // @[el2_swerv.scala 323:19]
|
|
wire [7:0] dbg_io_sb_axi_wstrb; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_sb_axi_bvalid; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_sb_axi_bready; // @[el2_swerv.scala 323:19]
|
|
wire [1:0] dbg_io_sb_axi_bresp; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_sb_axi_arvalid; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_sb_axi_arready; // @[el2_swerv.scala 323:19]
|
|
wire [31:0] dbg_io_sb_axi_araddr; // @[el2_swerv.scala 323:19]
|
|
wire [3:0] dbg_io_sb_axi_arregion; // @[el2_swerv.scala 323:19]
|
|
wire [2:0] dbg_io_sb_axi_arsize; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_sb_axi_rvalid; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_sb_axi_rready; // @[el2_swerv.scala 323:19]
|
|
wire [63:0] dbg_io_sb_axi_rdata; // @[el2_swerv.scala 323:19]
|
|
wire [1:0] dbg_io_sb_axi_rresp; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dbg_bus_clk_en; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_dbg_rst_l; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_clk_override; // @[el2_swerv.scala 323:19]
|
|
wire dbg_io_scan_mode; // @[el2_swerv.scala 323:19]
|
|
wire exu_clock; // @[el2_swerv.scala 324:19]
|
|
wire exu_reset; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_scan_mode; // @[el2_swerv.scala 324:19]
|
|
wire [1:0] exu_io_dec_data_en; // @[el2_swerv.scala 324:19]
|
|
wire [1:0] exu_io_dec_ctl_en; // @[el2_swerv.scala 324:19]
|
|
wire [31:0] exu_io_dbg_cmd_wrdata; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_land; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_lor; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_lxor; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_sll; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_srl; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_sra; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_beq; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_bne; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_blt; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_bge; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_add; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_sub; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_slt; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_unsign; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_jal; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_predict_t; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_predict_nt; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_csr_write; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_i0_ap_csr_imm; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_debug_wdata_rs1_d; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_predict_p_d_valid; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_predict_p_d_bits_pc4; // @[el2_swerv.scala 324:19]
|
|
wire [1:0] exu_io_dec_i0_predict_p_d_bits_hist; // @[el2_swerv.scala 324:19]
|
|
wire [11:0] exu_io_dec_i0_predict_p_d_bits_toffset; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_predict_p_d_bits_br_error; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_swerv.scala 324:19]
|
|
wire [30:0] exu_io_dec_i0_predict_p_d_bits_prett; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_predict_p_d_bits_pcall; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_predict_p_d_bits_pret; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_predict_p_d_bits_pja; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_predict_p_d_bits_way; // @[el2_swerv.scala 324:19]
|
|
wire [7:0] exu_io_i0_predict_fghr_d; // @[el2_swerv.scala 324:19]
|
|
wire [7:0] exu_io_i0_predict_index_d; // @[el2_swerv.scala 324:19]
|
|
wire [4:0] exu_io_i0_predict_btag_d; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_rs1_en_d; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_rs2_en_d; // @[el2_swerv.scala 324:19]
|
|
wire [31:0] exu_io_gpr_i0_rs1_d; // @[el2_swerv.scala 324:19]
|
|
wire [31:0] exu_io_gpr_i0_rs2_d; // @[el2_swerv.scala 324:19]
|
|
wire [31:0] exu_io_dec_i0_immed_d; // @[el2_swerv.scala 324:19]
|
|
wire [31:0] exu_io_dec_i0_rs1_bypass_data_d; // @[el2_swerv.scala 324:19]
|
|
wire [31:0] exu_io_dec_i0_rs2_bypass_data_d; // @[el2_swerv.scala 324:19]
|
|
wire [11:0] exu_io_dec_i0_br_immed_d; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_i0_select_pc_d; // @[el2_swerv.scala 324:19]
|
|
wire [30:0] exu_io_dec_i0_pc_d; // @[el2_swerv.scala 324:19]
|
|
wire [1:0] exu_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 324:19]
|
|
wire [1:0] exu_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_csr_ren_d; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_mul_p_valid; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_mul_p_bits_rs1_sign; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_mul_p_bits_rs2_sign; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_mul_p_bits_low; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_div_p_valid; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_div_p_bits_unsign; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_div_p_bits_rem; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_div_cancel; // @[el2_swerv.scala 324:19]
|
|
wire [30:0] exu_io_pred_correct_npc_x; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 324:19]
|
|
wire [30:0] exu_io_dec_tlu_flush_path_r; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_dec_extint_stall; // @[el2_swerv.scala 324:19]
|
|
wire [29:0] exu_io_dec_tlu_meihap; // @[el2_swerv.scala 324:19]
|
|
wire [31:0] exu_io_exu_lsu_rs1_d; // @[el2_swerv.scala 324:19]
|
|
wire [31:0] exu_io_exu_lsu_rs2_d; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_flush_final; // @[el2_swerv.scala 324:19]
|
|
wire [30:0] exu_io_exu_flush_path_final; // @[el2_swerv.scala 324:19]
|
|
wire [31:0] exu_io_exu_i0_result_x; // @[el2_swerv.scala 324:19]
|
|
wire [30:0] exu_io_exu_i0_pc_x; // @[el2_swerv.scala 324:19]
|
|
wire [31:0] exu_io_exu_csr_rs1_x; // @[el2_swerv.scala 324:19]
|
|
wire [30:0] exu_io_exu_npc_r; // @[el2_swerv.scala 324:19]
|
|
wire [1:0] exu_io_exu_i0_br_hist_r; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_i0_br_error_r; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_i0_br_start_error_r; // @[el2_swerv.scala 324:19]
|
|
wire [7:0] exu_io_exu_i0_br_index_r; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_i0_br_valid_r; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_i0_br_mp_r; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_i0_br_middle_r; // @[el2_swerv.scala 324:19]
|
|
wire [7:0] exu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_i0_br_way_r; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_mp_pkt_bits_boffset; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 324:19]
|
|
wire [1:0] exu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 324:19]
|
|
wire [11:0] exu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_mp_pkt_bits_pcall; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_mp_pkt_bits_pret; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_mp_pkt_bits_pja; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_mp_pkt_bits_way; // @[el2_swerv.scala 324:19]
|
|
wire [7:0] exu_io_exu_mp_eghr; // @[el2_swerv.scala 324:19]
|
|
wire [7:0] exu_io_exu_mp_fghr; // @[el2_swerv.scala 324:19]
|
|
wire [7:0] exu_io_exu_mp_index; // @[el2_swerv.scala 324:19]
|
|
wire [4:0] exu_io_exu_mp_btag; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_pmu_i0_br_misp; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_pmu_i0_br_ataken; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_pmu_i0_pc4; // @[el2_swerv.scala 324:19]
|
|
wire [31:0] exu_io_exu_div_result; // @[el2_swerv.scala 324:19]
|
|
wire exu_io_exu_div_wren; // @[el2_swerv.scala 324:19]
|
|
wire lsu_clock; // @[el2_swerv.scala 325:19]
|
|
wire lsu_reset; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_clk_override; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dec_tlu_force_halt; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dec_tlu_external_ldfwd_disable; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dec_tlu_wb_coalescing_disable; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dec_tlu_sideeffect_posted_disable; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_exu_lsu_rs1_d; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_exu_lsu_rs2_d; // @[el2_swerv.scala 325:19]
|
|
wire [11:0] lsu_io_dec_lsu_offset_d; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_p_valid; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_p_bits_fast_int; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_p_bits_by; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_p_bits_half; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_p_bits_word; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_p_bits_load; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_p_bits_store; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_p_bits_unsign; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_0_match_pkt; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_1_match_pkt; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_2_match_pkt; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_3_match_pkt; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dec_lsu_valid_raw_d; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_lsu_result_m; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_lsu_result_corr_r; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_load_stall_any; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_store_stall_any; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_fastint_stall_any; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_idle_any; // @[el2_swerv.scala 325:19]
|
|
wire [30:0] lsu_io_lsu_fir_addr; // @[el2_swerv.scala 325:19]
|
|
wire [1:0] lsu_io_lsu_fir_error; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_single_ecc_error_incr; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_error_pkt_r_valid; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_swerv.scala 325:19]
|
|
wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_imprecise_error_load_any; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_imprecise_error_store_any; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_lsu_imprecise_error_addr_any; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_nonblock_load_valid_m; // @[el2_swerv.scala 325:19]
|
|
wire [1:0] lsu_io_lsu_nonblock_load_tag_m; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_nonblock_load_inv_r; // @[el2_swerv.scala 325:19]
|
|
wire [1:0] lsu_io_lsu_nonblock_load_inv_tag_r; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_nonblock_load_data_valid; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_nonblock_load_data_error; // @[el2_swerv.scala 325:19]
|
|
wire [1:0] lsu_io_lsu_nonblock_load_data_tag; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_lsu_nonblock_load_data; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_pmu_load_external_m; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_pmu_store_external_m; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_pmu_bus_trxn; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_pmu_bus_misaligned; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_pmu_bus_error; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_pmu_bus_busy; // @[el2_swerv.scala 325:19]
|
|
wire [3:0] lsu_io_lsu_trigger_match_m; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dccm_wren; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dccm_rden; // @[el2_swerv.scala 325:19]
|
|
wire [15:0] lsu_io_dccm_wr_addr_lo; // @[el2_swerv.scala 325:19]
|
|
wire [15:0] lsu_io_dccm_wr_addr_hi; // @[el2_swerv.scala 325:19]
|
|
wire [15:0] lsu_io_dccm_rd_addr_lo; // @[el2_swerv.scala 325:19]
|
|
wire [15:0] lsu_io_dccm_rd_addr_hi; // @[el2_swerv.scala 325:19]
|
|
wire [38:0] lsu_io_dccm_wr_data_lo; // @[el2_swerv.scala 325:19]
|
|
wire [38:0] lsu_io_dccm_wr_data_hi; // @[el2_swerv.scala 325:19]
|
|
wire [38:0] lsu_io_dccm_rd_data_lo; // @[el2_swerv.scala 325:19]
|
|
wire [38:0] lsu_io_dccm_rd_data_hi; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_picm_wren; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_picm_rden; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_picm_mken; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_picm_rdaddr; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_picm_wraddr; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_picm_wr_data; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_picm_rd_data; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_axi_awvalid; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_axi_awready; // @[el2_swerv.scala 325:19]
|
|
wire [2:0] lsu_io_lsu_axi_awid; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_lsu_axi_awaddr; // @[el2_swerv.scala 325:19]
|
|
wire [3:0] lsu_io_lsu_axi_awregion; // @[el2_swerv.scala 325:19]
|
|
wire [2:0] lsu_io_lsu_axi_awsize; // @[el2_swerv.scala 325:19]
|
|
wire [3:0] lsu_io_lsu_axi_awcache; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_axi_wvalid; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_axi_wready; // @[el2_swerv.scala 325:19]
|
|
wire [63:0] lsu_io_lsu_axi_wdata; // @[el2_swerv.scala 325:19]
|
|
wire [7:0] lsu_io_lsu_axi_wstrb; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_axi_bvalid; // @[el2_swerv.scala 325:19]
|
|
wire [1:0] lsu_io_lsu_axi_bresp; // @[el2_swerv.scala 325:19]
|
|
wire [2:0] lsu_io_lsu_axi_bid; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_axi_arvalid; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_axi_arready; // @[el2_swerv.scala 325:19]
|
|
wire [2:0] lsu_io_lsu_axi_arid; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_lsu_axi_araddr; // @[el2_swerv.scala 325:19]
|
|
wire [3:0] lsu_io_lsu_axi_arregion; // @[el2_swerv.scala 325:19]
|
|
wire [2:0] lsu_io_lsu_axi_arsize; // @[el2_swerv.scala 325:19]
|
|
wire [3:0] lsu_io_lsu_axi_arcache; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_axi_rvalid; // @[el2_swerv.scala 325:19]
|
|
wire [63:0] lsu_io_lsu_axi_rdata; // @[el2_swerv.scala 325:19]
|
|
wire [2:0] lsu_io_lsu_axi_rid; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_lsu_bus_clk_en; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dma_dccm_req; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dma_mem_write; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dccm_dma_rvalid; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dccm_dma_ecc_error; // @[el2_swerv.scala 325:19]
|
|
wire [2:0] lsu_io_dma_mem_tag; // @[el2_swerv.scala 325:19]
|
|
wire [31:0] lsu_io_dma_mem_addr; // @[el2_swerv.scala 325:19]
|
|
wire [2:0] lsu_io_dma_mem_sz; // @[el2_swerv.scala 325:19]
|
|
wire [63:0] lsu_io_dma_mem_wdata; // @[el2_swerv.scala 325:19]
|
|
wire [2:0] lsu_io_dccm_dma_rtag; // @[el2_swerv.scala 325:19]
|
|
wire [63:0] lsu_io_dccm_dma_rdata; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_dccm_ready; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_scan_mode; // @[el2_swerv.scala 325:19]
|
|
wire lsu_io_free_clk; // @[el2_swerv.scala 325:19]
|
|
wire pic_ctrl_inst_clock; // @[el2_swerv.scala 326:29]
|
|
wire pic_ctrl_inst_reset; // @[el2_swerv.scala 326:29]
|
|
wire pic_ctrl_inst_io_scan_mode; // @[el2_swerv.scala 326:29]
|
|
wire pic_ctrl_inst_io_free_clk; // @[el2_swerv.scala 326:29]
|
|
wire pic_ctrl_inst_io_active_clk; // @[el2_swerv.scala 326:29]
|
|
wire pic_ctrl_inst_io_clk_override; // @[el2_swerv.scala 326:29]
|
|
wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[el2_swerv.scala 326:29]
|
|
wire [31:0] pic_ctrl_inst_io_picm_rdaddr; // @[el2_swerv.scala 326:29]
|
|
wire [31:0] pic_ctrl_inst_io_picm_wraddr; // @[el2_swerv.scala 326:29]
|
|
wire [31:0] pic_ctrl_inst_io_picm_wr_data; // @[el2_swerv.scala 326:29]
|
|
wire pic_ctrl_inst_io_picm_wren; // @[el2_swerv.scala 326:29]
|
|
wire pic_ctrl_inst_io_picm_rden; // @[el2_swerv.scala 326:29]
|
|
wire pic_ctrl_inst_io_picm_mken; // @[el2_swerv.scala 326:29]
|
|
wire [3:0] pic_ctrl_inst_io_meicurpl; // @[el2_swerv.scala 326:29]
|
|
wire [3:0] pic_ctrl_inst_io_meipt; // @[el2_swerv.scala 326:29]
|
|
wire pic_ctrl_inst_io_mexintpend; // @[el2_swerv.scala 326:29]
|
|
wire [7:0] pic_ctrl_inst_io_claimid; // @[el2_swerv.scala 326:29]
|
|
wire [3:0] pic_ctrl_inst_io_pl; // @[el2_swerv.scala 326:29]
|
|
wire [31:0] pic_ctrl_inst_io_picm_rd_data; // @[el2_swerv.scala 326:29]
|
|
wire pic_ctrl_inst_io_mhwakeup; // @[el2_swerv.scala 326:29]
|
|
wire dma_ctrl_clock; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_reset; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_free_clk; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_bus_clk_en; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_clk_override; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_scan_mode; // @[el2_swerv.scala 327:24]
|
|
wire [31:0] dma_ctrl_io_dbg_cmd_addr; // @[el2_swerv.scala 327:24]
|
|
wire [31:0] dma_ctrl_io_dbg_cmd_wrdata; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dbg_cmd_valid; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dbg_cmd_write; // @[el2_swerv.scala 327:24]
|
|
wire [1:0] dma_ctrl_io_dbg_cmd_type; // @[el2_swerv.scala 327:24]
|
|
wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dbg_dma_bubble; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_dbg_ready; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_dbg_cmd_done; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_dbg_cmd_fail; // @[el2_swerv.scala 327:24]
|
|
wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_dccm_req; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_iccm_req; // @[el2_swerv.scala 327:24]
|
|
wire [2:0] dma_ctrl_io_dma_mem_tag; // @[el2_swerv.scala 327:24]
|
|
wire [31:0] dma_ctrl_io_dma_mem_addr; // @[el2_swerv.scala 327:24]
|
|
wire [2:0] dma_ctrl_io_dma_mem_sz; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_mem_write; // @[el2_swerv.scala 327:24]
|
|
wire [63:0] dma_ctrl_io_dma_mem_wdata; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dccm_dma_rvalid; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dccm_dma_ecc_error; // @[el2_swerv.scala 327:24]
|
|
wire [2:0] dma_ctrl_io_dccm_dma_rtag; // @[el2_swerv.scala 327:24]
|
|
wire [63:0] dma_ctrl_io_dccm_dma_rdata; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_iccm_dma_rvalid; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_iccm_dma_ecc_error; // @[el2_swerv.scala 327:24]
|
|
wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[el2_swerv.scala 327:24]
|
|
wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_dccm_stall_any; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_iccm_stall_any; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dccm_ready; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_iccm_ready; // @[el2_swerv.scala 327:24]
|
|
wire [2:0] dma_ctrl_io_dec_tlu_dma_qos_prty; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_pmu_dccm_read; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_pmu_dccm_write; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_pmu_any_read; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_pmu_any_write; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_awvalid; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_awready; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_awid; // @[el2_swerv.scala 327:24]
|
|
wire [31:0] dma_ctrl_io_dma_axi_awaddr; // @[el2_swerv.scala 327:24]
|
|
wire [2:0] dma_ctrl_io_dma_axi_awsize; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_wvalid; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_wready; // @[el2_swerv.scala 327:24]
|
|
wire [63:0] dma_ctrl_io_dma_axi_wdata; // @[el2_swerv.scala 327:24]
|
|
wire [7:0] dma_ctrl_io_dma_axi_wstrb; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_bvalid; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_bready; // @[el2_swerv.scala 327:24]
|
|
wire [1:0] dma_ctrl_io_dma_axi_bresp; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_bid; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_arvalid; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_arready; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_arid; // @[el2_swerv.scala 327:24]
|
|
wire [31:0] dma_ctrl_io_dma_axi_araddr; // @[el2_swerv.scala 327:24]
|
|
wire [2:0] dma_ctrl_io_dma_axi_arsize; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_rvalid; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_rready; // @[el2_swerv.scala 327:24]
|
|
wire dma_ctrl_io_dma_axi_rid; // @[el2_swerv.scala 327:24]
|
|
wire [63:0] dma_ctrl_io_dma_axi_rdata; // @[el2_swerv.scala 327:24]
|
|
wire [1:0] dma_ctrl_io_dma_axi_rresp; // @[el2_swerv.scala 327:24]
|
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
|
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
|
|
wire _T_1 = dbg_io_dbg_core_rst_l; // @[el2_swerv.scala 332:67]
|
|
wire _T_2 = _T_1 | io_scan_mode; // @[el2_swerv.scala 332:70]
|
|
wire _T_5 = ~dec_io_dec_pause_state_cg; // @[el2_swerv.scala 333:23]
|
|
wire _T_6 = _T_5 | dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 333:50]
|
|
el2_ifu ifu ( // @[el2_swerv.scala 321:19]
|
|
.clock(ifu_clock),
|
|
.reset(ifu_reset),
|
|
.io_free_clk(ifu_io_free_clk),
|
|
.io_active_clk(ifu_io_active_clk),
|
|
.io_dec_i0_decode_d(ifu_io_dec_i0_decode_d),
|
|
.io_exu_flush_final(ifu_io_exu_flush_final),
|
|
.io_dec_tlu_i0_commit_cmt(ifu_io_dec_tlu_i0_commit_cmt),
|
|
.io_dec_tlu_flush_err_wb(ifu_io_dec_tlu_flush_err_wb),
|
|
.io_dec_tlu_flush_noredir_wb(ifu_io_dec_tlu_flush_noredir_wb),
|
|
.io_exu_flush_path_final(ifu_io_exu_flush_path_final),
|
|
.io_dec_tlu_mrac_ff(ifu_io_dec_tlu_mrac_ff),
|
|
.io_dec_tlu_fence_i_wb(ifu_io_dec_tlu_fence_i_wb),
|
|
.io_dec_tlu_flush_leak_one_wb(ifu_io_dec_tlu_flush_leak_one_wb),
|
|
.io_dec_tlu_bpred_disable(ifu_io_dec_tlu_bpred_disable),
|
|
.io_dec_tlu_core_ecc_disable(ifu_io_dec_tlu_core_ecc_disable),
|
|
.io_dec_tlu_force_halt(ifu_io_dec_tlu_force_halt),
|
|
.io_ifu_axi_arvalid(ifu_io_ifu_axi_arvalid),
|
|
.io_ifu_axi_arready(ifu_io_ifu_axi_arready),
|
|
.io_ifu_axi_arid(ifu_io_ifu_axi_arid),
|
|
.io_ifu_axi_araddr(ifu_io_ifu_axi_araddr),
|
|
.io_ifu_axi_arregion(ifu_io_ifu_axi_arregion),
|
|
.io_ifu_axi_rvalid(ifu_io_ifu_axi_rvalid),
|
|
.io_ifu_axi_rid(ifu_io_ifu_axi_rid),
|
|
.io_ifu_axi_rdata(ifu_io_ifu_axi_rdata),
|
|
.io_ifu_axi_rresp(ifu_io_ifu_axi_rresp),
|
|
.io_ifu_bus_clk_en(ifu_io_ifu_bus_clk_en),
|
|
.io_dma_iccm_req(ifu_io_dma_iccm_req),
|
|
.io_dma_mem_addr(ifu_io_dma_mem_addr),
|
|
.io_dma_mem_sz(ifu_io_dma_mem_sz),
|
|
.io_dma_mem_write(ifu_io_dma_mem_write),
|
|
.io_dma_mem_wdata(ifu_io_dma_mem_wdata),
|
|
.io_dma_mem_tag(ifu_io_dma_mem_tag),
|
|
.io_dma_iccm_stall_any(ifu_io_dma_iccm_stall_any),
|
|
.io_iccm_dma_ecc_error(ifu_io_iccm_dma_ecc_error),
|
|
.io_iccm_dma_rvalid(ifu_io_iccm_dma_rvalid),
|
|
.io_iccm_dma_rdata(ifu_io_iccm_dma_rdata),
|
|
.io_iccm_dma_rtag(ifu_io_iccm_dma_rtag),
|
|
.io_iccm_ready(ifu_io_iccm_ready),
|
|
.io_ifu_pmu_instr_aligned(ifu_io_ifu_pmu_instr_aligned),
|
|
.io_ifu_pmu_fetch_stall(ifu_io_ifu_pmu_fetch_stall),
|
|
.io_ifu_ic_error_start(ifu_io_ifu_ic_error_start),
|
|
.io_ic_rw_addr(ifu_io_ic_rw_addr),
|
|
.io_ic_wr_en(ifu_io_ic_wr_en),
|
|
.io_ic_rd_en(ifu_io_ic_rd_en),
|
|
.io_ic_wr_data_0(ifu_io_ic_wr_data_0),
|
|
.io_ic_wr_data_1(ifu_io_ic_wr_data_1),
|
|
.io_ic_rd_data(ifu_io_ic_rd_data),
|
|
.io_ic_debug_rd_data(ifu_io_ic_debug_rd_data),
|
|
.io_ictag_debug_rd_data(ifu_io_ictag_debug_rd_data),
|
|
.io_ic_debug_wr_data(ifu_io_ic_debug_wr_data),
|
|
.io_ifu_ic_debug_rd_data(ifu_io_ifu_ic_debug_rd_data),
|
|
.io_ic_eccerr(ifu_io_ic_eccerr),
|
|
.io_ic_premux_data(ifu_io_ic_premux_data),
|
|
.io_ic_sel_premux_data(ifu_io_ic_sel_premux_data),
|
|
.io_ic_debug_addr(ifu_io_ic_debug_addr),
|
|
.io_ic_debug_rd_en(ifu_io_ic_debug_rd_en),
|
|
.io_ic_debug_wr_en(ifu_io_ic_debug_wr_en),
|
|
.io_ic_debug_tag_array(ifu_io_ic_debug_tag_array),
|
|
.io_ic_debug_way(ifu_io_ic_debug_way),
|
|
.io_ic_tag_valid(ifu_io_ic_tag_valid),
|
|
.io_ic_rd_hit(ifu_io_ic_rd_hit),
|
|
.io_ic_tag_perr(ifu_io_ic_tag_perr),
|
|
.io_iccm_rw_addr(ifu_io_iccm_rw_addr),
|
|
.io_iccm_wren(ifu_io_iccm_wren),
|
|
.io_iccm_rden(ifu_io_iccm_rden),
|
|
.io_iccm_wr_data(ifu_io_iccm_wr_data),
|
|
.io_iccm_wr_size(ifu_io_iccm_wr_size),
|
|
.io_iccm_rd_data(ifu_io_iccm_rd_data),
|
|
.io_iccm_rd_data_ecc(ifu_io_iccm_rd_data_ecc),
|
|
.io_ifu_iccm_rd_ecc_single_err(ifu_io_ifu_iccm_rd_ecc_single_err),
|
|
.io_ifu_pmu_ic_miss(ifu_io_ifu_pmu_ic_miss),
|
|
.io_ifu_pmu_ic_hit(ifu_io_ifu_pmu_ic_hit),
|
|
.io_ifu_pmu_bus_error(ifu_io_ifu_pmu_bus_error),
|
|
.io_ifu_pmu_bus_busy(ifu_io_ifu_pmu_bus_busy),
|
|
.io_ifu_pmu_bus_trxn(ifu_io_ifu_pmu_bus_trxn),
|
|
.io_ifu_i0_icaf(ifu_io_ifu_i0_icaf),
|
|
.io_ifu_i0_icaf_type(ifu_io_ifu_i0_icaf_type),
|
|
.io_ifu_i0_valid(ifu_io_ifu_i0_valid),
|
|
.io_ifu_i0_icaf_f1(ifu_io_ifu_i0_icaf_f1),
|
|
.io_ifu_i0_dbecc(ifu_io_ifu_i0_dbecc),
|
|
.io_iccm_dma_sb_error(ifu_io_iccm_dma_sb_error),
|
|
.io_ifu_i0_instr(ifu_io_ifu_i0_instr),
|
|
.io_ifu_i0_pc(ifu_io_ifu_i0_pc),
|
|
.io_ifu_i0_pc4(ifu_io_ifu_i0_pc4),
|
|
.io_ifu_miss_state_idle(ifu_io_ifu_miss_state_idle),
|
|
.io_i0_brp_valid(ifu_io_i0_brp_valid),
|
|
.io_i0_brp_toffset(ifu_io_i0_brp_toffset),
|
|
.io_i0_brp_hist(ifu_io_i0_brp_hist),
|
|
.io_i0_brp_br_error(ifu_io_i0_brp_br_error),
|
|
.io_i0_brp_br_start_error(ifu_io_i0_brp_br_start_error),
|
|
.io_i0_brp_prett(ifu_io_i0_brp_prett),
|
|
.io_i0_brp_way(ifu_io_i0_brp_way),
|
|
.io_i0_brp_ret(ifu_io_i0_brp_ret),
|
|
.io_ifu_i0_bp_index(ifu_io_ifu_i0_bp_index),
|
|
.io_ifu_i0_bp_fghr(ifu_io_ifu_i0_bp_fghr),
|
|
.io_ifu_i0_bp_btag(ifu_io_ifu_i0_bp_btag),
|
|
.io_exu_mp_pkt_bits_misp(ifu_io_exu_mp_pkt_bits_misp),
|
|
.io_exu_mp_pkt_bits_ataken(ifu_io_exu_mp_pkt_bits_ataken),
|
|
.io_exu_mp_pkt_bits_boffset(ifu_io_exu_mp_pkt_bits_boffset),
|
|
.io_exu_mp_pkt_bits_pc4(ifu_io_exu_mp_pkt_bits_pc4),
|
|
.io_exu_mp_pkt_bits_hist(ifu_io_exu_mp_pkt_bits_hist),
|
|
.io_exu_mp_pkt_bits_toffset(ifu_io_exu_mp_pkt_bits_toffset),
|
|
.io_exu_mp_pkt_bits_pcall(ifu_io_exu_mp_pkt_bits_pcall),
|
|
.io_exu_mp_pkt_bits_pret(ifu_io_exu_mp_pkt_bits_pret),
|
|
.io_exu_mp_pkt_bits_pja(ifu_io_exu_mp_pkt_bits_pja),
|
|
.io_exu_mp_pkt_bits_way(ifu_io_exu_mp_pkt_bits_way),
|
|
.io_exu_mp_eghr(ifu_io_exu_mp_eghr),
|
|
.io_exu_mp_fghr(ifu_io_exu_mp_fghr),
|
|
.io_exu_mp_index(ifu_io_exu_mp_index),
|
|
.io_exu_mp_btag(ifu_io_exu_mp_btag),
|
|
.io_dec_tlu_br0_r_pkt_valid(ifu_io_dec_tlu_br0_r_pkt_valid),
|
|
.io_dec_tlu_br0_r_pkt_hist(ifu_io_dec_tlu_br0_r_pkt_hist),
|
|
.io_dec_tlu_br0_r_pkt_br_error(ifu_io_dec_tlu_br0_r_pkt_br_error),
|
|
.io_dec_tlu_br0_r_pkt_br_start_error(ifu_io_dec_tlu_br0_r_pkt_br_start_error),
|
|
.io_dec_tlu_br0_r_pkt_way(ifu_io_dec_tlu_br0_r_pkt_way),
|
|
.io_dec_tlu_br0_r_pkt_middle(ifu_io_dec_tlu_br0_r_pkt_middle),
|
|
.io_exu_i0_br_fghr_r(ifu_io_exu_i0_br_fghr_r),
|
|
.io_exu_i0_br_index_r(ifu_io_exu_i0_br_index_r),
|
|
.io_dec_tlu_flush_lower_wb(ifu_io_dec_tlu_flush_lower_wb),
|
|
.io_ifu_i0_cinst(ifu_io_ifu_i0_cinst),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wrdata(ifu_io_dec_tlu_ic_diag_pkt_icache_wrdata),
|
|
.io_dec_tlu_ic_diag_pkt_icache_dicawics(ifu_io_dec_tlu_ic_diag_pkt_icache_dicawics),
|
|
.io_dec_tlu_ic_diag_pkt_icache_rd_valid(ifu_io_dec_tlu_ic_diag_pkt_icache_rd_valid),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wr_valid(ifu_io_dec_tlu_ic_diag_pkt_icache_wr_valid),
|
|
.io_ifu_ic_debug_rd_data_valid(ifu_io_ifu_ic_debug_rd_data_valid),
|
|
.io_iccm_buf_correct_ecc(ifu_io_iccm_buf_correct_ecc),
|
|
.io_iccm_correction_state(ifu_io_iccm_correction_state),
|
|
.io_scan_mode(ifu_io_scan_mode)
|
|
);
|
|
el2_dec dec ( // @[el2_swerv.scala 322:19]
|
|
.clock(dec_clock),
|
|
.reset(dec_reset),
|
|
.io_free_clk(dec_io_free_clk),
|
|
.io_active_clk(dec_io_active_clk),
|
|
.io_lsu_fastint_stall_any(dec_io_lsu_fastint_stall_any),
|
|
.io_dec_extint_stall(dec_io_dec_extint_stall),
|
|
.io_dec_i0_decode_d(dec_io_dec_i0_decode_d),
|
|
.io_dec_pause_state_cg(dec_io_dec_pause_state_cg),
|
|
.io_rst_vec(dec_io_rst_vec),
|
|
.io_nmi_int(dec_io_nmi_int),
|
|
.io_nmi_vec(dec_io_nmi_vec),
|
|
.io_i_cpu_halt_req(dec_io_i_cpu_halt_req),
|
|
.io_i_cpu_run_req(dec_io_i_cpu_run_req),
|
|
.io_o_cpu_halt_status(dec_io_o_cpu_halt_status),
|
|
.io_o_cpu_halt_ack(dec_io_o_cpu_halt_ack),
|
|
.io_o_cpu_run_ack(dec_io_o_cpu_run_ack),
|
|
.io_o_debug_mode_status(dec_io_o_debug_mode_status),
|
|
.io_core_id(dec_io_core_id),
|
|
.io_mpc_debug_halt_req(dec_io_mpc_debug_halt_req),
|
|
.io_mpc_debug_run_req(dec_io_mpc_debug_run_req),
|
|
.io_mpc_reset_run_req(dec_io_mpc_reset_run_req),
|
|
.io_mpc_debug_halt_ack(dec_io_mpc_debug_halt_ack),
|
|
.io_mpc_debug_run_ack(dec_io_mpc_debug_run_ack),
|
|
.io_debug_brkpt_status(dec_io_debug_brkpt_status),
|
|
.io_exu_pmu_i0_br_misp(dec_io_exu_pmu_i0_br_misp),
|
|
.io_exu_pmu_i0_br_ataken(dec_io_exu_pmu_i0_br_ataken),
|
|
.io_exu_pmu_i0_pc4(dec_io_exu_pmu_i0_pc4),
|
|
.io_lsu_nonblock_load_valid_m(dec_io_lsu_nonblock_load_valid_m),
|
|
.io_lsu_nonblock_load_tag_m(dec_io_lsu_nonblock_load_tag_m),
|
|
.io_lsu_nonblock_load_inv_r(dec_io_lsu_nonblock_load_inv_r),
|
|
.io_lsu_nonblock_load_inv_tag_r(dec_io_lsu_nonblock_load_inv_tag_r),
|
|
.io_lsu_nonblock_load_data_valid(dec_io_lsu_nonblock_load_data_valid),
|
|
.io_lsu_nonblock_load_data_error(dec_io_lsu_nonblock_load_data_error),
|
|
.io_lsu_nonblock_load_data_tag(dec_io_lsu_nonblock_load_data_tag),
|
|
.io_lsu_nonblock_load_data(dec_io_lsu_nonblock_load_data),
|
|
.io_lsu_pmu_bus_trxn(dec_io_lsu_pmu_bus_trxn),
|
|
.io_lsu_pmu_bus_misaligned(dec_io_lsu_pmu_bus_misaligned),
|
|
.io_lsu_pmu_bus_error(dec_io_lsu_pmu_bus_error),
|
|
.io_lsu_pmu_bus_busy(dec_io_lsu_pmu_bus_busy),
|
|
.io_lsu_pmu_load_external_m(dec_io_lsu_pmu_load_external_m),
|
|
.io_lsu_pmu_store_external_m(dec_io_lsu_pmu_store_external_m),
|
|
.io_dma_pmu_dccm_read(dec_io_dma_pmu_dccm_read),
|
|
.io_dma_pmu_dccm_write(dec_io_dma_pmu_dccm_write),
|
|
.io_dma_pmu_any_read(dec_io_dma_pmu_any_read),
|
|
.io_dma_pmu_any_write(dec_io_dma_pmu_any_write),
|
|
.io_lsu_fir_addr(dec_io_lsu_fir_addr),
|
|
.io_lsu_fir_error(dec_io_lsu_fir_error),
|
|
.io_ifu_pmu_instr_aligned(dec_io_ifu_pmu_instr_aligned),
|
|
.io_ifu_pmu_fetch_stall(dec_io_ifu_pmu_fetch_stall),
|
|
.io_ifu_pmu_ic_miss(dec_io_ifu_pmu_ic_miss),
|
|
.io_ifu_pmu_ic_hit(dec_io_ifu_pmu_ic_hit),
|
|
.io_ifu_pmu_bus_error(dec_io_ifu_pmu_bus_error),
|
|
.io_ifu_pmu_bus_busy(dec_io_ifu_pmu_bus_busy),
|
|
.io_ifu_pmu_bus_trxn(dec_io_ifu_pmu_bus_trxn),
|
|
.io_ifu_ic_error_start(dec_io_ifu_ic_error_start),
|
|
.io_ifu_iccm_rd_ecc_single_err(dec_io_ifu_iccm_rd_ecc_single_err),
|
|
.io_lsu_trigger_match_m(dec_io_lsu_trigger_match_m),
|
|
.io_dbg_cmd_valid(dec_io_dbg_cmd_valid),
|
|
.io_dbg_cmd_write(dec_io_dbg_cmd_write),
|
|
.io_dbg_cmd_type(dec_io_dbg_cmd_type),
|
|
.io_dbg_cmd_addr(dec_io_dbg_cmd_addr),
|
|
.io_dbg_cmd_wrdata(dec_io_dbg_cmd_wrdata),
|
|
.io_ifu_i0_icaf(dec_io_ifu_i0_icaf),
|
|
.io_ifu_i0_icaf_type(dec_io_ifu_i0_icaf_type),
|
|
.io_ifu_i0_icaf_f1(dec_io_ifu_i0_icaf_f1),
|
|
.io_ifu_i0_dbecc(dec_io_ifu_i0_dbecc),
|
|
.io_lsu_idle_any(dec_io_lsu_idle_any),
|
|
.io_i0_brp_valid(dec_io_i0_brp_valid),
|
|
.io_i0_brp_toffset(dec_io_i0_brp_toffset),
|
|
.io_i0_brp_hist(dec_io_i0_brp_hist),
|
|
.io_i0_brp_br_error(dec_io_i0_brp_br_error),
|
|
.io_i0_brp_br_start_error(dec_io_i0_brp_br_start_error),
|
|
.io_i0_brp_prett(dec_io_i0_brp_prett),
|
|
.io_i0_brp_way(dec_io_i0_brp_way),
|
|
.io_i0_brp_ret(dec_io_i0_brp_ret),
|
|
.io_ifu_i0_bp_index(dec_io_ifu_i0_bp_index),
|
|
.io_ifu_i0_bp_fghr(dec_io_ifu_i0_bp_fghr),
|
|
.io_ifu_i0_bp_btag(dec_io_ifu_i0_bp_btag),
|
|
.io_lsu_error_pkt_r_valid(dec_io_lsu_error_pkt_r_valid),
|
|
.io_lsu_error_pkt_r_bits_single_ecc_error(dec_io_lsu_error_pkt_r_bits_single_ecc_error),
|
|
.io_lsu_error_pkt_r_bits_inst_type(dec_io_lsu_error_pkt_r_bits_inst_type),
|
|
.io_lsu_error_pkt_r_bits_exc_type(dec_io_lsu_error_pkt_r_bits_exc_type),
|
|
.io_lsu_error_pkt_r_bits_mscause(dec_io_lsu_error_pkt_r_bits_mscause),
|
|
.io_lsu_error_pkt_r_bits_addr(dec_io_lsu_error_pkt_r_bits_addr),
|
|
.io_lsu_single_ecc_error_incr(dec_io_lsu_single_ecc_error_incr),
|
|
.io_lsu_imprecise_error_load_any(dec_io_lsu_imprecise_error_load_any),
|
|
.io_lsu_imprecise_error_store_any(dec_io_lsu_imprecise_error_store_any),
|
|
.io_lsu_imprecise_error_addr_any(dec_io_lsu_imprecise_error_addr_any),
|
|
.io_exu_div_result(dec_io_exu_div_result),
|
|
.io_exu_div_wren(dec_io_exu_div_wren),
|
|
.io_exu_csr_rs1_x(dec_io_exu_csr_rs1_x),
|
|
.io_lsu_result_m(dec_io_lsu_result_m),
|
|
.io_lsu_result_corr_r(dec_io_lsu_result_corr_r),
|
|
.io_lsu_load_stall_any(dec_io_lsu_load_stall_any),
|
|
.io_lsu_store_stall_any(dec_io_lsu_store_stall_any),
|
|
.io_dma_dccm_stall_any(dec_io_dma_dccm_stall_any),
|
|
.io_dma_iccm_stall_any(dec_io_dma_iccm_stall_any),
|
|
.io_iccm_dma_sb_error(dec_io_iccm_dma_sb_error),
|
|
.io_exu_flush_final(dec_io_exu_flush_final),
|
|
.io_exu_npc_r(dec_io_exu_npc_r),
|
|
.io_exu_i0_result_x(dec_io_exu_i0_result_x),
|
|
.io_ifu_i0_valid(dec_io_ifu_i0_valid),
|
|
.io_ifu_i0_instr(dec_io_ifu_i0_instr),
|
|
.io_ifu_i0_pc(dec_io_ifu_i0_pc),
|
|
.io_ifu_i0_pc4(dec_io_ifu_i0_pc4),
|
|
.io_exu_i0_pc_x(dec_io_exu_i0_pc_x),
|
|
.io_mexintpend(dec_io_mexintpend),
|
|
.io_timer_int(dec_io_timer_int),
|
|
.io_soft_int(dec_io_soft_int),
|
|
.io_pic_claimid(dec_io_pic_claimid),
|
|
.io_pic_pl(dec_io_pic_pl),
|
|
.io_mhwakeup(dec_io_mhwakeup),
|
|
.io_dec_tlu_meicurpl(dec_io_dec_tlu_meicurpl),
|
|
.io_dec_tlu_meipt(dec_io_dec_tlu_meipt),
|
|
.io_ifu_ic_debug_rd_data(dec_io_ifu_ic_debug_rd_data),
|
|
.io_ifu_ic_debug_rd_data_valid(dec_io_ifu_ic_debug_rd_data_valid),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wrdata(dec_io_dec_tlu_ic_diag_pkt_icache_wrdata),
|
|
.io_dec_tlu_ic_diag_pkt_icache_dicawics(dec_io_dec_tlu_ic_diag_pkt_icache_dicawics),
|
|
.io_dec_tlu_ic_diag_pkt_icache_rd_valid(dec_io_dec_tlu_ic_diag_pkt_icache_rd_valid),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wr_valid(dec_io_dec_tlu_ic_diag_pkt_icache_wr_valid),
|
|
.io_dbg_halt_req(dec_io_dbg_halt_req),
|
|
.io_dbg_resume_req(dec_io_dbg_resume_req),
|
|
.io_ifu_miss_state_idle(dec_io_ifu_miss_state_idle),
|
|
.io_dec_tlu_dbg_halted(dec_io_dec_tlu_dbg_halted),
|
|
.io_dec_tlu_debug_mode(dec_io_dec_tlu_debug_mode),
|
|
.io_dec_tlu_resume_ack(dec_io_dec_tlu_resume_ack),
|
|
.io_dec_tlu_flush_noredir_r(dec_io_dec_tlu_flush_noredir_r),
|
|
.io_dec_tlu_mpc_halted_only(dec_io_dec_tlu_mpc_halted_only),
|
|
.io_dec_tlu_flush_leak_one_r(dec_io_dec_tlu_flush_leak_one_r),
|
|
.io_dec_tlu_flush_err_r(dec_io_dec_tlu_flush_err_r),
|
|
.io_dec_tlu_meihap(dec_io_dec_tlu_meihap),
|
|
.io_dec_debug_wdata_rs1_d(dec_io_dec_debug_wdata_rs1_d),
|
|
.io_dec_dbg_rddata(dec_io_dec_dbg_rddata),
|
|
.io_dec_dbg_cmd_done(dec_io_dec_dbg_cmd_done),
|
|
.io_dec_dbg_cmd_fail(dec_io_dec_dbg_cmd_fail),
|
|
.io_trigger_pkt_any_0_select(dec_io_trigger_pkt_any_0_select),
|
|
.io_trigger_pkt_any_0_match_pkt(dec_io_trigger_pkt_any_0_match_pkt),
|
|
.io_trigger_pkt_any_0_store(dec_io_trigger_pkt_any_0_store),
|
|
.io_trigger_pkt_any_0_load(dec_io_trigger_pkt_any_0_load),
|
|
.io_trigger_pkt_any_0_tdata2(dec_io_trigger_pkt_any_0_tdata2),
|
|
.io_trigger_pkt_any_1_select(dec_io_trigger_pkt_any_1_select),
|
|
.io_trigger_pkt_any_1_match_pkt(dec_io_trigger_pkt_any_1_match_pkt),
|
|
.io_trigger_pkt_any_1_store(dec_io_trigger_pkt_any_1_store),
|
|
.io_trigger_pkt_any_1_load(dec_io_trigger_pkt_any_1_load),
|
|
.io_trigger_pkt_any_1_tdata2(dec_io_trigger_pkt_any_1_tdata2),
|
|
.io_trigger_pkt_any_2_select(dec_io_trigger_pkt_any_2_select),
|
|
.io_trigger_pkt_any_2_match_pkt(dec_io_trigger_pkt_any_2_match_pkt),
|
|
.io_trigger_pkt_any_2_store(dec_io_trigger_pkt_any_2_store),
|
|
.io_trigger_pkt_any_2_load(dec_io_trigger_pkt_any_2_load),
|
|
.io_trigger_pkt_any_2_tdata2(dec_io_trigger_pkt_any_2_tdata2),
|
|
.io_trigger_pkt_any_3_select(dec_io_trigger_pkt_any_3_select),
|
|
.io_trigger_pkt_any_3_match_pkt(dec_io_trigger_pkt_any_3_match_pkt),
|
|
.io_trigger_pkt_any_3_store(dec_io_trigger_pkt_any_3_store),
|
|
.io_trigger_pkt_any_3_load(dec_io_trigger_pkt_any_3_load),
|
|
.io_trigger_pkt_any_3_tdata2(dec_io_trigger_pkt_any_3_tdata2),
|
|
.io_dec_tlu_force_halt(dec_io_dec_tlu_force_halt),
|
|
.io_exu_i0_br_hist_r(dec_io_exu_i0_br_hist_r),
|
|
.io_exu_i0_br_error_r(dec_io_exu_i0_br_error_r),
|
|
.io_exu_i0_br_start_error_r(dec_io_exu_i0_br_start_error_r),
|
|
.io_exu_i0_br_valid_r(dec_io_exu_i0_br_valid_r),
|
|
.io_exu_i0_br_mp_r(dec_io_exu_i0_br_mp_r),
|
|
.io_exu_i0_br_middle_r(dec_io_exu_i0_br_middle_r),
|
|
.io_exu_i0_br_way_r(dec_io_exu_i0_br_way_r),
|
|
.io_dec_i0_rs1_en_d(dec_io_dec_i0_rs1_en_d),
|
|
.io_dec_i0_rs2_en_d(dec_io_dec_i0_rs2_en_d),
|
|
.io_gpr_i0_rs1_d(dec_io_gpr_i0_rs1_d),
|
|
.io_gpr_i0_rs2_d(dec_io_gpr_i0_rs2_d),
|
|
.io_dec_i0_immed_d(dec_io_dec_i0_immed_d),
|
|
.io_dec_i0_br_immed_d(dec_io_dec_i0_br_immed_d),
|
|
.io_i0_ap_land(dec_io_i0_ap_land),
|
|
.io_i0_ap_lor(dec_io_i0_ap_lor),
|
|
.io_i0_ap_lxor(dec_io_i0_ap_lxor),
|
|
.io_i0_ap_sll(dec_io_i0_ap_sll),
|
|
.io_i0_ap_srl(dec_io_i0_ap_srl),
|
|
.io_i0_ap_sra(dec_io_i0_ap_sra),
|
|
.io_i0_ap_beq(dec_io_i0_ap_beq),
|
|
.io_i0_ap_bne(dec_io_i0_ap_bne),
|
|
.io_i0_ap_blt(dec_io_i0_ap_blt),
|
|
.io_i0_ap_bge(dec_io_i0_ap_bge),
|
|
.io_i0_ap_add(dec_io_i0_ap_add),
|
|
.io_i0_ap_sub(dec_io_i0_ap_sub),
|
|
.io_i0_ap_slt(dec_io_i0_ap_slt),
|
|
.io_i0_ap_unsign(dec_io_i0_ap_unsign),
|
|
.io_i0_ap_jal(dec_io_i0_ap_jal),
|
|
.io_i0_ap_predict_t(dec_io_i0_ap_predict_t),
|
|
.io_i0_ap_predict_nt(dec_io_i0_ap_predict_nt),
|
|
.io_i0_ap_csr_write(dec_io_i0_ap_csr_write),
|
|
.io_i0_ap_csr_imm(dec_io_i0_ap_csr_imm),
|
|
.io_dec_i0_alu_decode_d(dec_io_dec_i0_alu_decode_d),
|
|
.io_dec_i0_select_pc_d(dec_io_dec_i0_select_pc_d),
|
|
.io_dec_i0_pc_d(dec_io_dec_i0_pc_d),
|
|
.io_dec_i0_rs1_bypass_en_d(dec_io_dec_i0_rs1_bypass_en_d),
|
|
.io_dec_i0_rs2_bypass_en_d(dec_io_dec_i0_rs2_bypass_en_d),
|
|
.io_dec_i0_rs1_bypass_data_d(dec_io_dec_i0_rs1_bypass_data_d),
|
|
.io_dec_i0_rs2_bypass_data_d(dec_io_dec_i0_rs2_bypass_data_d),
|
|
.io_lsu_p_valid(dec_io_lsu_p_valid),
|
|
.io_lsu_p_bits_fast_int(dec_io_lsu_p_bits_fast_int),
|
|
.io_lsu_p_bits_by(dec_io_lsu_p_bits_by),
|
|
.io_lsu_p_bits_half(dec_io_lsu_p_bits_half),
|
|
.io_lsu_p_bits_word(dec_io_lsu_p_bits_word),
|
|
.io_lsu_p_bits_load(dec_io_lsu_p_bits_load),
|
|
.io_lsu_p_bits_store(dec_io_lsu_p_bits_store),
|
|
.io_lsu_p_bits_unsign(dec_io_lsu_p_bits_unsign),
|
|
.io_lsu_p_bits_store_data_bypass_d(dec_io_lsu_p_bits_store_data_bypass_d),
|
|
.io_lsu_p_bits_load_ldst_bypass_d(dec_io_lsu_p_bits_load_ldst_bypass_d),
|
|
.io_mul_p_valid(dec_io_mul_p_valid),
|
|
.io_mul_p_bits_rs1_sign(dec_io_mul_p_bits_rs1_sign),
|
|
.io_mul_p_bits_rs2_sign(dec_io_mul_p_bits_rs2_sign),
|
|
.io_mul_p_bits_low(dec_io_mul_p_bits_low),
|
|
.io_div_p_valid(dec_io_div_p_valid),
|
|
.io_div_p_bits_unsign(dec_io_div_p_bits_unsign),
|
|
.io_div_p_bits_rem(dec_io_div_p_bits_rem),
|
|
.io_dec_div_cancel(dec_io_dec_div_cancel),
|
|
.io_dec_lsu_offset_d(dec_io_dec_lsu_offset_d),
|
|
.io_dec_csr_ren_d(dec_io_dec_csr_ren_d),
|
|
.io_dec_tlu_flush_lower_r(dec_io_dec_tlu_flush_lower_r),
|
|
.io_dec_tlu_flush_path_r(dec_io_dec_tlu_flush_path_r),
|
|
.io_dec_tlu_i0_kill_writeb_r(dec_io_dec_tlu_i0_kill_writeb_r),
|
|
.io_dec_tlu_fence_i_r(dec_io_dec_tlu_fence_i_r),
|
|
.io_pred_correct_npc_x(dec_io_pred_correct_npc_x),
|
|
.io_dec_tlu_br0_r_pkt_valid(dec_io_dec_tlu_br0_r_pkt_valid),
|
|
.io_dec_tlu_br0_r_pkt_hist(dec_io_dec_tlu_br0_r_pkt_hist),
|
|
.io_dec_tlu_br0_r_pkt_br_error(dec_io_dec_tlu_br0_r_pkt_br_error),
|
|
.io_dec_tlu_br0_r_pkt_br_start_error(dec_io_dec_tlu_br0_r_pkt_br_start_error),
|
|
.io_dec_tlu_br0_r_pkt_way(dec_io_dec_tlu_br0_r_pkt_way),
|
|
.io_dec_tlu_br0_r_pkt_middle(dec_io_dec_tlu_br0_r_pkt_middle),
|
|
.io_dec_tlu_perfcnt0(dec_io_dec_tlu_perfcnt0),
|
|
.io_dec_tlu_perfcnt1(dec_io_dec_tlu_perfcnt1),
|
|
.io_dec_tlu_perfcnt2(dec_io_dec_tlu_perfcnt2),
|
|
.io_dec_tlu_perfcnt3(dec_io_dec_tlu_perfcnt3),
|
|
.io_dec_i0_predict_p_d_valid(dec_io_dec_i0_predict_p_d_valid),
|
|
.io_dec_i0_predict_p_d_bits_pc4(dec_io_dec_i0_predict_p_d_bits_pc4),
|
|
.io_dec_i0_predict_p_d_bits_hist(dec_io_dec_i0_predict_p_d_bits_hist),
|
|
.io_dec_i0_predict_p_d_bits_toffset(dec_io_dec_i0_predict_p_d_bits_toffset),
|
|
.io_dec_i0_predict_p_d_bits_br_error(dec_io_dec_i0_predict_p_d_bits_br_error),
|
|
.io_dec_i0_predict_p_d_bits_br_start_error(dec_io_dec_i0_predict_p_d_bits_br_start_error),
|
|
.io_dec_i0_predict_p_d_bits_prett(dec_io_dec_i0_predict_p_d_bits_prett),
|
|
.io_dec_i0_predict_p_d_bits_pcall(dec_io_dec_i0_predict_p_d_bits_pcall),
|
|
.io_dec_i0_predict_p_d_bits_pret(dec_io_dec_i0_predict_p_d_bits_pret),
|
|
.io_dec_i0_predict_p_d_bits_pja(dec_io_dec_i0_predict_p_d_bits_pja),
|
|
.io_dec_i0_predict_p_d_bits_way(dec_io_dec_i0_predict_p_d_bits_way),
|
|
.io_i0_predict_fghr_d(dec_io_i0_predict_fghr_d),
|
|
.io_i0_predict_index_d(dec_io_i0_predict_index_d),
|
|
.io_i0_predict_btag_d(dec_io_i0_predict_btag_d),
|
|
.io_dec_lsu_valid_raw_d(dec_io_dec_lsu_valid_raw_d),
|
|
.io_dec_tlu_mrac_ff(dec_io_dec_tlu_mrac_ff),
|
|
.io_dec_data_en(dec_io_dec_data_en),
|
|
.io_dec_ctl_en(dec_io_dec_ctl_en),
|
|
.io_ifu_i0_cinst(dec_io_ifu_i0_cinst),
|
|
.io_rv_trace_pkt_rv_i_valid_ip(dec_io_rv_trace_pkt_rv_i_valid_ip),
|
|
.io_rv_trace_pkt_rv_i_insn_ip(dec_io_rv_trace_pkt_rv_i_insn_ip),
|
|
.io_rv_trace_pkt_rv_i_address_ip(dec_io_rv_trace_pkt_rv_i_address_ip),
|
|
.io_rv_trace_pkt_rv_i_exception_ip(dec_io_rv_trace_pkt_rv_i_exception_ip),
|
|
.io_rv_trace_pkt_rv_i_ecause_ip(dec_io_rv_trace_pkt_rv_i_ecause_ip),
|
|
.io_rv_trace_pkt_rv_i_interrupt_ip(dec_io_rv_trace_pkt_rv_i_interrupt_ip),
|
|
.io_rv_trace_pkt_rv_i_tval_ip(dec_io_rv_trace_pkt_rv_i_tval_ip),
|
|
.io_dec_tlu_external_ldfwd_disable(dec_io_dec_tlu_external_ldfwd_disable),
|
|
.io_dec_tlu_sideeffect_posted_disable(dec_io_dec_tlu_sideeffect_posted_disable),
|
|
.io_dec_tlu_core_ecc_disable(dec_io_dec_tlu_core_ecc_disable),
|
|
.io_dec_tlu_bpred_disable(dec_io_dec_tlu_bpred_disable),
|
|
.io_dec_tlu_wb_coalescing_disable(dec_io_dec_tlu_wb_coalescing_disable),
|
|
.io_dec_tlu_dma_qos_prty(dec_io_dec_tlu_dma_qos_prty),
|
|
.io_dec_tlu_misc_clk_override(dec_io_dec_tlu_misc_clk_override),
|
|
.io_dec_tlu_lsu_clk_override(dec_io_dec_tlu_lsu_clk_override),
|
|
.io_dec_tlu_pic_clk_override(dec_io_dec_tlu_pic_clk_override),
|
|
.io_dec_tlu_dccm_clk_override(dec_io_dec_tlu_dccm_clk_override),
|
|
.io_dec_tlu_icm_clk_override(dec_io_dec_tlu_icm_clk_override),
|
|
.io_dec_tlu_i0_commit_cmt(dec_io_dec_tlu_i0_commit_cmt),
|
|
.io_scan_mode(dec_io_scan_mode)
|
|
);
|
|
el2_dbg dbg ( // @[el2_swerv.scala 323:19]
|
|
.clock(dbg_clock),
|
|
.reset(dbg_reset),
|
|
.io_dbg_cmd_addr(dbg_io_dbg_cmd_addr),
|
|
.io_dbg_cmd_wrdata(dbg_io_dbg_cmd_wrdata),
|
|
.io_dbg_cmd_valid(dbg_io_dbg_cmd_valid),
|
|
.io_dbg_cmd_write(dbg_io_dbg_cmd_write),
|
|
.io_dbg_cmd_type(dbg_io_dbg_cmd_type),
|
|
.io_dbg_cmd_size(dbg_io_dbg_cmd_size),
|
|
.io_dbg_core_rst_l(dbg_io_dbg_core_rst_l),
|
|
.io_core_dbg_rddata(dbg_io_core_dbg_rddata),
|
|
.io_core_dbg_cmd_done(dbg_io_core_dbg_cmd_done),
|
|
.io_core_dbg_cmd_fail(dbg_io_core_dbg_cmd_fail),
|
|
.io_dbg_dma_bubble(dbg_io_dbg_dma_bubble),
|
|
.io_dma_dbg_ready(dbg_io_dma_dbg_ready),
|
|
.io_dbg_halt_req(dbg_io_dbg_halt_req),
|
|
.io_dbg_resume_req(dbg_io_dbg_resume_req),
|
|
.io_dec_tlu_debug_mode(dbg_io_dec_tlu_debug_mode),
|
|
.io_dec_tlu_dbg_halted(dbg_io_dec_tlu_dbg_halted),
|
|
.io_dec_tlu_mpc_halted_only(dbg_io_dec_tlu_mpc_halted_only),
|
|
.io_dec_tlu_resume_ack(dbg_io_dec_tlu_resume_ack),
|
|
.io_dmi_reg_en(dbg_io_dmi_reg_en),
|
|
.io_dmi_reg_addr(dbg_io_dmi_reg_addr),
|
|
.io_dmi_reg_wr_en(dbg_io_dmi_reg_wr_en),
|
|
.io_dmi_reg_wdata(dbg_io_dmi_reg_wdata),
|
|
.io_sb_axi_awvalid(dbg_io_sb_axi_awvalid),
|
|
.io_sb_axi_awready(dbg_io_sb_axi_awready),
|
|
.io_sb_axi_awaddr(dbg_io_sb_axi_awaddr),
|
|
.io_sb_axi_awregion(dbg_io_sb_axi_awregion),
|
|
.io_sb_axi_awsize(dbg_io_sb_axi_awsize),
|
|
.io_sb_axi_wvalid(dbg_io_sb_axi_wvalid),
|
|
.io_sb_axi_wready(dbg_io_sb_axi_wready),
|
|
.io_sb_axi_wdata(dbg_io_sb_axi_wdata),
|
|
.io_sb_axi_wstrb(dbg_io_sb_axi_wstrb),
|
|
.io_sb_axi_bvalid(dbg_io_sb_axi_bvalid),
|
|
.io_sb_axi_bready(dbg_io_sb_axi_bready),
|
|
.io_sb_axi_bresp(dbg_io_sb_axi_bresp),
|
|
.io_sb_axi_arvalid(dbg_io_sb_axi_arvalid),
|
|
.io_sb_axi_arready(dbg_io_sb_axi_arready),
|
|
.io_sb_axi_araddr(dbg_io_sb_axi_araddr),
|
|
.io_sb_axi_arregion(dbg_io_sb_axi_arregion),
|
|
.io_sb_axi_arsize(dbg_io_sb_axi_arsize),
|
|
.io_sb_axi_rvalid(dbg_io_sb_axi_rvalid),
|
|
.io_sb_axi_rready(dbg_io_sb_axi_rready),
|
|
.io_sb_axi_rdata(dbg_io_sb_axi_rdata),
|
|
.io_sb_axi_rresp(dbg_io_sb_axi_rresp),
|
|
.io_dbg_bus_clk_en(dbg_io_dbg_bus_clk_en),
|
|
.io_dbg_rst_l(dbg_io_dbg_rst_l),
|
|
.io_clk_override(dbg_io_clk_override),
|
|
.io_scan_mode(dbg_io_scan_mode)
|
|
);
|
|
el2_exu exu ( // @[el2_swerv.scala 324:19]
|
|
.clock(exu_clock),
|
|
.reset(exu_reset),
|
|
.io_scan_mode(exu_io_scan_mode),
|
|
.io_dec_data_en(exu_io_dec_data_en),
|
|
.io_dec_ctl_en(exu_io_dec_ctl_en),
|
|
.io_dbg_cmd_wrdata(exu_io_dbg_cmd_wrdata),
|
|
.io_i0_ap_land(exu_io_i0_ap_land),
|
|
.io_i0_ap_lor(exu_io_i0_ap_lor),
|
|
.io_i0_ap_lxor(exu_io_i0_ap_lxor),
|
|
.io_i0_ap_sll(exu_io_i0_ap_sll),
|
|
.io_i0_ap_srl(exu_io_i0_ap_srl),
|
|
.io_i0_ap_sra(exu_io_i0_ap_sra),
|
|
.io_i0_ap_beq(exu_io_i0_ap_beq),
|
|
.io_i0_ap_bne(exu_io_i0_ap_bne),
|
|
.io_i0_ap_blt(exu_io_i0_ap_blt),
|
|
.io_i0_ap_bge(exu_io_i0_ap_bge),
|
|
.io_i0_ap_add(exu_io_i0_ap_add),
|
|
.io_i0_ap_sub(exu_io_i0_ap_sub),
|
|
.io_i0_ap_slt(exu_io_i0_ap_slt),
|
|
.io_i0_ap_unsign(exu_io_i0_ap_unsign),
|
|
.io_i0_ap_jal(exu_io_i0_ap_jal),
|
|
.io_i0_ap_predict_t(exu_io_i0_ap_predict_t),
|
|
.io_i0_ap_predict_nt(exu_io_i0_ap_predict_nt),
|
|
.io_i0_ap_csr_write(exu_io_i0_ap_csr_write),
|
|
.io_i0_ap_csr_imm(exu_io_i0_ap_csr_imm),
|
|
.io_dec_debug_wdata_rs1_d(exu_io_dec_debug_wdata_rs1_d),
|
|
.io_dec_i0_predict_p_d_valid(exu_io_dec_i0_predict_p_d_valid),
|
|
.io_dec_i0_predict_p_d_bits_pc4(exu_io_dec_i0_predict_p_d_bits_pc4),
|
|
.io_dec_i0_predict_p_d_bits_hist(exu_io_dec_i0_predict_p_d_bits_hist),
|
|
.io_dec_i0_predict_p_d_bits_toffset(exu_io_dec_i0_predict_p_d_bits_toffset),
|
|
.io_dec_i0_predict_p_d_bits_br_error(exu_io_dec_i0_predict_p_d_bits_br_error),
|
|
.io_dec_i0_predict_p_d_bits_br_start_error(exu_io_dec_i0_predict_p_d_bits_br_start_error),
|
|
.io_dec_i0_predict_p_d_bits_prett(exu_io_dec_i0_predict_p_d_bits_prett),
|
|
.io_dec_i0_predict_p_d_bits_pcall(exu_io_dec_i0_predict_p_d_bits_pcall),
|
|
.io_dec_i0_predict_p_d_bits_pret(exu_io_dec_i0_predict_p_d_bits_pret),
|
|
.io_dec_i0_predict_p_d_bits_pja(exu_io_dec_i0_predict_p_d_bits_pja),
|
|
.io_dec_i0_predict_p_d_bits_way(exu_io_dec_i0_predict_p_d_bits_way),
|
|
.io_i0_predict_fghr_d(exu_io_i0_predict_fghr_d),
|
|
.io_i0_predict_index_d(exu_io_i0_predict_index_d),
|
|
.io_i0_predict_btag_d(exu_io_i0_predict_btag_d),
|
|
.io_dec_i0_rs1_en_d(exu_io_dec_i0_rs1_en_d),
|
|
.io_dec_i0_rs2_en_d(exu_io_dec_i0_rs2_en_d),
|
|
.io_gpr_i0_rs1_d(exu_io_gpr_i0_rs1_d),
|
|
.io_gpr_i0_rs2_d(exu_io_gpr_i0_rs2_d),
|
|
.io_dec_i0_immed_d(exu_io_dec_i0_immed_d),
|
|
.io_dec_i0_rs1_bypass_data_d(exu_io_dec_i0_rs1_bypass_data_d),
|
|
.io_dec_i0_rs2_bypass_data_d(exu_io_dec_i0_rs2_bypass_data_d),
|
|
.io_dec_i0_br_immed_d(exu_io_dec_i0_br_immed_d),
|
|
.io_dec_i0_alu_decode_d(exu_io_dec_i0_alu_decode_d),
|
|
.io_dec_i0_select_pc_d(exu_io_dec_i0_select_pc_d),
|
|
.io_dec_i0_pc_d(exu_io_dec_i0_pc_d),
|
|
.io_dec_i0_rs1_bypass_en_d(exu_io_dec_i0_rs1_bypass_en_d),
|
|
.io_dec_i0_rs2_bypass_en_d(exu_io_dec_i0_rs2_bypass_en_d),
|
|
.io_dec_csr_ren_d(exu_io_dec_csr_ren_d),
|
|
.io_mul_p_valid(exu_io_mul_p_valid),
|
|
.io_mul_p_bits_rs1_sign(exu_io_mul_p_bits_rs1_sign),
|
|
.io_mul_p_bits_rs2_sign(exu_io_mul_p_bits_rs2_sign),
|
|
.io_mul_p_bits_low(exu_io_mul_p_bits_low),
|
|
.io_div_p_valid(exu_io_div_p_valid),
|
|
.io_div_p_bits_unsign(exu_io_div_p_bits_unsign),
|
|
.io_div_p_bits_rem(exu_io_div_p_bits_rem),
|
|
.io_dec_div_cancel(exu_io_dec_div_cancel),
|
|
.io_pred_correct_npc_x(exu_io_pred_correct_npc_x),
|
|
.io_dec_tlu_flush_lower_r(exu_io_dec_tlu_flush_lower_r),
|
|
.io_dec_tlu_flush_path_r(exu_io_dec_tlu_flush_path_r),
|
|
.io_dec_extint_stall(exu_io_dec_extint_stall),
|
|
.io_dec_tlu_meihap(exu_io_dec_tlu_meihap),
|
|
.io_exu_lsu_rs1_d(exu_io_exu_lsu_rs1_d),
|
|
.io_exu_lsu_rs2_d(exu_io_exu_lsu_rs2_d),
|
|
.io_exu_flush_final(exu_io_exu_flush_final),
|
|
.io_exu_flush_path_final(exu_io_exu_flush_path_final),
|
|
.io_exu_i0_result_x(exu_io_exu_i0_result_x),
|
|
.io_exu_i0_pc_x(exu_io_exu_i0_pc_x),
|
|
.io_exu_csr_rs1_x(exu_io_exu_csr_rs1_x),
|
|
.io_exu_npc_r(exu_io_exu_npc_r),
|
|
.io_exu_i0_br_hist_r(exu_io_exu_i0_br_hist_r),
|
|
.io_exu_i0_br_error_r(exu_io_exu_i0_br_error_r),
|
|
.io_exu_i0_br_start_error_r(exu_io_exu_i0_br_start_error_r),
|
|
.io_exu_i0_br_index_r(exu_io_exu_i0_br_index_r),
|
|
.io_exu_i0_br_valid_r(exu_io_exu_i0_br_valid_r),
|
|
.io_exu_i0_br_mp_r(exu_io_exu_i0_br_mp_r),
|
|
.io_exu_i0_br_middle_r(exu_io_exu_i0_br_middle_r),
|
|
.io_exu_i0_br_fghr_r(exu_io_exu_i0_br_fghr_r),
|
|
.io_exu_i0_br_way_r(exu_io_exu_i0_br_way_r),
|
|
.io_exu_mp_pkt_bits_misp(exu_io_exu_mp_pkt_bits_misp),
|
|
.io_exu_mp_pkt_bits_ataken(exu_io_exu_mp_pkt_bits_ataken),
|
|
.io_exu_mp_pkt_bits_boffset(exu_io_exu_mp_pkt_bits_boffset),
|
|
.io_exu_mp_pkt_bits_pc4(exu_io_exu_mp_pkt_bits_pc4),
|
|
.io_exu_mp_pkt_bits_hist(exu_io_exu_mp_pkt_bits_hist),
|
|
.io_exu_mp_pkt_bits_toffset(exu_io_exu_mp_pkt_bits_toffset),
|
|
.io_exu_mp_pkt_bits_pcall(exu_io_exu_mp_pkt_bits_pcall),
|
|
.io_exu_mp_pkt_bits_pret(exu_io_exu_mp_pkt_bits_pret),
|
|
.io_exu_mp_pkt_bits_pja(exu_io_exu_mp_pkt_bits_pja),
|
|
.io_exu_mp_pkt_bits_way(exu_io_exu_mp_pkt_bits_way),
|
|
.io_exu_mp_eghr(exu_io_exu_mp_eghr),
|
|
.io_exu_mp_fghr(exu_io_exu_mp_fghr),
|
|
.io_exu_mp_index(exu_io_exu_mp_index),
|
|
.io_exu_mp_btag(exu_io_exu_mp_btag),
|
|
.io_exu_pmu_i0_br_misp(exu_io_exu_pmu_i0_br_misp),
|
|
.io_exu_pmu_i0_br_ataken(exu_io_exu_pmu_i0_br_ataken),
|
|
.io_exu_pmu_i0_pc4(exu_io_exu_pmu_i0_pc4),
|
|
.io_exu_div_result(exu_io_exu_div_result),
|
|
.io_exu_div_wren(exu_io_exu_div_wren)
|
|
);
|
|
el2_lsu lsu ( // @[el2_swerv.scala 325:19]
|
|
.clock(lsu_clock),
|
|
.reset(lsu_reset),
|
|
.io_clk_override(lsu_io_clk_override),
|
|
.io_dec_tlu_flush_lower_r(lsu_io_dec_tlu_flush_lower_r),
|
|
.io_dec_tlu_i0_kill_writeb_r(lsu_io_dec_tlu_i0_kill_writeb_r),
|
|
.io_dec_tlu_force_halt(lsu_io_dec_tlu_force_halt),
|
|
.io_dec_tlu_external_ldfwd_disable(lsu_io_dec_tlu_external_ldfwd_disable),
|
|
.io_dec_tlu_wb_coalescing_disable(lsu_io_dec_tlu_wb_coalescing_disable),
|
|
.io_dec_tlu_sideeffect_posted_disable(lsu_io_dec_tlu_sideeffect_posted_disable),
|
|
.io_dec_tlu_core_ecc_disable(lsu_io_dec_tlu_core_ecc_disable),
|
|
.io_exu_lsu_rs1_d(lsu_io_exu_lsu_rs1_d),
|
|
.io_exu_lsu_rs2_d(lsu_io_exu_lsu_rs2_d),
|
|
.io_dec_lsu_offset_d(lsu_io_dec_lsu_offset_d),
|
|
.io_lsu_p_valid(lsu_io_lsu_p_valid),
|
|
.io_lsu_p_bits_fast_int(lsu_io_lsu_p_bits_fast_int),
|
|
.io_lsu_p_bits_by(lsu_io_lsu_p_bits_by),
|
|
.io_lsu_p_bits_half(lsu_io_lsu_p_bits_half),
|
|
.io_lsu_p_bits_word(lsu_io_lsu_p_bits_word),
|
|
.io_lsu_p_bits_load(lsu_io_lsu_p_bits_load),
|
|
.io_lsu_p_bits_store(lsu_io_lsu_p_bits_store),
|
|
.io_lsu_p_bits_unsign(lsu_io_lsu_p_bits_unsign),
|
|
.io_lsu_p_bits_store_data_bypass_d(lsu_io_lsu_p_bits_store_data_bypass_d),
|
|
.io_lsu_p_bits_load_ldst_bypass_d(lsu_io_lsu_p_bits_load_ldst_bypass_d),
|
|
.io_trigger_pkt_any_0_select(lsu_io_trigger_pkt_any_0_select),
|
|
.io_trigger_pkt_any_0_match_pkt(lsu_io_trigger_pkt_any_0_match_pkt),
|
|
.io_trigger_pkt_any_0_store(lsu_io_trigger_pkt_any_0_store),
|
|
.io_trigger_pkt_any_0_load(lsu_io_trigger_pkt_any_0_load),
|
|
.io_trigger_pkt_any_0_tdata2(lsu_io_trigger_pkt_any_0_tdata2),
|
|
.io_trigger_pkt_any_1_select(lsu_io_trigger_pkt_any_1_select),
|
|
.io_trigger_pkt_any_1_match_pkt(lsu_io_trigger_pkt_any_1_match_pkt),
|
|
.io_trigger_pkt_any_1_store(lsu_io_trigger_pkt_any_1_store),
|
|
.io_trigger_pkt_any_1_load(lsu_io_trigger_pkt_any_1_load),
|
|
.io_trigger_pkt_any_1_tdata2(lsu_io_trigger_pkt_any_1_tdata2),
|
|
.io_trigger_pkt_any_2_select(lsu_io_trigger_pkt_any_2_select),
|
|
.io_trigger_pkt_any_2_match_pkt(lsu_io_trigger_pkt_any_2_match_pkt),
|
|
.io_trigger_pkt_any_2_store(lsu_io_trigger_pkt_any_2_store),
|
|
.io_trigger_pkt_any_2_load(lsu_io_trigger_pkt_any_2_load),
|
|
.io_trigger_pkt_any_2_tdata2(lsu_io_trigger_pkt_any_2_tdata2),
|
|
.io_trigger_pkt_any_3_select(lsu_io_trigger_pkt_any_3_select),
|
|
.io_trigger_pkt_any_3_match_pkt(lsu_io_trigger_pkt_any_3_match_pkt),
|
|
.io_trigger_pkt_any_3_store(lsu_io_trigger_pkt_any_3_store),
|
|
.io_trigger_pkt_any_3_load(lsu_io_trigger_pkt_any_3_load),
|
|
.io_trigger_pkt_any_3_tdata2(lsu_io_trigger_pkt_any_3_tdata2),
|
|
.io_dec_lsu_valid_raw_d(lsu_io_dec_lsu_valid_raw_d),
|
|
.io_dec_tlu_mrac_ff(lsu_io_dec_tlu_mrac_ff),
|
|
.io_lsu_result_m(lsu_io_lsu_result_m),
|
|
.io_lsu_result_corr_r(lsu_io_lsu_result_corr_r),
|
|
.io_lsu_load_stall_any(lsu_io_lsu_load_stall_any),
|
|
.io_lsu_store_stall_any(lsu_io_lsu_store_stall_any),
|
|
.io_lsu_fastint_stall_any(lsu_io_lsu_fastint_stall_any),
|
|
.io_lsu_idle_any(lsu_io_lsu_idle_any),
|
|
.io_lsu_fir_addr(lsu_io_lsu_fir_addr),
|
|
.io_lsu_fir_error(lsu_io_lsu_fir_error),
|
|
.io_lsu_single_ecc_error_incr(lsu_io_lsu_single_ecc_error_incr),
|
|
.io_lsu_error_pkt_r_valid(lsu_io_lsu_error_pkt_r_valid),
|
|
.io_lsu_error_pkt_r_bits_single_ecc_error(lsu_io_lsu_error_pkt_r_bits_single_ecc_error),
|
|
.io_lsu_error_pkt_r_bits_inst_type(lsu_io_lsu_error_pkt_r_bits_inst_type),
|
|
.io_lsu_error_pkt_r_bits_exc_type(lsu_io_lsu_error_pkt_r_bits_exc_type),
|
|
.io_lsu_error_pkt_r_bits_mscause(lsu_io_lsu_error_pkt_r_bits_mscause),
|
|
.io_lsu_error_pkt_r_bits_addr(lsu_io_lsu_error_pkt_r_bits_addr),
|
|
.io_lsu_imprecise_error_load_any(lsu_io_lsu_imprecise_error_load_any),
|
|
.io_lsu_imprecise_error_store_any(lsu_io_lsu_imprecise_error_store_any),
|
|
.io_lsu_imprecise_error_addr_any(lsu_io_lsu_imprecise_error_addr_any),
|
|
.io_lsu_nonblock_load_valid_m(lsu_io_lsu_nonblock_load_valid_m),
|
|
.io_lsu_nonblock_load_tag_m(lsu_io_lsu_nonblock_load_tag_m),
|
|
.io_lsu_nonblock_load_inv_r(lsu_io_lsu_nonblock_load_inv_r),
|
|
.io_lsu_nonblock_load_inv_tag_r(lsu_io_lsu_nonblock_load_inv_tag_r),
|
|
.io_lsu_nonblock_load_data_valid(lsu_io_lsu_nonblock_load_data_valid),
|
|
.io_lsu_nonblock_load_data_error(lsu_io_lsu_nonblock_load_data_error),
|
|
.io_lsu_nonblock_load_data_tag(lsu_io_lsu_nonblock_load_data_tag),
|
|
.io_lsu_nonblock_load_data(lsu_io_lsu_nonblock_load_data),
|
|
.io_lsu_pmu_load_external_m(lsu_io_lsu_pmu_load_external_m),
|
|
.io_lsu_pmu_store_external_m(lsu_io_lsu_pmu_store_external_m),
|
|
.io_lsu_pmu_bus_trxn(lsu_io_lsu_pmu_bus_trxn),
|
|
.io_lsu_pmu_bus_misaligned(lsu_io_lsu_pmu_bus_misaligned),
|
|
.io_lsu_pmu_bus_error(lsu_io_lsu_pmu_bus_error),
|
|
.io_lsu_pmu_bus_busy(lsu_io_lsu_pmu_bus_busy),
|
|
.io_lsu_trigger_match_m(lsu_io_lsu_trigger_match_m),
|
|
.io_dccm_wren(lsu_io_dccm_wren),
|
|
.io_dccm_rden(lsu_io_dccm_rden),
|
|
.io_dccm_wr_addr_lo(lsu_io_dccm_wr_addr_lo),
|
|
.io_dccm_wr_addr_hi(lsu_io_dccm_wr_addr_hi),
|
|
.io_dccm_rd_addr_lo(lsu_io_dccm_rd_addr_lo),
|
|
.io_dccm_rd_addr_hi(lsu_io_dccm_rd_addr_hi),
|
|
.io_dccm_wr_data_lo(lsu_io_dccm_wr_data_lo),
|
|
.io_dccm_wr_data_hi(lsu_io_dccm_wr_data_hi),
|
|
.io_dccm_rd_data_lo(lsu_io_dccm_rd_data_lo),
|
|
.io_dccm_rd_data_hi(lsu_io_dccm_rd_data_hi),
|
|
.io_picm_wren(lsu_io_picm_wren),
|
|
.io_picm_rden(lsu_io_picm_rden),
|
|
.io_picm_mken(lsu_io_picm_mken),
|
|
.io_picm_rdaddr(lsu_io_picm_rdaddr),
|
|
.io_picm_wraddr(lsu_io_picm_wraddr),
|
|
.io_picm_wr_data(lsu_io_picm_wr_data),
|
|
.io_picm_rd_data(lsu_io_picm_rd_data),
|
|
.io_lsu_axi_awvalid(lsu_io_lsu_axi_awvalid),
|
|
.io_lsu_axi_awready(lsu_io_lsu_axi_awready),
|
|
.io_lsu_axi_awid(lsu_io_lsu_axi_awid),
|
|
.io_lsu_axi_awaddr(lsu_io_lsu_axi_awaddr),
|
|
.io_lsu_axi_awregion(lsu_io_lsu_axi_awregion),
|
|
.io_lsu_axi_awsize(lsu_io_lsu_axi_awsize),
|
|
.io_lsu_axi_awcache(lsu_io_lsu_axi_awcache),
|
|
.io_lsu_axi_wvalid(lsu_io_lsu_axi_wvalid),
|
|
.io_lsu_axi_wready(lsu_io_lsu_axi_wready),
|
|
.io_lsu_axi_wdata(lsu_io_lsu_axi_wdata),
|
|
.io_lsu_axi_wstrb(lsu_io_lsu_axi_wstrb),
|
|
.io_lsu_axi_bvalid(lsu_io_lsu_axi_bvalid),
|
|
.io_lsu_axi_bresp(lsu_io_lsu_axi_bresp),
|
|
.io_lsu_axi_bid(lsu_io_lsu_axi_bid),
|
|
.io_lsu_axi_arvalid(lsu_io_lsu_axi_arvalid),
|
|
.io_lsu_axi_arready(lsu_io_lsu_axi_arready),
|
|
.io_lsu_axi_arid(lsu_io_lsu_axi_arid),
|
|
.io_lsu_axi_araddr(lsu_io_lsu_axi_araddr),
|
|
.io_lsu_axi_arregion(lsu_io_lsu_axi_arregion),
|
|
.io_lsu_axi_arsize(lsu_io_lsu_axi_arsize),
|
|
.io_lsu_axi_arcache(lsu_io_lsu_axi_arcache),
|
|
.io_lsu_axi_rvalid(lsu_io_lsu_axi_rvalid),
|
|
.io_lsu_axi_rdata(lsu_io_lsu_axi_rdata),
|
|
.io_lsu_axi_rid(lsu_io_lsu_axi_rid),
|
|
.io_lsu_bus_clk_en(lsu_io_lsu_bus_clk_en),
|
|
.io_dma_dccm_req(lsu_io_dma_dccm_req),
|
|
.io_dma_mem_write(lsu_io_dma_mem_write),
|
|
.io_dccm_dma_rvalid(lsu_io_dccm_dma_rvalid),
|
|
.io_dccm_dma_ecc_error(lsu_io_dccm_dma_ecc_error),
|
|
.io_dma_mem_tag(lsu_io_dma_mem_tag),
|
|
.io_dma_mem_addr(lsu_io_dma_mem_addr),
|
|
.io_dma_mem_sz(lsu_io_dma_mem_sz),
|
|
.io_dma_mem_wdata(lsu_io_dma_mem_wdata),
|
|
.io_dccm_dma_rtag(lsu_io_dccm_dma_rtag),
|
|
.io_dccm_dma_rdata(lsu_io_dccm_dma_rdata),
|
|
.io_dccm_ready(lsu_io_dccm_ready),
|
|
.io_scan_mode(lsu_io_scan_mode),
|
|
.io_free_clk(lsu_io_free_clk)
|
|
);
|
|
el2_pic_ctrl pic_ctrl_inst ( // @[el2_swerv.scala 326:29]
|
|
.clock(pic_ctrl_inst_clock),
|
|
.reset(pic_ctrl_inst_reset),
|
|
.io_scan_mode(pic_ctrl_inst_io_scan_mode),
|
|
.io_free_clk(pic_ctrl_inst_io_free_clk),
|
|
.io_active_clk(pic_ctrl_inst_io_active_clk),
|
|
.io_clk_override(pic_ctrl_inst_io_clk_override),
|
|
.io_extintsrc_req(pic_ctrl_inst_io_extintsrc_req),
|
|
.io_picm_rdaddr(pic_ctrl_inst_io_picm_rdaddr),
|
|
.io_picm_wraddr(pic_ctrl_inst_io_picm_wraddr),
|
|
.io_picm_wr_data(pic_ctrl_inst_io_picm_wr_data),
|
|
.io_picm_wren(pic_ctrl_inst_io_picm_wren),
|
|
.io_picm_rden(pic_ctrl_inst_io_picm_rden),
|
|
.io_picm_mken(pic_ctrl_inst_io_picm_mken),
|
|
.io_meicurpl(pic_ctrl_inst_io_meicurpl),
|
|
.io_meipt(pic_ctrl_inst_io_meipt),
|
|
.io_mexintpend(pic_ctrl_inst_io_mexintpend),
|
|
.io_claimid(pic_ctrl_inst_io_claimid),
|
|
.io_pl(pic_ctrl_inst_io_pl),
|
|
.io_picm_rd_data(pic_ctrl_inst_io_picm_rd_data),
|
|
.io_mhwakeup(pic_ctrl_inst_io_mhwakeup)
|
|
);
|
|
el2_dma_ctrl dma_ctrl ( // @[el2_swerv.scala 327:24]
|
|
.clock(dma_ctrl_clock),
|
|
.reset(dma_ctrl_reset),
|
|
.io_free_clk(dma_ctrl_io_free_clk),
|
|
.io_dma_bus_clk_en(dma_ctrl_io_dma_bus_clk_en),
|
|
.io_clk_override(dma_ctrl_io_clk_override),
|
|
.io_scan_mode(dma_ctrl_io_scan_mode),
|
|
.io_dbg_cmd_addr(dma_ctrl_io_dbg_cmd_addr),
|
|
.io_dbg_cmd_wrdata(dma_ctrl_io_dbg_cmd_wrdata),
|
|
.io_dbg_cmd_valid(dma_ctrl_io_dbg_cmd_valid),
|
|
.io_dbg_cmd_write(dma_ctrl_io_dbg_cmd_write),
|
|
.io_dbg_cmd_type(dma_ctrl_io_dbg_cmd_type),
|
|
.io_dbg_cmd_size(dma_ctrl_io_dbg_cmd_size),
|
|
.io_dbg_dma_bubble(dma_ctrl_io_dbg_dma_bubble),
|
|
.io_dma_dbg_ready(dma_ctrl_io_dma_dbg_ready),
|
|
.io_dma_dbg_cmd_done(dma_ctrl_io_dma_dbg_cmd_done),
|
|
.io_dma_dbg_cmd_fail(dma_ctrl_io_dma_dbg_cmd_fail),
|
|
.io_dma_dbg_rddata(dma_ctrl_io_dma_dbg_rddata),
|
|
.io_dma_dccm_req(dma_ctrl_io_dma_dccm_req),
|
|
.io_dma_iccm_req(dma_ctrl_io_dma_iccm_req),
|
|
.io_dma_mem_tag(dma_ctrl_io_dma_mem_tag),
|
|
.io_dma_mem_addr(dma_ctrl_io_dma_mem_addr),
|
|
.io_dma_mem_sz(dma_ctrl_io_dma_mem_sz),
|
|
.io_dma_mem_write(dma_ctrl_io_dma_mem_write),
|
|
.io_dma_mem_wdata(dma_ctrl_io_dma_mem_wdata),
|
|
.io_dccm_dma_rvalid(dma_ctrl_io_dccm_dma_rvalid),
|
|
.io_dccm_dma_ecc_error(dma_ctrl_io_dccm_dma_ecc_error),
|
|
.io_dccm_dma_rtag(dma_ctrl_io_dccm_dma_rtag),
|
|
.io_dccm_dma_rdata(dma_ctrl_io_dccm_dma_rdata),
|
|
.io_iccm_dma_rvalid(dma_ctrl_io_iccm_dma_rvalid),
|
|
.io_iccm_dma_ecc_error(dma_ctrl_io_iccm_dma_ecc_error),
|
|
.io_iccm_dma_rtag(dma_ctrl_io_iccm_dma_rtag),
|
|
.io_iccm_dma_rdata(dma_ctrl_io_iccm_dma_rdata),
|
|
.io_dma_dccm_stall_any(dma_ctrl_io_dma_dccm_stall_any),
|
|
.io_dma_iccm_stall_any(dma_ctrl_io_dma_iccm_stall_any),
|
|
.io_dccm_ready(dma_ctrl_io_dccm_ready),
|
|
.io_iccm_ready(dma_ctrl_io_iccm_ready),
|
|
.io_dec_tlu_dma_qos_prty(dma_ctrl_io_dec_tlu_dma_qos_prty),
|
|
.io_dma_pmu_dccm_read(dma_ctrl_io_dma_pmu_dccm_read),
|
|
.io_dma_pmu_dccm_write(dma_ctrl_io_dma_pmu_dccm_write),
|
|
.io_dma_pmu_any_read(dma_ctrl_io_dma_pmu_any_read),
|
|
.io_dma_pmu_any_write(dma_ctrl_io_dma_pmu_any_write),
|
|
.io_dma_axi_awvalid(dma_ctrl_io_dma_axi_awvalid),
|
|
.io_dma_axi_awready(dma_ctrl_io_dma_axi_awready),
|
|
.io_dma_axi_awid(dma_ctrl_io_dma_axi_awid),
|
|
.io_dma_axi_awaddr(dma_ctrl_io_dma_axi_awaddr),
|
|
.io_dma_axi_awsize(dma_ctrl_io_dma_axi_awsize),
|
|
.io_dma_axi_wvalid(dma_ctrl_io_dma_axi_wvalid),
|
|
.io_dma_axi_wready(dma_ctrl_io_dma_axi_wready),
|
|
.io_dma_axi_wdata(dma_ctrl_io_dma_axi_wdata),
|
|
.io_dma_axi_wstrb(dma_ctrl_io_dma_axi_wstrb),
|
|
.io_dma_axi_bvalid(dma_ctrl_io_dma_axi_bvalid),
|
|
.io_dma_axi_bready(dma_ctrl_io_dma_axi_bready),
|
|
.io_dma_axi_bresp(dma_ctrl_io_dma_axi_bresp),
|
|
.io_dma_axi_bid(dma_ctrl_io_dma_axi_bid),
|
|
.io_dma_axi_arvalid(dma_ctrl_io_dma_axi_arvalid),
|
|
.io_dma_axi_arready(dma_ctrl_io_dma_axi_arready),
|
|
.io_dma_axi_arid(dma_ctrl_io_dma_axi_arid),
|
|
.io_dma_axi_araddr(dma_ctrl_io_dma_axi_araddr),
|
|
.io_dma_axi_arsize(dma_ctrl_io_dma_axi_arsize),
|
|
.io_dma_axi_rvalid(dma_ctrl_io_dma_axi_rvalid),
|
|
.io_dma_axi_rready(dma_ctrl_io_dma_axi_rready),
|
|
.io_dma_axi_rid(dma_ctrl_io_dma_axi_rid),
|
|
.io_dma_axi_rdata(dma_ctrl_io_dma_axi_rdata),
|
|
.io_dma_axi_rresp(dma_ctrl_io_dma_axi_rresp)
|
|
);
|
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_io_l1clk),
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en),
|
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
|
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en),
|
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
|
);
|
|
assign io_core_rst_l = reset & _T_2; // @[el2_swerv.scala 332:17]
|
|
assign io_trace_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[el2_swerv.scala 663:25]
|
|
assign io_trace_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[el2_swerv.scala 664:28]
|
|
assign io_trace_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[el2_swerv.scala 665:26]
|
|
assign io_trace_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[el2_swerv.scala 666:30]
|
|
assign io_trace_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[el2_swerv.scala 667:27]
|
|
assign io_trace_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[el2_swerv.scala 668:30]
|
|
assign io_trace_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[el2_swerv.scala 669:25]
|
|
assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[el2_swerv.scala 673:24]
|
|
assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[el2_swerv.scala 674:23]
|
|
assign io_dec_tlu_core_ecc_disable = dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 675:31]
|
|
assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[el2_swerv.scala 676:21]
|
|
assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[el2_swerv.scala 677:24]
|
|
assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[el2_swerv.scala 678:20]
|
|
assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[el2_swerv.scala 679:26]
|
|
assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[el2_swerv.scala 680:25]
|
|
assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[el2_swerv.scala 681:24]
|
|
assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[el2_swerv.scala 682:25]
|
|
assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[el2_swerv.scala 683:23]
|
|
assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[el2_swerv.scala 684:23]
|
|
assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[el2_swerv.scala 685:23]
|
|
assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[el2_swerv.scala 686:23]
|
|
assign io_dccm_wren = lsu_io_dccm_wren; // @[el2_swerv.scala 688:16]
|
|
assign io_dccm_rden = lsu_io_dccm_rden; // @[el2_swerv.scala 689:16]
|
|
assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[el2_swerv.scala 690:22]
|
|
assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[el2_swerv.scala 691:22]
|
|
assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[el2_swerv.scala 692:22]
|
|
assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[el2_swerv.scala 693:22]
|
|
assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[el2_swerv.scala 694:22]
|
|
assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[el2_swerv.scala 695:22]
|
|
assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[el2_swerv.scala 697:19]
|
|
assign io_iccm_wren = ifu_io_iccm_wren; // @[el2_swerv.scala 698:16]
|
|
assign io_iccm_rden = ifu_io_iccm_rden; // @[el2_swerv.scala 699:16]
|
|
assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[el2_swerv.scala 700:19]
|
|
assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[el2_swerv.scala 701:19]
|
|
assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[el2_swerv.scala 702:27]
|
|
assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[el2_swerv.scala 703:28]
|
|
assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[el2_swerv.scala 704:17]
|
|
assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[el2_swerv.scala 705:19]
|
|
assign io_ic_wr_en = ifu_io_ic_wr_en; // @[el2_swerv.scala 706:15]
|
|
assign io_ic_rd_en = ifu_io_ic_rd_en; // @[el2_swerv.scala 707:15]
|
|
assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[el2_swerv.scala 708:17]
|
|
assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[el2_swerv.scala 708:17]
|
|
assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[el2_swerv.scala 709:23]
|
|
assign io_ic_premux_data = ifu_io_ic_premux_data; // @[el2_swerv.scala 710:21]
|
|
assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[el2_swerv.scala 711:25]
|
|
assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[el2_swerv.scala 712:20]
|
|
assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[el2_swerv.scala 713:21]
|
|
assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[el2_swerv.scala 714:21]
|
|
assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[el2_swerv.scala 715:25]
|
|
assign io_ic_debug_way = ifu_io_ic_debug_way; // @[el2_swerv.scala 716:19]
|
|
assign io_lsu_axi_awvalid = lsu_io_lsu_axi_awvalid; // @[el2_swerv.scala 719:22]
|
|
assign io_lsu_axi_awid = lsu_io_lsu_axi_awid; // @[el2_swerv.scala 720:19]
|
|
assign io_lsu_axi_awaddr = lsu_io_lsu_axi_awaddr; // @[el2_swerv.scala 721:21]
|
|
assign io_lsu_axi_awregion = lsu_io_lsu_axi_awregion; // @[el2_swerv.scala 722:23]
|
|
assign io_lsu_axi_awlen = 8'h0; // @[el2_swerv.scala 723:20]
|
|
assign io_lsu_axi_awsize = lsu_io_lsu_axi_awsize; // @[el2_swerv.scala 724:21]
|
|
assign io_lsu_axi_awburst = 2'h1; // @[el2_swerv.scala 725:22]
|
|
assign io_lsu_axi_awlock = 1'h0; // @[el2_swerv.scala 726:21]
|
|
assign io_lsu_axi_awcache = lsu_io_lsu_axi_awcache; // @[el2_swerv.scala 727:22]
|
|
assign io_lsu_axi_awprot = 3'h0; // @[el2_swerv.scala 728:21]
|
|
assign io_lsu_axi_awqos = 4'h0; // @[el2_swerv.scala 729:20]
|
|
assign io_lsu_axi_wvalid = lsu_io_lsu_axi_wvalid; // @[el2_swerv.scala 730:21]
|
|
assign io_lsu_axi_wdata = lsu_io_lsu_axi_wdata; // @[el2_swerv.scala 731:20]
|
|
assign io_lsu_axi_wstrb = lsu_io_lsu_axi_wstrb; // @[el2_swerv.scala 732:20]
|
|
assign io_lsu_axi_wlast = 1'h1; // @[el2_swerv.scala 733:20]
|
|
assign io_lsu_axi_bready = 1'h1; // @[el2_swerv.scala 734:21]
|
|
assign io_lsu_axi_arvalid = lsu_io_lsu_axi_arvalid; // @[el2_swerv.scala 735:22]
|
|
assign io_lsu_axi_arid = lsu_io_lsu_axi_arid; // @[el2_swerv.scala 736:19]
|
|
assign io_lsu_axi_araddr = lsu_io_lsu_axi_araddr; // @[el2_swerv.scala 737:21]
|
|
assign io_lsu_axi_arregion = lsu_io_lsu_axi_arregion; // @[el2_swerv.scala 738:23]
|
|
assign io_lsu_axi_arlen = 8'h0; // @[el2_swerv.scala 739:20]
|
|
assign io_lsu_axi_arsize = lsu_io_lsu_axi_arsize; // @[el2_swerv.scala 740:21]
|
|
assign io_lsu_axi_arburst = 2'h1; // @[el2_swerv.scala 741:22]
|
|
assign io_lsu_axi_arlock = 1'h0; // @[el2_swerv.scala 742:21]
|
|
assign io_lsu_axi_arcache = lsu_io_lsu_axi_arcache; // @[el2_swerv.scala 743:22]
|
|
assign io_lsu_axi_arprot = 3'h0; // @[el2_swerv.scala 744:21]
|
|
assign io_lsu_axi_arqos = 4'h0; // @[el2_swerv.scala 745:20]
|
|
assign io_lsu_axi_rready = 1'h1; // @[el2_swerv.scala 746:21]
|
|
assign io_ifu_axi_awvalid = 1'h0; // @[el2_swerv.scala 749:22]
|
|
assign io_ifu_axi_awid = 3'h0; // @[el2_swerv.scala 750:19]
|
|
assign io_ifu_axi_awaddr = 32'h0; // @[el2_swerv.scala 751:21]
|
|
assign io_ifu_axi_awregion = 4'h0; // @[el2_swerv.scala 752:23]
|
|
assign io_ifu_axi_awlen = 8'h0; // @[el2_swerv.scala 753:20]
|
|
assign io_ifu_axi_awsize = 3'h0; // @[el2_swerv.scala 754:21]
|
|
assign io_ifu_axi_awburst = 2'h0; // @[el2_swerv.scala 755:22]
|
|
assign io_ifu_axi_awlock = 1'h0; // @[el2_swerv.scala 756:21]
|
|
assign io_ifu_axi_awcache = 4'h0; // @[el2_swerv.scala 757:22]
|
|
assign io_ifu_axi_awprot = 3'h0; // @[el2_swerv.scala 758:21]
|
|
assign io_ifu_axi_awqos = 4'h0; // @[el2_swerv.scala 759:20]
|
|
assign io_ifu_axi_wvalid = 1'h0; // @[el2_swerv.scala 760:21]
|
|
assign io_ifu_axi_wdata = 64'h0; // @[el2_swerv.scala 761:20]
|
|
assign io_ifu_axi_wstrb = 8'h0; // @[el2_swerv.scala 762:20]
|
|
assign io_ifu_axi_wlast = 1'h0; // @[el2_swerv.scala 763:20]
|
|
assign io_ifu_axi_bready = 1'h0; // @[el2_swerv.scala 764:21]
|
|
assign io_ifu_axi_arvalid = ifu_io_ifu_axi_arvalid; // @[el2_swerv.scala 765:22]
|
|
assign io_ifu_axi_arid = ifu_io_ifu_axi_arid; // @[el2_swerv.scala 766:19]
|
|
assign io_ifu_axi_araddr = ifu_io_ifu_axi_araddr; // @[el2_swerv.scala 767:21]
|
|
assign io_ifu_axi_arregion = ifu_io_ifu_axi_arregion; // @[el2_swerv.scala 768:23]
|
|
assign io_ifu_axi_arlen = 8'h0; // @[el2_swerv.scala 769:20]
|
|
assign io_ifu_axi_arsize = 3'h3; // @[el2_swerv.scala 770:21]
|
|
assign io_ifu_axi_arburst = 2'h1; // @[el2_swerv.scala 771:22]
|
|
assign io_ifu_axi_arlock = 1'h0; // @[el2_swerv.scala 772:21]
|
|
assign io_ifu_axi_arcache = 4'hf; // @[el2_swerv.scala 773:22]
|
|
assign io_ifu_axi_arprot = 3'h0; // @[el2_swerv.scala 774:21]
|
|
assign io_ifu_axi_arqos = 4'h0; // @[el2_swerv.scala 775:20]
|
|
assign io_ifu_axi_rready = 1'h1; // @[el2_swerv.scala 776:21]
|
|
assign io_sb_axi_awvalid = dbg_io_sb_axi_awvalid; // @[el2_swerv.scala 780:21]
|
|
assign io_sb_axi_awid = 1'h0; // @[el2_swerv.scala 781:18]
|
|
assign io_sb_axi_awaddr = dbg_io_sb_axi_awaddr; // @[el2_swerv.scala 782:20]
|
|
assign io_sb_axi_awregion = dbg_io_sb_axi_awregion; // @[el2_swerv.scala 783:22]
|
|
assign io_sb_axi_awlen = 8'h0; // @[el2_swerv.scala 784:19]
|
|
assign io_sb_axi_awsize = dbg_io_sb_axi_awsize; // @[el2_swerv.scala 785:20]
|
|
assign io_sb_axi_awburst = 2'h1; // @[el2_swerv.scala 786:21]
|
|
assign io_sb_axi_awlock = 1'h0; // @[el2_swerv.scala 787:20]
|
|
assign io_sb_axi_awcache = 4'hf; // @[el2_swerv.scala 788:21]
|
|
assign io_sb_axi_awprot = 3'h0; // @[el2_swerv.scala 789:20]
|
|
assign io_sb_axi_awqos = 4'h0; // @[el2_swerv.scala 790:19]
|
|
assign io_sb_axi_wvalid = dbg_io_sb_axi_wvalid; // @[el2_swerv.scala 791:20]
|
|
assign io_sb_axi_wdata = dbg_io_sb_axi_wdata; // @[el2_swerv.scala 792:19]
|
|
assign io_sb_axi_wstrb = dbg_io_sb_axi_wstrb; // @[el2_swerv.scala 793:19]
|
|
assign io_sb_axi_wlast = 1'h1; // @[el2_swerv.scala 794:19]
|
|
assign io_sb_axi_bready = 1'h1; // @[el2_swerv.scala 795:20]
|
|
assign io_sb_axi_arvalid = dbg_io_sb_axi_arvalid; // @[el2_swerv.scala 796:21]
|
|
assign io_sb_axi_arid = 1'h0; // @[el2_swerv.scala 797:18]
|
|
assign io_sb_axi_araddr = dbg_io_sb_axi_araddr; // @[el2_swerv.scala 798:20]
|
|
assign io_sb_axi_arregion = dbg_io_sb_axi_arregion; // @[el2_swerv.scala 799:22]
|
|
assign io_sb_axi_arlen = 8'h0; // @[el2_swerv.scala 800:19]
|
|
assign io_sb_axi_arsize = dbg_io_sb_axi_arsize; // @[el2_swerv.scala 801:20]
|
|
assign io_sb_axi_arburst = 2'h1; // @[el2_swerv.scala 802:21]
|
|
assign io_sb_axi_arlock = 1'h0; // @[el2_swerv.scala 803:20]
|
|
assign io_sb_axi_arcache = 4'h0; // @[el2_swerv.scala 804:21]
|
|
assign io_sb_axi_arprot = 3'h0; // @[el2_swerv.scala 805:20]
|
|
assign io_sb_axi_arqos = 4'h0; // @[el2_swerv.scala 806:19]
|
|
assign io_sb_axi_rready = 1'h1; // @[el2_swerv.scala 807:20]
|
|
assign io_dma_axi_awready = dma_ctrl_io_dma_axi_awready; // @[el2_swerv.scala 810:22]
|
|
assign io_dma_axi_wready = dma_ctrl_io_dma_axi_wready; // @[el2_swerv.scala 811:21]
|
|
assign io_dma_axi_bvalid = dma_ctrl_io_dma_axi_bvalid; // @[el2_swerv.scala 812:21]
|
|
assign io_dma_axi_bresp = dma_ctrl_io_dma_axi_bresp; // @[el2_swerv.scala 813:20]
|
|
assign io_dma_axi_bid = dma_ctrl_io_dma_axi_bid; // @[el2_swerv.scala 814:18]
|
|
assign io_dma_axi_arready = dma_ctrl_io_dma_axi_arready; // @[el2_swerv.scala 815:22]
|
|
assign io_dma_axi_rvalid = dma_ctrl_io_dma_axi_rvalid; // @[el2_swerv.scala 816:21]
|
|
assign io_dma_axi_rid = dma_ctrl_io_dma_axi_rid; // @[el2_swerv.scala 817:18]
|
|
assign io_dma_axi_rdata = dma_ctrl_io_dma_axi_rdata; // @[el2_swerv.scala 818:20]
|
|
assign io_dma_axi_rresp = dma_ctrl_io_dma_axi_rresp; // @[el2_swerv.scala 819:20]
|
|
assign io_dma_axi_rlast = 1'h1; // @[el2_swerv.scala 820:20]
|
|
assign io_haddr = 32'h0; // @[el2_swerv.scala 829:12]
|
|
assign io_hburst = 3'h0; // @[el2_swerv.scala 823:13]
|
|
assign io_hmastlock = 1'h0; // @[el2_swerv.scala 824:16]
|
|
assign io_hprot = 4'h0; // @[el2_swerv.scala 825:12]
|
|
assign io_hsize = 3'h0; // @[el2_swerv.scala 826:12]
|
|
assign io_htrans = 2'h0; // @[el2_swerv.scala 827:13]
|
|
assign io_hwrite = 1'h0; // @[el2_swerv.scala 828:13]
|
|
assign io_lsu_haddr = 32'h0; // @[el2_swerv.scala 831:16]
|
|
assign io_lsu_hburst = 3'h0; // @[el2_swerv.scala 832:17]
|
|
assign io_lsu_hmastlock = 1'h0; // @[el2_swerv.scala 833:20]
|
|
assign io_lsu_hprot = 4'h0; // @[el2_swerv.scala 834:16]
|
|
assign io_lsu_hsize = 3'h0; // @[el2_swerv.scala 835:16]
|
|
assign io_lsu_htrans = 2'h0; // @[el2_swerv.scala 836:17]
|
|
assign io_lsu_hwrite = 1'h0; // @[el2_swerv.scala 837:17]
|
|
assign io_lsu_hwdata = 64'h0; // @[el2_swerv.scala 838:17]
|
|
assign io_sb_haddr = 32'h0; // @[el2_swerv.scala 841:15]
|
|
assign io_sb_hburst = 3'h0; // @[el2_swerv.scala 842:16]
|
|
assign io_sb_hmastlock = 1'h0; // @[el2_swerv.scala 843:19]
|
|
assign io_sb_hprot = 4'h0; // @[el2_swerv.scala 844:15]
|
|
assign io_sb_hsize = 3'h0; // @[el2_swerv.scala 845:15]
|
|
assign io_sb_htrans = 2'h0; // @[el2_swerv.scala 846:16]
|
|
assign io_sb_hwrite = 1'h0; // @[el2_swerv.scala 847:16]
|
|
assign io_sb_hwdata = 64'h0; // @[el2_swerv.scala 848:16]
|
|
assign io_dma_hrdata = 64'h0; // @[el2_swerv.scala 850:17]
|
|
assign io_dma_hreadyout = 1'h0; // @[el2_swerv.scala 851:20]
|
|
assign io_dma_hresp = 1'h0; // @[el2_swerv.scala 852:16 el2_swerv.scala 856:16]
|
|
assign io_dmi_reg_rdata = 32'h0; // @[el2_swerv.scala 858:20]
|
|
assign ifu_clock = clock;
|
|
assign ifu_reset = io_core_rst_l; // @[el2_swerv.scala 344:13]
|
|
assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 346:19]
|
|
assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[el2_swerv.scala 347:21]
|
|
assign ifu_io_dec_i0_decode_d = dec_io_dec_i0_decode_d; // @[el2_swerv.scala 349:26]
|
|
assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[el2_swerv.scala 350:26]
|
|
assign ifu_io_dec_tlu_i0_commit_cmt = dec_io_dec_tlu_i0_commit_cmt; // @[el2_swerv.scala 351:32]
|
|
assign ifu_io_dec_tlu_flush_err_wb = dec_io_dec_tlu_flush_err_r; // @[el2_swerv.scala 352:31]
|
|
assign ifu_io_dec_tlu_flush_noredir_wb = dec_io_dec_tlu_flush_noredir_r; // @[el2_swerv.scala 353:35]
|
|
assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[el2_swerv.scala 354:31]
|
|
assign ifu_io_dec_tlu_mrac_ff = dec_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 355:26]
|
|
assign ifu_io_dec_tlu_fence_i_wb = dec_io_dec_tlu_fence_i_r; // @[el2_swerv.scala 356:29]
|
|
assign ifu_io_dec_tlu_flush_leak_one_wb = dec_io_dec_tlu_flush_leak_one_r; // @[el2_swerv.scala 357:36]
|
|
assign ifu_io_dec_tlu_bpred_disable = dec_io_dec_tlu_bpred_disable; // @[el2_swerv.scala 358:32]
|
|
assign ifu_io_dec_tlu_core_ecc_disable = dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 359:35]
|
|
assign ifu_io_dec_tlu_force_halt = dec_io_dec_tlu_force_halt; // @[el2_swerv.scala 360:29]
|
|
assign ifu_io_ifu_axi_arready = io_ifu_axi_arready; // @[el2_swerv.scala 361:26]
|
|
assign ifu_io_ifu_axi_rvalid = io_ifu_axi_rvalid; // @[el2_swerv.scala 362:25]
|
|
assign ifu_io_ifu_axi_rid = io_ifu_axi_rid; // @[el2_swerv.scala 363:22]
|
|
assign ifu_io_ifu_axi_rdata = io_ifu_axi_rdata; // @[el2_swerv.scala 364:24]
|
|
assign ifu_io_ifu_axi_rresp = io_ifu_axi_rresp; // @[el2_swerv.scala 365:24]
|
|
assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[el2_swerv.scala 366:25]
|
|
assign ifu_io_dma_iccm_req = dma_ctrl_io_dma_iccm_req; // @[el2_swerv.scala 367:23]
|
|
assign ifu_io_dma_mem_addr = dma_ctrl_io_dma_mem_addr; // @[el2_swerv.scala 368:23]
|
|
assign ifu_io_dma_mem_sz = dma_ctrl_io_dma_mem_sz; // @[el2_swerv.scala 369:21]
|
|
assign ifu_io_dma_mem_write = dma_ctrl_io_dma_mem_write; // @[el2_swerv.scala 370:24]
|
|
assign ifu_io_dma_mem_wdata = dma_ctrl_io_dma_mem_wdata; // @[el2_swerv.scala 371:24]
|
|
assign ifu_io_dma_mem_tag = dma_ctrl_io_dma_mem_tag; // @[el2_swerv.scala 372:22]
|
|
assign ifu_io_dma_iccm_stall_any = dma_ctrl_io_dma_iccm_stall_any; // @[el2_swerv.scala 373:29]
|
|
assign ifu_io_ic_rd_data = io_ic_rd_data; // @[el2_swerv.scala 374:21]
|
|
assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[el2_swerv.scala 375:27]
|
|
assign ifu_io_ictag_debug_rd_data = io_ictag_debug_rd_data; // @[el2_swerv.scala 376:30]
|
|
assign ifu_io_ic_eccerr = io_ic_eccerr; // @[el2_swerv.scala 377:20]
|
|
assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[el2_swerv.scala 379:20]
|
|
assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[el2_swerv.scala 380:22]
|
|
assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[el2_swerv.scala 381:23]
|
|
assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[el2_swerv.scala 348:27]
|
|
assign ifu_io_exu_mp_pkt_bits_misp = exu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 382:21]
|
|
assign ifu_io_exu_mp_pkt_bits_ataken = exu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 382:21]
|
|
assign ifu_io_exu_mp_pkt_bits_boffset = exu_io_exu_mp_pkt_bits_boffset; // @[el2_swerv.scala 382:21]
|
|
assign ifu_io_exu_mp_pkt_bits_pc4 = exu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 382:21]
|
|
assign ifu_io_exu_mp_pkt_bits_hist = exu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 382:21]
|
|
assign ifu_io_exu_mp_pkt_bits_toffset = exu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 382:21]
|
|
assign ifu_io_exu_mp_pkt_bits_pcall = exu_io_exu_mp_pkt_bits_pcall; // @[el2_swerv.scala 382:21]
|
|
assign ifu_io_exu_mp_pkt_bits_pret = exu_io_exu_mp_pkt_bits_pret; // @[el2_swerv.scala 382:21]
|
|
assign ifu_io_exu_mp_pkt_bits_pja = exu_io_exu_mp_pkt_bits_pja; // @[el2_swerv.scala 382:21]
|
|
assign ifu_io_exu_mp_pkt_bits_way = exu_io_exu_mp_pkt_bits_way; // @[el2_swerv.scala 382:21]
|
|
assign ifu_io_exu_mp_eghr = exu_io_exu_mp_eghr; // @[el2_swerv.scala 383:22]
|
|
assign ifu_io_exu_mp_fghr = exu_io_exu_mp_fghr; // @[el2_swerv.scala 384:22]
|
|
assign ifu_io_exu_mp_index = exu_io_exu_mp_index; // @[el2_swerv.scala 385:23]
|
|
assign ifu_io_exu_mp_btag = exu_io_exu_mp_btag; // @[el2_swerv.scala 386:22]
|
|
assign ifu_io_dec_tlu_br0_r_pkt_valid = dec_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 387:28]
|
|
assign ifu_io_dec_tlu_br0_r_pkt_hist = dec_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 387:28]
|
|
assign ifu_io_dec_tlu_br0_r_pkt_br_error = dec_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 387:28]
|
|
assign ifu_io_dec_tlu_br0_r_pkt_br_start_error = dec_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 387:28]
|
|
assign ifu_io_dec_tlu_br0_r_pkt_way = dec_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 387:28]
|
|
assign ifu_io_dec_tlu_br0_r_pkt_middle = dec_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 387:28]
|
|
assign ifu_io_exu_i0_br_fghr_r = exu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 388:27]
|
|
assign ifu_io_exu_i0_br_index_r = exu_io_exu_i0_br_index_r; // @[el2_swerv.scala 389:28]
|
|
assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 390:33]
|
|
assign ifu_io_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_swerv.scala 391:30]
|
|
assign ifu_io_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_swerv.scala 391:30]
|
|
assign ifu_io_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_swerv.scala 391:30]
|
|
assign ifu_io_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_swerv.scala 391:30]
|
|
assign ifu_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 345:20]
|
|
assign dec_clock = clock;
|
|
assign dec_reset = io_core_rst_l; // @[el2_swerv.scala 394:13]
|
|
assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 395:19]
|
|
assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[el2_swerv.scala 396:21]
|
|
assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[el2_swerv.scala 397:32]
|
|
assign dec_io_rst_vec = io_rst_vec; // @[el2_swerv.scala 398:18]
|
|
assign dec_io_nmi_int = io_nmi_int; // @[el2_swerv.scala 399:18]
|
|
assign dec_io_nmi_vec = io_nmi_vec; // @[el2_swerv.scala 400:18]
|
|
assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_swerv.scala 401:25]
|
|
assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_swerv.scala 402:24]
|
|
assign dec_io_core_id = io_core_id; // @[el2_swerv.scala 403:18]
|
|
assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_swerv.scala 404:29]
|
|
assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_swerv.scala 405:28]
|
|
assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_swerv.scala 406:28]
|
|
assign dec_io_exu_pmu_i0_br_misp = exu_io_exu_pmu_i0_br_misp; // @[el2_swerv.scala 407:29]
|
|
assign dec_io_exu_pmu_i0_br_ataken = exu_io_exu_pmu_i0_br_ataken; // @[el2_swerv.scala 408:31]
|
|
assign dec_io_exu_pmu_i0_pc4 = exu_io_exu_pmu_i0_pc4; // @[el2_swerv.scala 409:25]
|
|
assign dec_io_lsu_nonblock_load_valid_m = lsu_io_lsu_nonblock_load_valid_m; // @[el2_swerv.scala 410:36]
|
|
assign dec_io_lsu_nonblock_load_tag_m = lsu_io_lsu_nonblock_load_tag_m; // @[el2_swerv.scala 411:34]
|
|
assign dec_io_lsu_nonblock_load_inv_r = lsu_io_lsu_nonblock_load_inv_r; // @[el2_swerv.scala 412:34]
|
|
assign dec_io_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_nonblock_load_inv_tag_r; // @[el2_swerv.scala 413:38]
|
|
assign dec_io_lsu_nonblock_load_data_valid = lsu_io_lsu_nonblock_load_data_valid; // @[el2_swerv.scala 414:39]
|
|
assign dec_io_lsu_nonblock_load_data_error = lsu_io_lsu_nonblock_load_data_error; // @[el2_swerv.scala 415:39]
|
|
assign dec_io_lsu_nonblock_load_data_tag = lsu_io_lsu_nonblock_load_data_tag; // @[el2_swerv.scala 416:37]
|
|
assign dec_io_lsu_nonblock_load_data = lsu_io_lsu_nonblock_load_data; // @[el2_swerv.scala 417:33]
|
|
assign dec_io_lsu_pmu_bus_trxn = lsu_io_lsu_pmu_bus_trxn; // @[el2_swerv.scala 418:27]
|
|
assign dec_io_lsu_pmu_bus_misaligned = lsu_io_lsu_pmu_bus_misaligned; // @[el2_swerv.scala 419:33]
|
|
assign dec_io_lsu_pmu_bus_error = lsu_io_lsu_pmu_bus_error; // @[el2_swerv.scala 420:28]
|
|
assign dec_io_lsu_pmu_bus_busy = lsu_io_lsu_pmu_bus_busy; // @[el2_swerv.scala 421:27]
|
|
assign dec_io_lsu_pmu_load_external_m = lsu_io_lsu_pmu_load_external_m; // @[el2_swerv.scala 423:34]
|
|
assign dec_io_lsu_pmu_store_external_m = lsu_io_lsu_pmu_store_external_m; // @[el2_swerv.scala 424:35]
|
|
assign dec_io_dma_pmu_dccm_read = dma_ctrl_io_dma_pmu_dccm_read; // @[el2_swerv.scala 425:28]
|
|
assign dec_io_dma_pmu_dccm_write = dma_ctrl_io_dma_pmu_dccm_write; // @[el2_swerv.scala 426:29]
|
|
assign dec_io_dma_pmu_any_read = dma_ctrl_io_dma_pmu_any_read; // @[el2_swerv.scala 427:27]
|
|
assign dec_io_dma_pmu_any_write = dma_ctrl_io_dma_pmu_any_write; // @[el2_swerv.scala 428:28]
|
|
assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[el2_swerv.scala 429:23]
|
|
assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[el2_swerv.scala 430:24]
|
|
assign dec_io_ifu_pmu_instr_aligned = ifu_io_ifu_pmu_instr_aligned; // @[el2_swerv.scala 431:32]
|
|
assign dec_io_ifu_pmu_fetch_stall = ifu_io_ifu_pmu_fetch_stall; // @[el2_swerv.scala 432:30]
|
|
assign dec_io_ifu_pmu_ic_miss = ifu_io_ifu_pmu_ic_miss; // @[el2_swerv.scala 433:26]
|
|
assign dec_io_ifu_pmu_ic_hit = ifu_io_ifu_pmu_ic_hit; // @[el2_swerv.scala 434:25]
|
|
assign dec_io_ifu_pmu_bus_error = ifu_io_ifu_pmu_bus_error; // @[el2_swerv.scala 435:28]
|
|
assign dec_io_ifu_pmu_bus_busy = ifu_io_ifu_pmu_bus_busy; // @[el2_swerv.scala 436:27]
|
|
assign dec_io_ifu_pmu_bus_trxn = ifu_io_ifu_pmu_bus_trxn; // @[el2_swerv.scala 437:27]
|
|
assign dec_io_ifu_ic_error_start = ifu_io_ifu_ic_error_start; // @[el2_swerv.scala 438:29]
|
|
assign dec_io_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_iccm_rd_ecc_single_err; // @[el2_swerv.scala 439:37]
|
|
assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[el2_swerv.scala 440:30]
|
|
assign dec_io_dbg_cmd_valid = dbg_io_dbg_cmd_valid; // @[el2_swerv.scala 441:24]
|
|
assign dec_io_dbg_cmd_write = dbg_io_dbg_cmd_write; // @[el2_swerv.scala 442:24]
|
|
assign dec_io_dbg_cmd_type = dbg_io_dbg_cmd_type; // @[el2_swerv.scala 443:23]
|
|
assign dec_io_dbg_cmd_addr = dbg_io_dbg_cmd_addr; // @[el2_swerv.scala 444:23]
|
|
assign dec_io_dbg_cmd_wrdata = dbg_io_dbg_cmd_wrdata[1:0]; // @[el2_swerv.scala 445:25]
|
|
assign dec_io_ifu_i0_icaf = ifu_io_ifu_i0_icaf; // @[el2_swerv.scala 446:22]
|
|
assign dec_io_ifu_i0_icaf_type = ifu_io_ifu_i0_icaf_type; // @[el2_swerv.scala 447:27]
|
|
assign dec_io_ifu_i0_icaf_f1 = ifu_io_ifu_i0_icaf_f1; // @[el2_swerv.scala 448:25]
|
|
assign dec_io_ifu_i0_dbecc = ifu_io_ifu_i0_dbecc; // @[el2_swerv.scala 449:23]
|
|
assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[el2_swerv.scala 450:23]
|
|
assign dec_io_i0_brp_valid = ifu_io_i0_brp_valid; // @[el2_swerv.scala 451:17]
|
|
assign dec_io_i0_brp_toffset = ifu_io_i0_brp_toffset; // @[el2_swerv.scala 451:17]
|
|
assign dec_io_i0_brp_hist = ifu_io_i0_brp_hist; // @[el2_swerv.scala 451:17]
|
|
assign dec_io_i0_brp_br_error = ifu_io_i0_brp_br_error; // @[el2_swerv.scala 451:17]
|
|
assign dec_io_i0_brp_br_start_error = ifu_io_i0_brp_br_start_error; // @[el2_swerv.scala 451:17]
|
|
assign dec_io_i0_brp_prett = ifu_io_i0_brp_prett; // @[el2_swerv.scala 451:17]
|
|
assign dec_io_i0_brp_way = ifu_io_i0_brp_way; // @[el2_swerv.scala 451:17]
|
|
assign dec_io_i0_brp_ret = ifu_io_i0_brp_ret; // @[el2_swerv.scala 451:17]
|
|
assign dec_io_ifu_i0_bp_index = ifu_io_ifu_i0_bp_index; // @[el2_swerv.scala 452:26]
|
|
assign dec_io_ifu_i0_bp_fghr = ifu_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 453:25]
|
|
assign dec_io_ifu_i0_bp_btag = ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 454:25]
|
|
assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[el2_swerv.scala 455:26]
|
|
assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_swerv.scala 455:26]
|
|
assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_swerv.scala 455:26]
|
|
assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_swerv.scala 455:26]
|
|
assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 455:26]
|
|
assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 455:26]
|
|
assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[el2_swerv.scala 456:36]
|
|
assign dec_io_lsu_imprecise_error_load_any = lsu_io_lsu_imprecise_error_load_any; // @[el2_swerv.scala 457:39]
|
|
assign dec_io_lsu_imprecise_error_store_any = lsu_io_lsu_imprecise_error_store_any; // @[el2_swerv.scala 458:40]
|
|
assign dec_io_lsu_imprecise_error_addr_any = lsu_io_lsu_imprecise_error_addr_any; // @[el2_swerv.scala 459:39]
|
|
assign dec_io_exu_div_result = exu_io_exu_div_result; // @[el2_swerv.scala 460:25]
|
|
assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[el2_swerv.scala 461:23]
|
|
assign dec_io_exu_csr_rs1_x = exu_io_exu_csr_rs1_x; // @[el2_swerv.scala 462:24]
|
|
assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[el2_swerv.scala 463:23]
|
|
assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[el2_swerv.scala 464:28]
|
|
assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[el2_swerv.scala 465:29]
|
|
assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[el2_swerv.scala 466:30]
|
|
assign dec_io_dma_dccm_stall_any = dma_ctrl_io_dma_dccm_stall_any; // @[el2_swerv.scala 467:29]
|
|
assign dec_io_dma_iccm_stall_any = dma_ctrl_io_dma_iccm_stall_any; // @[el2_swerv.scala 468:29]
|
|
assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[el2_swerv.scala 469:28]
|
|
assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[el2_swerv.scala 470:26]
|
|
assign dec_io_exu_npc_r = exu_io_exu_npc_r; // @[el2_swerv.scala 471:20]
|
|
assign dec_io_exu_i0_result_x = exu_io_exu_i0_result_x; // @[el2_swerv.scala 472:26]
|
|
assign dec_io_ifu_i0_valid = ifu_io_ifu_i0_valid; // @[el2_swerv.scala 473:23]
|
|
assign dec_io_ifu_i0_instr = ifu_io_ifu_i0_instr; // @[el2_swerv.scala 474:23]
|
|
assign dec_io_ifu_i0_pc = ifu_io_ifu_i0_pc; // @[el2_swerv.scala 475:20]
|
|
assign dec_io_ifu_i0_pc4 = ifu_io_ifu_i0_pc4; // @[el2_swerv.scala 476:21]
|
|
assign dec_io_exu_i0_pc_x = exu_io_exu_i0_pc_x; // @[el2_swerv.scala 477:22]
|
|
assign dec_io_mexintpend = pic_ctrl_inst_io_mexintpend; // @[el2_swerv.scala 478:21]
|
|
assign dec_io_timer_int = io_timer_int; // @[el2_swerv.scala 496:20]
|
|
assign dec_io_soft_int = io_soft_int; // @[el2_swerv.scala 479:19]
|
|
assign dec_io_pic_claimid = pic_ctrl_inst_io_claimid; // @[el2_swerv.scala 480:22]
|
|
assign dec_io_pic_pl = pic_ctrl_inst_io_pl; // @[el2_swerv.scala 481:17]
|
|
assign dec_io_mhwakeup = pic_ctrl_inst_io_mhwakeup; // @[el2_swerv.scala 482:19]
|
|
assign dec_io_ifu_ic_debug_rd_data = ifu_io_ifu_ic_debug_rd_data; // @[el2_swerv.scala 483:31]
|
|
assign dec_io_ifu_ic_debug_rd_data_valid = ifu_io_ifu_ic_debug_rd_data_valid; // @[el2_swerv.scala 484:37]
|
|
assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[el2_swerv.scala 485:23]
|
|
assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[el2_swerv.scala 486:25]
|
|
assign dec_io_ifu_miss_state_idle = ifu_io_ifu_miss_state_idle; // @[el2_swerv.scala 487:30]
|
|
assign dec_io_exu_i0_br_hist_r = exu_io_exu_i0_br_hist_r; // @[el2_swerv.scala 488:27]
|
|
assign dec_io_exu_i0_br_error_r = exu_io_exu_i0_br_error_r; // @[el2_swerv.scala 489:28]
|
|
assign dec_io_exu_i0_br_start_error_r = exu_io_exu_i0_br_start_error_r; // @[el2_swerv.scala 490:34]
|
|
assign dec_io_exu_i0_br_valid_r = exu_io_exu_i0_br_valid_r; // @[el2_swerv.scala 491:28]
|
|
assign dec_io_exu_i0_br_mp_r = exu_io_exu_i0_br_mp_r; // @[el2_swerv.scala 492:25]
|
|
assign dec_io_exu_i0_br_middle_r = exu_io_exu_i0_br_middle_r; // @[el2_swerv.scala 493:29]
|
|
assign dec_io_exu_i0_br_way_r = exu_io_exu_i0_br_way_r; // @[el2_swerv.scala 494:26]
|
|
assign dec_io_ifu_i0_cinst = ifu_io_ifu_i0_cinst; // @[el2_swerv.scala 495:23]
|
|
assign dec_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 497:20]
|
|
assign dbg_clock = clock;
|
|
assign dbg_reset = io_core_rst_l; // @[el2_swerv.scala 576:13]
|
|
assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[el2_swerv.scala 577:26]
|
|
assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[el2_swerv.scala 578:28]
|
|
assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[el2_swerv.scala 579:28]
|
|
assign dbg_io_dma_dbg_ready = dma_ctrl_io_dma_dbg_ready; // @[el2_swerv.scala 580:24]
|
|
assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[el2_swerv.scala 581:29]
|
|
assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[el2_swerv.scala 582:29]
|
|
assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[el2_swerv.scala 583:34]
|
|
assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[el2_swerv.scala 584:29]
|
|
assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[el2_swerv.scala 585:21]
|
|
assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[el2_swerv.scala 586:23]
|
|
assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[el2_swerv.scala 587:24]
|
|
assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[el2_swerv.scala 588:24]
|
|
assign dbg_io_sb_axi_awready = io_sb_axi_awready; // @[el2_swerv.scala 589:25]
|
|
assign dbg_io_sb_axi_wready = io_sb_axi_wready; // @[el2_swerv.scala 590:24]
|
|
assign dbg_io_sb_axi_bvalid = io_sb_axi_bvalid; // @[el2_swerv.scala 591:24]
|
|
assign dbg_io_sb_axi_bresp = io_sb_axi_bresp; // @[el2_swerv.scala 592:23]
|
|
assign dbg_io_sb_axi_arready = io_sb_axi_arready; // @[el2_swerv.scala 593:25]
|
|
assign dbg_io_sb_axi_rvalid = io_sb_axi_rvalid; // @[el2_swerv.scala 594:24]
|
|
assign dbg_io_sb_axi_rdata = io_sb_axi_rdata; // @[el2_swerv.scala 595:23]
|
|
assign dbg_io_sb_axi_rresp = io_sb_axi_rresp; // @[el2_swerv.scala 596:23]
|
|
assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[el2_swerv.scala 597:25]
|
|
assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[el2_swerv.scala 598:20]
|
|
assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[el2_swerv.scala 599:23]
|
|
assign dbg_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 600:20]
|
|
assign exu_clock = clock;
|
|
assign exu_reset = io_core_rst_l; // @[el2_swerv.scala 500:13]
|
|
assign exu_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 501:20]
|
|
assign exu_io_dec_data_en = dec_io_dec_data_en; // @[el2_swerv.scala 502:22]
|
|
assign exu_io_dec_ctl_en = dec_io_dec_ctl_en; // @[el2_swerv.scala 503:21]
|
|
assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_cmd_wrdata; // @[el2_swerv.scala 504:25]
|
|
assign exu_io_i0_ap_land = dec_io_i0_ap_land; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_lor = dec_io_i0_ap_lor; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_lxor = dec_io_i0_ap_lxor; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_sll = dec_io_i0_ap_sll; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_srl = dec_io_i0_ap_srl; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_sra = dec_io_i0_ap_sra; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_beq = dec_io_i0_ap_beq; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_bne = dec_io_i0_ap_bne; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_blt = dec_io_i0_ap_blt; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_bge = dec_io_i0_ap_bge; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_add = dec_io_i0_ap_add; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_sub = dec_io_i0_ap_sub; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_slt = dec_io_i0_ap_slt; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_unsign = dec_io_i0_ap_unsign; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_jal = dec_io_i0_ap_jal; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_predict_t = dec_io_i0_ap_predict_t; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_predict_nt = dec_io_i0_ap_predict_nt; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_csr_write = dec_io_i0_ap_csr_write; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_i0_ap_csr_imm = dec_io_i0_ap_csr_imm; // @[el2_swerv.scala 505:16]
|
|
assign exu_io_dec_debug_wdata_rs1_d = dec_io_dec_debug_wdata_rs1_d; // @[el2_swerv.scala 506:32]
|
|
assign exu_io_dec_i0_predict_p_d_valid = dec_io_dec_i0_predict_p_d_valid; // @[el2_swerv.scala 507:29]
|
|
assign exu_io_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_i0_predict_p_d_bits_pc4; // @[el2_swerv.scala 507:29]
|
|
assign exu_io_dec_i0_predict_p_d_bits_hist = dec_io_dec_i0_predict_p_d_bits_hist; // @[el2_swerv.scala 507:29]
|
|
assign exu_io_dec_i0_predict_p_d_bits_toffset = dec_io_dec_i0_predict_p_d_bits_toffset; // @[el2_swerv.scala 507:29]
|
|
assign exu_io_dec_i0_predict_p_d_bits_br_error = dec_io_dec_i0_predict_p_d_bits_br_error; // @[el2_swerv.scala 507:29]
|
|
assign exu_io_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_swerv.scala 507:29]
|
|
assign exu_io_dec_i0_predict_p_d_bits_prett = dec_io_dec_i0_predict_p_d_bits_prett; // @[el2_swerv.scala 507:29]
|
|
assign exu_io_dec_i0_predict_p_d_bits_pcall = dec_io_dec_i0_predict_p_d_bits_pcall; // @[el2_swerv.scala 507:29]
|
|
assign exu_io_dec_i0_predict_p_d_bits_pret = dec_io_dec_i0_predict_p_d_bits_pret; // @[el2_swerv.scala 507:29]
|
|
assign exu_io_dec_i0_predict_p_d_bits_pja = dec_io_dec_i0_predict_p_d_bits_pja; // @[el2_swerv.scala 507:29]
|
|
assign exu_io_dec_i0_predict_p_d_bits_way = dec_io_dec_i0_predict_p_d_bits_way; // @[el2_swerv.scala 507:29]
|
|
assign exu_io_i0_predict_fghr_d = dec_io_i0_predict_fghr_d; // @[el2_swerv.scala 508:28]
|
|
assign exu_io_i0_predict_index_d = dec_io_i0_predict_index_d; // @[el2_swerv.scala 509:29]
|
|
assign exu_io_i0_predict_btag_d = dec_io_i0_predict_btag_d; // @[el2_swerv.scala 510:28]
|
|
assign exu_io_dec_i0_rs1_en_d = dec_io_dec_i0_rs1_en_d; // @[el2_swerv.scala 511:26]
|
|
assign exu_io_dec_i0_rs2_en_d = dec_io_dec_i0_rs2_en_d; // @[el2_swerv.scala 512:26]
|
|
assign exu_io_gpr_i0_rs1_d = dec_io_gpr_i0_rs1_d; // @[el2_swerv.scala 513:23]
|
|
assign exu_io_gpr_i0_rs2_d = dec_io_gpr_i0_rs2_d; // @[el2_swerv.scala 514:23]
|
|
assign exu_io_dec_i0_immed_d = dec_io_dec_i0_immed_d; // @[el2_swerv.scala 515:25]
|
|
assign exu_io_dec_i0_rs1_bypass_data_d = dec_io_dec_i0_rs1_bypass_data_d; // @[el2_swerv.scala 516:35]
|
|
assign exu_io_dec_i0_rs2_bypass_data_d = dec_io_dec_i0_rs2_bypass_data_d; // @[el2_swerv.scala 517:35]
|
|
assign exu_io_dec_i0_br_immed_d = dec_io_dec_i0_br_immed_d; // @[el2_swerv.scala 518:28]
|
|
assign exu_io_dec_i0_alu_decode_d = dec_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 519:30]
|
|
assign exu_io_dec_i0_select_pc_d = dec_io_dec_i0_select_pc_d; // @[el2_swerv.scala 520:29]
|
|
assign exu_io_dec_i0_pc_d = dec_io_dec_i0_pc_d; // @[el2_swerv.scala 521:22]
|
|
assign exu_io_dec_i0_rs1_bypass_en_d = dec_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 522:33]
|
|
assign exu_io_dec_i0_rs2_bypass_en_d = dec_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 523:33]
|
|
assign exu_io_dec_csr_ren_d = dec_io_dec_csr_ren_d; // @[el2_swerv.scala 524:24]
|
|
assign exu_io_mul_p_valid = dec_io_mul_p_valid; // @[el2_swerv.scala 525:16]
|
|
assign exu_io_mul_p_bits_rs1_sign = dec_io_mul_p_bits_rs1_sign; // @[el2_swerv.scala 525:16]
|
|
assign exu_io_mul_p_bits_rs2_sign = dec_io_mul_p_bits_rs2_sign; // @[el2_swerv.scala 525:16]
|
|
assign exu_io_mul_p_bits_low = dec_io_mul_p_bits_low; // @[el2_swerv.scala 525:16]
|
|
assign exu_io_div_p_valid = dec_io_div_p_valid; // @[el2_swerv.scala 526:16]
|
|
assign exu_io_div_p_bits_unsign = dec_io_div_p_bits_unsign; // @[el2_swerv.scala 526:16]
|
|
assign exu_io_div_p_bits_rem = dec_io_div_p_bits_rem; // @[el2_swerv.scala 526:16]
|
|
assign exu_io_dec_div_cancel = dec_io_dec_div_cancel; // @[el2_swerv.scala 527:25]
|
|
assign exu_io_pred_correct_npc_x = dec_io_pred_correct_npc_x; // @[el2_swerv.scala 528:29]
|
|
assign exu_io_dec_tlu_flush_lower_r = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 529:32]
|
|
assign exu_io_dec_tlu_flush_path_r = dec_io_dec_tlu_flush_path_r; // @[el2_swerv.scala 530:31]
|
|
assign exu_io_dec_extint_stall = dec_io_dec_extint_stall; // @[el2_swerv.scala 531:27]
|
|
assign exu_io_dec_tlu_meihap = dec_io_dec_tlu_meihap; // @[el2_swerv.scala 532:25]
|
|
assign lsu_clock = clock;
|
|
assign lsu_reset = io_core_rst_l; // @[el2_swerv.scala 536:13]
|
|
assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[el2_swerv.scala 537:23]
|
|
assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 538:32]
|
|
assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[el2_swerv.scala 539:35]
|
|
assign lsu_io_dec_tlu_force_halt = dec_io_dec_tlu_force_halt; // @[el2_swerv.scala 540:29]
|
|
assign lsu_io_dec_tlu_external_ldfwd_disable = dec_io_dec_tlu_external_ldfwd_disable; // @[el2_swerv.scala 541:41]
|
|
assign lsu_io_dec_tlu_wb_coalescing_disable = dec_io_dec_tlu_wb_coalescing_disable; // @[el2_swerv.scala 542:40]
|
|
assign lsu_io_dec_tlu_sideeffect_posted_disable = dec_io_dec_tlu_sideeffect_posted_disable; // @[el2_swerv.scala 543:44]
|
|
assign lsu_io_dec_tlu_core_ecc_disable = dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 544:35]
|
|
assign lsu_io_exu_lsu_rs1_d = exu_io_exu_lsu_rs1_d; // @[el2_swerv.scala 545:24]
|
|
assign lsu_io_exu_lsu_rs2_d = exu_io_exu_lsu_rs2_d; // @[el2_swerv.scala 546:24]
|
|
assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[el2_swerv.scala 547:27]
|
|
assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[el2_swerv.scala 548:16]
|
|
assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[el2_swerv.scala 548:16]
|
|
assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[el2_swerv.scala 548:16]
|
|
assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[el2_swerv.scala 548:16]
|
|
assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[el2_swerv.scala 548:16]
|
|
assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[el2_swerv.scala 548:16]
|
|
assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[el2_swerv.scala 548:16]
|
|
assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[el2_swerv.scala 548:16]
|
|
assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[el2_swerv.scala 548:16]
|
|
assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_swerv.scala 548:16]
|
|
assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 551:26]
|
|
assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[el2_swerv.scala 549:30]
|
|
assign lsu_io_dec_tlu_mrac_ff = dec_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 550:26]
|
|
assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[el2_swerv.scala 552:26]
|
|
assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[el2_swerv.scala 553:26]
|
|
assign lsu_io_picm_rd_data = pic_ctrl_inst_io_picm_rd_data; // @[el2_swerv.scala 657:23]
|
|
assign lsu_io_lsu_axi_awready = io_lsu_axi_awready; // @[el2_swerv.scala 554:26]
|
|
assign lsu_io_lsu_axi_wready = io_lsu_axi_wready; // @[el2_swerv.scala 555:25]
|
|
assign lsu_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[el2_swerv.scala 556:25]
|
|
assign lsu_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[el2_swerv.scala 557:24]
|
|
assign lsu_io_lsu_axi_bid = io_lsu_axi_bid; // @[el2_swerv.scala 558:22]
|
|
assign lsu_io_lsu_axi_arready = io_lsu_axi_arready; // @[el2_swerv.scala 559:26]
|
|
assign lsu_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[el2_swerv.scala 560:25]
|
|
assign lsu_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[el2_swerv.scala 562:24]
|
|
assign lsu_io_lsu_axi_rid = io_lsu_axi_rid; // @[el2_swerv.scala 561:22]
|
|
assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_swerv.scala 565:25]
|
|
assign lsu_io_dma_dccm_req = dma_ctrl_io_dma_dccm_req; // @[el2_swerv.scala 566:23]
|
|
assign lsu_io_dma_mem_write = dma_ctrl_io_dma_mem_write; // @[el2_swerv.scala 570:24]
|
|
assign lsu_io_dma_mem_tag = dma_ctrl_io_dma_mem_tag; // @[el2_swerv.scala 567:22]
|
|
assign lsu_io_dma_mem_addr = dma_ctrl_io_dma_mem_addr; // @[el2_swerv.scala 568:23]
|
|
assign lsu_io_dma_mem_sz = dma_ctrl_io_dma_mem_sz; // @[el2_swerv.scala 569:21]
|
|
assign lsu_io_dma_mem_wdata = dma_ctrl_io_dma_mem_wdata; // @[el2_swerv.scala 571:24]
|
|
assign lsu_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 572:20]
|
|
assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 573:19]
|
|
assign pic_ctrl_inst_clock = clock;
|
|
assign pic_ctrl_inst_reset = io_core_rst_l; // @[el2_swerv.scala 644:23]
|
|
assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 643:30]
|
|
assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 645:29]
|
|
assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[el2_swerv.scala 646:31]
|
|
assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[el2_swerv.scala 647:33]
|
|
assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[el2_swerv.scala 648:34]
|
|
assign pic_ctrl_inst_io_picm_rdaddr = lsu_io_picm_rdaddr; // @[el2_swerv.scala 649:32]
|
|
assign pic_ctrl_inst_io_picm_wraddr = lsu_io_picm_wraddr; // @[el2_swerv.scala 650:32]
|
|
assign pic_ctrl_inst_io_picm_wr_data = lsu_io_picm_wr_data; // @[el2_swerv.scala 651:33]
|
|
assign pic_ctrl_inst_io_picm_wren = lsu_io_picm_wren; // @[el2_swerv.scala 652:30]
|
|
assign pic_ctrl_inst_io_picm_rden = lsu_io_picm_rden; // @[el2_swerv.scala 653:30]
|
|
assign pic_ctrl_inst_io_picm_mken = lsu_io_picm_mken; // @[el2_swerv.scala 654:30]
|
|
assign pic_ctrl_inst_io_meicurpl = dec_io_dec_tlu_meicurpl; // @[el2_swerv.scala 655:29]
|
|
assign pic_ctrl_inst_io_meipt = dec_io_dec_tlu_meipt; // @[el2_swerv.scala 656:26]
|
|
assign dma_ctrl_clock = clock;
|
|
assign dma_ctrl_reset = io_core_rst_l; // @[el2_swerv.scala 604:18]
|
|
assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 605:24]
|
|
assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[el2_swerv.scala 606:30]
|
|
assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[el2_swerv.scala 607:28]
|
|
assign dma_ctrl_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 608:25]
|
|
assign dma_ctrl_io_dbg_cmd_addr = dbg_io_dbg_cmd_addr; // @[el2_swerv.scala 609:28]
|
|
assign dma_ctrl_io_dbg_cmd_wrdata = dbg_io_dbg_cmd_wrdata; // @[el2_swerv.scala 610:30]
|
|
assign dma_ctrl_io_dbg_cmd_valid = dbg_io_dbg_cmd_valid; // @[el2_swerv.scala 611:29]
|
|
assign dma_ctrl_io_dbg_cmd_write = dbg_io_dbg_cmd_write; // @[el2_swerv.scala 612:29]
|
|
assign dma_ctrl_io_dbg_cmd_type = dbg_io_dbg_cmd_type; // @[el2_swerv.scala 613:28]
|
|
assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[el2_swerv.scala 614:28]
|
|
assign dma_ctrl_io_dbg_dma_bubble = dbg_io_dbg_dma_bubble; // @[el2_swerv.scala 615:30]
|
|
assign dma_ctrl_io_dccm_dma_rvalid = lsu_io_dccm_dma_rvalid; // @[el2_swerv.scala 616:31]
|
|
assign dma_ctrl_io_dccm_dma_ecc_error = lsu_io_dccm_dma_ecc_error; // @[el2_swerv.scala 617:34]
|
|
assign dma_ctrl_io_dccm_dma_rtag = lsu_io_dccm_dma_rtag; // @[el2_swerv.scala 618:29]
|
|
assign dma_ctrl_io_dccm_dma_rdata = lsu_io_dccm_dma_rdata; // @[el2_swerv.scala 619:30]
|
|
assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[el2_swerv.scala 620:31]
|
|
assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[el2_swerv.scala 639:34]
|
|
assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[el2_swerv.scala 621:29]
|
|
assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[el2_swerv.scala 622:30]
|
|
assign dma_ctrl_io_dccm_ready = lsu_io_dccm_ready; // @[el2_swerv.scala 623:26]
|
|
assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[el2_swerv.scala 624:26]
|
|
assign dma_ctrl_io_dec_tlu_dma_qos_prty = dec_io_dec_tlu_dma_qos_prty; // @[el2_swerv.scala 625:36]
|
|
assign dma_ctrl_io_dma_axi_awvalid = io_dma_axi_awvalid; // @[el2_swerv.scala 626:31]
|
|
assign dma_ctrl_io_dma_axi_awid = io_dma_axi_awid; // @[el2_swerv.scala 627:28]
|
|
assign dma_ctrl_io_dma_axi_awaddr = io_dma_axi_awaddr; // @[el2_swerv.scala 628:30]
|
|
assign dma_ctrl_io_dma_axi_awsize = io_dma_axi_awsize; // @[el2_swerv.scala 629:30]
|
|
assign dma_ctrl_io_dma_axi_wvalid = io_dma_axi_wvalid; // @[el2_swerv.scala 630:30]
|
|
assign dma_ctrl_io_dma_axi_wdata = io_dma_axi_wdata; // @[el2_swerv.scala 631:29]
|
|
assign dma_ctrl_io_dma_axi_wstrb = io_dma_axi_wstrb; // @[el2_swerv.scala 632:29]
|
|
assign dma_ctrl_io_dma_axi_bready = io_dma_axi_bready; // @[el2_swerv.scala 633:30]
|
|
assign dma_ctrl_io_dma_axi_arvalid = io_dma_axi_arvalid; // @[el2_swerv.scala 634:31]
|
|
assign dma_ctrl_io_dma_axi_arid = io_dma_axi_arid; // @[el2_swerv.scala 635:28]
|
|
assign dma_ctrl_io_dma_axi_araddr = io_dma_axi_araddr; // @[el2_swerv.scala 636:30]
|
|
assign dma_ctrl_io_dma_axi_arsize = io_dma_axi_arsize; // @[el2_swerv.scala 637:30]
|
|
assign dma_ctrl_io_dma_axi_rready = io_dma_axi_rready; // @[el2_swerv.scala 638:30]
|
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_io_en = 1'h1; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
|
|
assign rvclkhdr_1_io_en = _T_6 | dec_io_dec_tlu_misc_clk_override; // @[el2_lib.scala 485:16]
|
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
|
endmodule
|