222 lines
13 KiB
Plaintext
222 lines
13 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit rvjtag_tap :
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module rvjtag_tap :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, flip rd_data : UInt<32>, flip rd_status : UInt<2>, flip idle : UInt<3>, flip dmi_stat : UInt<2>, flip jtag_id : UInt<32>, flip version : UInt<4>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<7>, wr_en : UInt<1>, rd_en : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>}
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io.tdo <= UInt<1>("h00") @[rvjtag_tap.scala 38:21]
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io.tdoEnable <= UInt<1>("h00") @[rvjtag_tap.scala 39:21]
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io.wr_data <= UInt<1>("h00") @[rvjtag_tap.scala 40:21]
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io.wr_addr <= UInt<1>("h00") @[rvjtag_tap.scala 41:21]
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io.wr_en <= UInt<1>("h00") @[rvjtag_tap.scala 42:21]
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io.rd_en <= UInt<1>("h00") @[rvjtag_tap.scala 43:21]
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io.dmi_reset <= UInt<1>("h00") @[rvjtag_tap.scala 44:21]
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io.dmi_hard_reset <= UInt<1>("h00") @[rvjtag_tap.scala 45:21]
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reg sr : UInt<41>, clock with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 48:20]
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reg nsr : UInt<41>, clock with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 49:20]
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reg dr : UInt<41>, clock with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 50:20]
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wire ir : UInt<5>
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ir <= UInt<1>("h00")
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wire jtag_reset : UInt<1>
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jtag_reset <= UInt<1>("h00")
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wire shift_dr : UInt<1>
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shift_dr <= UInt<1>("h00")
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wire pause_dr : UInt<1>
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pause_dr <= UInt<1>("h00")
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wire update_dr : UInt<1>
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update_dr <= UInt<1>("h00")
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wire capture_dr : UInt<1>
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capture_dr <= UInt<1>("h00")
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wire shift_ir : UInt<1>
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shift_ir <= UInt<1>("h00")
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wire pause_ir : UInt<1>
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pause_ir <= UInt<1>("h00")
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wire update_ir : UInt<1>
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update_ir <= UInt<1>("h00")
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wire capture_ir : UInt<1>
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capture_ir <= UInt<1>("h00")
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wire dr_en : UInt<2>
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dr_en <= UInt<1>("h00")
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wire devid_sel : UInt<1>
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devid_sel <= UInt<1>("h00")
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reg state : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[rvjtag_tap.scala 75:27]
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reg nstate : UInt, clock with : (reset => (reset, UInt<4>("h00"))) @[rvjtag_tap.scala 76:27]
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nstate <= state @[rvjtag_tap.scala 76:27]
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node _T = eq(UInt<4>("h00"), state) @[Conditional.scala 37:30]
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when _T : @[Conditional.scala 40:58]
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node _T_1 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 80:21]
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when _T_1 : @[rvjtag_tap.scala 80:32]
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nstate <= UInt<4>("h00") @[rvjtag_tap.scala 80:41]
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skip @[rvjtag_tap.scala 80:32]
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else : @[rvjtag_tap.scala 81:20]
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nstate <= UInt<4>("h01") @[rvjtag_tap.scala 81:29]
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skip @[rvjtag_tap.scala 81:20]
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skip @[Conditional.scala 40:58]
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else : @[Conditional.scala 39:67]
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node _T_2 = eq(UInt<4>("h01"), state) @[Conditional.scala 37:30]
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when _T_2 : @[Conditional.scala 39:67]
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node _T_3 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 84:21]
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when _T_3 : @[rvjtag_tap.scala 84:32]
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nstate <= UInt<4>("h02") @[rvjtag_tap.scala 84:40]
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skip @[rvjtag_tap.scala 84:32]
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else : @[rvjtag_tap.scala 85:20]
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nstate <= UInt<4>("h01") @[rvjtag_tap.scala 85:28]
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skip @[rvjtag_tap.scala 85:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_4 = eq(UInt<4>("h02"), state) @[Conditional.scala 37:30]
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when _T_4 : @[Conditional.scala 39:67]
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node _T_5 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 88:21]
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when _T_5 : @[rvjtag_tap.scala 88:32]
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nstate <= UInt<4>("h09") @[rvjtag_tap.scala 88:40]
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skip @[rvjtag_tap.scala 88:32]
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else : @[rvjtag_tap.scala 89:20]
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nstate <= UInt<4>("h03") @[rvjtag_tap.scala 89:28]
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skip @[rvjtag_tap.scala 89:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_6 = eq(UInt<4>("h03"), state) @[Conditional.scala 37:30]
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when _T_6 : @[Conditional.scala 39:67]
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node _T_7 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 92:21]
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when _T_7 : @[rvjtag_tap.scala 92:32]
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nstate <= UInt<4>("h05") @[rvjtag_tap.scala 92:40]
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skip @[rvjtag_tap.scala 92:32]
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else : @[rvjtag_tap.scala 93:20]
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nstate <= UInt<4>("h04") @[rvjtag_tap.scala 93:28]
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skip @[rvjtag_tap.scala 93:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_8 = eq(UInt<4>("h04"), state) @[Conditional.scala 37:30]
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when _T_8 : @[Conditional.scala 39:67]
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node _T_9 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 96:21]
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when _T_9 : @[rvjtag_tap.scala 96:32]
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nstate <= UInt<4>("h05") @[rvjtag_tap.scala 96:40]
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skip @[rvjtag_tap.scala 96:32]
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else : @[rvjtag_tap.scala 97:20]
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nstate <= UInt<4>("h04") @[rvjtag_tap.scala 97:28]
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skip @[rvjtag_tap.scala 97:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_10 = eq(UInt<4>("h05"), state) @[Conditional.scala 37:30]
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when _T_10 : @[Conditional.scala 39:67]
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node _T_11 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 100:21]
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when _T_11 : @[rvjtag_tap.scala 100:32]
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nstate <= UInt<4>("h08") @[rvjtag_tap.scala 100:40]
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skip @[rvjtag_tap.scala 100:32]
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else : @[rvjtag_tap.scala 101:20]
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nstate <= UInt<4>("h06") @[rvjtag_tap.scala 101:28]
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skip @[rvjtag_tap.scala 101:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_12 = eq(UInt<4>("h06"), state) @[Conditional.scala 37:30]
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when _T_12 : @[Conditional.scala 39:67]
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node _T_13 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 104:18]
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when _T_13 : @[rvjtag_tap.scala 104:29]
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nstate <= UInt<4>("h07") @[rvjtag_tap.scala 104:37]
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skip @[rvjtag_tap.scala 104:29]
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else : @[rvjtag_tap.scala 105:20]
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nstate <= UInt<4>("h06") @[rvjtag_tap.scala 105:28]
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skip @[rvjtag_tap.scala 105:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_14 = eq(UInt<4>("h07"), state) @[Conditional.scala 37:30]
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when _T_14 : @[Conditional.scala 39:67]
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node _T_15 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 108:18]
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when _T_15 : @[rvjtag_tap.scala 108:29]
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nstate <= UInt<4>("h08") @[rvjtag_tap.scala 108:37]
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skip @[rvjtag_tap.scala 108:29]
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else : @[rvjtag_tap.scala 109:20]
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nstate <= UInt<4>("h04") @[rvjtag_tap.scala 109:28]
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skip @[rvjtag_tap.scala 109:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_16 = eq(UInt<4>("h08"), state) @[Conditional.scala 37:30]
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when _T_16 : @[Conditional.scala 39:67]
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node _T_17 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 112:18]
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when _T_17 : @[rvjtag_tap.scala 112:29]
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nstate <= UInt<4>("h02") @[rvjtag_tap.scala 112:37]
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skip @[rvjtag_tap.scala 112:29]
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else : @[rvjtag_tap.scala 113:20]
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nstate <= UInt<4>("h01") @[rvjtag_tap.scala 113:28]
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skip @[rvjtag_tap.scala 113:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_18 = eq(UInt<4>("h09"), state) @[Conditional.scala 37:30]
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when _T_18 : @[Conditional.scala 39:67]
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node _T_19 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 116:18]
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when _T_19 : @[rvjtag_tap.scala 116:29]
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nstate <= UInt<4>("h09") @[rvjtag_tap.scala 116:37]
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skip @[rvjtag_tap.scala 116:29]
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else : @[rvjtag_tap.scala 117:20]
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nstate <= UInt<4>("h0a") @[rvjtag_tap.scala 117:28]
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skip @[rvjtag_tap.scala 117:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_20 = eq(UInt<4>("h0a"), state) @[Conditional.scala 37:30]
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when _T_20 : @[Conditional.scala 39:67]
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node _T_21 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 120:18]
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when _T_21 : @[rvjtag_tap.scala 120:29]
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nstate <= UInt<4>("h0c") @[rvjtag_tap.scala 120:37]
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skip @[rvjtag_tap.scala 120:29]
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else : @[rvjtag_tap.scala 121:20]
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nstate <= UInt<4>("h0b") @[rvjtag_tap.scala 121:28]
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skip @[rvjtag_tap.scala 121:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_22 = eq(UInt<4>("h0b"), state) @[Conditional.scala 37:30]
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when _T_22 : @[Conditional.scala 39:67]
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node _T_23 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 124:18]
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when _T_23 : @[rvjtag_tap.scala 124:29]
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nstate <= UInt<4>("h0c") @[rvjtag_tap.scala 124:37]
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skip @[rvjtag_tap.scala 124:29]
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else : @[rvjtag_tap.scala 125:20]
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nstate <= UInt<4>("h0b") @[rvjtag_tap.scala 125:28]
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skip @[rvjtag_tap.scala 125:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_24 = eq(UInt<4>("h0c"), state) @[Conditional.scala 37:30]
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when _T_24 : @[Conditional.scala 39:67]
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node _T_25 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 128:18]
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when _T_25 : @[rvjtag_tap.scala 128:29]
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nstate <= UInt<4>("h0f") @[rvjtag_tap.scala 128:37]
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skip @[rvjtag_tap.scala 128:29]
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else : @[rvjtag_tap.scala 129:20]
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nstate <= UInt<4>("h0d") @[rvjtag_tap.scala 129:28]
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skip @[rvjtag_tap.scala 129:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_26 = eq(UInt<4>("h0d"), state) @[Conditional.scala 37:30]
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when _T_26 : @[Conditional.scala 39:67]
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node _T_27 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 132:18]
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when _T_27 : @[rvjtag_tap.scala 132:29]
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nstate <= UInt<4>("h0e") @[rvjtag_tap.scala 132:37]
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skip @[rvjtag_tap.scala 132:29]
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else : @[rvjtag_tap.scala 133:20]
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nstate <= UInt<4>("h0d") @[rvjtag_tap.scala 133:28]
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skip @[rvjtag_tap.scala 133:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_28 = eq(UInt<4>("h0e"), state) @[Conditional.scala 37:30]
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when _T_28 : @[Conditional.scala 39:67]
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node _T_29 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 136:18]
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when _T_29 : @[rvjtag_tap.scala 136:29]
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nstate <= UInt<4>("h0f") @[rvjtag_tap.scala 136:37]
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skip @[rvjtag_tap.scala 136:29]
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else : @[rvjtag_tap.scala 137:20]
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nstate <= UInt<4>("h0b") @[rvjtag_tap.scala 137:28]
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skip @[rvjtag_tap.scala 137:20]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_30 = eq(UInt<4>("h0f"), state) @[Conditional.scala 37:30]
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when _T_30 : @[Conditional.scala 39:67]
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node _T_31 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 140:18]
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when _T_31 : @[rvjtag_tap.scala 140:29]
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nstate <= UInt<4>("h02") @[rvjtag_tap.scala 140:37]
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skip @[rvjtag_tap.scala 140:29]
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else : @[rvjtag_tap.scala 141:20]
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nstate <= UInt<4>("h01") @[rvjtag_tap.scala 141:28]
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skip @[rvjtag_tap.scala 141:20]
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skip @[Conditional.scala 39:67]
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