395 lines
11 KiB
Scala
395 lines
11 KiB
Scala
package include
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import chisel3._
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// use this for instance declaration val io = IO(Output(new el2_trace_pkt_t))
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class el2_trace_pkt_t extends Bundle{
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val rv_i_valid_ip = UInt(2.W)
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val rv_i_insn_ip = UInt(32.W)
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val rv_i_address_ip = UInt(32.W)
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val rv_i_exception_ip = UInt(2.W)
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val rv_i_ecause_ip = UInt(5.W)
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val rv_i_interrupt_ip = UInt(2.W)
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val rv_i_tval_ip = UInt(32.W)
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}
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object el2_inst_pkt_t extends Enumeration{
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val NULL = "b0000".U(4.W)
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val MUL = "b0001".U(4.W)
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val LOAD = "b0010".U(4.W)
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val STORE = "b0011".U(4.W)
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val ALU = "b0100".U(4.W)
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val CSRREAD = "b0101".U(4.W)
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val CSRWRITE = "b0110".U(4.W)
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val CSRRW = "b0111".U(4.W)
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val EBREAK = "b1000".U(4.W)
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val ECALL = "b1001".U(4.W)
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val FENCE = "b1010".U(4.W)
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val FENCEI = "b1011".U(4.W)
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val MRET = "b1100".U(4.W)
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val CONDBR = "b1101".U(4.W)
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val JAL = "b1110".U(4.W)
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val BITMANIPU = "b1111".U(4.W)
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}
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class el2_load_cam_pkt_t extends Bundle {
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val valid = UInt(1.W)
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val wb = UInt(1.W)
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val tag = UInt(3.W)
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val rd = UInt(5.W)
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}
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class el2_rets_pkt_t extends Bundle {
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val pc0_call = UInt(1.W)
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val pc0_ret = UInt(1.W)
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val pc0_pc4 = UInt(1.W)
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}
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class el2_br_pkt_t extends Bundle {
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val valid = UInt(1.W)
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val toffset = UInt(12.W)
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val hist = UInt(2.W)
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val br_error = UInt(1.W)
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val br_start_error = UInt(1.W)
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val bank = UInt(1.W)
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val prett = UInt(31.W) // predicted ret target
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val way = UInt(1.W)
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val ret = UInt(1.W)
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}
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class el2_br_tlu_pkt_t extends Bundle {
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val valid = UInt(1.W)
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val hist = UInt(2.W)
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val br_error = UInt(1.W)
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val br_start_error = UInt(1.W)
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val way = UInt(1.W)
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val middle = UInt(1.W)
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}
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class el2_predict_pkt_t extends Bundle {
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val misp = UInt(1.W)
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val ataken = UInt(1.W)
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val boffset = UInt(1.W)
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val pc4 = UInt(1.W)
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val hist = UInt(2.W)
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val toffset = UInt(12.W)
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// val valid = UInt(1.W)
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val br_error = UInt(1.W)
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val br_start_error = UInt(1.W)
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val prett = UInt(31.W)
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val pcall = UInt(1.W)
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val pret = UInt(1.W)
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val pja = UInt(1.W)
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val way = UInt(1.W)
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}
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class el2_trap_pkt_t extends Bundle {
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val legal = UInt(1.W)
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val icaf = UInt(1.W)
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val icaf_f1 = UInt(1.W)
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val icaf_type = UInt(2.W)
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val fence_i = UInt(1.W)
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val i0trigger = UInt(4.W)
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val pmu_i0_itype =UInt(4.W) //new el2_inst_pkt_t //pmu-instructiontype
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val pmu_i0_br_unpred = UInt(1.W) //pmu
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val pmu_divide = UInt(1.W)
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val pmu_lsu_misaligned = UInt(1.W)
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}
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class el2_dest_pkt_t extends Bundle {
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val i0rd = UInt(5.W)
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val i0load = UInt(1.W)
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val i0store = UInt(1.W)
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val i0div = UInt(1.W)
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val i0v = UInt(1.W)
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val i0valid = UInt(1.W)
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val csrwen = UInt(1.W)
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val csrwonly = UInt(1.W)
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val csrwaddr = UInt(12.W)
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}
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class el2_class_pkt_t extends Bundle {
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val mul = UInt(1.W)
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val load = UInt(1.W)
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val alu = UInt(1.W)
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}
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class el2_reg_pkt_t extends Bundle {
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val rs1 = UInt(5.W)
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val rs2 = UInt(5.W)
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val rd = UInt(5.W)
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}
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class el2_alu_pkt_t extends Bundle {
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val land = UInt(1.W)
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val lor = UInt(1.W)
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val lxor = UInt(1.W)
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val sll = UInt(1.W)
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val srl = UInt(1.W)
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val sra = UInt(1.W)
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val beq = UInt(1.W)
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val bne = UInt(1.W)
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val blt = UInt(1.W)
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val bge = UInt(1.W)
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val add = UInt(1.W)
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val sub = UInt(1.W)
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val slt = UInt(1.W)
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val unsign = UInt(1.W)
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val jal = UInt(1.W)
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val predict_t = UInt(1.W)
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val predict_nt = UInt(1.W)
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val csr_write = UInt(1.W)
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val csr_imm = UInt(1.W)
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}
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class el2_lsu_pkt_t extends Bundle {
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val fast_int = Bool()
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val by = Bool()
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val half = Bool()
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val word = Bool()
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val dword = Bool() // for dma
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val load = Bool()
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val store = Bool()
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val unsign = Bool()
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val dma = Bool() // dma pkt
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val store_data_bypass_d = Bool()
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val load_ldst_bypass_d = Bool()
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val store_data_bypass_m = Bool()
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// val valid = Bool()
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}
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class el2_lsu_error_pkt_t extends Bundle {
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// val exc_valid = UInt(1.W)
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val single_ecc_error = UInt(1.W)
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val inst_type = UInt(1.W) //0: Load, 1: Store
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val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault
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val mscause = UInt(4.W)
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val addr = UInt(32.W)
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}
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class el2_dec_pkt_t extends Bundle {
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val alu = Bool()
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val rs1 = Bool()
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val rs2 = Bool()
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val imm12 = Bool()
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val rd = Bool()
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val shimm5 = Bool()
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val imm20 = Bool()
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val pc = Bool()
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val load = Bool()
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val store = Bool()
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val lsu = Bool()
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val add = Bool()
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val sub = Bool()
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val land = Bool()
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val lor = Bool()
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val lxor = Bool()
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val sll = Bool()
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val sra = Bool()
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val srl = Bool()
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val slt = Bool()
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val unsign = Bool()
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val condbr = Bool()
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val beq = Bool()
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val bne = Bool()
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val bge = Bool()
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val blt = Bool()
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val jal = Bool()
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val by = Bool()
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val half = Bool()
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val word = Bool()
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val csr_read = Bool()
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val csr_clr = Bool()
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val csr_set = Bool()
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val csr_write = Bool()
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val csr_imm = Bool()
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val presync = Bool()
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val postsync = Bool()
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val ebreak = Bool()
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val ecall = Bool()
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val mret = Bool()
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val mul = Bool()
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val rs1_sign = Bool()
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val rs2_sign = Bool()
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val low = Bool()
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val div = Bool()
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val rem = Bool()
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val fence = Bool()
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val fence_i = Bool()
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val pm_alu = Bool()
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val legal = Bool()
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}
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class el2_mul_pkt_t extends Bundle {
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// val valid = UInt(1.W)
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val rs1_sign = UInt(1.W)
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val rs2_sign = UInt(1.W)
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val low = UInt(1.W)
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val bext = UInt(1.W)
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val bdep = UInt(1.W)
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val clmul = UInt(1.W)
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val clmulh = UInt(1.W)
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val clmulr = UInt(1.W)
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val grev = UInt(1.W)
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val shfl = UInt(1.W)
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val unshfl = UInt(1.W)
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val crc32_b = UInt(1.W)
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val crc32_h = UInt(1.W)
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val crc32_w = UInt(1.W)
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val crc32c_b = UInt(1.W)
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val crc32c_h = UInt(1.W)
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val crc32c_w = UInt(1.W)
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val bfp = UInt(1.W)
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}
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class el2_div_pkt_t extends Bundle {
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// val valid = UInt(1.W)
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val unsign = UInt(1.W)
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val rem = UInt(1.W)
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}
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class el2_ccm_ext_in_pkt_t extends Bundle {
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val TEST1 = UInt(1.W)
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val RME = UInt(1.W)
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val RM = UInt(4.W)
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val LS = UInt(1.W)
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val DS = UInt(1.W)
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val SD = UInt(1.W)
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val TEST_RNM = UInt(1.W)
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val BC1 = UInt(1.W)
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val BC2 = UInt(1.W)
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}
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class el2_dccm_ext_in_pkt_t extends Bundle {
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val TEST1 = UInt(1.W)
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val RME = UInt(1.W)
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val RM = UInt(4.W)
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val LS = UInt(1.W)
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val DS = UInt(1.W)
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val SD = UInt(1.W)
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val TEST_RNM = UInt(1.W)
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val BC1 = UInt(1.W)
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val BC2 = UInt(1.W)
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}
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class el2_ic_data_ext_in_pkt_t extends Bundle {
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val TEST1 = UInt(1.W)
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val RME = UInt(1.W)
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val RM = UInt(4.W)
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val LS = UInt(1.W)
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val DS = UInt(1.W)
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val SD = UInt(1.W)
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val TEST_RNM = UInt(1.W)
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val BC1 = UInt(1.W)
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val BC2 = UInt(1.W)
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}
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class el2_ic_tag_ext_in_pkt_t extends Bundle {
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val TEST1 = UInt(1.W)
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val RME = UInt(1.W)
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val RM = UInt(4.W)
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val LS = UInt(1.W)
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val DS = UInt(1.W)
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val SD = UInt(1.W)
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val TEST_RNM = UInt(1.W)
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val BC1 = UInt(1.W)
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val BC2 = UInt(1.W)
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}
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class el2_trigger_pkt_t extends Bundle {
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val select = UInt(1.W)
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val match_pkt = UInt(1.W)
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val store = UInt(1.W)
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val load = UInt(1.W)
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val execute = UInt(1.W)
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val m = UInt(1.W)
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val tdata2 = UInt(32.W)
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}
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class el2_cache_debug_pkt_t extends Bundle {
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val icache_wrdata = UInt(71.W) // {dicad1[1:0], dicad0h[31:0], dicad0[31:0]}
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val icache_dicawics = UInt(17.W) // Arraysel:24, Waysel:21:20, Index:16:3
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val icache_rd_valid = UInt(1.W)
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val icache_wr_valid = UInt(1.W)
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}
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class el2_dec_tlu_csr_pkt extends Bundle{
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val csr_misa =UInt(1.W)
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val csr_mvendorid =UInt(1.W)
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val csr_marchid =UInt(1.W)
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val csr_mimpid =UInt(1.W)
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val csr_mhartid =UInt(1.W)
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val csr_mstatus =UInt(1.W)
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val csr_mtvec =UInt(1.W)
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val csr_mip =UInt(1.W)
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val csr_mie =UInt(1.W)
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val csr_mcyclel =UInt(1.W)
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val csr_mcycleh =UInt(1.W)
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val csr_minstretl =UInt(1.W)
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val csr_minstreth =UInt(1.W)
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val csr_mscratch =UInt(1.W)
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val csr_mepc =UInt(1.W)
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val csr_mcause =UInt(1.W)
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val csr_mscause =UInt(1.W)
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val csr_mtval =UInt(1.W)
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val csr_mrac =UInt(1.W)
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val csr_dmst =UInt(1.W)
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val csr_mdseac =UInt(1.W)
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val csr_meihap =UInt(1.W)
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val csr_meivt =UInt(1.W)
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val csr_meipt =UInt(1.W)
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val csr_meicurpl =UInt(1.W)
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val csr_meicidpl =UInt(1.W)
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val csr_dcsr =UInt(1.W)
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val csr_mcgc =UInt(1.W)
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val csr_mfdc =UInt(1.W)
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val csr_dpc =UInt(1.W)
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val csr_mtsel =UInt(1.W)
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val csr_mtdata1 =UInt(1.W)
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val csr_mtdata2 =UInt(1.W)
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val csr_mhpmc3 =UInt(1.W)
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val csr_mhpmc4 =UInt(1.W)
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val csr_mhpmc5 =UInt(1.W)
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val csr_mhpmc6 =UInt(1.W)
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val csr_mhpmc3h =UInt(1.W)
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val csr_mhpmc4h =UInt(1.W)
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val csr_mhpmc5h =UInt(1.W)
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val csr_mhpmc6h =UInt(1.W)
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val csr_mhpme3 =UInt(1.W)
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val csr_mhpme4 =UInt(1.W)
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val csr_mhpme5 =UInt(1.W)
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val csr_mhpme6 =UInt(1.W)
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val csr_mcountinhibit =UInt(1.W)
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val csr_mitctl0 =UInt(1.W)
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val csr_mitctl1 =UInt(1.W)
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val csr_mitb0 =UInt(1.W)
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val csr_mitb1 =UInt(1.W)
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val csr_mitcnt0 =UInt(1.W)
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val csr_mitcnt1 =UInt(1.W)
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val csr_mpmc =UInt(1.W)
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val csr_mcpc =UInt(1.W)
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val csr_meicpct =UInt(1.W)
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val csr_mdeau =UInt(1.W)
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val csr_micect =UInt(1.W)
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val csr_miccmect =UInt(1.W)
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val csr_mdccmect =UInt(1.W)
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val csr_mfdht =UInt(1.W)
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val csr_mfdhs =UInt(1.W)
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val csr_dicawics =UInt(1.W)
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val csr_dicad0h =UInt(1.W)
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val csr_dicad0 =UInt(1.W)
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val csr_dicad1 =UInt(1.W)
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val csr_dicago =UInt(1.W)
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val presync =UInt(1.W)
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val postsync =UInt(1.W)
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val legal =UInt(1.W)
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}
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