228 lines
7.2 KiB
Scala
228 lines
7.2 KiB
Scala
import chisel3._
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import mem._
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import chisel3.util._
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import dmi._
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import include._
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import lib._
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class quasar_wrapper extends Module with lib with RequireAsyncReset {
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val io = IO(new Bundle{
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val dbg_rst_l = Input(AsyncReset())
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val rst_vec = Input(UInt(31.W))
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val nmi_int = Input(Bool())
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val nmi_vec = Input(UInt(31.W))
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val jtag_id = Input(UInt(31.W))
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// AXI Signals
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val lsu_axi = new axi_channels(LSU_BUS_TAG)
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val ifu_axi = new axi_channels(IFU_BUS_TAG)
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val sb_axi = new axi_channels(SB_BUS_TAG)
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val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
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// DMA slave
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val dma = new Bundle{
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val ahb= Flipped(new ahb_channel())
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val hsel = Input(Bool())
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val hreadyin = Input(Bool())}
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// val dma_haddr = Input(UInt(32.W))
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// val dma_hburst = Input(UInt(3.W))
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// val dma_hmastlock = Input(Bool())
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// val dma_hprot = Input(UInt(4.W))
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// val dma_hsize = Input(UInt(3.W))
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// val dma_htrans = Input(UInt(2.W))
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// val dma_hwrite = Input(Bool())
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// val dma_hwdata = Input(UInt(64.W))
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// val dma_hrdata = Output(UInt(64.W))
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// val dma_hreadyout = Output(Bool())
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// val dma_hresp = Output(Bool())
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val lsu_bus_clk_en = Input(Bool())
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val ifu_bus_clk_en = Input(Bool())
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val dbg_bus_clk_en = Input(Bool())
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val dma_bus_clk_en = Input(Bool())
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val timer_int = Input(Bool())
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val soft_int = Input(Bool())
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val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
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val dec_tlu_perfcnt0 = Output(Bool())
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val dec_tlu_perfcnt1 = Output(Bool())
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val dec_tlu_perfcnt2 = Output(Bool())
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val dec_tlu_perfcnt3 = Output(Bool())
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val jtag_tck = Input(Clock())
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val jtag_tms = Input(Bool())
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val jtag_tdi = Input(Bool())
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val jtag_trst_n = Input(Bool())
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val jtag_tdo = Output(Bool())
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val core_id = Input(UInt(28.W))
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val mpc_debug_halt_req = Input(Bool())
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val mpc_debug_run_req = Input(Bool())
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val mpc_reset_run_req = Input(Bool())
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val mpc_debug_halt_ack = Output(Bool())
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val mpc_debug_run_ack = Output(Bool())
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val debug_brkpt_status = Output(Bool())
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val i_cpu_halt_req = Input(Bool())
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val i_cpu_run_req = Input(Bool())
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val o_cpu_halt_ack = Output(Bool())
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val o_cpu_halt_status = Output(Bool())
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val o_debug_mode_status = Output(Bool())
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val o_cpu_run_ack = Output(Bool())
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val mbist_mode = Input(Bool())
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val rv_trace_pkt = new trace_pkt_t()
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val scan_mode = Input(Bool())
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})
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val mem = Module(new quasar.mem())
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val dmi_wrapper = Module(new dmi_wrapper())
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val swerv = Module(new quasar())
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dmi_wrapper.io.trst_n := io.jtag_trst_n
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dmi_wrapper.io.tck := io.jtag_tck
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dmi_wrapper.io.tms := io.jtag_tms
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dmi_wrapper.io.tdi := io.jtag_tdi
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dmi_wrapper.io.core_clk := clock
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dmi_wrapper.io.jtag_id := io.jtag_id
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dmi_wrapper.io.rd_data := swerv.io.dmi_reg_rdata
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dmi_wrapper.io.core_rst_n := io.dbg_rst_l
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swerv.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
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swerv.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
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swerv.io.dmi_reg_en := dmi_wrapper.io.reg_en
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swerv.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
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swerv.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
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io.jtag_tdo := dmi_wrapper.io.tdo
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// Memory signals
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mem.io.dccm_clk_override := swerv.io.dccm_clk_override
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mem.io.icm_clk_override := swerv.io.icm_clk_override
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mem.io.dec_tlu_core_ecc_disable := swerv.io.dec_tlu_core_ecc_disable
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mem.io.dccm <> swerv.io.dccm
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mem.io.rst_l := reset
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mem.io.clk := clock
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mem.io.scan_mode := io.scan_mode
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// Memory outputs
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swerv.io.dbg_rst_l := io.dbg_rst_l
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swerv.io.ic <> mem.io.ic
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swerv.io.iccm <> mem.io.iccm
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swerv.io.ahb.in <> 0.U.asTypeOf(swerv.io.ahb.in)
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swerv.io.lsu_ahb.in <> 0.U.asTypeOf(swerv.io.lsu_ahb.in)
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swerv.io.sb_ahb.in <> 0.U.asTypeOf(swerv.io.sb_ahb.in)
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io.dma.ahb.in <> 0.U.asTypeOf(io.dma.ahb.in)
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// swerv.io.sb_hready := 0.U
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// swerv.io.hrdata := 0.U
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// swerv.io.sb_hresp := 0.U
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// swerv.io.lsu_hrdata := 0.U
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// swerv.io.lsu_hresp := 0.U
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// swerv.io.lsu_hready := 0.U
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// swerv.io.hready := 0.U
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// swerv.io.hresp := 0.U
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// swerv.io.sb_hrdata := 0.U
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swerv.io.scan_mode := io.scan_mode
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// SweRV Inputs
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swerv.io.dbg_rst_l := io.dbg_rst_l
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swerv.io.rst_vec := io.rst_vec
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swerv.io.nmi_int := io.nmi_int
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swerv.io.nmi_vec := io.nmi_vec
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// external halt/run interface
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swerv.io.i_cpu_halt_req := io.i_cpu_halt_req
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swerv.io.i_cpu_run_req := io.i_cpu_run_req
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swerv.io.core_id := io.core_id
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// external MPC halt/run interface
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swerv.io.mpc_debug_halt_req := io.mpc_debug_halt_req
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swerv.io.mpc_debug_run_req := io.mpc_debug_run_req
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swerv.io.mpc_reset_run_req := io.mpc_reset_run_req
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//-------------------------- LSU AXI signals--------------------------
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// AXI Write Channels
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swerv.io.lsu_axi <> io.lsu_axi
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//-------------------------- IFU AXI signals--------------------------
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// AXI Write Channels
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swerv.io.ifu_axi <> io.ifu_axi
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//-------------------------- SB AXI signals--------------------------
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// AXI Write Channels
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swerv.io.sb_axi <> io.sb_axi
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//-------------------------- DMA AXI signals--------------------------
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// AXI Write Channels
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swerv.io.dma_axi <> io.dma_axi
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// DMA Slave
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swerv.io.dma.hsel := io.dma.hsel
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swerv.io.dma.ahb.out <> io.dma.ahb.out
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// swerv.io.dma_haddr := io.dma_haddr
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// swerv.io.dma_hburst := io.dma_hburst
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// swerv.io.dma_hmastlock := io.dma_hmastlock
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// swerv.io.dma_hprot := io.dma_hprot
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// swerv.io.dma_hsize := io.dma_hsize
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// swerv.io.dma_htrans := io.dma_htrans
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// swerv.io.dma_hwrite := io.dma_hwrite
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// swerv.io.dma_hwdata := io.dma_hwdata
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swerv.io.dma.hreadyin := io.dma.hreadyin
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swerv.io.lsu_bus_clk_en
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swerv.io.ifu_bus_clk_en
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swerv.io.dbg_bus_clk_en
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swerv.io.dma_bus_clk_en
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swerv.io.dmi_reg_en
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swerv.io.dmi_reg_addr
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swerv.io.dmi_reg_wr_en
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swerv.io.dmi_reg_wdata
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swerv.io.dmi_hard_reset
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swerv.io.extintsrc_req
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swerv.io.timer_int
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swerv.io.soft_int
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swerv.io.scan_mode
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swerv.io.lsu_bus_clk_en := io.lsu_bus_clk_en
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swerv.io.ifu_bus_clk_en := io.ifu_bus_clk_en
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swerv.io.dbg_bus_clk_en := io.dbg_bus_clk_en
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swerv.io.dma_bus_clk_en := io.dma_bus_clk_en
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swerv.io.timer_int := io.timer_int
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swerv.io.soft_int := io.soft_int
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swerv.io.extintsrc_req := io.extintsrc_req
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// Outputs
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val core_rst_l = swerv.io.core_rst_l
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io.rv_trace_pkt := swerv.io.rv_trace_pkt
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// external halt/run interface
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io.o_cpu_halt_ack := swerv.io.o_cpu_halt_ack
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io.o_cpu_halt_status := swerv.io.o_cpu_halt_status
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io.o_cpu_run_ack := swerv.io.o_cpu_run_ack
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io.o_debug_mode_status := swerv.io.o_debug_mode_status
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io.mpc_debug_halt_ack := swerv.io.mpc_debug_halt_ack
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io.mpc_debug_run_ack := swerv.io.mpc_debug_run_ack
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io.debug_brkpt_status := swerv.io.debug_brkpt_status
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io.dec_tlu_perfcnt0 := swerv.io.dec_tlu_perfcnt0
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io.dec_tlu_perfcnt1 := swerv.io.dec_tlu_perfcnt1
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io.dec_tlu_perfcnt2 := swerv.io.dec_tlu_perfcnt2
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io.dec_tlu_perfcnt3 := swerv.io.dec_tlu_perfcnt3
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//-------------------------- LSU AXI signals--------------------------
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// AXI Write Channels
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// DMA Slave
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// io.dma_hrdata := swerv.io.dma_hrdata
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// io.dma_hreadyout := swerv.io.dma_hreadyout
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// io.dma_hresp := swerv.io.dma_hresp
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}
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object QUASAR_Wrp extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()))
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} |