165 lines
8.7 KiB
Scala
165 lines
8.7 KiB
Scala
package lsu
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import chisel3._
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import chisel3.util._
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import chisel3.experimental.chiselName
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import include._
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import lib._
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@chiselName
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class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset {
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val io = IO(new Bundle{
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val lsu_c2_r_clk = Input(Clock())
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val lsu_pkt_m = Flipped(Valid(new el2_lsu_pkt_t))
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val lsu_pkt_r = Flipped(Valid(new el2_lsu_pkt_t))
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val stbuf_data_any = Input(UInt(DCCM_DATA_WIDTH.W))
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val dec_tlu_core_ecc_disable = Input(Bool())
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val lsu_dccm_rden_r = Input(Bool())
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val addr_in_dccm_r = Input(Bool())
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val lsu_addr_r = Input(UInt(DCCM_BITS.W))
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val end_addr_r = Input(UInt(DCCM_BITS.W))
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val lsu_addr_m = Input(UInt(DCCM_BITS.W))
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val end_addr_m = Input(UInt(DCCM_BITS.W))
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val dccm_rdata_hi_r = Input(UInt(DCCM_DATA_WIDTH.W))
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val dccm_rdata_lo_r = Input(UInt(DCCM_DATA_WIDTH.W))
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val dccm_rdata_hi_m = Input(UInt(DCCM_DATA_WIDTH.W))
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val dccm_rdata_lo_m = Input(UInt(DCCM_DATA_WIDTH.W))
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val dccm_data_ecc_hi_r = Input(UInt(DCCM_ECC_WIDTH.W))
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val dccm_data_ecc_lo_r = Input(UInt(DCCM_ECC_WIDTH.W))
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val dccm_data_ecc_hi_m = Input(UInt(DCCM_ECC_WIDTH.W))
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val dccm_data_ecc_lo_m = Input(UInt(DCCM_ECC_WIDTH.W))
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val ld_single_ecc_error_r = Input(Bool())
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val ld_single_ecc_error_r_ff = Input(Bool())
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val lsu_dccm_rden_m = Input(Bool())
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val addr_in_dccm_m = Input(Bool())
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val dma_dccm_wen = Input(Bool())
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val dma_dccm_wdata_lo = Input(UInt(32.W))
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val dma_dccm_wdata_hi = Input(UInt(32.W))
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val scan_mode = Input(Bool())
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//Outputs
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val sec_data_hi_r = Output(UInt(DCCM_DATA_WIDTH.W))
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val sec_data_lo_r = Output(UInt(DCCM_DATA_WIDTH.W))
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val sec_data_hi_m = Output(UInt(DCCM_DATA_WIDTH.W))
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val sec_data_lo_m = Output(UInt(DCCM_DATA_WIDTH.W))
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val sec_data_hi_r_ff = Output(UInt(DCCM_DATA_WIDTH.W))
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val sec_data_lo_r_ff = Output(UInt(DCCM_DATA_WIDTH.W))
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val dma_dccm_wdata_ecc_hi = Output(UInt(DCCM_ECC_WIDTH.W))
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val dma_dccm_wdata_ecc_lo = Output(UInt(DCCM_ECC_WIDTH.W))
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val stbuf_ecc_any = Output(UInt(DCCM_ECC_WIDTH.W))
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val sec_data_ecc_hi_r_ff = Output(UInt(DCCM_ECC_WIDTH.W))
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val sec_data_ecc_lo_r_ff = Output(UInt(DCCM_ECC_WIDTH.W))
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val single_ecc_error_hi_r = Output(Bool())
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val single_ecc_error_lo_r = Output(Bool())
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val lsu_single_ecc_error_r = Output(Bool())
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val lsu_double_ecc_error_r = Output(Bool())
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val lsu_single_ecc_error_m = Output(Bool())
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val lsu_double_ecc_error_m = Output(Bool())
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})
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val is_ldst_r = WireInit(Bool(),init = 0.U)
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val is_ldst_hi_any = WireInit(Bool(),init = 0.U)
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val is_ldst_lo_any = WireInit(Bool(),init = 0.U)
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val dccm_wdata_hi_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
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val dccm_wdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
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val dccm_rdata_hi_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
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val dccm_rdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
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// val dccm_wdata_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
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//val dccm_wdata_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
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val dccm_data_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
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val dccm_data_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
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val double_ecc_error_hi_m = WireInit(Bool(),init = 0.U)
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val double_ecc_error_lo_m = WireInit(Bool(),init = 0.U)
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val double_ecc_error_hi_r = WireInit(Bool(),init = 0.U)
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val double_ecc_error_lo_r = WireInit(Bool(),init = 0.U)
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val ldst_dual_m = WireInit(Bool(),init = 0.U)
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val ldst_dual_r = WireInit(Bool(),init = 0.U)
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val is_ldst_m = WireInit(Bool(),init = 0.U)
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val is_ldst_hi_m = WireInit(Bool(),init = 0.U)
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val is_ldst_lo_m = WireInit(Bool(),init = 0.U)
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val is_ldst_hi_r = WireInit(Bool(),init = 0.U)
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val is_ldst_lo_r = WireInit(Bool(),init = 0.U)
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io.sec_data_hi_m :=0.U
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io.sec_data_lo_m :=0.U
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io.lsu_single_ecc_error_m :=0.U
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io.lsu_double_ecc_error_m :=0.U
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//////////////////////////////CODE STARTS HERE///////////////////////
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val (ecc_out_hi_nc, sec_data_hi_any, single_ecc_error_hi_any, double_ecc_error_hi_any) = if(DCCM_ENABLE)
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rvecc_decode(is_ldst_hi_any, dccm_rdata_hi_any, dccm_data_ecc_hi_any, 0.U) else (0.U, 0.U, 0.U, 0.U)
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val ( ecc_out_lo_nc, sec_data_lo_any, single_ecc_error_lo_any, double_ecc_error_lo_any) = if(DCCM_ENABLE)
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rvecc_decode(is_ldst_lo_any, dccm_rdata_lo_any, dccm_data_ecc_lo_any, 0.U) else (0.U, 0.U, 0.U, 0.U)
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val dccm_wdata_ecc_lo_any = if(DCCM_ENABLE) rvecc_encode(dccm_wdata_lo_any) else (0.U)
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val dccm_wdata_ecc_hi_any = if(DCCM_ENABLE) rvecc_encode(dccm_wdata_hi_any) else (0.U)
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when (LOAD_TO_USE_PLUS1.B) {
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ldst_dual_r := io.lsu_addr_r(2) =/= io.end_addr_r(2)
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is_ldst_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.bits.load | io.lsu_pkt_r.bits.store) & io.addr_in_dccm_r & io.lsu_dccm_rden_r
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is_ldst_lo_r := is_ldst_r & !io.dec_tlu_core_ecc_disable
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is_ldst_hi_r := is_ldst_r & (ldst_dual_r | io.lsu_pkt_r.bits.dma) & !io.dec_tlu_core_ecc_disable
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is_ldst_hi_any := is_ldst_hi_r
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dccm_rdata_hi_any := io.dccm_rdata_hi_r
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dccm_data_ecc_hi_any := io.dccm_data_ecc_hi_r
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is_ldst_lo_any := is_ldst_lo_r
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dccm_rdata_lo_any := io.dccm_rdata_lo_r
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dccm_data_ecc_lo_any := io.dccm_data_ecc_lo_r
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io.sec_data_hi_r := sec_data_hi_any;
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io.single_ecc_error_hi_r := single_ecc_error_hi_any
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double_ecc_error_hi_r := double_ecc_error_hi_any
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io.sec_data_lo_r := sec_data_lo_any
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io.single_ecc_error_lo_r := single_ecc_error_lo_any
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double_ecc_error_lo_r := double_ecc_error_lo_any
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io.lsu_single_ecc_error_r := io.single_ecc_error_hi_r | io.single_ecc_error_lo_r;
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io.lsu_double_ecc_error_r := double_ecc_error_hi_r | double_ecc_error_lo_r
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}
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.otherwise {
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ldst_dual_m := io.lsu_addr_m(2) =/= io.end_addr_m(2)
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is_ldst_m := io.lsu_pkt_m.valid & (io.lsu_pkt_m.bits.load | io.lsu_pkt_m.bits.store) & io.addr_in_dccm_m & io.lsu_dccm_rden_m
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is_ldst_lo_m := is_ldst_m & !io.dec_tlu_core_ecc_disable
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is_ldst_hi_m := is_ldst_m & (ldst_dual_m | io.lsu_pkt_m.bits.dma) & !io.dec_tlu_core_ecc_disable
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is_ldst_hi_any := is_ldst_hi_m
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dccm_rdata_hi_any := io.dccm_rdata_hi_m
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dccm_data_ecc_hi_any := io.dccm_data_ecc_hi_m
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is_ldst_lo_any := is_ldst_lo_m
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dccm_rdata_lo_any := io.dccm_rdata_lo_m
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dccm_data_ecc_lo_any := io.dccm_data_ecc_lo_m
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io.sec_data_hi_m := sec_data_hi_any
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double_ecc_error_hi_m := double_ecc_error_hi_any
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io.sec_data_lo_m := sec_data_lo_any
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double_ecc_error_lo_m := double_ecc_error_lo_any
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io.lsu_single_ecc_error_m := single_ecc_error_hi_any | single_ecc_error_lo_any;
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io.lsu_double_ecc_error_m := double_ecc_error_hi_m | double_ecc_error_lo_m
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withClock(io.lsu_c2_r_clk) {io.lsu_single_ecc_error_r := RegNext(io.lsu_single_ecc_error_m,0.U)}
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withClock(io.lsu_c2_r_clk) {io.lsu_double_ecc_error_r := RegNext(io.lsu_double_ecc_error_m,0.U)}
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withClock(io.lsu_c2_r_clk) {io.single_ecc_error_lo_r := RegNext(single_ecc_error_lo_any,0.U)}
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withClock(io.lsu_c2_r_clk) {io.single_ecc_error_hi_r := RegNext(single_ecc_error_hi_any,0.U)}
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withClock(io.lsu_c2_r_clk) {io.sec_data_hi_r := RegNext(io.sec_data_hi_m,0.U)}
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withClock(io.lsu_c2_r_clk) {io.sec_data_lo_r := RegNext(io.sec_data_lo_m,0.U)}
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}
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// Logic for ECC generation during write
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dccm_wdata_lo_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_lo_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_lo, io.stbuf_data_any))
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dccm_wdata_hi_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_hi_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_hi, io.stbuf_data_any))
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io.sec_data_ecc_hi_r_ff := dccm_wdata_ecc_hi_any
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io.sec_data_ecc_lo_r_ff := dccm_wdata_ecc_lo_any
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io.stbuf_ecc_any := dccm_wdata_ecc_lo_any
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io.dma_dccm_wdata_ecc_hi := dccm_wdata_ecc_hi_any
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io.dma_dccm_wdata_ecc_lo := dccm_wdata_ecc_lo_any
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io.sec_data_hi_r_ff := rvdffe(io.sec_data_hi_r, io.ld_single_ecc_error_r,clock,io.scan_mode)
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io.sec_data_lo_r_ff := rvdffe(io.sec_data_lo_r, io.ld_single_ecc_error_r,clock,io.scan_mode)
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}
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object eccmain extends App{
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println("Generate Verilog")
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println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_ecc()))
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}
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