24 lines
628 B
Verilog
24 lines
628 B
Verilog
module MakeInout(
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input clock,
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input reset,
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input [15:0] io_in,
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input io_clk,
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input io_reset,
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output [15:0] io_out
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);
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wire [15:0] m_in; // @[GCD.scala 40:17]
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wire m_clk; // @[GCD.scala 40:17]
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wire m_reset; // @[GCD.scala 40:17]
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wire [15:0] m_out; // @[GCD.scala 40:17]
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rvdff m ( // @[GCD.scala 40:17]
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.in(m_in),
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.clk(m_clk),
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.reset(m_reset),
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.out(m_out)
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);
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assign io_out = m_out; // @[GCD.scala 42:8]
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assign m_in = io_in; // @[GCD.scala 42:8]
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assign m_clk = io_clk; // @[GCD.scala 42:8]
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assign m_reset = io_reset; // @[GCD.scala 42:8]
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endmodule
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