273 lines
16 KiB
Plaintext
273 lines
16 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit rvjtag_tap :
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module rvjtag_tap :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip trst : AsyncReset, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>, flip rd_status : UInt<2>, flip dmi_stat : UInt<2>, flip idle : UInt<3>, flip version : UInt<4>, flip jtag_id : UInt<31>, flip rd_data : UInt<32>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_en : UInt<1>, rd_en : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<0>}
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wire nsr : UInt<41>
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nsr <= UInt<41>("h00")
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reg sr : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 32:55]
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sr <= nsr @[rvjtag_tap.scala 32:55]
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wire dr : UInt<41>
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dr <= UInt<41>("h00")
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wire nstate : UInt<4>
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nstate <= UInt<4>("h00")
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reg state : UInt, io.tck with : (reset => (io.trst, UInt<4>("h00"))) @[rvjtag_tap.scala 39:57]
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state <= nstate @[rvjtag_tap.scala 39:57]
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wire ir : UInt<5>
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ir <= UInt<5>("h00")
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wire jtag_reset : UInt<1>
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jtag_reset <= UInt<1>("h00")
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wire shift_dr : UInt<1>
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shift_dr <= UInt<1>("h00")
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wire pause_dr : UInt<1>
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pause_dr <= UInt<1>("h00")
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wire update_dr : UInt<1>
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update_dr <= UInt<1>("h00")
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wire capture_dr : UInt<1>
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capture_dr <= UInt<1>("h00")
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wire shift_ir : UInt<1>
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shift_ir <= UInt<1>("h00")
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wire pause_ir : UInt<1>
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pause_ir <= UInt<1>("h00")
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wire update_ir : UInt<1>
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update_ir <= UInt<1>("h00")
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wire capture_ir : UInt<1>
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capture_ir <= UInt<1>("h00")
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wire dr_en : UInt<2>
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dr_en <= UInt<1>("h00")
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wire devid_sel : UInt<1>
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devid_sel <= UInt<1>("h00")
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node _T = eq(UInt<4>("h00"), state) @[Conditional.scala 37:30]
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when _T : @[Conditional.scala 40:58]
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node _T_1 = mux(io.tms, UInt<4>("h00"), UInt<4>("h01")) @[rvjtag_tap.scala 55:46]
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nstate <= _T_1 @[rvjtag_tap.scala 55:40]
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jtag_reset <= UInt<1>("h01") @[rvjtag_tap.scala 56:18]
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skip @[Conditional.scala 40:58]
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else : @[Conditional.scala 39:67]
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node _T_2 = eq(UInt<4>("h01"), state) @[Conditional.scala 37:30]
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when _T_2 : @[Conditional.scala 39:67]
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node _T_3 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 57:47]
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nstate <= _T_3 @[rvjtag_tap.scala 57:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_4 = eq(UInt<4>("h02"), state) @[Conditional.scala 37:30]
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when _T_4 : @[Conditional.scala 39:67]
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node _T_5 = mux(io.tms, UInt<4>("h09"), UInt<4>("h03")) @[rvjtag_tap.scala 58:47]
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nstate <= _T_5 @[rvjtag_tap.scala 58:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_6 = eq(UInt<4>("h03"), state) @[Conditional.scala 37:30]
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when _T_6 : @[Conditional.scala 39:67]
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node _T_7 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 59:47]
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nstate <= _T_7 @[rvjtag_tap.scala 59:41]
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capture_dr <= UInt<1>("h01") @[rvjtag_tap.scala 60:18]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_8 = eq(UInt<4>("h04"), state) @[Conditional.scala 37:30]
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when _T_8 : @[Conditional.scala 39:67]
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node _T_9 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 61:47]
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nstate <= _T_9 @[rvjtag_tap.scala 61:41]
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shift_dr <= UInt<1>("h01") @[rvjtag_tap.scala 62:16]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_10 = eq(UInt<4>("h05"), state) @[Conditional.scala 37:30]
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when _T_10 : @[Conditional.scala 39:67]
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node _T_11 = mux(io.tms, UInt<4>("h08"), UInt<4>("h06")) @[rvjtag_tap.scala 63:47]
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nstate <= _T_11 @[rvjtag_tap.scala 63:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_12 = eq(UInt<4>("h06"), state) @[Conditional.scala 37:30]
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when _T_12 : @[Conditional.scala 39:67]
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node _T_13 = mux(io.tms, UInt<4>("h07"), UInt<4>("h06")) @[rvjtag_tap.scala 64:47]
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nstate <= _T_13 @[rvjtag_tap.scala 64:41]
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pause_dr <= UInt<1>("h01") @[rvjtag_tap.scala 65:16]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_14 = eq(UInt<4>("h07"), state) @[Conditional.scala 37:30]
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when _T_14 : @[Conditional.scala 39:67]
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node _T_15 = mux(io.tms, UInt<4>("h08"), UInt<4>("h04")) @[rvjtag_tap.scala 66:47]
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nstate <= _T_15 @[rvjtag_tap.scala 66:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_16 = eq(UInt<4>("h08"), state) @[Conditional.scala 37:30]
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when _T_16 : @[Conditional.scala 39:67]
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node _T_17 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 67:47]
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nstate <= _T_17 @[rvjtag_tap.scala 67:41]
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update_dr <= UInt<1>("h01") @[rvjtag_tap.scala 68:17]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_18 = eq(UInt<4>("h09"), state) @[Conditional.scala 37:30]
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when _T_18 : @[Conditional.scala 39:67]
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node _T_19 = mux(io.tms, UInt<4>("h00"), UInt<4>("h0a")) @[rvjtag_tap.scala 69:47]
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nstate <= _T_19 @[rvjtag_tap.scala 69:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_20 = eq(UInt<4>("h0a"), state) @[Conditional.scala 37:30]
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when _T_20 : @[Conditional.scala 39:67]
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node _T_21 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 70:47]
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nstate <= _T_21 @[rvjtag_tap.scala 70:41]
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capture_ir <= UInt<1>("h01") @[rvjtag_tap.scala 71:18]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_22 = eq(UInt<4>("h0b"), state) @[Conditional.scala 37:30]
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when _T_22 : @[Conditional.scala 39:67]
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node _T_23 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 72:47]
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nstate <= _T_23 @[rvjtag_tap.scala 72:41]
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shift_ir <= UInt<1>("h01") @[rvjtag_tap.scala 73:16]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_24 = eq(UInt<4>("h0c"), state) @[Conditional.scala 37:30]
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when _T_24 : @[Conditional.scala 39:67]
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node _T_25 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0d")) @[rvjtag_tap.scala 74:47]
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nstate <= _T_25 @[rvjtag_tap.scala 74:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_26 = eq(UInt<4>("h0d"), state) @[Conditional.scala 37:30]
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when _T_26 : @[Conditional.scala 39:67]
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node _T_27 = mux(io.tms, UInt<4>("h0e"), UInt<4>("h0d")) @[rvjtag_tap.scala 75:47]
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nstate <= _T_27 @[rvjtag_tap.scala 75:41]
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pause_ir <= UInt<1>("h01") @[rvjtag_tap.scala 76:16]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_28 = eq(UInt<4>("h0e"), state) @[Conditional.scala 37:30]
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when _T_28 : @[Conditional.scala 39:67]
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node _T_29 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0b")) @[rvjtag_tap.scala 77:47]
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nstate <= _T_29 @[rvjtag_tap.scala 77:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_30 = eq(UInt<4>("h0f"), state) @[Conditional.scala 37:30]
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when _T_30 : @[Conditional.scala 39:67]
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node _T_31 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 78:47]
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nstate <= _T_31 @[rvjtag_tap.scala 78:41]
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update_ir <= UInt<1>("h01") @[rvjtag_tap.scala 79:17]
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skip @[Conditional.scala 39:67]
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node _T_32 = or(shift_dr, shift_ir) @[rvjtag_tap.scala 81:28]
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io.tdoEnable <= _T_32 @[rvjtag_tap.scala 81:16]
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node _T_33 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:93]
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node _T_34 = eq(_T_33, UInt<1>("h00")) @[rvjtag_tap.scala 85:98]
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node _T_35 = bits(_T_34, 0, 0) @[rvjtag_tap.scala 85:106]
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node _T_36 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:123]
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node _T_37 = mux(_T_35, UInt<5>("h01f"), _T_36) @[rvjtag_tap.scala 85:89]
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node _T_38 = mux(update_ir, _T_37, UInt<1>("h00")) @[rvjtag_tap.scala 85:75]
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node _T_39 = mux(jtag_reset, UInt<1>("h01"), _T_38) @[rvjtag_tap.scala 85:56]
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reg _T_40 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h01"))) @[rvjtag_tap.scala 85:52]
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_T_40 <= _T_39 @[rvjtag_tap.scala 85:52]
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ir <= _T_40 @[rvjtag_tap.scala 85:6]
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node _T_41 = eq(ir, UInt<5>("h01")) @[rvjtag_tap.scala 86:18]
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devid_sel <= _T_41 @[rvjtag_tap.scala 86:13]
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node _T_42 = eq(ir, UInt<5>("h011")) @[rvjtag_tap.scala 87:22]
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node _T_43 = eq(ir, UInt<5>("h010")) @[rvjtag_tap.scala 87:32]
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node _T_44 = cat(_T_42, _T_43) @[Cat.scala 29:58]
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dr_en <= _T_44 @[rvjtag_tap.scala 87:13]
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node _T_45 = eq(shift_dr, UInt<1>("h01")) @[rvjtag_tap.scala 92:16]
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when _T_45 : @[rvjtag_tap.scala 92:23]
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node _T_46 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 93:15]
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node _T_47 = eq(_T_46, UInt<1>("h01")) @[rvjtag_tap.scala 93:18]
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when _T_47 : @[rvjtag_tap.scala 93:28]
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node _T_48 = bits(sr, 40, 1) @[rvjtag_tap.scala 93:49]
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node _T_49 = cat(io.tdi, _T_48) @[Cat.scala 29:58]
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nsr <= _T_49 @[rvjtag_tap.scala 93:33]
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skip @[rvjtag_tap.scala 93:28]
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else : @[rvjtag_tap.scala 94:54]
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node _T_50 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 94:22]
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node _T_51 = eq(_T_50, UInt<1>("h01")) @[rvjtag_tap.scala 94:25]
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node _T_52 = eq(devid_sel, UInt<1>("h01")) @[rvjtag_tap.scala 94:44]
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node _T_53 = or(_T_51, _T_52) @[rvjtag_tap.scala 94:32]
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when _T_53 : @[rvjtag_tap.scala 94:54]
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node _T_54 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
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node _T_55 = bits(sr, 31, 1) @[rvjtag_tap.scala 94:106]
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node _T_56 = cat(_T_54, io.tdi) @[Cat.scala 29:58]
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node _T_57 = cat(_T_56, _T_55) @[Cat.scala 29:58]
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nsr <= _T_57 @[rvjtag_tap.scala 94:59]
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skip @[rvjtag_tap.scala 94:54]
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else : @[rvjtag_tap.scala 95:17]
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node _T_58 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12]
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node _T_59 = cat(_T_58, io.tdi) @[Cat.scala 29:58]
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nsr <= _T_59 @[rvjtag_tap.scala 95:22]
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skip @[rvjtag_tap.scala 95:17]
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skip @[rvjtag_tap.scala 92:23]
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else : @[rvjtag_tap.scala 97:33]
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node _T_60 = eq(capture_dr, UInt<1>("h01")) @[rvjtag_tap.scala 97:26]
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when _T_60 : @[rvjtag_tap.scala 97:33]
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node _T_61 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 98:17]
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when _T_61 : @[rvjtag_tap.scala 98:21]
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node _T_62 = mux(UInt<1>("h00"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
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node _T_63 = cat(UInt<6>("h07"), io.version) @[Cat.scala 29:58]
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node _T_64 = cat(_T_62, io.idle) @[Cat.scala 29:58]
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node _T_65 = cat(_T_64, io.dmi_stat) @[Cat.scala 29:58]
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node _T_66 = cat(_T_65, _T_63) @[Cat.scala 29:58]
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nsr <= _T_66 @[rvjtag_tap.scala 98:26]
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skip @[rvjtag_tap.scala 98:21]
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else : @[rvjtag_tap.scala 99:28]
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node _T_67 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 99:24]
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when _T_67 : @[rvjtag_tap.scala 99:28]
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node _T_68 = mux(UInt<1>("h00"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
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node _T_69 = cat(_T_68, io.rd_data) @[Cat.scala 29:58]
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node _T_70 = cat(_T_69, io.rd_status) @[Cat.scala 29:58]
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nsr <= _T_70 @[rvjtag_tap.scala 99:33]
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skip @[rvjtag_tap.scala 99:28]
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else : @[rvjtag_tap.scala 100:29]
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when devid_sel : @[rvjtag_tap.scala 100:29]
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node _T_71 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
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node _T_72 = cat(_T_71, io.jtag_id) @[Cat.scala 29:58]
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node _T_73 = cat(_T_72, UInt<1>("h01")) @[Cat.scala 29:58]
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nsr <= _T_73 @[rvjtag_tap.scala 100:34]
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skip @[rvjtag_tap.scala 100:29]
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skip @[rvjtag_tap.scala 97:33]
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else : @[rvjtag_tap.scala 102:30]
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node _T_74 = eq(shift_ir, UInt<1>("h01")) @[rvjtag_tap.scala 102:23]
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when _T_74 : @[rvjtag_tap.scala 102:30]
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node _T_75 = mux(UInt<1>("h00"), UInt<36>("h0fffffffff"), UInt<36>("h00")) @[Bitwise.scala 72:12]
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node _T_76 = bits(sr, 4, 1) @[rvjtag_tap.scala 102:78]
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node _T_77 = cat(_T_75, io.tdi) @[Cat.scala 29:58]
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node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58]
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nsr <= _T_78 @[rvjtag_tap.scala 102:35]
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skip @[rvjtag_tap.scala 102:30]
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else : @[rvjtag_tap.scala 103:32]
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node _T_79 = eq(capture_ir, UInt<1>("h01")) @[rvjtag_tap.scala 103:25]
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when _T_79 : @[rvjtag_tap.scala 103:32]
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node _T_80 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12]
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node _T_81 = cat(_T_80, UInt<1>("h01")) @[Cat.scala 29:58]
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nsr <= _T_81 @[rvjtag_tap.scala 103:37]
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skip @[rvjtag_tap.scala 103:32]
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node _T_82 = bits(sr, 0, 0) @[rvjtag_tap.scala 106:40]
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reg _T_83 : UInt<1>, io.tck with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 106:37]
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_T_83 <= _T_82 @[rvjtag_tap.scala 106:37]
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io.tdo <= _T_83 @[rvjtag_tap.scala 106:28]
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node _T_84 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 108:89]
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node _T_85 = bits(_T_84, 0, 0) @[rvjtag_tap.scala 108:99]
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node _T_86 = and(update_dr, _T_85) @[rvjtag_tap.scala 108:82]
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node _T_87 = bits(sr, 17, 17) @[rvjtag_tap.scala 108:104]
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node _T_88 = mux(_T_86, _T_87, UInt<1>("h00")) @[rvjtag_tap.scala 108:71]
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reg _T_89 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 108:67]
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_T_89 <= _T_88 @[rvjtag_tap.scala 108:67]
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io.dmi_hard_reset <= _T_89 @[rvjtag_tap.scala 108:57]
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node _T_90 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 109:84]
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node _T_91 = bits(_T_90, 0, 0) @[rvjtag_tap.scala 109:94]
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node _T_92 = and(update_dr, _T_91) @[rvjtag_tap.scala 109:77]
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node _T_93 = bits(sr, 16, 16) @[rvjtag_tap.scala 109:99]
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node _T_94 = mux(_T_92, _T_93, UInt<1>("h00")) @[rvjtag_tap.scala 109:66]
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reg _T_95 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 109:62]
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_T_95 <= _T_94 @[rvjtag_tap.scala 109:62]
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io.dmi_reset <= _T_95 @[rvjtag_tap.scala 109:52]
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node _T_96 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 111:74]
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node _T_97 = bits(_T_96, 0, 0) @[rvjtag_tap.scala 111:84]
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node _T_98 = and(update_dr, _T_97) @[rvjtag_tap.scala 111:67]
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node _T_99 = bits(dr, 40, 2) @[rvjtag_tap.scala 111:96]
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node _T_100 = cat(_T_99, UInt<2>("h00")) @[Cat.scala 29:58]
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node _T_101 = mux(_T_98, sr, _T_100) @[rvjtag_tap.scala 111:56]
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reg _T_102 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 111:52]
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_T_102 <= _T_101 @[rvjtag_tap.scala 111:52]
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dr <= _T_102 @[rvjtag_tap.scala 111:42]
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node _T_103 = bits(dr, 0, 0) @[rvjtag_tap.scala 113:19]
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io.rd_en <= _T_103 @[rvjtag_tap.scala 113:14]
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node _T_104 = bits(dr, 1, 1) @[rvjtag_tap.scala 114:19]
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io.wr_en <= _T_104 @[rvjtag_tap.scala 114:14]
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node _T_105 = bits(dr, 33, 2) @[rvjtag_tap.scala 115:19]
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io.wr_data <= _T_105 @[rvjtag_tap.scala 115:14]
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node _T_106 = bits(dr, 40, 34) @[rvjtag_tap.scala 116:19]
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io.wr_addr <= _T_106 @[rvjtag_tap.scala 116:14]
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