31 lines
1.1 KiB
Verilog
31 lines
1.1 KiB
Verilog
module EL2_IC_TAG(
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input clock,
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input reset,
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input io_clk,
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input io_rst_l,
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input io_clk_override,
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input io_dec_tlu_core_ecc_disable,
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input [28:0] io_ic_rw_addr,
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input [1:0] io_ic_wr_en,
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input [1:0] io_ic_tag_valid,
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input io_ic_rd_en,
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input [8:0] io_ic_debug_addr,
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input io_ic_debug_rd_en,
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input io_ic_debug_wr_en,
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input io_ic_debug_tag_array,
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input [1:0] io_ic_debug_way,
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output [25:0] io_ictag_debug_rd_data,
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input [70:0] io_ic_debug_wr_data,
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output [1:0] io_ic_rd_hit,
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output io_ic_tag_perr,
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input io_scan_mode,
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output [1:0] io_test
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);
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wire _T_2 = io_ic_rw_addr[5:4] == 2'h1; // @[el2_ifu_ic_mem.scala 68:92]
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wire [1:0] _T_4 = {_T_2,_T_2}; // @[Cat.scala 29:58]
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assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 75:26]
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assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 74:16]
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assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 73:18]
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assign io_test = io_ic_wr_en & _T_4; // @[el2_ifu_ic_mem.scala 72:10]
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endmodule
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