24 lines
741 B
JSON
24 lines
741 B
JSON
[
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxInlineAnno",
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"target":"MakeInout.rvdff",
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"name":"rvdff.v",
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"text":"\nmodule InoutPort( input [15:0] in,\n input clk,\n input reset,\n output [15:0] out);\n always@(posedge clk or negedge reset)\n begin\n if(reset == 0)\n out <= 0;\n else\n out <= in\n end\nendmodule\n "
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"MakeInout"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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] |