305 lines
22 KiB
Plaintext
305 lines
22 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_lsu_addrcheck :
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module rvrangecheck :
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input clock : Clock
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input reset : Reset
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output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
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node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
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node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
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io.in_region <= _T_1 @[beh_lib.scala 113:19]
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node _T_2 = bits(io.addr, 31, 16) @[beh_lib.scala 117:30]
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node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[beh_lib.scala 117:45]
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io.in_range <= _T_3 @[beh_lib.scala 117:19]
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module rvrangecheck_1 :
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input clock : Clock
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input reset : Reset
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output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
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node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
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node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
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io.in_region <= _T_1 @[beh_lib.scala 113:19]
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node _T_2 = bits(io.addr, 31, 16) @[beh_lib.scala 117:30]
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node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[beh_lib.scala 117:45]
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io.in_range <= _T_3 @[beh_lib.scala 117:19]
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module rvrangecheck_2 :
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input clock : Clock
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input reset : Reset
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output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
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node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
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node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
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io.in_region <= _T_1 @[beh_lib.scala 113:19]
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node _T_2 = bits(io.addr, 31, 15) @[beh_lib.scala 117:30]
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node _T_3 = eq(_T_2, UInt<17>("h01e018")) @[beh_lib.scala 117:45]
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io.in_range <= _T_3 @[beh_lib.scala 117:19]
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module rvrangecheck_3 :
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input clock : Clock
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input reset : Reset
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output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
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node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
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node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
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io.in_region <= _T_1 @[beh_lib.scala 113:19]
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node _T_2 = bits(io.addr, 31, 15) @[beh_lib.scala 117:30]
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node _T_3 = eq(_T_2, UInt<17>("h01e018")) @[beh_lib.scala 117:45]
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io.in_range <= _T_3 @[beh_lib.scala 117:19]
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module el2_lsu_addrcheck :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
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wire start_addr_in_dccm_d : UInt<1>
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start_addr_in_dccm_d <= UInt<1>("h00")
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wire start_addr_in_dccm_region_d : UInt<1>
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start_addr_in_dccm_region_d <= UInt<1>("h00")
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wire end_addr_in_dccm_d : UInt<1>
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end_addr_in_dccm_d <= UInt<1>("h00")
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wire end_addr_in_dccm_region_d : UInt<1>
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end_addr_in_dccm_region_d <= UInt<1>("h00")
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inst rvrangecheck of rvrangecheck @[el2_lsu_addrcheck.scala 45:44]
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rvrangecheck.clock <= clock
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rvrangecheck.reset <= reset
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rvrangecheck.io.addr <= io.start_addr_d @[el2_lsu_addrcheck.scala 46:41]
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start_addr_in_dccm_d <= rvrangecheck.io.in_range @[el2_lsu_addrcheck.scala 47:41]
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start_addr_in_dccm_region_d <= rvrangecheck.io.in_region @[el2_lsu_addrcheck.scala 48:41]
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inst rvrangecheck_1 of rvrangecheck_1 @[el2_lsu_addrcheck.scala 51:44]
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rvrangecheck_1.clock <= clock
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rvrangecheck_1.reset <= reset
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rvrangecheck_1.io.addr <= io.end_addr_d @[el2_lsu_addrcheck.scala 52:41]
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end_addr_in_dccm_d <= rvrangecheck_1.io.in_range @[el2_lsu_addrcheck.scala 53:41]
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end_addr_in_dccm_region_d <= rvrangecheck_1.io.in_region @[el2_lsu_addrcheck.scala 54:41]
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wire addr_in_iccm : UInt<1>
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addr_in_iccm <= UInt<1>("h00")
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node _T = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 65:37]
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node _T_1 = eq(_T, UInt<4>("h0e")) @[el2_lsu_addrcheck.scala 65:45]
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addr_in_iccm <= _T_1 @[el2_lsu_addrcheck.scala 65:18]
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inst start_addr_pic_rangecheck of rvrangecheck_2 @[el2_lsu_addrcheck.scala 74:41]
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start_addr_pic_rangecheck.clock <= clock
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start_addr_pic_rangecheck.reset <= reset
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node _T_2 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 75:55]
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start_addr_pic_rangecheck.io.addr <= _T_2 @[el2_lsu_addrcheck.scala 75:37]
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inst end_addr_pic_rangecheck of rvrangecheck_3 @[el2_lsu_addrcheck.scala 80:39]
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end_addr_pic_rangecheck.clock <= clock
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end_addr_pic_rangecheck.reset <= reset
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node _T_3 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 81:51]
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end_addr_pic_rangecheck.io.addr <= _T_3 @[el2_lsu_addrcheck.scala 81:35]
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node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 85:60]
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node _T_4 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 86:48]
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node _T_5 = eq(_T_4, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 86:54]
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node _T_6 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 86:92]
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node _T_7 = eq(_T_6, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 86:98]
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node base_reg_dccm_or_pic = or(_T_5, _T_7) @[el2_lsu_addrcheck.scala 86:74]
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node _T_8 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 87:57]
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io.addr_in_dccm_d <= _T_8 @[el2_lsu_addrcheck.scala 87:32]
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node _T_9 = and(start_addr_pic_rangecheck.io.in_range, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 88:56]
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io.addr_in_pic_d <= _T_9 @[el2_lsu_addrcheck.scala 88:32]
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node _T_10 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 90:63]
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node _T_11 = not(_T_10) @[el2_lsu_addrcheck.scala 90:33]
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io.addr_external_d <= _T_11 @[el2_lsu_addrcheck.scala 90:30]
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node _T_12 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 91:51]
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node csr_idx = cat(_T_12, UInt<1>("h01")) @[Cat.scala 29:58]
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node _T_13 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[el2_lsu_addrcheck.scala 92:50]
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node _T_14 = bits(_T_13, 0, 0) @[el2_lsu_addrcheck.scala 92:50]
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node _T_15 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 92:92]
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node _T_16 = or(_T_15, addr_in_iccm) @[el2_lsu_addrcheck.scala 92:121]
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node _T_17 = not(_T_16) @[el2_lsu_addrcheck.scala 92:62]
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node _T_18 = and(_T_14, _T_17) @[el2_lsu_addrcheck.scala 92:60]
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node _T_19 = and(_T_18, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 92:137]
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node _T_20 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[el2_lsu_addrcheck.scala 92:180]
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node is_sideeffects_d = and(_T_19, _T_20) @[el2_lsu_addrcheck.scala 92:158]
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node _T_21 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 93:69]
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node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:75]
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node _T_23 = and(io.lsu_pkt_d.word, _T_22) @[el2_lsu_addrcheck.scala 93:51]
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node _T_24 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 93:124]
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node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:128]
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node _T_26 = and(io.lsu_pkt_d.half, _T_25) @[el2_lsu_addrcheck.scala 93:106]
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node _T_27 = or(_T_23, _T_26) @[el2_lsu_addrcheck.scala 93:85]
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node is_aligned_d = or(_T_27, io.lsu_pkt_d.by) @[el2_lsu_addrcheck.scala 93:138]
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node _T_28 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_29 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_30 = cat(_T_29, _T_28) @[Cat.scala 29:58]
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node _T_31 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
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node _T_32 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
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node _T_33 = cat(_T_32, _T_31) @[Cat.scala 29:58]
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node _T_34 = cat(_T_33, _T_30) @[Cat.scala 29:58]
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node _T_35 = orr(_T_34) @[el2_lsu_addrcheck.scala 97:99]
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node _T_36 = not(_T_35) @[el2_lsu_addrcheck.scala 96:33]
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node _T_37 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 98:50]
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node _T_38 = or(_T_37, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 98:57]
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node _T_39 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 98:108]
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node _T_40 = eq(_T_38, _T_39) @[el2_lsu_addrcheck.scala 98:82]
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node _T_41 = and(UInt<1>("h01"), _T_40) @[el2_lsu_addrcheck.scala 98:31]
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node _T_42 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 99:50]
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node _T_43 = or(_T_42, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 99:57]
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node _T_44 = or(UInt<32>("h0c0000000"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 99:108]
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node _T_45 = eq(_T_43, _T_44) @[el2_lsu_addrcheck.scala 99:82]
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node _T_46 = and(UInt<1>("h01"), _T_45) @[el2_lsu_addrcheck.scala 99:31]
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node _T_47 = or(_T_41, _T_46) @[el2_lsu_addrcheck.scala 98:133]
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node _T_48 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 100:50]
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node _T_49 = or(_T_48, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 100:57]
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node _T_50 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 100:108]
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node _T_51 = eq(_T_49, _T_50) @[el2_lsu_addrcheck.scala 100:82]
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node _T_52 = and(UInt<1>("h01"), _T_51) @[el2_lsu_addrcheck.scala 100:31]
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node _T_53 = or(_T_47, _T_52) @[el2_lsu_addrcheck.scala 99:133]
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node _T_54 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 101:50]
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node _T_55 = or(_T_54, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 101:57]
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node _T_56 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 101:108]
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node _T_57 = eq(_T_55, _T_56) @[el2_lsu_addrcheck.scala 101:82]
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node _T_58 = and(UInt<1>("h01"), _T_57) @[el2_lsu_addrcheck.scala 101:31]
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node _T_59 = or(_T_53, _T_58) @[el2_lsu_addrcheck.scala 100:133]
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node _T_60 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 102:50]
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node _T_61 = or(_T_60, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 102:57]
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node _T_62 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 102:108]
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node _T_63 = eq(_T_61, _T_62) @[el2_lsu_addrcheck.scala 102:82]
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node _T_64 = and(UInt<1>("h00"), _T_63) @[el2_lsu_addrcheck.scala 102:31]
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node _T_65 = or(_T_59, _T_64) @[el2_lsu_addrcheck.scala 101:133]
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node _T_66 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 103:50]
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node _T_67 = or(_T_66, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 103:57]
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node _T_68 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 103:108]
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node _T_69 = eq(_T_67, _T_68) @[el2_lsu_addrcheck.scala 103:82]
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node _T_70 = and(UInt<1>("h00"), _T_69) @[el2_lsu_addrcheck.scala 103:31]
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node _T_71 = or(_T_65, _T_70) @[el2_lsu_addrcheck.scala 102:133]
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node _T_72 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 104:50]
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node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 104:57]
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node _T_74 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 104:108]
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node _T_75 = eq(_T_73, _T_74) @[el2_lsu_addrcheck.scala 104:82]
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node _T_76 = and(UInt<1>("h00"), _T_75) @[el2_lsu_addrcheck.scala 104:31]
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node _T_77 = or(_T_71, _T_76) @[el2_lsu_addrcheck.scala 103:133]
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node _T_78 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 105:50]
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node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 105:57]
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node _T_80 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 105:108]
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node _T_81 = eq(_T_79, _T_80) @[el2_lsu_addrcheck.scala 105:82]
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node _T_82 = and(UInt<1>("h00"), _T_81) @[el2_lsu_addrcheck.scala 105:31]
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node _T_83 = or(_T_77, _T_82) @[el2_lsu_addrcheck.scala 104:133]
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node _T_84 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 107:49]
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node _T_85 = or(_T_84, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 107:58]
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node _T_86 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 107:109]
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node _T_87 = eq(_T_85, _T_86) @[el2_lsu_addrcheck.scala 107:83]
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node _T_88 = and(UInt<1>("h01"), _T_87) @[el2_lsu_addrcheck.scala 107:32]
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node _T_89 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 108:50]
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node _T_90 = or(_T_89, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 108:59]
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node _T_91 = or(UInt<32>("h0c0000000"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 108:110]
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node _T_92 = eq(_T_90, _T_91) @[el2_lsu_addrcheck.scala 108:84]
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node _T_93 = and(UInt<1>("h01"), _T_92) @[el2_lsu_addrcheck.scala 108:33]
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node _T_94 = or(_T_88, _T_93) @[el2_lsu_addrcheck.scala 107:134]
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node _T_95 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 109:50]
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node _T_96 = or(_T_95, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 109:59]
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node _T_97 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 109:110]
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node _T_98 = eq(_T_96, _T_97) @[el2_lsu_addrcheck.scala 109:84]
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node _T_99 = and(UInt<1>("h01"), _T_98) @[el2_lsu_addrcheck.scala 109:33]
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node _T_100 = or(_T_94, _T_99) @[el2_lsu_addrcheck.scala 108:135]
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node _T_101 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 110:50]
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node _T_102 = or(_T_101, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 110:59]
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node _T_103 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 110:110]
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node _T_104 = eq(_T_102, _T_103) @[el2_lsu_addrcheck.scala 110:84]
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node _T_105 = and(UInt<1>("h01"), _T_104) @[el2_lsu_addrcheck.scala 110:33]
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node _T_106 = or(_T_100, _T_105) @[el2_lsu_addrcheck.scala 109:135]
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node _T_107 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 111:50]
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node _T_108 = or(_T_107, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 111:59]
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node _T_109 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 111:110]
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node _T_110 = eq(_T_108, _T_109) @[el2_lsu_addrcheck.scala 111:84]
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node _T_111 = and(UInt<1>("h00"), _T_110) @[el2_lsu_addrcheck.scala 111:33]
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node _T_112 = or(_T_106, _T_111) @[el2_lsu_addrcheck.scala 110:135]
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node _T_113 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 112:50]
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node _T_114 = or(_T_113, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 112:59]
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node _T_115 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 112:110]
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node _T_116 = eq(_T_114, _T_115) @[el2_lsu_addrcheck.scala 112:84]
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node _T_117 = and(UInt<1>("h00"), _T_116) @[el2_lsu_addrcheck.scala 112:33]
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node _T_118 = or(_T_112, _T_117) @[el2_lsu_addrcheck.scala 111:135]
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node _T_119 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 113:50]
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node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 113:59]
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node _T_121 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 113:110]
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node _T_122 = eq(_T_120, _T_121) @[el2_lsu_addrcheck.scala 113:84]
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node _T_123 = and(UInt<1>("h00"), _T_122) @[el2_lsu_addrcheck.scala 113:33]
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node _T_124 = or(_T_118, _T_123) @[el2_lsu_addrcheck.scala 112:135]
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node _T_125 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 114:50]
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node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 114:59]
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node _T_127 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 114:110]
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node _T_128 = eq(_T_126, _T_127) @[el2_lsu_addrcheck.scala 114:84]
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node _T_129 = and(UInt<1>("h00"), _T_128) @[el2_lsu_addrcheck.scala 114:33]
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node _T_130 = or(_T_124, _T_129) @[el2_lsu_addrcheck.scala 113:135]
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node _T_131 = and(_T_83, _T_130) @[el2_lsu_addrcheck.scala 106:7]
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node non_dccm_access_ok = or(_T_36, _T_131) @[el2_lsu_addrcheck.scala 97:104]
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node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 116:57]
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node _T_132 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 117:70]
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node _T_133 = neq(_T_132, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 117:76]
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node _T_134 = not(io.lsu_pkt_d.word) @[el2_lsu_addrcheck.scala 117:92]
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node _T_135 = or(_T_133, _T_134) @[el2_lsu_addrcheck.scala 117:90]
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node picm_access_fault_d = and(io.addr_in_pic_d, _T_135) @[el2_lsu_addrcheck.scala 117:51]
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wire unmapped_access_fault_d : UInt<1>
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unmapped_access_fault_d <= UInt<1>("h01")
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wire mpu_access_fault_d : UInt<1>
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mpu_access_fault_d <= UInt<1>("h01")
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node _T_136 = or(start_addr_in_dccm_d, start_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 122:87]
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node _T_137 = not(_T_136) @[el2_lsu_addrcheck.scala 122:64]
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node _T_138 = and(start_addr_in_dccm_region_d, _T_137) @[el2_lsu_addrcheck.scala 122:62]
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node _T_139 = or(end_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 124:57]
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node _T_140 = not(_T_139) @[el2_lsu_addrcheck.scala 124:36]
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node _T_141 = and(end_addr_in_dccm_region_d, _T_140) @[el2_lsu_addrcheck.scala 124:34]
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node _T_142 = or(_T_138, _T_141) @[el2_lsu_addrcheck.scala 122:112]
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node _T_143 = and(start_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 126:29]
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node _T_144 = or(_T_142, _T_143) @[el2_lsu_addrcheck.scala 124:85]
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node _T_145 = and(start_addr_pic_rangecheck.io.in_range, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 128:29]
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node _T_146 = or(_T_144, _T_145) @[el2_lsu_addrcheck.scala 126:85]
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unmapped_access_fault_d <= _T_146 @[el2_lsu_addrcheck.scala 122:29]
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node _T_147 = not(start_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 130:33]
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node _T_148 = not(non_dccm_access_ok) @[el2_lsu_addrcheck.scala 130:64]
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node _T_149 = and(_T_147, _T_148) @[el2_lsu_addrcheck.scala 130:62]
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mpu_access_fault_d <= _T_149 @[el2_lsu_addrcheck.scala 130:29]
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node _T_150 = or(unmapped_access_fault_d, mpu_access_fault_d) @[el2_lsu_addrcheck.scala 142:49]
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node _T_151 = or(_T_150, picm_access_fault_d) @[el2_lsu_addrcheck.scala 142:70]
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node _T_152 = or(_T_151, regpred_access_fault_d) @[el2_lsu_addrcheck.scala 142:92]
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node _T_153 = and(_T_152, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 142:118]
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node _T_154 = not(io.lsu_pkt_d.dma) @[el2_lsu_addrcheck.scala 142:141]
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node _T_155 = and(_T_153, _T_154) @[el2_lsu_addrcheck.scala 142:139]
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io.access_fault_d <= _T_155 @[el2_lsu_addrcheck.scala 142:21]
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node _T_156 = bits(unmapped_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:60]
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node _T_157 = bits(mpu_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:100]
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node _T_158 = bits(regpred_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:144]
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node _T_159 = bits(picm_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:185]
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node _T_160 = mux(_T_159, UInt<4>("h06"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 143:164]
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node _T_161 = mux(_T_158, UInt<4>("h05"), _T_160) @[el2_lsu_addrcheck.scala 143:120]
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node _T_162 = mux(_T_157, UInt<4>("h03"), _T_161) @[el2_lsu_addrcheck.scala 143:80]
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node access_fault_mscause_d = mux(_T_156, UInt<4>("h02"), _T_162) @[el2_lsu_addrcheck.scala 143:35]
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node _T_163 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 144:53]
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node _T_164 = bits(io.end_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 144:78]
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node regcross_misaligned_fault_d = neq(_T_163, _T_164) @[el2_lsu_addrcheck.scala 144:61]
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node _T_165 = not(is_aligned_d) @[el2_lsu_addrcheck.scala 145:59]
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node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_165) @[el2_lsu_addrcheck.scala 145:57]
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node _T_166 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[el2_lsu_addrcheck.scala 146:90]
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node _T_167 = or(regcross_misaligned_fault_d, _T_166) @[el2_lsu_addrcheck.scala 146:57]
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node _T_168 = and(_T_167, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 146:113]
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node _T_169 = not(io.lsu_pkt_d.dma) @[el2_lsu_addrcheck.scala 146:136]
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node _T_170 = and(_T_168, _T_169) @[el2_lsu_addrcheck.scala 146:134]
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io.misaligned_fault_d <= _T_170 @[el2_lsu_addrcheck.scala 146:25]
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node _T_171 = bits(sideeffect_misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 147:111]
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node _T_172 = mux(_T_171, UInt<4>("h01"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 147:80]
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node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_172) @[el2_lsu_addrcheck.scala 147:39]
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node _T_173 = bits(io.misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 148:50]
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node _T_174 = bits(misaligned_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 148:84]
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node _T_175 = bits(access_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 148:113]
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node _T_176 = mux(_T_173, _T_174, _T_175) @[el2_lsu_addrcheck.scala 148:27]
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io.exc_mscause_d <= _T_176 @[el2_lsu_addrcheck.scala 148:21]
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node _T_177 = not(start_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 149:66]
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node _T_178 = and(start_addr_in_dccm_region_d, _T_177) @[el2_lsu_addrcheck.scala 149:64]
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node _T_179 = not(end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 149:120]
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node _T_180 = and(end_addr_in_dccm_region_d, _T_179) @[el2_lsu_addrcheck.scala 149:118]
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node _T_181 = or(_T_178, _T_180) @[el2_lsu_addrcheck.scala 149:88]
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node _T_182 = and(_T_181, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 149:142]
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node _T_183 = and(_T_182, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 149:163]
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io.fir_dccm_access_error_d <= _T_183 @[el2_lsu_addrcheck.scala 149:31]
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node _T_184 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 150:66]
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node _T_185 = not(_T_184) @[el2_lsu_addrcheck.scala 150:36]
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node _T_186 = and(_T_185, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 150:95]
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node _T_187 = and(_T_186, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 150:116]
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io.fir_nondccm_access_error_d <= _T_187 @[el2_lsu_addrcheck.scala 150:33]
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reg _T_188 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 152:60]
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_T_188 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 152:60]
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io.is_sideeffects_m <= _T_188 @[el2_lsu_addrcheck.scala 152:50]
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